rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_1 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}} node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31) node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23) node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0) node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0) node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1) node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2) node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3) node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4) node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5) node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6) node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7) node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8) node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9) node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10) node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11) node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12) node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13) node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14) node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15) node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16) node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17) node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18) node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19) node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20) node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21) node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22) node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23) node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24) node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25) node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26) node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27) node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28) node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29) node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30) node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31) node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32) node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33) node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34) node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35) node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36) node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37) node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38) node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39) node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40) node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41) node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42) node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43) node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist) node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn) node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2) node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3) node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn) node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T) connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1 node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn) connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T) connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1 node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T) node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn) node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2) connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3 node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6) node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T) node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2) node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3) node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0) node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5) node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0) node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7) node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31) node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23) node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0) node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0) node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1) node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2) node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3) node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4) node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5) node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6) node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7) node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8) node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9) node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10) node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11) node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12) node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13) node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14) node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15) node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16) node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17) node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18) node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19) node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20) node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21) node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22) node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23) node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24) node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25) node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26) node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27) node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28) node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29) node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30) node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31) node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32) node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33) node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34) node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35) node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36) node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37) node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38) node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39) node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40) node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41) node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42) node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43) node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist) node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn) node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2) node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3) node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn) node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T) connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1 node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn) connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T) connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1 node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T) node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn) node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2) connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3 node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6) node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T) node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2) node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3) node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0) node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5) node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0) node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7) node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31) node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23) node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0) node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0) node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1) node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2) node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3) node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4) node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5) node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6) node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7) node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8) node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9) node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10) node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11) node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12) node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13) node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14) node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15) node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16) node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17) node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18) node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19) node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20) node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21) node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22) node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23) node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24) node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25) node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26) node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27) node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28) node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29) node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30) node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31) node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32) node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33) node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34) node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35) node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36) node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37) node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38) node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39) node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40) node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41) node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42) node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43) node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist) node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn) node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2) node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3) node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn) node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7) node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T) connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1 node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn) connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T) connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1 node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T) node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn) node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2) connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3 node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6) node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T) node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2) node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3) node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0) node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5) node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0) node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7) inst io_out_d_m1_resizer of RecFNToRecFN_150 connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_m2_resizer of RecFNToRecFN_151 connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_muladder of MulAddRecFN_e8_s24_65 connect io_out_d_muladder.io.op, UInt<1>(0h0) connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out connect io_out_d_muladder.io.c, io_out_d_self_rec wire io_out_d_out : { bits : UInt<32>} node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23) node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6) node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7) node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T) connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1 node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1) connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2 connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32) connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp) connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T) node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0) node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2) connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3 node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0) node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T) node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1) node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1) node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist) node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0) node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0) node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81)) node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1) node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2) node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf) node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5) node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0) node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T) node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1) node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut) node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut) connect io_out_d_out.bits, _io_out_d_out_bits_T connect io.out_d, io_out_d_out	module MacUnit_1( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [31:0] io_in_a_bits, // @[PE.scala:16:14] input [31:0] io_in_b_bits, // @[PE.scala:16:14] input [31:0] io_in_c_bits, // @[PE.scala:16:14] output [31:0] io_out_d_bits // @[PE.scala:16:14] ); wire io_out_d_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _io_out_d_muladder_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _io_out_d_m2_resizer_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _io_out_d_m1_resizer_io_out; // @[Arithmetic.scala:362:32] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:14:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:14:7] wire [31:0] io_in_c_bits_0 = io_in_c_bits; // @[PE.scala:14:7] wire [31:0] io_out_d_out_bits; // @[Arithmetic.scala:387:23] wire [31:0] io_out_d_bits_0; // @[PE.scala:14:7] wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] \| _io_out_d_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] \| _io_out_d_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] \| _io_out_d_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] assign io_out_d_bits_0 = io_out_d_out_bits; // @[PE.scala:14:7] wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_d_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_d_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_d_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN \| io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 \| _io_out_d_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_d_out_bits = _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] RecFNToRecFN_150 io_out_d_m1_resizer ( // @[Arithmetic.scala:362:32] .io_in (io_out_d_m1_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m1_resizer_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_151 io_out_d_m2_resizer ( // @[Arithmetic.scala:369:32] .io_in (io_out_d_m2_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m2_resizer_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_65 io_out_d_muladder ( // @[Arithmetic.scala:376:30] .io_a (_io_out_d_m1_resizer_io_out), // @[Arithmetic.scala:362:32] .io_b (_io_out_d_m2_resizer_io_out), // @[Arithmetic.scala:369:32] .io_c (io_out_d_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_muladder_io_out) ); // @[Arithmetic.scala:376:30] assign io_out_d_bits = io_out_d_bits_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_14 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `1` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `0` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8]}} regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire in_arb_reqs : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}[3] wire in_arb_vals : UInt<1>[3] node in_arb_filter_hi = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_vals[0]) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = mux(_in_arb_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _in_arb_filter_T_12 = mux(_in_arb_filter_T_9, UInt<6>(0h10), _in_arb_filter_T_11) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_8, UInt<6>(0h8), _in_arb_filter_T_12) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_7, UInt<6>(0h4), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_6, UInt<6>(0h2), _in_arb_filter_T_14) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<6>(0h1), _in_arb_filter_T_15) node _in_arb_sel_T = bits(in_arb_filter, 2, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 3) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) when _T_1 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = bits(in_arb_sel, 0, 0) node _mask_T_4 = bits(in_arb_sel, 1, 1) node _mask_T_5 = bits(in_arb_sel, 2, 2) node _mask_T_6 = mux(_mask_T_3, _mask_T, UInt<1>(0h0)) node _mask_T_7 = mux(_mask_T_4, _mask_T_1, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_5, _mask_T_2, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_6, _mask_T_7) node _mask_T_10 = or(_mask_T_9, _mask_T_8) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_10 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T) connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1 node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T) connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1 node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T) connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1 node _in_arb_reqs_0_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_5_T_1 = and(io.req.`0`.bits.vc_sel.`0`[5], _in_arb_reqs_0_0_5_T) connect in_arb_reqs[0].`0`[5], _in_arb_reqs_0_0_5_T_1 node _in_arb_reqs_0_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_6_T_1 = and(io.req.`0`.bits.vc_sel.`0`[6], _in_arb_reqs_0_0_6_T) connect in_arb_reqs[0].`0`[6], _in_arb_reqs_0_0_6_T_1 node _in_arb_reqs_0_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_7_T_1 = and(io.req.`0`.bits.vc_sel.`0`[7], _in_arb_reqs_0_0_7_T) connect in_arb_reqs[0].`0`[7], _in_arb_reqs_0_0_7_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T) connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1 node _in_arb_reqs_0_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_2_T_1 = and(io.req.`0`.bits.vc_sel.`1`[2], _in_arb_reqs_0_1_2_T) connect in_arb_reqs[0].`1`[2], _in_arb_reqs_0_1_2_T_1 node _in_arb_reqs_0_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_3_T_1 = and(io.req.`0`.bits.vc_sel.`1`[3], _in_arb_reqs_0_1_3_T) connect in_arb_reqs[0].`1`[3], _in_arb_reqs_0_1_3_T_1 node _in_arb_reqs_0_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_4_T_1 = and(io.req.`0`.bits.vc_sel.`1`[4], _in_arb_reqs_0_1_4_T) connect in_arb_reqs[0].`1`[4], _in_arb_reqs_0_1_4_T_1 node _in_arb_reqs_0_1_5_T = eq(io.channel_status.`1`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_5_T_1 = and(io.req.`0`.bits.vc_sel.`1`[5], _in_arb_reqs_0_1_5_T) connect in_arb_reqs[0].`1`[5], _in_arb_reqs_0_1_5_T_1 node _in_arb_reqs_0_1_6_T = eq(io.channel_status.`1`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_6_T_1 = and(io.req.`0`.bits.vc_sel.`1`[6], _in_arb_reqs_0_1_6_T) connect in_arb_reqs[0].`1`[6], _in_arb_reqs_0_1_6_T_1 node _in_arb_reqs_0_1_7_T = eq(io.channel_status.`1`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_7_T_1 = and(io.req.`0`.bits.vc_sel.`1`[7], _in_arb_reqs_0_1_7_T) connect in_arb_reqs[0].`1`[7], _in_arb_reqs_0_1_7_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_reqs_0_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_1_T_1 = and(io.req.`0`.bits.vc_sel.`2`[1], _in_arb_reqs_0_2_1_T) connect in_arb_reqs[0].`2`[1], _in_arb_reqs_0_2_1_T_1 node _in_arb_reqs_0_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_2_T_1 = and(io.req.`0`.bits.vc_sel.`2`[2], _in_arb_reqs_0_2_2_T) connect in_arb_reqs[0].`2`[2], _in_arb_reqs_0_2_2_T_1 node _in_arb_reqs_0_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_3_T_1 = and(io.req.`0`.bits.vc_sel.`2`[3], _in_arb_reqs_0_2_3_T) connect in_arb_reqs[0].`2`[3], _in_arb_reqs_0_2_3_T_1 node _in_arb_reqs_0_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_4_T_1 = and(io.req.`0`.bits.vc_sel.`2`[4], _in_arb_reqs_0_2_4_T) connect in_arb_reqs[0].`2`[4], _in_arb_reqs_0_2_4_T_1 node _in_arb_reqs_0_2_5_T = eq(io.channel_status.`2`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_5_T_1 = and(io.req.`0`.bits.vc_sel.`2`[5], _in_arb_reqs_0_2_5_T) connect in_arb_reqs[0].`2`[5], _in_arb_reqs_0_2_5_T_1 node _in_arb_reqs_0_2_6_T = eq(io.channel_status.`2`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_6_T_1 = and(io.req.`0`.bits.vc_sel.`2`[6], _in_arb_reqs_0_2_6_T) connect in_arb_reqs[0].`2`[6], _in_arb_reqs_0_2_6_T_1 node _in_arb_reqs_0_2_7_T = eq(io.channel_status.`2`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_7_T_1 = and(io.req.`0`.bits.vc_sel.`2`[7], _in_arb_reqs_0_2_7_T) connect in_arb_reqs[0].`2`[7], _in_arb_reqs_0_2_7_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3]) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4]) node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`0`[5]) node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`0`[6]) node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`0`[7]) node _in_arb_vals_0_T_7 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1]) node _in_arb_vals_0_T_8 = or(_in_arb_vals_0_T_7, in_arb_reqs[0].`1`[2]) node _in_arb_vals_0_T_9 = or(_in_arb_vals_0_T_8, in_arb_reqs[0].`1`[3]) node _in_arb_vals_0_T_10 = or(_in_arb_vals_0_T_9, in_arb_reqs[0].`1`[4]) node _in_arb_vals_0_T_11 = or(_in_arb_vals_0_T_10, in_arb_reqs[0].`1`[5]) node _in_arb_vals_0_T_12 = or(_in_arb_vals_0_T_11, in_arb_reqs[0].`1`[6]) node _in_arb_vals_0_T_13 = or(_in_arb_vals_0_T_12, in_arb_reqs[0].`1`[7]) node _in_arb_vals_0_T_14 = or(in_arb_reqs[0].`2`[0], in_arb_reqs[0].`2`[1]) node _in_arb_vals_0_T_15 = or(_in_arb_vals_0_T_14, in_arb_reqs[0].`2`[2]) node _in_arb_vals_0_T_16 = or(_in_arb_vals_0_T_15, in_arb_reqs[0].`2`[3]) node _in_arb_vals_0_T_17 = or(_in_arb_vals_0_T_16, in_arb_reqs[0].`2`[4]) node _in_arb_vals_0_T_18 = or(_in_arb_vals_0_T_17, in_arb_reqs[0].`2`[5]) node _in_arb_vals_0_T_19 = or(_in_arb_vals_0_T_18, in_arb_reqs[0].`2`[6]) node _in_arb_vals_0_T_20 = or(_in_arb_vals_0_T_19, in_arb_reqs[0].`2`[7]) node _in_arb_vals_0_T_21 = or(_in_arb_vals_0_T_6, _in_arb_vals_0_T_13) node _in_arb_vals_0_T_22 = or(_in_arb_vals_0_T_21, _in_arb_vals_0_T_20) node _in_arb_vals_0_T_23 = and(io.req.`0`.valid, _in_arb_vals_0_T_22) connect in_arb_vals[0], _in_arb_vals_0_T_23 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T) connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1 node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T) connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1 node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T) connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1 node _in_arb_reqs_1_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_5_T_1 = and(io.req.`1`.bits.vc_sel.`0`[5], _in_arb_reqs_1_0_5_T) connect in_arb_reqs[1].`0`[5], _in_arb_reqs_1_0_5_T_1 node _in_arb_reqs_1_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_6_T_1 = and(io.req.`1`.bits.vc_sel.`0`[6], _in_arb_reqs_1_0_6_T) connect in_arb_reqs[1].`0`[6], _in_arb_reqs_1_0_6_T_1 node _in_arb_reqs_1_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_7_T_1 = and(io.req.`1`.bits.vc_sel.`0`[7], _in_arb_reqs_1_0_7_T) connect in_arb_reqs[1].`0`[7], _in_arb_reqs_1_0_7_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T) connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1 node _in_arb_reqs_1_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_2_T_1 = and(io.req.`1`.bits.vc_sel.`1`[2], _in_arb_reqs_1_1_2_T) connect in_arb_reqs[1].`1`[2], _in_arb_reqs_1_1_2_T_1 node _in_arb_reqs_1_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_3_T_1 = and(io.req.`1`.bits.vc_sel.`1`[3], _in_arb_reqs_1_1_3_T) connect in_arb_reqs[1].`1`[3], _in_arb_reqs_1_1_3_T_1 node _in_arb_reqs_1_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_4_T_1 = and(io.req.`1`.bits.vc_sel.`1`[4], _in_arb_reqs_1_1_4_T) connect in_arb_reqs[1].`1`[4], _in_arb_reqs_1_1_4_T_1 node _in_arb_reqs_1_1_5_T = eq(io.channel_status.`1`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_5_T_1 = and(io.req.`1`.bits.vc_sel.`1`[5], _in_arb_reqs_1_1_5_T) connect in_arb_reqs[1].`1`[5], _in_arb_reqs_1_1_5_T_1 node _in_arb_reqs_1_1_6_T = eq(io.channel_status.`1`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_6_T_1 = and(io.req.`1`.bits.vc_sel.`1`[6], _in_arb_reqs_1_1_6_T) connect in_arb_reqs[1].`1`[6], _in_arb_reqs_1_1_6_T_1 node _in_arb_reqs_1_1_7_T = eq(io.channel_status.`1`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_7_T_1 = and(io.req.`1`.bits.vc_sel.`1`[7], _in_arb_reqs_1_1_7_T) connect in_arb_reqs[1].`1`[7], _in_arb_reqs_1_1_7_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_reqs_1_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_1_T_1 = and(io.req.`1`.bits.vc_sel.`2`[1], _in_arb_reqs_1_2_1_T) connect in_arb_reqs[1].`2`[1], _in_arb_reqs_1_2_1_T_1 node _in_arb_reqs_1_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_2_T_1 = and(io.req.`1`.bits.vc_sel.`2`[2], _in_arb_reqs_1_2_2_T) connect in_arb_reqs[1].`2`[2], _in_arb_reqs_1_2_2_T_1 node _in_arb_reqs_1_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_3_T_1 = and(io.req.`1`.bits.vc_sel.`2`[3], _in_arb_reqs_1_2_3_T) connect in_arb_reqs[1].`2`[3], _in_arb_reqs_1_2_3_T_1 node _in_arb_reqs_1_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_4_T_1 = and(io.req.`1`.bits.vc_sel.`2`[4], _in_arb_reqs_1_2_4_T) connect in_arb_reqs[1].`2`[4], _in_arb_reqs_1_2_4_T_1 node _in_arb_reqs_1_2_5_T = eq(io.channel_status.`2`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_5_T_1 = and(io.req.`1`.bits.vc_sel.`2`[5], _in_arb_reqs_1_2_5_T) connect in_arb_reqs[1].`2`[5], _in_arb_reqs_1_2_5_T_1 node _in_arb_reqs_1_2_6_T = eq(io.channel_status.`2`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_6_T_1 = and(io.req.`1`.bits.vc_sel.`2`[6], _in_arb_reqs_1_2_6_T) connect in_arb_reqs[1].`2`[6], _in_arb_reqs_1_2_6_T_1 node _in_arb_reqs_1_2_7_T = eq(io.channel_status.`2`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_7_T_1 = and(io.req.`1`.bits.vc_sel.`2`[7], _in_arb_reqs_1_2_7_T) connect in_arb_reqs[1].`2`[7], _in_arb_reqs_1_2_7_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3]) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4]) node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`0`[5]) node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`0`[6]) node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`0`[7]) node _in_arb_vals_1_T_7 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1]) node _in_arb_vals_1_T_8 = or(_in_arb_vals_1_T_7, in_arb_reqs[1].`1`[2]) node _in_arb_vals_1_T_9 = or(_in_arb_vals_1_T_8, in_arb_reqs[1].`1`[3]) node _in_arb_vals_1_T_10 = or(_in_arb_vals_1_T_9, in_arb_reqs[1].`1`[4]) node _in_arb_vals_1_T_11 = or(_in_arb_vals_1_T_10, in_arb_reqs[1].`1`[5]) node _in_arb_vals_1_T_12 = or(_in_arb_vals_1_T_11, in_arb_reqs[1].`1`[6]) node _in_arb_vals_1_T_13 = or(_in_arb_vals_1_T_12, in_arb_reqs[1].`1`[7]) node _in_arb_vals_1_T_14 = or(in_arb_reqs[1].`2`[0], in_arb_reqs[1].`2`[1]) node _in_arb_vals_1_T_15 = or(_in_arb_vals_1_T_14, in_arb_reqs[1].`2`[2]) node _in_arb_vals_1_T_16 = or(_in_arb_vals_1_T_15, in_arb_reqs[1].`2`[3]) node _in_arb_vals_1_T_17 = or(_in_arb_vals_1_T_16, in_arb_reqs[1].`2`[4]) node _in_arb_vals_1_T_18 = or(_in_arb_vals_1_T_17, in_arb_reqs[1].`2`[5]) node _in_arb_vals_1_T_19 = or(_in_arb_vals_1_T_18, in_arb_reqs[1].`2`[6]) node _in_arb_vals_1_T_20 = or(_in_arb_vals_1_T_19, in_arb_reqs[1].`2`[7]) node _in_arb_vals_1_T_21 = or(_in_arb_vals_1_T_6, _in_arb_vals_1_T_13) node _in_arb_vals_1_T_22 = or(_in_arb_vals_1_T_21, _in_arb_vals_1_T_20) node _in_arb_vals_1_T_23 = and(io.req.`1`.valid, _in_arb_vals_1_T_22) connect in_arb_vals[1], _in_arb_vals_1_T_23 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T) connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1 node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T) connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1 node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T) connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1 node _in_arb_reqs_2_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_5_T_1 = and(io.req.`2`.bits.vc_sel.`0`[5], _in_arb_reqs_2_0_5_T) connect in_arb_reqs[2].`0`[5], _in_arb_reqs_2_0_5_T_1 node _in_arb_reqs_2_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_6_T_1 = and(io.req.`2`.bits.vc_sel.`0`[6], _in_arb_reqs_2_0_6_T) connect in_arb_reqs[2].`0`[6], _in_arb_reqs_2_0_6_T_1 node _in_arb_reqs_2_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_7_T_1 = and(io.req.`2`.bits.vc_sel.`0`[7], _in_arb_reqs_2_0_7_T) connect in_arb_reqs[2].`0`[7], _in_arb_reqs_2_0_7_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T) connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1 node _in_arb_reqs_2_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_2_T_1 = and(io.req.`2`.bits.vc_sel.`1`[2], _in_arb_reqs_2_1_2_T) connect in_arb_reqs[2].`1`[2], _in_arb_reqs_2_1_2_T_1 node _in_arb_reqs_2_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_3_T_1 = and(io.req.`2`.bits.vc_sel.`1`[3], _in_arb_reqs_2_1_3_T) connect in_arb_reqs[2].`1`[3], _in_arb_reqs_2_1_3_T_1 node _in_arb_reqs_2_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_4_T_1 = and(io.req.`2`.bits.vc_sel.`1`[4], _in_arb_reqs_2_1_4_T) connect in_arb_reqs[2].`1`[4], _in_arb_reqs_2_1_4_T_1 node _in_arb_reqs_2_1_5_T = eq(io.channel_status.`1`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_5_T_1 = and(io.req.`2`.bits.vc_sel.`1`[5], _in_arb_reqs_2_1_5_T) connect in_arb_reqs[2].`1`[5], _in_arb_reqs_2_1_5_T_1 node _in_arb_reqs_2_1_6_T = eq(io.channel_status.`1`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_6_T_1 = and(io.req.`2`.bits.vc_sel.`1`[6], _in_arb_reqs_2_1_6_T) connect in_arb_reqs[2].`1`[6], _in_arb_reqs_2_1_6_T_1 node _in_arb_reqs_2_1_7_T = eq(io.channel_status.`1`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_7_T_1 = and(io.req.`2`.bits.vc_sel.`1`[7], _in_arb_reqs_2_1_7_T) connect in_arb_reqs[2].`1`[7], _in_arb_reqs_2_1_7_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_reqs_2_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_1_T_1 = and(io.req.`2`.bits.vc_sel.`2`[1], _in_arb_reqs_2_2_1_T) connect in_arb_reqs[2].`2`[1], _in_arb_reqs_2_2_1_T_1 node _in_arb_reqs_2_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_2_T_1 = and(io.req.`2`.bits.vc_sel.`2`[2], _in_arb_reqs_2_2_2_T) connect in_arb_reqs[2].`2`[2], _in_arb_reqs_2_2_2_T_1 node _in_arb_reqs_2_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_3_T_1 = and(io.req.`2`.bits.vc_sel.`2`[3], _in_arb_reqs_2_2_3_T) connect in_arb_reqs[2].`2`[3], _in_arb_reqs_2_2_3_T_1 node _in_arb_reqs_2_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_4_T_1 = and(io.req.`2`.bits.vc_sel.`2`[4], _in_arb_reqs_2_2_4_T) connect in_arb_reqs[2].`2`[4], _in_arb_reqs_2_2_4_T_1 node _in_arb_reqs_2_2_5_T = eq(io.channel_status.`2`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_5_T_1 = and(io.req.`2`.bits.vc_sel.`2`[5], _in_arb_reqs_2_2_5_T) connect in_arb_reqs[2].`2`[5], _in_arb_reqs_2_2_5_T_1 node _in_arb_reqs_2_2_6_T = eq(io.channel_status.`2`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_6_T_1 = and(io.req.`2`.bits.vc_sel.`2`[6], _in_arb_reqs_2_2_6_T) connect in_arb_reqs[2].`2`[6], _in_arb_reqs_2_2_6_T_1 node _in_arb_reqs_2_2_7_T = eq(io.channel_status.`2`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_7_T_1 = and(io.req.`2`.bits.vc_sel.`2`[7], _in_arb_reqs_2_2_7_T) connect in_arb_reqs[2].`2`[7], _in_arb_reqs_2_2_7_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3]) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4]) node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`0`[5]) node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`0`[6]) node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`0`[7]) node _in_arb_vals_2_T_7 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1]) node _in_arb_vals_2_T_8 = or(_in_arb_vals_2_T_7, in_arb_reqs[2].`1`[2]) node _in_arb_vals_2_T_9 = or(_in_arb_vals_2_T_8, in_arb_reqs[2].`1`[3]) node _in_arb_vals_2_T_10 = or(_in_arb_vals_2_T_9, in_arb_reqs[2].`1`[4]) node _in_arb_vals_2_T_11 = or(_in_arb_vals_2_T_10, in_arb_reqs[2].`1`[5]) node _in_arb_vals_2_T_12 = or(_in_arb_vals_2_T_11, in_arb_reqs[2].`1`[6]) node _in_arb_vals_2_T_13 = or(_in_arb_vals_2_T_12, in_arb_reqs[2].`1`[7]) node _in_arb_vals_2_T_14 = or(in_arb_reqs[2].`2`[0], in_arb_reqs[2].`2`[1]) node _in_arb_vals_2_T_15 = or(_in_arb_vals_2_T_14, in_arb_reqs[2].`2`[2]) node _in_arb_vals_2_T_16 = or(_in_arb_vals_2_T_15, in_arb_reqs[2].`2`[3]) node _in_arb_vals_2_T_17 = or(_in_arb_vals_2_T_16, in_arb_reqs[2].`2`[4]) node _in_arb_vals_2_T_18 = or(_in_arb_vals_2_T_17, in_arb_reqs[2].`2`[5]) node _in_arb_vals_2_T_19 = or(_in_arb_vals_2_T_18, in_arb_reqs[2].`2`[6]) node _in_arb_vals_2_T_20 = or(_in_arb_vals_2_T_19, in_arb_reqs[2].`2`[7]) node _in_arb_vals_2_T_21 = or(_in_arb_vals_2_T_6, _in_arb_vals_2_T_13) node _in_arb_vals_2_T_22 = or(_in_arb_vals_2_T_21, _in_arb_vals_2_T_20) node _in_arb_vals_2_T_23 = and(io.req.`2`.valid, _in_arb_vals_2_T_22) connect in_arb_vals[2], _in_arb_vals_2_T_23 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) wire in_alloc : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _in_flow_T_3 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_4 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = or(_in_flow_T_3, _in_flow_T_4) node _in_flow_T_7 = or(_in_flow_T_6, _in_flow_T_5) wire _in_flow_WIRE : UInt<2> connect _in_flow_WIRE, _in_flow_T_7 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_8 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_9 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_10 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_11 = or(_in_flow_T_8, _in_flow_T_9) node _in_flow_T_12 = or(_in_flow_T_11, _in_flow_T_10) wire _in_flow_WIRE_1 : UInt<5> connect _in_flow_WIRE_1, _in_flow_T_12 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_13 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_15 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_16 = or(_in_flow_T_13, _in_flow_T_14) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_15) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_17 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_21 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_22 = or(_in_flow_T_21, _in_flow_T_20) wire _in_flow_WIRE_3 : UInt<5> connect _in_flow_WIRE_3, _in_flow_T_22 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_23 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_24 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_25 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_26 = or(_in_flow_T_23, _in_flow_T_24) node _in_flow_T_27 = or(_in_flow_T_26, _in_flow_T_25) wire _in_flow_WIRE_4 : UInt<3> connect _in_flow_WIRE_4, _in_flow_T_27 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_4 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = or(_in_vc_T_3, _in_vc_T_4) node _in_vc_T_7 = or(_in_vc_T_6, _in_vc_T_5) wire in_vc : UInt<3> connect in_vc, _in_vc_T_7 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) wire in_vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _in_vc_sel_WIRE : UInt<1>[8] node _in_vc_sel_T_3 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_4 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = or(_in_vc_sel_T_3, _in_vc_sel_T_4) node _in_vc_sel_T_7 = or(_in_vc_sel_T_6, _in_vc_sel_T_5) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_7 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_8 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_9 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_10 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_11 = or(_in_vc_sel_T_8, _in_vc_sel_T_9) node _in_vc_sel_T_12 = or(_in_vc_sel_T_11, _in_vc_sel_T_10) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_12 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 node _in_vc_sel_T_13 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_15 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_16 = or(_in_vc_sel_T_13, _in_vc_sel_T_14) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_15) wire _in_vc_sel_WIRE_3 : UInt<1> connect _in_vc_sel_WIRE_3, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3 node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_21 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_22 = or(_in_vc_sel_T_21, _in_vc_sel_T_20) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_22 connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4 node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_25 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_26 = or(_in_vc_sel_T_23, _in_vc_sel_T_24) node _in_vc_sel_T_27 = or(_in_vc_sel_T_26, _in_vc_sel_T_25) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_27 connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5 node _in_vc_sel_T_28 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_29 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_30 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_31 = or(_in_vc_sel_T_28, _in_vc_sel_T_29) node _in_vc_sel_T_32 = or(_in_vc_sel_T_31, _in_vc_sel_T_30) wire _in_vc_sel_WIRE_6 : UInt<1> connect _in_vc_sel_WIRE_6, _in_vc_sel_T_32 connect _in_vc_sel_WIRE[5], _in_vc_sel_WIRE_6 node _in_vc_sel_T_33 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_33, _in_vc_sel_T_34) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_37 connect _in_vc_sel_WIRE[6], _in_vc_sel_WIRE_7 node _in_vc_sel_T_38 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_39 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_40 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_41 = or(_in_vc_sel_T_38, _in_vc_sel_T_39) node _in_vc_sel_T_42 = or(_in_vc_sel_T_41, _in_vc_sel_T_40) wire _in_vc_sel_WIRE_8 : UInt<1> connect _in_vc_sel_WIRE_8, _in_vc_sel_T_42 connect _in_vc_sel_WIRE[7], _in_vc_sel_WIRE_8 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_9 : UInt<1>[8] node _in_vc_sel_T_43 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_44 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_45 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_46 = or(_in_vc_sel_T_43, _in_vc_sel_T_44) node _in_vc_sel_T_47 = or(_in_vc_sel_T_46, _in_vc_sel_T_45) wire _in_vc_sel_WIRE_10 : UInt<1> connect _in_vc_sel_WIRE_10, _in_vc_sel_T_47 connect _in_vc_sel_WIRE_9[0], _in_vc_sel_WIRE_10 node _in_vc_sel_T_48 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_49 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_50 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_51 = or(_in_vc_sel_T_48, _in_vc_sel_T_49) node _in_vc_sel_T_52 = or(_in_vc_sel_T_51, _in_vc_sel_T_50) wire _in_vc_sel_WIRE_11 : UInt<1> connect _in_vc_sel_WIRE_11, _in_vc_sel_T_52 connect _in_vc_sel_WIRE_9[1], _in_vc_sel_WIRE_11 node _in_vc_sel_T_53 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[2], UInt<1>(0h0)) node _in_vc_sel_T_54 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[2], UInt<1>(0h0)) node _in_vc_sel_T_55 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[2], UInt<1>(0h0)) node _in_vc_sel_T_56 = or(_in_vc_sel_T_53, _in_vc_sel_T_54) node _in_vc_sel_T_57 = or(_in_vc_sel_T_56, _in_vc_sel_T_55) wire _in_vc_sel_WIRE_12 : UInt<1> connect _in_vc_sel_WIRE_12, _in_vc_sel_T_57 connect _in_vc_sel_WIRE_9[2], _in_vc_sel_WIRE_12 node _in_vc_sel_T_58 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[3], UInt<1>(0h0)) node _in_vc_sel_T_59 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[3], UInt<1>(0h0)) node _in_vc_sel_T_60 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[3], UInt<1>(0h0)) node _in_vc_sel_T_61 = or(_in_vc_sel_T_58, _in_vc_sel_T_59) node _in_vc_sel_T_62 = or(_in_vc_sel_T_61, _in_vc_sel_T_60) wire _in_vc_sel_WIRE_13 : UInt<1> connect _in_vc_sel_WIRE_13, _in_vc_sel_T_62 connect _in_vc_sel_WIRE_9[3], _in_vc_sel_WIRE_13 node _in_vc_sel_T_63 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[4], UInt<1>(0h0)) node _in_vc_sel_T_64 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[4], UInt<1>(0h0)) node _in_vc_sel_T_65 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[4], UInt<1>(0h0)) node _in_vc_sel_T_66 = or(_in_vc_sel_T_63, _in_vc_sel_T_64) node _in_vc_sel_T_67 = or(_in_vc_sel_T_66, _in_vc_sel_T_65) wire _in_vc_sel_WIRE_14 : UInt<1> connect _in_vc_sel_WIRE_14, _in_vc_sel_T_67 connect _in_vc_sel_WIRE_9[4], _in_vc_sel_WIRE_14 node _in_vc_sel_T_68 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[5], UInt<1>(0h0)) node _in_vc_sel_T_69 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[5], UInt<1>(0h0)) node _in_vc_sel_T_70 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[5], UInt<1>(0h0)) node _in_vc_sel_T_71 = or(_in_vc_sel_T_68, _in_vc_sel_T_69) node _in_vc_sel_T_72 = or(_in_vc_sel_T_71, _in_vc_sel_T_70) wire _in_vc_sel_WIRE_15 : UInt<1> connect _in_vc_sel_WIRE_15, _in_vc_sel_T_72 connect _in_vc_sel_WIRE_9[5], _in_vc_sel_WIRE_15 node _in_vc_sel_T_73 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[6], UInt<1>(0h0)) node _in_vc_sel_T_74 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[6], UInt<1>(0h0)) node _in_vc_sel_T_75 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[6], UInt<1>(0h0)) node _in_vc_sel_T_76 = or(_in_vc_sel_T_73, _in_vc_sel_T_74) node _in_vc_sel_T_77 = or(_in_vc_sel_T_76, _in_vc_sel_T_75) wire _in_vc_sel_WIRE_16 : UInt<1> connect _in_vc_sel_WIRE_16, _in_vc_sel_T_77 connect _in_vc_sel_WIRE_9[6], _in_vc_sel_WIRE_16 node _in_vc_sel_T_78 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[7], UInt<1>(0h0)) node _in_vc_sel_T_79 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[7], UInt<1>(0h0)) node _in_vc_sel_T_80 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[7], UInt<1>(0h0)) node _in_vc_sel_T_81 = or(_in_vc_sel_T_78, _in_vc_sel_T_79) node _in_vc_sel_T_82 = or(_in_vc_sel_T_81, _in_vc_sel_T_80) wire _in_vc_sel_WIRE_17 : UInt<1> connect _in_vc_sel_WIRE_17, _in_vc_sel_T_82 connect _in_vc_sel_WIRE_9[7], _in_vc_sel_WIRE_17 connect in_vc_sel.`1`, _in_vc_sel_WIRE_9 wire _in_vc_sel_WIRE_18 : UInt<1>[8] node _in_vc_sel_T_83 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_84 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_85 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_86 = or(_in_vc_sel_T_83, _in_vc_sel_T_84) node _in_vc_sel_T_87 = or(_in_vc_sel_T_86, _in_vc_sel_T_85) wire _in_vc_sel_WIRE_19 : UInt<1> connect _in_vc_sel_WIRE_19, _in_vc_sel_T_87 connect _in_vc_sel_WIRE_18[0], _in_vc_sel_WIRE_19 node _in_vc_sel_T_88 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_89 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_90 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_91 = or(_in_vc_sel_T_88, _in_vc_sel_T_89) node _in_vc_sel_T_92 = or(_in_vc_sel_T_91, _in_vc_sel_T_90) wire _in_vc_sel_WIRE_20 : UInt<1> connect _in_vc_sel_WIRE_20, _in_vc_sel_T_92 connect _in_vc_sel_WIRE_18[1], _in_vc_sel_WIRE_20 node _in_vc_sel_T_93 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[2], UInt<1>(0h0)) node _in_vc_sel_T_94 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[2], UInt<1>(0h0)) node _in_vc_sel_T_95 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[2], UInt<1>(0h0)) node _in_vc_sel_T_96 = or(_in_vc_sel_T_93, _in_vc_sel_T_94) node _in_vc_sel_T_97 = or(_in_vc_sel_T_96, _in_vc_sel_T_95) wire _in_vc_sel_WIRE_21 : UInt<1> connect _in_vc_sel_WIRE_21, _in_vc_sel_T_97 connect _in_vc_sel_WIRE_18[2], _in_vc_sel_WIRE_21 node _in_vc_sel_T_98 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[3], UInt<1>(0h0)) node _in_vc_sel_T_99 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[3], UInt<1>(0h0)) node _in_vc_sel_T_100 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[3], UInt<1>(0h0)) node _in_vc_sel_T_101 = or(_in_vc_sel_T_98, _in_vc_sel_T_99) node _in_vc_sel_T_102 = or(_in_vc_sel_T_101, _in_vc_sel_T_100) wire _in_vc_sel_WIRE_22 : UInt<1> connect _in_vc_sel_WIRE_22, _in_vc_sel_T_102 connect _in_vc_sel_WIRE_18[3], _in_vc_sel_WIRE_22 node _in_vc_sel_T_103 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[4], UInt<1>(0h0)) node _in_vc_sel_T_104 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[4], UInt<1>(0h0)) node _in_vc_sel_T_105 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[4], UInt<1>(0h0)) node _in_vc_sel_T_106 = or(_in_vc_sel_T_103, _in_vc_sel_T_104) node _in_vc_sel_T_107 = or(_in_vc_sel_T_106, _in_vc_sel_T_105) wire _in_vc_sel_WIRE_23 : UInt<1> connect _in_vc_sel_WIRE_23, _in_vc_sel_T_107 connect _in_vc_sel_WIRE_18[4], _in_vc_sel_WIRE_23 node _in_vc_sel_T_108 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[5], UInt<1>(0h0)) node _in_vc_sel_T_109 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[5], UInt<1>(0h0)) node _in_vc_sel_T_110 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[5], UInt<1>(0h0)) node _in_vc_sel_T_111 = or(_in_vc_sel_T_108, _in_vc_sel_T_109) node _in_vc_sel_T_112 = or(_in_vc_sel_T_111, _in_vc_sel_T_110) wire _in_vc_sel_WIRE_24 : UInt<1> connect _in_vc_sel_WIRE_24, _in_vc_sel_T_112 connect _in_vc_sel_WIRE_18[5], _in_vc_sel_WIRE_24 node _in_vc_sel_T_113 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[6], UInt<1>(0h0)) node _in_vc_sel_T_114 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[6], UInt<1>(0h0)) node _in_vc_sel_T_115 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[6], UInt<1>(0h0)) node _in_vc_sel_T_116 = or(_in_vc_sel_T_113, _in_vc_sel_T_114) node _in_vc_sel_T_117 = or(_in_vc_sel_T_116, _in_vc_sel_T_115) wire _in_vc_sel_WIRE_25 : UInt<1> connect _in_vc_sel_WIRE_25, _in_vc_sel_T_117 connect _in_vc_sel_WIRE_18[6], _in_vc_sel_WIRE_25 node _in_vc_sel_T_118 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[7], UInt<1>(0h0)) node _in_vc_sel_T_119 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[7], UInt<1>(0h0)) node _in_vc_sel_T_120 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[7], UInt<1>(0h0)) node _in_vc_sel_T_121 = or(_in_vc_sel_T_118, _in_vc_sel_T_119) node _in_vc_sel_T_122 = or(_in_vc_sel_T_121, _in_vc_sel_T_120) wire _in_vc_sel_WIRE_26 : UInt<1> connect _in_vc_sel_WIRE_26, _in_vc_sel_T_122 connect _in_vc_sel_WIRE_18[7], _in_vc_sel_WIRE_26 connect in_vc_sel.`2`, _in_vc_sel_WIRE_18 node _T_2 = or(in_arb_vals[0], in_arb_vals[1]) node _T_3 = or(_T_2, in_arb_vals[2]) node hi = bits(in_arb_sel, 2, 2) node lo = bits(in_arb_sel, 1, 0) node _T_4 = orr(hi) node _T_5 = or(hi, lo) node _T_6 = bits(_T_5, 1, 1) node _T_7 = cat(_T_4, _T_6) node _T_8 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_9 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_10 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_11 = or(_T_8, _T_9) node _T_12 = or(_T_11, _T_10) node lo_lo = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node lo_hi = cat(in_vc_sel.`0`[3], in_vc_sel.`0`[2]) node lo_1 = cat(lo_hi, lo_lo) node hi_lo = cat(in_vc_sel.`0`[5], in_vc_sel.`0`[4]) node hi_hi = cat(in_vc_sel.`0`[7], in_vc_sel.`0`[6]) node hi_1 = cat(hi_hi, hi_lo) node _T_13 = cat(hi_1, lo_1) node lo_lo_1 = cat(in_vc_sel.`1`[1], in_vc_sel.`1`[0]) node lo_hi_1 = cat(in_vc_sel.`1`[3], in_vc_sel.`1`[2]) node lo_2 = cat(lo_hi_1, lo_lo_1) node hi_lo_1 = cat(in_vc_sel.`1`[5], in_vc_sel.`1`[4]) node hi_hi_1 = cat(in_vc_sel.`1`[7], in_vc_sel.`1`[6]) node hi_2 = cat(hi_hi_1, hi_lo_1) node _T_14 = cat(hi_2, lo_2) node lo_lo_2 = cat(in_vc_sel.`2`[1], in_vc_sel.`2`[0]) node lo_hi_2 = cat(in_vc_sel.`2`[3], in_vc_sel.`2`[2]) node lo_3 = cat(lo_hi_2, lo_lo_2) node hi_lo_2 = cat(in_vc_sel.`2`[5], in_vc_sel.`2`[4]) node hi_hi_2 = cat(in_vc_sel.`2`[7], in_vc_sel.`2`[6]) node hi_3 = cat(hi_hi_2, hi_lo_2) node _T_15 = cat(hi_3, lo_3) node hi_4 = cat(_T_15, _T_14) node _T_16 = cat(hi_4, _T_13) regreset mask_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_16, _full_T) node full = cat(_T_16, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = bits(full, 10, 10) node _oh_T_11 = bits(full, 11, 11) node _oh_T_12 = bits(full, 12, 12) node _oh_T_13 = bits(full, 13, 13) node _oh_T_14 = bits(full, 14, 14) node _oh_T_15 = bits(full, 15, 15) node _oh_T_16 = bits(full, 16, 16) node _oh_T_17 = bits(full, 17, 17) node _oh_T_18 = bits(full, 18, 18) node _oh_T_19 = bits(full, 19, 19) node _oh_T_20 = bits(full, 20, 20) node _oh_T_21 = bits(full, 21, 21) node _oh_T_22 = bits(full, 22, 22) node _oh_T_23 = bits(full, 23, 23) node _oh_T_24 = bits(full, 24, 24) node _oh_T_25 = bits(full, 25, 25) node _oh_T_26 = bits(full, 26, 26) node _oh_T_27 = bits(full, 27, 27) node _oh_T_28 = bits(full, 28, 28) node _oh_T_29 = bits(full, 29, 29) node _oh_T_30 = bits(full, 30, 30) node _oh_T_31 = bits(full, 31, 31) node _oh_T_32 = bits(full, 32, 32) node _oh_T_33 = bits(full, 33, 33) node _oh_T_34 = bits(full, 34, 34) node _oh_T_35 = bits(full, 35, 35) node _oh_T_36 = bits(full, 36, 36) node _oh_T_37 = bits(full, 37, 37) node _oh_T_38 = bits(full, 38, 38) node _oh_T_39 = bits(full, 39, 39) node _oh_T_40 = bits(full, 40, 40) node _oh_T_41 = bits(full, 41, 41) node _oh_T_42 = bits(full, 42, 42) node _oh_T_43 = bits(full, 43, 43) node _oh_T_44 = bits(full, 44, 44) node _oh_T_45 = bits(full, 45, 45) node _oh_T_46 = bits(full, 46, 46) node _oh_T_47 = bits(full, 47, 47) node _oh_T_48 = mux(_oh_T_47, UInt<48>(0h800000000000), UInt<48>(0h0)) node _oh_T_49 = mux(_oh_T_46, UInt<48>(0h400000000000), _oh_T_48) node _oh_T_50 = mux(_oh_T_45, UInt<48>(0h200000000000), _oh_T_49) node _oh_T_51 = mux(_oh_T_44, UInt<48>(0h100000000000), _oh_T_50) node _oh_T_52 = mux(_oh_T_43, UInt<48>(0h80000000000), _oh_T_51) node _oh_T_53 = mux(_oh_T_42, UInt<48>(0h40000000000), _oh_T_52) node _oh_T_54 = mux(_oh_T_41, UInt<48>(0h20000000000), _oh_T_53) node _oh_T_55 = mux(_oh_T_40, UInt<48>(0h10000000000), _oh_T_54) node _oh_T_56 = mux(_oh_T_39, UInt<48>(0h8000000000), _oh_T_55) node _oh_T_57 = mux(_oh_T_38, UInt<48>(0h4000000000), _oh_T_56) node _oh_T_58 = mux(_oh_T_37, UInt<48>(0h2000000000), _oh_T_57) node _oh_T_59 = mux(_oh_T_36, UInt<48>(0h1000000000), _oh_T_58) node _oh_T_60 = mux(_oh_T_35, UInt<48>(0h800000000), _oh_T_59) node _oh_T_61 = mux(_oh_T_34, UInt<48>(0h400000000), _oh_T_60) node _oh_T_62 = mux(_oh_T_33, UInt<48>(0h200000000), _oh_T_61) node _oh_T_63 = mux(_oh_T_32, UInt<48>(0h100000000), _oh_T_62) node _oh_T_64 = mux(_oh_T_31, UInt<48>(0h80000000), _oh_T_63) node _oh_T_65 = mux(_oh_T_30, UInt<48>(0h40000000), _oh_T_64) node _oh_T_66 = mux(_oh_T_29, UInt<48>(0h20000000), _oh_T_65) node _oh_T_67 = mux(_oh_T_28, UInt<48>(0h10000000), _oh_T_66) node _oh_T_68 = mux(_oh_T_27, UInt<48>(0h8000000), _oh_T_67) node _oh_T_69 = mux(_oh_T_26, UInt<48>(0h4000000), _oh_T_68) node _oh_T_70 = mux(_oh_T_25, UInt<48>(0h2000000), _oh_T_69) node _oh_T_71 = mux(_oh_T_24, UInt<48>(0h1000000), _oh_T_70) node _oh_T_72 = mux(_oh_T_23, UInt<48>(0h800000), _oh_T_71) node _oh_T_73 = mux(_oh_T_22, UInt<48>(0h400000), _oh_T_72) node _oh_T_74 = mux(_oh_T_21, UInt<48>(0h200000), _oh_T_73) node _oh_T_75 = mux(_oh_T_20, UInt<48>(0h100000), _oh_T_74) node _oh_T_76 = mux(_oh_T_19, UInt<48>(0h80000), _oh_T_75) node _oh_T_77 = mux(_oh_T_18, UInt<48>(0h40000), _oh_T_76) node _oh_T_78 = mux(_oh_T_17, UInt<48>(0h20000), _oh_T_77) node _oh_T_79 = mux(_oh_T_16, UInt<48>(0h10000), _oh_T_78) node _oh_T_80 = mux(_oh_T_15, UInt<48>(0h8000), _oh_T_79) node _oh_T_81 = mux(_oh_T_14, UInt<48>(0h4000), _oh_T_80) node _oh_T_82 = mux(_oh_T_13, UInt<48>(0h2000), _oh_T_81) node _oh_T_83 = mux(_oh_T_12, UInt<48>(0h1000), _oh_T_82) node _oh_T_84 = mux(_oh_T_11, UInt<48>(0h800), _oh_T_83) node _oh_T_85 = mux(_oh_T_10, UInt<48>(0h400), _oh_T_84) node _oh_T_86 = mux(_oh_T_9, UInt<48>(0h200), _oh_T_85) node _oh_T_87 = mux(_oh_T_8, UInt<48>(0h100), _oh_T_86) node _oh_T_88 = mux(_oh_T_7, UInt<48>(0h80), _oh_T_87) node _oh_T_89 = mux(_oh_T_6, UInt<48>(0h40), _oh_T_88) node _oh_T_90 = mux(_oh_T_5, UInt<48>(0h20), _oh_T_89) node _oh_T_91 = mux(_oh_T_4, UInt<48>(0h10), _oh_T_90) node _oh_T_92 = mux(_oh_T_3, UInt<48>(0h8), _oh_T_91) node _oh_T_93 = mux(_oh_T_2, UInt<48>(0h4), _oh_T_92) node _oh_T_94 = mux(_oh_T_1, UInt<48>(0h2), _oh_T_93) node oh = mux(_oh_T, UInt<48>(0h1), _oh_T_94) node _sel_T = bits(oh, 23, 0) node _sel_T_1 = shr(oh, 24) node sel = or(_sel_T, _sel_T_1) when _T_12 : node _mask_T_11 = bits(sel, 0, 0) node _mask_T_12 = not(UInt<1>(0h0)) node _mask_T_13 = bits(sel, 1, 1) node _mask_T_14 = not(UInt<2>(0h0)) node _mask_T_15 = bits(sel, 2, 2) node _mask_T_16 = not(UInt<3>(0h0)) node _mask_T_17 = bits(sel, 3, 3) node _mask_T_18 = not(UInt<4>(0h0)) node _mask_T_19 = bits(sel, 4, 4) node _mask_T_20 = not(UInt<5>(0h0)) node _mask_T_21 = bits(sel, 5, 5) node _mask_T_22 = not(UInt<6>(0h0)) node _mask_T_23 = bits(sel, 6, 6) node _mask_T_24 = not(UInt<7>(0h0)) node _mask_T_25 = bits(sel, 7, 7) node _mask_T_26 = not(UInt<8>(0h0)) node _mask_T_27 = bits(sel, 8, 8) node _mask_T_28 = not(UInt<9>(0h0)) node _mask_T_29 = bits(sel, 9, 9) node _mask_T_30 = not(UInt<10>(0h0)) node _mask_T_31 = bits(sel, 10, 10) node _mask_T_32 = not(UInt<11>(0h0)) node _mask_T_33 = bits(sel, 11, 11) node _mask_T_34 = not(UInt<12>(0h0)) node _mask_T_35 = bits(sel, 12, 12) node _mask_T_36 = not(UInt<13>(0h0)) node _mask_T_37 = bits(sel, 13, 13) node _mask_T_38 = not(UInt<14>(0h0)) node _mask_T_39 = bits(sel, 14, 14) node _mask_T_40 = not(UInt<15>(0h0)) node _mask_T_41 = bits(sel, 15, 15) node _mask_T_42 = not(UInt<16>(0h0)) node _mask_T_43 = bits(sel, 16, 16) node _mask_T_44 = not(UInt<17>(0h0)) node _mask_T_45 = bits(sel, 17, 17) node _mask_T_46 = not(UInt<18>(0h0)) node _mask_T_47 = bits(sel, 18, 18) node _mask_T_48 = not(UInt<19>(0h0)) node _mask_T_49 = bits(sel, 19, 19) node _mask_T_50 = not(UInt<20>(0h0)) node _mask_T_51 = bits(sel, 20, 20) node _mask_T_52 = not(UInt<21>(0h0)) node _mask_T_53 = bits(sel, 21, 21) node _mask_T_54 = not(UInt<22>(0h0)) node _mask_T_55 = bits(sel, 22, 22) node _mask_T_56 = not(UInt<23>(0h0)) node _mask_T_57 = bits(sel, 23, 23) node _mask_T_58 = not(UInt<24>(0h0)) node _mask_T_59 = mux(_mask_T_57, _mask_T_58, UInt<1>(0h0)) node _mask_T_60 = mux(_mask_T_55, _mask_T_56, _mask_T_59) node _mask_T_61 = mux(_mask_T_53, _mask_T_54, _mask_T_60) node _mask_T_62 = mux(_mask_T_51, _mask_T_52, _mask_T_61) node _mask_T_63 = mux(_mask_T_49, _mask_T_50, _mask_T_62) node _mask_T_64 = mux(_mask_T_47, _mask_T_48, _mask_T_63) node _mask_T_65 = mux(_mask_T_45, _mask_T_46, _mask_T_64) node _mask_T_66 = mux(_mask_T_43, _mask_T_44, _mask_T_65) node _mask_T_67 = mux(_mask_T_41, _mask_T_42, _mask_T_66) node _mask_T_68 = mux(_mask_T_39, _mask_T_40, _mask_T_67) node _mask_T_69 = mux(_mask_T_37, _mask_T_38, _mask_T_68) node _mask_T_70 = mux(_mask_T_35, _mask_T_36, _mask_T_69) node _mask_T_71 = mux(_mask_T_33, _mask_T_34, _mask_T_70) node _mask_T_72 = mux(_mask_T_31, _mask_T_32, _mask_T_71) node _mask_T_73 = mux(_mask_T_29, _mask_T_30, _mask_T_72) node _mask_T_74 = mux(_mask_T_27, _mask_T_28, _mask_T_73) node _mask_T_75 = mux(_mask_T_25, _mask_T_26, _mask_T_74) node _mask_T_76 = mux(_mask_T_23, _mask_T_24, _mask_T_75) node _mask_T_77 = mux(_mask_T_21, _mask_T_22, _mask_T_76) node _mask_T_78 = mux(_mask_T_19, _mask_T_20, _mask_T_77) node _mask_T_79 = mux(_mask_T_17, _mask_T_18, _mask_T_78) node _mask_T_80 = mux(_mask_T_15, _mask_T_16, _mask_T_79) node _mask_T_81 = mux(_mask_T_13, _mask_T_14, _mask_T_80) node _mask_T_82 = mux(_mask_T_11, _mask_T_12, _mask_T_81) connect mask_1, _mask_T_82 wire _WIRE : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _WIRE_1 : UInt<24> connect _WIRE_1, sel node _T_17 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_17 node _T_18 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_18 node _T_19 = bits(_WIRE_1, 2, 2) connect _WIRE.`0`[2], _T_19 node _T_20 = bits(_WIRE_1, 3, 3) connect _WIRE.`0`[3], _T_20 node _T_21 = bits(_WIRE_1, 4, 4) connect _WIRE.`0`[4], _T_21 node _T_22 = bits(_WIRE_1, 5, 5) connect _WIRE.`0`[5], _T_22 node _T_23 = bits(_WIRE_1, 6, 6) connect _WIRE.`0`[6], _T_23 node _T_24 = bits(_WIRE_1, 7, 7) connect _WIRE.`0`[7], _T_24 node _T_25 = bits(_WIRE_1, 8, 8) connect _WIRE.`1`[0], _T_25 node _T_26 = bits(_WIRE_1, 9, 9) connect _WIRE.`1`[1], _T_26 node _T_27 = bits(_WIRE_1, 10, 10) connect _WIRE.`1`[2], _T_27 node _T_28 = bits(_WIRE_1, 11, 11) connect _WIRE.`1`[3], _T_28 node _T_29 = bits(_WIRE_1, 12, 12) connect _WIRE.`1`[4], _T_29 node _T_30 = bits(_WIRE_1, 13, 13) connect _WIRE.`1`[5], _T_30 node _T_31 = bits(_WIRE_1, 14, 14) connect _WIRE.`1`[6], _T_31 node _T_32 = bits(_WIRE_1, 15, 15) connect _WIRE.`1`[7], _T_32 node _T_33 = bits(_WIRE_1, 16, 16) connect _WIRE.`2`[0], _T_33 node _T_34 = bits(_WIRE_1, 17, 17) connect _WIRE.`2`[1], _T_34 node _T_35 = bits(_WIRE_1, 18, 18) connect _WIRE.`2`[2], _T_35 node _T_36 = bits(_WIRE_1, 19, 19) connect _WIRE.`2`[3], _T_36 node _T_37 = bits(_WIRE_1, 20, 20) connect _WIRE.`2`[4], _T_37 node _T_38 = bits(_WIRE_1, 21, 21) connect _WIRE.`2`[5], _T_38 node _T_39 = bits(_WIRE_1, 22, 22) connect _WIRE.`2`[6], _T_39 node _T_40 = bits(_WIRE_1, 23, 23) connect _WIRE.`2`[7], _T_40 wire _WIRE_2 : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`0`[2], UInt<1>(0h0) connect _WIRE_2.`0`[3], UInt<1>(0h0) connect _WIRE_2.`0`[4], UInt<1>(0h0) connect _WIRE_2.`0`[5], UInt<1>(0h0) connect _WIRE_2.`0`[6], UInt<1>(0h0) connect _WIRE_2.`0`[7], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`1`[1], UInt<1>(0h0) connect _WIRE_2.`1`[2], UInt<1>(0h0) connect _WIRE_2.`1`[3], UInt<1>(0h0) connect _WIRE_2.`1`[4], UInt<1>(0h0) connect _WIRE_2.`1`[5], UInt<1>(0h0) connect _WIRE_2.`1`[6], UInt<1>(0h0) connect _WIRE_2.`1`[7], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) connect _WIRE_2.`2`[1], UInt<1>(0h0) connect _WIRE_2.`2`[2], UInt<1>(0h0) connect _WIRE_2.`2`[3], UInt<1>(0h0) connect _WIRE_2.`2`[4], UInt<1>(0h0) connect _WIRE_2.`2`[5], UInt<1>(0h0) connect _WIRE_2.`2`[6], UInt<1>(0h0) connect _WIRE_2.`2`[7], UInt<1>(0h0) node _T_41 = mux(_T_3, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_41.`0` connect in_alloc.`1`, _T_41.`1` connect in_alloc.`2`, _T_41.`2` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`0`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`0`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`0`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`0`.vc_sel.`1`[2], in_alloc.`1`[2] connect io.resp.`0`.vc_sel.`1`[3], in_alloc.`1`[3] connect io.resp.`0`.vc_sel.`1`[4], in_alloc.`1`[4] connect io.resp.`0`.vc_sel.`1`[5], in_alloc.`1`[5] connect io.resp.`0`.vc_sel.`1`[6], in_alloc.`1`[6] connect io.resp.`0`.vc_sel.`1`[7], in_alloc.`1`[7] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`0`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`0`.vc_sel.`2`[2], in_alloc.`2`[2] connect io.resp.`0`.vc_sel.`2`[3], in_alloc.`2`[3] connect io.resp.`0`.vc_sel.`2`[4], in_alloc.`2`[4] connect io.resp.`0`.vc_sel.`2`[5], in_alloc.`2`[5] connect io.resp.`0`.vc_sel.`2`[6], in_alloc.`2`[6] connect io.resp.`0`.vc_sel.`2`[7], in_alloc.`2`[7] node lo_lo_3 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node lo_hi_3 = cat(io.resp.`0`.vc_sel.`0`[3], io.resp.`0`.vc_sel.`0`[2]) node lo_4 = cat(lo_hi_3, lo_lo_3) node hi_lo_3 = cat(io.resp.`0`.vc_sel.`0`[5], io.resp.`0`.vc_sel.`0`[4]) node hi_hi_3 = cat(io.resp.`0`.vc_sel.`0`[7], io.resp.`0`.vc_sel.`0`[6]) node hi_5 = cat(hi_hi_3, hi_lo_3) node _T_42 = cat(hi_5, lo_4) node lo_lo_4 = cat(io.resp.`0`.vc_sel.`1`[1], io.resp.`0`.vc_sel.`1`[0]) node lo_hi_4 = cat(io.resp.`0`.vc_sel.`1`[3], io.resp.`0`.vc_sel.`1`[2]) node lo_5 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(io.resp.`0`.vc_sel.`1`[5], io.resp.`0`.vc_sel.`1`[4]) node hi_hi_4 = cat(io.resp.`0`.vc_sel.`1`[7], io.resp.`0`.vc_sel.`1`[6]) node hi_6 = cat(hi_hi_4, hi_lo_4) node _T_43 = cat(hi_6, lo_5) node lo_lo_5 = cat(io.resp.`0`.vc_sel.`2`[1], io.resp.`0`.vc_sel.`2`[0]) node lo_hi_5 = cat(io.resp.`0`.vc_sel.`2`[3], io.resp.`0`.vc_sel.`2`[2]) node lo_6 = cat(lo_hi_5, lo_lo_5) node hi_lo_5 = cat(io.resp.`0`.vc_sel.`2`[5], io.resp.`0`.vc_sel.`2`[4]) node hi_hi_5 = cat(io.resp.`0`.vc_sel.`2`[7], io.resp.`0`.vc_sel.`2`[6]) node hi_7 = cat(hi_hi_5, hi_lo_5) node _T_44 = cat(hi_7, lo_6) node hi_8 = cat(_T_44, _T_43) node _T_45 = cat(hi_8, _T_42) node _T_46 = bits(_T_45, 0, 0) node _T_47 = bits(_T_45, 1, 1) node _T_48 = bits(_T_45, 2, 2) node _T_49 = bits(_T_45, 3, 3) node _T_50 = bits(_T_45, 4, 4) node _T_51 = bits(_T_45, 5, 5) node _T_52 = bits(_T_45, 6, 6) node _T_53 = bits(_T_45, 7, 7) node _T_54 = bits(_T_45, 8, 8) node _T_55 = bits(_T_45, 9, 9) node _T_56 = bits(_T_45, 10, 10) node _T_57 = bits(_T_45, 11, 11) node _T_58 = bits(_T_45, 12, 12) node _T_59 = bits(_T_45, 13, 13) node _T_60 = bits(_T_45, 14, 14) node _T_61 = bits(_T_45, 15, 15) node _T_62 = bits(_T_45, 16, 16) node _T_63 = bits(_T_45, 17, 17) node _T_64 = bits(_T_45, 18, 18) node _T_65 = bits(_T_45, 19, 19) node _T_66 = bits(_T_45, 20, 20) node _T_67 = bits(_T_45, 21, 21) node _T_68 = bits(_T_45, 22, 22) node _T_69 = bits(_T_45, 23, 23) node _T_70 = add(_T_47, _T_48) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(_T_46, _T_71) node _T_73 = bits(_T_72, 1, 0) node _T_74 = add(_T_50, _T_51) node _T_75 = bits(_T_74, 1, 0) node _T_76 = add(_T_49, _T_75) node _T_77 = bits(_T_76, 1, 0) node _T_78 = add(_T_73, _T_77) node _T_79 = bits(_T_78, 2, 0) node _T_80 = add(_T_53, _T_54) node _T_81 = bits(_T_80, 1, 0) node _T_82 = add(_T_52, _T_81) node _T_83 = bits(_T_82, 1, 0) node _T_84 = add(_T_56, _T_57) node _T_85 = bits(_T_84, 1, 0) node _T_86 = add(_T_55, _T_85) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(_T_83, _T_87) node _T_89 = bits(_T_88, 2, 0) node _T_90 = add(_T_79, _T_89) node _T_91 = bits(_T_90, 3, 0) node _T_92 = add(_T_59, _T_60) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_58, _T_93) node _T_95 = bits(_T_94, 1, 0) node _T_96 = add(_T_62, _T_63) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_61, _T_97) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_95, _T_99) node _T_101 = bits(_T_100, 2, 0) node _T_102 = add(_T_65, _T_66) node _T_103 = bits(_T_102, 1, 0) node _T_104 = add(_T_64, _T_103) node _T_105 = bits(_T_104, 1, 0) node _T_106 = add(_T_68, _T_69) node _T_107 = bits(_T_106, 1, 0) node _T_108 = add(_T_67, _T_107) node _T_109 = bits(_T_108, 1, 0) node _T_110 = add(_T_105, _T_109) node _T_111 = bits(_T_110, 2, 0) node _T_112 = add(_T_101, _T_111) node _T_113 = bits(_T_112, 3, 0) node _T_114 = add(_T_91, _T_113) node _T_115 = bits(_T_114, 4, 0) node _T_116 = leq(_T_115, UInt<1>(0h1)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_116, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`1`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`1`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`1`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`1`.vc_sel.`1`[2], in_alloc.`1`[2] connect io.resp.`1`.vc_sel.`1`[3], in_alloc.`1`[3] connect io.resp.`1`.vc_sel.`1`[4], in_alloc.`1`[4] connect io.resp.`1`.vc_sel.`1`[5], in_alloc.`1`[5] connect io.resp.`1`.vc_sel.`1`[6], in_alloc.`1`[6] connect io.resp.`1`.vc_sel.`1`[7], in_alloc.`1`[7] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`1`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`1`.vc_sel.`2`[2], in_alloc.`2`[2] connect io.resp.`1`.vc_sel.`2`[3], in_alloc.`2`[3] connect io.resp.`1`.vc_sel.`2`[4], in_alloc.`2`[4] connect io.resp.`1`.vc_sel.`2`[5], in_alloc.`2`[5] connect io.resp.`1`.vc_sel.`2`[6], in_alloc.`2`[6] connect io.resp.`1`.vc_sel.`2`[7], in_alloc.`2`[7] node lo_lo_6 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node lo_hi_6 = cat(io.resp.`1`.vc_sel.`0`[3], io.resp.`1`.vc_sel.`0`[2]) node lo_7 = cat(lo_hi_6, lo_lo_6) node hi_lo_6 = cat(io.resp.`1`.vc_sel.`0`[5], io.resp.`1`.vc_sel.`0`[4]) node hi_hi_6 = cat(io.resp.`1`.vc_sel.`0`[7], io.resp.`1`.vc_sel.`0`[6]) node hi_9 = cat(hi_hi_6, hi_lo_6) node _T_120 = cat(hi_9, lo_7) node lo_lo_7 = cat(io.resp.`1`.vc_sel.`1`[1], io.resp.`1`.vc_sel.`1`[0]) node lo_hi_7 = cat(io.resp.`1`.vc_sel.`1`[3], io.resp.`1`.vc_sel.`1`[2]) node lo_8 = cat(lo_hi_7, lo_lo_7) node hi_lo_7 = cat(io.resp.`1`.vc_sel.`1`[5], io.resp.`1`.vc_sel.`1`[4]) node hi_hi_7 = cat(io.resp.`1`.vc_sel.`1`[7], io.resp.`1`.vc_sel.`1`[6]) node hi_10 = cat(hi_hi_7, hi_lo_7) node _T_121 = cat(hi_10, lo_8) node lo_lo_8 = cat(io.resp.`1`.vc_sel.`2`[1], io.resp.`1`.vc_sel.`2`[0]) node lo_hi_8 = cat(io.resp.`1`.vc_sel.`2`[3], io.resp.`1`.vc_sel.`2`[2]) node lo_9 = cat(lo_hi_8, lo_lo_8) node hi_lo_8 = cat(io.resp.`1`.vc_sel.`2`[5], io.resp.`1`.vc_sel.`2`[4]) node hi_hi_8 = cat(io.resp.`1`.vc_sel.`2`[7], io.resp.`1`.vc_sel.`2`[6]) node hi_11 = cat(hi_hi_8, hi_lo_8) node _T_122 = cat(hi_11, lo_9) node hi_12 = cat(_T_122, _T_121) node _T_123 = cat(hi_12, _T_120) node _T_124 = bits(_T_123, 0, 0) node _T_125 = bits(_T_123, 1, 1) node _T_126 = bits(_T_123, 2, 2) node _T_127 = bits(_T_123, 3, 3) node _T_128 = bits(_T_123, 4, 4) node _T_129 = bits(_T_123, 5, 5) node _T_130 = bits(_T_123, 6, 6) node _T_131 = bits(_T_123, 7, 7) node _T_132 = bits(_T_123, 8, 8) node _T_133 = bits(_T_123, 9, 9) node _T_134 = bits(_T_123, 10, 10) node _T_135 = bits(_T_123, 11, 11) node _T_136 = bits(_T_123, 12, 12) node _T_137 = bits(_T_123, 13, 13) node _T_138 = bits(_T_123, 14, 14) node _T_139 = bits(_T_123, 15, 15) node _T_140 = bits(_T_123, 16, 16) node _T_141 = bits(_T_123, 17, 17) node _T_142 = bits(_T_123, 18, 18) node _T_143 = bits(_T_123, 19, 19) node _T_144 = bits(_T_123, 20, 20) node _T_145 = bits(_T_123, 21, 21) node _T_146 = bits(_T_123, 22, 22) node _T_147 = bits(_T_123, 23, 23) node _T_148 = add(_T_125, _T_126) node _T_149 = bits(_T_148, 1, 0) node _T_150 = add(_T_124, _T_149) node _T_151 = bits(_T_150, 1, 0) node _T_152 = add(_T_128, _T_129) node _T_153 = bits(_T_152, 1, 0) node _T_154 = add(_T_127, _T_153) node _T_155 = bits(_T_154, 1, 0) node _T_156 = add(_T_151, _T_155) node _T_157 = bits(_T_156, 2, 0) node _T_158 = add(_T_131, _T_132) node _T_159 = bits(_T_158, 1, 0) node _T_160 = add(_T_130, _T_159) node _T_161 = bits(_T_160, 1, 0) node _T_162 = add(_T_134, _T_135) node _T_163 = bits(_T_162, 1, 0) node _T_164 = add(_T_133, _T_163) node _T_165 = bits(_T_164, 1, 0) node _T_166 = add(_T_161, _T_165) node _T_167 = bits(_T_166, 2, 0) node _T_168 = add(_T_157, _T_167) node _T_169 = bits(_T_168, 3, 0) node _T_170 = add(_T_137, _T_138) node _T_171 = bits(_T_170, 1, 0) node _T_172 = add(_T_136, _T_171) node _T_173 = bits(_T_172, 1, 0) node _T_174 = add(_T_140, _T_141) node _T_175 = bits(_T_174, 1, 0) node _T_176 = add(_T_139, _T_175) node _T_177 = bits(_T_176, 1, 0) node _T_178 = add(_T_173, _T_177) node _T_179 = bits(_T_178, 2, 0) node _T_180 = add(_T_143, _T_144) node _T_181 = bits(_T_180, 1, 0) node _T_182 = add(_T_142, _T_181) node _T_183 = bits(_T_182, 1, 0) node _T_184 = add(_T_146, _T_147) node _T_185 = bits(_T_184, 1, 0) node _T_186 = add(_T_145, _T_185) node _T_187 = bits(_T_186, 1, 0) node _T_188 = add(_T_183, _T_187) node _T_189 = bits(_T_188, 2, 0) node _T_190 = add(_T_179, _T_189) node _T_191 = bits(_T_190, 3, 0) node _T_192 = add(_T_169, _T_191) node _T_193 = bits(_T_192, 4, 0) node _T_194 = leq(_T_193, UInt<1>(0h1)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_194, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`2`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`2`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`2`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`2`.vc_sel.`1`[2], in_alloc.`1`[2] connect io.resp.`2`.vc_sel.`1`[3], in_alloc.`1`[3] connect io.resp.`2`.vc_sel.`1`[4], in_alloc.`1`[4] connect io.resp.`2`.vc_sel.`1`[5], in_alloc.`1`[5] connect io.resp.`2`.vc_sel.`1`[6], in_alloc.`1`[6] connect io.resp.`2`.vc_sel.`1`[7], in_alloc.`1`[7] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`2`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`2`.vc_sel.`2`[2], in_alloc.`2`[2] connect io.resp.`2`.vc_sel.`2`[3], in_alloc.`2`[3] connect io.resp.`2`.vc_sel.`2`[4], in_alloc.`2`[4] connect io.resp.`2`.vc_sel.`2`[5], in_alloc.`2`[5] connect io.resp.`2`.vc_sel.`2`[6], in_alloc.`2`[6] connect io.resp.`2`.vc_sel.`2`[7], in_alloc.`2`[7] node lo_lo_9 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node lo_hi_9 = cat(io.resp.`2`.vc_sel.`0`[3], io.resp.`2`.vc_sel.`0`[2]) node lo_10 = cat(lo_hi_9, lo_lo_9) node hi_lo_9 = cat(io.resp.`2`.vc_sel.`0`[5], io.resp.`2`.vc_sel.`0`[4]) node hi_hi_9 = cat(io.resp.`2`.vc_sel.`0`[7], io.resp.`2`.vc_sel.`0`[6]) node hi_13 = cat(hi_hi_9, hi_lo_9) node _T_198 = cat(hi_13, lo_10) node lo_lo_10 = cat(io.resp.`2`.vc_sel.`1`[1], io.resp.`2`.vc_sel.`1`[0]) node lo_hi_10 = cat(io.resp.`2`.vc_sel.`1`[3], io.resp.`2`.vc_sel.`1`[2]) node lo_11 = cat(lo_hi_10, lo_lo_10) node hi_lo_10 = cat(io.resp.`2`.vc_sel.`1`[5], io.resp.`2`.vc_sel.`1`[4]) node hi_hi_10 = cat(io.resp.`2`.vc_sel.`1`[7], io.resp.`2`.vc_sel.`1`[6]) node hi_14 = cat(hi_hi_10, hi_lo_10) node _T_199 = cat(hi_14, lo_11) node lo_lo_11 = cat(io.resp.`2`.vc_sel.`2`[1], io.resp.`2`.vc_sel.`2`[0]) node lo_hi_11 = cat(io.resp.`2`.vc_sel.`2`[3], io.resp.`2`.vc_sel.`2`[2]) node lo_12 = cat(lo_hi_11, lo_lo_11) node hi_lo_11 = cat(io.resp.`2`.vc_sel.`2`[5], io.resp.`2`.vc_sel.`2`[4]) node hi_hi_11 = cat(io.resp.`2`.vc_sel.`2`[7], io.resp.`2`.vc_sel.`2`[6]) node hi_15 = cat(hi_hi_11, hi_lo_11) node _T_200 = cat(hi_15, lo_12) node hi_16 = cat(_T_200, _T_199) node _T_201 = cat(hi_16, _T_198) node _T_202 = bits(_T_201, 0, 0) node _T_203 = bits(_T_201, 1, 1) node _T_204 = bits(_T_201, 2, 2) node _T_205 = bits(_T_201, 3, 3) node _T_206 = bits(_T_201, 4, 4) node _T_207 = bits(_T_201, 5, 5) node _T_208 = bits(_T_201, 6, 6) node _T_209 = bits(_T_201, 7, 7) node _T_210 = bits(_T_201, 8, 8) node _T_211 = bits(_T_201, 9, 9) node _T_212 = bits(_T_201, 10, 10) node _T_213 = bits(_T_201, 11, 11) node _T_214 = bits(_T_201, 12, 12) node _T_215 = bits(_T_201, 13, 13) node _T_216 = bits(_T_201, 14, 14) node _T_217 = bits(_T_201, 15, 15) node _T_218 = bits(_T_201, 16, 16) node _T_219 = bits(_T_201, 17, 17) node _T_220 = bits(_T_201, 18, 18) node _T_221 = bits(_T_201, 19, 19) node _T_222 = bits(_T_201, 20, 20) node _T_223 = bits(_T_201, 21, 21) node _T_224 = bits(_T_201, 22, 22) node _T_225 = bits(_T_201, 23, 23) node _T_226 = add(_T_203, _T_204) node _T_227 = bits(_T_226, 1, 0) node _T_228 = add(_T_202, _T_227) node _T_229 = bits(_T_228, 1, 0) node _T_230 = add(_T_206, _T_207) node _T_231 = bits(_T_230, 1, 0) node _T_232 = add(_T_205, _T_231) node _T_233 = bits(_T_232, 1, 0) node _T_234 = add(_T_229, _T_233) node _T_235 = bits(_T_234, 2, 0) node _T_236 = add(_T_209, _T_210) node _T_237 = bits(_T_236, 1, 0) node _T_238 = add(_T_208, _T_237) node _T_239 = bits(_T_238, 1, 0) node _T_240 = add(_T_212, _T_213) node _T_241 = bits(_T_240, 1, 0) node _T_242 = add(_T_211, _T_241) node _T_243 = bits(_T_242, 1, 0) node _T_244 = add(_T_239, _T_243) node _T_245 = bits(_T_244, 2, 0) node _T_246 = add(_T_235, _T_245) node _T_247 = bits(_T_246, 3, 0) node _T_248 = add(_T_215, _T_216) node _T_249 = bits(_T_248, 1, 0) node _T_250 = add(_T_214, _T_249) node _T_251 = bits(_T_250, 1, 0) node _T_252 = add(_T_218, _T_219) node _T_253 = bits(_T_252, 1, 0) node _T_254 = add(_T_217, _T_253) node _T_255 = bits(_T_254, 1, 0) node _T_256 = add(_T_251, _T_255) node _T_257 = bits(_T_256, 2, 0) node _T_258 = add(_T_221, _T_222) node _T_259 = bits(_T_258, 1, 0) node _T_260 = add(_T_220, _T_259) node _T_261 = bits(_T_260, 1, 0) node _T_262 = add(_T_224, _T_225) node _T_263 = bits(_T_262, 1, 0) node _T_264 = add(_T_223, _T_263) node _T_265 = bits(_T_264, 1, 0) node _T_266 = add(_T_261, _T_265) node _T_267 = bits(_T_266, 2, 0) node _T_268 = add(_T_257, _T_267) node _T_269 = bits(_T_268, 3, 0) node _T_270 = add(_T_247, _T_269) node _T_271 = bits(_T_270, 4, 0) node _T_272 = leq(_T_271, UInt<1>(0h1)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_272, UInt<1>(0h1), "") : assert_2 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2] connect io.out_allocs.`0`[2].flow, in_flow connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3] connect io.out_allocs.`0`[3].flow, in_flow connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4] connect io.out_allocs.`0`[4].flow, in_flow connect io.out_allocs.`0`[5].alloc, in_alloc.`0`[5] connect io.out_allocs.`0`[5].flow, in_flow connect io.out_allocs.`0`[6].alloc, in_alloc.`0`[6] connect io.out_allocs.`0`[6].flow, in_flow connect io.out_allocs.`0`[7].alloc, in_alloc.`0`[7] connect io.out_allocs.`0`[7].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1] connect io.out_allocs.`1`[1].flow, in_flow connect io.out_allocs.`1`[2].alloc, in_alloc.`1`[2] connect io.out_allocs.`1`[2].flow, in_flow connect io.out_allocs.`1`[3].alloc, in_alloc.`1`[3] connect io.out_allocs.`1`[3].flow, in_flow connect io.out_allocs.`1`[4].alloc, in_alloc.`1`[4] connect io.out_allocs.`1`[4].flow, in_flow connect io.out_allocs.`1`[5].alloc, in_alloc.`1`[5] connect io.out_allocs.`1`[5].flow, in_flow connect io.out_allocs.`1`[6].alloc, in_alloc.`1`[6] connect io.out_allocs.`1`[6].flow, in_flow connect io.out_allocs.`1`[7].alloc, in_alloc.`1`[7] connect io.out_allocs.`1`[7].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow connect io.out_allocs.`2`[1].alloc, in_alloc.`2`[1] connect io.out_allocs.`2`[1].flow, in_flow connect io.out_allocs.`2`[2].alloc, in_alloc.`2`[2] connect io.out_allocs.`2`[2].flow, in_flow connect io.out_allocs.`2`[3].alloc, in_alloc.`2`[3] connect io.out_allocs.`2`[3].flow, in_flow connect io.out_allocs.`2`[4].alloc, in_alloc.`2`[4] connect io.out_allocs.`2`[4].flow, in_flow connect io.out_allocs.`2`[5].alloc, in_alloc.`2`[5] connect io.out_allocs.`2`[5].flow, in_flow connect io.out_allocs.`2`[6].alloc, in_alloc.`2`[6] connect io.out_allocs.`2`[6].flow, in_flow connect io.out_allocs.`2`[7].alloc, in_alloc.`2`[7] connect io.out_allocs.`2`[7].flow, in_flow	module RotatingSingleVCAllocator_14( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_3, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_4, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_5, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_6, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_7, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_3, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_4, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_5, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_6, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_7, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_3, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_4, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_5, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_6, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_7, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_3, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_4, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_5, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_6, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_7, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_3, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_4, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_5, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_6, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_7, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_3, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_4, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_5, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_6, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_7, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_3, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_4, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_5, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_6, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_7, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_3, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_4, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_5, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_6, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_7, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_3_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_4_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_5_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_6_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_7_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_3_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_4_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_5_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_6_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_7_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_6_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_7_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_3_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_4_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_5_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_6_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_7_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_3_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_4_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_5_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_6_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_7_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_5_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_6_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_7_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [2:0] mask; // @[SingleVCAllocator.scala:16:21] wire [2:0] _in_arb_filter_T_3 = {in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [5:0] in_arb_filter = _in_arb_filter_T_3[0] ? 6'h1 : _in_arb_filter_T_3[1] ? 6'h2 : _in_arb_filter_T_3[2] ? 6'h4 : in_arb_vals_0 ? 6'h8 : in_arb_vals_1 ? 6'h10 : {in_arb_vals_2, 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_arb_sel = in_arb_filter[2:0] \| in_arb_filter[5:3]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 \| in_arb_vals_1 \| in_arb_vals_2; // @[package.scala:81:59] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_2 = io_req_0_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_3 = io_req_0_bits_vc_sel_1_3 & ~io_channel_status_1_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_4 = io_req_0_bits_vc_sel_1_4 & ~io_channel_status_1_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_5 = io_req_0_bits_vc_sel_1_5 & ~io_channel_status_1_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_6 = io_req_0_bits_vc_sel_1_6 & ~io_channel_status_1_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_7 = io_req_0_bits_vc_sel_1_7 & ~io_channel_status_1_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_1 = io_req_0_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_2 = io_req_0_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_3 = io_req_0_bits_vc_sel_2_3 & ~io_channel_status_2_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_4 = io_req_0_bits_vc_sel_2_4 & ~io_channel_status_2_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_5 = io_req_0_bits_vc_sel_2_5 & ~io_channel_status_2_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_6 = io_req_0_bits_vc_sel_2_6 & ~io_channel_status_2_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_7 = io_req_0_bits_vc_sel_2_7 & ~io_channel_status_2_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_1_0 \| in_arb_reqs_0_1_1 \| in_arb_reqs_0_1_2 \| in_arb_reqs_0_1_3 \| in_arb_reqs_0_1_4 \| in_arb_reqs_0_1_5 \| in_arb_reqs_0_1_6 \| in_arb_reqs_0_1_7 \| in_arb_reqs_0_2_0 \| in_arb_reqs_0_2_1 \| in_arb_reqs_0_2_2 \| in_arb_reqs_0_2_3 \| in_arb_reqs_0_2_4 \| in_arb_reqs_0_2_5 \| in_arb_reqs_0_2_6 \| in_arb_reqs_0_2_7); // @[package.scala:81:59] wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_6 = io_req_1_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_7 = io_req_1_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_1 = io_req_1_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_2 = io_req_1_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_3 = io_req_1_bits_vc_sel_2_3 & ~io_channel_status_2_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_4 = io_req_1_bits_vc_sel_2_4 & ~io_channel_status_2_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_5 = io_req_1_bits_vc_sel_2_5 & ~io_channel_status_2_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_6 = io_req_1_bits_vc_sel_2_6 & ~io_channel_status_2_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_7 = io_req_1_bits_vc_sel_2_7 & ~io_channel_status_2_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_1 \| in_arb_reqs_1_0_2 \| in_arb_reqs_1_0_3 \| in_arb_reqs_1_0_4 \| in_arb_reqs_1_0_5 \| in_arb_reqs_1_0_6 \| in_arb_reqs_1_0_7 \| in_arb_reqs_1_2_0 \| in_arb_reqs_1_2_1 \| in_arb_reqs_1_2_2 \| in_arb_reqs_1_2_3 \| in_arb_reqs_1_2_4 \| in_arb_reqs_1_2_5 \| in_arb_reqs_1_2_6 \| in_arb_reqs_1_2_7); // @[package.scala:81:59] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_3 = io_req_2_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_4 = io_req_2_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_5 = io_req_2_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_6 = io_req_2_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_7 = io_req_2_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_2 = io_req_2_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_3 = io_req_2_bits_vc_sel_1_3 & ~io_channel_status_1_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_4 = io_req_2_bits_vc_sel_1_4 & ~io_channel_status_1_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_5 = io_req_2_bits_vc_sel_1_5 & ~io_channel_status_1_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_6 = io_req_2_bits_vc_sel_1_6 & ~io_channel_status_1_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_7 = io_req_2_bits_vc_sel_1_7 & ~io_channel_status_1_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_1 \| in_arb_reqs_2_0_2 \| in_arb_reqs_2_0_3 \| in_arb_reqs_2_0_4 \| in_arb_reqs_2_0_5 \| in_arb_reqs_2_0_6 \| in_arb_reqs_2_0_7 \| in_arb_reqs_2_1_0 \| in_arb_reqs_2_1_1 \| in_arb_reqs_2_1_2 \| in_arb_reqs_2_1_3 \| in_arb_reqs_2_1_4 \| in_arb_reqs_2_1_5 \| in_arb_reqs_2_1_6 \| in_arb_reqs_2_1_7); // @[package.scala:81:59] wire _in_vc_sel_T_12 = in_arb_sel[1] & in_arb_reqs_1_0_1 \| in_arb_sel[2] & in_arb_reqs_2_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_17 = in_arb_sel[1] & in_arb_reqs_1_0_2 \| in_arb_sel[2] & in_arb_reqs_2_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_22 = in_arb_sel[1] & in_arb_reqs_1_0_3 \| in_arb_sel[2] & in_arb_reqs_2_0_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_27 = in_arb_sel[1] & in_arb_reqs_1_0_4 \| in_arb_sel[2] & in_arb_reqs_2_0_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_32 = in_arb_sel[1] & in_arb_reqs_1_0_5 \| in_arb_sel[2] & in_arb_reqs_2_0_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_37 = in_arb_sel[1] & in_arb_reqs_1_0_6 \| in_arb_sel[2] & in_arb_reqs_2_0_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_42 = in_arb_sel[1] & in_arb_reqs_1_0_7 \| in_arb_sel[2] & in_arb_reqs_2_0_7; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_47 = in_arb_sel[0] & in_arb_reqs_0_1_0 \| in_arb_sel[2] & in_arb_reqs_2_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_52 = in_arb_sel[0] & in_arb_reqs_0_1_1 \| in_arb_sel[2] & in_arb_reqs_2_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_57 = in_arb_sel[0] & in_arb_reqs_0_1_2 \| in_arb_sel[2] & in_arb_reqs_2_1_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_62 = in_arb_sel[0] & in_arb_reqs_0_1_3 \| in_arb_sel[2] & in_arb_reqs_2_1_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_67 = in_arb_sel[0] & in_arb_reqs_0_1_4 \| in_arb_sel[2] & in_arb_reqs_2_1_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_72 = in_arb_sel[0] & in_arb_reqs_0_1_5 \| in_arb_sel[2] & in_arb_reqs_2_1_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_77 = in_arb_sel[0] & in_arb_reqs_0_1_6 \| in_arb_sel[2] & in_arb_reqs_2_1_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_82 = in_arb_sel[0] & in_arb_reqs_0_1_7 \| in_arb_sel[2] & in_arb_reqs_2_1_7; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_86 = in_arb_sel[0] & in_arb_reqs_0_2_0 \| in_arb_sel[1] & in_arb_reqs_1_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_91 = in_arb_sel[0] & in_arb_reqs_0_2_1 \| in_arb_sel[1] & in_arb_reqs_1_2_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_96 = in_arb_sel[0] & in_arb_reqs_0_2_2 \| in_arb_sel[1] & in_arb_reqs_1_2_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_101 = in_arb_sel[0] & in_arb_reqs_0_2_3 \| in_arb_sel[1] & in_arb_reqs_1_2_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_106 = in_arb_sel[0] & in_arb_reqs_0_2_4 \| in_arb_sel[1] & in_arb_reqs_1_2_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_111 = in_arb_sel[0] & in_arb_reqs_0_2_5 \| in_arb_sel[1] & in_arb_reqs_1_2_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_116 = in_arb_sel[0] & in_arb_reqs_0_2_6 \| in_arb_sel[1] & in_arb_reqs_1_2_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_121 = in_arb_sel[0] & in_arb_reqs_0_2_7 \| in_arb_sel[1] & in_arb_reqs_1_2_7; // @[Mux.scala:30:73, :32:36] reg [23:0] mask_1; // @[ISLIP.scala:17:25] wire [23:0] _full_T_1 = {_in_vc_sel_T_121, _in_vc_sel_T_116, _in_vc_sel_T_111, _in_vc_sel_T_106, _in_vc_sel_T_101, _in_vc_sel_T_96, _in_vc_sel_T_91, _in_vc_sel_T_86, _in_vc_sel_T_82, _in_vc_sel_T_77, _in_vc_sel_T_72, _in_vc_sel_T_67, _in_vc_sel_T_62, _in_vc_sel_T_57, _in_vc_sel_T_52, _in_vc_sel_T_47, _in_vc_sel_T_42, _in_vc_sel_T_37, _in_vc_sel_T_32, _in_vc_sel_T_27, _in_vc_sel_T_22, _in_vc_sel_T_17, _in_vc_sel_T_12, 1'h0} & ~mask_1; // @[Mux.scala:30:73] wire [47:0] oh = _full_T_1[0] ? 48'h1 : _full_T_1[1] ? 48'h2 : _full_T_1[2] ? 48'h4 : _full_T_1[3] ? 48'h8 : _full_T_1[4] ? 48'h10 : _full_T_1[5] ? 48'h20 : _full_T_1[6] ? 48'h40 : _full_T_1[7] ? 48'h80 : _full_T_1[8] ? 48'h100 : _full_T_1[9] ? 48'h200 : _full_T_1[10] ? 48'h400 : _full_T_1[11] ? 48'h800 : _full_T_1[12] ? 48'h1000 : _full_T_1[13] ? 48'h2000 : _full_T_1[14] ? 48'h4000 : _full_T_1[15] ? 48'h8000 : _full_T_1[16] ? 48'h10000 : _full_T_1[17] ? 48'h20000 : _full_T_1[18] ? 48'h40000 : _full_T_1[19] ? 48'h80000 : _full_T_1[20] ? 48'h100000 : _full_T_1[21] ? 48'h200000 : _full_T_1[22] ? 48'h400000 : _full_T_1[23] ? 48'h800000 : _in_vc_sel_T_12 ? 48'h2000000 : _in_vc_sel_T_17 ? 48'h4000000 : _in_vc_sel_T_22 ? 48'h8000000 : _in_vc_sel_T_27 ? 48'h10000000 : _in_vc_sel_T_32 ? 48'h20000000 : _in_vc_sel_T_37 ? 48'h40000000 : _in_vc_sel_T_42 ? 48'h80000000 : _in_vc_sel_T_47 ? 48'h100000000 : _in_vc_sel_T_52 ? 48'h200000000 : _in_vc_sel_T_57 ? 48'h400000000 : _in_vc_sel_T_62 ? 48'h800000000 : _in_vc_sel_T_67 ? 48'h1000000000 : _in_vc_sel_T_72 ? 48'h2000000000 : _in_vc_sel_T_77 ? 48'h4000000000 : _in_vc_sel_T_82 ? 48'h8000000000 : _in_vc_sel_T_86 ? 48'h10000000000 : _in_vc_sel_T_91 ? 48'h20000000000 : _in_vc_sel_T_96 ? 48'h40000000000 : _in_vc_sel_T_101 ? 48'h80000000000 : _in_vc_sel_T_106 ? 48'h100000000000 : _in_vc_sel_T_111 ? 48'h200000000000 : _in_vc_sel_T_116 ? 48'h400000000000 : {_in_vc_sel_T_121, 47'h0}; // @[OneHot.scala:85:71] wire [23:0] sel = oh[23:0] \| oh[47:24]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[16]; // @[package.scala:81:59] wire in_alloc_2_1 = _GEN & sel[17]; // @[package.scala:81:59] wire in_alloc_2_2 = _GEN & sel[18]; // @[package.scala:81:59] wire in_alloc_2_3 = _GEN & sel[19]; // @[package.scala:81:59] wire in_alloc_2_4 = _GEN & sel[20]; // @[package.scala:81:59] wire in_alloc_2_5 = _GEN & sel[21]; // @[package.scala:81:59] wire in_alloc_2_6 = _GEN & sel[22]; // @[package.scala:81:59] wire in_alloc_2_7 = _GEN & sel[23]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[9]; // @[package.scala:81:59] wire in_alloc_1_2 = _GEN & sel[10]; // @[package.scala:81:59] wire in_alloc_1_3 = _GEN & sel[11]; // @[package.scala:81:59] wire in_alloc_1_4 = _GEN & sel[12]; // @[package.scala:81:59] wire in_alloc_1_5 = _GEN & sel[13]; // @[package.scala:81:59] wire in_alloc_1_6 = _GEN & sel[14]; // @[package.scala:81:59] wire in_alloc_1_7 = _GEN & sel[15]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_6 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_0_7 = _GEN & sel[7]; // @[package.scala:81:59]
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem : input clock : Clock input reset : Reset output auto : { } inst buffer of TLBuffer_10 connect buffer.clock, clock connect buffer.reset, reset inst shrinker of TLSourceShrinker connect shrinker.clock, clock connect shrinker.reset, reset inst widget of TLWidthWidget8_10 connect widget.clock, clock connect widget.reset, reset	module TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset // @[LazyModuleImp.scala:138:7] ); TLBuffer_10 buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset) ); // @[Buffer.scala:75:28] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module SourceD : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<64>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip bs_rdat : { data : UInt<64>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_wdat : { data : UInt<64>}, flip evict_req : { set : UInt<10>, way : UInt<3>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<10>, way : UInt<3>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<1> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<1>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<3>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 2, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node _s1_mask_T = not(s1_bypass) node s1_mask = and(UInt<1>(0h1), _s1_mask_T) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 3) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 3) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid \|\| queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<3>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<1>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<8>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0)) node _T_19 = and(io.rel_pop.valid, _T_18) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_20 = and(s2_valid, s3_ready) when _T_20 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_21 = eq(s3_ready, UInt<1>(0h0)) node _T_22 = and(s2_valid, _T_21) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<3>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<1>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_2 = bits(queue.io.deq.bits.data, 63, 0) node s3_rdata = mux(_s3_rdata_T, _s3_rdata_T_1, _s3_rdata_T_2) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_23 = eq(s3_full, UInt<1>(0h0)) node _T_24 = eq(s3_need_r, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = or(_T_25, queue.io.deq.valid) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid)\n") : printf_1 assert(clock, _T_26, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_30 = and(s3_valid, s4_ready) when _T_30 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_31 = eq(s4_ready, UInt<1>(0h0)) node _T_32 = and(s3_valid, _T_31) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<3>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<64>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_9 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_10 = or(_io_bs_wadr_bits_mask_T_9, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_11 = or(_io_bs_wadr_bits_mask_T_10, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_12 = or(_io_bs_wadr_bits_mask_T_11, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_13 = or(_io_bs_wadr_bits_mask_T_12, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_14 = or(_io_bs_wadr_bits_mask_T_13, _io_bs_wadr_bits_mask_T_7) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_14 connect io.bs_wdat.data, atomics.io.data_out node _T_33 = and(s4_full, s4_need_pb) node _T_34 = and(_T_33, s4_pdata.corrupt) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_40 = and(io.bs_wadr.valid, _T_39) node _T_41 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_42 = and(s4_req.prio[0], _T_41) node _T_43 = eq(s4_req.param, UInt<3>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_46 = and(s4_req.prio[0], _T_45) node _T_47 = eq(s4_req.param, UInt<3>(0h1)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_50 = and(s4_req.prio[0], _T_49) node _T_51 = eq(s4_req.param, UInt<3>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_54 = and(s4_req.prio[0], _T_53) node _T_55 = eq(s4_req.param, UInt<3>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_58 = and(s4_req.prio[0], _T_57) node _T_59 = eq(s4_req.param, UInt<3>(0h4)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_62 = and(s4_req.prio[0], _T_61) node _T_63 = eq(s4_req.param, UInt<3>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_66 = and(s4_req.prio[0], _T_65) node _T_67 = eq(s4_req.param, UInt<3>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_70 = and(s4_req.prio[0], _T_69) node _T_71 = eq(s4_req.param, UInt<3>(0h2)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_74 = and(s4_req.prio[0], _T_73) node _T_75 = eq(s4_req.param, UInt<3>(0h3)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(s4_need_bs, UInt<1>(0h0)) node _T_78 = or(io.bs_wadr.ready, _T_77) when _T_78 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<3>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<64>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<3>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<64>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<64>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<3>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 2, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass = mux(pre_s3_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<3>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 2, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass = mux(pre_s3_5_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<3>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 2, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass = mux(pre_s3_6_match, UInt<1>(0h1), UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_2 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_3 = mux(_s3_bypass_data_T, _s3_bypass_data_T_1, _s3_bypass_data_T_2) node _s3_bypass_data_T_4 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_5 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_6 = bits(_s3_bypass_data_T_3, 63, 0) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_4, _s3_bypass_data_T_5, _s3_bypass_data_T_6) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_7 node _s3_bypass_data_T_8 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_9 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_10 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_11 = mux(_s3_bypass_data_T_8, _s3_bypass_data_T_9, _s3_bypass_data_T_10) connect s3_bypass_data, _s3_bypass_data_T_11 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_79 = and(io.req.valid, s2) node _T_80 = and(_T_79, s3) node _T_81 = and(_T_80, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_82 = and(io.req.valid, s2_1) node _T_83 = and(_T_82, s3_1) node _T_84 = and(_T_83, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_85 = and(io.req.valid, s2_2) node _T_86 = and(_T_85, s3_2) node _T_87 = and(_T_86, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_88 = and(io.req.valid, s2_3) node _T_89 = and(_T_88, s3_3) node _T_90 = and(_T_89, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_91 = and(io.req.valid, s2_4) node _T_92 = and(_T_91, s3_4) node _T_93 = and(_T_92, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_94 = and(io.req.valid, s2_5) node _T_95 = and(_T_94, s3_5) node _T_96 = and(_T_95, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_97 = and(io.req.valid, s2_6) node _T_98 = and(_T_97, s3_6) node _T_99 = and(_T_98, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_100 = and(io.req.valid, s2_7) node _T_101 = and(_T_100, s3_7) node _T_102 = and(_T_101, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<3>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 2, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass = mux(s1_2_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<3>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 2, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass = mux(s1_3_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<3>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 2, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass = mux(s1_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22	module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [63:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [7:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [63:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [63:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [63:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [7:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [63:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [7:0] _s2_pdata_raw_mask_T = 8'hFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [63:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [2:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [63:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [63:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [2:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [2:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:3]; // @[package.scala:243:46] wire [2:0] s1_beats1 = s1_single ? 3'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [2:0] _s1_beat_T = s1_req_offset[5:3]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 3'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [3:0] _s1_counter_T = {1'h0, s1_counter} + 4'h1; // @[SourceD.scala:86:27, :130:30] wire [2:0] _s1_counter_T_1 = _s1_counter_T[2:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [2:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [63:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [7:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [63:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [7:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [63:0] s2_pdata_r_data; // @[package.scala:88:63] reg [7:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [63:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [7:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 8'hFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [2:0] s3_beat; // @[SourceD.scala:192:26] wire [2:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [63:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [7:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [63:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [63:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [63:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [63:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [2:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [2:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [63:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [7:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [63:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_9 = _io_bs_wadr_bits_mask_T_8 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_10 = _io_bs_wadr_bits_mask_T_9 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_11 = _io_bs_wadr_bits_mask_T_10 \| _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_12 = _io_bs_wadr_bits_mask_T_11 \| _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_13 = _io_bs_wadr_bits_mask_T_12 \| _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_14 = _io_bs_wadr_bits_mask_T_13 \| _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:48:7, :275:87]
Generate the Verilog code corresponding to this FIRRTL code module PE_323 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_67 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_323( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_67 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_163 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_163( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_17 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}}, resp : { `3` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `2` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2]}} regreset mask : UInt<4>, clock, reset, UInt<4>(0h0) wire in_arb_reqs : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}[4] wire in_arb_vals : UInt<1>[4] node in_arb_filter_lo = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo) node in_arb_filter_lo_1 = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6) node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_12, UInt<8>(0h80), UInt<8>(0h0)) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_11, UInt<8>(0h40), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_10, UInt<8>(0h20), _in_arb_filter_T_14) node _in_arb_filter_T_16 = mux(_in_arb_filter_T_9, UInt<8>(0h10), _in_arb_filter_T_15) node _in_arb_filter_T_17 = mux(_in_arb_filter_T_8, UInt<8>(0h8), _in_arb_filter_T_16) node _in_arb_filter_T_18 = mux(_in_arb_filter_T_7, UInt<8>(0h4), _in_arb_filter_T_17) node _in_arb_filter_T_19 = mux(_in_arb_filter_T_6, UInt<8>(0h2), _in_arb_filter_T_18) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<8>(0h1), _in_arb_filter_T_19) node _in_arb_sel_T = bits(in_arb_filter, 3, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 4) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) node _T_2 = or(_T_1, in_arb_vals[3]) when _T_2 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = not(UInt<4>(0h0)) node _mask_T_4 = bits(in_arb_sel, 0, 0) node _mask_T_5 = bits(in_arb_sel, 1, 1) node _mask_T_6 = bits(in_arb_sel, 2, 2) node _mask_T_7 = bits(in_arb_sel, 3, 3) node _mask_T_8 = mux(_mask_T_4, _mask_T, UInt<1>(0h0)) node _mask_T_9 = mux(_mask_T_5, _mask_T_1, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_6, _mask_T_2, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_7, _mask_T_3, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_8, _mask_T_9) node _mask_T_13 = or(_mask_T_12, _mask_T_10) node _mask_T_14 = or(_mask_T_13, _mask_T_11) wire _mask_WIRE : UInt<4> connect _mask_WIRE, _mask_T_14 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T) connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T, _in_arb_vals_0_T_1) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`2`[0]) node _in_arb_vals_0_T_4 = and(io.req.`0`.valid, _in_arb_vals_0_T_3) connect in_arb_vals[0], _in_arb_vals_0_T_4 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T) connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T, _in_arb_vals_1_T_1) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`2`[0]) node _in_arb_vals_1_T_4 = and(io.req.`1`.valid, _in_arb_vals_1_T_3) connect in_arb_vals[1], _in_arb_vals_1_T_4 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T) connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T, _in_arb_vals_2_T_1) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`2`[0]) node _in_arb_vals_2_T_4 = and(io.req.`2`.valid, _in_arb_vals_2_T_3) connect in_arb_vals[2], _in_arb_vals_2_T_4 node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T) connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1 node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T) connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1 node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T) connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1 node _in_arb_reqs_3_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_1_T_1 = and(io.req.`3`.bits.vc_sel.`1`[1], _in_arb_reqs_3_1_1_T) connect in_arb_reqs[3].`1`[1], _in_arb_reqs_3_1_1_T_1 node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T) connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1 node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1]) node _in_arb_vals_3_T_1 = or(in_arb_reqs[3].`1`[0], in_arb_reqs[3].`1`[1]) node _in_arb_vals_3_T_2 = or(_in_arb_vals_3_T, _in_arb_vals_3_T_1) node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`2`[0]) node _in_arb_vals_3_T_4 = and(io.req.`3`.valid, _in_arb_vals_3_T_3) connect in_arb_vals[3], _in_arb_vals_3_T_4 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h0) wire in_alloc : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) node _in_flow_T_3 = bits(in_arb_sel, 3, 3) wire in_flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _in_flow_T_4 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_7 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_8 = or(_in_flow_T_4, _in_flow_T_5) node _in_flow_T_9 = or(_in_flow_T_8, _in_flow_T_6) node _in_flow_T_10 = or(_in_flow_T_9, _in_flow_T_7) wire _in_flow_WIRE : UInt<2> connect _in_flow_WIRE, _in_flow_T_10 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_11 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_12 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_13 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_15 = or(_in_flow_T_11, _in_flow_T_12) node _in_flow_T_16 = or(_in_flow_T_15, _in_flow_T_13) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_14) wire _in_flow_WIRE_1 : UInt<4> connect _in_flow_WIRE_1, _in_flow_T_17 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_21 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_22 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_23 = or(_in_flow_T_22, _in_flow_T_20) node _in_flow_T_24 = or(_in_flow_T_23, _in_flow_T_21) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_24 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_25 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_26 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_27 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_28 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_29 = or(_in_flow_T_25, _in_flow_T_26) node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_27) node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_28) wire _in_flow_WIRE_3 : UInt<4> connect _in_flow_WIRE_3, _in_flow_T_31 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_32 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_33 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_34 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_35 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_36 = or(_in_flow_T_32, _in_flow_T_33) node _in_flow_T_37 = or(_in_flow_T_36, _in_flow_T_34) node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_35) wire _in_flow_WIRE_4 : UInt<1> connect _in_flow_WIRE_4, _in_flow_T_38 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = bits(in_arb_sel, 3, 3) node _in_vc_T_4 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_7 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_8 = or(_in_vc_T_4, _in_vc_T_5) node _in_vc_T_9 = or(_in_vc_T_8, _in_vc_T_6) node _in_vc_T_10 = or(_in_vc_T_9, _in_vc_T_7) wire in_vc : UInt<1> connect in_vc, _in_vc_T_10 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3) wire in_vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _in_vc_sel_WIRE : UInt<1>[2] node _in_vc_sel_T_4 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_7 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_8 = or(_in_vc_sel_T_4, _in_vc_sel_T_5) node _in_vc_sel_T_9 = or(_in_vc_sel_T_8, _in_vc_sel_T_6) node _in_vc_sel_T_10 = or(_in_vc_sel_T_9, _in_vc_sel_T_7) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_10 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_11 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_12 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_13 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_15 = or(_in_vc_sel_T_11, _in_vc_sel_T_12) node _in_vc_sel_T_16 = or(_in_vc_sel_T_15, _in_vc_sel_T_13) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_14) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_3 : UInt<1>[2] node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_21 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_22 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_23 = or(_in_vc_sel_T_22, _in_vc_sel_T_20) node _in_vc_sel_T_24 = or(_in_vc_sel_T_23, _in_vc_sel_T_21) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_24 connect _in_vc_sel_WIRE_3[0], _in_vc_sel_WIRE_4 node _in_vc_sel_T_25 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_26 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_27 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_28 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_29 = or(_in_vc_sel_T_25, _in_vc_sel_T_26) node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_27) node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_28) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_31 connect _in_vc_sel_WIRE_3[1], _in_vc_sel_WIRE_5 connect in_vc_sel.`1`, _in_vc_sel_WIRE_3 wire _in_vc_sel_WIRE_6 : UInt<1>[1] node _in_vc_sel_T_32 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_33 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_32, _in_vc_sel_T_33) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_34) node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_38 connect _in_vc_sel_WIRE_6[0], _in_vc_sel_WIRE_7 connect in_vc_sel.`2`, _in_vc_sel_WIRE_6 node _T_3 = or(in_arb_vals[0], in_arb_vals[1]) node _T_4 = or(_T_3, in_arb_vals[2]) node _T_5 = or(_T_4, in_arb_vals[3]) node hi = bits(in_arb_sel, 3, 2) node lo = bits(in_arb_sel, 1, 0) node _T_6 = orr(hi) node _T_7 = or(hi, lo) node _T_8 = bits(_T_7, 1, 1) node _T_9 = cat(_T_6, _T_8) node _T_10 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_11 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_12 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_13 = and(io.req.`3`.ready, io.req.`3`.valid) node _T_14 = or(_T_10, _T_11) node _T_15 = or(_T_14, _T_12) node _T_16 = or(_T_15, _T_13) node _T_17 = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node _T_18 = cat(in_vc_sel.`1`[1], in_vc_sel.`1`[0]) node hi_1 = cat(in_vc_sel.`2`[0], _T_18) node _T_19 = cat(hi_1, _T_17) regreset mask_1 : UInt<5>, clock, reset, UInt<5>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_19, _full_T) node full = cat(_T_19, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = mux(_oh_T_9, UInt<10>(0h200), UInt<10>(0h0)) node _oh_T_11 = mux(_oh_T_8, UInt<10>(0h100), _oh_T_10) node _oh_T_12 = mux(_oh_T_7, UInt<10>(0h80), _oh_T_11) node _oh_T_13 = mux(_oh_T_6, UInt<10>(0h40), _oh_T_12) node _oh_T_14 = mux(_oh_T_5, UInt<10>(0h20), _oh_T_13) node _oh_T_15 = mux(_oh_T_4, UInt<10>(0h10), _oh_T_14) node _oh_T_16 = mux(_oh_T_3, UInt<10>(0h8), _oh_T_15) node _oh_T_17 = mux(_oh_T_2, UInt<10>(0h4), _oh_T_16) node _oh_T_18 = mux(_oh_T_1, UInt<10>(0h2), _oh_T_17) node oh = mux(_oh_T, UInt<10>(0h1), _oh_T_18) node _sel_T = bits(oh, 4, 0) node _sel_T_1 = shr(oh, 5) node sel = or(_sel_T, _sel_T_1) when _T_16 : node _mask_T_15 = bits(sel, 0, 0) node _mask_T_16 = not(UInt<1>(0h0)) node _mask_T_17 = bits(sel, 1, 1) node _mask_T_18 = not(UInt<2>(0h0)) node _mask_T_19 = bits(sel, 2, 2) node _mask_T_20 = not(UInt<3>(0h0)) node _mask_T_21 = bits(sel, 3, 3) node _mask_T_22 = not(UInt<4>(0h0)) node _mask_T_23 = bits(sel, 4, 4) node _mask_T_24 = not(UInt<5>(0h0)) node _mask_T_25 = mux(_mask_T_23, _mask_T_24, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_21, _mask_T_22, _mask_T_25) node _mask_T_27 = mux(_mask_T_19, _mask_T_20, _mask_T_26) node _mask_T_28 = mux(_mask_T_17, _mask_T_18, _mask_T_27) node _mask_T_29 = mux(_mask_T_15, _mask_T_16, _mask_T_28) connect mask_1, _mask_T_29 wire _WIRE : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _WIRE_1 : UInt<5> connect _WIRE_1, sel node _T_20 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_20 node _T_21 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_21 node _T_22 = bits(_WIRE_1, 2, 2) connect _WIRE.`1`[0], _T_22 node _T_23 = bits(_WIRE_1, 3, 3) connect _WIRE.`1`[1], _T_23 node _T_24 = bits(_WIRE_1, 4, 4) connect _WIRE.`2`[0], _T_24 wire _WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`1`[1], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) node _T_25 = mux(_T_5, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_25.`0` connect in_alloc.`1`, _T_25.`1` connect in_alloc.`2`, _T_25.`2` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_26 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node _T_27 = cat(io.resp.`0`.vc_sel.`1`[1], io.resp.`0`.vc_sel.`1`[0]) node hi_2 = cat(io.resp.`0`.vc_sel.`2`[0], _T_27) node _T_28 = cat(hi_2, _T_26) node _T_29 = bits(_T_28, 0, 0) node _T_30 = bits(_T_28, 1, 1) node _T_31 = bits(_T_28, 2, 2) node _T_32 = bits(_T_28, 3, 3) node _T_33 = bits(_T_28, 4, 4) node _T_34 = add(_T_29, _T_30) node _T_35 = bits(_T_34, 1, 0) node _T_36 = add(_T_32, _T_33) node _T_37 = bits(_T_36, 1, 0) node _T_38 = add(_T_31, _T_37) node _T_39 = bits(_T_38, 1, 0) node _T_40 = add(_T_35, _T_39) node _T_41 = bits(_T_40, 2, 0) node _T_42 = leq(_T_41, UInt<1>(0h1)) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_42, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_46 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node _T_47 = cat(io.resp.`1`.vc_sel.`1`[1], io.resp.`1`.vc_sel.`1`[0]) node hi_3 = cat(io.resp.`1`.vc_sel.`2`[0], _T_47) node _T_48 = cat(hi_3, _T_46) node _T_49 = bits(_T_48, 0, 0) node _T_50 = bits(_T_48, 1, 1) node _T_51 = bits(_T_48, 2, 2) node _T_52 = bits(_T_48, 3, 3) node _T_53 = bits(_T_48, 4, 4) node _T_54 = add(_T_49, _T_50) node _T_55 = bits(_T_54, 1, 0) node _T_56 = add(_T_52, _T_53) node _T_57 = bits(_T_56, 1, 0) node _T_58 = add(_T_51, _T_57) node _T_59 = bits(_T_58, 1, 0) node _T_60 = add(_T_55, _T_59) node _T_61 = bits(_T_60, 2, 0) node _T_62 = leq(_T_61, UInt<1>(0h1)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_62, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_66 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node _T_67 = cat(io.resp.`2`.vc_sel.`1`[1], io.resp.`2`.vc_sel.`1`[0]) node hi_4 = cat(io.resp.`2`.vc_sel.`2`[0], _T_67) node _T_68 = cat(hi_4, _T_66) node _T_69 = bits(_T_68, 0, 0) node _T_70 = bits(_T_68, 1, 1) node _T_71 = bits(_T_68, 2, 2) node _T_72 = bits(_T_68, 3, 3) node _T_73 = bits(_T_68, 4, 4) node _T_74 = add(_T_69, _T_70) node _T_75 = bits(_T_74, 1, 0) node _T_76 = add(_T_72, _T_73) node _T_77 = bits(_T_76, 1, 0) node _T_78 = add(_T_71, _T_77) node _T_79 = bits(_T_78, 1, 0) node _T_80 = add(_T_75, _T_79) node _T_81 = bits(_T_80, 2, 0) node _T_82 = leq(_T_81, UInt<1>(0h1)) node _T_83 = asUInt(reset) node _T_84 = eq(_T_83, UInt<1>(0h0)) when _T_84 : node _T_85 = eq(_T_82, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_82, UInt<1>(0h1), "") : assert_2 node _io_req_3_ready_T = bits(in_arb_sel, 3, 3) connect io.req.`3`.ready, _io_req_3_ready_T connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`3`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_86 = cat(io.resp.`3`.vc_sel.`0`[1], io.resp.`3`.vc_sel.`0`[0]) node _T_87 = cat(io.resp.`3`.vc_sel.`1`[1], io.resp.`3`.vc_sel.`1`[0]) node hi_5 = cat(io.resp.`3`.vc_sel.`2`[0], _T_87) node _T_88 = cat(hi_5, _T_86) node _T_89 = bits(_T_88, 0, 0) node _T_90 = bits(_T_88, 1, 1) node _T_91 = bits(_T_88, 2, 2) node _T_92 = bits(_T_88, 3, 3) node _T_93 = bits(_T_88, 4, 4) node _T_94 = add(_T_89, _T_90) node _T_95 = bits(_T_94, 1, 0) node _T_96 = add(_T_92, _T_93) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_91, _T_97) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_95, _T_99) node _T_101 = bits(_T_100, 2, 0) node _T_102 = leq(_T_101, UInt<1>(0h1)) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1] connect io.out_allocs.`1`[1].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow	module RotatingSingleVCAllocator_17( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_0_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [3:0] mask; // @[SingleVCAllocator.scala:16:21] wire [3:0] _in_arb_filter_T_3 = {in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : in_arb_vals_1 ? 8'h20 : in_arb_vals_2 ? 8'h40 : {in_arb_vals_3, 7'h0}; // @[OneHot.scala:85:71] wire [3:0] in_arb_sel = in_arb_filter[3:0] \| in_arb_filter[7:4]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 \| in_arb_vals_1 \| in_arb_vals_2 \| in_arb_vals_3; // @[package.scala:81:59] wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 \| io_req_0_bits_vc_sel_0_1 \| in_arb_reqs_0_1_0 \| io_req_0_bits_vc_sel_1_1 \| in_arb_reqs_0_2_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 \| io_req_1_bits_vc_sel_0_1 \| in_arb_reqs_1_1_0 \| io_req_1_bits_vc_sel_1_1 \| in_arb_reqs_1_2_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 \| io_req_2_bits_vc_sel_0_1 \| in_arb_reqs_2_1_0 \| io_req_2_bits_vc_sel_1_1 \| in_arb_reqs_2_2_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 \| io_req_3_bits_vc_sel_0_1 \| in_arb_reqs_3_1_0 \| io_req_3_bits_vc_sel_1_1 \| in_arb_reqs_3_2_0); // @[package.scala:81:59] wire _in_vc_sel_T_10 = in_arb_sel[0] & in_arb_reqs_0_0_0 \| in_arb_sel[1] & in_arb_reqs_1_0_0 \| in_arb_sel[2] & in_arb_reqs_2_0_0 \| in_arb_sel[3] & in_arb_reqs_3_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_17 = in_arb_sel[0] & io_req_0_bits_vc_sel_0_1 \| in_arb_sel[1] & io_req_1_bits_vc_sel_0_1 \| in_arb_sel[2] & io_req_2_bits_vc_sel_0_1 \| in_arb_sel[3] & io_req_3_bits_vc_sel_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_24 = in_arb_sel[0] & in_arb_reqs_0_1_0 \| in_arb_sel[1] & in_arb_reqs_1_1_0 \| in_arb_sel[2] & in_arb_reqs_2_1_0 \| in_arb_sel[3] & in_arb_reqs_3_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & io_req_0_bits_vc_sel_1_1 \| in_arb_sel[1] & io_req_1_bits_vc_sel_1_1 \| in_arb_sel[2] & io_req_2_bits_vc_sel_1_1 \| in_arb_sel[3] & io_req_3_bits_vc_sel_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_38 = in_arb_sel[0] & in_arb_reqs_0_2_0 \| in_arb_sel[1] & in_arb_reqs_1_2_0 \| in_arb_sel[2] & in_arb_reqs_2_2_0 \| in_arb_sel[3] & in_arb_reqs_3_2_0; // @[Mux.scala:30:73, :32:36] reg [4:0] mask_1; // @[ISLIP.scala:17:25] wire [4:0] _full_T_1 = {_in_vc_sel_T_38, _in_vc_sel_T_31, _in_vc_sel_T_24, _in_vc_sel_T_17, _in_vc_sel_T_10} & ~mask_1; // @[Mux.scala:30:73] wire [9:0] oh = _full_T_1[0] ? 10'h1 : _full_T_1[1] ? 10'h2 : _full_T_1[2] ? 10'h4 : _full_T_1[3] ? 10'h8 : _full_T_1[4] ? 10'h10 : _in_vc_sel_T_10 ? 10'h20 : _in_vc_sel_T_17 ? 10'h40 : _in_vc_sel_T_24 ? 10'h80 : _in_vc_sel_T_31 ? 10'h100 : {_in_vc_sel_T_38, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] sel = oh[4:0] \| oh[9:5]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
Generate the Verilog code corresponding to this FIRRTL code module PE_373 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_117 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_373( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_117 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_8 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_101 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_102 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_8( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_101 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_102 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_PutBufferCEntry_q2_e8 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<1>, data : { data : UInt<128>, corrupt : UInt<1>}}}, valid : UInt<2>, flip pop : { valid : UInt<1>, bits : UInt<1>}, data : { data : UInt<128>, corrupt : UInt<1>}} regreset valid : UInt<2>, clock, reset, UInt<2>(0h0) cmem head : UInt<3> [2] cmem tail : UInt<3> [2] regreset used : UInt<8>, clock, reset, UInt<8>(0h0) cmem next : UInt<3> [8] cmem data : { data : UInt<128>, corrupt : UInt<1>} [8] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 7, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 7, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 7, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = bits(_freeOH_T_9, 7, 0) node _freeOH_T_11 = shl(_freeOH_T_10, 1) node _freeOH_T_12 = not(_freeOH_T_11) node _freeOH_T_13 = not(used) node freeOH = and(_freeOH_T_12, _freeOH_T_13) node freeIdx_hi = bits(freeOH, 8, 8) node freeIdx_lo = bits(freeOH, 7, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 7, 4) node freeIdx_lo_1 = bits(_freeIdx_T_1, 3, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 3, 2) node freeIdx_lo_2 = bits(_freeIdx_T_3, 1, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node _freeIdx_T_6 = bits(_freeIdx_T_5, 1, 1) node _freeIdx_T_7 = cat(_freeIdx_T_4, _freeIdx_T_6) node _freeIdx_T_8 = cat(_freeIdx_T_2, _freeIdx_T_7) node freeIdx = cat(_freeIdx_T, _freeIdx_T_8) wire valid_set : UInt<2> connect valid_set, UInt<2>(0h0) wire valid_clr : UInt<2> connect valid_clr, UInt<2>(0h0) wire used_set : UInt<8> connect used_set, UInt<8>(0h0) wire used_clr : UInt<8> connect used_clr, UInt<8>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 0, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 1, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH node _T_1 = bits(freeIdx, 2, 0) write mport MPORT = data[_T_1], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_2 = eq(io.pop.valid, UInt<1>(0h0)) node _T_3 = dshr(io.valid, io.pop.bits) node _T_4 = bits(_T_3, 0, 0) node _T_5 = or(_T_2, _T_4) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire \|\| (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_5, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 2, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 7, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_9 = eq(pop_head, MPORT_4) when _T_9 : node valid_clr_shiftAmount = bits(io.pop.bits, 0, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 1, 0) connect valid_clr, _valid_clr_T_1 node _T_10 = and(io.push.ready, io.push.valid) node _T_11 = and(_T_10, push_valid) node _T_12 = eq(push_tail, pop_head) node _T_13 = and(_T_11, _T_12) read mport MPORT_5 = next[pop_head], clock node _T_14 = mux(_T_13, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_14 node _T_15 = eq(io.pop.valid, UInt<1>(0h0)) node _T_16 = or(UInt<1>(0h1), _T_15) node _T_17 = or(_T_16, pop_valid) when _T_17 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2	module ListBuffer_PutBufferCEntry_q2_e8( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input io_push_bits_index, // @[ListBuffer.scala:39:14] input [127:0] io_push_bits_data_data, // @[ListBuffer.scala:39:14] input io_push_bits_data_corrupt, // @[ListBuffer.scala:39:14] output [1:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input io_pop_bits, // @[ListBuffer.scala:39:14] output [127:0] io_data_data, // @[ListBuffer.scala:39:14] output io_data_corrupt // @[ListBuffer.scala:39:14] ); wire [128:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [2:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [2:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [2:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [2:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] reg [1:0] valid; // @[ListBuffer.scala:47:22] reg [7:0] used; // @[ListBuffer.scala:50:22] wire [7:0] _freeOH_T_13 = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [6:0] _freeOH_T_3 = _freeOH_T_13[6:0] \| {_freeOH_T_13[5:0], 1'h0}; // @[package.scala:253:{43,53}] wire [6:0] _freeOH_T_6 = _freeOH_T_3 \| {_freeOH_T_3[4:0], 2'h0}; // @[package.scala:253:{43,53}] wire [7:0] freeIdx_lo = {~(_freeOH_T_6 \| {_freeOH_T_6[2:0], 4'h0}), 1'h1} & _freeOH_T_13; // @[package.scala:253:{43,53}] wire [2:0] _freeIdx_T_3 = freeIdx_lo[7:5] \| freeIdx_lo[3:1]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_5 = _freeIdx_T_3[2] \| _freeIdx_T_3[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] _GEN = {1'h0, io_push_bits_index}; // @[ListBuffer.scala:63:25] wire [1:0] _push_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :63:25] wire io_push_ready_0 = used != 8'hFF; // @[ListBuffer.scala:50:22, :65:26] wire data_MPORT_en = io_push_ready_0 & io_push_valid; // @[Decoupled.scala:51:35] wire [2:0] data_MPORT_addr = {\|(freeIdx_lo[7:4]), \|(_freeIdx_T_3[2:1]), _freeIdx_T_5}; // @[OneHot.scala:30:18, :32:{14,28}] wire [1:0] _GEN_0 = {1'h0, io_pop_bits}; // @[ListBuffer.scala:86:37]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_30 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_282 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_283 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_284 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_30( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_282 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_283 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_284 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_45 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_45 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_45( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_45 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_66 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_139 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_140 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_66( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s11k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_22 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s11k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s11k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_46 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_47 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a26d64s11k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [10:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_22 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s11k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s11k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_17 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_24 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_17( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_24 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_12 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_12( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceA_3 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} wire a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} inst io_a_q of Queue2_TLBundleA_a32d64s4k3z3c_3 connect io_a_q.clock, clock connect io_a_q.reset, reset connect io_a_q.io.enq.valid, a.valid connect io_a_q.io.enq.bits.corrupt, a.bits.corrupt connect io_a_q.io.enq.bits.data, a.bits.data connect io_a_q.io.enq.bits.mask, a.bits.mask connect io_a_q.io.enq.bits.address, a.bits.address connect io_a_q.io.enq.bits.source, a.bits.source connect io_a_q.io.enq.bits.size, a.bits.size connect io_a_q.io.enq.bits.param, a.bits.param connect io_a_q.io.enq.bits.opcode, a.bits.opcode connect a.ready, io_a_q.io.enq.ready connect io.a.bits, io_a_q.io.deq.bits connect io.a.valid, io_a_q.io.deq.valid connect io_a_q.io.deq.ready, io.a.ready connect io.req.ready, a.ready connect a.valid, io.req.valid node _T = eq(a.ready, UInt<1>(0h0)) node _T_1 = and(a.valid, _T) node _a_bits_opcode_T = mux(io.req.bits.block, UInt<3>(0h6), UInt<3>(0h7)) connect a.bits.opcode, _a_bits_opcode_T connect a.bits.param, io.req.bits.param connect a.bits.size, UInt<3>(0h6) connect a.bits.source, io.req.bits.source node a_bits_address_base_y = or(io.req.bits.tag, UInt<9>(0h0)) node _a_bits_address_base_T = shr(a_bits_address_base_y, 9) node _a_bits_address_base_T_1 = eq(_a_bits_address_base_T, UInt<1>(0h0)) node _a_bits_address_base_T_2 = asUInt(reset) node _a_bits_address_base_T_3 = eq(_a_bits_address_base_T_2, UInt<1>(0h0)) when _a_bits_address_base_T_3 : node _a_bits_address_base_T_4 = eq(_a_bits_address_base_T_1, UInt<1>(0h0)) when _a_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf assert(clock, _a_bits_address_base_T_1, UInt<1>(0h1), "") : a_bits_address_base_assert node _a_bits_address_base_T_5 = bits(a_bits_address_base_y, 8, 0) node a_bits_address_base_y_1 = or(io.req.bits.set, UInt<11>(0h0)) node _a_bits_address_base_T_6 = shr(a_bits_address_base_y_1, 11) node _a_bits_address_base_T_7 = eq(_a_bits_address_base_T_6, UInt<1>(0h0)) node _a_bits_address_base_T_8 = asUInt(reset) node _a_bits_address_base_T_9 = eq(_a_bits_address_base_T_8, UInt<1>(0h0)) when _a_bits_address_base_T_9 : node _a_bits_address_base_T_10 = eq(_a_bits_address_base_T_7, UInt<1>(0h0)) when _a_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf_1 assert(clock, _a_bits_address_base_T_7, UInt<1>(0h1), "") : a_bits_address_base_assert_1 node _a_bits_address_base_T_11 = bits(a_bits_address_base_y_1, 10, 0) node a_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _a_bits_address_base_T_12 = shr(a_bits_address_base_y_2, 6) node _a_bits_address_base_T_13 = eq(_a_bits_address_base_T_12, UInt<1>(0h0)) node _a_bits_address_base_T_14 = asUInt(reset) node _a_bits_address_base_T_15 = eq(_a_bits_address_base_T_14, UInt<1>(0h0)) when _a_bits_address_base_T_15 : node _a_bits_address_base_T_16 = eq(_a_bits_address_base_T_13, UInt<1>(0h0)) when _a_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf_2 assert(clock, _a_bits_address_base_T_13, UInt<1>(0h1), "") : a_bits_address_base_assert_2 node _a_bits_address_base_T_17 = bits(a_bits_address_base_y_2, 5, 0) node a_bits_address_base_hi = cat(_a_bits_address_base_T_5, _a_bits_address_base_T_11) node a_bits_address_base = cat(a_bits_address_base_hi, _a_bits_address_base_T_17) node _a_bits_address_T = bits(a_bits_address_base, 0, 0) node _a_bits_address_T_1 = bits(a_bits_address_base, 1, 1) node _a_bits_address_T_2 = bits(a_bits_address_base, 2, 2) node _a_bits_address_T_3 = bits(a_bits_address_base, 3, 3) node _a_bits_address_T_4 = bits(a_bits_address_base, 4, 4) node _a_bits_address_T_5 = bits(a_bits_address_base, 5, 5) node _a_bits_address_T_6 = bits(a_bits_address_base, 6, 6) node _a_bits_address_T_7 = bits(a_bits_address_base, 7, 7) node _a_bits_address_T_8 = bits(a_bits_address_base, 8, 8) node _a_bits_address_T_9 = bits(a_bits_address_base, 9, 9) node _a_bits_address_T_10 = bits(a_bits_address_base, 10, 10) node _a_bits_address_T_11 = bits(a_bits_address_base, 11, 11) node _a_bits_address_T_12 = bits(a_bits_address_base, 12, 12) node _a_bits_address_T_13 = bits(a_bits_address_base, 13, 13) node _a_bits_address_T_14 = bits(a_bits_address_base, 14, 14) node _a_bits_address_T_15 = bits(a_bits_address_base, 15, 15) node _a_bits_address_T_16 = bits(a_bits_address_base, 16, 16) node _a_bits_address_T_17 = bits(a_bits_address_base, 17, 17) node _a_bits_address_T_18 = bits(a_bits_address_base, 18, 18) node _a_bits_address_T_19 = bits(a_bits_address_base, 19, 19) node _a_bits_address_T_20 = bits(a_bits_address_base, 20, 20) node _a_bits_address_T_21 = bits(a_bits_address_base, 21, 21) node _a_bits_address_T_22 = bits(a_bits_address_base, 22, 22) node _a_bits_address_T_23 = bits(a_bits_address_base, 23, 23) node _a_bits_address_T_24 = bits(a_bits_address_base, 24, 24) node _a_bits_address_T_25 = bits(a_bits_address_base, 25, 25) node a_bits_address_lo_lo_lo_lo = cat(_a_bits_address_T_1, _a_bits_address_T) node a_bits_address_lo_lo_lo_hi = cat(_a_bits_address_T_3, _a_bits_address_T_2) node a_bits_address_lo_lo_lo = cat(a_bits_address_lo_lo_lo_hi, a_bits_address_lo_lo_lo_lo) node a_bits_address_lo_lo_hi_lo = cat(_a_bits_address_T_5, _a_bits_address_T_4) node a_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node a_bits_address_lo_lo_hi = cat(a_bits_address_lo_lo_hi_hi, a_bits_address_lo_lo_hi_lo) node a_bits_address_lo_lo = cat(a_bits_address_lo_lo_hi, a_bits_address_lo_lo_lo) node a_bits_address_lo_hi_lo_lo = cat(_a_bits_address_T_6, UInt<1>(0h0)) node a_bits_address_lo_hi_lo_hi = cat(_a_bits_address_T_8, _a_bits_address_T_7) node a_bits_address_lo_hi_lo = cat(a_bits_address_lo_hi_lo_hi, a_bits_address_lo_hi_lo_lo) node a_bits_address_lo_hi_hi_lo = cat(_a_bits_address_T_10, _a_bits_address_T_9) node a_bits_address_lo_hi_hi_hi = cat(_a_bits_address_T_12, _a_bits_address_T_11) node a_bits_address_lo_hi_hi = cat(a_bits_address_lo_hi_hi_hi, a_bits_address_lo_hi_hi_lo) node a_bits_address_lo_hi = cat(a_bits_address_lo_hi_hi, a_bits_address_lo_hi_lo) node a_bits_address_lo = cat(a_bits_address_lo_hi, a_bits_address_lo_lo) node a_bits_address_hi_lo_lo_lo = cat(_a_bits_address_T_14, _a_bits_address_T_13) node a_bits_address_hi_lo_lo_hi = cat(_a_bits_address_T_16, _a_bits_address_T_15) node a_bits_address_hi_lo_lo = cat(a_bits_address_hi_lo_lo_hi, a_bits_address_hi_lo_lo_lo) node a_bits_address_hi_lo_hi_lo = cat(_a_bits_address_T_18, _a_bits_address_T_17) node a_bits_address_hi_lo_hi_hi = cat(_a_bits_address_T_20, _a_bits_address_T_19) node a_bits_address_hi_lo_hi = cat(a_bits_address_hi_lo_hi_hi, a_bits_address_hi_lo_hi_lo) node a_bits_address_hi_lo = cat(a_bits_address_hi_lo_hi, a_bits_address_hi_lo_lo) node a_bits_address_hi_hi_lo_lo = cat(_a_bits_address_T_22, _a_bits_address_T_21) node a_bits_address_hi_hi_lo_hi = cat(_a_bits_address_T_24, _a_bits_address_T_23) node a_bits_address_hi_hi_lo = cat(a_bits_address_hi_hi_lo_hi, a_bits_address_hi_hi_lo_lo) node a_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node a_bits_address_hi_hi_hi_hi = cat(_a_bits_address_T_25, UInt<1>(0h0)) node a_bits_address_hi_hi_hi = cat(a_bits_address_hi_hi_hi_hi, a_bits_address_hi_hi_hi_lo) node a_bits_address_hi_hi = cat(a_bits_address_hi_hi_hi, a_bits_address_hi_hi_lo) node a_bits_address_hi = cat(a_bits_address_hi_hi, a_bits_address_hi_lo) node _a_bits_address_T_26 = cat(a_bits_address_hi, a_bits_address_lo) connect a.bits.address, _a_bits_address_T_26 node _a_bits_mask_T = not(UInt<8>(0h0)) connect a.bits.mask, _a_bits_mask_T connect a.bits.data, UInt<1>(0h0) connect a.bits.corrupt, UInt<1>(0h0)	module SourceA_3( // @[SourceA.scala:33:7] input clock, // @[SourceA.scala:33:7] input reset, // @[SourceA.scala:33:7] output io_req_ready, // @[SourceA.scala:35:14] input io_req_valid, // @[SourceA.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceA.scala:35:14] input [10:0] io_req_bits_set, // @[SourceA.scala:35:14] input [2:0] io_req_bits_param, // @[SourceA.scala:35:14] input [3:0] io_req_bits_source, // @[SourceA.scala:35:14] input io_req_bits_block, // @[SourceA.scala:35:14] input io_a_ready, // @[SourceA.scala:35:14] output io_a_valid, // @[SourceA.scala:35:14] output [2:0] io_a_bits_opcode, // @[SourceA.scala:35:14] output [2:0] io_a_bits_param, // @[SourceA.scala:35:14] output [2:0] io_a_bits_size, // @[SourceA.scala:35:14] output [3:0] io_a_bits_source, // @[SourceA.scala:35:14] output [31:0] io_a_bits_address, // @[SourceA.scala:35:14] output [7:0] io_a_bits_mask, // @[SourceA.scala:35:14] output [63:0] io_a_bits_data, // @[SourceA.scala:35:14] output io_a_bits_corrupt // @[SourceA.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceA.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceA.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceA.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceA.scala:33:7] wire [3:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceA.scala:33:7] wire io_req_bits_block_0 = io_req_bits_block; // @[SourceA.scala:33:7] wire io_a_ready_0 = io_a_ready; // @[SourceA.scala:33:7] wire _a_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] a_bits_size = 3'h6; // @[SourceA.scala:43:15] wire [63:0] a_bits_data = 64'h0; // @[SourceA.scala:43:15] wire a_bits_corrupt = 1'h0; // @[SourceA.scala:43:15] wire _a_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _a_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _a_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire [5:0] a_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _a_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire [1:0] a_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire a_ready; // @[SourceA.scala:43:15] wire [7:0] a_bits_mask = 8'hFF; // @[SourceA.scala:43:15] wire [7:0] _a_bits_mask_T = 8'hFF; // @[SourceA.scala:55:21] wire a_valid = io_req_valid_0; // @[SourceA.scala:33:7, :43:15] wire [8:0] a_bits_address_base_y = io_req_bits_tag_0; // @[SourceA.scala:33:7] wire [10:0] a_bits_address_base_y_1 = io_req_bits_set_0; // @[SourceA.scala:33:7] wire [2:0] a_bits_param = io_req_bits_param_0; // @[SourceA.scala:33:7, :43:15] wire [3:0] a_bits_source = io_req_bits_source_0; // @[SourceA.scala:33:7, :43:15] wire io_req_ready_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_opcode_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_param_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_size_0; // @[SourceA.scala:33:7] wire [3:0] io_a_bits_source_0; // @[SourceA.scala:33:7] wire [31:0] io_a_bits_address_0; // @[SourceA.scala:33:7] wire [7:0] io_a_bits_mask_0; // @[SourceA.scala:33:7] wire [63:0] io_a_bits_data_0; // @[SourceA.scala:33:7] wire io_a_bits_corrupt_0; // @[SourceA.scala:33:7] wire io_a_valid_0; // @[SourceA.scala:33:7] assign io_req_ready_0 = a_ready; // @[SourceA.scala:33:7, :43:15] wire [2:0] _a_bits_opcode_T; // @[SourceA.scala:50:24] wire [31:0] _a_bits_address_T_26; // @[Parameters.scala:230:8] wire [2:0] a_bits_opcode; // @[SourceA.scala:43:15] wire [31:0] a_bits_address; // @[SourceA.scala:43:15] assign _a_bits_opcode_T = {2'h3, ~io_req_bits_block_0}; // @[SourceA.scala:33:7, :50:24] assign a_bits_opcode = _a_bits_opcode_T; // @[SourceA.scala:43:15, :50:24] wire [8:0] _a_bits_address_base_T_5 = a_bits_address_base_y; // @[Parameters.scala:221:15, :223:6] wire _a_bits_address_base_T_3 = ~_a_bits_address_base_T_2; // @[Parameters.scala:222:12] wire [10:0] _a_bits_address_base_T_11 = a_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6] wire _a_bits_address_base_T_9 = ~_a_bits_address_base_T_8; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_15 = ~_a_bits_address_base_T_14; // @[Parameters.scala:222:12] wire [19:0] a_bits_address_base_hi = {_a_bits_address_base_T_5, _a_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19] wire [25:0] a_bits_address_base = {a_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19] wire _a_bits_address_T = a_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_1 = a_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_2 = a_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_3 = a_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_4 = a_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_5 = a_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_6 = a_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_7 = a_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_8 = a_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_9 = a_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_10 = a_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_11 = a_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_12 = a_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_13 = a_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_14 = a_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_15 = a_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_16 = a_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_17 = a_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_18 = a_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_19 = a_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_20 = a_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_21 = a_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_22 = a_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_23 = a_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_24 = a_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_25 = a_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72] wire [1:0] a_bits_address_lo_lo_lo_lo = {_a_bits_address_T_1, _a_bits_address_T}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_lo_lo_hi = {_a_bits_address_T_3, _a_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_lo_lo = {a_bits_address_lo_lo_lo_hi, a_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_lo_hi_lo = {_a_bits_address_T_5, _a_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_lo_hi = {2'h0, a_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_lo_lo = {a_bits_address_lo_lo_hi, a_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_hi_lo_lo = {_a_bits_address_T_6, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_hi_lo_hi = {_a_bits_address_T_8, _a_bits_address_T_7}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_hi_lo = {a_bits_address_lo_hi_lo_hi, a_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_hi_hi_lo = {_a_bits_address_T_10, _a_bits_address_T_9}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_hi_hi_hi = {_a_bits_address_T_12, _a_bits_address_T_11}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_hi_hi = {a_bits_address_lo_hi_hi_hi, a_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_lo_hi = {a_bits_address_lo_hi_hi, a_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] a_bits_address_lo = {a_bits_address_lo_hi, a_bits_address_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_lo_lo_lo = {_a_bits_address_T_14, _a_bits_address_T_13}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_lo_lo_hi = {_a_bits_address_T_16, _a_bits_address_T_15}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_lo_lo = {a_bits_address_hi_lo_lo_hi, a_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_lo_hi_lo = {_a_bits_address_T_18, _a_bits_address_T_17}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_lo_hi_hi = {_a_bits_address_T_20, _a_bits_address_T_19}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_lo_hi = {a_bits_address_hi_lo_hi_hi, a_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_hi_lo = {a_bits_address_hi_lo_hi, a_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_lo_lo = {_a_bits_address_T_22, _a_bits_address_T_21}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_hi_lo_hi = {_a_bits_address_T_24, _a_bits_address_T_23}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_hi_lo = {a_bits_address_hi_hi_lo_hi, a_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_hi_hi = {_a_bits_address_T_25, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_hi_hi = {a_bits_address_hi_hi_hi_hi, 2'h0}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_hi_hi = {a_bits_address_hi_hi_hi, a_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] a_bits_address_hi = {a_bits_address_hi_hi, a_bits_address_hi_lo}; // @[Parameters.scala:230:8] assign _a_bits_address_T_26 = {a_bits_address_hi, a_bits_address_lo}; // @[Parameters.scala:230:8] assign a_bits_address = _a_bits_address_T_26; // @[SourceA.scala:43:15] Queue2_TLBundleA_a32d64s4k3z3c_3 io_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (a_ready), .io_enq_valid (a_valid), // @[SourceA.scala:43:15] .io_enq_bits_opcode (a_bits_opcode), // @[SourceA.scala:43:15] .io_enq_bits_param (a_bits_param), // @[SourceA.scala:43:15] .io_enq_bits_source (a_bits_source), // @[SourceA.scala:43:15] .io_enq_bits_address (a_bits_address), // @[SourceA.scala:43:15] .io_deq_ready (io_a_ready_0), // @[SourceA.scala:33:7] .io_deq_valid (io_a_valid_0), .io_deq_bits_opcode (io_a_bits_opcode_0), .io_deq_bits_param (io_a_bits_param_0), .io_deq_bits_size (io_a_bits_size_0), .io_deq_bits_source (io_a_bits_source_0), .io_deq_bits_address (io_a_bits_address_0), .io_deq_bits_mask (io_a_bits_mask_0), .io_deq_bits_data (io_a_bits_data_0), .io_deq_bits_corrupt (io_a_bits_corrupt_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceA.scala:33:7] assign io_a_valid = io_a_valid_0; // @[SourceA.scala:33:7] assign io_a_bits_opcode = io_a_bits_opcode_0; // @[SourceA.scala:33:7] assign io_a_bits_param = io_a_bits_param_0; // @[SourceA.scala:33:7] assign io_a_bits_size = io_a_bits_size_0; // @[SourceA.scala:33:7] assign io_a_bits_source = io_a_bits_source_0; // @[SourceA.scala:33:7] assign io_a_bits_address = io_a_bits_address_0; // @[SourceA.scala:33:7] assign io_a_bits_mask = io_a_bits_mask_0; // @[SourceA.scala:33:7] assign io_a_bits_data = io_a_bits_data_0; // @[SourceA.scala:33:7] assign io_a_bits_corrupt = io_a_bits_corrupt_0; // @[SourceA.scala:33:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Switch_20 : input clock : Clock input reset : Reset output io : { in : { flip `2` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], flip `1` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], flip `0` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1]}, out : { `3` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], `2` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], `1` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], `0` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1]}, sel : { `3` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `2` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `1` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `0` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1]}} wire in_flat : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[3] connect in_flat[0], io.in.`0`[0] connect in_flat[1], io.in.`1`[0] connect in_flat[2], io.in.`2`[0] node sel_flat_hi = cat(io.sel.`0`[0].`2`[0], io.sel.`0`[0].`1`[0]) node sel_flat = cat(sel_flat_hi, io.sel.`0`[0].`0`[0]) node _T = bits(sel_flat, 0, 0) node _T_1 = bits(sel_flat, 1, 1) node _T_2 = bits(sel_flat, 2, 2) node _T_3 = add(_T_1, _T_2) node _T_4 = bits(_T_3, 1, 0) node _T_5 = add(_T, _T_4) node _T_6 = bits(_T_5, 1, 0) node _T_7 = leq(_T_6, UInt<1>(0h1)) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _io_out_0_0_valid_T = bits(sel_flat, 0, 0) node _io_out_0_0_valid_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_valid_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_valid_T_3 = mux(_io_out_0_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_4 = mux(_io_out_0_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_5 = mux(_io_out_0_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_6 = or(_io_out_0_0_valid_T_3, _io_out_0_0_valid_T_4) node _io_out_0_0_valid_T_7 = or(_io_out_0_0_valid_T_6, _io_out_0_0_valid_T_5) wire _io_out_0_0_valid_WIRE : UInt<1> connect _io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_7 node _io_out_0_0_valid_T_8 = neq(sel_flat, UInt<1>(0h0)) node _io_out_0_0_valid_T_9 = and(_io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_8) connect io.out.`0`[0].valid, _io_out_0_0_valid_T_9 node _io_out_0_0_bits_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_T_2 = bits(sel_flat, 2, 2) wire _io_out_0_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_0_0_bits_T_3 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_4 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_5 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_6 = or(_io_out_0_0_bits_T_3, _io_out_0_0_bits_T_4) node _io_out_0_0_bits_T_7 = or(_io_out_0_0_bits_T_6, _io_out_0_0_bits_T_5) wire _io_out_0_0_bits_WIRE_1 : UInt<1> connect _io_out_0_0_bits_WIRE_1, _io_out_0_0_bits_T_7 connect _io_out_0_0_bits_WIRE.virt_channel_id, _io_out_0_0_bits_WIRE_1 wire _io_out_0_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_0_0_bits_T_8 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_9 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_10 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_11 = or(_io_out_0_0_bits_T_8, _io_out_0_0_bits_T_9) node _io_out_0_0_bits_T_12 = or(_io_out_0_0_bits_T_11, _io_out_0_0_bits_T_10) wire _io_out_0_0_bits_WIRE_3 : UInt<2> connect _io_out_0_0_bits_WIRE_3, _io_out_0_0_bits_T_12 connect _io_out_0_0_bits_WIRE_2.egress_node_id, _io_out_0_0_bits_WIRE_3 node _io_out_0_0_bits_T_13 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_14 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_15 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_16 = or(_io_out_0_0_bits_T_13, _io_out_0_0_bits_T_14) node _io_out_0_0_bits_T_17 = or(_io_out_0_0_bits_T_16, _io_out_0_0_bits_T_15) wire _io_out_0_0_bits_WIRE_4 : UInt<4> connect _io_out_0_0_bits_WIRE_4, _io_out_0_0_bits_T_17 connect _io_out_0_0_bits_WIRE_2.egress_node, _io_out_0_0_bits_WIRE_4 node _io_out_0_0_bits_T_18 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_19 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_20 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_21 = or(_io_out_0_0_bits_T_18, _io_out_0_0_bits_T_19) node _io_out_0_0_bits_T_22 = or(_io_out_0_0_bits_T_21, _io_out_0_0_bits_T_20) wire _io_out_0_0_bits_WIRE_5 : UInt<2> connect _io_out_0_0_bits_WIRE_5, _io_out_0_0_bits_T_22 connect _io_out_0_0_bits_WIRE_2.ingress_node_id, _io_out_0_0_bits_WIRE_5 node _io_out_0_0_bits_T_23 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_24 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_25 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_26 = or(_io_out_0_0_bits_T_23, _io_out_0_0_bits_T_24) node _io_out_0_0_bits_T_27 = or(_io_out_0_0_bits_T_26, _io_out_0_0_bits_T_25) wire _io_out_0_0_bits_WIRE_6 : UInt<4> connect _io_out_0_0_bits_WIRE_6, _io_out_0_0_bits_T_27 connect _io_out_0_0_bits_WIRE_2.ingress_node, _io_out_0_0_bits_WIRE_6 node _io_out_0_0_bits_T_28 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_29 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_30 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_31 = or(_io_out_0_0_bits_T_28, _io_out_0_0_bits_T_29) node _io_out_0_0_bits_T_32 = or(_io_out_0_0_bits_T_31, _io_out_0_0_bits_T_30) wire _io_out_0_0_bits_WIRE_7 : UInt<1> connect _io_out_0_0_bits_WIRE_7, _io_out_0_0_bits_T_32 connect _io_out_0_0_bits_WIRE_2.vnet_id, _io_out_0_0_bits_WIRE_7 connect _io_out_0_0_bits_WIRE.flow, _io_out_0_0_bits_WIRE_2 node _io_out_0_0_bits_T_33 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_34 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_35 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_36 = or(_io_out_0_0_bits_T_33, _io_out_0_0_bits_T_34) node _io_out_0_0_bits_T_37 = or(_io_out_0_0_bits_T_36, _io_out_0_0_bits_T_35) wire _io_out_0_0_bits_WIRE_8 : UInt<37> connect _io_out_0_0_bits_WIRE_8, _io_out_0_0_bits_T_37 connect _io_out_0_0_bits_WIRE.payload, _io_out_0_0_bits_WIRE_8 node _io_out_0_0_bits_T_38 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_39 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_40 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_41 = or(_io_out_0_0_bits_T_38, _io_out_0_0_bits_T_39) node _io_out_0_0_bits_T_42 = or(_io_out_0_0_bits_T_41, _io_out_0_0_bits_T_40) wire _io_out_0_0_bits_WIRE_9 : UInt<1> connect _io_out_0_0_bits_WIRE_9, _io_out_0_0_bits_T_42 connect _io_out_0_0_bits_WIRE.tail, _io_out_0_0_bits_WIRE_9 node _io_out_0_0_bits_T_43 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_44 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_45 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_46 = or(_io_out_0_0_bits_T_43, _io_out_0_0_bits_T_44) node _io_out_0_0_bits_T_47 = or(_io_out_0_0_bits_T_46, _io_out_0_0_bits_T_45) wire _io_out_0_0_bits_WIRE_10 : UInt<1> connect _io_out_0_0_bits_WIRE_10, _io_out_0_0_bits_T_47 connect _io_out_0_0_bits_WIRE.head, _io_out_0_0_bits_WIRE_10 connect io.out.`0`[0].bits, _io_out_0_0_bits_WIRE node _io_out_0_0_bits_virt_channel_id_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_virt_channel_id_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_virt_channel_id_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_bits_virt_channel_id_T_3 = mux(_io_out_0_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_4 = mux(_io_out_0_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_5 = mux(_io_out_0_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_6 = or(_io_out_0_0_bits_virt_channel_id_T_3, _io_out_0_0_bits_virt_channel_id_T_4) node _io_out_0_0_bits_virt_channel_id_T_7 = or(_io_out_0_0_bits_virt_channel_id_T_6, _io_out_0_0_bits_virt_channel_id_T_5) wire _io_out_0_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_0_0_bits_virt_channel_id_WIRE, _io_out_0_0_bits_virt_channel_id_T_7 connect io.out.`0`[0].bits.virt_channel_id, _io_out_0_0_bits_virt_channel_id_WIRE node sel_flat_hi_1 = cat(io.sel.`1`[0].`2`[0], io.sel.`1`[0].`1`[0]) node sel_flat_1 = cat(sel_flat_hi_1, io.sel.`1`[0].`0`[0]) node _T_11 = bits(sel_flat_1, 0, 0) node _T_12 = bits(sel_flat_1, 1, 1) node _T_13 = bits(sel_flat_1, 2, 2) node _T_14 = add(_T_12, _T_13) node _T_15 = bits(_T_14, 1, 0) node _T_16 = add(_T_11, _T_15) node _T_17 = bits(_T_16, 1, 0) node _T_18 = leq(_T_17, UInt<1>(0h1)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_1 assert(clock, _T_18, UInt<1>(0h1), "") : assert_1 node _io_out_1_0_valid_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_valid_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_valid_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_valid_T_3 = mux(_io_out_1_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_4 = mux(_io_out_1_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_5 = mux(_io_out_1_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_6 = or(_io_out_1_0_valid_T_3, _io_out_1_0_valid_T_4) node _io_out_1_0_valid_T_7 = or(_io_out_1_0_valid_T_6, _io_out_1_0_valid_T_5) wire _io_out_1_0_valid_WIRE : UInt<1> connect _io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_7 node _io_out_1_0_valid_T_8 = neq(sel_flat_1, UInt<1>(0h0)) node _io_out_1_0_valid_T_9 = and(_io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_8) connect io.out.`1`[0].valid, _io_out_1_0_valid_T_9 node _io_out_1_0_bits_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_T_2 = bits(sel_flat_1, 2, 2) wire _io_out_1_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_1_0_bits_T_3 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_4 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_5 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_6 = or(_io_out_1_0_bits_T_3, _io_out_1_0_bits_T_4) node _io_out_1_0_bits_T_7 = or(_io_out_1_0_bits_T_6, _io_out_1_0_bits_T_5) wire _io_out_1_0_bits_WIRE_1 : UInt<1> connect _io_out_1_0_bits_WIRE_1, _io_out_1_0_bits_T_7 connect _io_out_1_0_bits_WIRE.virt_channel_id, _io_out_1_0_bits_WIRE_1 wire _io_out_1_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_1_0_bits_T_8 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_9 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_10 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_11 = or(_io_out_1_0_bits_T_8, _io_out_1_0_bits_T_9) node _io_out_1_0_bits_T_12 = or(_io_out_1_0_bits_T_11, _io_out_1_0_bits_T_10) wire _io_out_1_0_bits_WIRE_3 : UInt<2> connect _io_out_1_0_bits_WIRE_3, _io_out_1_0_bits_T_12 connect _io_out_1_0_bits_WIRE_2.egress_node_id, _io_out_1_0_bits_WIRE_3 node _io_out_1_0_bits_T_13 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_14 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_15 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_16 = or(_io_out_1_0_bits_T_13, _io_out_1_0_bits_T_14) node _io_out_1_0_bits_T_17 = or(_io_out_1_0_bits_T_16, _io_out_1_0_bits_T_15) wire _io_out_1_0_bits_WIRE_4 : UInt<4> connect _io_out_1_0_bits_WIRE_4, _io_out_1_0_bits_T_17 connect _io_out_1_0_bits_WIRE_2.egress_node, _io_out_1_0_bits_WIRE_4 node _io_out_1_0_bits_T_18 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_19 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_20 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_21 = or(_io_out_1_0_bits_T_18, _io_out_1_0_bits_T_19) node _io_out_1_0_bits_T_22 = or(_io_out_1_0_bits_T_21, _io_out_1_0_bits_T_20) wire _io_out_1_0_bits_WIRE_5 : UInt<2> connect _io_out_1_0_bits_WIRE_5, _io_out_1_0_bits_T_22 connect _io_out_1_0_bits_WIRE_2.ingress_node_id, _io_out_1_0_bits_WIRE_5 node _io_out_1_0_bits_T_23 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_24 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_25 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_26 = or(_io_out_1_0_bits_T_23, _io_out_1_0_bits_T_24) node _io_out_1_0_bits_T_27 = or(_io_out_1_0_bits_T_26, _io_out_1_0_bits_T_25) wire _io_out_1_0_bits_WIRE_6 : UInt<4> connect _io_out_1_0_bits_WIRE_6, _io_out_1_0_bits_T_27 connect _io_out_1_0_bits_WIRE_2.ingress_node, _io_out_1_0_bits_WIRE_6 node _io_out_1_0_bits_T_28 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_29 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_30 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_31 = or(_io_out_1_0_bits_T_28, _io_out_1_0_bits_T_29) node _io_out_1_0_bits_T_32 = or(_io_out_1_0_bits_T_31, _io_out_1_0_bits_T_30) wire _io_out_1_0_bits_WIRE_7 : UInt<1> connect _io_out_1_0_bits_WIRE_7, _io_out_1_0_bits_T_32 connect _io_out_1_0_bits_WIRE_2.vnet_id, _io_out_1_0_bits_WIRE_7 connect _io_out_1_0_bits_WIRE.flow, _io_out_1_0_bits_WIRE_2 node _io_out_1_0_bits_T_33 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_34 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_35 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_36 = or(_io_out_1_0_bits_T_33, _io_out_1_0_bits_T_34) node _io_out_1_0_bits_T_37 = or(_io_out_1_0_bits_T_36, _io_out_1_0_bits_T_35) wire _io_out_1_0_bits_WIRE_8 : UInt<37> connect _io_out_1_0_bits_WIRE_8, _io_out_1_0_bits_T_37 connect _io_out_1_0_bits_WIRE.payload, _io_out_1_0_bits_WIRE_8 node _io_out_1_0_bits_T_38 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_39 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_40 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_41 = or(_io_out_1_0_bits_T_38, _io_out_1_0_bits_T_39) node _io_out_1_0_bits_T_42 = or(_io_out_1_0_bits_T_41, _io_out_1_0_bits_T_40) wire _io_out_1_0_bits_WIRE_9 : UInt<1> connect _io_out_1_0_bits_WIRE_9, _io_out_1_0_bits_T_42 connect _io_out_1_0_bits_WIRE.tail, _io_out_1_0_bits_WIRE_9 node _io_out_1_0_bits_T_43 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_44 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_45 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_46 = or(_io_out_1_0_bits_T_43, _io_out_1_0_bits_T_44) node _io_out_1_0_bits_T_47 = or(_io_out_1_0_bits_T_46, _io_out_1_0_bits_T_45) wire _io_out_1_0_bits_WIRE_10 : UInt<1> connect _io_out_1_0_bits_WIRE_10, _io_out_1_0_bits_T_47 connect _io_out_1_0_bits_WIRE.head, _io_out_1_0_bits_WIRE_10 connect io.out.`1`[0].bits, _io_out_1_0_bits_WIRE node _io_out_1_0_bits_virt_channel_id_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_virt_channel_id_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_virt_channel_id_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_bits_virt_channel_id_T_3 = mux(_io_out_1_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_4 = mux(_io_out_1_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_5 = mux(_io_out_1_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_6 = or(_io_out_1_0_bits_virt_channel_id_T_3, _io_out_1_0_bits_virt_channel_id_T_4) node _io_out_1_0_bits_virt_channel_id_T_7 = or(_io_out_1_0_bits_virt_channel_id_T_6, _io_out_1_0_bits_virt_channel_id_T_5) wire _io_out_1_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_1_0_bits_virt_channel_id_WIRE, _io_out_1_0_bits_virt_channel_id_T_7 connect io.out.`1`[0].bits.virt_channel_id, _io_out_1_0_bits_virt_channel_id_WIRE node sel_flat_hi_2 = cat(io.sel.`2`[0].`2`[0], io.sel.`2`[0].`1`[0]) node sel_flat_2 = cat(sel_flat_hi_2, io.sel.`2`[0].`0`[0]) node _T_22 = bits(sel_flat_2, 0, 0) node _T_23 = bits(sel_flat_2, 1, 1) node _T_24 = bits(sel_flat_2, 2, 2) node _T_25 = add(_T_23, _T_24) node _T_26 = bits(_T_25, 1, 0) node _T_27 = add(_T_22, _T_26) node _T_28 = bits(_T_27, 1, 0) node _T_29 = leq(_T_28, UInt<1>(0h1)) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_2 assert(clock, _T_29, UInt<1>(0h1), "") : assert_2 node _io_out_2_0_valid_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_valid_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_valid_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_valid_T_3 = mux(_io_out_2_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_4 = mux(_io_out_2_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_5 = mux(_io_out_2_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_6 = or(_io_out_2_0_valid_T_3, _io_out_2_0_valid_T_4) node _io_out_2_0_valid_T_7 = or(_io_out_2_0_valid_T_6, _io_out_2_0_valid_T_5) wire _io_out_2_0_valid_WIRE : UInt<1> connect _io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_7 node _io_out_2_0_valid_T_8 = neq(sel_flat_2, UInt<1>(0h0)) node _io_out_2_0_valid_T_9 = and(_io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_8) connect io.out.`2`[0].valid, _io_out_2_0_valid_T_9 node _io_out_2_0_bits_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_T_2 = bits(sel_flat_2, 2, 2) wire _io_out_2_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_2_0_bits_T_3 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_4 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_5 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_6 = or(_io_out_2_0_bits_T_3, _io_out_2_0_bits_T_4) node _io_out_2_0_bits_T_7 = or(_io_out_2_0_bits_T_6, _io_out_2_0_bits_T_5) wire _io_out_2_0_bits_WIRE_1 : UInt<1> connect _io_out_2_0_bits_WIRE_1, _io_out_2_0_bits_T_7 connect _io_out_2_0_bits_WIRE.virt_channel_id, _io_out_2_0_bits_WIRE_1 wire _io_out_2_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_2_0_bits_T_8 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_9 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_10 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_11 = or(_io_out_2_0_bits_T_8, _io_out_2_0_bits_T_9) node _io_out_2_0_bits_T_12 = or(_io_out_2_0_bits_T_11, _io_out_2_0_bits_T_10) wire _io_out_2_0_bits_WIRE_3 : UInt<2> connect _io_out_2_0_bits_WIRE_3, _io_out_2_0_bits_T_12 connect _io_out_2_0_bits_WIRE_2.egress_node_id, _io_out_2_0_bits_WIRE_3 node _io_out_2_0_bits_T_13 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_14 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_15 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_16 = or(_io_out_2_0_bits_T_13, _io_out_2_0_bits_T_14) node _io_out_2_0_bits_T_17 = or(_io_out_2_0_bits_T_16, _io_out_2_0_bits_T_15) wire _io_out_2_0_bits_WIRE_4 : UInt<4> connect _io_out_2_0_bits_WIRE_4, _io_out_2_0_bits_T_17 connect _io_out_2_0_bits_WIRE_2.egress_node, _io_out_2_0_bits_WIRE_4 node _io_out_2_0_bits_T_18 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_19 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_20 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_21 = or(_io_out_2_0_bits_T_18, _io_out_2_0_bits_T_19) node _io_out_2_0_bits_T_22 = or(_io_out_2_0_bits_T_21, _io_out_2_0_bits_T_20) wire _io_out_2_0_bits_WIRE_5 : UInt<2> connect _io_out_2_0_bits_WIRE_5, _io_out_2_0_bits_T_22 connect _io_out_2_0_bits_WIRE_2.ingress_node_id, _io_out_2_0_bits_WIRE_5 node _io_out_2_0_bits_T_23 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_24 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_25 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_26 = or(_io_out_2_0_bits_T_23, _io_out_2_0_bits_T_24) node _io_out_2_0_bits_T_27 = or(_io_out_2_0_bits_T_26, _io_out_2_0_bits_T_25) wire _io_out_2_0_bits_WIRE_6 : UInt<4> connect _io_out_2_0_bits_WIRE_6, _io_out_2_0_bits_T_27 connect _io_out_2_0_bits_WIRE_2.ingress_node, _io_out_2_0_bits_WIRE_6 node _io_out_2_0_bits_T_28 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_29 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_30 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_31 = or(_io_out_2_0_bits_T_28, _io_out_2_0_bits_T_29) node _io_out_2_0_bits_T_32 = or(_io_out_2_0_bits_T_31, _io_out_2_0_bits_T_30) wire _io_out_2_0_bits_WIRE_7 : UInt<1> connect _io_out_2_0_bits_WIRE_7, _io_out_2_0_bits_T_32 connect _io_out_2_0_bits_WIRE_2.vnet_id, _io_out_2_0_bits_WIRE_7 connect _io_out_2_0_bits_WIRE.flow, _io_out_2_0_bits_WIRE_2 node _io_out_2_0_bits_T_33 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_34 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_35 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_36 = or(_io_out_2_0_bits_T_33, _io_out_2_0_bits_T_34) node _io_out_2_0_bits_T_37 = or(_io_out_2_0_bits_T_36, _io_out_2_0_bits_T_35) wire _io_out_2_0_bits_WIRE_8 : UInt<37> connect _io_out_2_0_bits_WIRE_8, _io_out_2_0_bits_T_37 connect _io_out_2_0_bits_WIRE.payload, _io_out_2_0_bits_WIRE_8 node _io_out_2_0_bits_T_38 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_39 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_40 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_41 = or(_io_out_2_0_bits_T_38, _io_out_2_0_bits_T_39) node _io_out_2_0_bits_T_42 = or(_io_out_2_0_bits_T_41, _io_out_2_0_bits_T_40) wire _io_out_2_0_bits_WIRE_9 : UInt<1> connect _io_out_2_0_bits_WIRE_9, _io_out_2_0_bits_T_42 connect _io_out_2_0_bits_WIRE.tail, _io_out_2_0_bits_WIRE_9 node _io_out_2_0_bits_T_43 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_44 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_45 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_46 = or(_io_out_2_0_bits_T_43, _io_out_2_0_bits_T_44) node _io_out_2_0_bits_T_47 = or(_io_out_2_0_bits_T_46, _io_out_2_0_bits_T_45) wire _io_out_2_0_bits_WIRE_10 : UInt<1> connect _io_out_2_0_bits_WIRE_10, _io_out_2_0_bits_T_47 connect _io_out_2_0_bits_WIRE.head, _io_out_2_0_bits_WIRE_10 connect io.out.`2`[0].bits, _io_out_2_0_bits_WIRE node _io_out_2_0_bits_virt_channel_id_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_virt_channel_id_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_virt_channel_id_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_bits_virt_channel_id_T_3 = mux(_io_out_2_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_4 = mux(_io_out_2_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_5 = mux(_io_out_2_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_6 = or(_io_out_2_0_bits_virt_channel_id_T_3, _io_out_2_0_bits_virt_channel_id_T_4) node _io_out_2_0_bits_virt_channel_id_T_7 = or(_io_out_2_0_bits_virt_channel_id_T_6, _io_out_2_0_bits_virt_channel_id_T_5) wire _io_out_2_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_2_0_bits_virt_channel_id_WIRE, _io_out_2_0_bits_virt_channel_id_T_7 connect io.out.`2`[0].bits.virt_channel_id, _io_out_2_0_bits_virt_channel_id_WIRE node sel_flat_hi_3 = cat(io.sel.`3`[0].`2`[0], io.sel.`3`[0].`1`[0]) node sel_flat_3 = cat(sel_flat_hi_3, io.sel.`3`[0].`0`[0]) node _T_33 = bits(sel_flat_3, 0, 0) node _T_34 = bits(sel_flat_3, 1, 1) node _T_35 = bits(sel_flat_3, 2, 2) node _T_36 = add(_T_34, _T_35) node _T_37 = bits(_T_36, 1, 0) node _T_38 = add(_T_33, _T_37) node _T_39 = bits(_T_38, 1, 0) node _T_40 = leq(_T_39, UInt<1>(0h1)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_3 assert(clock, _T_40, UInt<1>(0h1), "") : assert_3 node _io_out_3_0_valid_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_valid_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_valid_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_valid_T_3 = mux(_io_out_3_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_4 = mux(_io_out_3_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_5 = mux(_io_out_3_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_6 = or(_io_out_3_0_valid_T_3, _io_out_3_0_valid_T_4) node _io_out_3_0_valid_T_7 = or(_io_out_3_0_valid_T_6, _io_out_3_0_valid_T_5) wire _io_out_3_0_valid_WIRE : UInt<1> connect _io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_7 node _io_out_3_0_valid_T_8 = neq(sel_flat_3, UInt<1>(0h0)) node _io_out_3_0_valid_T_9 = and(_io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_8) connect io.out.`3`[0].valid, _io_out_3_0_valid_T_9 node _io_out_3_0_bits_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_T_2 = bits(sel_flat_3, 2, 2) wire _io_out_3_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_3_0_bits_T_3 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_4 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_5 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_6 = or(_io_out_3_0_bits_T_3, _io_out_3_0_bits_T_4) node _io_out_3_0_bits_T_7 = or(_io_out_3_0_bits_T_6, _io_out_3_0_bits_T_5) wire _io_out_3_0_bits_WIRE_1 : UInt<1> connect _io_out_3_0_bits_WIRE_1, _io_out_3_0_bits_T_7 connect _io_out_3_0_bits_WIRE.virt_channel_id, _io_out_3_0_bits_WIRE_1 wire _io_out_3_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_3_0_bits_T_8 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_9 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_10 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_11 = or(_io_out_3_0_bits_T_8, _io_out_3_0_bits_T_9) node _io_out_3_0_bits_T_12 = or(_io_out_3_0_bits_T_11, _io_out_3_0_bits_T_10) wire _io_out_3_0_bits_WIRE_3 : UInt<2> connect _io_out_3_0_bits_WIRE_3, _io_out_3_0_bits_T_12 connect _io_out_3_0_bits_WIRE_2.egress_node_id, _io_out_3_0_bits_WIRE_3 node _io_out_3_0_bits_T_13 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_14 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_15 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_16 = or(_io_out_3_0_bits_T_13, _io_out_3_0_bits_T_14) node _io_out_3_0_bits_T_17 = or(_io_out_3_0_bits_T_16, _io_out_3_0_bits_T_15) wire _io_out_3_0_bits_WIRE_4 : UInt<4> connect _io_out_3_0_bits_WIRE_4, _io_out_3_0_bits_T_17 connect _io_out_3_0_bits_WIRE_2.egress_node, _io_out_3_0_bits_WIRE_4 node _io_out_3_0_bits_T_18 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_19 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_20 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_21 = or(_io_out_3_0_bits_T_18, _io_out_3_0_bits_T_19) node _io_out_3_0_bits_T_22 = or(_io_out_3_0_bits_T_21, _io_out_3_0_bits_T_20) wire _io_out_3_0_bits_WIRE_5 : UInt<2> connect _io_out_3_0_bits_WIRE_5, _io_out_3_0_bits_T_22 connect _io_out_3_0_bits_WIRE_2.ingress_node_id, _io_out_3_0_bits_WIRE_5 node _io_out_3_0_bits_T_23 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_24 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_25 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_26 = or(_io_out_3_0_bits_T_23, _io_out_3_0_bits_T_24) node _io_out_3_0_bits_T_27 = or(_io_out_3_0_bits_T_26, _io_out_3_0_bits_T_25) wire _io_out_3_0_bits_WIRE_6 : UInt<4> connect _io_out_3_0_bits_WIRE_6, _io_out_3_0_bits_T_27 connect _io_out_3_0_bits_WIRE_2.ingress_node, _io_out_3_0_bits_WIRE_6 node _io_out_3_0_bits_T_28 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_29 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_30 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_31 = or(_io_out_3_0_bits_T_28, _io_out_3_0_bits_T_29) node _io_out_3_0_bits_T_32 = or(_io_out_3_0_bits_T_31, _io_out_3_0_bits_T_30) wire _io_out_3_0_bits_WIRE_7 : UInt<1> connect _io_out_3_0_bits_WIRE_7, _io_out_3_0_bits_T_32 connect _io_out_3_0_bits_WIRE_2.vnet_id, _io_out_3_0_bits_WIRE_7 connect _io_out_3_0_bits_WIRE.flow, _io_out_3_0_bits_WIRE_2 node _io_out_3_0_bits_T_33 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_34 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_35 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_36 = or(_io_out_3_0_bits_T_33, _io_out_3_0_bits_T_34) node _io_out_3_0_bits_T_37 = or(_io_out_3_0_bits_T_36, _io_out_3_0_bits_T_35) wire _io_out_3_0_bits_WIRE_8 : UInt<37> connect _io_out_3_0_bits_WIRE_8, _io_out_3_0_bits_T_37 connect _io_out_3_0_bits_WIRE.payload, _io_out_3_0_bits_WIRE_8 node _io_out_3_0_bits_T_38 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_39 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_40 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_41 = or(_io_out_3_0_bits_T_38, _io_out_3_0_bits_T_39) node _io_out_3_0_bits_T_42 = or(_io_out_3_0_bits_T_41, _io_out_3_0_bits_T_40) wire _io_out_3_0_bits_WIRE_9 : UInt<1> connect _io_out_3_0_bits_WIRE_9, _io_out_3_0_bits_T_42 connect _io_out_3_0_bits_WIRE.tail, _io_out_3_0_bits_WIRE_9 node _io_out_3_0_bits_T_43 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_44 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_45 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_46 = or(_io_out_3_0_bits_T_43, _io_out_3_0_bits_T_44) node _io_out_3_0_bits_T_47 = or(_io_out_3_0_bits_T_46, _io_out_3_0_bits_T_45) wire _io_out_3_0_bits_WIRE_10 : UInt<1> connect _io_out_3_0_bits_WIRE_10, _io_out_3_0_bits_T_47 connect _io_out_3_0_bits_WIRE.head, _io_out_3_0_bits_WIRE_10 connect io.out.`3`[0].bits, _io_out_3_0_bits_WIRE node _io_out_3_0_bits_virt_channel_id_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_virt_channel_id_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_virt_channel_id_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_bits_virt_channel_id_T_3 = mux(_io_out_3_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_4 = mux(_io_out_3_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_5 = mux(_io_out_3_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_6 = or(_io_out_3_0_bits_virt_channel_id_T_3, _io_out_3_0_bits_virt_channel_id_T_4) node _io_out_3_0_bits_virt_channel_id_T_7 = or(_io_out_3_0_bits_virt_channel_id_T_6, _io_out_3_0_bits_virt_channel_id_T_5) wire _io_out_3_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_3_0_bits_virt_channel_id_WIRE, _io_out_3_0_bits_virt_channel_id_T_7 connect io.out.`3`[0].bits.virt_channel_id, _io_out_3_0_bits_virt_channel_id_WIRE	module Switch_20( // @[Switch.scala:16:7] input clock, // @[Switch.scala:16:7] input reset, // @[Switch.scala:16:7] input io_in_2_0_valid, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_tail, // @[Switch.scala:27:14] input [36:0] io_in_2_0_bits_flit_payload, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_2_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [1:0] io_in_2_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_2_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_2_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input io_in_2_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_1_0_valid, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14] input [36:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [1:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_0_0_valid, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14] input [36:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [1:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14] output io_out_3_0_valid, // @[Switch.scala:27:14] output io_out_3_0_bits_head, // @[Switch.scala:27:14] output io_out_3_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_3_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_3_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_2_0_valid, // @[Switch.scala:27:14] output io_out_2_0_bits_head, // @[Switch.scala:27:14] output io_out_2_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14] output io_out_2_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_2_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_2_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_2_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_2_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output io_out_2_0_bits_virt_channel_id, // @[Switch.scala:27:14] output io_out_1_0_valid, // @[Switch.scala:27:14] output io_out_1_0_bits_head, // @[Switch.scala:27:14] output io_out_1_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14] output io_out_1_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_1_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_1_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output io_out_1_0_bits_virt_channel_id, // @[Switch.scala:27:14] output io_out_0_0_valid, // @[Switch.scala:27:14] output io_out_0_0_bits_head, // @[Switch.scala:27:14] output io_out_0_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14] output io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14] input io_sel_3_0_2_0, // @[Switch.scala:27:14] input io_sel_3_0_1_0, // @[Switch.scala:27:14] input io_sel_3_0_0_0, // @[Switch.scala:27:14] input io_sel_2_0_2_0, // @[Switch.scala:27:14] input io_sel_2_0_1_0, // @[Switch.scala:27:14] input io_sel_2_0_0_0, // @[Switch.scala:27:14] input io_sel_1_0_2_0, // @[Switch.scala:27:14] input io_sel_0_0_2_0, // @[Switch.scala:27:14] input io_sel_0_0_1_0, // @[Switch.scala:27:14] input io_sel_0_0_0_0 // @[Switch.scala:27:14] );
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_79 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2	module NoCMonitor_79( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 6) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 6) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_37 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_47, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<6>(0h20)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<6>(0h21)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<6>(0h22)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<6>(0h23)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0) node _T_64 = shr(io.in.a.bits.source, 6) node _T_65 = eq(_T_64, UInt<1>(0h1)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0) node _T_77 = shr(io.in.a.bits.source, 6) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_93 = cvt(_T_92) node _T_94 = and(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = asSInt(_T_94) node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0))) node _T_97 = or(_T_91, _T_96) node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = and(_T_11, _T_24) node _T_115 = and(_T_114, _T_37) node _T_116 = and(_T_115, _T_50) node _T_117 = and(_T_116, _T_63) node _T_118 = and(_T_117, _T_76) node _T_119 = and(_T_118, _T_89) node _T_120 = and(_T_119, _T_97) node _T_121 = and(_T_120, _T_105) node _T_122 = and(_T_121, _T_113) node _T_123 = asUInt(reset) node _T_124 = eq(_T_123, UInt<1>(0h0)) when _T_124 : node _T_125 = eq(_T_122, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_122, UInt<1>(0h1), "") : assert_1 node _T_126 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_126 : node _T_127 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_128 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_131 = shr(io.in.a.bits.source, 2) node _T_132 = eq(_T_131, UInt<6>(0h20)) node _T_133 = leq(UInt<1>(0h0), uncommonBits_6) node _T_134 = and(_T_132, _T_133) node _T_135 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_136 = and(_T_134, _T_135) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_137 = shr(io.in.a.bits.source, 2) node _T_138 = eq(_T_137, UInt<6>(0h21)) node _T_139 = leq(UInt<1>(0h0), uncommonBits_7) node _T_140 = and(_T_138, _T_139) node _T_141 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_142 = and(_T_140, _T_141) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_143 = shr(io.in.a.bits.source, 2) node _T_144 = eq(_T_143, UInt<6>(0h22)) node _T_145 = leq(UInt<1>(0h0), uncommonBits_8) node _T_146 = and(_T_144, _T_145) node _T_147 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_149 = shr(io.in.a.bits.source, 2) node _T_150 = eq(_T_149, UInt<6>(0h23)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_9) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0) node _T_155 = shr(io.in.a.bits.source, 6) node _T_156 = eq(_T_155, UInt<1>(0h1)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_10) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_10, UInt<6>(0h3f)) node _T_160 = and(_T_158, _T_159) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0) node _T_161 = shr(io.in.a.bits.source, 6) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = leq(UInt<1>(0h0), uncommonBits_11) node _T_164 = and(_T_162, _T_163) node _T_165 = leq(uncommonBits_11, UInt<6>(0h3f)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_168 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_169 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_170 = or(_T_130, _T_136) node _T_171 = or(_T_170, _T_142) node _T_172 = or(_T_171, _T_148) node _T_173 = or(_T_172, _T_154) node _T_174 = or(_T_173, _T_160) node _T_175 = or(_T_174, _T_166) node _T_176 = or(_T_175, _T_167) node _T_177 = or(_T_176, _T_168) node _T_178 = or(_T_177, _T_169) node _T_179 = and(_T_129, _T_178) node _T_180 = or(UInt<1>(0h0), _T_179) node _T_181 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<14>(0h2000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_188 = cvt(_T_187) node _T_189 = and(_T_188, asSInt(UInt<13>(0h1000))) node _T_190 = asSInt(_T_189) node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0))) node _T_192 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<17>(0h10000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<18>(0h2f000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<17>(0h10000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<13>(0h1000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<27>(0h4000000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<13>(0h1000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = or(_T_186, _T_191) node _T_223 = or(_T_222, _T_196) node _T_224 = or(_T_223, _T_201) node _T_225 = or(_T_224, _T_206) node _T_226 = or(_T_225, _T_211) node _T_227 = or(_T_226, _T_216) node _T_228 = or(_T_227, _T_221) node _T_229 = and(_T_181, _T_228) node _T_230 = or(UInt<1>(0h0), _T_229) node _T_231 = and(_T_180, _T_230) node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : node _T_234 = eq(_T_231, UInt<1>(0h0)) when _T_234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_231, UInt<1>(0h1), "") : assert_2 node _T_235 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<6>(0h20)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_12) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<6>(0h21)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_13) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_248 = shr(io.in.a.bits.source, 2) node _T_249 = eq(_T_248, UInt<6>(0h22)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_14) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_254 = shr(io.in.a.bits.source, 2) node _T_255 = eq(_T_254, UInt<6>(0h23)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_15) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0) node _T_260 = shr(io.in.a.bits.source, 6) node _T_261 = eq(_T_260, UInt<1>(0h1)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_16) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_16, UInt<6>(0h3f)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0) node _T_266 = shr(io.in.a.bits.source, 6) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_17) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_17, UInt<6>(0h3f)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_273 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_274 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_235 connect _WIRE[1], _T_241 connect _WIRE[2], _T_247 connect _WIRE[3], _T_253 connect _WIRE[4], _T_259 connect _WIRE[5], _T_265 connect _WIRE[6], _T_271 connect _WIRE[7], _T_272 connect _WIRE[8], _T_273 connect _WIRE[9], _T_274 node _T_275 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_276 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_278 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_279 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_280 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_281 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_282 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = mux(_WIRE[7], _T_275, UInt<1>(0h0)) node _T_284 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_285 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = or(_T_276, _T_277) node _T_287 = or(_T_286, _T_278) node _T_288 = or(_T_287, _T_279) node _T_289 = or(_T_288, _T_280) node _T_290 = or(_T_289, _T_281) node _T_291 = or(_T_290, _T_282) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_284) node _T_294 = or(_T_293, _T_285) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_294 node _T_295 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_296 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_297 = and(_T_295, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_300 = cvt(_T_299) node _T_301 = and(_T_300, asSInt(UInt<14>(0h2000))) node _T_302 = asSInt(_T_301) node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0))) node _T_304 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_305 = cvt(_T_304) node _T_306 = and(_T_305, asSInt(UInt<13>(0h1000))) node _T_307 = asSInt(_T_306) node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h10000))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<18>(0h2f000))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<17>(0h10000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<27>(0h4000000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<13>(0h1000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = or(_T_303, _T_308) node _T_340 = or(_T_339, _T_313) node _T_341 = or(_T_340, _T_318) node _T_342 = or(_T_341, _T_323) node _T_343 = or(_T_342, _T_328) node _T_344 = or(_T_343, _T_333) node _T_345 = or(_T_344, _T_338) node _T_346 = and(_T_298, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(_WIRE_1, _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_348, UInt<1>(0h1), "") : assert_3 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(source_ok, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_355 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_355, UInt<1>(0h1), "") : assert_5 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_362, UInt<1>(0h1), "") : assert_7 node _T_366 = not(io.in.a.bits.mask) node _T_367 = eq(_T_366, UInt<1>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_367, UInt<1>(0h1), "") : assert_8 node _T_371 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_371, UInt<1>(0h1), "") : assert_9 node _T_375 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_375 : node _T_376 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_377 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_380 = shr(io.in.a.bits.source, 2) node _T_381 = eq(_T_380, UInt<6>(0h20)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_18) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_386 = shr(io.in.a.bits.source, 2) node _T_387 = eq(_T_386, UInt<6>(0h21)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_19) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_392 = shr(io.in.a.bits.source, 2) node _T_393 = eq(_T_392, UInt<6>(0h22)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_20) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_398 = shr(io.in.a.bits.source, 2) node _T_399 = eq(_T_398, UInt<6>(0h23)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_21) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_403 = and(_T_401, _T_402) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0) node _T_404 = shr(io.in.a.bits.source, 6) node _T_405 = eq(_T_404, UInt<1>(0h1)) node _T_406 = leq(UInt<1>(0h0), uncommonBits_22) node _T_407 = and(_T_405, _T_406) node _T_408 = leq(uncommonBits_22, UInt<6>(0h3f)) node _T_409 = and(_T_407, _T_408) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0) node _T_410 = shr(io.in.a.bits.source, 6) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = leq(UInt<1>(0h0), uncommonBits_23) node _T_413 = and(_T_411, _T_412) node _T_414 = leq(uncommonBits_23, UInt<6>(0h3f)) node _T_415 = and(_T_413, _T_414) node _T_416 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_417 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_418 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_419 = or(_T_379, _T_385) node _T_420 = or(_T_419, _T_391) node _T_421 = or(_T_420, _T_397) node _T_422 = or(_T_421, _T_403) node _T_423 = or(_T_422, _T_409) node _T_424 = or(_T_423, _T_415) node _T_425 = or(_T_424, _T_416) node _T_426 = or(_T_425, _T_417) node _T_427 = or(_T_426, _T_418) node _T_428 = and(_T_378, _T_427) node _T_429 = or(UInt<1>(0h0), _T_428) node _T_430 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<14>(0h2000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<27>(0h4000000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<13>(0h1000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = or(_T_435, _T_440) node _T_472 = or(_T_471, _T_445) node _T_473 = or(_T_472, _T_450) node _T_474 = or(_T_473, _T_455) node _T_475 = or(_T_474, _T_460) node _T_476 = or(_T_475, _T_465) node _T_477 = or(_T_476, _T_470) node _T_478 = and(_T_430, _T_477) node _T_479 = or(UInt<1>(0h0), _T_478) node _T_480 = and(_T_429, _T_479) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_480, UInt<1>(0h1), "") : assert_10 node _T_484 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_485 = shr(io.in.a.bits.source, 2) node _T_486 = eq(_T_485, UInt<6>(0h20)) node _T_487 = leq(UInt<1>(0h0), uncommonBits_24) node _T_488 = and(_T_486, _T_487) node _T_489 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_490 = and(_T_488, _T_489) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_491 = shr(io.in.a.bits.source, 2) node _T_492 = eq(_T_491, UInt<6>(0h21)) node _T_493 = leq(UInt<1>(0h0), uncommonBits_25) node _T_494 = and(_T_492, _T_493) node _T_495 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_496 = and(_T_494, _T_495) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_497 = shr(io.in.a.bits.source, 2) node _T_498 = eq(_T_497, UInt<6>(0h22)) node _T_499 = leq(UInt<1>(0h0), uncommonBits_26) node _T_500 = and(_T_498, _T_499) node _T_501 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_502 = and(_T_500, _T_501) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_503 = shr(io.in.a.bits.source, 2) node _T_504 = eq(_T_503, UInt<6>(0h23)) node _T_505 = leq(UInt<1>(0h0), uncommonBits_27) node _T_506 = and(_T_504, _T_505) node _T_507 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_508 = and(_T_506, _T_507) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0) node _T_509 = shr(io.in.a.bits.source, 6) node _T_510 = eq(_T_509, UInt<1>(0h1)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_28) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_28, UInt<6>(0h3f)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0) node _T_515 = shr(io.in.a.bits.source, 6) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_29) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_29, UInt<6>(0h3f)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_522 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_523 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_484 connect _WIRE_2[1], _T_490 connect _WIRE_2[2], _T_496 connect _WIRE_2[3], _T_502 connect _WIRE_2[4], _T_508 connect _WIRE_2[5], _T_514 connect _WIRE_2[6], _T_520 connect _WIRE_2[7], _T_521 connect _WIRE_2[8], _T_522 connect _WIRE_2[9], _T_523 node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_525 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_527 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_528 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_529 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_531 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_532 = mux(_WIRE_2[7], _T_524, UInt<1>(0h0)) node _T_533 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_534 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_535 = or(_T_525, _T_526) node _T_536 = or(_T_535, _T_527) node _T_537 = or(_T_536, _T_528) node _T_538 = or(_T_537, _T_529) node _T_539 = or(_T_538, _T_530) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_532) node _T_542 = or(_T_541, _T_533) node _T_543 = or(_T_542, _T_534) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_543 node _T_544 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_545 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_546 = and(_T_544, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<14>(0h2000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_554 = cvt(_T_553) node _T_555 = and(_T_554, asSInt(UInt<13>(0h1000))) node _T_556 = asSInt(_T_555) node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0))) node _T_558 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_559 = cvt(_T_558) node _T_560 = and(_T_559, asSInt(UInt<17>(0h10000))) node _T_561 = asSInt(_T_560) node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0))) node _T_563 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_564 = cvt(_T_563) node _T_565 = and(_T_564, asSInt(UInt<18>(0h2f000))) node _T_566 = asSInt(_T_565) node _T_567 = eq(_T_566, asSInt(UInt<1>(0h0))) node _T_568 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_569 = cvt(_T_568) node _T_570 = and(_T_569, asSInt(UInt<17>(0h10000))) node _T_571 = asSInt(_T_570) node _T_572 = eq(_T_571, asSInt(UInt<1>(0h0))) node _T_573 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<27>(0h4000000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<13>(0h1000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = or(_T_552, _T_557) node _T_589 = or(_T_588, _T_562) node _T_590 = or(_T_589, _T_567) node _T_591 = or(_T_590, _T_572) node _T_592 = or(_T_591, _T_577) node _T_593 = or(_T_592, _T_582) node _T_594 = or(_T_593, _T_587) node _T_595 = and(_T_547, _T_594) node _T_596 = or(UInt<1>(0h0), _T_595) node _T_597 = and(_WIRE_3, _T_596) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_597, UInt<1>(0h1), "") : assert_11 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(source_ok, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_604 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_604, UInt<1>(0h1), "") : assert_13 node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(is_aligned, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_611 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_611, UInt<1>(0h1), "") : assert_15 node _T_615 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(_T_615, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_615, UInt<1>(0h1), "") : assert_16 node _T_619 = not(io.in.a.bits.mask) node _T_620 = eq(_T_619, UInt<1>(0h0)) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_620, UInt<1>(0h1), "") : assert_17 node _T_624 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_624, UInt<1>(0h1), "") : assert_18 node _T_628 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_628 : node _T_629 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_630 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_631 = and(_T_629, _T_630) node _T_632 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<6>(0h20)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_30) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_639 = shr(io.in.a.bits.source, 2) node _T_640 = eq(_T_639, UInt<6>(0h21)) node _T_641 = leq(UInt<1>(0h0), uncommonBits_31) node _T_642 = and(_T_640, _T_641) node _T_643 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_644 = and(_T_642, _T_643) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_645 = shr(io.in.a.bits.source, 2) node _T_646 = eq(_T_645, UInt<6>(0h22)) node _T_647 = leq(UInt<1>(0h0), uncommonBits_32) node _T_648 = and(_T_646, _T_647) node _T_649 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_650 = and(_T_648, _T_649) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_651 = shr(io.in.a.bits.source, 2) node _T_652 = eq(_T_651, UInt<6>(0h23)) node _T_653 = leq(UInt<1>(0h0), uncommonBits_33) node _T_654 = and(_T_652, _T_653) node _T_655 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_656 = and(_T_654, _T_655) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0) node _T_657 = shr(io.in.a.bits.source, 6) node _T_658 = eq(_T_657, UInt<1>(0h1)) node _T_659 = leq(UInt<1>(0h0), uncommonBits_34) node _T_660 = and(_T_658, _T_659) node _T_661 = leq(uncommonBits_34, UInt<6>(0h3f)) node _T_662 = and(_T_660, _T_661) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0) node _T_663 = shr(io.in.a.bits.source, 6) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = leq(UInt<1>(0h0), uncommonBits_35) node _T_666 = and(_T_664, _T_665) node _T_667 = leq(uncommonBits_35, UInt<6>(0h3f)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_670 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_671 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_672 = or(_T_632, _T_638) node _T_673 = or(_T_672, _T_644) node _T_674 = or(_T_673, _T_650) node _T_675 = or(_T_674, _T_656) node _T_676 = or(_T_675, _T_662) node _T_677 = or(_T_676, _T_668) node _T_678 = or(_T_677, _T_669) node _T_679 = or(_T_678, _T_670) node _T_680 = or(_T_679, _T_671) node _T_681 = and(_T_631, _T_680) node _T_682 = or(UInt<1>(0h0), _T_681) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_682, UInt<1>(0h1), "") : assert_19 node _T_686 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_687 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_688 = and(_T_686, _T_687) node _T_689 = or(UInt<1>(0h0), _T_688) node _T_690 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<13>(0h1000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = and(_T_689, _T_694) node _T_696 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_697 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_698 = and(_T_696, _T_697) node _T_699 = or(UInt<1>(0h0), _T_698) node _T_700 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<14>(0h2000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<17>(0h10000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<18>(0h2f000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<17>(0h10000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<27>(0h4000000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<13>(0h1000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = or(_T_704, _T_709) node _T_736 = or(_T_735, _T_714) node _T_737 = or(_T_736, _T_719) node _T_738 = or(_T_737, _T_724) node _T_739 = or(_T_738, _T_729) node _T_740 = or(_T_739, _T_734) node _T_741 = and(_T_699, _T_740) node _T_742 = or(UInt<1>(0h0), _T_695) node _T_743 = or(_T_742, _T_741) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_743, UInt<1>(0h1), "") : assert_20 node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(source_ok, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(is_aligned, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_753 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_754 = asUInt(reset) node _T_755 = eq(_T_754, UInt<1>(0h0)) when _T_755 : node _T_756 = eq(_T_753, UInt<1>(0h0)) when _T_756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_753, UInt<1>(0h1), "") : assert_23 node _T_757 = eq(io.in.a.bits.mask, mask) node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(_T_757, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_757, UInt<1>(0h1), "") : assert_24 node _T_761 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_761, UInt<1>(0h1), "") : assert_25 node _T_765 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<6>(0h20)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_36) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<6>(0h21)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_37) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<6>(0h22)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_38) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<6>(0h23)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_39) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0) node _T_794 = shr(io.in.a.bits.source, 6) node _T_795 = eq(_T_794, UInt<1>(0h1)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_40) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_40, UInt<6>(0h3f)) node _T_799 = and(_T_797, _T_798) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0) node _T_800 = shr(io.in.a.bits.source, 6) node _T_801 = eq(_T_800, UInt<1>(0h0)) node _T_802 = leq(UInt<1>(0h0), uncommonBits_41) node _T_803 = and(_T_801, _T_802) node _T_804 = leq(uncommonBits_41, UInt<6>(0h3f)) node _T_805 = and(_T_803, _T_804) node _T_806 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_807 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_808 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_809 = or(_T_769, _T_775) node _T_810 = or(_T_809, _T_781) node _T_811 = or(_T_810, _T_787) node _T_812 = or(_T_811, _T_793) node _T_813 = or(_T_812, _T_799) node _T_814 = or(_T_813, _T_805) node _T_815 = or(_T_814, _T_806) node _T_816 = or(_T_815, _T_807) node _T_817 = or(_T_816, _T_808) node _T_818 = and(_T_768, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = and(_T_823, _T_828) node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_831 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_832 = and(_T_830, _T_831) node _T_833 = or(UInt<1>(0h0), _T_832) node _T_834 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<14>(0h2000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<18>(0h2f000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<27>(0h4000000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<13>(0h1000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_838, _T_843) node _T_865 = or(_T_864, _T_848) node _T_866 = or(_T_865, _T_853) node _T_867 = or(_T_866, _T_858) node _T_868 = or(_T_867, _T_863) node _T_869 = and(_T_833, _T_868) node _T_870 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_871 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<17>(0h10000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = and(_T_870, _T_875) node _T_877 = or(UInt<1>(0h0), _T_829) node _T_878 = or(_T_877, _T_869) node _T_879 = or(_T_878, _T_876) node _T_880 = and(_T_819, _T_879) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_880, UInt<1>(0h1), "") : assert_26 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(source_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(is_aligned, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_890, UInt<1>(0h1), "") : assert_29 node _T_894 = eq(io.in.a.bits.mask, mask) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_894, UInt<1>(0h1), "") : assert_30 node _T_898 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_898 : node _T_899 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_900 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_901 = and(_T_899, _T_900) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_903 = shr(io.in.a.bits.source, 2) node _T_904 = eq(_T_903, UInt<6>(0h20)) node _T_905 = leq(UInt<1>(0h0), uncommonBits_42) node _T_906 = and(_T_904, _T_905) node _T_907 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_908 = and(_T_906, _T_907) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_909 = shr(io.in.a.bits.source, 2) node _T_910 = eq(_T_909, UInt<6>(0h21)) node _T_911 = leq(UInt<1>(0h0), uncommonBits_43) node _T_912 = and(_T_910, _T_911) node _T_913 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_914 = and(_T_912, _T_913) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_915 = shr(io.in.a.bits.source, 2) node _T_916 = eq(_T_915, UInt<6>(0h22)) node _T_917 = leq(UInt<1>(0h0), uncommonBits_44) node _T_918 = and(_T_916, _T_917) node _T_919 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_920 = and(_T_918, _T_919) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_921 = shr(io.in.a.bits.source, 2) node _T_922 = eq(_T_921, UInt<6>(0h23)) node _T_923 = leq(UInt<1>(0h0), uncommonBits_45) node _T_924 = and(_T_922, _T_923) node _T_925 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_926 = and(_T_924, _T_925) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0) node _T_927 = shr(io.in.a.bits.source, 6) node _T_928 = eq(_T_927, UInt<1>(0h1)) node _T_929 = leq(UInt<1>(0h0), uncommonBits_46) node _T_930 = and(_T_928, _T_929) node _T_931 = leq(uncommonBits_46, UInt<6>(0h3f)) node _T_932 = and(_T_930, _T_931) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0) node _T_933 = shr(io.in.a.bits.source, 6) node _T_934 = eq(_T_933, UInt<1>(0h0)) node _T_935 = leq(UInt<1>(0h0), uncommonBits_47) node _T_936 = and(_T_934, _T_935) node _T_937 = leq(uncommonBits_47, UInt<6>(0h3f)) node _T_938 = and(_T_936, _T_937) node _T_939 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_940 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_941 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_942 = or(_T_902, _T_908) node _T_943 = or(_T_942, _T_914) node _T_944 = or(_T_943, _T_920) node _T_945 = or(_T_944, _T_926) node _T_946 = or(_T_945, _T_932) node _T_947 = or(_T_946, _T_938) node _T_948 = or(_T_947, _T_939) node _T_949 = or(_T_948, _T_940) node _T_950 = or(_T_949, _T_941) node _T_951 = and(_T_901, _T_950) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_954 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_955 = and(_T_953, _T_954) node _T_956 = or(UInt<1>(0h0), _T_955) node _T_957 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<13>(0h1000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = and(_T_956, _T_961) node _T_963 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_964 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_965 = and(_T_963, _T_964) node _T_966 = or(UInt<1>(0h0), _T_965) node _T_967 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_968 = cvt(_T_967) node _T_969 = and(_T_968, asSInt(UInt<14>(0h2000))) node _T_970 = asSInt(_T_969) node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0))) node _T_972 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<18>(0h2f000))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<17>(0h10000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<27>(0h4000000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<13>(0h1000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = or(_T_971, _T_976) node _T_998 = or(_T_997, _T_981) node _T_999 = or(_T_998, _T_986) node _T_1000 = or(_T_999, _T_991) node _T_1001 = or(_T_1000, _T_996) node _T_1002 = and(_T_966, _T_1001) node _T_1003 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1004 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = and(_T_1003, _T_1008) node _T_1010 = or(UInt<1>(0h0), _T_962) node _T_1011 = or(_T_1010, _T_1002) node _T_1012 = or(_T_1011, _T_1009) node _T_1013 = and(_T_952, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_31 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(source_ok, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1023 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_34 node _T_1027 = not(mask) node _T_1028 = and(io.in.a.bits.mask, _T_1027) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_35 node _T_1033 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1033 : node _T_1034 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1035 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1038 = shr(io.in.a.bits.source, 2) node _T_1039 = eq(_T_1038, UInt<6>(0h20)) node _T_1040 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1043 = and(_T_1041, _T_1042) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1044 = shr(io.in.a.bits.source, 2) node _T_1045 = eq(_T_1044, UInt<6>(0h21)) node _T_1046 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1049 = and(_T_1047, _T_1048) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1050 = shr(io.in.a.bits.source, 2) node _T_1051 = eq(_T_1050, UInt<6>(0h22)) node _T_1052 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1053 = and(_T_1051, _T_1052) node _T_1054 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1055 = and(_T_1053, _T_1054) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1056 = shr(io.in.a.bits.source, 2) node _T_1057 = eq(_T_1056, UInt<6>(0h23)) node _T_1058 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1061 = and(_T_1059, _T_1060) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0) node _T_1062 = shr(io.in.a.bits.source, 6) node _T_1063 = eq(_T_1062, UInt<1>(0h1)) node _T_1064 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1065 = and(_T_1063, _T_1064) node _T_1066 = leq(uncommonBits_52, UInt<6>(0h3f)) node _T_1067 = and(_T_1065, _T_1066) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0) node _T_1068 = shr(io.in.a.bits.source, 6) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) node _T_1070 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = leq(uncommonBits_53, UInt<6>(0h3f)) node _T_1073 = and(_T_1071, _T_1072) node _T_1074 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1075 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1076 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1077 = or(_T_1037, _T_1043) node _T_1078 = or(_T_1077, _T_1049) node _T_1079 = or(_T_1078, _T_1055) node _T_1080 = or(_T_1079, _T_1061) node _T_1081 = or(_T_1080, _T_1067) node _T_1082 = or(_T_1081, _T_1073) node _T_1083 = or(_T_1082, _T_1074) node _T_1084 = or(_T_1083, _T_1075) node _T_1085 = or(_T_1084, _T_1076) node _T_1086 = and(_T_1036, _T_1085) node _T_1087 = or(UInt<1>(0h0), _T_1086) node _T_1088 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1089 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = or(UInt<1>(0h0), _T_1090) node _T_1092 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1093 = cvt(_T_1092) node _T_1094 = and(_T_1093, asSInt(UInt<14>(0h2000))) node _T_1095 = asSInt(_T_1094) node _T_1096 = eq(_T_1095, asSInt(UInt<1>(0h0))) node _T_1097 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1098 = cvt(_T_1097) node _T_1099 = and(_T_1098, asSInt(UInt<13>(0h1000))) node _T_1100 = asSInt(_T_1099) node _T_1101 = eq(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1103 = cvt(_T_1102) node _T_1104 = and(_T_1103, asSInt(UInt<18>(0h2f000))) node _T_1105 = asSInt(_T_1104) node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0))) node _T_1107 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1108 = cvt(_T_1107) node _T_1109 = and(_T_1108, asSInt(UInt<17>(0h10000))) node _T_1110 = asSInt(_T_1109) node _T_1111 = eq(_T_1110, asSInt(UInt<1>(0h0))) node _T_1112 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<13>(0h1000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1118 = cvt(_T_1117) node _T_1119 = and(_T_1118, asSInt(UInt<27>(0h4000000))) node _T_1120 = asSInt(_T_1119) node _T_1121 = eq(_T_1120, asSInt(UInt<1>(0h0))) node _T_1122 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1123 = cvt(_T_1122) node _T_1124 = and(_T_1123, asSInt(UInt<13>(0h1000))) node _T_1125 = asSInt(_T_1124) node _T_1126 = eq(_T_1125, asSInt(UInt<1>(0h0))) node _T_1127 = or(_T_1096, _T_1101) node _T_1128 = or(_T_1127, _T_1106) node _T_1129 = or(_T_1128, _T_1111) node _T_1130 = or(_T_1129, _T_1116) node _T_1131 = or(_T_1130, _T_1121) node _T_1132 = or(_T_1131, _T_1126) node _T_1133 = and(_T_1091, _T_1132) node _T_1134 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1135 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1136 = cvt(_T_1135) node _T_1137 = and(_T_1136, asSInt(UInt<17>(0h10000))) node _T_1138 = asSInt(_T_1137) node _T_1139 = eq(_T_1138, asSInt(UInt<1>(0h0))) node _T_1140 = and(_T_1134, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1133) node _T_1142 = or(_T_1141, _T_1140) node _T_1143 = and(_T_1087, _T_1142) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_36 node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(source_ok, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(is_aligned, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1153 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_39 node _T_1157 = eq(io.in.a.bits.mask, mask) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_40 node _T_1161 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1161 : node _T_1162 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1163 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1164 = and(_T_1162, _T_1163) node _T_1165 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1166 = shr(io.in.a.bits.source, 2) node _T_1167 = eq(_T_1166, UInt<6>(0h20)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1171 = and(_T_1169, _T_1170) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1172 = shr(io.in.a.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<6>(0h21)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1178 = shr(io.in.a.bits.source, 2) node _T_1179 = eq(_T_1178, UInt<6>(0h22)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1184 = shr(io.in.a.bits.source, 2) node _T_1185 = eq(_T_1184, UInt<6>(0h23)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0) node _T_1190 = shr(io.in.a.bits.source, 6) node _T_1191 = eq(_T_1190, UInt<1>(0h1)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_58, UInt<6>(0h3f)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0) node _T_1196 = shr(io.in.a.bits.source, 6) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_59, UInt<6>(0h3f)) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1203 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1204 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1205 = or(_T_1165, _T_1171) node _T_1206 = or(_T_1205, _T_1177) node _T_1207 = or(_T_1206, _T_1183) node _T_1208 = or(_T_1207, _T_1189) node _T_1209 = or(_T_1208, _T_1195) node _T_1210 = or(_T_1209, _T_1201) node _T_1211 = or(_T_1210, _T_1202) node _T_1212 = or(_T_1211, _T_1203) node _T_1213 = or(_T_1212, _T_1204) node _T_1214 = and(_T_1164, _T_1213) node _T_1215 = or(UInt<1>(0h0), _T_1214) node _T_1216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1217 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = or(UInt<1>(0h0), _T_1218) node _T_1220 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<14>(0h2000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<18>(0h2f000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<17>(0h10000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<13>(0h1000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1246 = cvt(_T_1245) node _T_1247 = and(_T_1246, asSInt(UInt<27>(0h4000000))) node _T_1248 = asSInt(_T_1247) node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0))) node _T_1250 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = or(_T_1224, _T_1229) node _T_1256 = or(_T_1255, _T_1234) node _T_1257 = or(_T_1256, _T_1239) node _T_1258 = or(_T_1257, _T_1244) node _T_1259 = or(_T_1258, _T_1249) node _T_1260 = or(_T_1259, _T_1254) node _T_1261 = and(_T_1219, _T_1260) node _T_1262 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1263 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = and(_T_1262, _T_1267) node _T_1269 = or(UInt<1>(0h0), _T_1261) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = and(_T_1215, _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_41 node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(source_ok, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(is_aligned, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1281 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_44 node _T_1285 = eq(io.in.a.bits.mask, mask) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_45 node _T_1289 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1289 : node _T_1290 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1291 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1292 = and(_T_1290, _T_1291) node _T_1293 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1294 = shr(io.in.a.bits.source, 2) node _T_1295 = eq(_T_1294, UInt<6>(0h20)) node _T_1296 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1297 = and(_T_1295, _T_1296) node _T_1298 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1299 = and(_T_1297, _T_1298) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1300 = shr(io.in.a.bits.source, 2) node _T_1301 = eq(_T_1300, UInt<6>(0h21)) node _T_1302 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1303 = and(_T_1301, _T_1302) node _T_1304 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1305 = and(_T_1303, _T_1304) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1306 = shr(io.in.a.bits.source, 2) node _T_1307 = eq(_T_1306, UInt<6>(0h22)) node _T_1308 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1309 = and(_T_1307, _T_1308) node _T_1310 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1311 = and(_T_1309, _T_1310) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1312 = shr(io.in.a.bits.source, 2) node _T_1313 = eq(_T_1312, UInt<6>(0h23)) node _T_1314 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1315 = and(_T_1313, _T_1314) node _T_1316 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1317 = and(_T_1315, _T_1316) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0) node _T_1318 = shr(io.in.a.bits.source, 6) node _T_1319 = eq(_T_1318, UInt<1>(0h1)) node _T_1320 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1321 = and(_T_1319, _T_1320) node _T_1322 = leq(uncommonBits_64, UInt<6>(0h3f)) node _T_1323 = and(_T_1321, _T_1322) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0) node _T_1324 = shr(io.in.a.bits.source, 6) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) node _T_1326 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = leq(uncommonBits_65, UInt<6>(0h3f)) node _T_1329 = and(_T_1327, _T_1328) node _T_1330 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1331 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1332 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1333 = or(_T_1293, _T_1299) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1311) node _T_1336 = or(_T_1335, _T_1317) node _T_1337 = or(_T_1336, _T_1323) node _T_1338 = or(_T_1337, _T_1329) node _T_1339 = or(_T_1338, _T_1330) node _T_1340 = or(_T_1339, _T_1331) node _T_1341 = or(_T_1340, _T_1332) node _T_1342 = and(_T_1292, _T_1341) node _T_1343 = or(UInt<1>(0h0), _T_1342) node _T_1344 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1345 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = or(UInt<1>(0h0), _T_1346) node _T_1348 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<13>(0h1000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = and(_T_1347, _T_1352) node _T_1354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1355 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1356 = cvt(_T_1355) node _T_1357 = and(_T_1356, asSInt(UInt<14>(0h2000))) node _T_1358 = asSInt(_T_1357) node _T_1359 = eq(_T_1358, asSInt(UInt<1>(0h0))) node _T_1360 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1361 = cvt(_T_1360) node _T_1362 = and(_T_1361, asSInt(UInt<17>(0h10000))) node _T_1363 = asSInt(_T_1362) node _T_1364 = eq(_T_1363, asSInt(UInt<1>(0h0))) node _T_1365 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1366 = cvt(_T_1365) node _T_1367 = and(_T_1366, asSInt(UInt<18>(0h2f000))) node _T_1368 = asSInt(_T_1367) node _T_1369 = eq(_T_1368, asSInt(UInt<1>(0h0))) node _T_1370 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<17>(0h10000))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1376 = cvt(_T_1375) node _T_1377 = and(_T_1376, asSInt(UInt<13>(0h1000))) node _T_1378 = asSInt(_T_1377) node _T_1379 = eq(_T_1378, asSInt(UInt<1>(0h0))) node _T_1380 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<27>(0h4000000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = or(_T_1359, _T_1364) node _T_1391 = or(_T_1390, _T_1369) node _T_1392 = or(_T_1391, _T_1374) node _T_1393 = or(_T_1392, _T_1379) node _T_1394 = or(_T_1393, _T_1384) node _T_1395 = or(_T_1394, _T_1389) node _T_1396 = and(_T_1354, _T_1395) node _T_1397 = or(UInt<1>(0h0), _T_1353) node _T_1398 = or(_T_1397, _T_1396) node _T_1399 = and(_T_1343, _T_1398) node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(_T_1399, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1399, UInt<1>(0h1), "") : assert_46 node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(source_ok, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1406 = asUInt(reset) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) when _T_1407 : node _T_1408 = eq(is_aligned, UInt<1>(0h0)) when _T_1408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1409 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_49 node _T_1413 = eq(io.in.a.bits.mask, mask) node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(_T_1413, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1413, UInt<1>(0h1), "") : assert_50 node _T_1417 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1418 = asUInt(reset) node _T_1419 = eq(_T_1418, UInt<1>(0h0)) when _T_1419 : node _T_1420 = eq(_T_1417, UInt<1>(0h0)) when _T_1420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1417, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1421 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_52 node _source_ok_T_48 = eq(io.in.d.bits.source, UInt<8>(0h90)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<6>(0h20)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<6>(0h21)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<6>(0h22)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<6>(0h23)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 6) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<1>(0h1)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 6) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<8>(0ha0)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<8>(0ha1)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha2)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_48 connect _source_ok_WIRE_1[1], _source_ok_T_54 connect _source_ok_WIRE_1[2], _source_ok_T_60 connect _source_ok_WIRE_1[3], _source_ok_T_66 connect _source_ok_WIRE_1[4], _source_ok_T_72 connect _source_ok_WIRE_1[5], _source_ok_T_78 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 node _source_ok_T_88 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[2]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[3]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[4]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[5]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[6]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[7]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_95, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1425 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1425 : node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(source_ok_1, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1429 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_54 node _T_1433 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_55 node _T_1437 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(_T_1437, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1437, UInt<1>(0h1), "") : assert_56 node _T_1441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_57 node _T_1445 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1445 : node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok_1, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(sink_ok, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1452 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_60 node _T_1456 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_61 node _T_1460 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_62 node _T_1464 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_63 node _T_1468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1469 = or(UInt<1>(0h1), _T_1468) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_64 node _T_1473 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1473 : node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok_1, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(sink_ok, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1480 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_67 node _T_1484 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_68 node _T_1488 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_69 node _T_1492 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1493 = or(_T_1492, io.in.d.bits.corrupt) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_70 node _T_1497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1498 = or(UInt<1>(0h1), _T_1497) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_71 node _T_1502 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1502 : node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(source_ok_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1506 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(_T_1506, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1506, UInt<1>(0h1), "") : assert_73 node _T_1510 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_74 node _T_1514 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1515 = or(UInt<1>(0h1), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_75 node _T_1519 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1519 : node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(source_ok_1, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1523 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_77 node _T_1527 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1528 = or(_T_1527, io.in.d.bits.corrupt) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_78 node _T_1532 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1533 = or(UInt<1>(0h1), _T_1532) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_79 node _T_1537 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1537 : node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(source_ok_1, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1541 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1542 = asUInt(reset) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) when _T_1543 : node _T_1544 = eq(_T_1541, UInt<1>(0h0)) when _T_1544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1541, UInt<1>(0h1), "") : assert_81 node _T_1545 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_82 node _T_1549 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1550 = or(UInt<1>(0h1), _T_1549) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.mask, UInt<16>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1554 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1558 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(_T_1558, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1558, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1562 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1566 = eq(a_first, UInt<1>(0h0)) node _T_1567 = and(io.in.a.valid, _T_1566) when _T_1567 : node _T_1568 = eq(io.in.a.bits.opcode, opcode) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_87 node _T_1572 = eq(io.in.a.bits.param, param) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_88 node _T_1576 = eq(io.in.a.bits.size, size) node _T_1577 = asUInt(reset) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(_T_1576, UInt<1>(0h0)) when _T_1579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1576, UInt<1>(0h1), "") : assert_89 node _T_1580 = eq(io.in.a.bits.source, source) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_90 node _T_1584 = eq(io.in.a.bits.address, address) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_91 node _T_1588 = and(io.in.a.ready, io.in.a.valid) node _T_1589 = and(_T_1588, a_first) when _T_1589 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1590 = eq(d_first, UInt<1>(0h0)) node _T_1591 = and(io.in.d.valid, _T_1590) when _T_1591 : node _T_1592 = eq(io.in.d.bits.opcode, opcode_1) node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(_T_1592, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1592, UInt<1>(0h1), "") : assert_92 node _T_1596 = eq(io.in.d.bits.param, param_1) node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(_T_1596, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1596, UInt<1>(0h1), "") : assert_93 node _T_1600 = eq(io.in.d.bits.size, size_1) node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(_T_1600, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1600, UInt<1>(0h1), "") : assert_94 node _T_1604 = eq(io.in.d.bits.source, source_1) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_95 node _T_1608 = eq(io.in.d.bits.sink, sink) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_96 node _T_1612 = eq(io.in.d.bits.denied, denied) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_97 node _T_1616 = and(io.in.d.ready, io.in.d.valid) node _T_1617 = and(_T_1616, d_first) when _T_1617 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<163>, clock, reset, UInt<163>(0h0) regreset inflight_opcodes : UInt<652>, clock, reset, UInt<652>(0h0) regreset inflight_sizes : UInt<1304>, clock, reset, UInt<1304>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<163> connect a_set, UInt<163>(0h0) wire a_set_wo_ready : UInt<163> connect a_set_wo_ready, UInt<163>(0h0) wire a_opcodes_set : UInt<652> connect a_opcodes_set, UInt<652>(0h0) wire a_sizes_set : UInt<1304> connect a_sizes_set, UInt<1304>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1618 = and(io.in.a.valid, a_first_1) node _T_1619 = and(_T_1618, UInt<1>(0h1)) when _T_1619 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1620 = and(io.in.a.ready, io.in.a.valid) node _T_1621 = and(_T_1620, a_first_1) node _T_1622 = and(_T_1621, UInt<1>(0h1)) when _T_1622 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1623 = dshr(inflight, io.in.a.bits.source) node _T_1624 = bits(_T_1623, 0, 0) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) node _T_1626 = asUInt(reset) node _T_1627 = eq(_T_1626, UInt<1>(0h0)) when _T_1627 : node _T_1628 = eq(_T_1625, UInt<1>(0h0)) when _T_1628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1625, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<163> connect d_clr, UInt<163>(0h0) wire d_clr_wo_ready : UInt<163> connect d_clr_wo_ready, UInt<163>(0h0) wire d_opcodes_clr : UInt<652> connect d_opcodes_clr, UInt<652>(0h0) wire d_sizes_clr : UInt<1304> connect d_sizes_clr, UInt<1304>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1629 = and(io.in.d.valid, d_first_1) node _T_1630 = and(_T_1629, UInt<1>(0h1)) node _T_1631 = eq(d_release_ack, UInt<1>(0h0)) node _T_1632 = and(_T_1630, _T_1631) when _T_1632 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1633 = and(io.in.d.ready, io.in.d.valid) node _T_1634 = and(_T_1633, d_first_1) node _T_1635 = and(_T_1634, UInt<1>(0h1)) node _T_1636 = eq(d_release_ack, UInt<1>(0h0)) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1638 = and(io.in.d.valid, d_first_1) node _T_1639 = and(_T_1638, UInt<1>(0h1)) node _T_1640 = eq(d_release_ack, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1642 = dshr(inflight, io.in.d.bits.source) node _T_1643 = bits(_T_1642, 0, 0) node _T_1644 = or(_T_1643, same_cycle_resp) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1648 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1649 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1650 = or(_T_1648, _T_1649) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_100 node _T_1654 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_101 else : node _T_1658 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1659 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1660 = or(_T_1658, _T_1659) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_102 node _T_1664 = eq(io.in.d.bits.size, a_size_lookup) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_103 node _T_1668 = and(io.in.d.valid, d_first_1) node _T_1669 = and(_T_1668, a_first_1) node _T_1670 = and(_T_1669, io.in.a.valid) node _T_1671 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = eq(d_release_ack, UInt<1>(0h0)) node _T_1674 = and(_T_1672, _T_1673) when _T_1674 : node _T_1675 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1676 = or(_T_1675, io.in.a.ready) node _T_1677 = asUInt(reset) node _T_1678 = eq(_T_1677, UInt<1>(0h0)) when _T_1678 : node _T_1679 = eq(_T_1676, UInt<1>(0h0)) when _T_1679 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1676, UInt<1>(0h1), "") : assert_104 node _T_1680 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1681 = orr(a_set_wo_ready) node _T_1682 = eq(_T_1681, UInt<1>(0h0)) node _T_1683 = or(_T_1680, _T_1682) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_6 node _T_1687 = orr(inflight) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) node _T_1689 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1690 = or(_T_1688, _T_1689) node _T_1691 = lt(watchdog, plusarg_reader.out) node _T_1692 = or(_T_1690, _T_1691) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1696 = and(io.in.a.ready, io.in.a.valid) node _T_1697 = and(io.in.d.ready, io.in.d.valid) node _T_1698 = or(_T_1696, _T_1697) when _T_1698 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<163>, clock, reset, UInt<163>(0h0) regreset inflight_opcodes_1 : UInt<652>, clock, reset, UInt<652>(0h0) regreset inflight_sizes_1 : UInt<1304>, clock, reset, UInt<1304>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<163> connect c_set, UInt<163>(0h0) wire c_set_wo_ready : UInt<163> connect c_set_wo_ready, UInt<163>(0h0) wire c_opcodes_set : UInt<652> connect c_opcodes_set, UInt<652>(0h0) wire c_sizes_set : UInt<1304> connect c_sizes_set, UInt<1304>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1699 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1700 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1701 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1702 = and(_T_1700, _T_1701) node _T_1703 = and(_T_1699, _T_1702) when _T_1703 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1704 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1705 = and(_T_1704, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1706 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1707 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1708 = and(_T_1706, _T_1707) node _T_1709 = and(_T_1705, _T_1708) when _T_1709 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1710 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1711 = bits(_T_1710, 0, 0) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) node _T_1713 = asUInt(reset) node _T_1714 = eq(_T_1713, UInt<1>(0h0)) when _T_1714 : node _T_1715 = eq(_T_1712, UInt<1>(0h0)) when _T_1715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1712, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<163> connect d_clr_1, UInt<163>(0h0) wire d_clr_wo_ready_1 : UInt<163> connect d_clr_wo_ready_1, UInt<163>(0h0) wire d_opcodes_clr_1 : UInt<652> connect d_opcodes_clr_1, UInt<652>(0h0) wire d_sizes_clr_1 : UInt<1304> connect d_sizes_clr_1, UInt<1304>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1716 = and(io.in.d.valid, d_first_2) node _T_1717 = and(_T_1716, UInt<1>(0h1)) node _T_1718 = and(_T_1717, d_release_ack_1) when _T_1718 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1719 = and(io.in.d.ready, io.in.d.valid) node _T_1720 = and(_T_1719, d_first_2) node _T_1721 = and(_T_1720, UInt<1>(0h1)) node _T_1722 = and(_T_1721, d_release_ack_1) when _T_1722 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1723 = and(io.in.d.valid, d_first_2) node _T_1724 = and(_T_1723, UInt<1>(0h1)) node _T_1725 = and(_T_1724, d_release_ack_1) when _T_1725 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1726 = dshr(inflight_1, io.in.d.bits.source) node _T_1727 = bits(_T_1726, 0, 0) node _T_1728 = or(_T_1727, same_cycle_resp_1) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1732 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1733 = asUInt(reset) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) when _T_1734 : node _T_1735 = eq(_T_1732, UInt<1>(0h0)) when _T_1735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1732, UInt<1>(0h1), "") : assert_109 else : node _T_1736 = eq(io.in.d.bits.size, c_size_lookup) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_110 node _T_1740 = and(io.in.d.valid, d_first_2) node _T_1741 = and(_T_1740, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1742 = and(_T_1741, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1743 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1744 = and(_T_1742, _T_1743) node _T_1745 = and(_T_1744, d_release_ack_1) node _T_1746 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1747 = and(_T_1745, _T_1746) when _T_1747 : node _T_1748 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<128>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1749 = or(_T_1748, _WIRE_27.ready) node _T_1750 = asUInt(reset) node _T_1751 = eq(_T_1750, UInt<1>(0h0)) when _T_1751 : node _T_1752 = eq(_T_1749, UInt<1>(0h0)) when _T_1752 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1749, UInt<1>(0h1), "") : assert_111 node _T_1753 = orr(c_set_wo_ready) when _T_1753 : node _T_1754 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1755 = asUInt(reset) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) when _T_1756 : node _T_1757 = eq(_T_1754, UInt<1>(0h0)) when _T_1757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1754, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_7 node _T_1758 = orr(inflight_1) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1761 = or(_T_1759, _T_1760) node _T_1762 = lt(watchdog_1, plusarg_reader_1.out) node _T_1763 = or(_T_1761, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<128>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1767 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1768 = and(io.in.d.ready, io.in.d.valid) node _T_1769 = or(_T_1767, _T_1768) when _T_1769 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1303:0] c_sizes_set = 1304'h0; // @[Monitor.scala:741:34] wire [651:0] c_opcodes_set = 652'h0; // @[Monitor.scala:740:34] wire [162:0] c_set = 163'h0; // @[Monitor.scala:738:34] wire [162:0] c_set_wo_ready = 163'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_25 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_31 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_47 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_49 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_55 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_50 = _source_ok_T_49 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_73 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_79 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire _source_ok_T_74 = _source_ok_T_73 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_89 = _source_ok_T_88 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_90 = _source_ok_T_89 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_91 = _source_ok_T_90 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_95 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1696 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1696; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1696; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1769 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1769; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1769; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1769; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [162:0] inflight; // @[Monitor.scala:614:27] reg [651:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1303:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [162:0] a_set; // @[Monitor.scala:626:34] wire [162:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [651:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1303:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [651:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [651:0] _a_opcode_lookup_T_6 = {648'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [651:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1303:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1303:0] _a_size_lookup_T_6 = {1296'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1303:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1303:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1622 = _T_1696 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1622 ? _a_set_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1622 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1622 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1622 ? _a_opcodes_set_T_1[651:0] : 652'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1622 ? _a_sizes_set_T_1[1303:0] : 1304'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [162:0] d_clr; // @[Monitor.scala:664:34] wire [162:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [651:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1303:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1668 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1668 & ~d_release_ack ? _d_clr_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1637 = _T_1769 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1637 ? _d_clr_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1637 ? _d_opcodes_clr_T_5[651:0] : 652'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1637 ? _d_sizes_clr_T_5[1303:0] : 1304'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [162:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [162:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [162:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [651:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [651:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [651:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1303:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1303:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1303:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [162:0] inflight_1; // @[Monitor.scala:726:35] wire [162:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [651:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [651:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1303:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1303:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [651:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [651:0] _c_opcode_lookup_T_6 = {648'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [651:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1303:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1303:0] _c_size_lookup_T_6 = {1296'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1303:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1303:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [162:0] d_clr_1; // @[Monitor.scala:774:34] wire [162:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [651:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1303:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1740 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1740 & d_release_ack_1 ? _d_clr_wo_ready_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1722 = _T_1769 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1722 ? _d_clr_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1722 ? _d_opcodes_clr_T_11[651:0] : 652'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1722 ? _d_sizes_clr_T_11[1303:0] : 1304'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [162:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [162:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [651:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [651:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1303:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1303:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AXI4UserYanker : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.extra_id invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.extra_id invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.extra_id invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.extra_id invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in inst Queue8_BundleMap of Queue8_BundleMap connect Queue8_BundleMap.clock, clock connect Queue8_BundleMap.reset, reset inst Queue8_BundleMap_1 of Queue8_BundleMap_1 connect Queue8_BundleMap_1.clock, clock connect Queue8_BundleMap_1.reset, reset inst Queue8_BundleMap_2 of Queue8_BundleMap_2 connect Queue8_BundleMap_2.clock, clock connect Queue8_BundleMap_2.reset, reset inst Queue8_BundleMap_3 of Queue8_BundleMap_3 connect Queue8_BundleMap_3.clock, clock connect Queue8_BundleMap_3.reset, reset inst Queue7_BundleMap of Queue7_BundleMap connect Queue7_BundleMap.clock, clock connect Queue7_BundleMap.reset, reset inst Queue7_BundleMap_1 of Queue7_BundleMap_1 connect Queue7_BundleMap_1.clock, clock connect Queue7_BundleMap_1.reset, reset inst Queue7_BundleMap_2 of Queue7_BundleMap_2 connect Queue7_BundleMap_2.clock, clock connect Queue7_BundleMap_2.reset, reset inst Queue7_BundleMap_3 of Queue7_BundleMap_3 connect Queue7_BundleMap_3.clock, clock connect Queue7_BundleMap_3.reset, reset inst Queue7_BundleMap_4 of Queue7_BundleMap_4 connect Queue7_BundleMap_4.clock, clock connect Queue7_BundleMap_4.reset, reset inst Queue7_BundleMap_5 of Queue7_BundleMap_5 connect Queue7_BundleMap_5.clock, clock connect Queue7_BundleMap_5.reset, reset inst Queue7_BundleMap_6 of Queue7_BundleMap_6 connect Queue7_BundleMap_6.clock, clock connect Queue7_BundleMap_6.reset, reset inst Queue7_BundleMap_7 of Queue7_BundleMap_7 connect Queue7_BundleMap_7.clock, clock connect Queue7_BundleMap_7.reset, reset inst Queue7_BundleMap_8 of Queue7_BundleMap_8 connect Queue7_BundleMap_8.clock, clock connect Queue7_BundleMap_8.reset, reset inst Queue7_BundleMap_9 of Queue7_BundleMap_9 connect Queue7_BundleMap_9.clock, clock connect Queue7_BundleMap_9.reset, reset inst Queue7_BundleMap_10 of Queue7_BundleMap_10 connect Queue7_BundleMap_10.clock, clock connect Queue7_BundleMap_10.reset, reset inst Queue7_BundleMap_11 of Queue7_BundleMap_11 connect Queue7_BundleMap_11.clock, clock connect Queue7_BundleMap_11.reset, reset inst Queue8_BundleMap_4 of Queue8_BundleMap_4 connect Queue8_BundleMap_4.clock, clock connect Queue8_BundleMap_4.reset, reset inst Queue8_BundleMap_5 of Queue8_BundleMap_5 connect Queue8_BundleMap_5.clock, clock connect Queue8_BundleMap_5.reset, reset inst Queue8_BundleMap_6 of Queue8_BundleMap_6 connect Queue8_BundleMap_6.clock, clock connect Queue8_BundleMap_6.reset, reset inst Queue8_BundleMap_7 of Queue8_BundleMap_7 connect Queue8_BundleMap_7.clock, clock connect Queue8_BundleMap_7.reset, reset inst Queue7_BundleMap_12 of Queue7_BundleMap_12 connect Queue7_BundleMap_12.clock, clock connect Queue7_BundleMap_12.reset, reset inst Queue7_BundleMap_13 of Queue7_BundleMap_13 connect Queue7_BundleMap_13.clock, clock connect Queue7_BundleMap_13.reset, reset inst Queue7_BundleMap_14 of Queue7_BundleMap_14 connect Queue7_BundleMap_14.clock, clock connect Queue7_BundleMap_14.reset, reset inst Queue7_BundleMap_15 of Queue7_BundleMap_15 connect Queue7_BundleMap_15.clock, clock connect Queue7_BundleMap_15.reset, reset inst Queue7_BundleMap_16 of Queue7_BundleMap_16 connect Queue7_BundleMap_16.clock, clock connect Queue7_BundleMap_16.reset, reset inst Queue7_BundleMap_17 of Queue7_BundleMap_17 connect Queue7_BundleMap_17.clock, clock connect Queue7_BundleMap_17.reset, reset inst Queue7_BundleMap_18 of Queue7_BundleMap_18 connect Queue7_BundleMap_18.clock, clock connect Queue7_BundleMap_18.reset, reset inst Queue7_BundleMap_19 of Queue7_BundleMap_19 connect Queue7_BundleMap_19.clock, clock connect Queue7_BundleMap_19.reset, reset inst Queue7_BundleMap_20 of Queue7_BundleMap_20 connect Queue7_BundleMap_20.clock, clock connect Queue7_BundleMap_20.reset, reset inst Queue7_BundleMap_21 of Queue7_BundleMap_21 connect Queue7_BundleMap_21.clock, clock connect Queue7_BundleMap_21.reset, reset inst Queue7_BundleMap_22 of Queue7_BundleMap_22 connect Queue7_BundleMap_22.clock, clock connect Queue7_BundleMap_22.reset, reset inst Queue7_BundleMap_23 of Queue7_BundleMap_23 connect Queue7_BundleMap_23.clock, clock connect Queue7_BundleMap_23.reset, reset wire _ar_ready_WIRE : UInt<1>[16] connect _ar_ready_WIRE[0], Queue8_BundleMap.io.enq.ready connect _ar_ready_WIRE[1], Queue8_BundleMap_1.io.enq.ready connect _ar_ready_WIRE[2], Queue8_BundleMap_2.io.enq.ready connect _ar_ready_WIRE[3], Queue8_BundleMap_3.io.enq.ready connect _ar_ready_WIRE[4], Queue7_BundleMap.io.enq.ready connect _ar_ready_WIRE[5], Queue7_BundleMap_1.io.enq.ready connect _ar_ready_WIRE[6], Queue7_BundleMap_2.io.enq.ready connect _ar_ready_WIRE[7], Queue7_BundleMap_3.io.enq.ready connect _ar_ready_WIRE[8], Queue7_BundleMap_4.io.enq.ready connect _ar_ready_WIRE[9], Queue7_BundleMap_5.io.enq.ready connect _ar_ready_WIRE[10], Queue7_BundleMap_6.io.enq.ready connect _ar_ready_WIRE[11], Queue7_BundleMap_7.io.enq.ready connect _ar_ready_WIRE[12], Queue7_BundleMap_8.io.enq.ready connect _ar_ready_WIRE[13], Queue7_BundleMap_9.io.enq.ready connect _ar_ready_WIRE[14], Queue7_BundleMap_10.io.enq.ready connect _ar_ready_WIRE[15], Queue7_BundleMap_11.io.enq.ready node _nodeIn_ar_ready_T = and(nodeOut.ar.ready, _ar_ready_WIRE[nodeIn.ar.bits.id]) connect nodeIn.ar.ready, _nodeIn_ar_ready_T node _nodeOut_ar_valid_T = and(nodeIn.ar.valid, _ar_ready_WIRE[nodeIn.ar.bits.id]) connect nodeOut.ar.valid, _nodeOut_ar_valid_T connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id wire _r_valid_WIRE : UInt<1>[16] connect _r_valid_WIRE[0], Queue8_BundleMap.io.deq.valid connect _r_valid_WIRE[1], Queue8_BundleMap_1.io.deq.valid connect _r_valid_WIRE[2], Queue8_BundleMap_2.io.deq.valid connect _r_valid_WIRE[3], Queue8_BundleMap_3.io.deq.valid connect _r_valid_WIRE[4], Queue7_BundleMap.io.deq.valid connect _r_valid_WIRE[5], Queue7_BundleMap_1.io.deq.valid connect _r_valid_WIRE[6], Queue7_BundleMap_2.io.deq.valid connect _r_valid_WIRE[7], Queue7_BundleMap_3.io.deq.valid connect _r_valid_WIRE[8], Queue7_BundleMap_4.io.deq.valid connect _r_valid_WIRE[9], Queue7_BundleMap_5.io.deq.valid connect _r_valid_WIRE[10], Queue7_BundleMap_6.io.deq.valid connect _r_valid_WIRE[11], Queue7_BundleMap_7.io.deq.valid connect _r_valid_WIRE[12], Queue7_BundleMap_8.io.deq.valid connect _r_valid_WIRE[13], Queue7_BundleMap_9.io.deq.valid connect _r_valid_WIRE[14], Queue7_BundleMap_10.io.deq.valid connect _r_valid_WIRE[15], Queue7_BundleMap_11.io.deq.valid wire _r_bits_WIRE : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}[16] connect _r_bits_WIRE[0], Queue8_BundleMap.io.deq.bits connect _r_bits_WIRE[1], Queue8_BundleMap_1.io.deq.bits connect _r_bits_WIRE[2], Queue8_BundleMap_2.io.deq.bits connect _r_bits_WIRE[3], Queue8_BundleMap_3.io.deq.bits connect _r_bits_WIRE[4], Queue7_BundleMap.io.deq.bits connect _r_bits_WIRE[5], Queue7_BundleMap_1.io.deq.bits connect _r_bits_WIRE[6], Queue7_BundleMap_2.io.deq.bits connect _r_bits_WIRE[7], Queue7_BundleMap_3.io.deq.bits connect _r_bits_WIRE[8], Queue7_BundleMap_4.io.deq.bits connect _r_bits_WIRE[9], Queue7_BundleMap_5.io.deq.bits connect _r_bits_WIRE[10], Queue7_BundleMap_6.io.deq.bits connect _r_bits_WIRE[11], Queue7_BundleMap_7.io.deq.bits connect _r_bits_WIRE[12], Queue7_BundleMap_8.io.deq.bits connect _r_bits_WIRE[13], Queue7_BundleMap_9.io.deq.bits connect _r_bits_WIRE[14], Queue7_BundleMap_10.io.deq.bits connect _r_bits_WIRE[15], Queue7_BundleMap_11.io.deq.bits node _T = eq(nodeOut.r.valid, UInt<1>(0h0)) node _T_1 = or(_T, _r_valid_WIRE[nodeOut.r.bits.id]) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at UserYanker.scala:69 assert (!out.r.valid \|\| r_valid) // Q must be ready faster than the response\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready connect nodeIn.r.bits.echo.extra_id, _r_bits_WIRE[nodeOut.r.bits.id].extra_id connect nodeIn.r.bits.echo.tl_state.source, _r_bits_WIRE[nodeOut.r.bits.id].tl_state.source connect nodeIn.r.bits.echo.tl_state.size, _r_bits_WIRE[nodeOut.r.bits.id].tl_state.size node arsel_shiftAmount = bits(nodeIn.ar.bits.id, 3, 0) node _arsel_T = dshl(UInt<1>(0h1), arsel_shiftAmount) node _arsel_T_1 = bits(_arsel_T, 15, 0) node arsel_0 = bits(_arsel_T_1, 0, 0) node arsel_1 = bits(_arsel_T_1, 1, 1) node arsel_2 = bits(_arsel_T_1, 2, 2) node arsel_3 = bits(_arsel_T_1, 3, 3) node arsel_4 = bits(_arsel_T_1, 4, 4) node arsel_5 = bits(_arsel_T_1, 5, 5) node arsel_6 = bits(_arsel_T_1, 6, 6) node arsel_7 = bits(_arsel_T_1, 7, 7) node arsel_8 = bits(_arsel_T_1, 8, 8) node arsel_9 = bits(_arsel_T_1, 9, 9) node arsel_10 = bits(_arsel_T_1, 10, 10) node arsel_11 = bits(_arsel_T_1, 11, 11) node arsel_12 = bits(_arsel_T_1, 12, 12) node arsel_13 = bits(_arsel_T_1, 13, 13) node arsel_14 = bits(_arsel_T_1, 14, 14) node arsel_15 = bits(_arsel_T_1, 15, 15) node rsel_shiftAmount = bits(nodeOut.r.bits.id, 3, 0) node _rsel_T = dshl(UInt<1>(0h1), rsel_shiftAmount) node _rsel_T_1 = bits(_rsel_T, 15, 0) node rsel_0 = bits(_rsel_T_1, 0, 0) node rsel_1 = bits(_rsel_T_1, 1, 1) node rsel_2 = bits(_rsel_T_1, 2, 2) node rsel_3 = bits(_rsel_T_1, 3, 3) node rsel_4 = bits(_rsel_T_1, 4, 4) node rsel_5 = bits(_rsel_T_1, 5, 5) node rsel_6 = bits(_rsel_T_1, 6, 6) node rsel_7 = bits(_rsel_T_1, 7, 7) node rsel_8 = bits(_rsel_T_1, 8, 8) node rsel_9 = bits(_rsel_T_1, 9, 9) node rsel_10 = bits(_rsel_T_1, 10, 10) node rsel_11 = bits(_rsel_T_1, 11, 11) node rsel_12 = bits(_rsel_T_1, 12, 12) node rsel_13 = bits(_rsel_T_1, 13, 13) node rsel_14 = bits(_rsel_T_1, 14, 14) node rsel_15 = bits(_rsel_T_1, 15, 15) node _T_5 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_6 = and(_T_5, rsel_0) node _T_7 = and(_T_6, nodeOut.r.bits.last) connect Queue8_BundleMap.io.deq.ready, _T_7 invalidate Queue8_BundleMap.io.deq.valid invalidate Queue8_BundleMap.io.deq.bits.extra_id invalidate Queue8_BundleMap.io.deq.bits.tl_state.source invalidate Queue8_BundleMap.io.deq.bits.tl_state.size node _T_8 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_9 = and(_T_8, arsel_0) connect Queue8_BundleMap.io.enq.valid, _T_9 invalidate Queue8_BundleMap.io.enq.ready connect Queue8_BundleMap.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap.io.count node _T_10 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_11 = and(_T_10, rsel_1) node _T_12 = and(_T_11, nodeOut.r.bits.last) connect Queue8_BundleMap_1.io.deq.ready, _T_12 invalidate Queue8_BundleMap_1.io.deq.valid invalidate Queue8_BundleMap_1.io.deq.bits.extra_id invalidate Queue8_BundleMap_1.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_1.io.deq.bits.tl_state.size node _T_13 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_14 = and(_T_13, arsel_1) connect Queue8_BundleMap_1.io.enq.valid, _T_14 invalidate Queue8_BundleMap_1.io.enq.ready connect Queue8_BundleMap_1.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap_1.io.count node _T_15 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_16 = and(_T_15, rsel_2) node _T_17 = and(_T_16, nodeOut.r.bits.last) connect Queue8_BundleMap_2.io.deq.ready, _T_17 invalidate Queue8_BundleMap_2.io.deq.valid invalidate Queue8_BundleMap_2.io.deq.bits.extra_id invalidate Queue8_BundleMap_2.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_2.io.deq.bits.tl_state.size node _T_18 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_19 = and(_T_18, arsel_2) connect Queue8_BundleMap_2.io.enq.valid, _T_19 invalidate Queue8_BundleMap_2.io.enq.ready connect Queue8_BundleMap_2.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap_2.io.count node _T_20 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_21 = and(_T_20, rsel_3) node _T_22 = and(_T_21, nodeOut.r.bits.last) connect Queue8_BundleMap_3.io.deq.ready, _T_22 invalidate Queue8_BundleMap_3.io.deq.valid invalidate Queue8_BundleMap_3.io.deq.bits.extra_id invalidate Queue8_BundleMap_3.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_3.io.deq.bits.tl_state.size node _T_23 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_24 = and(_T_23, arsel_3) connect Queue8_BundleMap_3.io.enq.valid, _T_24 invalidate Queue8_BundleMap_3.io.enq.ready connect Queue8_BundleMap_3.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap_3.io.count node _T_25 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_26 = and(_T_25, rsel_4) node _T_27 = and(_T_26, nodeOut.r.bits.last) connect Queue7_BundleMap.io.deq.ready, _T_27 invalidate Queue7_BundleMap.io.deq.valid invalidate Queue7_BundleMap.io.deq.bits.extra_id invalidate Queue7_BundleMap.io.deq.bits.tl_state.source invalidate Queue7_BundleMap.io.deq.bits.tl_state.size node _T_28 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_29 = and(_T_28, arsel_4) connect Queue7_BundleMap.io.enq.valid, _T_29 invalidate Queue7_BundleMap.io.enq.ready connect Queue7_BundleMap.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap.io.count node _T_30 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_31 = and(_T_30, rsel_5) node _T_32 = and(_T_31, nodeOut.r.bits.last) connect Queue7_BundleMap_1.io.deq.ready, _T_32 invalidate Queue7_BundleMap_1.io.deq.valid invalidate Queue7_BundleMap_1.io.deq.bits.extra_id invalidate Queue7_BundleMap_1.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_1.io.deq.bits.tl_state.size node _T_33 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_34 = and(_T_33, arsel_5) connect Queue7_BundleMap_1.io.enq.valid, _T_34 invalidate Queue7_BundleMap_1.io.enq.ready connect Queue7_BundleMap_1.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_1.io.count node _T_35 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_36 = and(_T_35, rsel_6) node _T_37 = and(_T_36, nodeOut.r.bits.last) connect Queue7_BundleMap_2.io.deq.ready, _T_37 invalidate Queue7_BundleMap_2.io.deq.valid invalidate Queue7_BundleMap_2.io.deq.bits.extra_id invalidate Queue7_BundleMap_2.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_2.io.deq.bits.tl_state.size node _T_38 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_39 = and(_T_38, arsel_6) connect Queue7_BundleMap_2.io.enq.valid, _T_39 invalidate Queue7_BundleMap_2.io.enq.ready connect Queue7_BundleMap_2.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_2.io.count node _T_40 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_41 = and(_T_40, rsel_7) node _T_42 = and(_T_41, nodeOut.r.bits.last) connect Queue7_BundleMap_3.io.deq.ready, _T_42 invalidate Queue7_BundleMap_3.io.deq.valid invalidate Queue7_BundleMap_3.io.deq.bits.extra_id invalidate Queue7_BundleMap_3.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_3.io.deq.bits.tl_state.size node _T_43 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_44 = and(_T_43, arsel_7) connect Queue7_BundleMap_3.io.enq.valid, _T_44 invalidate Queue7_BundleMap_3.io.enq.ready connect Queue7_BundleMap_3.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_3.io.count node _T_45 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_46 = and(_T_45, rsel_8) node _T_47 = and(_T_46, nodeOut.r.bits.last) connect Queue7_BundleMap_4.io.deq.ready, _T_47 invalidate Queue7_BundleMap_4.io.deq.valid invalidate Queue7_BundleMap_4.io.deq.bits.extra_id invalidate Queue7_BundleMap_4.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_4.io.deq.bits.tl_state.size node _T_48 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_49 = and(_T_48, arsel_8) connect Queue7_BundleMap_4.io.enq.valid, _T_49 invalidate Queue7_BundleMap_4.io.enq.ready connect Queue7_BundleMap_4.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_4.io.count node _T_50 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_51 = and(_T_50, rsel_9) node _T_52 = and(_T_51, nodeOut.r.bits.last) connect Queue7_BundleMap_5.io.deq.ready, _T_52 invalidate Queue7_BundleMap_5.io.deq.valid invalidate Queue7_BundleMap_5.io.deq.bits.extra_id invalidate Queue7_BundleMap_5.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_5.io.deq.bits.tl_state.size node _T_53 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_54 = and(_T_53, arsel_9) connect Queue7_BundleMap_5.io.enq.valid, _T_54 invalidate Queue7_BundleMap_5.io.enq.ready connect Queue7_BundleMap_5.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_5.io.count node _T_55 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_56 = and(_T_55, rsel_10) node _T_57 = and(_T_56, nodeOut.r.bits.last) connect Queue7_BundleMap_6.io.deq.ready, _T_57 invalidate Queue7_BundleMap_6.io.deq.valid invalidate Queue7_BundleMap_6.io.deq.bits.extra_id invalidate Queue7_BundleMap_6.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_6.io.deq.bits.tl_state.size node _T_58 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_59 = and(_T_58, arsel_10) connect Queue7_BundleMap_6.io.enq.valid, _T_59 invalidate Queue7_BundleMap_6.io.enq.ready connect Queue7_BundleMap_6.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_6.io.count node _T_60 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_61 = and(_T_60, rsel_11) node _T_62 = and(_T_61, nodeOut.r.bits.last) connect Queue7_BundleMap_7.io.deq.ready, _T_62 invalidate Queue7_BundleMap_7.io.deq.valid invalidate Queue7_BundleMap_7.io.deq.bits.extra_id invalidate Queue7_BundleMap_7.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_7.io.deq.bits.tl_state.size node _T_63 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_64 = and(_T_63, arsel_11) connect Queue7_BundleMap_7.io.enq.valid, _T_64 invalidate Queue7_BundleMap_7.io.enq.ready connect Queue7_BundleMap_7.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_7.io.count node _T_65 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_66 = and(_T_65, rsel_12) node _T_67 = and(_T_66, nodeOut.r.bits.last) connect Queue7_BundleMap_8.io.deq.ready, _T_67 invalidate Queue7_BundleMap_8.io.deq.valid invalidate Queue7_BundleMap_8.io.deq.bits.extra_id invalidate Queue7_BundleMap_8.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_8.io.deq.bits.tl_state.size node _T_68 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_69 = and(_T_68, arsel_12) connect Queue7_BundleMap_8.io.enq.valid, _T_69 invalidate Queue7_BundleMap_8.io.enq.ready connect Queue7_BundleMap_8.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_8.io.count node _T_70 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_71 = and(_T_70, rsel_13) node _T_72 = and(_T_71, nodeOut.r.bits.last) connect Queue7_BundleMap_9.io.deq.ready, _T_72 invalidate Queue7_BundleMap_9.io.deq.valid invalidate Queue7_BundleMap_9.io.deq.bits.extra_id invalidate Queue7_BundleMap_9.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_9.io.deq.bits.tl_state.size node _T_73 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_74 = and(_T_73, arsel_13) connect Queue7_BundleMap_9.io.enq.valid, _T_74 invalidate Queue7_BundleMap_9.io.enq.ready connect Queue7_BundleMap_9.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_9.io.count node _T_75 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_76 = and(_T_75, rsel_14) node _T_77 = and(_T_76, nodeOut.r.bits.last) connect Queue7_BundleMap_10.io.deq.ready, _T_77 invalidate Queue7_BundleMap_10.io.deq.valid invalidate Queue7_BundleMap_10.io.deq.bits.extra_id invalidate Queue7_BundleMap_10.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_10.io.deq.bits.tl_state.size node _T_78 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_79 = and(_T_78, arsel_14) connect Queue7_BundleMap_10.io.enq.valid, _T_79 invalidate Queue7_BundleMap_10.io.enq.ready connect Queue7_BundleMap_10.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_10.io.count node _T_80 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_81 = and(_T_80, rsel_15) node _T_82 = and(_T_81, nodeOut.r.bits.last) connect Queue7_BundleMap_11.io.deq.ready, _T_82 invalidate Queue7_BundleMap_11.io.deq.valid invalidate Queue7_BundleMap_11.io.deq.bits.extra_id invalidate Queue7_BundleMap_11.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_11.io.deq.bits.tl_state.size node _T_83 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_84 = and(_T_83, arsel_15) connect Queue7_BundleMap_11.io.enq.valid, _T_84 invalidate Queue7_BundleMap_11.io.enq.ready connect Queue7_BundleMap_11.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_11.io.count wire _aw_ready_WIRE : UInt<1>[16] connect _aw_ready_WIRE[0], Queue8_BundleMap_4.io.enq.ready connect _aw_ready_WIRE[1], Queue8_BundleMap_5.io.enq.ready connect _aw_ready_WIRE[2], Queue8_BundleMap_6.io.enq.ready connect _aw_ready_WIRE[3], Queue8_BundleMap_7.io.enq.ready connect _aw_ready_WIRE[4], Queue7_BundleMap_12.io.enq.ready connect _aw_ready_WIRE[5], Queue7_BundleMap_13.io.enq.ready connect _aw_ready_WIRE[6], Queue7_BundleMap_14.io.enq.ready connect _aw_ready_WIRE[7], Queue7_BundleMap_15.io.enq.ready connect _aw_ready_WIRE[8], Queue7_BundleMap_16.io.enq.ready connect _aw_ready_WIRE[9], Queue7_BundleMap_17.io.enq.ready connect _aw_ready_WIRE[10], Queue7_BundleMap_18.io.enq.ready connect _aw_ready_WIRE[11], Queue7_BundleMap_19.io.enq.ready connect _aw_ready_WIRE[12], Queue7_BundleMap_20.io.enq.ready connect _aw_ready_WIRE[13], Queue7_BundleMap_21.io.enq.ready connect _aw_ready_WIRE[14], Queue7_BundleMap_22.io.enq.ready connect _aw_ready_WIRE[15], Queue7_BundleMap_23.io.enq.ready node _nodeIn_aw_ready_T = and(nodeOut.aw.ready, _aw_ready_WIRE[nodeIn.aw.bits.id]) connect nodeIn.aw.ready, _nodeIn_aw_ready_T node _nodeOut_aw_valid_T = and(nodeIn.aw.valid, _aw_ready_WIRE[nodeIn.aw.bits.id]) connect nodeOut.aw.valid, _nodeOut_aw_valid_T connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id wire _b_valid_WIRE : UInt<1>[16] connect _b_valid_WIRE[0], Queue8_BundleMap_4.io.deq.valid connect _b_valid_WIRE[1], Queue8_BundleMap_5.io.deq.valid connect _b_valid_WIRE[2], Queue8_BundleMap_6.io.deq.valid connect _b_valid_WIRE[3], Queue8_BundleMap_7.io.deq.valid connect _b_valid_WIRE[4], Queue7_BundleMap_12.io.deq.valid connect _b_valid_WIRE[5], Queue7_BundleMap_13.io.deq.valid connect _b_valid_WIRE[6], Queue7_BundleMap_14.io.deq.valid connect _b_valid_WIRE[7], Queue7_BundleMap_15.io.deq.valid connect _b_valid_WIRE[8], Queue7_BundleMap_16.io.deq.valid connect _b_valid_WIRE[9], Queue7_BundleMap_17.io.deq.valid connect _b_valid_WIRE[10], Queue7_BundleMap_18.io.deq.valid connect _b_valid_WIRE[11], Queue7_BundleMap_19.io.deq.valid connect _b_valid_WIRE[12], Queue7_BundleMap_20.io.deq.valid connect _b_valid_WIRE[13], Queue7_BundleMap_21.io.deq.valid connect _b_valid_WIRE[14], Queue7_BundleMap_22.io.deq.valid connect _b_valid_WIRE[15], Queue7_BundleMap_23.io.deq.valid wire _b_bits_WIRE : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}[16] connect _b_bits_WIRE[0], Queue8_BundleMap_4.io.deq.bits connect _b_bits_WIRE[1], Queue8_BundleMap_5.io.deq.bits connect _b_bits_WIRE[2], Queue8_BundleMap_6.io.deq.bits connect _b_bits_WIRE[3], Queue8_BundleMap_7.io.deq.bits connect _b_bits_WIRE[4], Queue7_BundleMap_12.io.deq.bits connect _b_bits_WIRE[5], Queue7_BundleMap_13.io.deq.bits connect _b_bits_WIRE[6], Queue7_BundleMap_14.io.deq.bits connect _b_bits_WIRE[7], Queue7_BundleMap_15.io.deq.bits connect _b_bits_WIRE[8], Queue7_BundleMap_16.io.deq.bits connect _b_bits_WIRE[9], Queue7_BundleMap_17.io.deq.bits connect _b_bits_WIRE[10], Queue7_BundleMap_18.io.deq.bits connect _b_bits_WIRE[11], Queue7_BundleMap_19.io.deq.bits connect _b_bits_WIRE[12], Queue7_BundleMap_20.io.deq.bits connect _b_bits_WIRE[13], Queue7_BundleMap_21.io.deq.bits connect _b_bits_WIRE[14], Queue7_BundleMap_22.io.deq.bits connect _b_bits_WIRE[15], Queue7_BundleMap_23.io.deq.bits node _T_85 = eq(nodeOut.b.valid, UInt<1>(0h0)) node _T_86 = or(_T_85, _b_valid_WIRE[nodeOut.b.bits.id]) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at UserYanker.scala:98 assert (!out.b.valid \|\| b_valid) // Q must be ready faster than the response\n") : printf_1 assert(clock, _T_86, UInt<1>(0h1), "") : assert_1 connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.b.bits.echo, _b_bits_WIRE[nodeOut.b.bits.id] node awsel_shiftAmount = bits(nodeIn.aw.bits.id, 3, 0) node _awsel_T = dshl(UInt<1>(0h1), awsel_shiftAmount) node _awsel_T_1 = bits(_awsel_T, 15, 0) node awsel_0 = bits(_awsel_T_1, 0, 0) node awsel_1 = bits(_awsel_T_1, 1, 1) node awsel_2 = bits(_awsel_T_1, 2, 2) node awsel_3 = bits(_awsel_T_1, 3, 3) node awsel_4 = bits(_awsel_T_1, 4, 4) node awsel_5 = bits(_awsel_T_1, 5, 5) node awsel_6 = bits(_awsel_T_1, 6, 6) node awsel_7 = bits(_awsel_T_1, 7, 7) node awsel_8 = bits(_awsel_T_1, 8, 8) node awsel_9 = bits(_awsel_T_1, 9, 9) node awsel_10 = bits(_awsel_T_1, 10, 10) node awsel_11 = bits(_awsel_T_1, 11, 11) node awsel_12 = bits(_awsel_T_1, 12, 12) node awsel_13 = bits(_awsel_T_1, 13, 13) node awsel_14 = bits(_awsel_T_1, 14, 14) node awsel_15 = bits(_awsel_T_1, 15, 15) node bsel_shiftAmount = bits(nodeOut.b.bits.id, 3, 0) node _bsel_T = dshl(UInt<1>(0h1), bsel_shiftAmount) node _bsel_T_1 = bits(_bsel_T, 15, 0) node bsel_0 = bits(_bsel_T_1, 0, 0) node bsel_1 = bits(_bsel_T_1, 1, 1) node bsel_2 = bits(_bsel_T_1, 2, 2) node bsel_3 = bits(_bsel_T_1, 3, 3) node bsel_4 = bits(_bsel_T_1, 4, 4) node bsel_5 = bits(_bsel_T_1, 5, 5) node bsel_6 = bits(_bsel_T_1, 6, 6) node bsel_7 = bits(_bsel_T_1, 7, 7) node bsel_8 = bits(_bsel_T_1, 8, 8) node bsel_9 = bits(_bsel_T_1, 9, 9) node bsel_10 = bits(_bsel_T_1, 10, 10) node bsel_11 = bits(_bsel_T_1, 11, 11) node bsel_12 = bits(_bsel_T_1, 12, 12) node bsel_13 = bits(_bsel_T_1, 13, 13) node bsel_14 = bits(_bsel_T_1, 14, 14) node bsel_15 = bits(_bsel_T_1, 15, 15) node _T_90 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_91 = and(_T_90, bsel_0) connect Queue8_BundleMap_4.io.deq.ready, _T_91 invalidate Queue8_BundleMap_4.io.deq.valid invalidate Queue8_BundleMap_4.io.deq.bits.extra_id invalidate Queue8_BundleMap_4.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_4.io.deq.bits.tl_state.size node _T_92 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_93 = and(_T_92, awsel_0) connect Queue8_BundleMap_4.io.enq.valid, _T_93 invalidate Queue8_BundleMap_4.io.enq.ready connect Queue8_BundleMap_4.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_4.io.count node _T_94 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_95 = and(_T_94, bsel_1) connect Queue8_BundleMap_5.io.deq.ready, _T_95 invalidate Queue8_BundleMap_5.io.deq.valid invalidate Queue8_BundleMap_5.io.deq.bits.extra_id invalidate Queue8_BundleMap_5.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_5.io.deq.bits.tl_state.size node _T_96 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_97 = and(_T_96, awsel_1) connect Queue8_BundleMap_5.io.enq.valid, _T_97 invalidate Queue8_BundleMap_5.io.enq.ready connect Queue8_BundleMap_5.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_5.io.count node _T_98 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_99 = and(_T_98, bsel_2) connect Queue8_BundleMap_6.io.deq.ready, _T_99 invalidate Queue8_BundleMap_6.io.deq.valid invalidate Queue8_BundleMap_6.io.deq.bits.extra_id invalidate Queue8_BundleMap_6.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_6.io.deq.bits.tl_state.size node _T_100 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_101 = and(_T_100, awsel_2) connect Queue8_BundleMap_6.io.enq.valid, _T_101 invalidate Queue8_BundleMap_6.io.enq.ready connect Queue8_BundleMap_6.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_6.io.count node _T_102 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_103 = and(_T_102, bsel_3) connect Queue8_BundleMap_7.io.deq.ready, _T_103 invalidate Queue8_BundleMap_7.io.deq.valid invalidate Queue8_BundleMap_7.io.deq.bits.extra_id invalidate Queue8_BundleMap_7.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_7.io.deq.bits.tl_state.size node _T_104 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_105 = and(_T_104, awsel_3) connect Queue8_BundleMap_7.io.enq.valid, _T_105 invalidate Queue8_BundleMap_7.io.enq.ready connect Queue8_BundleMap_7.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_7.io.count node _T_106 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_107 = and(_T_106, bsel_4) connect Queue7_BundleMap_12.io.deq.ready, _T_107 invalidate Queue7_BundleMap_12.io.deq.valid invalidate Queue7_BundleMap_12.io.deq.bits.extra_id invalidate Queue7_BundleMap_12.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_12.io.deq.bits.tl_state.size node _T_108 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_109 = and(_T_108, awsel_4) connect Queue7_BundleMap_12.io.enq.valid, _T_109 invalidate Queue7_BundleMap_12.io.enq.ready connect Queue7_BundleMap_12.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_12.io.count node _T_110 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_111 = and(_T_110, bsel_5) connect Queue7_BundleMap_13.io.deq.ready, _T_111 invalidate Queue7_BundleMap_13.io.deq.valid invalidate Queue7_BundleMap_13.io.deq.bits.extra_id invalidate Queue7_BundleMap_13.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_13.io.deq.bits.tl_state.size node _T_112 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_113 = and(_T_112, awsel_5) connect Queue7_BundleMap_13.io.enq.valid, _T_113 invalidate Queue7_BundleMap_13.io.enq.ready connect Queue7_BundleMap_13.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_13.io.count node _T_114 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_115 = and(_T_114, bsel_6) connect Queue7_BundleMap_14.io.deq.ready, _T_115 invalidate Queue7_BundleMap_14.io.deq.valid invalidate Queue7_BundleMap_14.io.deq.bits.extra_id invalidate Queue7_BundleMap_14.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_14.io.deq.bits.tl_state.size node _T_116 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_117 = and(_T_116, awsel_6) connect Queue7_BundleMap_14.io.enq.valid, _T_117 invalidate Queue7_BundleMap_14.io.enq.ready connect Queue7_BundleMap_14.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_14.io.count node _T_118 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_119 = and(_T_118, bsel_7) connect Queue7_BundleMap_15.io.deq.ready, _T_119 invalidate Queue7_BundleMap_15.io.deq.valid invalidate Queue7_BundleMap_15.io.deq.bits.extra_id invalidate Queue7_BundleMap_15.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_15.io.deq.bits.tl_state.size node _T_120 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_121 = and(_T_120, awsel_7) connect Queue7_BundleMap_15.io.enq.valid, _T_121 invalidate Queue7_BundleMap_15.io.enq.ready connect Queue7_BundleMap_15.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_15.io.count node _T_122 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_123 = and(_T_122, bsel_8) connect Queue7_BundleMap_16.io.deq.ready, _T_123 invalidate Queue7_BundleMap_16.io.deq.valid invalidate Queue7_BundleMap_16.io.deq.bits.extra_id invalidate Queue7_BundleMap_16.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_16.io.deq.bits.tl_state.size node _T_124 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_125 = and(_T_124, awsel_8) connect Queue7_BundleMap_16.io.enq.valid, _T_125 invalidate Queue7_BundleMap_16.io.enq.ready connect Queue7_BundleMap_16.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_16.io.count node _T_126 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_127 = and(_T_126, bsel_9) connect Queue7_BundleMap_17.io.deq.ready, _T_127 invalidate Queue7_BundleMap_17.io.deq.valid invalidate Queue7_BundleMap_17.io.deq.bits.extra_id invalidate Queue7_BundleMap_17.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_17.io.deq.bits.tl_state.size node _T_128 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_129 = and(_T_128, awsel_9) connect Queue7_BundleMap_17.io.enq.valid, _T_129 invalidate Queue7_BundleMap_17.io.enq.ready connect Queue7_BundleMap_17.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_17.io.count node _T_130 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_131 = and(_T_130, bsel_10) connect Queue7_BundleMap_18.io.deq.ready, _T_131 invalidate Queue7_BundleMap_18.io.deq.valid invalidate Queue7_BundleMap_18.io.deq.bits.extra_id invalidate Queue7_BundleMap_18.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_18.io.deq.bits.tl_state.size node _T_132 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_133 = and(_T_132, awsel_10) connect Queue7_BundleMap_18.io.enq.valid, _T_133 invalidate Queue7_BundleMap_18.io.enq.ready connect Queue7_BundleMap_18.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_18.io.count node _T_134 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_135 = and(_T_134, bsel_11) connect Queue7_BundleMap_19.io.deq.ready, _T_135 invalidate Queue7_BundleMap_19.io.deq.valid invalidate Queue7_BundleMap_19.io.deq.bits.extra_id invalidate Queue7_BundleMap_19.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_19.io.deq.bits.tl_state.size node _T_136 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_137 = and(_T_136, awsel_11) connect Queue7_BundleMap_19.io.enq.valid, _T_137 invalidate Queue7_BundleMap_19.io.enq.ready connect Queue7_BundleMap_19.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_19.io.count node _T_138 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_139 = and(_T_138, bsel_12) connect Queue7_BundleMap_20.io.deq.ready, _T_139 invalidate Queue7_BundleMap_20.io.deq.valid invalidate Queue7_BundleMap_20.io.deq.bits.extra_id invalidate Queue7_BundleMap_20.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_20.io.deq.bits.tl_state.size node _T_140 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_141 = and(_T_140, awsel_12) connect Queue7_BundleMap_20.io.enq.valid, _T_141 invalidate Queue7_BundleMap_20.io.enq.ready connect Queue7_BundleMap_20.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_20.io.count node _T_142 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_143 = and(_T_142, bsel_13) connect Queue7_BundleMap_21.io.deq.ready, _T_143 invalidate Queue7_BundleMap_21.io.deq.valid invalidate Queue7_BundleMap_21.io.deq.bits.extra_id invalidate Queue7_BundleMap_21.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_21.io.deq.bits.tl_state.size node _T_144 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_145 = and(_T_144, awsel_13) connect Queue7_BundleMap_21.io.enq.valid, _T_145 invalidate Queue7_BundleMap_21.io.enq.ready connect Queue7_BundleMap_21.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_21.io.count node _T_146 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_147 = and(_T_146, bsel_14) connect Queue7_BundleMap_22.io.deq.ready, _T_147 invalidate Queue7_BundleMap_22.io.deq.valid invalidate Queue7_BundleMap_22.io.deq.bits.extra_id invalidate Queue7_BundleMap_22.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_22.io.deq.bits.tl_state.size node _T_148 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_149 = and(_T_148, awsel_14) connect Queue7_BundleMap_22.io.enq.valid, _T_149 invalidate Queue7_BundleMap_22.io.enq.ready connect Queue7_BundleMap_22.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_22.io.count node _T_150 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_151 = and(_T_150, bsel_15) connect Queue7_BundleMap_23.io.deq.ready, _T_151 invalidate Queue7_BundleMap_23.io.deq.valid invalidate Queue7_BundleMap_23.io.deq.bits.extra_id invalidate Queue7_BundleMap_23.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_23.io.deq.bits.tl_state.size node _T_152 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_153 = and(_T_152, awsel_15) connect Queue7_BundleMap_23.io.enq.valid, _T_153 invalidate Queue7_BundleMap_23.io.enq.ready connect Queue7_BundleMap_23.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_23.io.count connect nodeOut.w, nodeIn.w	module AXI4UserYanker( // @[UserYanker.scala:36:9] input clock, // @[UserYanker.scala:36:9] input reset, // @[UserYanker.scala:36:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire _Queue7_BundleMap_23_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_23_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_23_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_23_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_23_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_22_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_22_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_22_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_22_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_22_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_21_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_21_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_21_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_21_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_21_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_20_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_20_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_20_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_20_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_20_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_19_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_19_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_19_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_19_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_19_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_18_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_18_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_18_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_18_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_18_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_17_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_17_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_17_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_17_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_17_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_16_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_16_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_16_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_16_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_16_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_15_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_15_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_15_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_15_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_15_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_14_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_14_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_14_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_14_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_14_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_13_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_13_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_13_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_13_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_13_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_12_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_12_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_12_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_12_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_12_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_7_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_7_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_7_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_7_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_7_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_6_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_6_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_6_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_6_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_6_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_5_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_5_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_5_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_5_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_5_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_4_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_4_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_4_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_4_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_4_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_11_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_11_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_11_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_11_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_11_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_10_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_10_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_10_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_10_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_10_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_9_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_9_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_9_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_9_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_9_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_8_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_8_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_8_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_8_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_8_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_7_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_7_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_7_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_7_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_7_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_6_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_6_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_6_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_6_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_6_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_5_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_5_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_5_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_5_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_5_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_4_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_4_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_4_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_4_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_4_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_3_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_3_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_3_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_3_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_3_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_2_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_2_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_2_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_2_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_2_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_1_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_1_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_1_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_1_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_1_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_3_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_3_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_3_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_3_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_3_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_2_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_2_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_2_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_2_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_2_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_1_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_1_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_1_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_1_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_1_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire [15:0] _GEN = {{_Queue7_BundleMap_11_io_enq_ready}, {_Queue7_BundleMap_10_io_enq_ready}, {_Queue7_BundleMap_9_io_enq_ready}, {_Queue7_BundleMap_8_io_enq_ready}, {_Queue7_BundleMap_7_io_enq_ready}, {_Queue7_BundleMap_6_io_enq_ready}, {_Queue7_BundleMap_5_io_enq_ready}, {_Queue7_BundleMap_4_io_enq_ready}, {_Queue7_BundleMap_3_io_enq_ready}, {_Queue7_BundleMap_2_io_enq_ready}, {_Queue7_BundleMap_1_io_enq_ready}, {_Queue7_BundleMap_io_enq_ready}, {_Queue8_BundleMap_3_io_enq_ready}, {_Queue8_BundleMap_2_io_enq_ready}, {_Queue8_BundleMap_1_io_enq_ready}, {_Queue8_BundleMap_io_enq_ready}}; // @[UserYanker.scala:51:17, :60:36] wire [15:0][3:0] _GEN_0 = {{_Queue7_BundleMap_11_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_10_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_9_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_8_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_7_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_6_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_5_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_4_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_3_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_2_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_1_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_3_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_2_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_1_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_io_deq_bits_tl_state_size}}; // @[UserYanker.scala:51:17, :73:22] wire [15:0][6:0] _GEN_1 = {{_Queue7_BundleMap_11_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_10_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_9_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_8_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_7_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_6_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_5_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_4_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_3_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_2_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_1_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_3_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_2_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_1_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_io_deq_bits_tl_state_source}}; // @[UserYanker.scala:51:17, :73:22] wire [15:0][2:0] _GEN_2 = {{_Queue7_BundleMap_11_io_deq_bits_extra_id}, {_Queue7_BundleMap_10_io_deq_bits_extra_id}, {_Queue7_BundleMap_9_io_deq_bits_extra_id}, {_Queue7_BundleMap_8_io_deq_bits_extra_id}, {_Queue7_BundleMap_7_io_deq_bits_extra_id}, {_Queue7_BundleMap_6_io_deq_bits_extra_id}, {_Queue7_BundleMap_5_io_deq_bits_extra_id}, {_Queue7_BundleMap_4_io_deq_bits_extra_id}, {_Queue7_BundleMap_3_io_deq_bits_extra_id}, {_Queue7_BundleMap_2_io_deq_bits_extra_id}, {_Queue7_BundleMap_1_io_deq_bits_extra_id}, {_Queue7_BundleMap_io_deq_bits_extra_id}, {_Queue8_BundleMap_3_io_deq_bits_extra_id}, {_Queue8_BundleMap_2_io_deq_bits_extra_id}, {_Queue8_BundleMap_1_io_deq_bits_extra_id}, {_Queue8_BundleMap_io_deq_bits_extra_id}}; // @[UserYanker.scala:51:17, :73:22] wire _GEN_3 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala:78:37] wire _GEN_4 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala:81:37] wire [15:0] _GEN_5 = {{_Queue7_BundleMap_23_io_enq_ready}, {_Queue7_BundleMap_22_io_enq_ready}, {_Queue7_BundleMap_21_io_enq_ready}, {_Queue7_BundleMap_20_io_enq_ready}, {_Queue7_BundleMap_19_io_enq_ready}, {_Queue7_BundleMap_18_io_enq_ready}, {_Queue7_BundleMap_17_io_enq_ready}, {_Queue7_BundleMap_16_io_enq_ready}, {_Queue7_BundleMap_15_io_enq_ready}, {_Queue7_BundleMap_14_io_enq_ready}, {_Queue7_BundleMap_13_io_enq_ready}, {_Queue7_BundleMap_12_io_enq_ready}, {_Queue8_BundleMap_7_io_enq_ready}, {_Queue8_BundleMap_6_io_enq_ready}, {_Queue8_BundleMap_5_io_enq_ready}, {_Queue8_BundleMap_4_io_enq_ready}}; // @[UserYanker.scala:51:17, :89:36]
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_14 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `1` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `0` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<20> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_14, decoded_andMatrixOutputs_andMatrixInput_15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_12, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_12_1, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_8_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_decoded_orMatrixOutputs_T_6, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs, 12, 12) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs, 13, 13) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs, 14, 14) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs, 15, 15) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs, 16, 16) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs, 17, 17) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs, 18, 18) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs, 19, 19) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs, 20, 20) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs, 21, 21) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs, 22, 22) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo) node decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_invMatrixOutputs_lo_hi_lo_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, decoded_invMatrixOutputs_lo_hi_lo) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_invMatrixOutputs_hi_lo_lo_hi, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, decoded_invMatrixOutputs_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_20, _decoded_invMatrixOutputs_T_19) node decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_invMatrixOutputs_hi_hi_lo_hi, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi, _decoded_invMatrixOutputs_T_21) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_lo) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 15, 0) node _decoded_T_1 = shl(UInt<8>(0hff), 8) node _decoded_T_2 = xor(UInt<16>(0hffff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 8) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 7, 0) node _decoded_T_6 = shl(_decoded_T_5, 8) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 11, 0) node _decoded_T_11 = shl(_decoded_T_10, 4) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 4) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 11, 0) node _decoded_T_16 = shl(_decoded_T_15, 4) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 13, 0) node _decoded_T_21 = shl(_decoded_T_20, 2) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 2) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 13, 0) node _decoded_T_26 = shl(_decoded_T_25, 2) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(_decoded_T_22, 14, 0) node _decoded_T_31 = shl(_decoded_T_30, 1) node _decoded_T_32 = xor(_decoded_T_22, _decoded_T_31) node _decoded_T_33 = shr(_decoded_T_29, 1) node _decoded_T_34 = and(_decoded_T_33, _decoded_T_32) node _decoded_T_35 = bits(_decoded_T_29, 14, 0) node _decoded_T_36 = shl(_decoded_T_35, 1) node _decoded_T_37 = not(_decoded_T_32) node _decoded_T_38 = and(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = or(_decoded_T_34, _decoded_T_38) node _decoded_T_40 = bits(decoded_plaOutput, 23, 16) node _decoded_T_41 = shl(UInt<4>(0hf), 4) node _decoded_T_42 = xor(UInt<8>(0hff), _decoded_T_41) node _decoded_T_43 = shr(_decoded_T_40, 4) node _decoded_T_44 = and(_decoded_T_43, _decoded_T_42) node _decoded_T_45 = bits(_decoded_T_40, 3, 0) node _decoded_T_46 = shl(_decoded_T_45, 4) node _decoded_T_47 = not(_decoded_T_42) node _decoded_T_48 = and(_decoded_T_46, _decoded_T_47) node _decoded_T_49 = or(_decoded_T_44, _decoded_T_48) node _decoded_T_50 = bits(_decoded_T_42, 5, 0) node _decoded_T_51 = shl(_decoded_T_50, 2) node _decoded_T_52 = xor(_decoded_T_42, _decoded_T_51) node _decoded_T_53 = shr(_decoded_T_49, 2) node _decoded_T_54 = and(_decoded_T_53, _decoded_T_52) node _decoded_T_55 = bits(_decoded_T_49, 5, 0) node _decoded_T_56 = shl(_decoded_T_55, 2) node _decoded_T_57 = not(_decoded_T_52) node _decoded_T_58 = and(_decoded_T_56, _decoded_T_57) node _decoded_T_59 = or(_decoded_T_54, _decoded_T_58) node _decoded_T_60 = bits(_decoded_T_52, 6, 0) node _decoded_T_61 = shl(_decoded_T_60, 1) node _decoded_T_62 = xor(_decoded_T_52, _decoded_T_61) node _decoded_T_63 = shr(_decoded_T_59, 1) node _decoded_T_64 = and(_decoded_T_63, _decoded_T_62) node _decoded_T_65 = bits(_decoded_T_59, 6, 0) node _decoded_T_66 = shl(_decoded_T_65, 1) node _decoded_T_67 = not(_decoded_T_62) node _decoded_T_68 = and(_decoded_T_66, _decoded_T_67) node _decoded_T_69 = or(_decoded_T_64, _decoded_T_68) node decoded = cat(_decoded_T_39, _decoded_T_69) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_1_3_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`1`[3], _io_resp_0_vc_sel_1_3_T node _io_resp_0_vc_sel_1_4_T = bits(decoded, 12, 12) connect io.resp.`0`.vc_sel.`1`[4], _io_resp_0_vc_sel_1_4_T node _io_resp_0_vc_sel_1_5_T = bits(decoded, 13, 13) connect io.resp.`0`.vc_sel.`1`[5], _io_resp_0_vc_sel_1_5_T node _io_resp_0_vc_sel_1_6_T = bits(decoded, 14, 14) connect io.resp.`0`.vc_sel.`1`[6], _io_resp_0_vc_sel_1_6_T node _io_resp_0_vc_sel_1_7_T = bits(decoded, 15, 15) connect io.resp.`0`.vc_sel.`1`[7], _io_resp_0_vc_sel_1_7_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 16, 16) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 17, 17) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 18, 18) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_2_3_T = bits(decoded, 19, 19) connect io.resp.`0`.vc_sel.`2`[3], _io_resp_0_vc_sel_2_3_T node _io_resp_0_vc_sel_2_4_T = bits(decoded, 20, 20) connect io.resp.`0`.vc_sel.`2`[4], _io_resp_0_vc_sel_2_4_T node _io_resp_0_vc_sel_2_5_T = bits(decoded, 21, 21) connect io.resp.`0`.vc_sel.`2`[5], _io_resp_0_vc_sel_2_5_T node _io_resp_0_vc_sel_2_6_T = bits(decoded, 22, 22) connect io.resp.`0`.vc_sel.`2`[6], _io_resp_0_vc_sel_2_6_T node _io_resp_0_vc_sel_2_7_T = bits(decoded, 23, 23) connect io.resp.`0`.vc_sel.`2`[7], _io_resp_0_vc_sel_2_7_T connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<20> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_14_2, decoded_andMatrixOutputs_andMatrixInput_15_1) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_14_3, decoded_andMatrixOutputs_andMatrixInput_15_2) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_12_3, decoded_andMatrixOutputs_andMatrixInput_13_3) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_lo_lo_lo_2) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_10_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_12_4, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_14_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_14_5, decoded_andMatrixOutputs_andMatrixInput_15_3) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_12_5, decoded_andMatrixOutputs_andMatrixInput_13_5) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_3) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_10_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_14_6, decoded_andMatrixOutputs_andMatrixInput_15_4) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_12_6, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_lo_lo_lo_4) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_12_7, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_14_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_hi_lo_lo_7) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_10, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_plaInput_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_11, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_14_8, decoded_andMatrixOutputs_andMatrixInput_15_5) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_12_8, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_5) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_10_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_10, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_8) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_14_9, decoded_andMatrixOutputs_andMatrixInput_15_6) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_12_9, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_lo_lo_lo_6) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_10_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_hi_lo_lo_9) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_12_10, decoded_andMatrixOutputs_andMatrixInput_13_10) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_14_10) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_10_10, decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_andMatrixOutputs_andMatrixInput_9_10) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_hi_lo_lo_10) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_plaInput_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_7_15, decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_5_15, decoded_andMatrixOutputs_andMatrixInput_6_15) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_16, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_17, decoded_andMatrixOutputs_andMatrixInput_3_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_16 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node decoded_orMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_18 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node decoded_orMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_20 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_6) node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_13_2, decoded_andMatrixOutputs_2_2_1) node decoded_orMatrixOutputs_lo_7 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_8_2) node _decoded_orMatrixOutputs_T_22 = cat(decoded_orMatrixOutputs_hi_7, decoded_orMatrixOutputs_lo_7) node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_8 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_1) node _decoded_orMatrixOutputs_T_24 = cat(decoded_orMatrixOutputs_hi_8, decoded_orMatrixOutputs_lo_8) node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_9 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_2) node _decoded_orMatrixOutputs_T_26 = cat(decoded_orMatrixOutputs_hi_9, decoded_orMatrixOutputs_lo_9) node _decoded_orMatrixOutputs_T_27 = orr(_decoded_orMatrixOutputs_T_26) node decoded_orMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_10 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_3) node _decoded_orMatrixOutputs_T_28 = cat(decoded_orMatrixOutputs_hi_10, decoded_orMatrixOutputs_lo_10) node _decoded_orMatrixOutputs_T_29 = orr(_decoded_orMatrixOutputs_T_28) node decoded_orMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_11 = cat(decoded_orMatrixOutputs_lo_hi_5, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_11 = cat(decoded_orMatrixOutputs_hi_hi_5, decoded_orMatrixOutputs_hi_lo_4) node _decoded_orMatrixOutputs_T_30 = cat(decoded_orMatrixOutputs_hi_11, decoded_orMatrixOutputs_lo_11) node _decoded_orMatrixOutputs_T_31 = orr(_decoded_orMatrixOutputs_T_30) node decoded_orMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_12 = cat(decoded_orMatrixOutputs_lo_hi_6, decoded_orMatrixOutputs_lo_lo_5) node decoded_orMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_6, decoded_orMatrixOutputs_hi_lo_5) node _decoded_orMatrixOutputs_T_32 = cat(decoded_orMatrixOutputs_hi_12, decoded_orMatrixOutputs_lo_12) node _decoded_orMatrixOutputs_T_33 = orr(_decoded_orMatrixOutputs_T_32) node decoded_orMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_13 = cat(decoded_orMatrixOutputs_lo_hi_7, decoded_orMatrixOutputs_lo_lo_6) node decoded_orMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_7, decoded_orMatrixOutputs_hi_lo_6) node _decoded_orMatrixOutputs_T_34 = cat(decoded_orMatrixOutputs_hi_13, decoded_orMatrixOutputs_lo_13) node _decoded_orMatrixOutputs_T_35 = orr(_decoded_orMatrixOutputs_T_34) node decoded_orMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_14 = cat(decoded_orMatrixOutputs_lo_hi_8, decoded_orMatrixOutputs_lo_lo_7) node decoded_orMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_8, decoded_orMatrixOutputs_hi_lo_7) node _decoded_orMatrixOutputs_T_36 = cat(decoded_orMatrixOutputs_hi_14, decoded_orMatrixOutputs_lo_14) node _decoded_orMatrixOutputs_T_37 = orr(_decoded_orMatrixOutputs_T_36) node decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_15, _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_1, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_21, _decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_1, _decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_lo_lo_8 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, decoded_orMatrixOutputs_lo_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_1, _decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_9 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_orMatrixOutputs_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_15 = cat(decoded_orMatrixOutputs_lo_hi_9, decoded_orMatrixOutputs_lo_lo_8) node decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_25) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_8 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, decoded_orMatrixOutputs_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_33, _decoded_orMatrixOutputs_T_31) node decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_1, _decoded_orMatrixOutputs_T_29) node decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_37) node decoded_orMatrixOutputs_hi_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_1, _decoded_orMatrixOutputs_T_35) node decoded_orMatrixOutputs_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_8, decoded_orMatrixOutputs_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_9, decoded_orMatrixOutputs_hi_lo_8) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_15, decoded_orMatrixOutputs_lo_15) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_1, 11, 11) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_1, 12, 12) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_1, 13, 13) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_1, 14, 14) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_1, 15, 15) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_1, 16, 16) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_1, 17, 17) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_1, 18, 18) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_1, 19, 19) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_1, 20, 20) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_1, 21, 21) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_1, 22, 22) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_1, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25) node decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_1, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_1, _decoded_invMatrixOutputs_T_27) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_1, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_1, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, decoded_invMatrixOutputs_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_1, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_41, _decoded_invMatrixOutputs_T_40) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_1, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_1, _decoded_invMatrixOutputs_T_42) node decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_1, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_70 = bits(decoded_plaOutput_1, 15, 0) node _decoded_T_71 = shl(UInt<8>(0hff), 8) node _decoded_T_72 = xor(UInt<16>(0hffff), _decoded_T_71) node _decoded_T_73 = shr(_decoded_T_70, 8) node _decoded_T_74 = and(_decoded_T_73, _decoded_T_72) node _decoded_T_75 = bits(_decoded_T_70, 7, 0) node _decoded_T_76 = shl(_decoded_T_75, 8) node _decoded_T_77 = not(_decoded_T_72) node _decoded_T_78 = and(_decoded_T_76, _decoded_T_77) node _decoded_T_79 = or(_decoded_T_74, _decoded_T_78) node _decoded_T_80 = bits(_decoded_T_72, 11, 0) node _decoded_T_81 = shl(_decoded_T_80, 4) node _decoded_T_82 = xor(_decoded_T_72, _decoded_T_81) node _decoded_T_83 = shr(_decoded_T_79, 4) node _decoded_T_84 = and(_decoded_T_83, _decoded_T_82) node _decoded_T_85 = bits(_decoded_T_79, 11, 0) node _decoded_T_86 = shl(_decoded_T_85, 4) node _decoded_T_87 = not(_decoded_T_82) node _decoded_T_88 = and(_decoded_T_86, _decoded_T_87) node _decoded_T_89 = or(_decoded_T_84, _decoded_T_88) node _decoded_T_90 = bits(_decoded_T_82, 13, 0) node _decoded_T_91 = shl(_decoded_T_90, 2) node _decoded_T_92 = xor(_decoded_T_82, _decoded_T_91) node _decoded_T_93 = shr(_decoded_T_89, 2) node _decoded_T_94 = and(_decoded_T_93, _decoded_T_92) node _decoded_T_95 = bits(_decoded_T_89, 13, 0) node _decoded_T_96 = shl(_decoded_T_95, 2) node _decoded_T_97 = not(_decoded_T_92) node _decoded_T_98 = and(_decoded_T_96, _decoded_T_97) node _decoded_T_99 = or(_decoded_T_94, _decoded_T_98) node _decoded_T_100 = bits(_decoded_T_92, 14, 0) node _decoded_T_101 = shl(_decoded_T_100, 1) node _decoded_T_102 = xor(_decoded_T_92, _decoded_T_101) node _decoded_T_103 = shr(_decoded_T_99, 1) node _decoded_T_104 = and(_decoded_T_103, _decoded_T_102) node _decoded_T_105 = bits(_decoded_T_99, 14, 0) node _decoded_T_106 = shl(_decoded_T_105, 1) node _decoded_T_107 = not(_decoded_T_102) node _decoded_T_108 = and(_decoded_T_106, _decoded_T_107) node _decoded_T_109 = or(_decoded_T_104, _decoded_T_108) node _decoded_T_110 = bits(decoded_plaOutput_1, 23, 16) node _decoded_T_111 = shl(UInt<4>(0hf), 4) node _decoded_T_112 = xor(UInt<8>(0hff), _decoded_T_111) node _decoded_T_113 = shr(_decoded_T_110, 4) node _decoded_T_114 = and(_decoded_T_113, _decoded_T_112) node _decoded_T_115 = bits(_decoded_T_110, 3, 0) node _decoded_T_116 = shl(_decoded_T_115, 4) node _decoded_T_117 = not(_decoded_T_112) node _decoded_T_118 = and(_decoded_T_116, _decoded_T_117) node _decoded_T_119 = or(_decoded_T_114, _decoded_T_118) node _decoded_T_120 = bits(_decoded_T_112, 5, 0) node _decoded_T_121 = shl(_decoded_T_120, 2) node _decoded_T_122 = xor(_decoded_T_112, _decoded_T_121) node _decoded_T_123 = shr(_decoded_T_119, 2) node _decoded_T_124 = and(_decoded_T_123, _decoded_T_122) node _decoded_T_125 = bits(_decoded_T_119, 5, 0) node _decoded_T_126 = shl(_decoded_T_125, 2) node _decoded_T_127 = not(_decoded_T_122) node _decoded_T_128 = and(_decoded_T_126, _decoded_T_127) node _decoded_T_129 = or(_decoded_T_124, _decoded_T_128) node _decoded_T_130 = bits(_decoded_T_122, 6, 0) node _decoded_T_131 = shl(_decoded_T_130, 1) node _decoded_T_132 = xor(_decoded_T_122, _decoded_T_131) node _decoded_T_133 = shr(_decoded_T_129, 1) node _decoded_T_134 = and(_decoded_T_133, _decoded_T_132) node _decoded_T_135 = bits(_decoded_T_129, 6, 0) node _decoded_T_136 = shl(_decoded_T_135, 1) node _decoded_T_137 = not(_decoded_T_132) node _decoded_T_138 = and(_decoded_T_136, _decoded_T_137) node _decoded_T_139 = or(_decoded_T_134, _decoded_T_138) node decoded_1 = cat(_decoded_T_109, _decoded_T_139) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_1_3_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`1`[3], _io_resp_1_vc_sel_1_3_T node _io_resp_1_vc_sel_1_4_T = bits(decoded_1, 12, 12) connect io.resp.`1`.vc_sel.`1`[4], _io_resp_1_vc_sel_1_4_T node _io_resp_1_vc_sel_1_5_T = bits(decoded_1, 13, 13) connect io.resp.`1`.vc_sel.`1`[5], _io_resp_1_vc_sel_1_5_T node _io_resp_1_vc_sel_1_6_T = bits(decoded_1, 14, 14) connect io.resp.`1`.vc_sel.`1`[6], _io_resp_1_vc_sel_1_6_T node _io_resp_1_vc_sel_1_7_T = bits(decoded_1, 15, 15) connect io.resp.`1`.vc_sel.`1`[7], _io_resp_1_vc_sel_1_7_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 16, 16) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 17, 17) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 18, 18) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_2_3_T = bits(decoded_1, 19, 19) connect io.resp.`1`.vc_sel.`2`[3], _io_resp_1_vc_sel_2_3_T node _io_resp_1_vc_sel_2_4_T = bits(decoded_1, 20, 20) connect io.resp.`1`.vc_sel.`2`[4], _io_resp_1_vc_sel_2_4_T node _io_resp_1_vc_sel_2_5_T = bits(decoded_1, 21, 21) connect io.resp.`1`.vc_sel.`2`[5], _io_resp_1_vc_sel_2_5_T node _io_resp_1_vc_sel_2_6_T = bits(decoded_1, 22, 22) connect io.resp.`1`.vc_sel.`2`[6], _io_resp_1_vc_sel_2_6_T node _io_resp_1_vc_sel_2_7_T = bits(decoded_1, 23, 23) connect io.resp.`1`.vc_sel.`2`[7], _io_resp_1_vc_sel_2_7_T connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<20> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_plaInput_2, 17, 17) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_plaInput_2, 18, 18) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_21) node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_plaInput_2, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_plaInput_2, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_23) node _decoded_orMatrixOutputs_T_38 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_39 = orr(_decoded_orMatrixOutputs_T_38) node _decoded_orMatrixOutputs_T_40 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_41 = orr(_decoded_orMatrixOutputs_T_40) node _decoded_orMatrixOutputs_T_42 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_43 = orr(_decoded_orMatrixOutputs_T_42) node _decoded_orMatrixOutputs_T_44 = orr(decoded_andMatrixOutputs_2_2_2) node decoded_orMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_45 = cat(decoded_orMatrixOutputs_hi_16, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_46 = orr(_decoded_orMatrixOutputs_T_45) node decoded_orMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_47 = cat(decoded_orMatrixOutputs_hi_17, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_48 = orr(_decoded_orMatrixOutputs_T_47) node decoded_orMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_49 = cat(decoded_orMatrixOutputs_hi_18, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_50 = orr(_decoded_orMatrixOutputs_T_49) node decoded_orMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_51 = cat(decoded_orMatrixOutputs_hi_19, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_52 = orr(_decoded_orMatrixOutputs_T_51) node decoded_orMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_53 = cat(decoded_orMatrixOutputs_hi_20, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_54 = orr(_decoded_orMatrixOutputs_T_53) node decoded_orMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_55 = cat(decoded_orMatrixOutputs_hi_21, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_56 = orr(_decoded_orMatrixOutputs_T_55) node decoded_orMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_57 = cat(decoded_orMatrixOutputs_hi_22, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_58 = orr(_decoded_orMatrixOutputs_T_57) node decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_9 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, decoded_orMatrixOutputs_lo_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_39, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_44, _decoded_orMatrixOutputs_T_43) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_2, _decoded_orMatrixOutputs_T_41) node decoded_orMatrixOutputs_lo_hi_10 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, decoded_orMatrixOutputs_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_16 = cat(decoded_orMatrixOutputs_lo_hi_10, decoded_orMatrixOutputs_lo_lo_9) node decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_48, _decoded_orMatrixOutputs_T_46) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_9 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, decoded_orMatrixOutputs_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_54, _decoded_orMatrixOutputs_T_52) node decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_2, _decoded_orMatrixOutputs_T_50) node decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_58) node decoded_orMatrixOutputs_hi_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_2, _decoded_orMatrixOutputs_T_56) node decoded_orMatrixOutputs_hi_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_hi_9, decoded_orMatrixOutputs_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_23 = cat(decoded_orMatrixOutputs_hi_hi_10, decoded_orMatrixOutputs_hi_lo_9) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_23, decoded_orMatrixOutputs_lo_16) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_2, 11, 11) node _decoded_invMatrixOutputs_T_60 = bits(decoded_orMatrixOutputs_2, 12, 12) node _decoded_invMatrixOutputs_T_61 = bits(decoded_orMatrixOutputs_2, 13, 13) node _decoded_invMatrixOutputs_T_62 = bits(decoded_orMatrixOutputs_2, 14, 14) node _decoded_invMatrixOutputs_T_63 = bits(decoded_orMatrixOutputs_2, 15, 15) node _decoded_invMatrixOutputs_T_64 = bits(decoded_orMatrixOutputs_2, 16, 16) node _decoded_invMatrixOutputs_T_65 = bits(decoded_orMatrixOutputs_2, 17, 17) node _decoded_invMatrixOutputs_T_66 = bits(decoded_orMatrixOutputs_2, 18, 18) node _decoded_invMatrixOutputs_T_67 = bits(decoded_orMatrixOutputs_2, 19, 19) node _decoded_invMatrixOutputs_T_68 = bits(decoded_orMatrixOutputs_2, 20, 20) node _decoded_invMatrixOutputs_T_69 = bits(decoded_orMatrixOutputs_2, 21, 21) node _decoded_invMatrixOutputs_T_70 = bits(decoded_orMatrixOutputs_2, 22, 22) node _decoded_invMatrixOutputs_T_71 = bits(decoded_orMatrixOutputs_2, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_50, _decoded_invMatrixOutputs_T_49) node decoded_invMatrixOutputs_lo_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_2, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_2, _decoded_invMatrixOutputs_T_51) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_56, _decoded_invMatrixOutputs_T_55) node decoded_invMatrixOutputs_lo_hi_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_2, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_2, _decoded_invMatrixOutputs_T_57) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, decoded_invMatrixOutputs_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_62, _decoded_invMatrixOutputs_T_61) node decoded_invMatrixOutputs_hi_lo_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_2, _decoded_invMatrixOutputs_T_60) node decoded_invMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_65, _decoded_invMatrixOutputs_T_64) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_2, _decoded_invMatrixOutputs_T_63) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_68, _decoded_invMatrixOutputs_T_67) node decoded_invMatrixOutputs_hi_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_2, _decoded_invMatrixOutputs_T_66) node decoded_invMatrixOutputs_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_71, _decoded_invMatrixOutputs_T_70) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_2, _decoded_invMatrixOutputs_T_69) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_140 = bits(decoded_plaOutput_2, 15, 0) node _decoded_T_141 = shl(UInt<8>(0hff), 8) node _decoded_T_142 = xor(UInt<16>(0hffff), _decoded_T_141) node _decoded_T_143 = shr(_decoded_T_140, 8) node _decoded_T_144 = and(_decoded_T_143, _decoded_T_142) node _decoded_T_145 = bits(_decoded_T_140, 7, 0) node _decoded_T_146 = shl(_decoded_T_145, 8) node _decoded_T_147 = not(_decoded_T_142) node _decoded_T_148 = and(_decoded_T_146, _decoded_T_147) node _decoded_T_149 = or(_decoded_T_144, _decoded_T_148) node _decoded_T_150 = bits(_decoded_T_142, 11, 0) node _decoded_T_151 = shl(_decoded_T_150, 4) node _decoded_T_152 = xor(_decoded_T_142, _decoded_T_151) node _decoded_T_153 = shr(_decoded_T_149, 4) node _decoded_T_154 = and(_decoded_T_153, _decoded_T_152) node _decoded_T_155 = bits(_decoded_T_149, 11, 0) node _decoded_T_156 = shl(_decoded_T_155, 4) node _decoded_T_157 = not(_decoded_T_152) node _decoded_T_158 = and(_decoded_T_156, _decoded_T_157) node _decoded_T_159 = or(_decoded_T_154, _decoded_T_158) node _decoded_T_160 = bits(_decoded_T_152, 13, 0) node _decoded_T_161 = shl(_decoded_T_160, 2) node _decoded_T_162 = xor(_decoded_T_152, _decoded_T_161) node _decoded_T_163 = shr(_decoded_T_159, 2) node _decoded_T_164 = and(_decoded_T_163, _decoded_T_162) node _decoded_T_165 = bits(_decoded_T_159, 13, 0) node _decoded_T_166 = shl(_decoded_T_165, 2) node _decoded_T_167 = not(_decoded_T_162) node _decoded_T_168 = and(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = or(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_162, 14, 0) node _decoded_T_171 = shl(_decoded_T_170, 1) node _decoded_T_172 = xor(_decoded_T_162, _decoded_T_171) node _decoded_T_173 = shr(_decoded_T_169, 1) node _decoded_T_174 = and(_decoded_T_173, _decoded_T_172) node _decoded_T_175 = bits(_decoded_T_169, 14, 0) node _decoded_T_176 = shl(_decoded_T_175, 1) node _decoded_T_177 = not(_decoded_T_172) node _decoded_T_178 = and(_decoded_T_176, _decoded_T_177) node _decoded_T_179 = or(_decoded_T_174, _decoded_T_178) node _decoded_T_180 = bits(decoded_plaOutput_2, 23, 16) node _decoded_T_181 = shl(UInt<4>(0hf), 4) node _decoded_T_182 = xor(UInt<8>(0hff), _decoded_T_181) node _decoded_T_183 = shr(_decoded_T_180, 4) node _decoded_T_184 = and(_decoded_T_183, _decoded_T_182) node _decoded_T_185 = bits(_decoded_T_180, 3, 0) node _decoded_T_186 = shl(_decoded_T_185, 4) node _decoded_T_187 = not(_decoded_T_182) node _decoded_T_188 = and(_decoded_T_186, _decoded_T_187) node _decoded_T_189 = or(_decoded_T_184, _decoded_T_188) node _decoded_T_190 = bits(_decoded_T_182, 5, 0) node _decoded_T_191 = shl(_decoded_T_190, 2) node _decoded_T_192 = xor(_decoded_T_182, _decoded_T_191) node _decoded_T_193 = shr(_decoded_T_189, 2) node _decoded_T_194 = and(_decoded_T_193, _decoded_T_192) node _decoded_T_195 = bits(_decoded_T_189, 5, 0) node _decoded_T_196 = shl(_decoded_T_195, 2) node _decoded_T_197 = not(_decoded_T_192) node _decoded_T_198 = and(_decoded_T_196, _decoded_T_197) node _decoded_T_199 = or(_decoded_T_194, _decoded_T_198) node _decoded_T_200 = bits(_decoded_T_192, 6, 0) node _decoded_T_201 = shl(_decoded_T_200, 1) node _decoded_T_202 = xor(_decoded_T_192, _decoded_T_201) node _decoded_T_203 = shr(_decoded_T_199, 1) node _decoded_T_204 = and(_decoded_T_203, _decoded_T_202) node _decoded_T_205 = bits(_decoded_T_199, 6, 0) node _decoded_T_206 = shl(_decoded_T_205, 1) node _decoded_T_207 = not(_decoded_T_202) node _decoded_T_208 = and(_decoded_T_206, _decoded_T_207) node _decoded_T_209 = or(_decoded_T_204, _decoded_T_208) node decoded_2 = cat(_decoded_T_179, _decoded_T_209) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_1_3_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`1`[3], _io_resp_2_vc_sel_1_3_T node _io_resp_2_vc_sel_1_4_T = bits(decoded_2, 12, 12) connect io.resp.`2`.vc_sel.`1`[4], _io_resp_2_vc_sel_1_4_T node _io_resp_2_vc_sel_1_5_T = bits(decoded_2, 13, 13) connect io.resp.`2`.vc_sel.`1`[5], _io_resp_2_vc_sel_1_5_T node _io_resp_2_vc_sel_1_6_T = bits(decoded_2, 14, 14) connect io.resp.`2`.vc_sel.`1`[6], _io_resp_2_vc_sel_1_6_T node _io_resp_2_vc_sel_1_7_T = bits(decoded_2, 15, 15) connect io.resp.`2`.vc_sel.`1`[7], _io_resp_2_vc_sel_1_7_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 16, 16) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 17, 17) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 18, 18) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_2_3_T = bits(decoded_2, 19, 19) connect io.resp.`2`.vc_sel.`2`[3], _io_resp_2_vc_sel_2_3_T node _io_resp_2_vc_sel_2_4_T = bits(decoded_2, 20, 20) connect io.resp.`2`.vc_sel.`2`[4], _io_resp_2_vc_sel_2_4_T node _io_resp_2_vc_sel_2_5_T = bits(decoded_2, 21, 21) connect io.resp.`2`.vc_sel.`2`[5], _io_resp_2_vc_sel_2_5_T node _io_resp_2_vc_sel_2_6_T = bits(decoded_2, 22, 22) connect io.resp.`2`.vc_sel.`2`[6], _io_resp_2_vc_sel_2_6_T node _io_resp_2_vc_sel_2_7_T = bits(decoded_2, 23, 23) connect io.resp.`2`.vc_sel.`2`[7], _io_resp_2_vc_sel_2_7_T extmodule plusarg_reader_32 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_14( // @[RouteComputer.scala:29:7] input [2:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_7 // @[RouteComputer.scala:40:14] ); wire [15:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id[1:0], io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] _decoded_orMatrixOutputs_T_4 = {&{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[2]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [15:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id[1]}; // @[pla.scala:78:21] wire [15:0] _decoded_andMatrixOutputs_T_3 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_6 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_7 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_8 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_9 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_10 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_11 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_12 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_13 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_14 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_15 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_16 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_17 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_invInputs_2 = ~io_req_2_bits_flow_egress_node_id; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_18 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _decoded_andMatrixOutputs_T_19 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _decoded_andMatrixOutputs_T_21 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] _decoded_orMatrixOutputs_T_42 = {&{decoded_invInputs_2[0], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] assign io_resp_2_vc_sel_1_4 = &{decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_1_5 = \|_decoded_orMatrixOutputs_T_42; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_1_6 = \|_decoded_orMatrixOutputs_T_42; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_1_7 = \|_decoded_orMatrixOutputs_T_42; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_0_1 = \|{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_1 = \|{&{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_2 = \|{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_3 = \|{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_4 = \|{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_5 = \|{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_6 = \|{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_7 = \|{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_1 = \|{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_2 = \|{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_3 = \|{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_4 = \|{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_5 = \|{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_6 = \|{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_7 = \|{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_5 = \|_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_2_6 = \|_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_2_7 = \|_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_1_4 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_1_5 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_1_6 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_1_7 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_59 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_70 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_59( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_70 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_5 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_5 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut	module DivSqrtRecFMToRaw_small_e5_s11_5( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e5_s11_5 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_110 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_110( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_52 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_308 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_52( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_308 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SynchronizerShiftReg_w1_d3 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = bits(io.d, 0, 0) inst output_chain of NonSyncResetSynchronizerPrimitiveShiftReg_d3 connect output_chain.clock, clock connect output_chain.reset, reset connect output_chain.io.d, _output_T wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module SynchronizerShiftReg_w1_d3( // @[SynchronizerReg.scala:169:7] input clock, // @[SynchronizerReg.scala:169:7] input reset, // @[SynchronizerReg.scala:169:7] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h0; // @[SynchronizerReg.scala:169:7, :173:39] wire _output_T = 1'h0; // @[SynchronizerReg.scala:169:7, :173:39] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:169:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:169:7] NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE : UInt<1>[7] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5]) node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = and(_T_11, _T_24) node _T_81 = and(_T_80, _T_37) node _T_82 = and(_T_81, _T_50) node _T_83 = and(_T_82, _T_63) node _T_84 = and(_T_83, _T_71) node _T_85 = and(_T_84, _T_79) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_85, UInt<1>(0h1), "") : assert_1 node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_89 : node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<1>(0h0)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_4) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_100 = shr(io.in.a.bits.source, 2) node _T_101 = eq(_T_100, UInt<1>(0h1)) node _T_102 = leq(UInt<1>(0h0), uncommonBits_5) node _T_103 = and(_T_101, _T_102) node _T_104 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_105 = and(_T_103, _T_104) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_106 = shr(io.in.a.bits.source, 2) node _T_107 = eq(_T_106, UInt<2>(0h2)) node _T_108 = leq(UInt<1>(0h0), uncommonBits_6) node _T_109 = and(_T_107, _T_108) node _T_110 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_111 = and(_T_109, _T_110) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<2>(0h3)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_7) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_119 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_120 = or(_T_93, _T_99) node _T_121 = or(_T_120, _T_105) node _T_122 = or(_T_121, _T_111) node _T_123 = or(_T_122, _T_117) node _T_124 = or(_T_123, _T_118) node _T_125 = or(_T_124, _T_119) node _T_126 = and(_T_92, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_129 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<14>(0h2000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<13>(0h1000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<17>(0h10000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<18>(0h2f000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<17>(0h10000))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<27>(0h4000000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<19>(0h40000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = or(_T_133, _T_138) node _T_170 = or(_T_169, _T_143) node _T_171 = or(_T_170, _T_148) node _T_172 = or(_T_171, _T_153) node _T_173 = or(_T_172, _T_158) node _T_174 = or(_T_173, _T_163) node _T_175 = or(_T_174, _T_168) node _T_176 = and(_T_128, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = and(_T_127, _T_177) node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_T_178, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_178, UInt<1>(0h1), "") : assert_2 node _T_182 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_183 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_184 = and(_T_182, _T_183) node _T_185 = or(UInt<1>(0h0), _T_184) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<14>(0h2000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<13>(0h1000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<18>(0h2f000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<17>(0h10000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<19>(0h40000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = or(_T_190, _T_195) node _T_227 = or(_T_226, _T_200) node _T_228 = or(_T_227, _T_205) node _T_229 = or(_T_228, _T_210) node _T_230 = or(_T_229, _T_215) node _T_231 = or(_T_230, _T_220) node _T_232 = or(_T_231, _T_225) node _T_233 = and(_T_185, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(UInt<1>(0h0), _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_8) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_9) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_10) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_11) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_293 = or(_T_266, _T_272) node _T_294 = or(_T_293, _T_278) node _T_295 = or(_T_294, _T_284) node _T_296 = or(_T_295, _T_290) node _T_297 = or(_T_296, _T_291) node _T_298 = or(_T_297, _T_292) node _T_299 = and(_T_265, _T_298) node _T_300 = or(UInt<1>(0h0), _T_299) node _T_301 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_302 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_303 = cvt(_T_302) node _T_304 = and(_T_303, asSInt(UInt<14>(0h2000))) node _T_305 = asSInt(_T_304) node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0))) node _T_307 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<17>(0h10000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<18>(0h2f000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<17>(0h10000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<27>(0h4000000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<19>(0h40000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = or(_T_306, _T_311) node _T_343 = or(_T_342, _T_316) node _T_344 = or(_T_343, _T_321) node _T_345 = or(_T_344, _T_326) node _T_346 = or(_T_345, _T_331) node _T_347 = or(_T_346, _T_336) node _T_348 = or(_T_347, _T_341) node _T_349 = and(_T_301, _T_348) node _T_350 = or(UInt<1>(0h0), _T_349) node _T_351 = and(_T_300, _T_350) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_351, UInt<1>(0h1), "") : assert_10 node _T_355 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_356 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_357 = and(_T_355, _T_356) node _T_358 = or(UInt<1>(0h0), _T_357) node _T_359 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<14>(0h2000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<13>(0h1000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<17>(0h10000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<18>(0h2f000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h10000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<27>(0h4000000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<19>(0h40000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = or(_T_363, _T_368) node _T_400 = or(_T_399, _T_373) node _T_401 = or(_T_400, _T_378) node _T_402 = or(_T_401, _T_383) node _T_403 = or(_T_402, _T_388) node _T_404 = or(_T_403, _T_393) node _T_405 = or(_T_404, _T_398) node _T_406 = and(_T_358, _T_405) node _T_407 = or(UInt<1>(0h0), _T_406) node _T_408 = and(UInt<1>(0h0), _T_407) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_408, UInt<1>(0h1), "") : assert_11 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(source_ok, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_415, UInt<1>(0h1), "") : assert_13 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_422, UInt<1>(0h1), "") : assert_15 node _T_426 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_426, UInt<1>(0h1), "") : assert_16 node _T_430 = not(io.in.a.bits.mask) node _T_431 = eq(_T_430, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_431, UInt<1>(0h1), "") : assert_17 node _T_435 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_435, UInt<1>(0h1), "") : assert_18 node _T_439 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_439 : node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_444 = shr(io.in.a.bits.source, 2) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = leq(UInt<1>(0h0), uncommonBits_12) node _T_447 = and(_T_445, _T_446) node _T_448 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_449 = and(_T_447, _T_448) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_450 = shr(io.in.a.bits.source, 2) node _T_451 = eq(_T_450, UInt<1>(0h1)) node _T_452 = leq(UInt<1>(0h0), uncommonBits_13) node _T_453 = and(_T_451, _T_452) node _T_454 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_455 = and(_T_453, _T_454) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_456 = shr(io.in.a.bits.source, 2) node _T_457 = eq(_T_456, UInt<2>(0h2)) node _T_458 = leq(UInt<1>(0h0), uncommonBits_14) node _T_459 = and(_T_457, _T_458) node _T_460 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_461 = and(_T_459, _T_460) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_462 = shr(io.in.a.bits.source, 2) node _T_463 = eq(_T_462, UInt<2>(0h3)) node _T_464 = leq(UInt<1>(0h0), uncommonBits_15) node _T_465 = and(_T_463, _T_464) node _T_466 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_470 = or(_T_443, _T_449) node _T_471 = or(_T_470, _T_455) node _T_472 = or(_T_471, _T_461) node _T_473 = or(_T_472, _T_467) node _T_474 = or(_T_473, _T_468) node _T_475 = or(_T_474, _T_469) node _T_476 = and(_T_442, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_477, UInt<1>(0h1), "") : assert_19 node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_482 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_483 = and(_T_481, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_486 = cvt(_T_485) node _T_487 = and(_T_486, asSInt(UInt<13>(0h1000))) node _T_488 = asSInt(_T_487) node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0))) node _T_490 = and(_T_484, _T_489) node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_493 = and(_T_491, _T_492) node _T_494 = or(UInt<1>(0h0), _T_493) node _T_495 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<14>(0h2000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<17>(0h10000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<18>(0h2f000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<17>(0h10000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<27>(0h4000000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<19>(0h40000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = or(_T_499, _T_504) node _T_531 = or(_T_530, _T_509) node _T_532 = or(_T_531, _T_514) node _T_533 = or(_T_532, _T_519) node _T_534 = or(_T_533, _T_524) node _T_535 = or(_T_534, _T_529) node _T_536 = and(_T_494, _T_535) node _T_537 = or(UInt<1>(0h0), _T_490) node _T_538 = or(_T_537, _T_536) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_538, UInt<1>(0h1), "") : assert_20 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(source_ok, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(is_aligned, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_548 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_548, UInt<1>(0h1), "") : assert_23 node _T_552 = eq(io.in.a.bits.mask, mask) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_552, UInt<1>(0h1), "") : assert_24 node _T_556 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_556, UInt<1>(0h1), "") : assert_25 node _T_560 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_560 : node _T_561 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_562 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<1>(0h0)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_16) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<1>(0h1)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_17) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_577 = shr(io.in.a.bits.source, 2) node _T_578 = eq(_T_577, UInt<2>(0h2)) node _T_579 = leq(UInt<1>(0h0), uncommonBits_18) node _T_580 = and(_T_578, _T_579) node _T_581 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_582 = and(_T_580, _T_581) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_583 = shr(io.in.a.bits.source, 2) node _T_584 = eq(_T_583, UInt<2>(0h3)) node _T_585 = leq(UInt<1>(0h0), uncommonBits_19) node _T_586 = and(_T_584, _T_585) node _T_587 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_588 = and(_T_586, _T_587) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_591 = or(_T_564, _T_570) node _T_592 = or(_T_591, _T_576) node _T_593 = or(_T_592, _T_582) node _T_594 = or(_T_593, _T_588) node _T_595 = or(_T_594, _T_589) node _T_596 = or(_T_595, _T_590) node _T_597 = and(_T_563, _T_596) node _T_598 = or(UInt<1>(0h0), _T_597) node _T_599 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_600 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_601 = and(_T_599, _T_600) node _T_602 = or(UInt<1>(0h0), _T_601) node _T_603 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = and(_T_602, _T_607) node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_611 = and(_T_609, _T_610) node _T_612 = or(UInt<1>(0h0), _T_611) node _T_613 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<14>(0h2000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<18>(0h2f000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<27>(0h4000000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<13>(0h1000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<19>(0h40000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = or(_T_617, _T_622) node _T_644 = or(_T_643, _T_627) node _T_645 = or(_T_644, _T_632) node _T_646 = or(_T_645, _T_637) node _T_647 = or(_T_646, _T_642) node _T_648 = and(_T_612, _T_647) node _T_649 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_650 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = and(_T_649, _T_654) node _T_656 = or(UInt<1>(0h0), _T_608) node _T_657 = or(_T_656, _T_648) node _T_658 = or(_T_657, _T_655) node _T_659 = and(_T_598, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_659, UInt<1>(0h1), "") : assert_26 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(source_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(is_aligned, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_669, UInt<1>(0h1), "") : assert_29 node _T_673 = eq(io.in.a.bits.mask, mask) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_673, UInt<1>(0h1), "") : assert_30 node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_677 : node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<1>(0h0)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_20) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_688 = shr(io.in.a.bits.source, 2) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_21) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_694 = shr(io.in.a.bits.source, 2) node _T_695 = eq(_T_694, UInt<2>(0h2)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_22) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_699 = and(_T_697, _T_698) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_700 = shr(io.in.a.bits.source, 2) node _T_701 = eq(_T_700, UInt<2>(0h3)) node _T_702 = leq(UInt<1>(0h0), uncommonBits_23) node _T_703 = and(_T_701, _T_702) node _T_704 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_708 = or(_T_681, _T_687) node _T_709 = or(_T_708, _T_693) node _T_710 = or(_T_709, _T_699) node _T_711 = or(_T_710, _T_705) node _T_712 = or(_T_711, _T_706) node _T_713 = or(_T_712, _T_707) node _T_714 = and(_T_680, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_717 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_718 = and(_T_716, _T_717) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = and(_T_719, _T_724) node _T_726 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_727 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_728 = and(_T_726, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<14>(0h2000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<18>(0h2f000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<17>(0h10000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<27>(0h4000000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<13>(0h1000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<19>(0h40000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = or(_T_734, _T_739) node _T_761 = or(_T_760, _T_744) node _T_762 = or(_T_761, _T_749) node _T_763 = or(_T_762, _T_754) node _T_764 = or(_T_763, _T_759) node _T_765 = and(_T_729, _T_764) node _T_766 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_767 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_768 = cvt(_T_767) node _T_769 = and(_T_768, asSInt(UInt<17>(0h10000))) node _T_770 = asSInt(_T_769) node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0))) node _T_772 = and(_T_766, _T_771) node _T_773 = or(UInt<1>(0h0), _T_725) node _T_774 = or(_T_773, _T_765) node _T_775 = or(_T_774, _T_772) node _T_776 = and(_T_715, _T_775) node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(_T_776, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_776, UInt<1>(0h1), "") : assert_31 node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(source_ok, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(is_aligned, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_786 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_786, UInt<1>(0h1), "") : assert_34 node _T_790 = not(mask) node _T_791 = and(io.in.a.bits.mask, _T_790) node _T_792 = eq(_T_791, UInt<1>(0h0)) node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(_T_792, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_792, UInt<1>(0h1), "") : assert_35 node _T_796 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_796 : node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_799 = and(_T_797, _T_798) node _T_800 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_801 = shr(io.in.a.bits.source, 2) node _T_802 = eq(_T_801, UInt<1>(0h0)) node _T_803 = leq(UInt<1>(0h0), uncommonBits_24) node _T_804 = and(_T_802, _T_803) node _T_805 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_806 = and(_T_804, _T_805) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_807 = shr(io.in.a.bits.source, 2) node _T_808 = eq(_T_807, UInt<1>(0h1)) node _T_809 = leq(UInt<1>(0h0), uncommonBits_25) node _T_810 = and(_T_808, _T_809) node _T_811 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_812 = and(_T_810, _T_811) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_813 = shr(io.in.a.bits.source, 2) node _T_814 = eq(_T_813, UInt<2>(0h2)) node _T_815 = leq(UInt<1>(0h0), uncommonBits_26) node _T_816 = and(_T_814, _T_815) node _T_817 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_819 = shr(io.in.a.bits.source, 2) node _T_820 = eq(_T_819, UInt<2>(0h3)) node _T_821 = leq(UInt<1>(0h0), uncommonBits_27) node _T_822 = and(_T_820, _T_821) node _T_823 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_824 = and(_T_822, _T_823) node _T_825 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_826 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_827 = or(_T_800, _T_806) node _T_828 = or(_T_827, _T_812) node _T_829 = or(_T_828, _T_818) node _T_830 = or(_T_829, _T_824) node _T_831 = or(_T_830, _T_825) node _T_832 = or(_T_831, _T_826) node _T_833 = and(_T_799, _T_832) node _T_834 = or(UInt<1>(0h0), _T_833) node _T_835 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_836 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _T_838 = or(UInt<1>(0h0), _T_837) node _T_839 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<14>(0h2000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<13>(0h1000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<18>(0h2f000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<17>(0h10000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<27>(0h4000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<13>(0h1000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<19>(0h40000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = or(_T_843, _T_848) node _T_875 = or(_T_874, _T_853) node _T_876 = or(_T_875, _T_858) node _T_877 = or(_T_876, _T_863) node _T_878 = or(_T_877, _T_868) node _T_879 = or(_T_878, _T_873) node _T_880 = and(_T_838, _T_879) node _T_881 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_882 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<17>(0h10000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = and(_T_881, _T_886) node _T_888 = or(UInt<1>(0h0), _T_880) node _T_889 = or(_T_888, _T_887) node _T_890 = and(_T_834, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_890, UInt<1>(0h1), "") : assert_36 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_900 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_900, UInt<1>(0h1), "") : assert_39 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_904, UInt<1>(0h1), "") : assert_40 node _T_908 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_908 : node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_913 = shr(io.in.a.bits.source, 2) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = leq(UInt<1>(0h0), uncommonBits_28) node _T_916 = and(_T_914, _T_915) node _T_917 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_918 = and(_T_916, _T_917) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_919 = shr(io.in.a.bits.source, 2) node _T_920 = eq(_T_919, UInt<1>(0h1)) node _T_921 = leq(UInt<1>(0h0), uncommonBits_29) node _T_922 = and(_T_920, _T_921) node _T_923 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_924 = and(_T_922, _T_923) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_925 = shr(io.in.a.bits.source, 2) node _T_926 = eq(_T_925, UInt<2>(0h2)) node _T_927 = leq(UInt<1>(0h0), uncommonBits_30) node _T_928 = and(_T_926, _T_927) node _T_929 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_930 = and(_T_928, _T_929) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_931 = shr(io.in.a.bits.source, 2) node _T_932 = eq(_T_931, UInt<2>(0h3)) node _T_933 = leq(UInt<1>(0h0), uncommonBits_31) node _T_934 = and(_T_932, _T_933) node _T_935 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_936 = and(_T_934, _T_935) node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_939 = or(_T_912, _T_918) node _T_940 = or(_T_939, _T_924) node _T_941 = or(_T_940, _T_930) node _T_942 = or(_T_941, _T_936) node _T_943 = or(_T_942, _T_937) node _T_944 = or(_T_943, _T_938) node _T_945 = and(_T_911, _T_944) node _T_946 = or(UInt<1>(0h0), _T_945) node _T_947 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_948 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_949 = and(_T_947, _T_948) node _T_950 = or(UInt<1>(0h0), _T_949) node _T_951 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<14>(0h2000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_957 = cvt(_T_956) node _T_958 = and(_T_957, asSInt(UInt<13>(0h1000))) node _T_959 = asSInt(_T_958) node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0))) node _T_961 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_962 = cvt(_T_961) node _T_963 = and(_T_962, asSInt(UInt<18>(0h2f000))) node _T_964 = asSInt(_T_963) node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0))) node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<17>(0h10000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_977 = cvt(_T_976) node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000))) node _T_979 = asSInt(_T_978) node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0))) node _T_981 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_982 = cvt(_T_981) node _T_983 = and(_T_982, asSInt(UInt<19>(0h40000))) node _T_984 = asSInt(_T_983) node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0))) node _T_986 = or(_T_955, _T_960) node _T_987 = or(_T_986, _T_965) node _T_988 = or(_T_987, _T_970) node _T_989 = or(_T_988, _T_975) node _T_990 = or(_T_989, _T_980) node _T_991 = or(_T_990, _T_985) node _T_992 = and(_T_950, _T_991) node _T_993 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_994 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = and(_T_993, _T_998) node _T_1000 = or(UInt<1>(0h0), _T_992) node _T_1001 = or(_T_1000, _T_999) node _T_1002 = and(_T_946, _T_1001) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_41 node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(source_ok, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(is_aligned, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1012 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_44 node _T_1016 = eq(io.in.a.bits.mask, mask) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_45 node _T_1020 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1020 : node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1022 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1025 = shr(io.in.a.bits.source, 2) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) node _T_1027 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1028 = and(_T_1026, _T_1027) node _T_1029 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1030 = and(_T_1028, _T_1029) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1031 = shr(io.in.a.bits.source, 2) node _T_1032 = eq(_T_1031, UInt<1>(0h1)) node _T_1033 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1034 = and(_T_1032, _T_1033) node _T_1035 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1036 = and(_T_1034, _T_1035) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1037 = shr(io.in.a.bits.source, 2) node _T_1038 = eq(_T_1037, UInt<2>(0h2)) node _T_1039 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1042 = and(_T_1040, _T_1041) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1043 = shr(io.in.a.bits.source, 2) node _T_1044 = eq(_T_1043, UInt<2>(0h3)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1050 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1051 = or(_T_1024, _T_1030) node _T_1052 = or(_T_1051, _T_1036) node _T_1053 = or(_T_1052, _T_1042) node _T_1054 = or(_T_1053, _T_1048) node _T_1055 = or(_T_1054, _T_1049) node _T_1056 = or(_T_1055, _T_1050) node _T_1057 = and(_T_1023, _T_1056) node _T_1058 = or(UInt<1>(0h0), _T_1057) node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = or(UInt<1>(0h0), _T_1061) node _T_1063 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = and(_T_1062, _T_1067) node _T_1069 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1070 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1071 = cvt(_T_1070) node _T_1072 = and(_T_1071, asSInt(UInt<14>(0h2000))) node _T_1073 = asSInt(_T_1072) node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0))) node _T_1075 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1076 = cvt(_T_1075) node _T_1077 = and(_T_1076, asSInt(UInt<17>(0h10000))) node _T_1078 = asSInt(_T_1077) node _T_1079 = eq(_T_1078, asSInt(UInt<1>(0h0))) node _T_1080 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1081 = cvt(_T_1080) node _T_1082 = and(_T_1081, asSInt(UInt<18>(0h2f000))) node _T_1083 = asSInt(_T_1082) node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0))) node _T_1085 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1086 = cvt(_T_1085) node _T_1087 = and(_T_1086, asSInt(UInt<17>(0h10000))) node _T_1088 = asSInt(_T_1087) node _T_1089 = eq(_T_1088, asSInt(UInt<1>(0h0))) node _T_1090 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1091 = cvt(_T_1090) node _T_1092 = and(_T_1091, asSInt(UInt<27>(0h4000000))) node _T_1093 = asSInt(_T_1092) node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0))) node _T_1095 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1096 = cvt(_T_1095) node _T_1097 = and(_T_1096, asSInt(UInt<13>(0h1000))) node _T_1098 = asSInt(_T_1097) node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0))) node _T_1100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1101 = cvt(_T_1100) node _T_1102 = and(_T_1101, asSInt(UInt<19>(0h40000))) node _T_1103 = asSInt(_T_1102) node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0))) node _T_1105 = or(_T_1074, _T_1079) node _T_1106 = or(_T_1105, _T_1084) node _T_1107 = or(_T_1106, _T_1089) node _T_1108 = or(_T_1107, _T_1094) node _T_1109 = or(_T_1108, _T_1099) node _T_1110 = or(_T_1109, _T_1104) node _T_1111 = and(_T_1069, _T_1110) node _T_1112 = or(UInt<1>(0h0), _T_1068) node _T_1113 = or(_T_1112, _T_1111) node _T_1114 = and(_T_1058, _T_1113) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_46 node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(source_ok, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(is_aligned, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1124 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_49 node _T_1128 = eq(io.in.a.bits.mask, mask) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_50 node _T_1132 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1136 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_52 node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_33 = shr(io.in.d.bits.source, 2) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE_1 : UInt<1>[7] connect _source_ok_WIRE_1[0], _source_ok_T_32 connect _source_ok_WIRE_1[1], _source_ok_T_38 connect _source_ok_WIRE_1[2], _source_ok_T_44 connect _source_ok_WIRE_1[3], _source_ok_T_50 connect _source_ok_WIRE_1[4], _source_ok_T_56 connect _source_ok_WIRE_1[5], _source_ok_T_57 connect _source_ok_WIRE_1[6], _source_ok_T_58 node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5]) node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1140 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1140 : node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(source_ok_1, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1144 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_54 node _T_1148 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_55 node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_56 node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_57 node _T_1160 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1160 : node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(source_ok_1, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(sink_ok, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1167 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_60 node _T_1171 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_61 node _T_1175 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_62 node _T_1179 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_63 node _T_1183 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1184 = or(UInt<1>(0h1), _T_1183) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_64 node _T_1188 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1188 : node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(source_ok_1, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(sink_ok, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1195 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_67 node _T_1199 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_68 node _T_1203 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_69 node _T_1207 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1208 = or(_T_1207, io.in.d.bits.corrupt) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_70 node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1213 = or(UInt<1>(0h1), _T_1212) node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(_T_1213, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1213, UInt<1>(0h1), "") : assert_71 node _T_1217 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1217 : node _T_1218 = asUInt(reset) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) when _T_1219 : node _T_1220 = eq(source_ok_1, UInt<1>(0h0)) when _T_1220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1221 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_73 node _T_1225 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_74 node _T_1229 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1230 = or(UInt<1>(0h1), _T_1229) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_75 node _T_1234 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1234 : node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(source_ok_1, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1238 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_77 node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1243 = or(_T_1242, io.in.d.bits.corrupt) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_78 node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1248 = or(UInt<1>(0h1), _T_1247) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_79 node _T_1252 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1252 : node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(source_ok_1, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1256 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_81 node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_82 node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1265 = or(UInt<1>(0h1), _T_1264) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1269 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1273 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1277 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1281 = eq(a_first, UInt<1>(0h0)) node _T_1282 = and(io.in.a.valid, _T_1281) when _T_1282 : node _T_1283 = eq(io.in.a.bits.opcode, opcode) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_87 node _T_1287 = eq(io.in.a.bits.param, param) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_88 node _T_1291 = eq(io.in.a.bits.size, size) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_89 node _T_1295 = eq(io.in.a.bits.source, source) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_90 node _T_1299 = eq(io.in.a.bits.address, address) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_91 node _T_1303 = and(io.in.a.ready, io.in.a.valid) node _T_1304 = and(_T_1303, a_first) when _T_1304 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1305 = eq(d_first, UInt<1>(0h0)) node _T_1306 = and(io.in.d.valid, _T_1305) when _T_1306 : node _T_1307 = eq(io.in.d.bits.opcode, opcode_1) node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(_T_1307, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1307, UInt<1>(0h1), "") : assert_92 node _T_1311 = eq(io.in.d.bits.param, param_1) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_93 node _T_1315 = eq(io.in.d.bits.size, size_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_94 node _T_1319 = eq(io.in.d.bits.source, source_1) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_95 node _T_1323 = eq(io.in.d.bits.sink, sink) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_96 node _T_1327 = eq(io.in.d.bits.denied, denied) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_97 node _T_1331 = and(io.in.d.ready, io.in.d.valid) node _T_1332 = and(_T_1331, d_first) when _T_1332 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<34>, clock, reset, UInt<34>(0h0) regreset inflight_opcodes : UInt<136>, clock, reset, UInt<136>(0h0) regreset inflight_sizes : UInt<272>, clock, reset, UInt<272>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<34> connect a_set, UInt<34>(0h0) wire a_set_wo_ready : UInt<34> connect a_set_wo_ready, UInt<34>(0h0) wire a_opcodes_set : UInt<136> connect a_opcodes_set, UInt<136>(0h0) wire a_sizes_set : UInt<272> connect a_sizes_set, UInt<272>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1333 = and(io.in.a.valid, a_first_1) node _T_1334 = and(_T_1333, UInt<1>(0h1)) when _T_1334 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(_T_1335, a_first_1) node _T_1337 = and(_T_1336, UInt<1>(0h1)) when _T_1337 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1338 = dshr(inflight, io.in.a.bits.source) node _T_1339 = bits(_T_1338, 0, 0) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<34> connect d_clr, UInt<34>(0h0) wire d_clr_wo_ready : UInt<34> connect d_clr_wo_ready, UInt<34>(0h0) wire d_opcodes_clr : UInt<136> connect d_opcodes_clr, UInt<136>(0h0) wire d_sizes_clr : UInt<272> connect d_sizes_clr, UInt<272>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1344 = and(io.in.d.valid, d_first_1) node _T_1345 = and(_T_1344, UInt<1>(0h1)) node _T_1346 = eq(d_release_ack, UInt<1>(0h0)) node _T_1347 = and(_T_1345, _T_1346) when _T_1347 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1348 = and(io.in.d.ready, io.in.d.valid) node _T_1349 = and(_T_1348, d_first_1) node _T_1350 = and(_T_1349, UInt<1>(0h1)) node _T_1351 = eq(d_release_ack, UInt<1>(0h0)) node _T_1352 = and(_T_1350, _T_1351) when _T_1352 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1353 = and(io.in.d.valid, d_first_1) node _T_1354 = and(_T_1353, UInt<1>(0h1)) node _T_1355 = eq(d_release_ack, UInt<1>(0h0)) node _T_1356 = and(_T_1354, _T_1355) when _T_1356 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1357 = dshr(inflight, io.in.d.bits.source) node _T_1358 = bits(_T_1357, 0, 0) node _T_1359 = or(_T_1358, same_cycle_resp) node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(_T_1359, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1359, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1363 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1364 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1365 = or(_T_1363, _T_1364) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_100 node _T_1369 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1370 = asUInt(reset) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) when _T_1371 : node _T_1372 = eq(_T_1369, UInt<1>(0h0)) when _T_1372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1369, UInt<1>(0h1), "") : assert_101 else : node _T_1373 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1374 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1375 = or(_T_1373, _T_1374) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_102 node _T_1379 = eq(io.in.d.bits.size, a_size_lookup) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_103 node _T_1383 = and(io.in.d.valid, d_first_1) node _T_1384 = and(_T_1383, a_first_1) node _T_1385 = and(_T_1384, io.in.a.valid) node _T_1386 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = eq(d_release_ack, UInt<1>(0h0)) node _T_1389 = and(_T_1387, _T_1388) when _T_1389 : node _T_1390 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1391 = or(_T_1390, io.in.a.ready) node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(_T_1391, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1391, UInt<1>(0h1), "") : assert_104 node _T_1395 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1396 = orr(a_set_wo_ready) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) node _T_1398 = or(_T_1395, _T_1397) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_1402 = orr(inflight) node _T_1403 = eq(_T_1402, UInt<1>(0h0)) node _T_1404 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1405 = or(_T_1403, _T_1404) node _T_1406 = lt(watchdog, plusarg_reader.out) node _T_1407 = or(_T_1405, _T_1406) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1411 = and(io.in.a.ready, io.in.a.valid) node _T_1412 = and(io.in.d.ready, io.in.d.valid) node _T_1413 = or(_T_1411, _T_1412) when _T_1413 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<34>, clock, reset, UInt<34>(0h0) regreset inflight_opcodes_1 : UInt<136>, clock, reset, UInt<136>(0h0) regreset inflight_sizes_1 : UInt<272>, clock, reset, UInt<272>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<34> connect c_set, UInt<34>(0h0) wire c_set_wo_ready : UInt<34> connect c_set_wo_ready, UInt<34>(0h0) wire c_opcodes_set : UInt<136> connect c_opcodes_set, UInt<136>(0h0) wire c_sizes_set : UInt<272> connect c_sizes_set, UInt<272>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1414 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1415 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1416 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1417 = and(_T_1415, _T_1416) node _T_1418 = and(_T_1414, _T_1417) when _T_1418 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1419 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1420 = and(_T_1419, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1421 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1422 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1423 = and(_T_1421, _T_1422) node _T_1424 = and(_T_1420, _T_1423) when _T_1424 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1425 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1426 = bits(_T_1425, 0, 0) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<34> connect d_clr_1, UInt<34>(0h0) wire d_clr_wo_ready_1 : UInt<34> connect d_clr_wo_ready_1, UInt<34>(0h0) wire d_opcodes_clr_1 : UInt<136> connect d_opcodes_clr_1, UInt<136>(0h0) wire d_sizes_clr_1 : UInt<272> connect d_sizes_clr_1, UInt<272>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1431 = and(io.in.d.valid, d_first_2) node _T_1432 = and(_T_1431, UInt<1>(0h1)) node _T_1433 = and(_T_1432, d_release_ack_1) when _T_1433 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1434 = and(io.in.d.ready, io.in.d.valid) node _T_1435 = and(_T_1434, d_first_2) node _T_1436 = and(_T_1435, UInt<1>(0h1)) node _T_1437 = and(_T_1436, d_release_ack_1) when _T_1437 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1438 = and(io.in.d.valid, d_first_2) node _T_1439 = and(_T_1438, UInt<1>(0h1)) node _T_1440 = and(_T_1439, d_release_ack_1) when _T_1440 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1441 = dshr(inflight_1, io.in.d.bits.source) node _T_1442 = bits(_T_1441, 0, 0) node _T_1443 = or(_T_1442, same_cycle_resp_1) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1447 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_109 else : node _T_1451 = eq(io.in.d.bits.size, c_size_lookup) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_110 node _T_1455 = and(io.in.d.valid, d_first_2) node _T_1456 = and(_T_1455, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1457 = and(_T_1456, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1458 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = and(_T_1459, d_release_ack_1) node _T_1461 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1462 = and(_T_1460, _T_1461) when _T_1462 : node _T_1463 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1464 = or(_T_1463, _WIRE_23.ready) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_111 node _T_1468 = orr(c_set_wo_ready) when _T_1468 : node _T_1469 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1473 = orr(inflight_1) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) node _T_1475 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1476 = or(_T_1474, _T_1475) node _T_1477 = lt(watchdog_1, plusarg_reader_1.out) node _T_1478 = or(_T_1476, _T_1477) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1482 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1483 = and(io.in.d.ready, io.in.d.valid) node _T_1484 = or(_T_1482, _T_1483) when _T_1484 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14] wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27] wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25] wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28] wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [271:0] c_sizes_set = 272'h0; // @[Monitor.scala:741:34] wire [135:0] c_opcodes_set = 136'h0; // @[Monitor.scala:740:34] wire [33:0] c_set = 34'h0; // @[Monitor.scala:738:34] wire [33:0] c_set_wo_ready = 34'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_28 = _source_ok_T_27 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_31 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_33 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_39 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_46 = _source_ok_T_45 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = _source_ok_T_51 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire _source_ok_T_57 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire _source_ok_T_58 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_63 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _T_1411 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1411; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1411; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1484; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1484; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1484; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [33:0] inflight; // @[Monitor.scala:614:27] reg [135:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [271:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [33:0] a_set; // @[Monitor.scala:626:34] wire [33:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [135:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [271:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [135:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [135:0] _a_opcode_lookup_T_6 = {132'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [135:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [271:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [271:0] _a_size_lookup_T_6 = {264'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [271:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[271:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1337 = _T_1411 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1337 ? _a_set_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1337 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1337 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1337 ? _a_opcodes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1337 ? _a_sizes_set_T_1[271:0] : 272'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [33:0] d_clr; // @[Monitor.scala:664:34] wire [33:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [135:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [271:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1383 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1383 & ~d_release_ack ? _d_clr_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1352 = _T_1484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1352 ? _d_clr_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1352 ? _d_opcodes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1352 ? _d_sizes_clr_T_5[271:0] : 272'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [33:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [33:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [33:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [135:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [135:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [135:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [271:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [271:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [271:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [33:0] inflight_1; // @[Monitor.scala:726:35] wire [33:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [135:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [135:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [271:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [271:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_2; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [135:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [135:0] _c_opcode_lookup_T_6 = {132'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [135:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [271:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [271:0] _c_size_lookup_T_6 = {264'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [271:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[271:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [33:0] d_clr_1; // @[Monitor.scala:774:34] wire [33:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [135:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [271:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1455 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1455 & d_release_ack_1 ? _d_clr_wo_ready_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1437 = _T_1484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1437 ? _d_clr_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1437 ? _d_opcodes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1437 ? _d_sizes_clr_T_11[271:0] : 272'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [33:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [33:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [135:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [135:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [271:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [271:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_43 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_43( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_4 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_4 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_4 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_4 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d	module TLMasterACDToNoC_4( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_4 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_4 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_8 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_8 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_8 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_17 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFN_e8_s24_8( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_8 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_8 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_17 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_111 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_112 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x2 : output auto : { flip in : { sync : UInt<1>[2]}, out : UInt<1>[2]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[2]} invalidate nodeIn.sync[0] invalidate nodeIn.sync[1] wire nodeOut : UInt<1>[2] invalidate nodeOut[0] invalidate nodeOut[1] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync	module IntSyncSyncCrossingSink_n1x2( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomLSUShim_1 : input clock : Clock input reset : Reset output io : { flip lsu : { exe : { flip req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<34>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}}[1], flip dis_uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[1], dis_ldq_idx : UInt<4>[1], dis_stq_idx : UInt<4>[1], ldq_full : UInt<1>[1], stq_full : UInt<1>[1], flip fp_stdata : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, flip commit : { valids : UInt<1>[1], arch_valids : UInt<1>[1], uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[1], rbk_valids : UInt<1>[1], rollback : UInt<1>, debug_wdata : UInt<64>[1]}, flip commit_load_at_rob_head : UInt<1>, clr_bsy : { valid : UInt<1>, bits : UInt<6>}[2], clr_unsafe : { valid : UInt<1>, bits : UInt<6>}[1], flip fence_dmem : UInt<1>, spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], ld_miss : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip exception : UInt<1>, fencei_rdy : UInt<1>, lxcpt : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<34>}}, flip tsc_reg : UInt, perf : { acquire : UInt<1>, release : UInt<1>, tlbMiss : UInt<1>}}, flip tracegen : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<6>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<6>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} invalidate io.tracegen.clock_enabled invalidate io.tracegen.keep_clock_enabled invalidate io.tracegen.perf.storeBufferEmptyAfterStore invalidate io.tracegen.perf.storeBufferEmptyAfterLoad invalidate io.tracegen.perf.canAcceptLoadThenLoad invalidate io.tracegen.perf.canAcceptStoreThenRMW invalidate io.tracegen.perf.canAcceptStoreThenLoad invalidate io.tracegen.perf.blocked invalidate io.tracegen.perf.tlbMiss invalidate io.tracegen.perf.grant invalidate io.tracegen.perf.release invalidate io.tracegen.perf.acquire invalidate io.tracegen.store_pending invalidate io.tracegen.ordered invalidate io.tracegen.s2_gpa_is_pte invalidate io.tracegen.s2_gpa invalidate io.tracegen.s2_xcpt.ae.st invalidate io.tracegen.s2_xcpt.ae.ld invalidate io.tracegen.s2_xcpt.gf.st invalidate io.tracegen.s2_xcpt.gf.ld invalidate io.tracegen.s2_xcpt.pf.st invalidate io.tracegen.s2_xcpt.pf.ld invalidate io.tracegen.s2_xcpt.ma.st invalidate io.tracegen.s2_xcpt.ma.ld invalidate io.tracegen.replay_next invalidate io.tracegen.resp.bits.store_data invalidate io.tracegen.resp.bits.data_raw invalidate io.tracegen.resp.bits.data_word_bypass invalidate io.tracegen.resp.bits.has_data invalidate io.tracegen.resp.bits.replay invalidate io.tracegen.resp.bits.mask invalidate io.tracegen.resp.bits.data invalidate io.tracegen.resp.bits.dv invalidate io.tracegen.resp.bits.dprv invalidate io.tracegen.resp.bits.signed invalidate io.tracegen.resp.bits.size invalidate io.tracegen.resp.bits.cmd invalidate io.tracegen.resp.bits.tag invalidate io.tracegen.resp.bits.addr invalidate io.tracegen.resp.valid invalidate io.tracegen.s2_paddr invalidate io.tracegen.s2_uncached invalidate io.tracegen.s2_kill invalidate io.tracegen.s2_nack_cause_raw invalidate io.tracegen.s2_nack invalidate io.tracegen.s1_data.mask invalidate io.tracegen.s1_data.data invalidate io.tracegen.s1_kill invalidate io.tracegen.req.bits.mask invalidate io.tracegen.req.bits.data invalidate io.tracegen.req.bits.no_xcpt invalidate io.tracegen.req.bits.no_alloc invalidate io.tracegen.req.bits.no_resp invalidate io.tracegen.req.bits.phys invalidate io.tracegen.req.bits.dv invalidate io.tracegen.req.bits.dprv invalidate io.tracegen.req.bits.signed invalidate io.tracegen.req.bits.size invalidate io.tracegen.req.bits.cmd invalidate io.tracegen.req.bits.tag invalidate io.tracegen.req.bits.addr invalidate io.tracegen.req.valid invalidate io.tracegen.req.ready invalidate io.lsu.perf.tlbMiss invalidate io.lsu.perf.release invalidate io.lsu.perf.acquire invalidate io.lsu.tsc_reg invalidate io.lsu.lxcpt.bits.badvaddr invalidate io.lsu.lxcpt.bits.cause invalidate io.lsu.lxcpt.bits.uop.debug_tsrc invalidate io.lsu.lxcpt.bits.uop.debug_fsrc invalidate io.lsu.lxcpt.bits.uop.bp_xcpt_if invalidate io.lsu.lxcpt.bits.uop.bp_debug_if invalidate io.lsu.lxcpt.bits.uop.xcpt_ma_if invalidate io.lsu.lxcpt.bits.uop.xcpt_ae_if invalidate io.lsu.lxcpt.bits.uop.xcpt_pf_if invalidate io.lsu.lxcpt.bits.uop.fp_single invalidate io.lsu.lxcpt.bits.uop.fp_val invalidate io.lsu.lxcpt.bits.uop.frs3_en invalidate io.lsu.lxcpt.bits.uop.lrs2_rtype invalidate io.lsu.lxcpt.bits.uop.lrs1_rtype invalidate io.lsu.lxcpt.bits.uop.dst_rtype invalidate io.lsu.lxcpt.bits.uop.ldst_val invalidate io.lsu.lxcpt.bits.uop.lrs3 invalidate io.lsu.lxcpt.bits.uop.lrs2 invalidate io.lsu.lxcpt.bits.uop.lrs1 invalidate io.lsu.lxcpt.bits.uop.ldst invalidate io.lsu.lxcpt.bits.uop.ldst_is_rs1 invalidate io.lsu.lxcpt.bits.uop.flush_on_commit invalidate io.lsu.lxcpt.bits.uop.is_unique invalidate io.lsu.lxcpt.bits.uop.is_sys_pc2epc invalidate io.lsu.lxcpt.bits.uop.uses_stq invalidate io.lsu.lxcpt.bits.uop.uses_ldq invalidate io.lsu.lxcpt.bits.uop.is_amo invalidate io.lsu.lxcpt.bits.uop.is_fencei invalidate io.lsu.lxcpt.bits.uop.is_fence invalidate io.lsu.lxcpt.bits.uop.mem_signed invalidate io.lsu.lxcpt.bits.uop.mem_size invalidate io.lsu.lxcpt.bits.uop.mem_cmd invalidate io.lsu.lxcpt.bits.uop.bypassable invalidate io.lsu.lxcpt.bits.uop.exc_cause invalidate io.lsu.lxcpt.bits.uop.exception invalidate io.lsu.lxcpt.bits.uop.stale_pdst invalidate io.lsu.lxcpt.bits.uop.ppred_busy invalidate io.lsu.lxcpt.bits.uop.prs3_busy invalidate io.lsu.lxcpt.bits.uop.prs2_busy invalidate io.lsu.lxcpt.bits.uop.prs1_busy invalidate io.lsu.lxcpt.bits.uop.ppred invalidate io.lsu.lxcpt.bits.uop.prs3 invalidate io.lsu.lxcpt.bits.uop.prs2 invalidate io.lsu.lxcpt.bits.uop.prs1 invalidate io.lsu.lxcpt.bits.uop.pdst invalidate io.lsu.lxcpt.bits.uop.rxq_idx invalidate io.lsu.lxcpt.bits.uop.stq_idx invalidate io.lsu.lxcpt.bits.uop.ldq_idx invalidate io.lsu.lxcpt.bits.uop.rob_idx invalidate io.lsu.lxcpt.bits.uop.csr_addr invalidate io.lsu.lxcpt.bits.uop.imm_packed invalidate io.lsu.lxcpt.bits.uop.taken invalidate io.lsu.lxcpt.bits.uop.pc_lob invalidate io.lsu.lxcpt.bits.uop.edge_inst invalidate io.lsu.lxcpt.bits.uop.ftq_idx invalidate io.lsu.lxcpt.bits.uop.br_tag invalidate io.lsu.lxcpt.bits.uop.br_mask invalidate io.lsu.lxcpt.bits.uop.is_sfb invalidate io.lsu.lxcpt.bits.uop.is_jal invalidate io.lsu.lxcpt.bits.uop.is_jalr invalidate io.lsu.lxcpt.bits.uop.is_br invalidate io.lsu.lxcpt.bits.uop.iw_p2_poisoned invalidate io.lsu.lxcpt.bits.uop.iw_p1_poisoned invalidate io.lsu.lxcpt.bits.uop.iw_state invalidate io.lsu.lxcpt.bits.uop.ctrl.is_std invalidate io.lsu.lxcpt.bits.uop.ctrl.is_sta invalidate io.lsu.lxcpt.bits.uop.ctrl.is_load invalidate io.lsu.lxcpt.bits.uop.ctrl.csr_cmd invalidate io.lsu.lxcpt.bits.uop.ctrl.fcn_dw invalidate io.lsu.lxcpt.bits.uop.ctrl.op_fcn invalidate io.lsu.lxcpt.bits.uop.ctrl.imm_sel invalidate io.lsu.lxcpt.bits.uop.ctrl.op2_sel invalidate io.lsu.lxcpt.bits.uop.ctrl.op1_sel invalidate io.lsu.lxcpt.bits.uop.ctrl.br_type invalidate io.lsu.lxcpt.bits.uop.fu_code invalidate io.lsu.lxcpt.bits.uop.iq_type invalidate io.lsu.lxcpt.bits.uop.debug_pc invalidate io.lsu.lxcpt.bits.uop.is_rvc invalidate io.lsu.lxcpt.bits.uop.debug_inst invalidate io.lsu.lxcpt.bits.uop.inst invalidate io.lsu.lxcpt.bits.uop.uopc invalidate io.lsu.lxcpt.valid invalidate io.lsu.fencei_rdy invalidate io.lsu.exception invalidate io.lsu.rob_head_idx invalidate io.lsu.rob_pnr_idx invalidate io.lsu.brupdate.b2.target_offset invalidate io.lsu.brupdate.b2.jalr_target invalidate io.lsu.brupdate.b2.pc_sel invalidate io.lsu.brupdate.b2.cfi_type invalidate io.lsu.brupdate.b2.taken invalidate io.lsu.brupdate.b2.mispredict invalidate io.lsu.brupdate.b2.valid invalidate io.lsu.brupdate.b2.uop.debug_tsrc invalidate io.lsu.brupdate.b2.uop.debug_fsrc invalidate io.lsu.brupdate.b2.uop.bp_xcpt_if invalidate io.lsu.brupdate.b2.uop.bp_debug_if invalidate io.lsu.brupdate.b2.uop.xcpt_ma_if invalidate io.lsu.brupdate.b2.uop.xcpt_ae_if invalidate io.lsu.brupdate.b2.uop.xcpt_pf_if invalidate io.lsu.brupdate.b2.uop.fp_single invalidate io.lsu.brupdate.b2.uop.fp_val invalidate io.lsu.brupdate.b2.uop.frs3_en invalidate io.lsu.brupdate.b2.uop.lrs2_rtype invalidate io.lsu.brupdate.b2.uop.lrs1_rtype invalidate io.lsu.brupdate.b2.uop.dst_rtype invalidate io.lsu.brupdate.b2.uop.ldst_val invalidate io.lsu.brupdate.b2.uop.lrs3 invalidate io.lsu.brupdate.b2.uop.lrs2 invalidate io.lsu.brupdate.b2.uop.lrs1 invalidate io.lsu.brupdate.b2.uop.ldst invalidate io.lsu.brupdate.b2.uop.ldst_is_rs1 invalidate io.lsu.brupdate.b2.uop.flush_on_commit invalidate io.lsu.brupdate.b2.uop.is_unique invalidate io.lsu.brupdate.b2.uop.is_sys_pc2epc invalidate io.lsu.brupdate.b2.uop.uses_stq invalidate io.lsu.brupdate.b2.uop.uses_ldq invalidate io.lsu.brupdate.b2.uop.is_amo invalidate io.lsu.brupdate.b2.uop.is_fencei invalidate io.lsu.brupdate.b2.uop.is_fence invalidate io.lsu.brupdate.b2.uop.mem_signed invalidate io.lsu.brupdate.b2.uop.mem_size invalidate io.lsu.brupdate.b2.uop.mem_cmd invalidate io.lsu.brupdate.b2.uop.bypassable invalidate io.lsu.brupdate.b2.uop.exc_cause invalidate io.lsu.brupdate.b2.uop.exception invalidate io.lsu.brupdate.b2.uop.stale_pdst invalidate io.lsu.brupdate.b2.uop.ppred_busy invalidate io.lsu.brupdate.b2.uop.prs3_busy invalidate io.lsu.brupdate.b2.uop.prs2_busy invalidate io.lsu.brupdate.b2.uop.prs1_busy invalidate io.lsu.brupdate.b2.uop.ppred invalidate io.lsu.brupdate.b2.uop.prs3 invalidate io.lsu.brupdate.b2.uop.prs2 invalidate io.lsu.brupdate.b2.uop.prs1 invalidate io.lsu.brupdate.b2.uop.pdst invalidate io.lsu.brupdate.b2.uop.rxq_idx invalidate io.lsu.brupdate.b2.uop.stq_idx invalidate io.lsu.brupdate.b2.uop.ldq_idx invalidate io.lsu.brupdate.b2.uop.rob_idx invalidate io.lsu.brupdate.b2.uop.csr_addr invalidate io.lsu.brupdate.b2.uop.imm_packed invalidate io.lsu.brupdate.b2.uop.taken invalidate io.lsu.brupdate.b2.uop.pc_lob invalidate io.lsu.brupdate.b2.uop.edge_inst invalidate io.lsu.brupdate.b2.uop.ftq_idx invalidate io.lsu.brupdate.b2.uop.br_tag invalidate io.lsu.brupdate.b2.uop.br_mask invalidate io.lsu.brupdate.b2.uop.is_sfb invalidate io.lsu.brupdate.b2.uop.is_jal invalidate io.lsu.brupdate.b2.uop.is_jalr invalidate io.lsu.brupdate.b2.uop.is_br invalidate io.lsu.brupdate.b2.uop.iw_p2_poisoned invalidate io.lsu.brupdate.b2.uop.iw_p1_poisoned invalidate io.lsu.brupdate.b2.uop.iw_state invalidate io.lsu.brupdate.b2.uop.ctrl.is_std invalidate io.lsu.brupdate.b2.uop.ctrl.is_sta invalidate io.lsu.brupdate.b2.uop.ctrl.is_load invalidate io.lsu.brupdate.b2.uop.ctrl.csr_cmd invalidate io.lsu.brupdate.b2.uop.ctrl.fcn_dw invalidate io.lsu.brupdate.b2.uop.ctrl.op_fcn invalidate io.lsu.brupdate.b2.uop.ctrl.imm_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op2_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op1_sel invalidate io.lsu.brupdate.b2.uop.ctrl.br_type invalidate io.lsu.brupdate.b2.uop.fu_code invalidate io.lsu.brupdate.b2.uop.iq_type invalidate io.lsu.brupdate.b2.uop.debug_pc invalidate io.lsu.brupdate.b2.uop.is_rvc invalidate io.lsu.brupdate.b2.uop.debug_inst invalidate io.lsu.brupdate.b2.uop.inst invalidate io.lsu.brupdate.b2.uop.uopc invalidate io.lsu.brupdate.b1.mispredict_mask invalidate io.lsu.brupdate.b1.resolve_mask invalidate io.lsu.ld_miss invalidate io.lsu.spec_ld_wakeup[0].bits invalidate io.lsu.spec_ld_wakeup[0].valid invalidate io.lsu.fence_dmem invalidate io.lsu.clr_unsafe[0].bits invalidate io.lsu.clr_unsafe[0].valid invalidate io.lsu.clr_bsy[0].bits invalidate io.lsu.clr_bsy[0].valid invalidate io.lsu.clr_bsy[1].bits invalidate io.lsu.clr_bsy[1].valid invalidate io.lsu.commit_load_at_rob_head invalidate io.lsu.commit.debug_wdata[0] invalidate io.lsu.commit.rollback invalidate io.lsu.commit.rbk_valids[0] invalidate io.lsu.commit.debug_insts[0] invalidate io.lsu.commit.fflags.bits invalidate io.lsu.commit.fflags.valid invalidate io.lsu.commit.uops[0].debug_tsrc invalidate io.lsu.commit.uops[0].debug_fsrc invalidate io.lsu.commit.uops[0].bp_xcpt_if invalidate io.lsu.commit.uops[0].bp_debug_if invalidate io.lsu.commit.uops[0].xcpt_ma_if invalidate io.lsu.commit.uops[0].xcpt_ae_if invalidate io.lsu.commit.uops[0].xcpt_pf_if invalidate io.lsu.commit.uops[0].fp_single invalidate io.lsu.commit.uops[0].fp_val invalidate io.lsu.commit.uops[0].frs3_en invalidate io.lsu.commit.uops[0].lrs2_rtype invalidate io.lsu.commit.uops[0].lrs1_rtype invalidate io.lsu.commit.uops[0].dst_rtype invalidate io.lsu.commit.uops[0].ldst_val invalidate io.lsu.commit.uops[0].lrs3 invalidate io.lsu.commit.uops[0].lrs2 invalidate io.lsu.commit.uops[0].lrs1 invalidate io.lsu.commit.uops[0].ldst invalidate io.lsu.commit.uops[0].ldst_is_rs1 invalidate io.lsu.commit.uops[0].flush_on_commit invalidate io.lsu.commit.uops[0].is_unique invalidate io.lsu.commit.uops[0].is_sys_pc2epc invalidate io.lsu.commit.uops[0].uses_stq invalidate io.lsu.commit.uops[0].uses_ldq invalidate io.lsu.commit.uops[0].is_amo invalidate io.lsu.commit.uops[0].is_fencei invalidate io.lsu.commit.uops[0].is_fence invalidate io.lsu.commit.uops[0].mem_signed invalidate io.lsu.commit.uops[0].mem_size invalidate io.lsu.commit.uops[0].mem_cmd invalidate io.lsu.commit.uops[0].bypassable invalidate io.lsu.commit.uops[0].exc_cause invalidate io.lsu.commit.uops[0].exception invalidate io.lsu.commit.uops[0].stale_pdst invalidate io.lsu.commit.uops[0].ppred_busy invalidate io.lsu.commit.uops[0].prs3_busy invalidate io.lsu.commit.uops[0].prs2_busy invalidate io.lsu.commit.uops[0].prs1_busy invalidate io.lsu.commit.uops[0].ppred invalidate io.lsu.commit.uops[0].prs3 invalidate io.lsu.commit.uops[0].prs2 invalidate io.lsu.commit.uops[0].prs1 invalidate io.lsu.commit.uops[0].pdst invalidate io.lsu.commit.uops[0].rxq_idx invalidate io.lsu.commit.uops[0].stq_idx invalidate io.lsu.commit.uops[0].ldq_idx invalidate io.lsu.commit.uops[0].rob_idx invalidate io.lsu.commit.uops[0].csr_addr invalidate io.lsu.commit.uops[0].imm_packed invalidate io.lsu.commit.uops[0].taken invalidate io.lsu.commit.uops[0].pc_lob invalidate io.lsu.commit.uops[0].edge_inst invalidate io.lsu.commit.uops[0].ftq_idx invalidate io.lsu.commit.uops[0].br_tag invalidate io.lsu.commit.uops[0].br_mask invalidate io.lsu.commit.uops[0].is_sfb invalidate io.lsu.commit.uops[0].is_jal invalidate io.lsu.commit.uops[0].is_jalr invalidate io.lsu.commit.uops[0].is_br invalidate io.lsu.commit.uops[0].iw_p2_poisoned invalidate io.lsu.commit.uops[0].iw_p1_poisoned invalidate io.lsu.commit.uops[0].iw_state invalidate io.lsu.commit.uops[0].ctrl.is_std invalidate io.lsu.commit.uops[0].ctrl.is_sta invalidate io.lsu.commit.uops[0].ctrl.is_load invalidate io.lsu.commit.uops[0].ctrl.csr_cmd invalidate io.lsu.commit.uops[0].ctrl.fcn_dw invalidate io.lsu.commit.uops[0].ctrl.op_fcn invalidate io.lsu.commit.uops[0].ctrl.imm_sel invalidate io.lsu.commit.uops[0].ctrl.op2_sel invalidate io.lsu.commit.uops[0].ctrl.op1_sel invalidate io.lsu.commit.uops[0].ctrl.br_type invalidate io.lsu.commit.uops[0].fu_code invalidate io.lsu.commit.uops[0].iq_type invalidate io.lsu.commit.uops[0].debug_pc invalidate io.lsu.commit.uops[0].is_rvc invalidate io.lsu.commit.uops[0].debug_inst invalidate io.lsu.commit.uops[0].inst invalidate io.lsu.commit.uops[0].uopc invalidate io.lsu.commit.arch_valids[0] invalidate io.lsu.commit.valids[0] invalidate io.lsu.fp_stdata.bits.fflags.bits.flags invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exception invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.taken invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uopc invalidate io.lsu.fp_stdata.bits.fflags.valid invalidate io.lsu.fp_stdata.bits.predicated invalidate io.lsu.fp_stdata.bits.data invalidate io.lsu.fp_stdata.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.uop.exception invalidate io.lsu.fp_stdata.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.uop.taken invalidate io.lsu.fp_stdata.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.uop.inst invalidate io.lsu.fp_stdata.bits.uop.uopc invalidate io.lsu.fp_stdata.valid invalidate io.lsu.fp_stdata.ready invalidate io.lsu.stq_full[0] invalidate io.lsu.ldq_full[0] invalidate io.lsu.dis_stq_idx[0] invalidate io.lsu.dis_ldq_idx[0] invalidate io.lsu.dis_uops[0].bits.debug_tsrc invalidate io.lsu.dis_uops[0].bits.debug_fsrc invalidate io.lsu.dis_uops[0].bits.bp_xcpt_if invalidate io.lsu.dis_uops[0].bits.bp_debug_if invalidate io.lsu.dis_uops[0].bits.xcpt_ma_if invalidate io.lsu.dis_uops[0].bits.xcpt_ae_if invalidate io.lsu.dis_uops[0].bits.xcpt_pf_if invalidate io.lsu.dis_uops[0].bits.fp_single invalidate io.lsu.dis_uops[0].bits.fp_val invalidate io.lsu.dis_uops[0].bits.frs3_en invalidate io.lsu.dis_uops[0].bits.lrs2_rtype invalidate io.lsu.dis_uops[0].bits.lrs1_rtype invalidate io.lsu.dis_uops[0].bits.dst_rtype invalidate io.lsu.dis_uops[0].bits.ldst_val invalidate io.lsu.dis_uops[0].bits.lrs3 invalidate io.lsu.dis_uops[0].bits.lrs2 invalidate io.lsu.dis_uops[0].bits.lrs1 invalidate io.lsu.dis_uops[0].bits.ldst invalidate io.lsu.dis_uops[0].bits.ldst_is_rs1 invalidate io.lsu.dis_uops[0].bits.flush_on_commit invalidate io.lsu.dis_uops[0].bits.is_unique invalidate io.lsu.dis_uops[0].bits.is_sys_pc2epc invalidate io.lsu.dis_uops[0].bits.uses_stq invalidate io.lsu.dis_uops[0].bits.uses_ldq invalidate io.lsu.dis_uops[0].bits.is_amo invalidate io.lsu.dis_uops[0].bits.is_fencei invalidate io.lsu.dis_uops[0].bits.is_fence invalidate io.lsu.dis_uops[0].bits.mem_signed invalidate io.lsu.dis_uops[0].bits.mem_size invalidate io.lsu.dis_uops[0].bits.mem_cmd invalidate io.lsu.dis_uops[0].bits.bypassable invalidate io.lsu.dis_uops[0].bits.exc_cause invalidate io.lsu.dis_uops[0].bits.exception invalidate io.lsu.dis_uops[0].bits.stale_pdst invalidate io.lsu.dis_uops[0].bits.ppred_busy invalidate io.lsu.dis_uops[0].bits.prs3_busy invalidate io.lsu.dis_uops[0].bits.prs2_busy invalidate io.lsu.dis_uops[0].bits.prs1_busy invalidate io.lsu.dis_uops[0].bits.ppred invalidate io.lsu.dis_uops[0].bits.prs3 invalidate io.lsu.dis_uops[0].bits.prs2 invalidate io.lsu.dis_uops[0].bits.prs1 invalidate io.lsu.dis_uops[0].bits.pdst invalidate io.lsu.dis_uops[0].bits.rxq_idx invalidate io.lsu.dis_uops[0].bits.stq_idx invalidate io.lsu.dis_uops[0].bits.ldq_idx invalidate io.lsu.dis_uops[0].bits.rob_idx invalidate io.lsu.dis_uops[0].bits.csr_addr invalidate io.lsu.dis_uops[0].bits.imm_packed invalidate io.lsu.dis_uops[0].bits.taken invalidate io.lsu.dis_uops[0].bits.pc_lob invalidate io.lsu.dis_uops[0].bits.edge_inst invalidate io.lsu.dis_uops[0].bits.ftq_idx invalidate io.lsu.dis_uops[0].bits.br_tag invalidate io.lsu.dis_uops[0].bits.br_mask invalidate io.lsu.dis_uops[0].bits.is_sfb invalidate io.lsu.dis_uops[0].bits.is_jal invalidate io.lsu.dis_uops[0].bits.is_jalr invalidate io.lsu.dis_uops[0].bits.is_br invalidate io.lsu.dis_uops[0].bits.iw_p2_poisoned invalidate io.lsu.dis_uops[0].bits.iw_p1_poisoned invalidate io.lsu.dis_uops[0].bits.iw_state invalidate io.lsu.dis_uops[0].bits.ctrl.is_std invalidate io.lsu.dis_uops[0].bits.ctrl.is_sta invalidate io.lsu.dis_uops[0].bits.ctrl.is_load invalidate io.lsu.dis_uops[0].bits.ctrl.csr_cmd invalidate io.lsu.dis_uops[0].bits.ctrl.fcn_dw invalidate io.lsu.dis_uops[0].bits.ctrl.op_fcn invalidate io.lsu.dis_uops[0].bits.ctrl.imm_sel invalidate io.lsu.dis_uops[0].bits.ctrl.op2_sel invalidate io.lsu.dis_uops[0].bits.ctrl.op1_sel invalidate io.lsu.dis_uops[0].bits.ctrl.br_type invalidate io.lsu.dis_uops[0].bits.fu_code invalidate io.lsu.dis_uops[0].bits.iq_type invalidate io.lsu.dis_uops[0].bits.debug_pc invalidate io.lsu.dis_uops[0].bits.is_rvc invalidate io.lsu.dis_uops[0].bits.debug_inst invalidate io.lsu.dis_uops[0].bits.inst invalidate io.lsu.dis_uops[0].bits.uopc invalidate io.lsu.dis_uops[0].valid invalidate io.lsu.exe[0].fresp.bits.fflags.bits.flags invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].fresp.bits.fflags.valid invalidate io.lsu.exe[0].fresp.bits.predicated invalidate io.lsu.exe[0].fresp.bits.data invalidate io.lsu.exe[0].fresp.bits.uop.debug_tsrc invalidate io.lsu.exe[0].fresp.bits.uop.debug_fsrc invalidate io.lsu.exe[0].fresp.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].fresp.bits.uop.bp_debug_if invalidate io.lsu.exe[0].fresp.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].fresp.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].fresp.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].fresp.bits.uop.fp_single invalidate io.lsu.exe[0].fresp.bits.uop.fp_val invalidate io.lsu.exe[0].fresp.bits.uop.frs3_en invalidate io.lsu.exe[0].fresp.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].fresp.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].fresp.bits.uop.dst_rtype invalidate io.lsu.exe[0].fresp.bits.uop.ldst_val invalidate io.lsu.exe[0].fresp.bits.uop.lrs3 invalidate io.lsu.exe[0].fresp.bits.uop.lrs2 invalidate io.lsu.exe[0].fresp.bits.uop.lrs1 invalidate io.lsu.exe[0].fresp.bits.uop.ldst invalidate io.lsu.exe[0].fresp.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].fresp.bits.uop.flush_on_commit invalidate io.lsu.exe[0].fresp.bits.uop.is_unique invalidate io.lsu.exe[0].fresp.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].fresp.bits.uop.uses_stq invalidate io.lsu.exe[0].fresp.bits.uop.uses_ldq invalidate io.lsu.exe[0].fresp.bits.uop.is_amo invalidate io.lsu.exe[0].fresp.bits.uop.is_fencei invalidate io.lsu.exe[0].fresp.bits.uop.is_fence invalidate io.lsu.exe[0].fresp.bits.uop.mem_signed invalidate io.lsu.exe[0].fresp.bits.uop.mem_size invalidate io.lsu.exe[0].fresp.bits.uop.mem_cmd invalidate io.lsu.exe[0].fresp.bits.uop.bypassable invalidate io.lsu.exe[0].fresp.bits.uop.exc_cause invalidate io.lsu.exe[0].fresp.bits.uop.exception invalidate io.lsu.exe[0].fresp.bits.uop.stale_pdst invalidate io.lsu.exe[0].fresp.bits.uop.ppred_busy invalidate io.lsu.exe[0].fresp.bits.uop.prs3_busy invalidate io.lsu.exe[0].fresp.bits.uop.prs2_busy invalidate io.lsu.exe[0].fresp.bits.uop.prs1_busy invalidate io.lsu.exe[0].fresp.bits.uop.ppred invalidate io.lsu.exe[0].fresp.bits.uop.prs3 invalidate io.lsu.exe[0].fresp.bits.uop.prs2 invalidate io.lsu.exe[0].fresp.bits.uop.prs1 invalidate io.lsu.exe[0].fresp.bits.uop.pdst invalidate io.lsu.exe[0].fresp.bits.uop.rxq_idx invalidate io.lsu.exe[0].fresp.bits.uop.stq_idx invalidate io.lsu.exe[0].fresp.bits.uop.ldq_idx invalidate io.lsu.exe[0].fresp.bits.uop.rob_idx invalidate io.lsu.exe[0].fresp.bits.uop.csr_addr invalidate io.lsu.exe[0].fresp.bits.uop.imm_packed invalidate io.lsu.exe[0].fresp.bits.uop.taken invalidate io.lsu.exe[0].fresp.bits.uop.pc_lob invalidate io.lsu.exe[0].fresp.bits.uop.edge_inst invalidate io.lsu.exe[0].fresp.bits.uop.ftq_idx invalidate io.lsu.exe[0].fresp.bits.uop.br_tag invalidate io.lsu.exe[0].fresp.bits.uop.br_mask invalidate io.lsu.exe[0].fresp.bits.uop.is_sfb invalidate io.lsu.exe[0].fresp.bits.uop.is_jal invalidate io.lsu.exe[0].fresp.bits.uop.is_jalr invalidate io.lsu.exe[0].fresp.bits.uop.is_br invalidate io.lsu.exe[0].fresp.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].fresp.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].fresp.bits.uop.iw_state invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].fresp.bits.uop.fu_code invalidate io.lsu.exe[0].fresp.bits.uop.iq_type invalidate io.lsu.exe[0].fresp.bits.uop.debug_pc invalidate io.lsu.exe[0].fresp.bits.uop.is_rvc invalidate io.lsu.exe[0].fresp.bits.uop.debug_inst invalidate io.lsu.exe[0].fresp.bits.uop.inst invalidate io.lsu.exe[0].fresp.bits.uop.uopc invalidate io.lsu.exe[0].fresp.valid invalidate io.lsu.exe[0].fresp.ready invalidate io.lsu.exe[0].iresp.bits.fflags.bits.flags invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].iresp.bits.fflags.valid invalidate io.lsu.exe[0].iresp.bits.predicated invalidate io.lsu.exe[0].iresp.bits.data invalidate io.lsu.exe[0].iresp.bits.uop.debug_tsrc invalidate io.lsu.exe[0].iresp.bits.uop.debug_fsrc invalidate io.lsu.exe[0].iresp.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].iresp.bits.uop.bp_debug_if invalidate io.lsu.exe[0].iresp.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].iresp.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].iresp.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].iresp.bits.uop.fp_single invalidate io.lsu.exe[0].iresp.bits.uop.fp_val invalidate io.lsu.exe[0].iresp.bits.uop.frs3_en invalidate io.lsu.exe[0].iresp.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].iresp.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].iresp.bits.uop.dst_rtype invalidate io.lsu.exe[0].iresp.bits.uop.ldst_val invalidate io.lsu.exe[0].iresp.bits.uop.lrs3 invalidate io.lsu.exe[0].iresp.bits.uop.lrs2 invalidate io.lsu.exe[0].iresp.bits.uop.lrs1 invalidate io.lsu.exe[0].iresp.bits.uop.ldst invalidate io.lsu.exe[0].iresp.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].iresp.bits.uop.flush_on_commit invalidate io.lsu.exe[0].iresp.bits.uop.is_unique invalidate io.lsu.exe[0].iresp.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].iresp.bits.uop.uses_stq invalidate io.lsu.exe[0].iresp.bits.uop.uses_ldq invalidate io.lsu.exe[0].iresp.bits.uop.is_amo invalidate io.lsu.exe[0].iresp.bits.uop.is_fencei invalidate io.lsu.exe[0].iresp.bits.uop.is_fence invalidate io.lsu.exe[0].iresp.bits.uop.mem_signed invalidate io.lsu.exe[0].iresp.bits.uop.mem_size invalidate io.lsu.exe[0].iresp.bits.uop.mem_cmd invalidate io.lsu.exe[0].iresp.bits.uop.bypassable invalidate io.lsu.exe[0].iresp.bits.uop.exc_cause invalidate io.lsu.exe[0].iresp.bits.uop.exception invalidate io.lsu.exe[0].iresp.bits.uop.stale_pdst invalidate io.lsu.exe[0].iresp.bits.uop.ppred_busy invalidate io.lsu.exe[0].iresp.bits.uop.prs3_busy invalidate io.lsu.exe[0].iresp.bits.uop.prs2_busy invalidate io.lsu.exe[0].iresp.bits.uop.prs1_busy invalidate io.lsu.exe[0].iresp.bits.uop.ppred invalidate io.lsu.exe[0].iresp.bits.uop.prs3 invalidate io.lsu.exe[0].iresp.bits.uop.prs2 invalidate io.lsu.exe[0].iresp.bits.uop.prs1 invalidate io.lsu.exe[0].iresp.bits.uop.pdst invalidate io.lsu.exe[0].iresp.bits.uop.rxq_idx invalidate io.lsu.exe[0].iresp.bits.uop.stq_idx invalidate io.lsu.exe[0].iresp.bits.uop.ldq_idx invalidate io.lsu.exe[0].iresp.bits.uop.rob_idx invalidate io.lsu.exe[0].iresp.bits.uop.csr_addr invalidate io.lsu.exe[0].iresp.bits.uop.imm_packed invalidate io.lsu.exe[0].iresp.bits.uop.taken invalidate io.lsu.exe[0].iresp.bits.uop.pc_lob invalidate io.lsu.exe[0].iresp.bits.uop.edge_inst invalidate io.lsu.exe[0].iresp.bits.uop.ftq_idx invalidate io.lsu.exe[0].iresp.bits.uop.br_tag invalidate io.lsu.exe[0].iresp.bits.uop.br_mask invalidate io.lsu.exe[0].iresp.bits.uop.is_sfb invalidate io.lsu.exe[0].iresp.bits.uop.is_jal invalidate io.lsu.exe[0].iresp.bits.uop.is_jalr invalidate io.lsu.exe[0].iresp.bits.uop.is_br invalidate io.lsu.exe[0].iresp.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].iresp.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].iresp.bits.uop.iw_state invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].iresp.bits.uop.fu_code invalidate io.lsu.exe[0].iresp.bits.uop.iq_type invalidate io.lsu.exe[0].iresp.bits.uop.debug_pc invalidate io.lsu.exe[0].iresp.bits.uop.is_rvc invalidate io.lsu.exe[0].iresp.bits.uop.debug_inst invalidate io.lsu.exe[0].iresp.bits.uop.inst invalidate io.lsu.exe[0].iresp.bits.uop.uopc invalidate io.lsu.exe[0].iresp.valid invalidate io.lsu.exe[0].iresp.ready invalidate io.lsu.exe[0].req.bits.sfence.bits.hg invalidate io.lsu.exe[0].req.bits.sfence.bits.hv invalidate io.lsu.exe[0].req.bits.sfence.bits.asid invalidate io.lsu.exe[0].req.bits.sfence.bits.addr invalidate io.lsu.exe[0].req.bits.sfence.bits.rs2 invalidate io.lsu.exe[0].req.bits.sfence.bits.rs1 invalidate io.lsu.exe[0].req.bits.sfence.valid invalidate io.lsu.exe[0].req.bits.mxcpt.bits invalidate io.lsu.exe[0].req.bits.mxcpt.valid invalidate io.lsu.exe[0].req.bits.addr invalidate io.lsu.exe[0].req.bits.fflags.bits.flags invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].req.bits.fflags.valid invalidate io.lsu.exe[0].req.bits.data invalidate io.lsu.exe[0].req.bits.predicated invalidate io.lsu.exe[0].req.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.uop.exception invalidate io.lsu.exe[0].req.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.uop.taken invalidate io.lsu.exe[0].req.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.uop.inst invalidate io.lsu.exe[0].req.bits.uop.uopc invalidate io.lsu.exe[0].req.valid connect io.lsu.tsc_reg, UInt<1>(0h0) reg rob : { addr : UInt<34>, tag : UInt<6>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}[64], clock node _rob_respd_T = not(UInt<64>(0h0)) node _rob_respd_T_1 = bits(_rob_respd_T, 0, 0) node _rob_respd_T_2 = bits(_rob_respd_T, 1, 1) node _rob_respd_T_3 = bits(_rob_respd_T, 2, 2) node _rob_respd_T_4 = bits(_rob_respd_T, 3, 3) node _rob_respd_T_5 = bits(_rob_respd_T, 4, 4) node _rob_respd_T_6 = bits(_rob_respd_T, 5, 5) node _rob_respd_T_7 = bits(_rob_respd_T, 6, 6) node _rob_respd_T_8 = bits(_rob_respd_T, 7, 7) node _rob_respd_T_9 = bits(_rob_respd_T, 8, 8) node _rob_respd_T_10 = bits(_rob_respd_T, 9, 9) node _rob_respd_T_11 = bits(_rob_respd_T, 10, 10) node _rob_respd_T_12 = bits(_rob_respd_T, 11, 11) node _rob_respd_T_13 = bits(_rob_respd_T, 12, 12) node _rob_respd_T_14 = bits(_rob_respd_T, 13, 13) node _rob_respd_T_15 = bits(_rob_respd_T, 14, 14) node _rob_respd_T_16 = bits(_rob_respd_T, 15, 15) node _rob_respd_T_17 = bits(_rob_respd_T, 16, 16) node _rob_respd_T_18 = bits(_rob_respd_T, 17, 17) node _rob_respd_T_19 = bits(_rob_respd_T, 18, 18) node _rob_respd_T_20 = bits(_rob_respd_T, 19, 19) node _rob_respd_T_21 = bits(_rob_respd_T, 20, 20) node _rob_respd_T_22 = bits(_rob_respd_T, 21, 21) node _rob_respd_T_23 = bits(_rob_respd_T, 22, 22) node _rob_respd_T_24 = bits(_rob_respd_T, 23, 23) node _rob_respd_T_25 = bits(_rob_respd_T, 24, 24) node _rob_respd_T_26 = bits(_rob_respd_T, 25, 25) node _rob_respd_T_27 = bits(_rob_respd_T, 26, 26) node _rob_respd_T_28 = bits(_rob_respd_T, 27, 27) node _rob_respd_T_29 = bits(_rob_respd_T, 28, 28) node _rob_respd_T_30 = bits(_rob_respd_T, 29, 29) node _rob_respd_T_31 = bits(_rob_respd_T, 30, 30) node _rob_respd_T_32 = bits(_rob_respd_T, 31, 31) node _rob_respd_T_33 = bits(_rob_respd_T, 32, 32) node _rob_respd_T_34 = bits(_rob_respd_T, 33, 33) node _rob_respd_T_35 = bits(_rob_respd_T, 34, 34) node _rob_respd_T_36 = bits(_rob_respd_T, 35, 35) node _rob_respd_T_37 = bits(_rob_respd_T, 36, 36) node _rob_respd_T_38 = bits(_rob_respd_T, 37, 37) node _rob_respd_T_39 = bits(_rob_respd_T, 38, 38) node _rob_respd_T_40 = bits(_rob_respd_T, 39, 39) node _rob_respd_T_41 = bits(_rob_respd_T, 40, 40) node _rob_respd_T_42 = bits(_rob_respd_T, 41, 41) node _rob_respd_T_43 = bits(_rob_respd_T, 42, 42) node _rob_respd_T_44 = bits(_rob_respd_T, 43, 43) node _rob_respd_T_45 = bits(_rob_respd_T, 44, 44) node _rob_respd_T_46 = bits(_rob_respd_T, 45, 45) node _rob_respd_T_47 = bits(_rob_respd_T, 46, 46) node _rob_respd_T_48 = bits(_rob_respd_T, 47, 47) node _rob_respd_T_49 = bits(_rob_respd_T, 48, 48) node _rob_respd_T_50 = bits(_rob_respd_T, 49, 49) node _rob_respd_T_51 = bits(_rob_respd_T, 50, 50) node _rob_respd_T_52 = bits(_rob_respd_T, 51, 51) node _rob_respd_T_53 = bits(_rob_respd_T, 52, 52) node _rob_respd_T_54 = bits(_rob_respd_T, 53, 53) node _rob_respd_T_55 = bits(_rob_respd_T, 54, 54) node _rob_respd_T_56 = bits(_rob_respd_T, 55, 55) node _rob_respd_T_57 = bits(_rob_respd_T, 56, 56) node _rob_respd_T_58 = bits(_rob_respd_T, 57, 57) node _rob_respd_T_59 = bits(_rob_respd_T, 58, 58) node _rob_respd_T_60 = bits(_rob_respd_T, 59, 59) node _rob_respd_T_61 = bits(_rob_respd_T, 60, 60) node _rob_respd_T_62 = bits(_rob_respd_T, 61, 61) node _rob_respd_T_63 = bits(_rob_respd_T, 62, 62) node _rob_respd_T_64 = bits(_rob_respd_T, 63, 63) wire _rob_respd_WIRE : UInt<1>[64] connect _rob_respd_WIRE[0], _rob_respd_T_1 connect _rob_respd_WIRE[1], _rob_respd_T_2 connect _rob_respd_WIRE[2], _rob_respd_T_3 connect _rob_respd_WIRE[3], _rob_respd_T_4 connect _rob_respd_WIRE[4], _rob_respd_T_5 connect _rob_respd_WIRE[5], _rob_respd_T_6 connect _rob_respd_WIRE[6], _rob_respd_T_7 connect _rob_respd_WIRE[7], _rob_respd_T_8 connect _rob_respd_WIRE[8], _rob_respd_T_9 connect _rob_respd_WIRE[9], _rob_respd_T_10 connect _rob_respd_WIRE[10], _rob_respd_T_11 connect _rob_respd_WIRE[11], _rob_respd_T_12 connect _rob_respd_WIRE[12], _rob_respd_T_13 connect _rob_respd_WIRE[13], _rob_respd_T_14 connect _rob_respd_WIRE[14], _rob_respd_T_15 connect _rob_respd_WIRE[15], _rob_respd_T_16 connect _rob_respd_WIRE[16], _rob_respd_T_17 connect _rob_respd_WIRE[17], _rob_respd_T_18 connect _rob_respd_WIRE[18], _rob_respd_T_19 connect _rob_respd_WIRE[19], _rob_respd_T_20 connect _rob_respd_WIRE[20], _rob_respd_T_21 connect _rob_respd_WIRE[21], _rob_respd_T_22 connect _rob_respd_WIRE[22], _rob_respd_T_23 connect _rob_respd_WIRE[23], _rob_respd_T_24 connect _rob_respd_WIRE[24], _rob_respd_T_25 connect _rob_respd_WIRE[25], _rob_respd_T_26 connect _rob_respd_WIRE[26], _rob_respd_T_27 connect _rob_respd_WIRE[27], _rob_respd_T_28 connect _rob_respd_WIRE[28], _rob_respd_T_29 connect _rob_respd_WIRE[29], _rob_respd_T_30 connect _rob_respd_WIRE[30], _rob_respd_T_31 connect _rob_respd_WIRE[31], _rob_respd_T_32 connect _rob_respd_WIRE[32], _rob_respd_T_33 connect _rob_respd_WIRE[33], _rob_respd_T_34 connect _rob_respd_WIRE[34], _rob_respd_T_35 connect _rob_respd_WIRE[35], _rob_respd_T_36 connect _rob_respd_WIRE[36], _rob_respd_T_37 connect _rob_respd_WIRE[37], _rob_respd_T_38 connect _rob_respd_WIRE[38], _rob_respd_T_39 connect _rob_respd_WIRE[39], _rob_respd_T_40 connect _rob_respd_WIRE[40], _rob_respd_T_41 connect _rob_respd_WIRE[41], _rob_respd_T_42 connect _rob_respd_WIRE[42], _rob_respd_T_43 connect _rob_respd_WIRE[43], _rob_respd_T_44 connect _rob_respd_WIRE[44], _rob_respd_T_45 connect _rob_respd_WIRE[45], _rob_respd_T_46 connect _rob_respd_WIRE[46], _rob_respd_T_47 connect _rob_respd_WIRE[47], _rob_respd_T_48 connect _rob_respd_WIRE[48], _rob_respd_T_49 connect _rob_respd_WIRE[49], _rob_respd_T_50 connect _rob_respd_WIRE[50], _rob_respd_T_51 connect _rob_respd_WIRE[51], _rob_respd_T_52 connect _rob_respd_WIRE[52], _rob_respd_T_53 connect _rob_respd_WIRE[53], _rob_respd_T_54 connect _rob_respd_WIRE[54], _rob_respd_T_55 connect _rob_respd_WIRE[55], _rob_respd_T_56 connect _rob_respd_WIRE[56], _rob_respd_T_57 connect _rob_respd_WIRE[57], _rob_respd_T_58 connect _rob_respd_WIRE[58], _rob_respd_T_59 connect _rob_respd_WIRE[59], _rob_respd_T_60 connect _rob_respd_WIRE[60], _rob_respd_T_61 connect _rob_respd_WIRE[61], _rob_respd_T_62 connect _rob_respd_WIRE[62], _rob_respd_T_63 connect _rob_respd_WIRE[63], _rob_respd_T_64 regreset rob_respd : UInt<1>[64], clock, reset, _rob_respd_WIRE reg rob_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[64], clock wire _rob_bsy_WIRE : UInt<1>[64] connect _rob_bsy_WIRE[0], UInt<1>(0h0) connect _rob_bsy_WIRE[1], UInt<1>(0h0) connect _rob_bsy_WIRE[2], UInt<1>(0h0) connect _rob_bsy_WIRE[3], UInt<1>(0h0) connect _rob_bsy_WIRE[4], UInt<1>(0h0) connect _rob_bsy_WIRE[5], UInt<1>(0h0) connect _rob_bsy_WIRE[6], UInt<1>(0h0) connect _rob_bsy_WIRE[7], UInt<1>(0h0) connect _rob_bsy_WIRE[8], UInt<1>(0h0) connect _rob_bsy_WIRE[9], UInt<1>(0h0) connect _rob_bsy_WIRE[10], UInt<1>(0h0) connect _rob_bsy_WIRE[11], UInt<1>(0h0) connect _rob_bsy_WIRE[12], UInt<1>(0h0) connect _rob_bsy_WIRE[13], UInt<1>(0h0) connect _rob_bsy_WIRE[14], UInt<1>(0h0) connect _rob_bsy_WIRE[15], UInt<1>(0h0) connect _rob_bsy_WIRE[16], UInt<1>(0h0) connect _rob_bsy_WIRE[17], UInt<1>(0h0) connect _rob_bsy_WIRE[18], UInt<1>(0h0) connect _rob_bsy_WIRE[19], UInt<1>(0h0) connect _rob_bsy_WIRE[20], UInt<1>(0h0) connect _rob_bsy_WIRE[21], UInt<1>(0h0) connect _rob_bsy_WIRE[22], UInt<1>(0h0) connect _rob_bsy_WIRE[23], UInt<1>(0h0) connect _rob_bsy_WIRE[24], UInt<1>(0h0) connect _rob_bsy_WIRE[25], UInt<1>(0h0) connect _rob_bsy_WIRE[26], UInt<1>(0h0) connect _rob_bsy_WIRE[27], UInt<1>(0h0) connect _rob_bsy_WIRE[28], UInt<1>(0h0) connect _rob_bsy_WIRE[29], UInt<1>(0h0) connect _rob_bsy_WIRE[30], UInt<1>(0h0) connect _rob_bsy_WIRE[31], UInt<1>(0h0) connect _rob_bsy_WIRE[32], UInt<1>(0h0) connect _rob_bsy_WIRE[33], UInt<1>(0h0) connect _rob_bsy_WIRE[34], UInt<1>(0h0) connect _rob_bsy_WIRE[35], UInt<1>(0h0) connect _rob_bsy_WIRE[36], UInt<1>(0h0) connect _rob_bsy_WIRE[37], UInt<1>(0h0) connect _rob_bsy_WIRE[38], UInt<1>(0h0) connect _rob_bsy_WIRE[39], UInt<1>(0h0) connect _rob_bsy_WIRE[40], UInt<1>(0h0) connect _rob_bsy_WIRE[41], UInt<1>(0h0) connect _rob_bsy_WIRE[42], UInt<1>(0h0) connect _rob_bsy_WIRE[43], UInt<1>(0h0) connect _rob_bsy_WIRE[44], UInt<1>(0h0) connect _rob_bsy_WIRE[45], UInt<1>(0h0) connect _rob_bsy_WIRE[46], UInt<1>(0h0) connect _rob_bsy_WIRE[47], UInt<1>(0h0) connect _rob_bsy_WIRE[48], UInt<1>(0h0) connect _rob_bsy_WIRE[49], UInt<1>(0h0) connect _rob_bsy_WIRE[50], UInt<1>(0h0) connect _rob_bsy_WIRE[51], UInt<1>(0h0) connect _rob_bsy_WIRE[52], UInt<1>(0h0) connect _rob_bsy_WIRE[53], UInt<1>(0h0) connect _rob_bsy_WIRE[54], UInt<1>(0h0) connect _rob_bsy_WIRE[55], UInt<1>(0h0) connect _rob_bsy_WIRE[56], UInt<1>(0h0) connect _rob_bsy_WIRE[57], UInt<1>(0h0) connect _rob_bsy_WIRE[58], UInt<1>(0h0) connect _rob_bsy_WIRE[59], UInt<1>(0h0) connect _rob_bsy_WIRE[60], UInt<1>(0h0) connect _rob_bsy_WIRE[61], UInt<1>(0h0) connect _rob_bsy_WIRE[62], UInt<1>(0h0) connect _rob_bsy_WIRE[63], UInt<1>(0h0) regreset rob_bsy : UInt<1>[64], clock, reset, _rob_bsy_WIRE regreset rob_head : UInt<6>, clock, reset, UInt<6>(0h0) regreset rob_tail : UInt<6>, clock, reset, UInt<6>(0h0) regreset rob_wait_till_empty : UInt<1>, clock, reset, UInt<1>(0h0) node _ready_for_amo_T = eq(rob_tail, rob_head) node ready_for_amo = and(_ready_for_amo_T, io.lsu.fencei_rdy) when ready_for_amo : connect rob_wait_till_empty, UInt<1>(0h0) node _io_tracegen_req_ready_T = eq(rob_bsy[rob_tail], UInt<1>(0h0)) node _io_tracegen_req_ready_T_1 = eq(rob_wait_till_empty, UInt<1>(0h0)) node _io_tracegen_req_ready_T_2 = and(_io_tracegen_req_ready_T, _io_tracegen_req_ready_T_1) node _io_tracegen_req_ready_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _io_tracegen_req_ready_T_4 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _io_tracegen_req_ready_T_5 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _io_tracegen_req_ready_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _io_tracegen_req_ready_T_7 = or(_io_tracegen_req_ready_T_3, _io_tracegen_req_ready_T_4) node _io_tracegen_req_ready_T_8 = or(_io_tracegen_req_ready_T_7, _io_tracegen_req_ready_T_5) node _io_tracegen_req_ready_T_9 = or(_io_tracegen_req_ready_T_8, _io_tracegen_req_ready_T_6) node _io_tracegen_req_ready_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _io_tracegen_req_ready_T_11 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _io_tracegen_req_ready_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _io_tracegen_req_ready_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _io_tracegen_req_ready_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _io_tracegen_req_ready_T_15 = or(_io_tracegen_req_ready_T_10, _io_tracegen_req_ready_T_11) node _io_tracegen_req_ready_T_16 = or(_io_tracegen_req_ready_T_15, _io_tracegen_req_ready_T_12) node _io_tracegen_req_ready_T_17 = or(_io_tracegen_req_ready_T_16, _io_tracegen_req_ready_T_13) node _io_tracegen_req_ready_T_18 = or(_io_tracegen_req_ready_T_17, _io_tracegen_req_ready_T_14) node _io_tracegen_req_ready_T_19 = or(_io_tracegen_req_ready_T_9, _io_tracegen_req_ready_T_18) node _io_tracegen_req_ready_T_20 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _io_tracegen_req_ready_T_21 = or(_io_tracegen_req_ready_T_19, _io_tracegen_req_ready_T_20) node _io_tracegen_req_ready_T_22 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _io_tracegen_req_ready_T_23 = or(_io_tracegen_req_ready_T_21, _io_tracegen_req_ready_T_22) node _io_tracegen_req_ready_T_24 = eq(_io_tracegen_req_ready_T_23, UInt<1>(0h0)) node _io_tracegen_req_ready_T_25 = or(ready_for_amo, _io_tracegen_req_ready_T_24) node _io_tracegen_req_ready_T_26 = and(_io_tracegen_req_ready_T_2, _io_tracegen_req_ready_T_25) node _io_tracegen_req_ready_T_27 = eq(rob_tail, UInt<6>(0h3f)) node _io_tracegen_req_ready_T_28 = add(rob_tail, UInt<1>(0h1)) node _io_tracegen_req_ready_T_29 = tail(_io_tracegen_req_ready_T_28, 1) node _io_tracegen_req_ready_T_30 = mux(_io_tracegen_req_ready_T_27, UInt<1>(0h0), _io_tracegen_req_ready_T_29) node _io_tracegen_req_ready_T_31 = neq(_io_tracegen_req_ready_T_30, rob_head) node _io_tracegen_req_ready_T_32 = and(_io_tracegen_req_ready_T_26, _io_tracegen_req_ready_T_31) node _io_tracegen_req_ready_T_33 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h0)) node _io_tracegen_req_ready_T_34 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h10)) node _io_tracegen_req_ready_T_35 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _io_tracegen_req_ready_T_36 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _io_tracegen_req_ready_T_37 = or(_io_tracegen_req_ready_T_33, _io_tracegen_req_ready_T_34) node _io_tracegen_req_ready_T_38 = or(_io_tracegen_req_ready_T_37, _io_tracegen_req_ready_T_35) node _io_tracegen_req_ready_T_39 = or(_io_tracegen_req_ready_T_38, _io_tracegen_req_ready_T_36) node _io_tracegen_req_ready_T_40 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _io_tracegen_req_ready_T_41 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _io_tracegen_req_ready_T_42 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _io_tracegen_req_ready_T_43 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _io_tracegen_req_ready_T_44 = or(_io_tracegen_req_ready_T_40, _io_tracegen_req_ready_T_41) node _io_tracegen_req_ready_T_45 = or(_io_tracegen_req_ready_T_44, _io_tracegen_req_ready_T_42) node _io_tracegen_req_ready_T_46 = or(_io_tracegen_req_ready_T_45, _io_tracegen_req_ready_T_43) node _io_tracegen_req_ready_T_47 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _io_tracegen_req_ready_T_48 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _io_tracegen_req_ready_T_49 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _io_tracegen_req_ready_T_50 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _io_tracegen_req_ready_T_51 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _io_tracegen_req_ready_T_52 = or(_io_tracegen_req_ready_T_47, _io_tracegen_req_ready_T_48) node _io_tracegen_req_ready_T_53 = or(_io_tracegen_req_ready_T_52, _io_tracegen_req_ready_T_49) node _io_tracegen_req_ready_T_54 = or(_io_tracegen_req_ready_T_53, _io_tracegen_req_ready_T_50) node _io_tracegen_req_ready_T_55 = or(_io_tracegen_req_ready_T_54, _io_tracegen_req_ready_T_51) node _io_tracegen_req_ready_T_56 = or(_io_tracegen_req_ready_T_46, _io_tracegen_req_ready_T_55) node _io_tracegen_req_ready_T_57 = or(_io_tracegen_req_ready_T_39, _io_tracegen_req_ready_T_56) node _io_tracegen_req_ready_T_58 = and(io.lsu.ldq_full[0], _io_tracegen_req_ready_T_57) node _io_tracegen_req_ready_T_59 = eq(_io_tracegen_req_ready_T_58, UInt<1>(0h0)) node _io_tracegen_req_ready_T_60 = and(_io_tracegen_req_ready_T_32, _io_tracegen_req_ready_T_59) node _io_tracegen_req_ready_T_61 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _io_tracegen_req_ready_T_62 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _io_tracegen_req_ready_T_63 = or(_io_tracegen_req_ready_T_61, _io_tracegen_req_ready_T_62) node _io_tracegen_req_ready_T_64 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _io_tracegen_req_ready_T_65 = or(_io_tracegen_req_ready_T_63, _io_tracegen_req_ready_T_64) node _io_tracegen_req_ready_T_66 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _io_tracegen_req_ready_T_67 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _io_tracegen_req_ready_T_68 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _io_tracegen_req_ready_T_69 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _io_tracegen_req_ready_T_70 = or(_io_tracegen_req_ready_T_66, _io_tracegen_req_ready_T_67) node _io_tracegen_req_ready_T_71 = or(_io_tracegen_req_ready_T_70, _io_tracegen_req_ready_T_68) node _io_tracegen_req_ready_T_72 = or(_io_tracegen_req_ready_T_71, _io_tracegen_req_ready_T_69) node _io_tracegen_req_ready_T_73 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _io_tracegen_req_ready_T_74 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _io_tracegen_req_ready_T_75 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _io_tracegen_req_ready_T_76 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _io_tracegen_req_ready_T_77 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _io_tracegen_req_ready_T_78 = or(_io_tracegen_req_ready_T_73, _io_tracegen_req_ready_T_74) node _io_tracegen_req_ready_T_79 = or(_io_tracegen_req_ready_T_78, _io_tracegen_req_ready_T_75) node _io_tracegen_req_ready_T_80 = or(_io_tracegen_req_ready_T_79, _io_tracegen_req_ready_T_76) node _io_tracegen_req_ready_T_81 = or(_io_tracegen_req_ready_T_80, _io_tracegen_req_ready_T_77) node _io_tracegen_req_ready_T_82 = or(_io_tracegen_req_ready_T_72, _io_tracegen_req_ready_T_81) node _io_tracegen_req_ready_T_83 = or(_io_tracegen_req_ready_T_65, _io_tracegen_req_ready_T_82) node _io_tracegen_req_ready_T_84 = and(io.lsu.stq_full[0], _io_tracegen_req_ready_T_83) node _io_tracegen_req_ready_T_85 = eq(_io_tracegen_req_ready_T_84, UInt<1>(0h0)) node _io_tracegen_req_ready_T_86 = and(_io_tracegen_req_ready_T_60, _io_tracegen_req_ready_T_85) connect io.tracegen.req.ready, _io_tracegen_req_ready_T_86 wire _tracegen_uop_WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect _tracegen_uop_WIRE.debug_tsrc, UInt<2>(0h0) connect _tracegen_uop_WIRE.debug_fsrc, UInt<2>(0h0) connect _tracegen_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.fp_single, UInt<1>(0h0) connect _tracegen_uop_WIRE.fp_val, UInt<1>(0h0) connect _tracegen_uop_WIRE.frs3_en, UInt<1>(0h0) connect _tracegen_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _tracegen_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _tracegen_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _tracegen_uop_WIRE.ldst_val, UInt<1>(0h0) connect _tracegen_uop_WIRE.lrs3, UInt<6>(0h0) connect _tracegen_uop_WIRE.lrs2, UInt<6>(0h0) connect _tracegen_uop_WIRE.lrs1, UInt<6>(0h0) connect _tracegen_uop_WIRE.ldst, UInt<6>(0h0) connect _tracegen_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _tracegen_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_unique, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _tracegen_uop_WIRE.uses_stq, UInt<1>(0h0) connect _tracegen_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_amo, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_fencei, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_fence, UInt<1>(0h0) connect _tracegen_uop_WIRE.mem_signed, UInt<1>(0h0) connect _tracegen_uop_WIRE.mem_size, UInt<2>(0h0) connect _tracegen_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _tracegen_uop_WIRE.bypassable, UInt<1>(0h0) connect _tracegen_uop_WIRE.exc_cause, UInt<64>(0h0) connect _tracegen_uop_WIRE.exception, UInt<1>(0h0) connect _tracegen_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _tracegen_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.ppred, UInt<4>(0h0) connect _tracegen_uop_WIRE.prs3, UInt<7>(0h0) connect _tracegen_uop_WIRE.prs2, UInt<7>(0h0) connect _tracegen_uop_WIRE.prs1, UInt<7>(0h0) connect _tracegen_uop_WIRE.pdst, UInt<7>(0h0) connect _tracegen_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _tracegen_uop_WIRE.stq_idx, UInt<4>(0h0) connect _tracegen_uop_WIRE.ldq_idx, UInt<4>(0h0) connect _tracegen_uop_WIRE.rob_idx, UInt<6>(0h0) connect _tracegen_uop_WIRE.csr_addr, UInt<12>(0h0) connect _tracegen_uop_WIRE.imm_packed, UInt<20>(0h0) connect _tracegen_uop_WIRE.taken, UInt<1>(0h0) connect _tracegen_uop_WIRE.pc_lob, UInt<6>(0h0) connect _tracegen_uop_WIRE.edge_inst, UInt<1>(0h0) connect _tracegen_uop_WIRE.ftq_idx, UInt<4>(0h0) connect _tracegen_uop_WIRE.br_tag, UInt<2>(0h0) connect _tracegen_uop_WIRE.br_mask, UInt<4>(0h0) connect _tracegen_uop_WIRE.is_sfb, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_jal, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_jalr, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_br, UInt<1>(0h0) connect _tracegen_uop_WIRE.iw_p2_poisoned, UInt<1>(0h0) connect _tracegen_uop_WIRE.iw_p1_poisoned, UInt<1>(0h0) connect _tracegen_uop_WIRE.iw_state, UInt<2>(0h0) connect _tracegen_uop_WIRE.ctrl.is_std, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.is_sta, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.is_load, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.csr_cmd, UInt<3>(0h0) connect _tracegen_uop_WIRE.ctrl.fcn_dw, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.op_fcn, UInt<5>(0h0) connect _tracegen_uop_WIRE.ctrl.imm_sel, UInt<3>(0h0) connect _tracegen_uop_WIRE.ctrl.op2_sel, UInt<3>(0h0) connect _tracegen_uop_WIRE.ctrl.op1_sel, UInt<2>(0h0) connect _tracegen_uop_WIRE.ctrl.br_type, UInt<4>(0h0) connect _tracegen_uop_WIRE.fu_code, UInt<10>(0h0) connect _tracegen_uop_WIRE.iq_type, UInt<3>(0h0) connect _tracegen_uop_WIRE.debug_pc, UInt<34>(0h0) connect _tracegen_uop_WIRE.is_rvc, UInt<1>(0h0) connect _tracegen_uop_WIRE.debug_inst, UInt<32>(0h0) connect _tracegen_uop_WIRE.inst, UInt<32>(0h0) connect _tracegen_uop_WIRE.uopc, UInt<7>(0h0) wire tracegen_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect tracegen_uop, _tracegen_uop_WIRE node _tracegen_uop_uses_ldq_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h0)) node _tracegen_uop_uses_ldq_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h10)) node _tracegen_uop_uses_ldq_T_2 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _tracegen_uop_uses_ldq_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_uses_ldq_T_4 = or(_tracegen_uop_uses_ldq_T, _tracegen_uop_uses_ldq_T_1) node _tracegen_uop_uses_ldq_T_5 = or(_tracegen_uop_uses_ldq_T_4, _tracegen_uop_uses_ldq_T_2) node _tracegen_uop_uses_ldq_T_6 = or(_tracegen_uop_uses_ldq_T_5, _tracegen_uop_uses_ldq_T_3) node _tracegen_uop_uses_ldq_T_7 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_uses_ldq_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_uses_ldq_T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_uses_ldq_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_uses_ldq_T_11 = or(_tracegen_uop_uses_ldq_T_7, _tracegen_uop_uses_ldq_T_8) node _tracegen_uop_uses_ldq_T_12 = or(_tracegen_uop_uses_ldq_T_11, _tracegen_uop_uses_ldq_T_9) node _tracegen_uop_uses_ldq_T_13 = or(_tracegen_uop_uses_ldq_T_12, _tracegen_uop_uses_ldq_T_10) node _tracegen_uop_uses_ldq_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_uses_ldq_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_uses_ldq_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_uses_ldq_T_17 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_uses_ldq_T_18 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_uses_ldq_T_19 = or(_tracegen_uop_uses_ldq_T_14, _tracegen_uop_uses_ldq_T_15) node _tracegen_uop_uses_ldq_T_20 = or(_tracegen_uop_uses_ldq_T_19, _tracegen_uop_uses_ldq_T_16) node _tracegen_uop_uses_ldq_T_21 = or(_tracegen_uop_uses_ldq_T_20, _tracegen_uop_uses_ldq_T_17) node _tracegen_uop_uses_ldq_T_22 = or(_tracegen_uop_uses_ldq_T_21, _tracegen_uop_uses_ldq_T_18) node _tracegen_uop_uses_ldq_T_23 = or(_tracegen_uop_uses_ldq_T_13, _tracegen_uop_uses_ldq_T_22) node _tracegen_uop_uses_ldq_T_24 = or(_tracegen_uop_uses_ldq_T_6, _tracegen_uop_uses_ldq_T_23) node _tracegen_uop_uses_ldq_T_25 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_uses_ldq_T_26 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_uses_ldq_T_27 = or(_tracegen_uop_uses_ldq_T_25, _tracegen_uop_uses_ldq_T_26) node _tracegen_uop_uses_ldq_T_28 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_uses_ldq_T_29 = or(_tracegen_uop_uses_ldq_T_27, _tracegen_uop_uses_ldq_T_28) node _tracegen_uop_uses_ldq_T_30 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_uses_ldq_T_31 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_uses_ldq_T_32 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_uses_ldq_T_33 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_uses_ldq_T_34 = or(_tracegen_uop_uses_ldq_T_30, _tracegen_uop_uses_ldq_T_31) node _tracegen_uop_uses_ldq_T_35 = or(_tracegen_uop_uses_ldq_T_34, _tracegen_uop_uses_ldq_T_32) node _tracegen_uop_uses_ldq_T_36 = or(_tracegen_uop_uses_ldq_T_35, _tracegen_uop_uses_ldq_T_33) node _tracegen_uop_uses_ldq_T_37 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_uses_ldq_T_38 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_uses_ldq_T_39 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_uses_ldq_T_40 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_uses_ldq_T_41 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_uses_ldq_T_42 = or(_tracegen_uop_uses_ldq_T_37, _tracegen_uop_uses_ldq_T_38) node _tracegen_uop_uses_ldq_T_43 = or(_tracegen_uop_uses_ldq_T_42, _tracegen_uop_uses_ldq_T_39) node _tracegen_uop_uses_ldq_T_44 = or(_tracegen_uop_uses_ldq_T_43, _tracegen_uop_uses_ldq_T_40) node _tracegen_uop_uses_ldq_T_45 = or(_tracegen_uop_uses_ldq_T_44, _tracegen_uop_uses_ldq_T_41) node _tracegen_uop_uses_ldq_T_46 = or(_tracegen_uop_uses_ldq_T_36, _tracegen_uop_uses_ldq_T_45) node _tracegen_uop_uses_ldq_T_47 = or(_tracegen_uop_uses_ldq_T_29, _tracegen_uop_uses_ldq_T_46) node _tracegen_uop_uses_ldq_T_48 = eq(_tracegen_uop_uses_ldq_T_47, UInt<1>(0h0)) node _tracegen_uop_uses_ldq_T_49 = and(_tracegen_uop_uses_ldq_T_24, _tracegen_uop_uses_ldq_T_48) connect tracegen_uop.uses_ldq, _tracegen_uop_uses_ldq_T_49 node _tracegen_uop_uses_stq_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_uses_stq_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_uses_stq_T_2 = or(_tracegen_uop_uses_stq_T, _tracegen_uop_uses_stq_T_1) node _tracegen_uop_uses_stq_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_uses_stq_T_4 = or(_tracegen_uop_uses_stq_T_2, _tracegen_uop_uses_stq_T_3) node _tracegen_uop_uses_stq_T_5 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_uses_stq_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_uses_stq_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_uses_stq_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_uses_stq_T_9 = or(_tracegen_uop_uses_stq_T_5, _tracegen_uop_uses_stq_T_6) node _tracegen_uop_uses_stq_T_10 = or(_tracegen_uop_uses_stq_T_9, _tracegen_uop_uses_stq_T_7) node _tracegen_uop_uses_stq_T_11 = or(_tracegen_uop_uses_stq_T_10, _tracegen_uop_uses_stq_T_8) node _tracegen_uop_uses_stq_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_uses_stq_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_uses_stq_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_uses_stq_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_uses_stq_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_uses_stq_T_17 = or(_tracegen_uop_uses_stq_T_12, _tracegen_uop_uses_stq_T_13) node _tracegen_uop_uses_stq_T_18 = or(_tracegen_uop_uses_stq_T_17, _tracegen_uop_uses_stq_T_14) node _tracegen_uop_uses_stq_T_19 = or(_tracegen_uop_uses_stq_T_18, _tracegen_uop_uses_stq_T_15) node _tracegen_uop_uses_stq_T_20 = or(_tracegen_uop_uses_stq_T_19, _tracegen_uop_uses_stq_T_16) node _tracegen_uop_uses_stq_T_21 = or(_tracegen_uop_uses_stq_T_11, _tracegen_uop_uses_stq_T_20) node _tracegen_uop_uses_stq_T_22 = or(_tracegen_uop_uses_stq_T_4, _tracegen_uop_uses_stq_T_21) connect tracegen_uop.uses_stq, _tracegen_uop_uses_stq_T_22 connect tracegen_uop.rob_idx, rob_tail connect tracegen_uop.uopc, io.tracegen.req.bits.tag connect tracegen_uop.mem_size, io.tracegen.req.bits.size connect tracegen_uop.mem_cmd, io.tracegen.req.bits.cmd connect tracegen_uop.mem_signed, io.tracegen.req.bits.signed connect tracegen_uop.ldq_idx, io.lsu.dis_ldq_idx[0] connect tracegen_uop.stq_idx, io.lsu.dis_stq_idx[0] node _tracegen_uop_is_amo_T = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_is_amo_T_1 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_is_amo_T_2 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_is_amo_T_3 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_is_amo_T_4 = or(_tracegen_uop_is_amo_T, _tracegen_uop_is_amo_T_1) node _tracegen_uop_is_amo_T_5 = or(_tracegen_uop_is_amo_T_4, _tracegen_uop_is_amo_T_2) node _tracegen_uop_is_amo_T_6 = or(_tracegen_uop_is_amo_T_5, _tracegen_uop_is_amo_T_3) node _tracegen_uop_is_amo_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_is_amo_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_is_amo_T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_is_amo_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_is_amo_T_11 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_is_amo_T_12 = or(_tracegen_uop_is_amo_T_7, _tracegen_uop_is_amo_T_8) node _tracegen_uop_is_amo_T_13 = or(_tracegen_uop_is_amo_T_12, _tracegen_uop_is_amo_T_9) node _tracegen_uop_is_amo_T_14 = or(_tracegen_uop_is_amo_T_13, _tracegen_uop_is_amo_T_10) node _tracegen_uop_is_amo_T_15 = or(_tracegen_uop_is_amo_T_14, _tracegen_uop_is_amo_T_11) node _tracegen_uop_is_amo_T_16 = or(_tracegen_uop_is_amo_T_6, _tracegen_uop_is_amo_T_15) node _tracegen_uop_is_amo_T_17 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_is_amo_T_18 = or(_tracegen_uop_is_amo_T_16, _tracegen_uop_is_amo_T_17) connect tracegen_uop.is_amo, _tracegen_uop_is_amo_T_18 node _tracegen_uop_ctrl_is_load_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h0)) node _tracegen_uop_ctrl_is_load_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h10)) node _tracegen_uop_ctrl_is_load_T_2 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _tracegen_uop_ctrl_is_load_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_load_T_4 = or(_tracegen_uop_ctrl_is_load_T, _tracegen_uop_ctrl_is_load_T_1) node _tracegen_uop_ctrl_is_load_T_5 = or(_tracegen_uop_ctrl_is_load_T_4, _tracegen_uop_ctrl_is_load_T_2) node _tracegen_uop_ctrl_is_load_T_6 = or(_tracegen_uop_ctrl_is_load_T_5, _tracegen_uop_ctrl_is_load_T_3) node _tracegen_uop_ctrl_is_load_T_7 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_load_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_load_T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_load_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_load_T_11 = or(_tracegen_uop_ctrl_is_load_T_7, _tracegen_uop_ctrl_is_load_T_8) node _tracegen_uop_ctrl_is_load_T_12 = or(_tracegen_uop_ctrl_is_load_T_11, _tracegen_uop_ctrl_is_load_T_9) node _tracegen_uop_ctrl_is_load_T_13 = or(_tracegen_uop_ctrl_is_load_T_12, _tracegen_uop_ctrl_is_load_T_10) node _tracegen_uop_ctrl_is_load_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_load_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_load_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_load_T_17 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_load_T_18 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_load_T_19 = or(_tracegen_uop_ctrl_is_load_T_14, _tracegen_uop_ctrl_is_load_T_15) node _tracegen_uop_ctrl_is_load_T_20 = or(_tracegen_uop_ctrl_is_load_T_19, _tracegen_uop_ctrl_is_load_T_16) node _tracegen_uop_ctrl_is_load_T_21 = or(_tracegen_uop_ctrl_is_load_T_20, _tracegen_uop_ctrl_is_load_T_17) node _tracegen_uop_ctrl_is_load_T_22 = or(_tracegen_uop_ctrl_is_load_T_21, _tracegen_uop_ctrl_is_load_T_18) node _tracegen_uop_ctrl_is_load_T_23 = or(_tracegen_uop_ctrl_is_load_T_13, _tracegen_uop_ctrl_is_load_T_22) node _tracegen_uop_ctrl_is_load_T_24 = or(_tracegen_uop_ctrl_is_load_T_6, _tracegen_uop_ctrl_is_load_T_23) node _tracegen_uop_ctrl_is_load_T_25 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_ctrl_is_load_T_26 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_ctrl_is_load_T_27 = or(_tracegen_uop_ctrl_is_load_T_25, _tracegen_uop_ctrl_is_load_T_26) node _tracegen_uop_ctrl_is_load_T_28 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_load_T_29 = or(_tracegen_uop_ctrl_is_load_T_27, _tracegen_uop_ctrl_is_load_T_28) node _tracegen_uop_ctrl_is_load_T_30 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_load_T_31 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_load_T_32 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_load_T_33 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_load_T_34 = or(_tracegen_uop_ctrl_is_load_T_30, _tracegen_uop_ctrl_is_load_T_31) node _tracegen_uop_ctrl_is_load_T_35 = or(_tracegen_uop_ctrl_is_load_T_34, _tracegen_uop_ctrl_is_load_T_32) node _tracegen_uop_ctrl_is_load_T_36 = or(_tracegen_uop_ctrl_is_load_T_35, _tracegen_uop_ctrl_is_load_T_33) node _tracegen_uop_ctrl_is_load_T_37 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_load_T_38 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_load_T_39 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_load_T_40 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_load_T_41 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_load_T_42 = or(_tracegen_uop_ctrl_is_load_T_37, _tracegen_uop_ctrl_is_load_T_38) node _tracegen_uop_ctrl_is_load_T_43 = or(_tracegen_uop_ctrl_is_load_T_42, _tracegen_uop_ctrl_is_load_T_39) node _tracegen_uop_ctrl_is_load_T_44 = or(_tracegen_uop_ctrl_is_load_T_43, _tracegen_uop_ctrl_is_load_T_40) node _tracegen_uop_ctrl_is_load_T_45 = or(_tracegen_uop_ctrl_is_load_T_44, _tracegen_uop_ctrl_is_load_T_41) node _tracegen_uop_ctrl_is_load_T_46 = or(_tracegen_uop_ctrl_is_load_T_36, _tracegen_uop_ctrl_is_load_T_45) node _tracegen_uop_ctrl_is_load_T_47 = or(_tracegen_uop_ctrl_is_load_T_29, _tracegen_uop_ctrl_is_load_T_46) node _tracegen_uop_ctrl_is_load_T_48 = eq(_tracegen_uop_ctrl_is_load_T_47, UInt<1>(0h0)) node _tracegen_uop_ctrl_is_load_T_49 = and(_tracegen_uop_ctrl_is_load_T_24, _tracegen_uop_ctrl_is_load_T_48) connect tracegen_uop.ctrl.is_load, _tracegen_uop_ctrl_is_load_T_49 node _tracegen_uop_ctrl_is_sta_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_ctrl_is_sta_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_ctrl_is_sta_T_2 = or(_tracegen_uop_ctrl_is_sta_T, _tracegen_uop_ctrl_is_sta_T_1) node _tracegen_uop_ctrl_is_sta_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_sta_T_4 = or(_tracegen_uop_ctrl_is_sta_T_2, _tracegen_uop_ctrl_is_sta_T_3) node _tracegen_uop_ctrl_is_sta_T_5 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_sta_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_sta_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_sta_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_sta_T_9 = or(_tracegen_uop_ctrl_is_sta_T_5, _tracegen_uop_ctrl_is_sta_T_6) node _tracegen_uop_ctrl_is_sta_T_10 = or(_tracegen_uop_ctrl_is_sta_T_9, _tracegen_uop_ctrl_is_sta_T_7) node _tracegen_uop_ctrl_is_sta_T_11 = or(_tracegen_uop_ctrl_is_sta_T_10, _tracegen_uop_ctrl_is_sta_T_8) node _tracegen_uop_ctrl_is_sta_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_sta_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_sta_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_sta_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_sta_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_sta_T_17 = or(_tracegen_uop_ctrl_is_sta_T_12, _tracegen_uop_ctrl_is_sta_T_13) node _tracegen_uop_ctrl_is_sta_T_18 = or(_tracegen_uop_ctrl_is_sta_T_17, _tracegen_uop_ctrl_is_sta_T_14) node _tracegen_uop_ctrl_is_sta_T_19 = or(_tracegen_uop_ctrl_is_sta_T_18, _tracegen_uop_ctrl_is_sta_T_15) node _tracegen_uop_ctrl_is_sta_T_20 = or(_tracegen_uop_ctrl_is_sta_T_19, _tracegen_uop_ctrl_is_sta_T_16) node _tracegen_uop_ctrl_is_sta_T_21 = or(_tracegen_uop_ctrl_is_sta_T_11, _tracegen_uop_ctrl_is_sta_T_20) node _tracegen_uop_ctrl_is_sta_T_22 = or(_tracegen_uop_ctrl_is_sta_T_4, _tracegen_uop_ctrl_is_sta_T_21) connect tracegen_uop.ctrl.is_sta, _tracegen_uop_ctrl_is_sta_T_22 node _tracegen_uop_ctrl_is_std_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_ctrl_is_std_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_ctrl_is_std_T_2 = or(_tracegen_uop_ctrl_is_std_T, _tracegen_uop_ctrl_is_std_T_1) node _tracegen_uop_ctrl_is_std_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_std_T_4 = or(_tracegen_uop_ctrl_is_std_T_2, _tracegen_uop_ctrl_is_std_T_3) node _tracegen_uop_ctrl_is_std_T_5 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_std_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_std_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_std_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_std_T_9 = or(_tracegen_uop_ctrl_is_std_T_5, _tracegen_uop_ctrl_is_std_T_6) node _tracegen_uop_ctrl_is_std_T_10 = or(_tracegen_uop_ctrl_is_std_T_9, _tracegen_uop_ctrl_is_std_T_7) node _tracegen_uop_ctrl_is_std_T_11 = or(_tracegen_uop_ctrl_is_std_T_10, _tracegen_uop_ctrl_is_std_T_8) node _tracegen_uop_ctrl_is_std_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_std_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_std_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_std_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_std_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_std_T_17 = or(_tracegen_uop_ctrl_is_std_T_12, _tracegen_uop_ctrl_is_std_T_13) node _tracegen_uop_ctrl_is_std_T_18 = or(_tracegen_uop_ctrl_is_std_T_17, _tracegen_uop_ctrl_is_std_T_14) node _tracegen_uop_ctrl_is_std_T_19 = or(_tracegen_uop_ctrl_is_std_T_18, _tracegen_uop_ctrl_is_std_T_15) node _tracegen_uop_ctrl_is_std_T_20 = or(_tracegen_uop_ctrl_is_std_T_19, _tracegen_uop_ctrl_is_std_T_16) node _tracegen_uop_ctrl_is_std_T_21 = or(_tracegen_uop_ctrl_is_std_T_11, _tracegen_uop_ctrl_is_std_T_20) node _tracegen_uop_ctrl_is_std_T_22 = or(_tracegen_uop_ctrl_is_std_T_4, _tracegen_uop_ctrl_is_std_T_21) connect tracegen_uop.ctrl.is_std, _tracegen_uop_ctrl_is_std_T_22 node _io_lsu_dis_uops_0_valid_T = and(io.tracegen.req.ready, io.tracegen.req.valid) connect io.lsu.dis_uops[0].valid, _io_lsu_dis_uops_0_valid_T connect io.lsu.dis_uops[0].bits, tracegen_uop node _T = and(io.tracegen.req.ready, io.tracegen.req.valid) when _T : node _rob_tail_T = eq(rob_tail, UInt<6>(0h3f)) node _rob_tail_T_1 = add(rob_tail, UInt<1>(0h1)) node _rob_tail_T_2 = tail(_rob_tail_T_1, 1) node _rob_tail_T_3 = mux(_rob_tail_T, UInt<1>(0h0), _rob_tail_T_2) connect rob_tail, _rob_tail_T_3 connect rob_bsy[rob_tail], UInt<1>(0h1) connect rob_uop[rob_tail], tracegen_uop connect rob_respd[rob_tail], UInt<1>(0h0) connect rob[rob_tail], io.tracegen.req.bits node _T_1 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _T_2 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _T_3 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _T_4 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _T_5 = or(_T_1, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = or(_T_6, _T_4) node _T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _T_11 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _T_13 = or(_T_8, _T_9) node _T_14 = or(_T_13, _T_10) node _T_15 = or(_T_14, _T_11) node _T_16 = or(_T_15, _T_12) node _T_17 = or(_T_7, _T_16) node _T_18 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _T_19 = or(_T_17, _T_18) node _T_20 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _T_21 = or(_T_19, _T_20) when _T_21 : connect rob_wait_till_empty, UInt<1>(0h1) connect io.lsu.fp_stdata.valid, UInt<1>(0h0) invalidate io.lsu.fp_stdata.bits.fflags.bits.flags invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exception invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.taken invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uopc invalidate io.lsu.fp_stdata.bits.fflags.valid invalidate io.lsu.fp_stdata.bits.predicated invalidate io.lsu.fp_stdata.bits.data invalidate io.lsu.fp_stdata.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.uop.exception invalidate io.lsu.fp_stdata.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.uop.taken invalidate io.lsu.fp_stdata.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.uop.inst invalidate io.lsu.fp_stdata.bits.uop.uopc node _io_lsu_commit_valids_0_T = eq(rob_bsy[rob_head], UInt<1>(0h0)) node _io_lsu_commit_valids_0_T_1 = neq(rob_head, rob_tail) node _io_lsu_commit_valids_0_T_2 = and(_io_lsu_commit_valids_0_T, _io_lsu_commit_valids_0_T_1) node _io_lsu_commit_valids_0_T_3 = and(_io_lsu_commit_valids_0_T_2, rob_respd[rob_head]) connect io.lsu.commit.valids[0], _io_lsu_commit_valids_0_T_3 connect io.lsu.commit.uops[0], rob_uop[rob_head] connect io.lsu.commit.rbk_valids[0], UInt<1>(0h0) connect io.lsu.commit.rollback, UInt<1>(0h0) invalidate io.lsu.commit.fflags.bits invalidate io.lsu.commit.fflags.valid when io.lsu.commit.valids[0] : node _rob_head_T = eq(rob_head, UInt<6>(0h3f)) node _rob_head_T_1 = add(rob_head, UInt<1>(0h1)) node _rob_head_T_2 = tail(_rob_head_T_1, 1) node _rob_head_T_3 = mux(_rob_head_T, UInt<1>(0h0), _rob_head_T_2) connect rob_head, _rob_head_T_3 when io.lsu.clr_bsy[0].valid : connect rob_bsy[io.lsu.clr_bsy[0].bits], UInt<1>(0h0) node _T_22 = neq(rob[io.lsu.clr_unsafe[0].bits].cmd, UInt<3>(0h6)) node _T_23 = and(io.lsu.clr_unsafe[0].valid, _T_22) when _T_23 : connect rob_bsy[io.lsu.clr_unsafe[0].bits], UInt<1>(0h0) when io.lsu.exe[0].iresp.valid : connect rob_bsy[io.lsu.exe[0].iresp.bits.uop.rob_idx], UInt<1>(0h0) node _T_24 = eq(io.lsu.lxcpt.valid, UInt<1>(0h0)) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at tracegen.scala:115 assert(!io.lsu.lxcpt.valid)\n") : printf assert(clock, _T_24, UInt<1>(0h1), "") : assert node _io_lsu_exe_0_req_valid_T = and(io.tracegen.req.ready, io.tracegen.req.valid) reg io_lsu_exe_0_req_valid_REG : UInt<1>, clock connect io_lsu_exe_0_req_valid_REG, _io_lsu_exe_0_req_valid_T connect io.lsu.exe[0].req.valid, io_lsu_exe_0_req_valid_REG invalidate io.lsu.exe[0].req.bits.sfence.bits.hg invalidate io.lsu.exe[0].req.bits.sfence.bits.hv invalidate io.lsu.exe[0].req.bits.sfence.bits.asid invalidate io.lsu.exe[0].req.bits.sfence.bits.addr invalidate io.lsu.exe[0].req.bits.sfence.bits.rs2 invalidate io.lsu.exe[0].req.bits.sfence.bits.rs1 invalidate io.lsu.exe[0].req.bits.sfence.valid invalidate io.lsu.exe[0].req.bits.mxcpt.bits invalidate io.lsu.exe[0].req.bits.mxcpt.valid invalidate io.lsu.exe[0].req.bits.addr invalidate io.lsu.exe[0].req.bits.fflags.bits.flags invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].req.bits.fflags.valid invalidate io.lsu.exe[0].req.bits.data invalidate io.lsu.exe[0].req.bits.predicated invalidate io.lsu.exe[0].req.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.uop.exception invalidate io.lsu.exe[0].req.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.uop.taken invalidate io.lsu.exe[0].req.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.uop.inst invalidate io.lsu.exe[0].req.bits.uop.uopc reg io_lsu_exe_0_req_bits_uop_REG : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock connect io_lsu_exe_0_req_bits_uop_REG, tracegen_uop connect io.lsu.exe[0].req.bits.uop, io_lsu_exe_0_req_bits_uop_REG reg io_lsu_exe_0_req_bits_addr_REG : UInt, clock connect io_lsu_exe_0_req_bits_addr_REG, io.tracegen.req.bits.addr connect io.lsu.exe[0].req.bits.addr, io_lsu_exe_0_req_bits_addr_REG reg io_lsu_exe_0_req_bits_data_REG : UInt, clock connect io_lsu_exe_0_req_bits_data_REG, io.tracegen.req.bits.data connect io.lsu.exe[0].req.bits.data, io_lsu_exe_0_req_bits_data_REG connect io.tracegen.resp.valid, io.lsu.exe[0].iresp.valid invalidate io.tracegen.resp.bits.store_data invalidate io.tracegen.resp.bits.data_raw invalidate io.tracegen.resp.bits.data_word_bypass invalidate io.tracegen.resp.bits.has_data invalidate io.tracegen.resp.bits.replay invalidate io.tracegen.resp.bits.mask invalidate io.tracegen.resp.bits.data invalidate io.tracegen.resp.bits.dv invalidate io.tracegen.resp.bits.dprv invalidate io.tracegen.resp.bits.signed invalidate io.tracegen.resp.bits.size invalidate io.tracegen.resp.bits.cmd invalidate io.tracegen.resp.bits.tag invalidate io.tracegen.resp.bits.addr connect io.tracegen.resp.bits.tag, io.lsu.exe[0].iresp.bits.uop.uopc connect io.tracegen.resp.bits.size, io.lsu.exe[0].iresp.bits.uop.mem_size connect io.tracegen.resp.bits.data, io.lsu.exe[0].iresp.bits.data node _store_resp_idx_T = eq(rob_respd[0], UInt<1>(0h0)) node _store_resp_idx_T_1 = eq(rob[0].cmd, UInt<1>(0h1)) node _store_resp_idx_T_2 = eq(rob[0].cmd, UInt<5>(0h11)) node _store_resp_idx_T_3 = or(_store_resp_idx_T_1, _store_resp_idx_T_2) node _store_resp_idx_T_4 = eq(rob[0].cmd, UInt<3>(0h7)) node _store_resp_idx_T_5 = or(_store_resp_idx_T_3, _store_resp_idx_T_4) node _store_resp_idx_T_6 = eq(rob[0].cmd, UInt<3>(0h4)) node _store_resp_idx_T_7 = eq(rob[0].cmd, UInt<4>(0h9)) node _store_resp_idx_T_8 = eq(rob[0].cmd, UInt<4>(0ha)) node _store_resp_idx_T_9 = eq(rob[0].cmd, UInt<4>(0hb)) node _store_resp_idx_T_10 = or(_store_resp_idx_T_6, _store_resp_idx_T_7) node _store_resp_idx_T_11 = or(_store_resp_idx_T_10, _store_resp_idx_T_8) node _store_resp_idx_T_12 = or(_store_resp_idx_T_11, _store_resp_idx_T_9) node _store_resp_idx_T_13 = eq(rob[0].cmd, UInt<4>(0h8)) node _store_resp_idx_T_14 = eq(rob[0].cmd, UInt<4>(0hc)) node _store_resp_idx_T_15 = eq(rob[0].cmd, UInt<4>(0hd)) node _store_resp_idx_T_16 = eq(rob[0].cmd, UInt<4>(0he)) node _store_resp_idx_T_17 = eq(rob[0].cmd, UInt<4>(0hf)) node _store_resp_idx_T_18 = or(_store_resp_idx_T_13, _store_resp_idx_T_14) node _store_resp_idx_T_19 = or(_store_resp_idx_T_18, _store_resp_idx_T_15) node _store_resp_idx_T_20 = or(_store_resp_idx_T_19, _store_resp_idx_T_16) node _store_resp_idx_T_21 = or(_store_resp_idx_T_20, _store_resp_idx_T_17) node _store_resp_idx_T_22 = or(_store_resp_idx_T_12, _store_resp_idx_T_21) node _store_resp_idx_T_23 = or(_store_resp_idx_T_5, _store_resp_idx_T_22) node _store_resp_idx_T_24 = and(_store_resp_idx_T, _store_resp_idx_T_23) node _store_resp_idx_T_25 = eq(rob_respd[1], UInt<1>(0h0)) node _store_resp_idx_T_26 = eq(rob[1].cmd, UInt<1>(0h1)) node _store_resp_idx_T_27 = eq(rob[1].cmd, UInt<5>(0h11)) node _store_resp_idx_T_28 = or(_store_resp_idx_T_26, _store_resp_idx_T_27) node _store_resp_idx_T_29 = eq(rob[1].cmd, UInt<3>(0h7)) node _store_resp_idx_T_30 = or(_store_resp_idx_T_28, _store_resp_idx_T_29) node _store_resp_idx_T_31 = eq(rob[1].cmd, UInt<3>(0h4)) node _store_resp_idx_T_32 = eq(rob[1].cmd, UInt<4>(0h9)) node _store_resp_idx_T_33 = eq(rob[1].cmd, UInt<4>(0ha)) node _store_resp_idx_T_34 = eq(rob[1].cmd, UInt<4>(0hb)) node _store_resp_idx_T_35 = or(_store_resp_idx_T_31, _store_resp_idx_T_32) node _store_resp_idx_T_36 = or(_store_resp_idx_T_35, _store_resp_idx_T_33) node _store_resp_idx_T_37 = or(_store_resp_idx_T_36, _store_resp_idx_T_34) node _store_resp_idx_T_38 = eq(rob[1].cmd, UInt<4>(0h8)) node _store_resp_idx_T_39 = eq(rob[1].cmd, UInt<4>(0hc)) node _store_resp_idx_T_40 = eq(rob[1].cmd, UInt<4>(0hd)) node _store_resp_idx_T_41 = eq(rob[1].cmd, UInt<4>(0he)) node _store_resp_idx_T_42 = eq(rob[1].cmd, UInt<4>(0hf)) node _store_resp_idx_T_43 = or(_store_resp_idx_T_38, _store_resp_idx_T_39) node _store_resp_idx_T_44 = or(_store_resp_idx_T_43, _store_resp_idx_T_40) node _store_resp_idx_T_45 = or(_store_resp_idx_T_44, _store_resp_idx_T_41) node _store_resp_idx_T_46 = or(_store_resp_idx_T_45, _store_resp_idx_T_42) node _store_resp_idx_T_47 = or(_store_resp_idx_T_37, _store_resp_idx_T_46) node _store_resp_idx_T_48 = or(_store_resp_idx_T_30, _store_resp_idx_T_47) node _store_resp_idx_T_49 = and(_store_resp_idx_T_25, _store_resp_idx_T_48) node _store_resp_idx_T_50 = eq(rob_respd[2], UInt<1>(0h0)) node _store_resp_idx_T_51 = eq(rob[2].cmd, UInt<1>(0h1)) node _store_resp_idx_T_52 = eq(rob[2].cmd, UInt<5>(0h11)) node _store_resp_idx_T_53 = or(_store_resp_idx_T_51, _store_resp_idx_T_52) node _store_resp_idx_T_54 = eq(rob[2].cmd, UInt<3>(0h7)) node _store_resp_idx_T_55 = or(_store_resp_idx_T_53, _store_resp_idx_T_54) node _store_resp_idx_T_56 = eq(rob[2].cmd, UInt<3>(0h4)) node _store_resp_idx_T_57 = eq(rob[2].cmd, UInt<4>(0h9)) node _store_resp_idx_T_58 = eq(rob[2].cmd, UInt<4>(0ha)) node _store_resp_idx_T_59 = eq(rob[2].cmd, UInt<4>(0hb)) node _store_resp_idx_T_60 = or(_store_resp_idx_T_56, _store_resp_idx_T_57) node _store_resp_idx_T_61 = or(_store_resp_idx_T_60, _store_resp_idx_T_58) node _store_resp_idx_T_62 = or(_store_resp_idx_T_61, _store_resp_idx_T_59) node _store_resp_idx_T_63 = eq(rob[2].cmd, UInt<4>(0h8)) node _store_resp_idx_T_64 = eq(rob[2].cmd, UInt<4>(0hc)) node _store_resp_idx_T_65 = eq(rob[2].cmd, UInt<4>(0hd)) node _store_resp_idx_T_66 = eq(rob[2].cmd, UInt<4>(0he)) node _store_resp_idx_T_67 = eq(rob[2].cmd, UInt<4>(0hf)) node _store_resp_idx_T_68 = or(_store_resp_idx_T_63, _store_resp_idx_T_64) node _store_resp_idx_T_69 = or(_store_resp_idx_T_68, _store_resp_idx_T_65) node _store_resp_idx_T_70 = or(_store_resp_idx_T_69, _store_resp_idx_T_66) node _store_resp_idx_T_71 = or(_store_resp_idx_T_70, _store_resp_idx_T_67) node _store_resp_idx_T_72 = or(_store_resp_idx_T_62, _store_resp_idx_T_71) node _store_resp_idx_T_73 = or(_store_resp_idx_T_55, _store_resp_idx_T_72) node _store_resp_idx_T_74 = and(_store_resp_idx_T_50, _store_resp_idx_T_73) node _store_resp_idx_T_75 = eq(rob_respd[3], UInt<1>(0h0)) node _store_resp_idx_T_76 = eq(rob[3].cmd, UInt<1>(0h1)) node _store_resp_idx_T_77 = eq(rob[3].cmd, UInt<5>(0h11)) node _store_resp_idx_T_78 = or(_store_resp_idx_T_76, _store_resp_idx_T_77) node _store_resp_idx_T_79 = eq(rob[3].cmd, UInt<3>(0h7)) node _store_resp_idx_T_80 = or(_store_resp_idx_T_78, _store_resp_idx_T_79) node _store_resp_idx_T_81 = eq(rob[3].cmd, UInt<3>(0h4)) node _store_resp_idx_T_82 = eq(rob[3].cmd, UInt<4>(0h9)) node _store_resp_idx_T_83 = eq(rob[3].cmd, UInt<4>(0ha)) node _store_resp_idx_T_84 = eq(rob[3].cmd, UInt<4>(0hb)) node _store_resp_idx_T_85 = or(_store_resp_idx_T_81, _store_resp_idx_T_82) node _store_resp_idx_T_86 = or(_store_resp_idx_T_85, _store_resp_idx_T_83) node _store_resp_idx_T_87 = or(_store_resp_idx_T_86, _store_resp_idx_T_84) node _store_resp_idx_T_88 = eq(rob[3].cmd, UInt<4>(0h8)) node _store_resp_idx_T_89 = eq(rob[3].cmd, UInt<4>(0hc)) node _store_resp_idx_T_90 = eq(rob[3].cmd, UInt<4>(0hd)) node _store_resp_idx_T_91 = eq(rob[3].cmd, UInt<4>(0he)) node _store_resp_idx_T_92 = eq(rob[3].cmd, UInt<4>(0hf)) node _store_resp_idx_T_93 = or(_store_resp_idx_T_88, _store_resp_idx_T_89) node _store_resp_idx_T_94 = or(_store_resp_idx_T_93, _store_resp_idx_T_90) node _store_resp_idx_T_95 = or(_store_resp_idx_T_94, _store_resp_idx_T_91) node _store_resp_idx_T_96 = or(_store_resp_idx_T_95, _store_resp_idx_T_92) node _store_resp_idx_T_97 = or(_store_resp_idx_T_87, _store_resp_idx_T_96) node _store_resp_idx_T_98 = or(_store_resp_idx_T_80, _store_resp_idx_T_97) node _store_resp_idx_T_99 = and(_store_resp_idx_T_75, _store_resp_idx_T_98) node _store_resp_idx_T_100 = eq(rob_respd[4], UInt<1>(0h0)) node _store_resp_idx_T_101 = eq(rob[4].cmd, UInt<1>(0h1)) node _store_resp_idx_T_102 = eq(rob[4].cmd, UInt<5>(0h11)) node _store_resp_idx_T_103 = or(_store_resp_idx_T_101, _store_resp_idx_T_102) node _store_resp_idx_T_104 = eq(rob[4].cmd, UInt<3>(0h7)) node _store_resp_idx_T_105 = or(_store_resp_idx_T_103, _store_resp_idx_T_104) node _store_resp_idx_T_106 = eq(rob[4].cmd, UInt<3>(0h4)) node _store_resp_idx_T_107 = eq(rob[4].cmd, UInt<4>(0h9)) node _store_resp_idx_T_108 = eq(rob[4].cmd, UInt<4>(0ha)) node _store_resp_idx_T_109 = eq(rob[4].cmd, UInt<4>(0hb)) node _store_resp_idx_T_110 = or(_store_resp_idx_T_106, _store_resp_idx_T_107) node _store_resp_idx_T_111 = or(_store_resp_idx_T_110, _store_resp_idx_T_108) node _store_resp_idx_T_112 = or(_store_resp_idx_T_111, _store_resp_idx_T_109) node _store_resp_idx_T_113 = eq(rob[4].cmd, UInt<4>(0h8)) node _store_resp_idx_T_114 = eq(rob[4].cmd, UInt<4>(0hc)) node _store_resp_idx_T_115 = eq(rob[4].cmd, UInt<4>(0hd)) node _store_resp_idx_T_116 = eq(rob[4].cmd, UInt<4>(0he)) node _store_resp_idx_T_117 = eq(rob[4].cmd, UInt<4>(0hf)) node _store_resp_idx_T_118 = or(_store_resp_idx_T_113, _store_resp_idx_T_114) node _store_resp_idx_T_119 = or(_store_resp_idx_T_118, _store_resp_idx_T_115) node _store_resp_idx_T_120 = or(_store_resp_idx_T_119, _store_resp_idx_T_116) node _store_resp_idx_T_121 = or(_store_resp_idx_T_120, _store_resp_idx_T_117) node _store_resp_idx_T_122 = or(_store_resp_idx_T_112, _store_resp_idx_T_121) node _store_resp_idx_T_123 = or(_store_resp_idx_T_105, _store_resp_idx_T_122) node _store_resp_idx_T_124 = and(_store_resp_idx_T_100, _store_resp_idx_T_123) node _store_resp_idx_T_125 = eq(rob_respd[5], UInt<1>(0h0)) node _store_resp_idx_T_126 = eq(rob[5].cmd, UInt<1>(0h1)) node _store_resp_idx_T_127 = eq(rob[5].cmd, UInt<5>(0h11)) node _store_resp_idx_T_128 = or(_store_resp_idx_T_126, _store_resp_idx_T_127) node _store_resp_idx_T_129 = eq(rob[5].cmd, UInt<3>(0h7)) node _store_resp_idx_T_130 = or(_store_resp_idx_T_128, _store_resp_idx_T_129) node _store_resp_idx_T_131 = eq(rob[5].cmd, UInt<3>(0h4)) node _store_resp_idx_T_132 = eq(rob[5].cmd, UInt<4>(0h9)) node _store_resp_idx_T_133 = eq(rob[5].cmd, UInt<4>(0ha)) node _store_resp_idx_T_134 = eq(rob[5].cmd, UInt<4>(0hb)) node _store_resp_idx_T_135 = or(_store_resp_idx_T_131, _store_resp_idx_T_132) node _store_resp_idx_T_136 = or(_store_resp_idx_T_135, _store_resp_idx_T_133) node _store_resp_idx_T_137 = or(_store_resp_idx_T_136, _store_resp_idx_T_134) node _store_resp_idx_T_138 = eq(rob[5].cmd, UInt<4>(0h8)) node _store_resp_idx_T_139 = eq(rob[5].cmd, UInt<4>(0hc)) node _store_resp_idx_T_140 = eq(rob[5].cmd, UInt<4>(0hd)) node _store_resp_idx_T_141 = eq(rob[5].cmd, UInt<4>(0he)) node _store_resp_idx_T_142 = eq(rob[5].cmd, UInt<4>(0hf)) node _store_resp_idx_T_143 = or(_store_resp_idx_T_138, _store_resp_idx_T_139) node _store_resp_idx_T_144 = or(_store_resp_idx_T_143, _store_resp_idx_T_140) node _store_resp_idx_T_145 = or(_store_resp_idx_T_144, _store_resp_idx_T_141) node _store_resp_idx_T_146 = or(_store_resp_idx_T_145, _store_resp_idx_T_142) node _store_resp_idx_T_147 = or(_store_resp_idx_T_137, _store_resp_idx_T_146) node _store_resp_idx_T_148 = or(_store_resp_idx_T_130, _store_resp_idx_T_147) node _store_resp_idx_T_149 = and(_store_resp_idx_T_125, _store_resp_idx_T_148) node _store_resp_idx_T_150 = eq(rob_respd[6], UInt<1>(0h0)) node _store_resp_idx_T_151 = eq(rob[6].cmd, UInt<1>(0h1)) node _store_resp_idx_T_152 = eq(rob[6].cmd, UInt<5>(0h11)) node _store_resp_idx_T_153 = or(_store_resp_idx_T_151, _store_resp_idx_T_152) node _store_resp_idx_T_154 = eq(rob[6].cmd, UInt<3>(0h7)) node _store_resp_idx_T_155 = or(_store_resp_idx_T_153, _store_resp_idx_T_154) node _store_resp_idx_T_156 = eq(rob[6].cmd, UInt<3>(0h4)) node _store_resp_idx_T_157 = eq(rob[6].cmd, UInt<4>(0h9)) node _store_resp_idx_T_158 = eq(rob[6].cmd, UInt<4>(0ha)) node _store_resp_idx_T_159 = eq(rob[6].cmd, UInt<4>(0hb)) node _store_resp_idx_T_160 = or(_store_resp_idx_T_156, _store_resp_idx_T_157) node _store_resp_idx_T_161 = or(_store_resp_idx_T_160, _store_resp_idx_T_158) node _store_resp_idx_T_162 = or(_store_resp_idx_T_161, _store_resp_idx_T_159) node _store_resp_idx_T_163 = eq(rob[6].cmd, UInt<4>(0h8)) node _store_resp_idx_T_164 = eq(rob[6].cmd, UInt<4>(0hc)) node _store_resp_idx_T_165 = eq(rob[6].cmd, UInt<4>(0hd)) node _store_resp_idx_T_166 = eq(rob[6].cmd, UInt<4>(0he)) node _store_resp_idx_T_167 = eq(rob[6].cmd, UInt<4>(0hf)) node _store_resp_idx_T_168 = or(_store_resp_idx_T_163, _store_resp_idx_T_164) node _store_resp_idx_T_169 = or(_store_resp_idx_T_168, _store_resp_idx_T_165) node _store_resp_idx_T_170 = or(_store_resp_idx_T_169, _store_resp_idx_T_166) node _store_resp_idx_T_171 = or(_store_resp_idx_T_170, _store_resp_idx_T_167) node _store_resp_idx_T_172 = or(_store_resp_idx_T_162, _store_resp_idx_T_171) node _store_resp_idx_T_173 = or(_store_resp_idx_T_155, _store_resp_idx_T_172) node _store_resp_idx_T_174 = and(_store_resp_idx_T_150, _store_resp_idx_T_173) node _store_resp_idx_T_175 = eq(rob_respd[7], UInt<1>(0h0)) node _store_resp_idx_T_176 = eq(rob[7].cmd, UInt<1>(0h1)) node _store_resp_idx_T_177 = eq(rob[7].cmd, UInt<5>(0h11)) node _store_resp_idx_T_178 = or(_store_resp_idx_T_176, _store_resp_idx_T_177) node _store_resp_idx_T_179 = eq(rob[7].cmd, UInt<3>(0h7)) node _store_resp_idx_T_180 = or(_store_resp_idx_T_178, _store_resp_idx_T_179) node _store_resp_idx_T_181 = eq(rob[7].cmd, UInt<3>(0h4)) node _store_resp_idx_T_182 = eq(rob[7].cmd, UInt<4>(0h9)) node _store_resp_idx_T_183 = eq(rob[7].cmd, UInt<4>(0ha)) node _store_resp_idx_T_184 = eq(rob[7].cmd, UInt<4>(0hb)) node _store_resp_idx_T_185 = or(_store_resp_idx_T_181, _store_resp_idx_T_182) node _store_resp_idx_T_186 = or(_store_resp_idx_T_185, _store_resp_idx_T_183) node _store_resp_idx_T_187 = or(_store_resp_idx_T_186, _store_resp_idx_T_184) node _store_resp_idx_T_188 = eq(rob[7].cmd, UInt<4>(0h8)) node _store_resp_idx_T_189 = eq(rob[7].cmd, UInt<4>(0hc)) node _store_resp_idx_T_190 = eq(rob[7].cmd, UInt<4>(0hd)) node _store_resp_idx_T_191 = eq(rob[7].cmd, UInt<4>(0he)) node _store_resp_idx_T_192 = eq(rob[7].cmd, UInt<4>(0hf)) node _store_resp_idx_T_193 = or(_store_resp_idx_T_188, _store_resp_idx_T_189) node _store_resp_idx_T_194 = or(_store_resp_idx_T_193, _store_resp_idx_T_190) node _store_resp_idx_T_195 = or(_store_resp_idx_T_194, _store_resp_idx_T_191) node _store_resp_idx_T_196 = or(_store_resp_idx_T_195, _store_resp_idx_T_192) node _store_resp_idx_T_197 = or(_store_resp_idx_T_187, _store_resp_idx_T_196) node _store_resp_idx_T_198 = or(_store_resp_idx_T_180, _store_resp_idx_T_197) node _store_resp_idx_T_199 = and(_store_resp_idx_T_175, _store_resp_idx_T_198) node _store_resp_idx_T_200 = eq(rob_respd[8], UInt<1>(0h0)) node _store_resp_idx_T_201 = eq(rob[8].cmd, UInt<1>(0h1)) node _store_resp_idx_T_202 = eq(rob[8].cmd, UInt<5>(0h11)) node _store_resp_idx_T_203 = or(_store_resp_idx_T_201, _store_resp_idx_T_202) node _store_resp_idx_T_204 = eq(rob[8].cmd, UInt<3>(0h7)) node _store_resp_idx_T_205 = or(_store_resp_idx_T_203, _store_resp_idx_T_204) node _store_resp_idx_T_206 = eq(rob[8].cmd, UInt<3>(0h4)) node _store_resp_idx_T_207 = eq(rob[8].cmd, UInt<4>(0h9)) node _store_resp_idx_T_208 = eq(rob[8].cmd, UInt<4>(0ha)) node _store_resp_idx_T_209 = eq(rob[8].cmd, UInt<4>(0hb)) node _store_resp_idx_T_210 = or(_store_resp_idx_T_206, _store_resp_idx_T_207) node _store_resp_idx_T_211 = or(_store_resp_idx_T_210, _store_resp_idx_T_208) node _store_resp_idx_T_212 = or(_store_resp_idx_T_211, _store_resp_idx_T_209) node _store_resp_idx_T_213 = eq(rob[8].cmd, UInt<4>(0h8)) node _store_resp_idx_T_214 = eq(rob[8].cmd, UInt<4>(0hc)) node _store_resp_idx_T_215 = eq(rob[8].cmd, UInt<4>(0hd)) node _store_resp_idx_T_216 = eq(rob[8].cmd, UInt<4>(0he)) node _store_resp_idx_T_217 = eq(rob[8].cmd, UInt<4>(0hf)) node _store_resp_idx_T_218 = or(_store_resp_idx_T_213, _store_resp_idx_T_214) node _store_resp_idx_T_219 = or(_store_resp_idx_T_218, _store_resp_idx_T_215) node _store_resp_idx_T_220 = or(_store_resp_idx_T_219, _store_resp_idx_T_216) node _store_resp_idx_T_221 = or(_store_resp_idx_T_220, _store_resp_idx_T_217) node _store_resp_idx_T_222 = or(_store_resp_idx_T_212, _store_resp_idx_T_221) node _store_resp_idx_T_223 = or(_store_resp_idx_T_205, _store_resp_idx_T_222) node _store_resp_idx_T_224 = and(_store_resp_idx_T_200, _store_resp_idx_T_223) node _store_resp_idx_T_225 = eq(rob_respd[9], UInt<1>(0h0)) node _store_resp_idx_T_226 = eq(rob[9].cmd, UInt<1>(0h1)) node _store_resp_idx_T_227 = eq(rob[9].cmd, UInt<5>(0h11)) node _store_resp_idx_T_228 = or(_store_resp_idx_T_226, _store_resp_idx_T_227) node _store_resp_idx_T_229 = eq(rob[9].cmd, UInt<3>(0h7)) node _store_resp_idx_T_230 = or(_store_resp_idx_T_228, _store_resp_idx_T_229) node _store_resp_idx_T_231 = eq(rob[9].cmd, UInt<3>(0h4)) node _store_resp_idx_T_232 = eq(rob[9].cmd, UInt<4>(0h9)) node _store_resp_idx_T_233 = eq(rob[9].cmd, UInt<4>(0ha)) node _store_resp_idx_T_234 = eq(rob[9].cmd, UInt<4>(0hb)) node _store_resp_idx_T_235 = or(_store_resp_idx_T_231, _store_resp_idx_T_232) node _store_resp_idx_T_236 = or(_store_resp_idx_T_235, _store_resp_idx_T_233) node _store_resp_idx_T_237 = or(_store_resp_idx_T_236, _store_resp_idx_T_234) node _store_resp_idx_T_238 = eq(rob[9].cmd, UInt<4>(0h8)) node _store_resp_idx_T_239 = eq(rob[9].cmd, UInt<4>(0hc)) node _store_resp_idx_T_240 = eq(rob[9].cmd, UInt<4>(0hd)) node _store_resp_idx_T_241 = eq(rob[9].cmd, UInt<4>(0he)) node _store_resp_idx_T_242 = eq(rob[9].cmd, UInt<4>(0hf)) node _store_resp_idx_T_243 = or(_store_resp_idx_T_238, _store_resp_idx_T_239) node _store_resp_idx_T_244 = or(_store_resp_idx_T_243, _store_resp_idx_T_240) node _store_resp_idx_T_245 = or(_store_resp_idx_T_244, _store_resp_idx_T_241) node _store_resp_idx_T_246 = or(_store_resp_idx_T_245, _store_resp_idx_T_242) node _store_resp_idx_T_247 = or(_store_resp_idx_T_237, _store_resp_idx_T_246) node _store_resp_idx_T_248 = or(_store_resp_idx_T_230, _store_resp_idx_T_247) node _store_resp_idx_T_249 = and(_store_resp_idx_T_225, _store_resp_idx_T_248) node _store_resp_idx_T_250 = eq(rob_respd[10], UInt<1>(0h0)) node _store_resp_idx_T_251 = eq(rob[10].cmd, UInt<1>(0h1)) node _store_resp_idx_T_252 = eq(rob[10].cmd, UInt<5>(0h11)) node _store_resp_idx_T_253 = or(_store_resp_idx_T_251, _store_resp_idx_T_252) node _store_resp_idx_T_254 = eq(rob[10].cmd, UInt<3>(0h7)) node _store_resp_idx_T_255 = or(_store_resp_idx_T_253, _store_resp_idx_T_254) node _store_resp_idx_T_256 = eq(rob[10].cmd, UInt<3>(0h4)) node _store_resp_idx_T_257 = eq(rob[10].cmd, UInt<4>(0h9)) node _store_resp_idx_T_258 = eq(rob[10].cmd, UInt<4>(0ha)) node _store_resp_idx_T_259 = eq(rob[10].cmd, UInt<4>(0hb)) node _store_resp_idx_T_260 = or(_store_resp_idx_T_256, _store_resp_idx_T_257) node _store_resp_idx_T_261 = or(_store_resp_idx_T_260, _store_resp_idx_T_258) node _store_resp_idx_T_262 = or(_store_resp_idx_T_261, _store_resp_idx_T_259) node _store_resp_idx_T_263 = eq(rob[10].cmd, UInt<4>(0h8)) node _store_resp_idx_T_264 = eq(rob[10].cmd, UInt<4>(0hc)) node _store_resp_idx_T_265 = eq(rob[10].cmd, UInt<4>(0hd)) node _store_resp_idx_T_266 = eq(rob[10].cmd, UInt<4>(0he)) node _store_resp_idx_T_267 = eq(rob[10].cmd, UInt<4>(0hf)) node _store_resp_idx_T_268 = or(_store_resp_idx_T_263, _store_resp_idx_T_264) node _store_resp_idx_T_269 = or(_store_resp_idx_T_268, _store_resp_idx_T_265) node _store_resp_idx_T_270 = or(_store_resp_idx_T_269, _store_resp_idx_T_266) node _store_resp_idx_T_271 = or(_store_resp_idx_T_270, _store_resp_idx_T_267) node _store_resp_idx_T_272 = or(_store_resp_idx_T_262, _store_resp_idx_T_271) node _store_resp_idx_T_273 = or(_store_resp_idx_T_255, _store_resp_idx_T_272) node _store_resp_idx_T_274 = and(_store_resp_idx_T_250, _store_resp_idx_T_273) node _store_resp_idx_T_275 = eq(rob_respd[11], UInt<1>(0h0)) node _store_resp_idx_T_276 = eq(rob[11].cmd, UInt<1>(0h1)) node _store_resp_idx_T_277 = eq(rob[11].cmd, UInt<5>(0h11)) node _store_resp_idx_T_278 = or(_store_resp_idx_T_276, _store_resp_idx_T_277) node _store_resp_idx_T_279 = eq(rob[11].cmd, UInt<3>(0h7)) node _store_resp_idx_T_280 = or(_store_resp_idx_T_278, _store_resp_idx_T_279) node _store_resp_idx_T_281 = eq(rob[11].cmd, UInt<3>(0h4)) node _store_resp_idx_T_282 = eq(rob[11].cmd, UInt<4>(0h9)) node _store_resp_idx_T_283 = eq(rob[11].cmd, UInt<4>(0ha)) node _store_resp_idx_T_284 = eq(rob[11].cmd, UInt<4>(0hb)) node _store_resp_idx_T_285 = or(_store_resp_idx_T_281, _store_resp_idx_T_282) node _store_resp_idx_T_286 = or(_store_resp_idx_T_285, _store_resp_idx_T_283) node _store_resp_idx_T_287 = or(_store_resp_idx_T_286, _store_resp_idx_T_284) node _store_resp_idx_T_288 = eq(rob[11].cmd, UInt<4>(0h8)) node _store_resp_idx_T_289 = eq(rob[11].cmd, UInt<4>(0hc)) node _store_resp_idx_T_290 = eq(rob[11].cmd, UInt<4>(0hd)) node _store_resp_idx_T_291 = eq(rob[11].cmd, UInt<4>(0he)) node _store_resp_idx_T_292 = eq(rob[11].cmd, UInt<4>(0hf)) node _store_resp_idx_T_293 = or(_store_resp_idx_T_288, _store_resp_idx_T_289) node _store_resp_idx_T_294 = or(_store_resp_idx_T_293, _store_resp_idx_T_290) node _store_resp_idx_T_295 = or(_store_resp_idx_T_294, _store_resp_idx_T_291) node _store_resp_idx_T_296 = or(_store_resp_idx_T_295, _store_resp_idx_T_292) node _store_resp_idx_T_297 = or(_store_resp_idx_T_287, _store_resp_idx_T_296) node _store_resp_idx_T_298 = or(_store_resp_idx_T_280, _store_resp_idx_T_297) node _store_resp_idx_T_299 = and(_store_resp_idx_T_275, _store_resp_idx_T_298) node _store_resp_idx_T_300 = eq(rob_respd[12], UInt<1>(0h0)) node _store_resp_idx_T_301 = eq(rob[12].cmd, UInt<1>(0h1)) node _store_resp_idx_T_302 = eq(rob[12].cmd, UInt<5>(0h11)) node _store_resp_idx_T_303 = or(_store_resp_idx_T_301, _store_resp_idx_T_302) node _store_resp_idx_T_304 = eq(rob[12].cmd, UInt<3>(0h7)) node _store_resp_idx_T_305 = or(_store_resp_idx_T_303, _store_resp_idx_T_304) node _store_resp_idx_T_306 = eq(rob[12].cmd, UInt<3>(0h4)) node _store_resp_idx_T_307 = eq(rob[12].cmd, UInt<4>(0h9)) node _store_resp_idx_T_308 = eq(rob[12].cmd, UInt<4>(0ha)) node _store_resp_idx_T_309 = eq(rob[12].cmd, UInt<4>(0hb)) node _store_resp_idx_T_310 = or(_store_resp_idx_T_306, _store_resp_idx_T_307) node _store_resp_idx_T_311 = or(_store_resp_idx_T_310, _store_resp_idx_T_308) node _store_resp_idx_T_312 = or(_store_resp_idx_T_311, _store_resp_idx_T_309) node _store_resp_idx_T_313 = eq(rob[12].cmd, UInt<4>(0h8)) node _store_resp_idx_T_314 = eq(rob[12].cmd, UInt<4>(0hc)) node _store_resp_idx_T_315 = eq(rob[12].cmd, UInt<4>(0hd)) node _store_resp_idx_T_316 = eq(rob[12].cmd, UInt<4>(0he)) node _store_resp_idx_T_317 = eq(rob[12].cmd, UInt<4>(0hf)) node _store_resp_idx_T_318 = or(_store_resp_idx_T_313, _store_resp_idx_T_314) node _store_resp_idx_T_319 = or(_store_resp_idx_T_318, _store_resp_idx_T_315) node _store_resp_idx_T_320 = or(_store_resp_idx_T_319, _store_resp_idx_T_316) node _store_resp_idx_T_321 = or(_store_resp_idx_T_320, _store_resp_idx_T_317) node _store_resp_idx_T_322 = or(_store_resp_idx_T_312, _store_resp_idx_T_321) node _store_resp_idx_T_323 = or(_store_resp_idx_T_305, _store_resp_idx_T_322) node _store_resp_idx_T_324 = and(_store_resp_idx_T_300, _store_resp_idx_T_323) node _store_resp_idx_T_325 = eq(rob_respd[13], UInt<1>(0h0)) node _store_resp_idx_T_326 = eq(rob[13].cmd, UInt<1>(0h1)) node _store_resp_idx_T_327 = eq(rob[13].cmd, UInt<5>(0h11)) node _store_resp_idx_T_328 = or(_store_resp_idx_T_326, _store_resp_idx_T_327) node _store_resp_idx_T_329 = eq(rob[13].cmd, UInt<3>(0h7)) node _store_resp_idx_T_330 = or(_store_resp_idx_T_328, _store_resp_idx_T_329) node _store_resp_idx_T_331 = eq(rob[13].cmd, UInt<3>(0h4)) node _store_resp_idx_T_332 = eq(rob[13].cmd, UInt<4>(0h9)) node _store_resp_idx_T_333 = eq(rob[13].cmd, UInt<4>(0ha)) node _store_resp_idx_T_334 = eq(rob[13].cmd, UInt<4>(0hb)) node _store_resp_idx_T_335 = or(_store_resp_idx_T_331, _store_resp_idx_T_332) node _store_resp_idx_T_336 = or(_store_resp_idx_T_335, _store_resp_idx_T_333) node _store_resp_idx_T_337 = or(_store_resp_idx_T_336, _store_resp_idx_T_334) node _store_resp_idx_T_338 = eq(rob[13].cmd, UInt<4>(0h8)) node _store_resp_idx_T_339 = eq(rob[13].cmd, UInt<4>(0hc)) node _store_resp_idx_T_340 = eq(rob[13].cmd, UInt<4>(0hd)) node _store_resp_idx_T_341 = eq(rob[13].cmd, UInt<4>(0he)) node _store_resp_idx_T_342 = eq(rob[13].cmd, UInt<4>(0hf)) node _store_resp_idx_T_343 = or(_store_resp_idx_T_338, _store_resp_idx_T_339) node _store_resp_idx_T_344 = or(_store_resp_idx_T_343, _store_resp_idx_T_340) node _store_resp_idx_T_345 = or(_store_resp_idx_T_344, _store_resp_idx_T_341) node _store_resp_idx_T_346 = or(_store_resp_idx_T_345, _store_resp_idx_T_342) node _store_resp_idx_T_347 = or(_store_resp_idx_T_337, _store_resp_idx_T_346) node _store_resp_idx_T_348 = or(_store_resp_idx_T_330, _store_resp_idx_T_347) node _store_resp_idx_T_349 = and(_store_resp_idx_T_325, _store_resp_idx_T_348) node _store_resp_idx_T_350 = eq(rob_respd[14], UInt<1>(0h0)) node _store_resp_idx_T_351 = eq(rob[14].cmd, UInt<1>(0h1)) node _store_resp_idx_T_352 = eq(rob[14].cmd, UInt<5>(0h11)) node _store_resp_idx_T_353 = or(_store_resp_idx_T_351, _store_resp_idx_T_352) node _store_resp_idx_T_354 = eq(rob[14].cmd, UInt<3>(0h7)) node _store_resp_idx_T_355 = or(_store_resp_idx_T_353, _store_resp_idx_T_354) node _store_resp_idx_T_356 = eq(rob[14].cmd, UInt<3>(0h4)) node _store_resp_idx_T_357 = eq(rob[14].cmd, UInt<4>(0h9)) node _store_resp_idx_T_358 = eq(rob[14].cmd, UInt<4>(0ha)) node _store_resp_idx_T_359 = eq(rob[14].cmd, UInt<4>(0hb)) node _store_resp_idx_T_360 = or(_store_resp_idx_T_356, _store_resp_idx_T_357) node _store_resp_idx_T_361 = or(_store_resp_idx_T_360, _store_resp_idx_T_358) node _store_resp_idx_T_362 = or(_store_resp_idx_T_361, _store_resp_idx_T_359) node _store_resp_idx_T_363 = eq(rob[14].cmd, UInt<4>(0h8)) node _store_resp_idx_T_364 = eq(rob[14].cmd, UInt<4>(0hc)) node _store_resp_idx_T_365 = eq(rob[14].cmd, UInt<4>(0hd)) node _store_resp_idx_T_366 = eq(rob[14].cmd, UInt<4>(0he)) node _store_resp_idx_T_367 = eq(rob[14].cmd, UInt<4>(0hf)) node _store_resp_idx_T_368 = or(_store_resp_idx_T_363, _store_resp_idx_T_364) node _store_resp_idx_T_369 = or(_store_resp_idx_T_368, _store_resp_idx_T_365) node _store_resp_idx_T_370 = or(_store_resp_idx_T_369, _store_resp_idx_T_366) node _store_resp_idx_T_371 = or(_store_resp_idx_T_370, _store_resp_idx_T_367) node _store_resp_idx_T_372 = or(_store_resp_idx_T_362, _store_resp_idx_T_371) node _store_resp_idx_T_373 = or(_store_resp_idx_T_355, _store_resp_idx_T_372) node _store_resp_idx_T_374 = and(_store_resp_idx_T_350, _store_resp_idx_T_373) node _store_resp_idx_T_375 = eq(rob_respd[15], UInt<1>(0h0)) node _store_resp_idx_T_376 = eq(rob[15].cmd, UInt<1>(0h1)) node _store_resp_idx_T_377 = eq(rob[15].cmd, UInt<5>(0h11)) node _store_resp_idx_T_378 = or(_store_resp_idx_T_376, _store_resp_idx_T_377) node _store_resp_idx_T_379 = eq(rob[15].cmd, UInt<3>(0h7)) node _store_resp_idx_T_380 = or(_store_resp_idx_T_378, _store_resp_idx_T_379) node _store_resp_idx_T_381 = eq(rob[15].cmd, UInt<3>(0h4)) node _store_resp_idx_T_382 = eq(rob[15].cmd, UInt<4>(0h9)) node _store_resp_idx_T_383 = eq(rob[15].cmd, UInt<4>(0ha)) node _store_resp_idx_T_384 = eq(rob[15].cmd, UInt<4>(0hb)) node _store_resp_idx_T_385 = or(_store_resp_idx_T_381, _store_resp_idx_T_382) node _store_resp_idx_T_386 = or(_store_resp_idx_T_385, _store_resp_idx_T_383) node _store_resp_idx_T_387 = or(_store_resp_idx_T_386, _store_resp_idx_T_384) node _store_resp_idx_T_388 = eq(rob[15].cmd, UInt<4>(0h8)) node _store_resp_idx_T_389 = eq(rob[15].cmd, UInt<4>(0hc)) node _store_resp_idx_T_390 = eq(rob[15].cmd, UInt<4>(0hd)) node _store_resp_idx_T_391 = eq(rob[15].cmd, UInt<4>(0he)) node _store_resp_idx_T_392 = eq(rob[15].cmd, UInt<4>(0hf)) node _store_resp_idx_T_393 = or(_store_resp_idx_T_388, _store_resp_idx_T_389) node _store_resp_idx_T_394 = or(_store_resp_idx_T_393, _store_resp_idx_T_390) node _store_resp_idx_T_395 = or(_store_resp_idx_T_394, _store_resp_idx_T_391) node _store_resp_idx_T_396 = or(_store_resp_idx_T_395, _store_resp_idx_T_392) node _store_resp_idx_T_397 = or(_store_resp_idx_T_387, _store_resp_idx_T_396) node _store_resp_idx_T_398 = or(_store_resp_idx_T_380, _store_resp_idx_T_397) node _store_resp_idx_T_399 = and(_store_resp_idx_T_375, _store_resp_idx_T_398) node _store_resp_idx_T_400 = eq(rob_respd[16], UInt<1>(0h0)) node _store_resp_idx_T_401 = eq(rob[16].cmd, UInt<1>(0h1)) node _store_resp_idx_T_402 = eq(rob[16].cmd, UInt<5>(0h11)) node _store_resp_idx_T_403 = or(_store_resp_idx_T_401, _store_resp_idx_T_402) node _store_resp_idx_T_404 = eq(rob[16].cmd, UInt<3>(0h7)) node _store_resp_idx_T_405 = or(_store_resp_idx_T_403, _store_resp_idx_T_404) node _store_resp_idx_T_406 = eq(rob[16].cmd, UInt<3>(0h4)) node _store_resp_idx_T_407 = eq(rob[16].cmd, UInt<4>(0h9)) node _store_resp_idx_T_408 = eq(rob[16].cmd, UInt<4>(0ha)) node _store_resp_idx_T_409 = eq(rob[16].cmd, UInt<4>(0hb)) node _store_resp_idx_T_410 = or(_store_resp_idx_T_406, _store_resp_idx_T_407) node _store_resp_idx_T_411 = or(_store_resp_idx_T_410, _store_resp_idx_T_408) node _store_resp_idx_T_412 = or(_store_resp_idx_T_411, _store_resp_idx_T_409) node _store_resp_idx_T_413 = eq(rob[16].cmd, UInt<4>(0h8)) node _store_resp_idx_T_414 = eq(rob[16].cmd, UInt<4>(0hc)) node _store_resp_idx_T_415 = eq(rob[16].cmd, UInt<4>(0hd)) node _store_resp_idx_T_416 = eq(rob[16].cmd, UInt<4>(0he)) node _store_resp_idx_T_417 = eq(rob[16].cmd, UInt<4>(0hf)) node _store_resp_idx_T_418 = or(_store_resp_idx_T_413, _store_resp_idx_T_414) node _store_resp_idx_T_419 = or(_store_resp_idx_T_418, _store_resp_idx_T_415) node _store_resp_idx_T_420 = or(_store_resp_idx_T_419, _store_resp_idx_T_416) node _store_resp_idx_T_421 = or(_store_resp_idx_T_420, _store_resp_idx_T_417) node _store_resp_idx_T_422 = or(_store_resp_idx_T_412, _store_resp_idx_T_421) node _store_resp_idx_T_423 = or(_store_resp_idx_T_405, _store_resp_idx_T_422) node _store_resp_idx_T_424 = and(_store_resp_idx_T_400, _store_resp_idx_T_423) node _store_resp_idx_T_425 = eq(rob_respd[17], UInt<1>(0h0)) node _store_resp_idx_T_426 = eq(rob[17].cmd, UInt<1>(0h1)) node _store_resp_idx_T_427 = eq(rob[17].cmd, UInt<5>(0h11)) node _store_resp_idx_T_428 = or(_store_resp_idx_T_426, _store_resp_idx_T_427) node _store_resp_idx_T_429 = eq(rob[17].cmd, UInt<3>(0h7)) node _store_resp_idx_T_430 = or(_store_resp_idx_T_428, _store_resp_idx_T_429) node _store_resp_idx_T_431 = eq(rob[17].cmd, UInt<3>(0h4)) node _store_resp_idx_T_432 = eq(rob[17].cmd, UInt<4>(0h9)) node _store_resp_idx_T_433 = eq(rob[17].cmd, UInt<4>(0ha)) node _store_resp_idx_T_434 = eq(rob[17].cmd, UInt<4>(0hb)) node _store_resp_idx_T_435 = or(_store_resp_idx_T_431, _store_resp_idx_T_432) node _store_resp_idx_T_436 = or(_store_resp_idx_T_435, _store_resp_idx_T_433) node _store_resp_idx_T_437 = or(_store_resp_idx_T_436, _store_resp_idx_T_434) node _store_resp_idx_T_438 = eq(rob[17].cmd, UInt<4>(0h8)) node _store_resp_idx_T_439 = eq(rob[17].cmd, UInt<4>(0hc)) node _store_resp_idx_T_440 = eq(rob[17].cmd, UInt<4>(0hd)) node _store_resp_idx_T_441 = eq(rob[17].cmd, UInt<4>(0he)) node _store_resp_idx_T_442 = eq(rob[17].cmd, UInt<4>(0hf)) node _store_resp_idx_T_443 = or(_store_resp_idx_T_438, _store_resp_idx_T_439) node _store_resp_idx_T_444 = or(_store_resp_idx_T_443, _store_resp_idx_T_440) node _store_resp_idx_T_445 = or(_store_resp_idx_T_444, _store_resp_idx_T_441) node _store_resp_idx_T_446 = or(_store_resp_idx_T_445, _store_resp_idx_T_442) node _store_resp_idx_T_447 = or(_store_resp_idx_T_437, _store_resp_idx_T_446) node _store_resp_idx_T_448 = or(_store_resp_idx_T_430, _store_resp_idx_T_447) node _store_resp_idx_T_449 = and(_store_resp_idx_T_425, _store_resp_idx_T_448) node _store_resp_idx_T_450 = eq(rob_respd[18], UInt<1>(0h0)) node _store_resp_idx_T_451 = eq(rob[18].cmd, UInt<1>(0h1)) node _store_resp_idx_T_452 = eq(rob[18].cmd, UInt<5>(0h11)) node _store_resp_idx_T_453 = or(_store_resp_idx_T_451, _store_resp_idx_T_452) node _store_resp_idx_T_454 = eq(rob[18].cmd, UInt<3>(0h7)) node _store_resp_idx_T_455 = or(_store_resp_idx_T_453, _store_resp_idx_T_454) node _store_resp_idx_T_456 = eq(rob[18].cmd, UInt<3>(0h4)) node _store_resp_idx_T_457 = eq(rob[18].cmd, UInt<4>(0h9)) node _store_resp_idx_T_458 = eq(rob[18].cmd, UInt<4>(0ha)) node _store_resp_idx_T_459 = eq(rob[18].cmd, UInt<4>(0hb)) node _store_resp_idx_T_460 = or(_store_resp_idx_T_456, _store_resp_idx_T_457) node _store_resp_idx_T_461 = or(_store_resp_idx_T_460, _store_resp_idx_T_458) node _store_resp_idx_T_462 = or(_store_resp_idx_T_461, _store_resp_idx_T_459) node _store_resp_idx_T_463 = eq(rob[18].cmd, UInt<4>(0h8)) node _store_resp_idx_T_464 = eq(rob[18].cmd, UInt<4>(0hc)) node _store_resp_idx_T_465 = eq(rob[18].cmd, UInt<4>(0hd)) node _store_resp_idx_T_466 = eq(rob[18].cmd, UInt<4>(0he)) node _store_resp_idx_T_467 = eq(rob[18].cmd, UInt<4>(0hf)) node _store_resp_idx_T_468 = or(_store_resp_idx_T_463, _store_resp_idx_T_464) node _store_resp_idx_T_469 = or(_store_resp_idx_T_468, _store_resp_idx_T_465) node _store_resp_idx_T_470 = or(_store_resp_idx_T_469, _store_resp_idx_T_466) node _store_resp_idx_T_471 = or(_store_resp_idx_T_470, _store_resp_idx_T_467) node _store_resp_idx_T_472 = or(_store_resp_idx_T_462, _store_resp_idx_T_471) node _store_resp_idx_T_473 = or(_store_resp_idx_T_455, _store_resp_idx_T_472) node _store_resp_idx_T_474 = and(_store_resp_idx_T_450, _store_resp_idx_T_473) node _store_resp_idx_T_475 = eq(rob_respd[19], UInt<1>(0h0)) node _store_resp_idx_T_476 = eq(rob[19].cmd, UInt<1>(0h1)) node _store_resp_idx_T_477 = eq(rob[19].cmd, UInt<5>(0h11)) node _store_resp_idx_T_478 = or(_store_resp_idx_T_476, _store_resp_idx_T_477) node _store_resp_idx_T_479 = eq(rob[19].cmd, UInt<3>(0h7)) node _store_resp_idx_T_480 = or(_store_resp_idx_T_478, _store_resp_idx_T_479) node _store_resp_idx_T_481 = eq(rob[19].cmd, UInt<3>(0h4)) node _store_resp_idx_T_482 = eq(rob[19].cmd, UInt<4>(0h9)) node _store_resp_idx_T_483 = eq(rob[19].cmd, UInt<4>(0ha)) node _store_resp_idx_T_484 = eq(rob[19].cmd, UInt<4>(0hb)) node _store_resp_idx_T_485 = or(_store_resp_idx_T_481, _store_resp_idx_T_482) node _store_resp_idx_T_486 = or(_store_resp_idx_T_485, _store_resp_idx_T_483) node _store_resp_idx_T_487 = or(_store_resp_idx_T_486, _store_resp_idx_T_484) node _store_resp_idx_T_488 = eq(rob[19].cmd, UInt<4>(0h8)) node _store_resp_idx_T_489 = eq(rob[19].cmd, UInt<4>(0hc)) node _store_resp_idx_T_490 = eq(rob[19].cmd, UInt<4>(0hd)) node _store_resp_idx_T_491 = eq(rob[19].cmd, UInt<4>(0he)) node _store_resp_idx_T_492 = eq(rob[19].cmd, UInt<4>(0hf)) node _store_resp_idx_T_493 = or(_store_resp_idx_T_488, _store_resp_idx_T_489) node _store_resp_idx_T_494 = or(_store_resp_idx_T_493, _store_resp_idx_T_490) node _store_resp_idx_T_495 = or(_store_resp_idx_T_494, _store_resp_idx_T_491) node _store_resp_idx_T_496 = or(_store_resp_idx_T_495, _store_resp_idx_T_492) node _store_resp_idx_T_497 = or(_store_resp_idx_T_487, _store_resp_idx_T_496) node _store_resp_idx_T_498 = or(_store_resp_idx_T_480, _store_resp_idx_T_497) node _store_resp_idx_T_499 = and(_store_resp_idx_T_475, _store_resp_idx_T_498) node _store_resp_idx_T_500 = eq(rob_respd[20], UInt<1>(0h0)) node _store_resp_idx_T_501 = eq(rob[20].cmd, UInt<1>(0h1)) node _store_resp_idx_T_502 = eq(rob[20].cmd, UInt<5>(0h11)) node _store_resp_idx_T_503 = or(_store_resp_idx_T_501, _store_resp_idx_T_502) node _store_resp_idx_T_504 = eq(rob[20].cmd, UInt<3>(0h7)) node _store_resp_idx_T_505 = or(_store_resp_idx_T_503, _store_resp_idx_T_504) node _store_resp_idx_T_506 = eq(rob[20].cmd, UInt<3>(0h4)) node _store_resp_idx_T_507 = eq(rob[20].cmd, UInt<4>(0h9)) node _store_resp_idx_T_508 = eq(rob[20].cmd, UInt<4>(0ha)) node _store_resp_idx_T_509 = eq(rob[20].cmd, UInt<4>(0hb)) node _store_resp_idx_T_510 = or(_store_resp_idx_T_506, _store_resp_idx_T_507) node _store_resp_idx_T_511 = or(_store_resp_idx_T_510, _store_resp_idx_T_508) node _store_resp_idx_T_512 = or(_store_resp_idx_T_511, _store_resp_idx_T_509) node _store_resp_idx_T_513 = eq(rob[20].cmd, UInt<4>(0h8)) node _store_resp_idx_T_514 = eq(rob[20].cmd, UInt<4>(0hc)) node _store_resp_idx_T_515 = eq(rob[20].cmd, UInt<4>(0hd)) node _store_resp_idx_T_516 = eq(rob[20].cmd, UInt<4>(0he)) node _store_resp_idx_T_517 = eq(rob[20].cmd, UInt<4>(0hf)) node _store_resp_idx_T_518 = or(_store_resp_idx_T_513, _store_resp_idx_T_514) node _store_resp_idx_T_519 = or(_store_resp_idx_T_518, _store_resp_idx_T_515) node _store_resp_idx_T_520 = or(_store_resp_idx_T_519, _store_resp_idx_T_516) node _store_resp_idx_T_521 = or(_store_resp_idx_T_520, _store_resp_idx_T_517) node _store_resp_idx_T_522 = or(_store_resp_idx_T_512, _store_resp_idx_T_521) node _store_resp_idx_T_523 = or(_store_resp_idx_T_505, _store_resp_idx_T_522) node _store_resp_idx_T_524 = and(_store_resp_idx_T_500, _store_resp_idx_T_523) node _store_resp_idx_T_525 = eq(rob_respd[21], UInt<1>(0h0)) node _store_resp_idx_T_526 = eq(rob[21].cmd, UInt<1>(0h1)) node _store_resp_idx_T_527 = eq(rob[21].cmd, UInt<5>(0h11)) node _store_resp_idx_T_528 = or(_store_resp_idx_T_526, _store_resp_idx_T_527) node _store_resp_idx_T_529 = eq(rob[21].cmd, UInt<3>(0h7)) node _store_resp_idx_T_530 = or(_store_resp_idx_T_528, _store_resp_idx_T_529) node _store_resp_idx_T_531 = eq(rob[21].cmd, UInt<3>(0h4)) node _store_resp_idx_T_532 = eq(rob[21].cmd, UInt<4>(0h9)) node _store_resp_idx_T_533 = eq(rob[21].cmd, UInt<4>(0ha)) node _store_resp_idx_T_534 = eq(rob[21].cmd, UInt<4>(0hb)) node _store_resp_idx_T_535 = or(_store_resp_idx_T_531, _store_resp_idx_T_532) node _store_resp_idx_T_536 = or(_store_resp_idx_T_535, _store_resp_idx_T_533) node _store_resp_idx_T_537 = or(_store_resp_idx_T_536, _store_resp_idx_T_534) node _store_resp_idx_T_538 = eq(rob[21].cmd, UInt<4>(0h8)) node _store_resp_idx_T_539 = eq(rob[21].cmd, UInt<4>(0hc)) node _store_resp_idx_T_540 = eq(rob[21].cmd, UInt<4>(0hd)) node _store_resp_idx_T_541 = eq(rob[21].cmd, UInt<4>(0he)) node _store_resp_idx_T_542 = eq(rob[21].cmd, UInt<4>(0hf)) node _store_resp_idx_T_543 = or(_store_resp_idx_T_538, _store_resp_idx_T_539) node _store_resp_idx_T_544 = or(_store_resp_idx_T_543, _store_resp_idx_T_540) node _store_resp_idx_T_545 = or(_store_resp_idx_T_544, _store_resp_idx_T_541) node _store_resp_idx_T_546 = or(_store_resp_idx_T_545, _store_resp_idx_T_542) node _store_resp_idx_T_547 = or(_store_resp_idx_T_537, _store_resp_idx_T_546) node _store_resp_idx_T_548 = or(_store_resp_idx_T_530, _store_resp_idx_T_547) node _store_resp_idx_T_549 = and(_store_resp_idx_T_525, _store_resp_idx_T_548) node _store_resp_idx_T_550 = eq(rob_respd[22], UInt<1>(0h0)) node _store_resp_idx_T_551 = eq(rob[22].cmd, UInt<1>(0h1)) node _store_resp_idx_T_552 = eq(rob[22].cmd, UInt<5>(0h11)) node _store_resp_idx_T_553 = or(_store_resp_idx_T_551, _store_resp_idx_T_552) node _store_resp_idx_T_554 = eq(rob[22].cmd, UInt<3>(0h7)) node _store_resp_idx_T_555 = or(_store_resp_idx_T_553, _store_resp_idx_T_554) node _store_resp_idx_T_556 = eq(rob[22].cmd, UInt<3>(0h4)) node _store_resp_idx_T_557 = eq(rob[22].cmd, UInt<4>(0h9)) node _store_resp_idx_T_558 = eq(rob[22].cmd, UInt<4>(0ha)) node _store_resp_idx_T_559 = eq(rob[22].cmd, UInt<4>(0hb)) node _store_resp_idx_T_560 = or(_store_resp_idx_T_556, _store_resp_idx_T_557) node _store_resp_idx_T_561 = or(_store_resp_idx_T_560, _store_resp_idx_T_558) node _store_resp_idx_T_562 = or(_store_resp_idx_T_561, _store_resp_idx_T_559) node _store_resp_idx_T_563 = eq(rob[22].cmd, UInt<4>(0h8)) node _store_resp_idx_T_564 = eq(rob[22].cmd, UInt<4>(0hc)) node _store_resp_idx_T_565 = eq(rob[22].cmd, UInt<4>(0hd)) node _store_resp_idx_T_566 = eq(rob[22].cmd, UInt<4>(0he)) node _store_resp_idx_T_567 = eq(rob[22].cmd, UInt<4>(0hf)) node _store_resp_idx_T_568 = or(_store_resp_idx_T_563, _store_resp_idx_T_564) node _store_resp_idx_T_569 = or(_store_resp_idx_T_568, _store_resp_idx_T_565) node _store_resp_idx_T_570 = or(_store_resp_idx_T_569, _store_resp_idx_T_566) node _store_resp_idx_T_571 = or(_store_resp_idx_T_570, _store_resp_idx_T_567) node _store_resp_idx_T_572 = or(_store_resp_idx_T_562, _store_resp_idx_T_571) node _store_resp_idx_T_573 = or(_store_resp_idx_T_555, _store_resp_idx_T_572) node _store_resp_idx_T_574 = and(_store_resp_idx_T_550, _store_resp_idx_T_573) node _store_resp_idx_T_575 = eq(rob_respd[23], UInt<1>(0h0)) node _store_resp_idx_T_576 = eq(rob[23].cmd, UInt<1>(0h1)) node _store_resp_idx_T_577 = eq(rob[23].cmd, UInt<5>(0h11)) node _store_resp_idx_T_578 = or(_store_resp_idx_T_576, _store_resp_idx_T_577) node _store_resp_idx_T_579 = eq(rob[23].cmd, UInt<3>(0h7)) node _store_resp_idx_T_580 = or(_store_resp_idx_T_578, _store_resp_idx_T_579) node _store_resp_idx_T_581 = eq(rob[23].cmd, UInt<3>(0h4)) node _store_resp_idx_T_582 = eq(rob[23].cmd, UInt<4>(0h9)) node _store_resp_idx_T_583 = eq(rob[23].cmd, UInt<4>(0ha)) node _store_resp_idx_T_584 = eq(rob[23].cmd, UInt<4>(0hb)) node _store_resp_idx_T_585 = or(_store_resp_idx_T_581, _store_resp_idx_T_582) node _store_resp_idx_T_586 = or(_store_resp_idx_T_585, _store_resp_idx_T_583) node _store_resp_idx_T_587 = or(_store_resp_idx_T_586, _store_resp_idx_T_584) node _store_resp_idx_T_588 = eq(rob[23].cmd, UInt<4>(0h8)) node _store_resp_idx_T_589 = eq(rob[23].cmd, UInt<4>(0hc)) node _store_resp_idx_T_590 = eq(rob[23].cmd, UInt<4>(0hd)) node _store_resp_idx_T_591 = eq(rob[23].cmd, UInt<4>(0he)) node _store_resp_idx_T_592 = eq(rob[23].cmd, UInt<4>(0hf)) node _store_resp_idx_T_593 = or(_store_resp_idx_T_588, _store_resp_idx_T_589) node _store_resp_idx_T_594 = or(_store_resp_idx_T_593, _store_resp_idx_T_590) node _store_resp_idx_T_595 = or(_store_resp_idx_T_594, _store_resp_idx_T_591) node _store_resp_idx_T_596 = or(_store_resp_idx_T_595, _store_resp_idx_T_592) node _store_resp_idx_T_597 = or(_store_resp_idx_T_587, _store_resp_idx_T_596) node _store_resp_idx_T_598 = or(_store_resp_idx_T_580, _store_resp_idx_T_597) node _store_resp_idx_T_599 = and(_store_resp_idx_T_575, _store_resp_idx_T_598) node _store_resp_idx_T_600 = eq(rob_respd[24], UInt<1>(0h0)) node _store_resp_idx_T_601 = eq(rob[24].cmd, UInt<1>(0h1)) node _store_resp_idx_T_602 = eq(rob[24].cmd, UInt<5>(0h11)) node _store_resp_idx_T_603 = or(_store_resp_idx_T_601, _store_resp_idx_T_602) node _store_resp_idx_T_604 = eq(rob[24].cmd, UInt<3>(0h7)) node _store_resp_idx_T_605 = or(_store_resp_idx_T_603, _store_resp_idx_T_604) node _store_resp_idx_T_606 = eq(rob[24].cmd, UInt<3>(0h4)) node _store_resp_idx_T_607 = eq(rob[24].cmd, UInt<4>(0h9)) node _store_resp_idx_T_608 = eq(rob[24].cmd, UInt<4>(0ha)) node _store_resp_idx_T_609 = eq(rob[24].cmd, UInt<4>(0hb)) node _store_resp_idx_T_610 = or(_store_resp_idx_T_606, _store_resp_idx_T_607) node _store_resp_idx_T_611 = or(_store_resp_idx_T_610, _store_resp_idx_T_608) node _store_resp_idx_T_612 = or(_store_resp_idx_T_611, _store_resp_idx_T_609) node _store_resp_idx_T_613 = eq(rob[24].cmd, UInt<4>(0h8)) node _store_resp_idx_T_614 = eq(rob[24].cmd, UInt<4>(0hc)) node _store_resp_idx_T_615 = eq(rob[24].cmd, UInt<4>(0hd)) node _store_resp_idx_T_616 = eq(rob[24].cmd, UInt<4>(0he)) node _store_resp_idx_T_617 = eq(rob[24].cmd, UInt<4>(0hf)) node _store_resp_idx_T_618 = or(_store_resp_idx_T_613, _store_resp_idx_T_614) node _store_resp_idx_T_619 = or(_store_resp_idx_T_618, _store_resp_idx_T_615) node _store_resp_idx_T_620 = or(_store_resp_idx_T_619, _store_resp_idx_T_616) node _store_resp_idx_T_621 = or(_store_resp_idx_T_620, _store_resp_idx_T_617) node _store_resp_idx_T_622 = or(_store_resp_idx_T_612, _store_resp_idx_T_621) node _store_resp_idx_T_623 = or(_store_resp_idx_T_605, _store_resp_idx_T_622) node _store_resp_idx_T_624 = and(_store_resp_idx_T_600, _store_resp_idx_T_623) node _store_resp_idx_T_625 = eq(rob_respd[25], UInt<1>(0h0)) node _store_resp_idx_T_626 = eq(rob[25].cmd, UInt<1>(0h1)) node _store_resp_idx_T_627 = eq(rob[25].cmd, UInt<5>(0h11)) node _store_resp_idx_T_628 = or(_store_resp_idx_T_626, _store_resp_idx_T_627) node _store_resp_idx_T_629 = eq(rob[25].cmd, UInt<3>(0h7)) node _store_resp_idx_T_630 = or(_store_resp_idx_T_628, _store_resp_idx_T_629) node _store_resp_idx_T_631 = eq(rob[25].cmd, UInt<3>(0h4)) node _store_resp_idx_T_632 = eq(rob[25].cmd, UInt<4>(0h9)) node _store_resp_idx_T_633 = eq(rob[25].cmd, UInt<4>(0ha)) node _store_resp_idx_T_634 = eq(rob[25].cmd, UInt<4>(0hb)) node _store_resp_idx_T_635 = or(_store_resp_idx_T_631, _store_resp_idx_T_632) node _store_resp_idx_T_636 = or(_store_resp_idx_T_635, _store_resp_idx_T_633) node _store_resp_idx_T_637 = or(_store_resp_idx_T_636, _store_resp_idx_T_634) node _store_resp_idx_T_638 = eq(rob[25].cmd, UInt<4>(0h8)) node _store_resp_idx_T_639 = eq(rob[25].cmd, UInt<4>(0hc)) node _store_resp_idx_T_640 = eq(rob[25].cmd, UInt<4>(0hd)) node _store_resp_idx_T_641 = eq(rob[25].cmd, UInt<4>(0he)) node _store_resp_idx_T_642 = eq(rob[25].cmd, UInt<4>(0hf)) node _store_resp_idx_T_643 = or(_store_resp_idx_T_638, _store_resp_idx_T_639) node _store_resp_idx_T_644 = or(_store_resp_idx_T_643, _store_resp_idx_T_640) node _store_resp_idx_T_645 = or(_store_resp_idx_T_644, _store_resp_idx_T_641) node _store_resp_idx_T_646 = or(_store_resp_idx_T_645, _store_resp_idx_T_642) node _store_resp_idx_T_647 = or(_store_resp_idx_T_637, _store_resp_idx_T_646) node _store_resp_idx_T_648 = or(_store_resp_idx_T_630, _store_resp_idx_T_647) node _store_resp_idx_T_649 = and(_store_resp_idx_T_625, _store_resp_idx_T_648) node _store_resp_idx_T_650 = eq(rob_respd[26], UInt<1>(0h0)) node _store_resp_idx_T_651 = eq(rob[26].cmd, UInt<1>(0h1)) node _store_resp_idx_T_652 = eq(rob[26].cmd, UInt<5>(0h11)) node _store_resp_idx_T_653 = or(_store_resp_idx_T_651, _store_resp_idx_T_652) node _store_resp_idx_T_654 = eq(rob[26].cmd, UInt<3>(0h7)) node _store_resp_idx_T_655 = or(_store_resp_idx_T_653, _store_resp_idx_T_654) node _store_resp_idx_T_656 = eq(rob[26].cmd, UInt<3>(0h4)) node _store_resp_idx_T_657 = eq(rob[26].cmd, UInt<4>(0h9)) node _store_resp_idx_T_658 = eq(rob[26].cmd, UInt<4>(0ha)) node _store_resp_idx_T_659 = eq(rob[26].cmd, UInt<4>(0hb)) node _store_resp_idx_T_660 = or(_store_resp_idx_T_656, _store_resp_idx_T_657) node _store_resp_idx_T_661 = or(_store_resp_idx_T_660, _store_resp_idx_T_658) node _store_resp_idx_T_662 = or(_store_resp_idx_T_661, _store_resp_idx_T_659) node _store_resp_idx_T_663 = eq(rob[26].cmd, UInt<4>(0h8)) node _store_resp_idx_T_664 = eq(rob[26].cmd, UInt<4>(0hc)) node _store_resp_idx_T_665 = eq(rob[26].cmd, UInt<4>(0hd)) node _store_resp_idx_T_666 = eq(rob[26].cmd, UInt<4>(0he)) node _store_resp_idx_T_667 = eq(rob[26].cmd, UInt<4>(0hf)) node _store_resp_idx_T_668 = or(_store_resp_idx_T_663, _store_resp_idx_T_664) node _store_resp_idx_T_669 = or(_store_resp_idx_T_668, _store_resp_idx_T_665) node _store_resp_idx_T_670 = or(_store_resp_idx_T_669, _store_resp_idx_T_666) node _store_resp_idx_T_671 = or(_store_resp_idx_T_670, _store_resp_idx_T_667) node _store_resp_idx_T_672 = or(_store_resp_idx_T_662, _store_resp_idx_T_671) node _store_resp_idx_T_673 = or(_store_resp_idx_T_655, _store_resp_idx_T_672) node _store_resp_idx_T_674 = and(_store_resp_idx_T_650, _store_resp_idx_T_673) node _store_resp_idx_T_675 = eq(rob_respd[27], UInt<1>(0h0)) node _store_resp_idx_T_676 = eq(rob[27].cmd, UInt<1>(0h1)) node _store_resp_idx_T_677 = eq(rob[27].cmd, UInt<5>(0h11)) node _store_resp_idx_T_678 = or(_store_resp_idx_T_676, _store_resp_idx_T_677) node _store_resp_idx_T_679 = eq(rob[27].cmd, UInt<3>(0h7)) node _store_resp_idx_T_680 = or(_store_resp_idx_T_678, _store_resp_idx_T_679) node _store_resp_idx_T_681 = eq(rob[27].cmd, UInt<3>(0h4)) node _store_resp_idx_T_682 = eq(rob[27].cmd, UInt<4>(0h9)) node _store_resp_idx_T_683 = eq(rob[27].cmd, UInt<4>(0ha)) node _store_resp_idx_T_684 = eq(rob[27].cmd, UInt<4>(0hb)) node _store_resp_idx_T_685 = or(_store_resp_idx_T_681, _store_resp_idx_T_682) node _store_resp_idx_T_686 = or(_store_resp_idx_T_685, _store_resp_idx_T_683) node _store_resp_idx_T_687 = or(_store_resp_idx_T_686, _store_resp_idx_T_684) node _store_resp_idx_T_688 = eq(rob[27].cmd, UInt<4>(0h8)) node _store_resp_idx_T_689 = eq(rob[27].cmd, UInt<4>(0hc)) node _store_resp_idx_T_690 = eq(rob[27].cmd, UInt<4>(0hd)) node _store_resp_idx_T_691 = eq(rob[27].cmd, UInt<4>(0he)) node _store_resp_idx_T_692 = eq(rob[27].cmd, UInt<4>(0hf)) node _store_resp_idx_T_693 = or(_store_resp_idx_T_688, _store_resp_idx_T_689) node _store_resp_idx_T_694 = or(_store_resp_idx_T_693, _store_resp_idx_T_690) node _store_resp_idx_T_695 = or(_store_resp_idx_T_694, _store_resp_idx_T_691) node _store_resp_idx_T_696 = or(_store_resp_idx_T_695, _store_resp_idx_T_692) node _store_resp_idx_T_697 = or(_store_resp_idx_T_687, _store_resp_idx_T_696) node _store_resp_idx_T_698 = or(_store_resp_idx_T_680, _store_resp_idx_T_697) node _store_resp_idx_T_699 = and(_store_resp_idx_T_675, _store_resp_idx_T_698) node _store_resp_idx_T_700 = eq(rob_respd[28], UInt<1>(0h0)) node _store_resp_idx_T_701 = eq(rob[28].cmd, UInt<1>(0h1)) node _store_resp_idx_T_702 = eq(rob[28].cmd, UInt<5>(0h11)) node _store_resp_idx_T_703 = or(_store_resp_idx_T_701, _store_resp_idx_T_702) node _store_resp_idx_T_704 = eq(rob[28].cmd, UInt<3>(0h7)) node _store_resp_idx_T_705 = or(_store_resp_idx_T_703, _store_resp_idx_T_704) node _store_resp_idx_T_706 = eq(rob[28].cmd, UInt<3>(0h4)) node _store_resp_idx_T_707 = eq(rob[28].cmd, UInt<4>(0h9)) node _store_resp_idx_T_708 = eq(rob[28].cmd, UInt<4>(0ha)) node _store_resp_idx_T_709 = eq(rob[28].cmd, UInt<4>(0hb)) node _store_resp_idx_T_710 = or(_store_resp_idx_T_706, _store_resp_idx_T_707) node _store_resp_idx_T_711 = or(_store_resp_idx_T_710, _store_resp_idx_T_708) node _store_resp_idx_T_712 = or(_store_resp_idx_T_711, _store_resp_idx_T_709) node _store_resp_idx_T_713 = eq(rob[28].cmd, UInt<4>(0h8)) node _store_resp_idx_T_714 = eq(rob[28].cmd, UInt<4>(0hc)) node _store_resp_idx_T_715 = eq(rob[28].cmd, UInt<4>(0hd)) node _store_resp_idx_T_716 = eq(rob[28].cmd, UInt<4>(0he)) node _store_resp_idx_T_717 = eq(rob[28].cmd, UInt<4>(0hf)) node _store_resp_idx_T_718 = or(_store_resp_idx_T_713, _store_resp_idx_T_714) node _store_resp_idx_T_719 = or(_store_resp_idx_T_718, _store_resp_idx_T_715) node _store_resp_idx_T_720 = or(_store_resp_idx_T_719, _store_resp_idx_T_716) node _store_resp_idx_T_721 = or(_store_resp_idx_T_720, _store_resp_idx_T_717) node _store_resp_idx_T_722 = or(_store_resp_idx_T_712, _store_resp_idx_T_721) node _store_resp_idx_T_723 = or(_store_resp_idx_T_705, _store_resp_idx_T_722) node _store_resp_idx_T_724 = and(_store_resp_idx_T_700, _store_resp_idx_T_723) node _store_resp_idx_T_725 = eq(rob_respd[29], UInt<1>(0h0)) node _store_resp_idx_T_726 = eq(rob[29].cmd, UInt<1>(0h1)) node _store_resp_idx_T_727 = eq(rob[29].cmd, UInt<5>(0h11)) node _store_resp_idx_T_728 = or(_store_resp_idx_T_726, _store_resp_idx_T_727) node _store_resp_idx_T_729 = eq(rob[29].cmd, UInt<3>(0h7)) node _store_resp_idx_T_730 = or(_store_resp_idx_T_728, _store_resp_idx_T_729) node _store_resp_idx_T_731 = eq(rob[29].cmd, UInt<3>(0h4)) node _store_resp_idx_T_732 = eq(rob[29].cmd, UInt<4>(0h9)) node _store_resp_idx_T_733 = eq(rob[29].cmd, UInt<4>(0ha)) node _store_resp_idx_T_734 = eq(rob[29].cmd, UInt<4>(0hb)) node _store_resp_idx_T_735 = or(_store_resp_idx_T_731, _store_resp_idx_T_732) node _store_resp_idx_T_736 = or(_store_resp_idx_T_735, _store_resp_idx_T_733) node _store_resp_idx_T_737 = or(_store_resp_idx_T_736, _store_resp_idx_T_734) node _store_resp_idx_T_738 = eq(rob[29].cmd, UInt<4>(0h8)) node _store_resp_idx_T_739 = eq(rob[29].cmd, UInt<4>(0hc)) node _store_resp_idx_T_740 = eq(rob[29].cmd, UInt<4>(0hd)) node _store_resp_idx_T_741 = eq(rob[29].cmd, UInt<4>(0he)) node _store_resp_idx_T_742 = eq(rob[29].cmd, UInt<4>(0hf)) node _store_resp_idx_T_743 = or(_store_resp_idx_T_738, _store_resp_idx_T_739) node _store_resp_idx_T_744 = or(_store_resp_idx_T_743, _store_resp_idx_T_740) node _store_resp_idx_T_745 = or(_store_resp_idx_T_744, _store_resp_idx_T_741) node _store_resp_idx_T_746 = or(_store_resp_idx_T_745, _store_resp_idx_T_742) node _store_resp_idx_T_747 = or(_store_resp_idx_T_737, _store_resp_idx_T_746) node _store_resp_idx_T_748 = or(_store_resp_idx_T_730, _store_resp_idx_T_747) node _store_resp_idx_T_749 = and(_store_resp_idx_T_725, _store_resp_idx_T_748) node _store_resp_idx_T_750 = eq(rob_respd[30], UInt<1>(0h0)) node _store_resp_idx_T_751 = eq(rob[30].cmd, UInt<1>(0h1)) node _store_resp_idx_T_752 = eq(rob[30].cmd, UInt<5>(0h11)) node _store_resp_idx_T_753 = or(_store_resp_idx_T_751, _store_resp_idx_T_752) node _store_resp_idx_T_754 = eq(rob[30].cmd, UInt<3>(0h7)) node _store_resp_idx_T_755 = or(_store_resp_idx_T_753, _store_resp_idx_T_754) node _store_resp_idx_T_756 = eq(rob[30].cmd, UInt<3>(0h4)) node _store_resp_idx_T_757 = eq(rob[30].cmd, UInt<4>(0h9)) node _store_resp_idx_T_758 = eq(rob[30].cmd, UInt<4>(0ha)) node _store_resp_idx_T_759 = eq(rob[30].cmd, UInt<4>(0hb)) node _store_resp_idx_T_760 = or(_store_resp_idx_T_756, _store_resp_idx_T_757) node _store_resp_idx_T_761 = or(_store_resp_idx_T_760, _store_resp_idx_T_758) node _store_resp_idx_T_762 = or(_store_resp_idx_T_761, _store_resp_idx_T_759) node _store_resp_idx_T_763 = eq(rob[30].cmd, UInt<4>(0h8)) node _store_resp_idx_T_764 = eq(rob[30].cmd, UInt<4>(0hc)) node _store_resp_idx_T_765 = eq(rob[30].cmd, UInt<4>(0hd)) node _store_resp_idx_T_766 = eq(rob[30].cmd, UInt<4>(0he)) node _store_resp_idx_T_767 = eq(rob[30].cmd, UInt<4>(0hf)) node _store_resp_idx_T_768 = or(_store_resp_idx_T_763, _store_resp_idx_T_764) node _store_resp_idx_T_769 = or(_store_resp_idx_T_768, _store_resp_idx_T_765) node _store_resp_idx_T_770 = or(_store_resp_idx_T_769, _store_resp_idx_T_766) node _store_resp_idx_T_771 = or(_store_resp_idx_T_770, _store_resp_idx_T_767) node _store_resp_idx_T_772 = or(_store_resp_idx_T_762, _store_resp_idx_T_771) node _store_resp_idx_T_773 = or(_store_resp_idx_T_755, _store_resp_idx_T_772) node _store_resp_idx_T_774 = and(_store_resp_idx_T_750, _store_resp_idx_T_773) node _store_resp_idx_T_775 = eq(rob_respd[31], UInt<1>(0h0)) node _store_resp_idx_T_776 = eq(rob[31].cmd, UInt<1>(0h1)) node _store_resp_idx_T_777 = eq(rob[31].cmd, UInt<5>(0h11)) node _store_resp_idx_T_778 = or(_store_resp_idx_T_776, _store_resp_idx_T_777) node _store_resp_idx_T_779 = eq(rob[31].cmd, UInt<3>(0h7)) node _store_resp_idx_T_780 = or(_store_resp_idx_T_778, _store_resp_idx_T_779) node _store_resp_idx_T_781 = eq(rob[31].cmd, UInt<3>(0h4)) node _store_resp_idx_T_782 = eq(rob[31].cmd, UInt<4>(0h9)) node _store_resp_idx_T_783 = eq(rob[31].cmd, UInt<4>(0ha)) node _store_resp_idx_T_784 = eq(rob[31].cmd, UInt<4>(0hb)) node _store_resp_idx_T_785 = or(_store_resp_idx_T_781, _store_resp_idx_T_782) node _store_resp_idx_T_786 = or(_store_resp_idx_T_785, _store_resp_idx_T_783) node _store_resp_idx_T_787 = or(_store_resp_idx_T_786, _store_resp_idx_T_784) node _store_resp_idx_T_788 = eq(rob[31].cmd, UInt<4>(0h8)) node _store_resp_idx_T_789 = eq(rob[31].cmd, UInt<4>(0hc)) node _store_resp_idx_T_790 = eq(rob[31].cmd, UInt<4>(0hd)) node _store_resp_idx_T_791 = eq(rob[31].cmd, UInt<4>(0he)) node _store_resp_idx_T_792 = eq(rob[31].cmd, UInt<4>(0hf)) node _store_resp_idx_T_793 = or(_store_resp_idx_T_788, _store_resp_idx_T_789) node _store_resp_idx_T_794 = or(_store_resp_idx_T_793, _store_resp_idx_T_790) node _store_resp_idx_T_795 = or(_store_resp_idx_T_794, _store_resp_idx_T_791) node _store_resp_idx_T_796 = or(_store_resp_idx_T_795, _store_resp_idx_T_792) node _store_resp_idx_T_797 = or(_store_resp_idx_T_787, _store_resp_idx_T_796) node _store_resp_idx_T_798 = or(_store_resp_idx_T_780, _store_resp_idx_T_797) node _store_resp_idx_T_799 = and(_store_resp_idx_T_775, _store_resp_idx_T_798) node _store_resp_idx_T_800 = eq(rob_respd[32], UInt<1>(0h0)) node _store_resp_idx_T_801 = eq(rob[32].cmd, UInt<1>(0h1)) node _store_resp_idx_T_802 = eq(rob[32].cmd, UInt<5>(0h11)) node _store_resp_idx_T_803 = or(_store_resp_idx_T_801, _store_resp_idx_T_802) node _store_resp_idx_T_804 = eq(rob[32].cmd, UInt<3>(0h7)) node _store_resp_idx_T_805 = or(_store_resp_idx_T_803, _store_resp_idx_T_804) node _store_resp_idx_T_806 = eq(rob[32].cmd, UInt<3>(0h4)) node _store_resp_idx_T_807 = eq(rob[32].cmd, UInt<4>(0h9)) node _store_resp_idx_T_808 = eq(rob[32].cmd, UInt<4>(0ha)) node _store_resp_idx_T_809 = eq(rob[32].cmd, UInt<4>(0hb)) node _store_resp_idx_T_810 = or(_store_resp_idx_T_806, _store_resp_idx_T_807) node _store_resp_idx_T_811 = or(_store_resp_idx_T_810, _store_resp_idx_T_808) node _store_resp_idx_T_812 = or(_store_resp_idx_T_811, _store_resp_idx_T_809) node _store_resp_idx_T_813 = eq(rob[32].cmd, UInt<4>(0h8)) node _store_resp_idx_T_814 = eq(rob[32].cmd, UInt<4>(0hc)) node _store_resp_idx_T_815 = eq(rob[32].cmd, UInt<4>(0hd)) node _store_resp_idx_T_816 = eq(rob[32].cmd, UInt<4>(0he)) node _store_resp_idx_T_817 = eq(rob[32].cmd, UInt<4>(0hf)) node _store_resp_idx_T_818 = or(_store_resp_idx_T_813, _store_resp_idx_T_814) node _store_resp_idx_T_819 = or(_store_resp_idx_T_818, _store_resp_idx_T_815) node _store_resp_idx_T_820 = or(_store_resp_idx_T_819, _store_resp_idx_T_816) node _store_resp_idx_T_821 = or(_store_resp_idx_T_820, _store_resp_idx_T_817) node _store_resp_idx_T_822 = or(_store_resp_idx_T_812, _store_resp_idx_T_821) node _store_resp_idx_T_823 = or(_store_resp_idx_T_805, _store_resp_idx_T_822) node _store_resp_idx_T_824 = and(_store_resp_idx_T_800, _store_resp_idx_T_823) node _store_resp_idx_T_825 = eq(rob_respd[33], UInt<1>(0h0)) node _store_resp_idx_T_826 = eq(rob[33].cmd, UInt<1>(0h1)) node _store_resp_idx_T_827 = eq(rob[33].cmd, UInt<5>(0h11)) node _store_resp_idx_T_828 = or(_store_resp_idx_T_826, _store_resp_idx_T_827) node _store_resp_idx_T_829 = eq(rob[33].cmd, UInt<3>(0h7)) node _store_resp_idx_T_830 = or(_store_resp_idx_T_828, _store_resp_idx_T_829) node _store_resp_idx_T_831 = eq(rob[33].cmd, UInt<3>(0h4)) node _store_resp_idx_T_832 = eq(rob[33].cmd, UInt<4>(0h9)) node _store_resp_idx_T_833 = eq(rob[33].cmd, UInt<4>(0ha)) node _store_resp_idx_T_834 = eq(rob[33].cmd, UInt<4>(0hb)) node _store_resp_idx_T_835 = or(_store_resp_idx_T_831, _store_resp_idx_T_832) node _store_resp_idx_T_836 = or(_store_resp_idx_T_835, _store_resp_idx_T_833) node _store_resp_idx_T_837 = or(_store_resp_idx_T_836, _store_resp_idx_T_834) node _store_resp_idx_T_838 = eq(rob[33].cmd, UInt<4>(0h8)) node _store_resp_idx_T_839 = eq(rob[33].cmd, UInt<4>(0hc)) node _store_resp_idx_T_840 = eq(rob[33].cmd, UInt<4>(0hd)) node _store_resp_idx_T_841 = eq(rob[33].cmd, UInt<4>(0he)) node _store_resp_idx_T_842 = eq(rob[33].cmd, UInt<4>(0hf)) node _store_resp_idx_T_843 = or(_store_resp_idx_T_838, _store_resp_idx_T_839) node _store_resp_idx_T_844 = or(_store_resp_idx_T_843, _store_resp_idx_T_840) node _store_resp_idx_T_845 = or(_store_resp_idx_T_844, _store_resp_idx_T_841) node _store_resp_idx_T_846 = or(_store_resp_idx_T_845, _store_resp_idx_T_842) node _store_resp_idx_T_847 = or(_store_resp_idx_T_837, _store_resp_idx_T_846) node _store_resp_idx_T_848 = or(_store_resp_idx_T_830, _store_resp_idx_T_847) node _store_resp_idx_T_849 = and(_store_resp_idx_T_825, _store_resp_idx_T_848) node _store_resp_idx_T_850 = eq(rob_respd[34], UInt<1>(0h0)) node _store_resp_idx_T_851 = eq(rob[34].cmd, UInt<1>(0h1)) node _store_resp_idx_T_852 = eq(rob[34].cmd, UInt<5>(0h11)) node _store_resp_idx_T_853 = or(_store_resp_idx_T_851, _store_resp_idx_T_852) node _store_resp_idx_T_854 = eq(rob[34].cmd, UInt<3>(0h7)) node _store_resp_idx_T_855 = or(_store_resp_idx_T_853, _store_resp_idx_T_854) node _store_resp_idx_T_856 = eq(rob[34].cmd, UInt<3>(0h4)) node _store_resp_idx_T_857 = eq(rob[34].cmd, UInt<4>(0h9)) node _store_resp_idx_T_858 = eq(rob[34].cmd, UInt<4>(0ha)) node _store_resp_idx_T_859 = eq(rob[34].cmd, UInt<4>(0hb)) node _store_resp_idx_T_860 = or(_store_resp_idx_T_856, _store_resp_idx_T_857) node _store_resp_idx_T_861 = or(_store_resp_idx_T_860, _store_resp_idx_T_858) node _store_resp_idx_T_862 = or(_store_resp_idx_T_861, _store_resp_idx_T_859) node _store_resp_idx_T_863 = eq(rob[34].cmd, UInt<4>(0h8)) node _store_resp_idx_T_864 = eq(rob[34].cmd, UInt<4>(0hc)) node _store_resp_idx_T_865 = eq(rob[34].cmd, UInt<4>(0hd)) node _store_resp_idx_T_866 = eq(rob[34].cmd, UInt<4>(0he)) node _store_resp_idx_T_867 = eq(rob[34].cmd, UInt<4>(0hf)) node _store_resp_idx_T_868 = or(_store_resp_idx_T_863, _store_resp_idx_T_864) node _store_resp_idx_T_869 = or(_store_resp_idx_T_868, _store_resp_idx_T_865) node _store_resp_idx_T_870 = or(_store_resp_idx_T_869, _store_resp_idx_T_866) node _store_resp_idx_T_871 = or(_store_resp_idx_T_870, _store_resp_idx_T_867) node _store_resp_idx_T_872 = or(_store_resp_idx_T_862, _store_resp_idx_T_871) node _store_resp_idx_T_873 = or(_store_resp_idx_T_855, _store_resp_idx_T_872) node _store_resp_idx_T_874 = and(_store_resp_idx_T_850, _store_resp_idx_T_873) node _store_resp_idx_T_875 = eq(rob_respd[35], UInt<1>(0h0)) node _store_resp_idx_T_876 = eq(rob[35].cmd, UInt<1>(0h1)) node _store_resp_idx_T_877 = eq(rob[35].cmd, UInt<5>(0h11)) node _store_resp_idx_T_878 = or(_store_resp_idx_T_876, _store_resp_idx_T_877) node _store_resp_idx_T_879 = eq(rob[35].cmd, UInt<3>(0h7)) node _store_resp_idx_T_880 = or(_store_resp_idx_T_878, _store_resp_idx_T_879) node _store_resp_idx_T_881 = eq(rob[35].cmd, UInt<3>(0h4)) node _store_resp_idx_T_882 = eq(rob[35].cmd, UInt<4>(0h9)) node _store_resp_idx_T_883 = eq(rob[35].cmd, UInt<4>(0ha)) node _store_resp_idx_T_884 = eq(rob[35].cmd, UInt<4>(0hb)) node _store_resp_idx_T_885 = or(_store_resp_idx_T_881, _store_resp_idx_T_882) node _store_resp_idx_T_886 = or(_store_resp_idx_T_885, _store_resp_idx_T_883) node _store_resp_idx_T_887 = or(_store_resp_idx_T_886, _store_resp_idx_T_884) node _store_resp_idx_T_888 = eq(rob[35].cmd, UInt<4>(0h8)) node _store_resp_idx_T_889 = eq(rob[35].cmd, UInt<4>(0hc)) node _store_resp_idx_T_890 = eq(rob[35].cmd, UInt<4>(0hd)) node _store_resp_idx_T_891 = eq(rob[35].cmd, UInt<4>(0he)) node _store_resp_idx_T_892 = eq(rob[35].cmd, UInt<4>(0hf)) node _store_resp_idx_T_893 = or(_store_resp_idx_T_888, _store_resp_idx_T_889) node _store_resp_idx_T_894 = or(_store_resp_idx_T_893, _store_resp_idx_T_890) node _store_resp_idx_T_895 = or(_store_resp_idx_T_894, _store_resp_idx_T_891) node _store_resp_idx_T_896 = or(_store_resp_idx_T_895, _store_resp_idx_T_892) node _store_resp_idx_T_897 = or(_store_resp_idx_T_887, _store_resp_idx_T_896) node _store_resp_idx_T_898 = or(_store_resp_idx_T_880, _store_resp_idx_T_897) node _store_resp_idx_T_899 = and(_store_resp_idx_T_875, _store_resp_idx_T_898) node _store_resp_idx_T_900 = eq(rob_respd[36], UInt<1>(0h0)) node _store_resp_idx_T_901 = eq(rob[36].cmd, UInt<1>(0h1)) node _store_resp_idx_T_902 = eq(rob[36].cmd, UInt<5>(0h11)) node _store_resp_idx_T_903 = or(_store_resp_idx_T_901, _store_resp_idx_T_902) node _store_resp_idx_T_904 = eq(rob[36].cmd, UInt<3>(0h7)) node _store_resp_idx_T_905 = or(_store_resp_idx_T_903, _store_resp_idx_T_904) node _store_resp_idx_T_906 = eq(rob[36].cmd, UInt<3>(0h4)) node _store_resp_idx_T_907 = eq(rob[36].cmd, UInt<4>(0h9)) node _store_resp_idx_T_908 = eq(rob[36].cmd, UInt<4>(0ha)) node _store_resp_idx_T_909 = eq(rob[36].cmd, UInt<4>(0hb)) node _store_resp_idx_T_910 = or(_store_resp_idx_T_906, _store_resp_idx_T_907) node _store_resp_idx_T_911 = or(_store_resp_idx_T_910, _store_resp_idx_T_908) node _store_resp_idx_T_912 = or(_store_resp_idx_T_911, _store_resp_idx_T_909) node _store_resp_idx_T_913 = eq(rob[36].cmd, UInt<4>(0h8)) node _store_resp_idx_T_914 = eq(rob[36].cmd, UInt<4>(0hc)) node _store_resp_idx_T_915 = eq(rob[36].cmd, UInt<4>(0hd)) node _store_resp_idx_T_916 = eq(rob[36].cmd, UInt<4>(0he)) node _store_resp_idx_T_917 = eq(rob[36].cmd, UInt<4>(0hf)) node _store_resp_idx_T_918 = or(_store_resp_idx_T_913, _store_resp_idx_T_914) node _store_resp_idx_T_919 = or(_store_resp_idx_T_918, _store_resp_idx_T_915) node _store_resp_idx_T_920 = or(_store_resp_idx_T_919, _store_resp_idx_T_916) node _store_resp_idx_T_921 = or(_store_resp_idx_T_920, _store_resp_idx_T_917) node _store_resp_idx_T_922 = or(_store_resp_idx_T_912, _store_resp_idx_T_921) node _store_resp_idx_T_923 = or(_store_resp_idx_T_905, _store_resp_idx_T_922) node _store_resp_idx_T_924 = and(_store_resp_idx_T_900, _store_resp_idx_T_923) node _store_resp_idx_T_925 = eq(rob_respd[37], UInt<1>(0h0)) node _store_resp_idx_T_926 = eq(rob[37].cmd, UInt<1>(0h1)) node _store_resp_idx_T_927 = eq(rob[37].cmd, UInt<5>(0h11)) node _store_resp_idx_T_928 = or(_store_resp_idx_T_926, _store_resp_idx_T_927) node _store_resp_idx_T_929 = eq(rob[37].cmd, UInt<3>(0h7)) node _store_resp_idx_T_930 = or(_store_resp_idx_T_928, _store_resp_idx_T_929) node _store_resp_idx_T_931 = eq(rob[37].cmd, UInt<3>(0h4)) node _store_resp_idx_T_932 = eq(rob[37].cmd, UInt<4>(0h9)) node _store_resp_idx_T_933 = eq(rob[37].cmd, UInt<4>(0ha)) node _store_resp_idx_T_934 = eq(rob[37].cmd, UInt<4>(0hb)) node _store_resp_idx_T_935 = or(_store_resp_idx_T_931, _store_resp_idx_T_932) node _store_resp_idx_T_936 = or(_store_resp_idx_T_935, _store_resp_idx_T_933) node _store_resp_idx_T_937 = or(_store_resp_idx_T_936, _store_resp_idx_T_934) node _store_resp_idx_T_938 = eq(rob[37].cmd, UInt<4>(0h8)) node _store_resp_idx_T_939 = eq(rob[37].cmd, UInt<4>(0hc)) node _store_resp_idx_T_940 = eq(rob[37].cmd, UInt<4>(0hd)) node _store_resp_idx_T_941 = eq(rob[37].cmd, UInt<4>(0he)) node _store_resp_idx_T_942 = eq(rob[37].cmd, UInt<4>(0hf)) node _store_resp_idx_T_943 = or(_store_resp_idx_T_938, _store_resp_idx_T_939) node _store_resp_idx_T_944 = or(_store_resp_idx_T_943, _store_resp_idx_T_940) node _store_resp_idx_T_945 = or(_store_resp_idx_T_944, _store_resp_idx_T_941) node _store_resp_idx_T_946 = or(_store_resp_idx_T_945, _store_resp_idx_T_942) node _store_resp_idx_T_947 = or(_store_resp_idx_T_937, _store_resp_idx_T_946) node _store_resp_idx_T_948 = or(_store_resp_idx_T_930, _store_resp_idx_T_947) node _store_resp_idx_T_949 = and(_store_resp_idx_T_925, _store_resp_idx_T_948) node _store_resp_idx_T_950 = eq(rob_respd[38], UInt<1>(0h0)) node _store_resp_idx_T_951 = eq(rob[38].cmd, UInt<1>(0h1)) node _store_resp_idx_T_952 = eq(rob[38].cmd, UInt<5>(0h11)) node _store_resp_idx_T_953 = or(_store_resp_idx_T_951, _store_resp_idx_T_952) node _store_resp_idx_T_954 = eq(rob[38].cmd, UInt<3>(0h7)) node _store_resp_idx_T_955 = or(_store_resp_idx_T_953, _store_resp_idx_T_954) node _store_resp_idx_T_956 = eq(rob[38].cmd, UInt<3>(0h4)) node _store_resp_idx_T_957 = eq(rob[38].cmd, UInt<4>(0h9)) node _store_resp_idx_T_958 = eq(rob[38].cmd, UInt<4>(0ha)) node _store_resp_idx_T_959 = eq(rob[38].cmd, UInt<4>(0hb)) node _store_resp_idx_T_960 = or(_store_resp_idx_T_956, _store_resp_idx_T_957) node _store_resp_idx_T_961 = or(_store_resp_idx_T_960, _store_resp_idx_T_958) node _store_resp_idx_T_962 = or(_store_resp_idx_T_961, _store_resp_idx_T_959) node _store_resp_idx_T_963 = eq(rob[38].cmd, UInt<4>(0h8)) node _store_resp_idx_T_964 = eq(rob[38].cmd, UInt<4>(0hc)) node _store_resp_idx_T_965 = eq(rob[38].cmd, UInt<4>(0hd)) node _store_resp_idx_T_966 = eq(rob[38].cmd, UInt<4>(0he)) node _store_resp_idx_T_967 = eq(rob[38].cmd, UInt<4>(0hf)) node _store_resp_idx_T_968 = or(_store_resp_idx_T_963, _store_resp_idx_T_964) node _store_resp_idx_T_969 = or(_store_resp_idx_T_968, _store_resp_idx_T_965) node _store_resp_idx_T_970 = or(_store_resp_idx_T_969, _store_resp_idx_T_966) node _store_resp_idx_T_971 = or(_store_resp_idx_T_970, _store_resp_idx_T_967) node _store_resp_idx_T_972 = or(_store_resp_idx_T_962, _store_resp_idx_T_971) node _store_resp_idx_T_973 = or(_store_resp_idx_T_955, _store_resp_idx_T_972) node _store_resp_idx_T_974 = and(_store_resp_idx_T_950, _store_resp_idx_T_973) node _store_resp_idx_T_975 = eq(rob_respd[39], UInt<1>(0h0)) node _store_resp_idx_T_976 = eq(rob[39].cmd, UInt<1>(0h1)) node _store_resp_idx_T_977 = eq(rob[39].cmd, UInt<5>(0h11)) node _store_resp_idx_T_978 = or(_store_resp_idx_T_976, _store_resp_idx_T_977) node _store_resp_idx_T_979 = eq(rob[39].cmd, UInt<3>(0h7)) node _store_resp_idx_T_980 = or(_store_resp_idx_T_978, _store_resp_idx_T_979) node _store_resp_idx_T_981 = eq(rob[39].cmd, UInt<3>(0h4)) node _store_resp_idx_T_982 = eq(rob[39].cmd, UInt<4>(0h9)) node _store_resp_idx_T_983 = eq(rob[39].cmd, UInt<4>(0ha)) node _store_resp_idx_T_984 = eq(rob[39].cmd, UInt<4>(0hb)) node _store_resp_idx_T_985 = or(_store_resp_idx_T_981, _store_resp_idx_T_982) node _store_resp_idx_T_986 = or(_store_resp_idx_T_985, _store_resp_idx_T_983) node _store_resp_idx_T_987 = or(_store_resp_idx_T_986, _store_resp_idx_T_984) node _store_resp_idx_T_988 = eq(rob[39].cmd, UInt<4>(0h8)) node _store_resp_idx_T_989 = eq(rob[39].cmd, UInt<4>(0hc)) node _store_resp_idx_T_990 = eq(rob[39].cmd, UInt<4>(0hd)) node _store_resp_idx_T_991 = eq(rob[39].cmd, UInt<4>(0he)) node _store_resp_idx_T_992 = eq(rob[39].cmd, UInt<4>(0hf)) node _store_resp_idx_T_993 = or(_store_resp_idx_T_988, _store_resp_idx_T_989) node _store_resp_idx_T_994 = or(_store_resp_idx_T_993, _store_resp_idx_T_990) node _store_resp_idx_T_995 = or(_store_resp_idx_T_994, _store_resp_idx_T_991) node _store_resp_idx_T_996 = or(_store_resp_idx_T_995, _store_resp_idx_T_992) node _store_resp_idx_T_997 = or(_store_resp_idx_T_987, _store_resp_idx_T_996) node _store_resp_idx_T_998 = or(_store_resp_idx_T_980, _store_resp_idx_T_997) node _store_resp_idx_T_999 = and(_store_resp_idx_T_975, _store_resp_idx_T_998) node _store_resp_idx_T_1000 = eq(rob_respd[40], UInt<1>(0h0)) node _store_resp_idx_T_1001 = eq(rob[40].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1002 = eq(rob[40].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1003 = or(_store_resp_idx_T_1001, _store_resp_idx_T_1002) node _store_resp_idx_T_1004 = eq(rob[40].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1005 = or(_store_resp_idx_T_1003, _store_resp_idx_T_1004) node _store_resp_idx_T_1006 = eq(rob[40].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1007 = eq(rob[40].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1008 = eq(rob[40].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1009 = eq(rob[40].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1010 = or(_store_resp_idx_T_1006, _store_resp_idx_T_1007) node _store_resp_idx_T_1011 = or(_store_resp_idx_T_1010, _store_resp_idx_T_1008) node _store_resp_idx_T_1012 = or(_store_resp_idx_T_1011, _store_resp_idx_T_1009) node _store_resp_idx_T_1013 = eq(rob[40].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1014 = eq(rob[40].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1015 = eq(rob[40].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1016 = eq(rob[40].cmd, UInt<4>(0he)) node _store_resp_idx_T_1017 = eq(rob[40].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1018 = or(_store_resp_idx_T_1013, _store_resp_idx_T_1014) node _store_resp_idx_T_1019 = or(_store_resp_idx_T_1018, _store_resp_idx_T_1015) node _store_resp_idx_T_1020 = or(_store_resp_idx_T_1019, _store_resp_idx_T_1016) node _store_resp_idx_T_1021 = or(_store_resp_idx_T_1020, _store_resp_idx_T_1017) node _store_resp_idx_T_1022 = or(_store_resp_idx_T_1012, _store_resp_idx_T_1021) node _store_resp_idx_T_1023 = or(_store_resp_idx_T_1005, _store_resp_idx_T_1022) node _store_resp_idx_T_1024 = and(_store_resp_idx_T_1000, _store_resp_idx_T_1023) node _store_resp_idx_T_1025 = eq(rob_respd[41], UInt<1>(0h0)) node _store_resp_idx_T_1026 = eq(rob[41].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1027 = eq(rob[41].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1028 = or(_store_resp_idx_T_1026, _store_resp_idx_T_1027) node _store_resp_idx_T_1029 = eq(rob[41].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1030 = or(_store_resp_idx_T_1028, _store_resp_idx_T_1029) node _store_resp_idx_T_1031 = eq(rob[41].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1032 = eq(rob[41].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1033 = eq(rob[41].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1034 = eq(rob[41].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1035 = or(_store_resp_idx_T_1031, _store_resp_idx_T_1032) node _store_resp_idx_T_1036 = or(_store_resp_idx_T_1035, _store_resp_idx_T_1033) node _store_resp_idx_T_1037 = or(_store_resp_idx_T_1036, _store_resp_idx_T_1034) node _store_resp_idx_T_1038 = eq(rob[41].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1039 = eq(rob[41].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1040 = eq(rob[41].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1041 = eq(rob[41].cmd, UInt<4>(0he)) node _store_resp_idx_T_1042 = eq(rob[41].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1043 = or(_store_resp_idx_T_1038, _store_resp_idx_T_1039) node _store_resp_idx_T_1044 = or(_store_resp_idx_T_1043, _store_resp_idx_T_1040) node _store_resp_idx_T_1045 = or(_store_resp_idx_T_1044, _store_resp_idx_T_1041) node _store_resp_idx_T_1046 = or(_store_resp_idx_T_1045, _store_resp_idx_T_1042) node _store_resp_idx_T_1047 = or(_store_resp_idx_T_1037, _store_resp_idx_T_1046) node _store_resp_idx_T_1048 = or(_store_resp_idx_T_1030, _store_resp_idx_T_1047) node _store_resp_idx_T_1049 = and(_store_resp_idx_T_1025, _store_resp_idx_T_1048) node _store_resp_idx_T_1050 = eq(rob_respd[42], UInt<1>(0h0)) node _store_resp_idx_T_1051 = eq(rob[42].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1052 = eq(rob[42].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1053 = or(_store_resp_idx_T_1051, _store_resp_idx_T_1052) node _store_resp_idx_T_1054 = eq(rob[42].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1055 = or(_store_resp_idx_T_1053, _store_resp_idx_T_1054) node _store_resp_idx_T_1056 = eq(rob[42].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1057 = eq(rob[42].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1058 = eq(rob[42].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1059 = eq(rob[42].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1060 = or(_store_resp_idx_T_1056, _store_resp_idx_T_1057) node _store_resp_idx_T_1061 = or(_store_resp_idx_T_1060, _store_resp_idx_T_1058) node _store_resp_idx_T_1062 = or(_store_resp_idx_T_1061, _store_resp_idx_T_1059) node _store_resp_idx_T_1063 = eq(rob[42].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1064 = eq(rob[42].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1065 = eq(rob[42].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1066 = eq(rob[42].cmd, UInt<4>(0he)) node _store_resp_idx_T_1067 = eq(rob[42].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1068 = or(_store_resp_idx_T_1063, _store_resp_idx_T_1064) node _store_resp_idx_T_1069 = or(_store_resp_idx_T_1068, _store_resp_idx_T_1065) node _store_resp_idx_T_1070 = or(_store_resp_idx_T_1069, _store_resp_idx_T_1066) node _store_resp_idx_T_1071 = or(_store_resp_idx_T_1070, _store_resp_idx_T_1067) node _store_resp_idx_T_1072 = or(_store_resp_idx_T_1062, _store_resp_idx_T_1071) node _store_resp_idx_T_1073 = or(_store_resp_idx_T_1055, _store_resp_idx_T_1072) node _store_resp_idx_T_1074 = and(_store_resp_idx_T_1050, _store_resp_idx_T_1073) node _store_resp_idx_T_1075 = eq(rob_respd[43], UInt<1>(0h0)) node _store_resp_idx_T_1076 = eq(rob[43].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1077 = eq(rob[43].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1078 = or(_store_resp_idx_T_1076, _store_resp_idx_T_1077) node _store_resp_idx_T_1079 = eq(rob[43].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1080 = or(_store_resp_idx_T_1078, _store_resp_idx_T_1079) node _store_resp_idx_T_1081 = eq(rob[43].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1082 = eq(rob[43].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1083 = eq(rob[43].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1084 = eq(rob[43].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1085 = or(_store_resp_idx_T_1081, _store_resp_idx_T_1082) node _store_resp_idx_T_1086 = or(_store_resp_idx_T_1085, _store_resp_idx_T_1083) node _store_resp_idx_T_1087 = or(_store_resp_idx_T_1086, _store_resp_idx_T_1084) node _store_resp_idx_T_1088 = eq(rob[43].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1089 = eq(rob[43].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1090 = eq(rob[43].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1091 = eq(rob[43].cmd, UInt<4>(0he)) node _store_resp_idx_T_1092 = eq(rob[43].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1093 = or(_store_resp_idx_T_1088, _store_resp_idx_T_1089) node _store_resp_idx_T_1094 = or(_store_resp_idx_T_1093, _store_resp_idx_T_1090) node _store_resp_idx_T_1095 = or(_store_resp_idx_T_1094, _store_resp_idx_T_1091) node _store_resp_idx_T_1096 = or(_store_resp_idx_T_1095, _store_resp_idx_T_1092) node _store_resp_idx_T_1097 = or(_store_resp_idx_T_1087, _store_resp_idx_T_1096) node _store_resp_idx_T_1098 = or(_store_resp_idx_T_1080, _store_resp_idx_T_1097) node _store_resp_idx_T_1099 = and(_store_resp_idx_T_1075, _store_resp_idx_T_1098) node _store_resp_idx_T_1100 = eq(rob_respd[44], UInt<1>(0h0)) node _store_resp_idx_T_1101 = eq(rob[44].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1102 = eq(rob[44].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1103 = or(_store_resp_idx_T_1101, _store_resp_idx_T_1102) node _store_resp_idx_T_1104 = eq(rob[44].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1105 = or(_store_resp_idx_T_1103, _store_resp_idx_T_1104) node _store_resp_idx_T_1106 = eq(rob[44].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1107 = eq(rob[44].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1108 = eq(rob[44].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1109 = eq(rob[44].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1110 = or(_store_resp_idx_T_1106, _store_resp_idx_T_1107) node _store_resp_idx_T_1111 = or(_store_resp_idx_T_1110, _store_resp_idx_T_1108) node _store_resp_idx_T_1112 = or(_store_resp_idx_T_1111, _store_resp_idx_T_1109) node _store_resp_idx_T_1113 = eq(rob[44].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1114 = eq(rob[44].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1115 = eq(rob[44].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1116 = eq(rob[44].cmd, UInt<4>(0he)) node _store_resp_idx_T_1117 = eq(rob[44].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1118 = or(_store_resp_idx_T_1113, _store_resp_idx_T_1114) node _store_resp_idx_T_1119 = or(_store_resp_idx_T_1118, _store_resp_idx_T_1115) node _store_resp_idx_T_1120 = or(_store_resp_idx_T_1119, _store_resp_idx_T_1116) node _store_resp_idx_T_1121 = or(_store_resp_idx_T_1120, _store_resp_idx_T_1117) node _store_resp_idx_T_1122 = or(_store_resp_idx_T_1112, _store_resp_idx_T_1121) node _store_resp_idx_T_1123 = or(_store_resp_idx_T_1105, _store_resp_idx_T_1122) node _store_resp_idx_T_1124 = and(_store_resp_idx_T_1100, _store_resp_idx_T_1123) node _store_resp_idx_T_1125 = eq(rob_respd[45], UInt<1>(0h0)) node _store_resp_idx_T_1126 = eq(rob[45].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1127 = eq(rob[45].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1128 = or(_store_resp_idx_T_1126, _store_resp_idx_T_1127) node _store_resp_idx_T_1129 = eq(rob[45].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1130 = or(_store_resp_idx_T_1128, _store_resp_idx_T_1129) node _store_resp_idx_T_1131 = eq(rob[45].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1132 = eq(rob[45].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1133 = eq(rob[45].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1134 = eq(rob[45].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1135 = or(_store_resp_idx_T_1131, _store_resp_idx_T_1132) node _store_resp_idx_T_1136 = or(_store_resp_idx_T_1135, _store_resp_idx_T_1133) node _store_resp_idx_T_1137 = or(_store_resp_idx_T_1136, _store_resp_idx_T_1134) node _store_resp_idx_T_1138 = eq(rob[45].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1139 = eq(rob[45].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1140 = eq(rob[45].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1141 = eq(rob[45].cmd, UInt<4>(0he)) node _store_resp_idx_T_1142 = eq(rob[45].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1143 = or(_store_resp_idx_T_1138, _store_resp_idx_T_1139) node _store_resp_idx_T_1144 = or(_store_resp_idx_T_1143, _store_resp_idx_T_1140) node _store_resp_idx_T_1145 = or(_store_resp_idx_T_1144, _store_resp_idx_T_1141) node _store_resp_idx_T_1146 = or(_store_resp_idx_T_1145, _store_resp_idx_T_1142) node _store_resp_idx_T_1147 = or(_store_resp_idx_T_1137, _store_resp_idx_T_1146) node _store_resp_idx_T_1148 = or(_store_resp_idx_T_1130, _store_resp_idx_T_1147) node _store_resp_idx_T_1149 = and(_store_resp_idx_T_1125, _store_resp_idx_T_1148) node _store_resp_idx_T_1150 = eq(rob_respd[46], UInt<1>(0h0)) node _store_resp_idx_T_1151 = eq(rob[46].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1152 = eq(rob[46].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1153 = or(_store_resp_idx_T_1151, _store_resp_idx_T_1152) node _store_resp_idx_T_1154 = eq(rob[46].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1155 = or(_store_resp_idx_T_1153, _store_resp_idx_T_1154) node _store_resp_idx_T_1156 = eq(rob[46].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1157 = eq(rob[46].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1158 = eq(rob[46].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1159 = eq(rob[46].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1160 = or(_store_resp_idx_T_1156, _store_resp_idx_T_1157) node _store_resp_idx_T_1161 = or(_store_resp_idx_T_1160, _store_resp_idx_T_1158) node _store_resp_idx_T_1162 = or(_store_resp_idx_T_1161, _store_resp_idx_T_1159) node _store_resp_idx_T_1163 = eq(rob[46].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1164 = eq(rob[46].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1165 = eq(rob[46].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1166 = eq(rob[46].cmd, UInt<4>(0he)) node _store_resp_idx_T_1167 = eq(rob[46].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1168 = or(_store_resp_idx_T_1163, _store_resp_idx_T_1164) node _store_resp_idx_T_1169 = or(_store_resp_idx_T_1168, _store_resp_idx_T_1165) node _store_resp_idx_T_1170 = or(_store_resp_idx_T_1169, _store_resp_idx_T_1166) node _store_resp_idx_T_1171 = or(_store_resp_idx_T_1170, _store_resp_idx_T_1167) node _store_resp_idx_T_1172 = or(_store_resp_idx_T_1162, _store_resp_idx_T_1171) node _store_resp_idx_T_1173 = or(_store_resp_idx_T_1155, _store_resp_idx_T_1172) node _store_resp_idx_T_1174 = and(_store_resp_idx_T_1150, _store_resp_idx_T_1173) node _store_resp_idx_T_1175 = eq(rob_respd[47], UInt<1>(0h0)) node _store_resp_idx_T_1176 = eq(rob[47].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1177 = eq(rob[47].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1178 = or(_store_resp_idx_T_1176, _store_resp_idx_T_1177) node _store_resp_idx_T_1179 = eq(rob[47].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1180 = or(_store_resp_idx_T_1178, _store_resp_idx_T_1179) node _store_resp_idx_T_1181 = eq(rob[47].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1182 = eq(rob[47].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1183 = eq(rob[47].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1184 = eq(rob[47].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1185 = or(_store_resp_idx_T_1181, _store_resp_idx_T_1182) node _store_resp_idx_T_1186 = or(_store_resp_idx_T_1185, _store_resp_idx_T_1183) node _store_resp_idx_T_1187 = or(_store_resp_idx_T_1186, _store_resp_idx_T_1184) node _store_resp_idx_T_1188 = eq(rob[47].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1189 = eq(rob[47].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1190 = eq(rob[47].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1191 = eq(rob[47].cmd, UInt<4>(0he)) node _store_resp_idx_T_1192 = eq(rob[47].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1193 = or(_store_resp_idx_T_1188, _store_resp_idx_T_1189) node _store_resp_idx_T_1194 = or(_store_resp_idx_T_1193, _store_resp_idx_T_1190) node _store_resp_idx_T_1195 = or(_store_resp_idx_T_1194, _store_resp_idx_T_1191) node _store_resp_idx_T_1196 = or(_store_resp_idx_T_1195, _store_resp_idx_T_1192) node _store_resp_idx_T_1197 = or(_store_resp_idx_T_1187, _store_resp_idx_T_1196) node _store_resp_idx_T_1198 = or(_store_resp_idx_T_1180, _store_resp_idx_T_1197) node _store_resp_idx_T_1199 = and(_store_resp_idx_T_1175, _store_resp_idx_T_1198) node _store_resp_idx_T_1200 = eq(rob_respd[48], UInt<1>(0h0)) node _store_resp_idx_T_1201 = eq(rob[48].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1202 = eq(rob[48].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1203 = or(_store_resp_idx_T_1201, _store_resp_idx_T_1202) node _store_resp_idx_T_1204 = eq(rob[48].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1205 = or(_store_resp_idx_T_1203, _store_resp_idx_T_1204) node _store_resp_idx_T_1206 = eq(rob[48].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1207 = eq(rob[48].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1208 = eq(rob[48].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1209 = eq(rob[48].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1210 = or(_store_resp_idx_T_1206, _store_resp_idx_T_1207) node _store_resp_idx_T_1211 = or(_store_resp_idx_T_1210, _store_resp_idx_T_1208) node _store_resp_idx_T_1212 = or(_store_resp_idx_T_1211, _store_resp_idx_T_1209) node _store_resp_idx_T_1213 = eq(rob[48].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1214 = eq(rob[48].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1215 = eq(rob[48].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1216 = eq(rob[48].cmd, UInt<4>(0he)) node _store_resp_idx_T_1217 = eq(rob[48].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1218 = or(_store_resp_idx_T_1213, _store_resp_idx_T_1214) node _store_resp_idx_T_1219 = or(_store_resp_idx_T_1218, _store_resp_idx_T_1215) node _store_resp_idx_T_1220 = or(_store_resp_idx_T_1219, _store_resp_idx_T_1216) node _store_resp_idx_T_1221 = or(_store_resp_idx_T_1220, _store_resp_idx_T_1217) node _store_resp_idx_T_1222 = or(_store_resp_idx_T_1212, _store_resp_idx_T_1221) node _store_resp_idx_T_1223 = or(_store_resp_idx_T_1205, _store_resp_idx_T_1222) node _store_resp_idx_T_1224 = and(_store_resp_idx_T_1200, _store_resp_idx_T_1223) node _store_resp_idx_T_1225 = eq(rob_respd[49], UInt<1>(0h0)) node _store_resp_idx_T_1226 = eq(rob[49].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1227 = eq(rob[49].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1228 = or(_store_resp_idx_T_1226, _store_resp_idx_T_1227) node _store_resp_idx_T_1229 = eq(rob[49].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1230 = or(_store_resp_idx_T_1228, _store_resp_idx_T_1229) node _store_resp_idx_T_1231 = eq(rob[49].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1232 = eq(rob[49].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1233 = eq(rob[49].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1234 = eq(rob[49].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1235 = or(_store_resp_idx_T_1231, _store_resp_idx_T_1232) node _store_resp_idx_T_1236 = or(_store_resp_idx_T_1235, _store_resp_idx_T_1233) node _store_resp_idx_T_1237 = or(_store_resp_idx_T_1236, _store_resp_idx_T_1234) node _store_resp_idx_T_1238 = eq(rob[49].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1239 = eq(rob[49].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1240 = eq(rob[49].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1241 = eq(rob[49].cmd, UInt<4>(0he)) node _store_resp_idx_T_1242 = eq(rob[49].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1243 = or(_store_resp_idx_T_1238, _store_resp_idx_T_1239) node _store_resp_idx_T_1244 = or(_store_resp_idx_T_1243, _store_resp_idx_T_1240) node _store_resp_idx_T_1245 = or(_store_resp_idx_T_1244, _store_resp_idx_T_1241) node _store_resp_idx_T_1246 = or(_store_resp_idx_T_1245, _store_resp_idx_T_1242) node _store_resp_idx_T_1247 = or(_store_resp_idx_T_1237, _store_resp_idx_T_1246) node _store_resp_idx_T_1248 = or(_store_resp_idx_T_1230, _store_resp_idx_T_1247) node _store_resp_idx_T_1249 = and(_store_resp_idx_T_1225, _store_resp_idx_T_1248) node _store_resp_idx_T_1250 = eq(rob_respd[50], UInt<1>(0h0)) node _store_resp_idx_T_1251 = eq(rob[50].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1252 = eq(rob[50].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1253 = or(_store_resp_idx_T_1251, _store_resp_idx_T_1252) node _store_resp_idx_T_1254 = eq(rob[50].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1255 = or(_store_resp_idx_T_1253, _store_resp_idx_T_1254) node _store_resp_idx_T_1256 = eq(rob[50].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1257 = eq(rob[50].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1258 = eq(rob[50].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1259 = eq(rob[50].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1260 = or(_store_resp_idx_T_1256, _store_resp_idx_T_1257) node _store_resp_idx_T_1261 = or(_store_resp_idx_T_1260, _store_resp_idx_T_1258) node _store_resp_idx_T_1262 = or(_store_resp_idx_T_1261, _store_resp_idx_T_1259) node _store_resp_idx_T_1263 = eq(rob[50].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1264 = eq(rob[50].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1265 = eq(rob[50].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1266 = eq(rob[50].cmd, UInt<4>(0he)) node _store_resp_idx_T_1267 = eq(rob[50].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1268 = or(_store_resp_idx_T_1263, _store_resp_idx_T_1264) node _store_resp_idx_T_1269 = or(_store_resp_idx_T_1268, _store_resp_idx_T_1265) node _store_resp_idx_T_1270 = or(_store_resp_idx_T_1269, _store_resp_idx_T_1266) node _store_resp_idx_T_1271 = or(_store_resp_idx_T_1270, _store_resp_idx_T_1267) node _store_resp_idx_T_1272 = or(_store_resp_idx_T_1262, _store_resp_idx_T_1271) node _store_resp_idx_T_1273 = or(_store_resp_idx_T_1255, _store_resp_idx_T_1272) node _store_resp_idx_T_1274 = and(_store_resp_idx_T_1250, _store_resp_idx_T_1273) node _store_resp_idx_T_1275 = eq(rob_respd[51], UInt<1>(0h0)) node _store_resp_idx_T_1276 = eq(rob[51].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1277 = eq(rob[51].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1278 = or(_store_resp_idx_T_1276, _store_resp_idx_T_1277) node _store_resp_idx_T_1279 = eq(rob[51].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1280 = or(_store_resp_idx_T_1278, _store_resp_idx_T_1279) node _store_resp_idx_T_1281 = eq(rob[51].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1282 = eq(rob[51].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1283 = eq(rob[51].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1284 = eq(rob[51].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1285 = or(_store_resp_idx_T_1281, _store_resp_idx_T_1282) node _store_resp_idx_T_1286 = or(_store_resp_idx_T_1285, _store_resp_idx_T_1283) node _store_resp_idx_T_1287 = or(_store_resp_idx_T_1286, _store_resp_idx_T_1284) node _store_resp_idx_T_1288 = eq(rob[51].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1289 = eq(rob[51].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1290 = eq(rob[51].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1291 = eq(rob[51].cmd, UInt<4>(0he)) node _store_resp_idx_T_1292 = eq(rob[51].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1293 = or(_store_resp_idx_T_1288, _store_resp_idx_T_1289) node _store_resp_idx_T_1294 = or(_store_resp_idx_T_1293, _store_resp_idx_T_1290) node _store_resp_idx_T_1295 = or(_store_resp_idx_T_1294, _store_resp_idx_T_1291) node _store_resp_idx_T_1296 = or(_store_resp_idx_T_1295, _store_resp_idx_T_1292) node _store_resp_idx_T_1297 = or(_store_resp_idx_T_1287, _store_resp_idx_T_1296) node _store_resp_idx_T_1298 = or(_store_resp_idx_T_1280, _store_resp_idx_T_1297) node _store_resp_idx_T_1299 = and(_store_resp_idx_T_1275, _store_resp_idx_T_1298) node _store_resp_idx_T_1300 = eq(rob_respd[52], UInt<1>(0h0)) node _store_resp_idx_T_1301 = eq(rob[52].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1302 = eq(rob[52].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1303 = or(_store_resp_idx_T_1301, _store_resp_idx_T_1302) node _store_resp_idx_T_1304 = eq(rob[52].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1305 = or(_store_resp_idx_T_1303, _store_resp_idx_T_1304) node _store_resp_idx_T_1306 = eq(rob[52].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1307 = eq(rob[52].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1308 = eq(rob[52].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1309 = eq(rob[52].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1310 = or(_store_resp_idx_T_1306, _store_resp_idx_T_1307) node _store_resp_idx_T_1311 = or(_store_resp_idx_T_1310, _store_resp_idx_T_1308) node _store_resp_idx_T_1312 = or(_store_resp_idx_T_1311, _store_resp_idx_T_1309) node _store_resp_idx_T_1313 = eq(rob[52].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1314 = eq(rob[52].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1315 = eq(rob[52].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1316 = eq(rob[52].cmd, UInt<4>(0he)) node _store_resp_idx_T_1317 = eq(rob[52].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1318 = or(_store_resp_idx_T_1313, _store_resp_idx_T_1314) node _store_resp_idx_T_1319 = or(_store_resp_idx_T_1318, _store_resp_idx_T_1315) node _store_resp_idx_T_1320 = or(_store_resp_idx_T_1319, _store_resp_idx_T_1316) node _store_resp_idx_T_1321 = or(_store_resp_idx_T_1320, _store_resp_idx_T_1317) node _store_resp_idx_T_1322 = or(_store_resp_idx_T_1312, _store_resp_idx_T_1321) node _store_resp_idx_T_1323 = or(_store_resp_idx_T_1305, _store_resp_idx_T_1322) node _store_resp_idx_T_1324 = and(_store_resp_idx_T_1300, _store_resp_idx_T_1323) node _store_resp_idx_T_1325 = eq(rob_respd[53], UInt<1>(0h0)) node _store_resp_idx_T_1326 = eq(rob[53].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1327 = eq(rob[53].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1328 = or(_store_resp_idx_T_1326, _store_resp_idx_T_1327) node _store_resp_idx_T_1329 = eq(rob[53].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1330 = or(_store_resp_idx_T_1328, _store_resp_idx_T_1329) node _store_resp_idx_T_1331 = eq(rob[53].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1332 = eq(rob[53].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1333 = eq(rob[53].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1334 = eq(rob[53].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1335 = or(_store_resp_idx_T_1331, _store_resp_idx_T_1332) node _store_resp_idx_T_1336 = or(_store_resp_idx_T_1335, _store_resp_idx_T_1333) node _store_resp_idx_T_1337 = or(_store_resp_idx_T_1336, _store_resp_idx_T_1334) node _store_resp_idx_T_1338 = eq(rob[53].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1339 = eq(rob[53].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1340 = eq(rob[53].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1341 = eq(rob[53].cmd, UInt<4>(0he)) node _store_resp_idx_T_1342 = eq(rob[53].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1343 = or(_store_resp_idx_T_1338, _store_resp_idx_T_1339) node _store_resp_idx_T_1344 = or(_store_resp_idx_T_1343, _store_resp_idx_T_1340) node _store_resp_idx_T_1345 = or(_store_resp_idx_T_1344, _store_resp_idx_T_1341) node _store_resp_idx_T_1346 = or(_store_resp_idx_T_1345, _store_resp_idx_T_1342) node _store_resp_idx_T_1347 = or(_store_resp_idx_T_1337, _store_resp_idx_T_1346) node _store_resp_idx_T_1348 = or(_store_resp_idx_T_1330, _store_resp_idx_T_1347) node _store_resp_idx_T_1349 = and(_store_resp_idx_T_1325, _store_resp_idx_T_1348) node _store_resp_idx_T_1350 = eq(rob_respd[54], UInt<1>(0h0)) node _store_resp_idx_T_1351 = eq(rob[54].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1352 = eq(rob[54].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1353 = or(_store_resp_idx_T_1351, _store_resp_idx_T_1352) node _store_resp_idx_T_1354 = eq(rob[54].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1355 = or(_store_resp_idx_T_1353, _store_resp_idx_T_1354) node _store_resp_idx_T_1356 = eq(rob[54].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1357 = eq(rob[54].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1358 = eq(rob[54].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1359 = eq(rob[54].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1360 = or(_store_resp_idx_T_1356, _store_resp_idx_T_1357) node _store_resp_idx_T_1361 = or(_store_resp_idx_T_1360, _store_resp_idx_T_1358) node _store_resp_idx_T_1362 = or(_store_resp_idx_T_1361, _store_resp_idx_T_1359) node _store_resp_idx_T_1363 = eq(rob[54].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1364 = eq(rob[54].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1365 = eq(rob[54].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1366 = eq(rob[54].cmd, UInt<4>(0he)) node _store_resp_idx_T_1367 = eq(rob[54].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1368 = or(_store_resp_idx_T_1363, _store_resp_idx_T_1364) node _store_resp_idx_T_1369 = or(_store_resp_idx_T_1368, _store_resp_idx_T_1365) node _store_resp_idx_T_1370 = or(_store_resp_idx_T_1369, _store_resp_idx_T_1366) node _store_resp_idx_T_1371 = or(_store_resp_idx_T_1370, _store_resp_idx_T_1367) node _store_resp_idx_T_1372 = or(_store_resp_idx_T_1362, _store_resp_idx_T_1371) node _store_resp_idx_T_1373 = or(_store_resp_idx_T_1355, _store_resp_idx_T_1372) node _store_resp_idx_T_1374 = and(_store_resp_idx_T_1350, _store_resp_idx_T_1373) node _store_resp_idx_T_1375 = eq(rob_respd[55], UInt<1>(0h0)) node _store_resp_idx_T_1376 = eq(rob[55].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1377 = eq(rob[55].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1378 = or(_store_resp_idx_T_1376, _store_resp_idx_T_1377) node _store_resp_idx_T_1379 = eq(rob[55].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1380 = or(_store_resp_idx_T_1378, _store_resp_idx_T_1379) node _store_resp_idx_T_1381 = eq(rob[55].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1382 = eq(rob[55].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1383 = eq(rob[55].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1384 = eq(rob[55].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1385 = or(_store_resp_idx_T_1381, _store_resp_idx_T_1382) node _store_resp_idx_T_1386 = or(_store_resp_idx_T_1385, _store_resp_idx_T_1383) node _store_resp_idx_T_1387 = or(_store_resp_idx_T_1386, _store_resp_idx_T_1384) node _store_resp_idx_T_1388 = eq(rob[55].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1389 = eq(rob[55].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1390 = eq(rob[55].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1391 = eq(rob[55].cmd, UInt<4>(0he)) node _store_resp_idx_T_1392 = eq(rob[55].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1393 = or(_store_resp_idx_T_1388, _store_resp_idx_T_1389) node _store_resp_idx_T_1394 = or(_store_resp_idx_T_1393, _store_resp_idx_T_1390) node _store_resp_idx_T_1395 = or(_store_resp_idx_T_1394, _store_resp_idx_T_1391) node _store_resp_idx_T_1396 = or(_store_resp_idx_T_1395, _store_resp_idx_T_1392) node _store_resp_idx_T_1397 = or(_store_resp_idx_T_1387, _store_resp_idx_T_1396) node _store_resp_idx_T_1398 = or(_store_resp_idx_T_1380, _store_resp_idx_T_1397) node _store_resp_idx_T_1399 = and(_store_resp_idx_T_1375, _store_resp_idx_T_1398) node _store_resp_idx_T_1400 = eq(rob_respd[56], UInt<1>(0h0)) node _store_resp_idx_T_1401 = eq(rob[56].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1402 = eq(rob[56].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1403 = or(_store_resp_idx_T_1401, _store_resp_idx_T_1402) node _store_resp_idx_T_1404 = eq(rob[56].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1405 = or(_store_resp_idx_T_1403, _store_resp_idx_T_1404) node _store_resp_idx_T_1406 = eq(rob[56].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1407 = eq(rob[56].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1408 = eq(rob[56].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1409 = eq(rob[56].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1410 = or(_store_resp_idx_T_1406, _store_resp_idx_T_1407) node _store_resp_idx_T_1411 = or(_store_resp_idx_T_1410, _store_resp_idx_T_1408) node _store_resp_idx_T_1412 = or(_store_resp_idx_T_1411, _store_resp_idx_T_1409) node _store_resp_idx_T_1413 = eq(rob[56].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1414 = eq(rob[56].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1415 = eq(rob[56].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1416 = eq(rob[56].cmd, UInt<4>(0he)) node _store_resp_idx_T_1417 = eq(rob[56].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1418 = or(_store_resp_idx_T_1413, _store_resp_idx_T_1414) node _store_resp_idx_T_1419 = or(_store_resp_idx_T_1418, _store_resp_idx_T_1415) node _store_resp_idx_T_1420 = or(_store_resp_idx_T_1419, _store_resp_idx_T_1416) node _store_resp_idx_T_1421 = or(_store_resp_idx_T_1420, _store_resp_idx_T_1417) node _store_resp_idx_T_1422 = or(_store_resp_idx_T_1412, _store_resp_idx_T_1421) node _store_resp_idx_T_1423 = or(_store_resp_idx_T_1405, _store_resp_idx_T_1422) node _store_resp_idx_T_1424 = and(_store_resp_idx_T_1400, _store_resp_idx_T_1423) node _store_resp_idx_T_1425 = eq(rob_respd[57], UInt<1>(0h0)) node _store_resp_idx_T_1426 = eq(rob[57].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1427 = eq(rob[57].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1428 = or(_store_resp_idx_T_1426, _store_resp_idx_T_1427) node _store_resp_idx_T_1429 = eq(rob[57].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1430 = or(_store_resp_idx_T_1428, _store_resp_idx_T_1429) node _store_resp_idx_T_1431 = eq(rob[57].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1432 = eq(rob[57].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1433 = eq(rob[57].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1434 = eq(rob[57].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1435 = or(_store_resp_idx_T_1431, _store_resp_idx_T_1432) node _store_resp_idx_T_1436 = or(_store_resp_idx_T_1435, _store_resp_idx_T_1433) node _store_resp_idx_T_1437 = or(_store_resp_idx_T_1436, _store_resp_idx_T_1434) node _store_resp_idx_T_1438 = eq(rob[57].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1439 = eq(rob[57].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1440 = eq(rob[57].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1441 = eq(rob[57].cmd, UInt<4>(0he)) node _store_resp_idx_T_1442 = eq(rob[57].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1443 = or(_store_resp_idx_T_1438, _store_resp_idx_T_1439) node _store_resp_idx_T_1444 = or(_store_resp_idx_T_1443, _store_resp_idx_T_1440) node _store_resp_idx_T_1445 = or(_store_resp_idx_T_1444, _store_resp_idx_T_1441) node _store_resp_idx_T_1446 = or(_store_resp_idx_T_1445, _store_resp_idx_T_1442) node _store_resp_idx_T_1447 = or(_store_resp_idx_T_1437, _store_resp_idx_T_1446) node _store_resp_idx_T_1448 = or(_store_resp_idx_T_1430, _store_resp_idx_T_1447) node _store_resp_idx_T_1449 = and(_store_resp_idx_T_1425, _store_resp_idx_T_1448) node _store_resp_idx_T_1450 = eq(rob_respd[58], UInt<1>(0h0)) node _store_resp_idx_T_1451 = eq(rob[58].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1452 = eq(rob[58].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1453 = or(_store_resp_idx_T_1451, _store_resp_idx_T_1452) node _store_resp_idx_T_1454 = eq(rob[58].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1455 = or(_store_resp_idx_T_1453, _store_resp_idx_T_1454) node _store_resp_idx_T_1456 = eq(rob[58].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1457 = eq(rob[58].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1458 = eq(rob[58].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1459 = eq(rob[58].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1460 = or(_store_resp_idx_T_1456, _store_resp_idx_T_1457) node _store_resp_idx_T_1461 = or(_store_resp_idx_T_1460, _store_resp_idx_T_1458) node _store_resp_idx_T_1462 = or(_store_resp_idx_T_1461, _store_resp_idx_T_1459) node _store_resp_idx_T_1463 = eq(rob[58].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1464 = eq(rob[58].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1465 = eq(rob[58].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1466 = eq(rob[58].cmd, UInt<4>(0he)) node _store_resp_idx_T_1467 = eq(rob[58].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1468 = or(_store_resp_idx_T_1463, _store_resp_idx_T_1464) node _store_resp_idx_T_1469 = or(_store_resp_idx_T_1468, _store_resp_idx_T_1465) node _store_resp_idx_T_1470 = or(_store_resp_idx_T_1469, _store_resp_idx_T_1466) node _store_resp_idx_T_1471 = or(_store_resp_idx_T_1470, _store_resp_idx_T_1467) node _store_resp_idx_T_1472 = or(_store_resp_idx_T_1462, _store_resp_idx_T_1471) node _store_resp_idx_T_1473 = or(_store_resp_idx_T_1455, _store_resp_idx_T_1472) node _store_resp_idx_T_1474 = and(_store_resp_idx_T_1450, _store_resp_idx_T_1473) node _store_resp_idx_T_1475 = eq(rob_respd[59], UInt<1>(0h0)) node _store_resp_idx_T_1476 = eq(rob[59].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1477 = eq(rob[59].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1478 = or(_store_resp_idx_T_1476, _store_resp_idx_T_1477) node _store_resp_idx_T_1479 = eq(rob[59].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1480 = or(_store_resp_idx_T_1478, _store_resp_idx_T_1479) node _store_resp_idx_T_1481 = eq(rob[59].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1482 = eq(rob[59].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1483 = eq(rob[59].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1484 = eq(rob[59].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1485 = or(_store_resp_idx_T_1481, _store_resp_idx_T_1482) node _store_resp_idx_T_1486 = or(_store_resp_idx_T_1485, _store_resp_idx_T_1483) node _store_resp_idx_T_1487 = or(_store_resp_idx_T_1486, _store_resp_idx_T_1484) node _store_resp_idx_T_1488 = eq(rob[59].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1489 = eq(rob[59].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1490 = eq(rob[59].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1491 = eq(rob[59].cmd, UInt<4>(0he)) node _store_resp_idx_T_1492 = eq(rob[59].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1493 = or(_store_resp_idx_T_1488, _store_resp_idx_T_1489) node _store_resp_idx_T_1494 = or(_store_resp_idx_T_1493, _store_resp_idx_T_1490) node _store_resp_idx_T_1495 = or(_store_resp_idx_T_1494, _store_resp_idx_T_1491) node _store_resp_idx_T_1496 = or(_store_resp_idx_T_1495, _store_resp_idx_T_1492) node _store_resp_idx_T_1497 = or(_store_resp_idx_T_1487, _store_resp_idx_T_1496) node _store_resp_idx_T_1498 = or(_store_resp_idx_T_1480, _store_resp_idx_T_1497) node _store_resp_idx_T_1499 = and(_store_resp_idx_T_1475, _store_resp_idx_T_1498) node _store_resp_idx_T_1500 = eq(rob_respd[60], UInt<1>(0h0)) node _store_resp_idx_T_1501 = eq(rob[60].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1502 = eq(rob[60].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1503 = or(_store_resp_idx_T_1501, _store_resp_idx_T_1502) node _store_resp_idx_T_1504 = eq(rob[60].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1505 = or(_store_resp_idx_T_1503, _store_resp_idx_T_1504) node _store_resp_idx_T_1506 = eq(rob[60].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1507 = eq(rob[60].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1508 = eq(rob[60].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1509 = eq(rob[60].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1510 = or(_store_resp_idx_T_1506, _store_resp_idx_T_1507) node _store_resp_idx_T_1511 = or(_store_resp_idx_T_1510, _store_resp_idx_T_1508) node _store_resp_idx_T_1512 = or(_store_resp_idx_T_1511, _store_resp_idx_T_1509) node _store_resp_idx_T_1513 = eq(rob[60].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1514 = eq(rob[60].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1515 = eq(rob[60].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1516 = eq(rob[60].cmd, UInt<4>(0he)) node _store_resp_idx_T_1517 = eq(rob[60].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1518 = or(_store_resp_idx_T_1513, _store_resp_idx_T_1514) node _store_resp_idx_T_1519 = or(_store_resp_idx_T_1518, _store_resp_idx_T_1515) node _store_resp_idx_T_1520 = or(_store_resp_idx_T_1519, _store_resp_idx_T_1516) node _store_resp_idx_T_1521 = or(_store_resp_idx_T_1520, _store_resp_idx_T_1517) node _store_resp_idx_T_1522 = or(_store_resp_idx_T_1512, _store_resp_idx_T_1521) node _store_resp_idx_T_1523 = or(_store_resp_idx_T_1505, _store_resp_idx_T_1522) node _store_resp_idx_T_1524 = and(_store_resp_idx_T_1500, _store_resp_idx_T_1523) node _store_resp_idx_T_1525 = eq(rob_respd[61], UInt<1>(0h0)) node _store_resp_idx_T_1526 = eq(rob[61].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1527 = eq(rob[61].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1528 = or(_store_resp_idx_T_1526, _store_resp_idx_T_1527) node _store_resp_idx_T_1529 = eq(rob[61].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1530 = or(_store_resp_idx_T_1528, _store_resp_idx_T_1529) node _store_resp_idx_T_1531 = eq(rob[61].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1532 = eq(rob[61].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1533 = eq(rob[61].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1534 = eq(rob[61].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1535 = or(_store_resp_idx_T_1531, _store_resp_idx_T_1532) node _store_resp_idx_T_1536 = or(_store_resp_idx_T_1535, _store_resp_idx_T_1533) node _store_resp_idx_T_1537 = or(_store_resp_idx_T_1536, _store_resp_idx_T_1534) node _store_resp_idx_T_1538 = eq(rob[61].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1539 = eq(rob[61].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1540 = eq(rob[61].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1541 = eq(rob[61].cmd, UInt<4>(0he)) node _store_resp_idx_T_1542 = eq(rob[61].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1543 = or(_store_resp_idx_T_1538, _store_resp_idx_T_1539) node _store_resp_idx_T_1544 = or(_store_resp_idx_T_1543, _store_resp_idx_T_1540) node _store_resp_idx_T_1545 = or(_store_resp_idx_T_1544, _store_resp_idx_T_1541) node _store_resp_idx_T_1546 = or(_store_resp_idx_T_1545, _store_resp_idx_T_1542) node _store_resp_idx_T_1547 = or(_store_resp_idx_T_1537, _store_resp_idx_T_1546) node _store_resp_idx_T_1548 = or(_store_resp_idx_T_1530, _store_resp_idx_T_1547) node _store_resp_idx_T_1549 = and(_store_resp_idx_T_1525, _store_resp_idx_T_1548) node _store_resp_idx_T_1550 = eq(rob_respd[62], UInt<1>(0h0)) node _store_resp_idx_T_1551 = eq(rob[62].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1552 = eq(rob[62].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1553 = or(_store_resp_idx_T_1551, _store_resp_idx_T_1552) node _store_resp_idx_T_1554 = eq(rob[62].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1555 = or(_store_resp_idx_T_1553, _store_resp_idx_T_1554) node _store_resp_idx_T_1556 = eq(rob[62].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1557 = eq(rob[62].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1558 = eq(rob[62].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1559 = eq(rob[62].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1560 = or(_store_resp_idx_T_1556, _store_resp_idx_T_1557) node _store_resp_idx_T_1561 = or(_store_resp_idx_T_1560, _store_resp_idx_T_1558) node _store_resp_idx_T_1562 = or(_store_resp_idx_T_1561, _store_resp_idx_T_1559) node _store_resp_idx_T_1563 = eq(rob[62].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1564 = eq(rob[62].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1565 = eq(rob[62].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1566 = eq(rob[62].cmd, UInt<4>(0he)) node _store_resp_idx_T_1567 = eq(rob[62].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1568 = or(_store_resp_idx_T_1563, _store_resp_idx_T_1564) node _store_resp_idx_T_1569 = or(_store_resp_idx_T_1568, _store_resp_idx_T_1565) node _store_resp_idx_T_1570 = or(_store_resp_idx_T_1569, _store_resp_idx_T_1566) node _store_resp_idx_T_1571 = or(_store_resp_idx_T_1570, _store_resp_idx_T_1567) node _store_resp_idx_T_1572 = or(_store_resp_idx_T_1562, _store_resp_idx_T_1571) node _store_resp_idx_T_1573 = or(_store_resp_idx_T_1555, _store_resp_idx_T_1572) node _store_resp_idx_T_1574 = and(_store_resp_idx_T_1550, _store_resp_idx_T_1573) node _store_resp_idx_T_1575 = eq(rob_respd[63], UInt<1>(0h0)) node _store_resp_idx_T_1576 = eq(rob[63].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1577 = eq(rob[63].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1578 = or(_store_resp_idx_T_1576, _store_resp_idx_T_1577) node _store_resp_idx_T_1579 = eq(rob[63].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1580 = or(_store_resp_idx_T_1578, _store_resp_idx_T_1579) node _store_resp_idx_T_1581 = eq(rob[63].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1582 = eq(rob[63].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1583 = eq(rob[63].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1584 = eq(rob[63].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1585 = or(_store_resp_idx_T_1581, _store_resp_idx_T_1582) node _store_resp_idx_T_1586 = or(_store_resp_idx_T_1585, _store_resp_idx_T_1583) node _store_resp_idx_T_1587 = or(_store_resp_idx_T_1586, _store_resp_idx_T_1584) node _store_resp_idx_T_1588 = eq(rob[63].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1589 = eq(rob[63].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1590 = eq(rob[63].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1591 = eq(rob[63].cmd, UInt<4>(0he)) node _store_resp_idx_T_1592 = eq(rob[63].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1593 = or(_store_resp_idx_T_1588, _store_resp_idx_T_1589) node _store_resp_idx_T_1594 = or(_store_resp_idx_T_1593, _store_resp_idx_T_1590) node _store_resp_idx_T_1595 = or(_store_resp_idx_T_1594, _store_resp_idx_T_1591) node _store_resp_idx_T_1596 = or(_store_resp_idx_T_1595, _store_resp_idx_T_1592) node _store_resp_idx_T_1597 = or(_store_resp_idx_T_1587, _store_resp_idx_T_1596) node _store_resp_idx_T_1598 = or(_store_resp_idx_T_1580, _store_resp_idx_T_1597) node _store_resp_idx_T_1599 = and(_store_resp_idx_T_1575, _store_resp_idx_T_1598) node _store_resp_idx_T_1600 = mux(_store_resp_idx_T_1574, UInt<6>(0h3e), UInt<6>(0h3f)) node _store_resp_idx_T_1601 = mux(_store_resp_idx_T_1549, UInt<6>(0h3d), _store_resp_idx_T_1600) node _store_resp_idx_T_1602 = mux(_store_resp_idx_T_1524, UInt<6>(0h3c), _store_resp_idx_T_1601) node _store_resp_idx_T_1603 = mux(_store_resp_idx_T_1499, UInt<6>(0h3b), _store_resp_idx_T_1602) node _store_resp_idx_T_1604 = mux(_store_resp_idx_T_1474, UInt<6>(0h3a), _store_resp_idx_T_1603) node _store_resp_idx_T_1605 = mux(_store_resp_idx_T_1449, UInt<6>(0h39), _store_resp_idx_T_1604) node _store_resp_idx_T_1606 = mux(_store_resp_idx_T_1424, UInt<6>(0h38), _store_resp_idx_T_1605) node _store_resp_idx_T_1607 = mux(_store_resp_idx_T_1399, UInt<6>(0h37), _store_resp_idx_T_1606) node _store_resp_idx_T_1608 = mux(_store_resp_idx_T_1374, UInt<6>(0h36), _store_resp_idx_T_1607) node _store_resp_idx_T_1609 = mux(_store_resp_idx_T_1349, UInt<6>(0h35), _store_resp_idx_T_1608) node _store_resp_idx_T_1610 = mux(_store_resp_idx_T_1324, UInt<6>(0h34), _store_resp_idx_T_1609) node _store_resp_idx_T_1611 = mux(_store_resp_idx_T_1299, UInt<6>(0h33), _store_resp_idx_T_1610) node _store_resp_idx_T_1612 = mux(_store_resp_idx_T_1274, UInt<6>(0h32), _store_resp_idx_T_1611) node _store_resp_idx_T_1613 = mux(_store_resp_idx_T_1249, UInt<6>(0h31), _store_resp_idx_T_1612) node _store_resp_idx_T_1614 = mux(_store_resp_idx_T_1224, UInt<6>(0h30), _store_resp_idx_T_1613) node _store_resp_idx_T_1615 = mux(_store_resp_idx_T_1199, UInt<6>(0h2f), _store_resp_idx_T_1614) node _store_resp_idx_T_1616 = mux(_store_resp_idx_T_1174, UInt<6>(0h2e), _store_resp_idx_T_1615) node _store_resp_idx_T_1617 = mux(_store_resp_idx_T_1149, UInt<6>(0h2d), _store_resp_idx_T_1616) node _store_resp_idx_T_1618 = mux(_store_resp_idx_T_1124, UInt<6>(0h2c), _store_resp_idx_T_1617) node _store_resp_idx_T_1619 = mux(_store_resp_idx_T_1099, UInt<6>(0h2b), _store_resp_idx_T_1618) node _store_resp_idx_T_1620 = mux(_store_resp_idx_T_1074, UInt<6>(0h2a), _store_resp_idx_T_1619) node _store_resp_idx_T_1621 = mux(_store_resp_idx_T_1049, UInt<6>(0h29), _store_resp_idx_T_1620) node _store_resp_idx_T_1622 = mux(_store_resp_idx_T_1024, UInt<6>(0h28), _store_resp_idx_T_1621) node _store_resp_idx_T_1623 = mux(_store_resp_idx_T_999, UInt<6>(0h27), _store_resp_idx_T_1622) node _store_resp_idx_T_1624 = mux(_store_resp_idx_T_974, UInt<6>(0h26), _store_resp_idx_T_1623) node _store_resp_idx_T_1625 = mux(_store_resp_idx_T_949, UInt<6>(0h25), _store_resp_idx_T_1624) node _store_resp_idx_T_1626 = mux(_store_resp_idx_T_924, UInt<6>(0h24), _store_resp_idx_T_1625) node _store_resp_idx_T_1627 = mux(_store_resp_idx_T_899, UInt<6>(0h23), _store_resp_idx_T_1626) node _store_resp_idx_T_1628 = mux(_store_resp_idx_T_874, UInt<6>(0h22), _store_resp_idx_T_1627) node _store_resp_idx_T_1629 = mux(_store_resp_idx_T_849, UInt<6>(0h21), _store_resp_idx_T_1628) node _store_resp_idx_T_1630 = mux(_store_resp_idx_T_824, UInt<6>(0h20), _store_resp_idx_T_1629) node _store_resp_idx_T_1631 = mux(_store_resp_idx_T_799, UInt<5>(0h1f), _store_resp_idx_T_1630) node _store_resp_idx_T_1632 = mux(_store_resp_idx_T_774, UInt<5>(0h1e), _store_resp_idx_T_1631) node _store_resp_idx_T_1633 = mux(_store_resp_idx_T_749, UInt<5>(0h1d), _store_resp_idx_T_1632) node _store_resp_idx_T_1634 = mux(_store_resp_idx_T_724, UInt<5>(0h1c), _store_resp_idx_T_1633) node _store_resp_idx_T_1635 = mux(_store_resp_idx_T_699, UInt<5>(0h1b), _store_resp_idx_T_1634) node _store_resp_idx_T_1636 = mux(_store_resp_idx_T_674, UInt<5>(0h1a), _store_resp_idx_T_1635) node _store_resp_idx_T_1637 = mux(_store_resp_idx_T_649, UInt<5>(0h19), _store_resp_idx_T_1636) node _store_resp_idx_T_1638 = mux(_store_resp_idx_T_624, UInt<5>(0h18), _store_resp_idx_T_1637) node _store_resp_idx_T_1639 = mux(_store_resp_idx_T_599, UInt<5>(0h17), _store_resp_idx_T_1638) node _store_resp_idx_T_1640 = mux(_store_resp_idx_T_574, UInt<5>(0h16), _store_resp_idx_T_1639) node _store_resp_idx_T_1641 = mux(_store_resp_idx_T_549, UInt<5>(0h15), _store_resp_idx_T_1640) node _store_resp_idx_T_1642 = mux(_store_resp_idx_T_524, UInt<5>(0h14), _store_resp_idx_T_1641) node _store_resp_idx_T_1643 = mux(_store_resp_idx_T_499, UInt<5>(0h13), _store_resp_idx_T_1642) node _store_resp_idx_T_1644 = mux(_store_resp_idx_T_474, UInt<5>(0h12), _store_resp_idx_T_1643) node _store_resp_idx_T_1645 = mux(_store_resp_idx_T_449, UInt<5>(0h11), _store_resp_idx_T_1644) node _store_resp_idx_T_1646 = mux(_store_resp_idx_T_424, UInt<5>(0h10), _store_resp_idx_T_1645) node _store_resp_idx_T_1647 = mux(_store_resp_idx_T_399, UInt<4>(0hf), _store_resp_idx_T_1646) node _store_resp_idx_T_1648 = mux(_store_resp_idx_T_374, UInt<4>(0he), _store_resp_idx_T_1647) node _store_resp_idx_T_1649 = mux(_store_resp_idx_T_349, UInt<4>(0hd), _store_resp_idx_T_1648) node _store_resp_idx_T_1650 = mux(_store_resp_idx_T_324, UInt<4>(0hc), _store_resp_idx_T_1649) node _store_resp_idx_T_1651 = mux(_store_resp_idx_T_299, UInt<4>(0hb), _store_resp_idx_T_1650) node _store_resp_idx_T_1652 = mux(_store_resp_idx_T_274, UInt<4>(0ha), _store_resp_idx_T_1651) node _store_resp_idx_T_1653 = mux(_store_resp_idx_T_249, UInt<4>(0h9), _store_resp_idx_T_1652) node _store_resp_idx_T_1654 = mux(_store_resp_idx_T_224, UInt<4>(0h8), _store_resp_idx_T_1653) node _store_resp_idx_T_1655 = mux(_store_resp_idx_T_199, UInt<3>(0h7), _store_resp_idx_T_1654) node _store_resp_idx_T_1656 = mux(_store_resp_idx_T_174, UInt<3>(0h6), _store_resp_idx_T_1655) node _store_resp_idx_T_1657 = mux(_store_resp_idx_T_149, UInt<3>(0h5), _store_resp_idx_T_1656) node _store_resp_idx_T_1658 = mux(_store_resp_idx_T_124, UInt<3>(0h4), _store_resp_idx_T_1657) node _store_resp_idx_T_1659 = mux(_store_resp_idx_T_99, UInt<2>(0h3), _store_resp_idx_T_1658) node _store_resp_idx_T_1660 = mux(_store_resp_idx_T_74, UInt<2>(0h2), _store_resp_idx_T_1659) node _store_resp_idx_T_1661 = mux(_store_resp_idx_T_49, UInt<1>(0h1), _store_resp_idx_T_1660) node store_resp_idx = mux(_store_resp_idx_T_24, UInt<1>(0h0), _store_resp_idx_T_1661) node _can_do_store_resp_T = not(rob_respd[store_resp_idx]) node _can_do_store_resp_T_1 = eq(rob[store_resp_idx].cmd, UInt<1>(0h1)) node _can_do_store_resp_T_2 = eq(rob[store_resp_idx].cmd, UInt<5>(0h11)) node _can_do_store_resp_T_3 = or(_can_do_store_resp_T_1, _can_do_store_resp_T_2) node _can_do_store_resp_T_4 = eq(rob[store_resp_idx].cmd, UInt<3>(0h7)) node _can_do_store_resp_T_5 = or(_can_do_store_resp_T_3, _can_do_store_resp_T_4) node _can_do_store_resp_T_6 = eq(rob[store_resp_idx].cmd, UInt<3>(0h4)) node _can_do_store_resp_T_7 = eq(rob[store_resp_idx].cmd, UInt<4>(0h9)) node _can_do_store_resp_T_8 = eq(rob[store_resp_idx].cmd, UInt<4>(0ha)) node _can_do_store_resp_T_9 = eq(rob[store_resp_idx].cmd, UInt<4>(0hb)) node _can_do_store_resp_T_10 = or(_can_do_store_resp_T_6, _can_do_store_resp_T_7) node _can_do_store_resp_T_11 = or(_can_do_store_resp_T_10, _can_do_store_resp_T_8) node _can_do_store_resp_T_12 = or(_can_do_store_resp_T_11, _can_do_store_resp_T_9) node _can_do_store_resp_T_13 = eq(rob[store_resp_idx].cmd, UInt<4>(0h8)) node _can_do_store_resp_T_14 = eq(rob[store_resp_idx].cmd, UInt<4>(0hc)) node _can_do_store_resp_T_15 = eq(rob[store_resp_idx].cmd, UInt<4>(0hd)) node _can_do_store_resp_T_16 = eq(rob[store_resp_idx].cmd, UInt<4>(0he)) node _can_do_store_resp_T_17 = eq(rob[store_resp_idx].cmd, UInt<4>(0hf)) node _can_do_store_resp_T_18 = or(_can_do_store_resp_T_13, _can_do_store_resp_T_14) node _can_do_store_resp_T_19 = or(_can_do_store_resp_T_18, _can_do_store_resp_T_15) node _can_do_store_resp_T_20 = or(_can_do_store_resp_T_19, _can_do_store_resp_T_16) node _can_do_store_resp_T_21 = or(_can_do_store_resp_T_20, _can_do_store_resp_T_17) node _can_do_store_resp_T_22 = or(_can_do_store_resp_T_12, _can_do_store_resp_T_21) node _can_do_store_resp_T_23 = or(_can_do_store_resp_T_5, _can_do_store_resp_T_22) node _can_do_store_resp_T_24 = and(_can_do_store_resp_T, _can_do_store_resp_T_23) node _can_do_store_resp_T_25 = eq(rob[store_resp_idx].cmd, UInt<1>(0h0)) node _can_do_store_resp_T_26 = eq(rob[store_resp_idx].cmd, UInt<5>(0h10)) node _can_do_store_resp_T_27 = eq(rob[store_resp_idx].cmd, UInt<3>(0h6)) node _can_do_store_resp_T_28 = eq(rob[store_resp_idx].cmd, UInt<3>(0h7)) node _can_do_store_resp_T_29 = or(_can_do_store_resp_T_25, _can_do_store_resp_T_26) node _can_do_store_resp_T_30 = or(_can_do_store_resp_T_29, _can_do_store_resp_T_27) node _can_do_store_resp_T_31 = or(_can_do_store_resp_T_30, _can_do_store_resp_T_28) node _can_do_store_resp_T_32 = eq(rob[store_resp_idx].cmd, UInt<3>(0h4)) node _can_do_store_resp_T_33 = eq(rob[store_resp_idx].cmd, UInt<4>(0h9)) node _can_do_store_resp_T_34 = eq(rob[store_resp_idx].cmd, UInt<4>(0ha)) node _can_do_store_resp_T_35 = eq(rob[store_resp_idx].cmd, UInt<4>(0hb)) node _can_do_store_resp_T_36 = or(_can_do_store_resp_T_32, _can_do_store_resp_T_33) node _can_do_store_resp_T_37 = or(_can_do_store_resp_T_36, _can_do_store_resp_T_34) node _can_do_store_resp_T_38 = or(_can_do_store_resp_T_37, _can_do_store_resp_T_35) node _can_do_store_resp_T_39 = eq(rob[store_resp_idx].cmd, UInt<4>(0h8)) node _can_do_store_resp_T_40 = eq(rob[store_resp_idx].cmd, UInt<4>(0hc)) node _can_do_store_resp_T_41 = eq(rob[store_resp_idx].cmd, UInt<4>(0hd)) node _can_do_store_resp_T_42 = eq(rob[store_resp_idx].cmd, UInt<4>(0he)) node _can_do_store_resp_T_43 = eq(rob[store_resp_idx].cmd, UInt<4>(0hf)) node _can_do_store_resp_T_44 = or(_can_do_store_resp_T_39, _can_do_store_resp_T_40) node _can_do_store_resp_T_45 = or(_can_do_store_resp_T_44, _can_do_store_resp_T_41) node _can_do_store_resp_T_46 = or(_can_do_store_resp_T_45, _can_do_store_resp_T_42) node _can_do_store_resp_T_47 = or(_can_do_store_resp_T_46, _can_do_store_resp_T_43) node _can_do_store_resp_T_48 = or(_can_do_store_resp_T_38, _can_do_store_resp_T_47) node _can_do_store_resp_T_49 = or(_can_do_store_resp_T_31, _can_do_store_resp_T_48) node _can_do_store_resp_T_50 = eq(_can_do_store_resp_T_49, UInt<1>(0h0)) node can_do_store_resp = and(_can_do_store_resp_T_24, _can_do_store_resp_T_50) node _T_28 = eq(io.lsu.exe[0].iresp.valid, UInt<1>(0h0)) node _T_29 = and(can_do_store_resp, _T_28) when _T_29 : connect rob_respd[store_resp_idx], UInt<1>(0h1) connect io.tracegen.resp.valid, UInt<1>(0h1) connect io.tracegen.resp.bits.tag, rob[store_resp_idx].tag when io.lsu.exe[0].iresp.valid : connect rob_respd[io.lsu.exe[0].iresp.bits.uop.rob_idx], UInt<1>(0h1) connect io.lsu.exe[0].fresp.ready, UInt<1>(0h1) connect io.lsu.exe[0].iresp.ready, UInt<1>(0h1) connect io.lsu.exception, UInt<1>(0h0) connect io.lsu.fence_dmem, UInt<1>(0h0) connect io.lsu.rob_pnr_idx, rob_tail connect io.lsu.commit_load_at_rob_head, UInt<1>(0h0) wire _io_lsu_brupdate_b1_WIRE : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>} connect _io_lsu_brupdate_b1_WIRE.mispredict_mask, UInt<4>(0h0) connect _io_lsu_brupdate_b1_WIRE.resolve_mask, UInt<4>(0h0) connect io.lsu.brupdate.b1, _io_lsu_brupdate_b1_WIRE invalidate io.lsu.brupdate.b2.uop.debug_tsrc invalidate io.lsu.brupdate.b2.uop.debug_fsrc invalidate io.lsu.brupdate.b2.uop.bp_xcpt_if invalidate io.lsu.brupdate.b2.uop.bp_debug_if invalidate io.lsu.brupdate.b2.uop.xcpt_ma_if invalidate io.lsu.brupdate.b2.uop.xcpt_ae_if invalidate io.lsu.brupdate.b2.uop.xcpt_pf_if invalidate io.lsu.brupdate.b2.uop.fp_single invalidate io.lsu.brupdate.b2.uop.fp_val invalidate io.lsu.brupdate.b2.uop.frs3_en invalidate io.lsu.brupdate.b2.uop.lrs2_rtype invalidate io.lsu.brupdate.b2.uop.lrs1_rtype invalidate io.lsu.brupdate.b2.uop.dst_rtype invalidate io.lsu.brupdate.b2.uop.ldst_val invalidate io.lsu.brupdate.b2.uop.lrs3 invalidate io.lsu.brupdate.b2.uop.lrs2 invalidate io.lsu.brupdate.b2.uop.lrs1 invalidate io.lsu.brupdate.b2.uop.ldst invalidate io.lsu.brupdate.b2.uop.ldst_is_rs1 invalidate io.lsu.brupdate.b2.uop.flush_on_commit invalidate io.lsu.brupdate.b2.uop.is_unique invalidate io.lsu.brupdate.b2.uop.is_sys_pc2epc invalidate io.lsu.brupdate.b2.uop.uses_stq invalidate io.lsu.brupdate.b2.uop.uses_ldq invalidate io.lsu.brupdate.b2.uop.is_amo invalidate io.lsu.brupdate.b2.uop.is_fencei invalidate io.lsu.brupdate.b2.uop.is_fence invalidate io.lsu.brupdate.b2.uop.mem_signed invalidate io.lsu.brupdate.b2.uop.mem_size invalidate io.lsu.brupdate.b2.uop.mem_cmd invalidate io.lsu.brupdate.b2.uop.bypassable invalidate io.lsu.brupdate.b2.uop.exc_cause invalidate io.lsu.brupdate.b2.uop.exception invalidate io.lsu.brupdate.b2.uop.stale_pdst invalidate io.lsu.brupdate.b2.uop.ppred_busy invalidate io.lsu.brupdate.b2.uop.prs3_busy invalidate io.lsu.brupdate.b2.uop.prs2_busy invalidate io.lsu.brupdate.b2.uop.prs1_busy invalidate io.lsu.brupdate.b2.uop.ppred invalidate io.lsu.brupdate.b2.uop.prs3 invalidate io.lsu.brupdate.b2.uop.prs2 invalidate io.lsu.brupdate.b2.uop.prs1 invalidate io.lsu.brupdate.b2.uop.pdst invalidate io.lsu.brupdate.b2.uop.rxq_idx invalidate io.lsu.brupdate.b2.uop.stq_idx invalidate io.lsu.brupdate.b2.uop.ldq_idx invalidate io.lsu.brupdate.b2.uop.rob_idx invalidate io.lsu.brupdate.b2.uop.csr_addr invalidate io.lsu.brupdate.b2.uop.imm_packed invalidate io.lsu.brupdate.b2.uop.taken invalidate io.lsu.brupdate.b2.uop.pc_lob invalidate io.lsu.brupdate.b2.uop.edge_inst invalidate io.lsu.brupdate.b2.uop.ftq_idx invalidate io.lsu.brupdate.b2.uop.br_tag invalidate io.lsu.brupdate.b2.uop.br_mask invalidate io.lsu.brupdate.b2.uop.is_sfb invalidate io.lsu.brupdate.b2.uop.is_jal invalidate io.lsu.brupdate.b2.uop.is_jalr invalidate io.lsu.brupdate.b2.uop.is_br invalidate io.lsu.brupdate.b2.uop.iw_p2_poisoned invalidate io.lsu.brupdate.b2.uop.iw_p1_poisoned invalidate io.lsu.brupdate.b2.uop.iw_state invalidate io.lsu.brupdate.b2.uop.ctrl.is_std invalidate io.lsu.brupdate.b2.uop.ctrl.is_sta invalidate io.lsu.brupdate.b2.uop.ctrl.is_load invalidate io.lsu.brupdate.b2.uop.ctrl.csr_cmd invalidate io.lsu.brupdate.b2.uop.ctrl.fcn_dw invalidate io.lsu.brupdate.b2.uop.ctrl.op_fcn invalidate io.lsu.brupdate.b2.uop.ctrl.imm_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op2_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op1_sel invalidate io.lsu.brupdate.b2.uop.ctrl.br_type invalidate io.lsu.brupdate.b2.uop.fu_code invalidate io.lsu.brupdate.b2.uop.iq_type invalidate io.lsu.brupdate.b2.uop.debug_pc invalidate io.lsu.brupdate.b2.uop.is_rvc invalidate io.lsu.brupdate.b2.uop.debug_inst invalidate io.lsu.brupdate.b2.uop.inst invalidate io.lsu.brupdate.b2.uop.uopc connect io.lsu.brupdate.b2.mispredict, UInt<1>(0h0) connect io.lsu.brupdate.b2.taken, UInt<1>(0h0) connect io.lsu.brupdate.b2.cfi_type, UInt<1>(0h0) connect io.lsu.brupdate.b2.pc_sel, UInt<1>(0h0) connect io.lsu.brupdate.b2.jalr_target, UInt<1>(0h0) connect io.lsu.brupdate.b2.target_offset, asSInt(UInt<2>(0h0)) connect io.lsu.rob_head_idx, rob_head node _io_tracegen_ordered_T = and(ready_for_amo, io.lsu.fencei_rdy) connect io.tracegen.ordered, _io_tracegen_ordered_T	module BoomLSUShim_1( // @[tracegen.scala:20:7] input clock, // @[tracegen.scala:20:7] input reset, // @[tracegen.scala:20:7] output io_lsu_exe_0_req_valid, // @[tracegen.scala:22:14] output [6:0] io_lsu_exe_0_req_bits_uop_uopc, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] output [5:0] io_lsu_exe_0_req_bits_uop_rob_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_exe_0_req_bits_uop_ldq_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_exe_0_req_bits_uop_stq_idx, // @[tracegen.scala:22:14] output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_is_amo, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_uses_ldq, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_uses_stq, // @[tracegen.scala:22:14] output [63:0] io_lsu_exe_0_req_bits_data, // @[tracegen.scala:22:14] output [33:0] io_lsu_exe_0_req_bits_addr, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_inst, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_rvc, // @[tracegen.scala:22:14] input [33:0] io_lsu_exe_0_iresp_bits_uop_debug_pc, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type, // @[tracegen.scala:22:14] input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_br, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_jalr, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_jal, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_sfb, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_br_mask, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_br_tag, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_edge_inst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_taken, // @[tracegen.scala:22:14] input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed, // @[tracegen.scala:22:14] input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_rob_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_stq_idx, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_pdst, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs1, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs2, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs3, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ppred, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_prs1_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_prs2_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_prs3_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ppred_busy, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_exception, // @[tracegen.scala:22:14] input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_bypassable, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_mem_signed, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_fence, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_fencei, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_amo, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_uses_ldq, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_uses_stq, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_unique, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_flush_on_commit, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ldst_val, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_frs3_en, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_fp_val, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_fp_single, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_bp_debug_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc, // @[tracegen.scala:22:14] input [63:0] io_lsu_exe_0_iresp_bits_data, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_inst, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_rvc, // @[tracegen.scala:22:14] input [33:0] io_lsu_exe_0_fresp_bits_uop_debug_pc, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type, // @[tracegen.scala:22:14] input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_br, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_jalr, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_jal, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_sfb, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_br_mask, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_br_tag, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_edge_inst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_taken, // @[tracegen.scala:22:14] input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed, // @[tracegen.scala:22:14] input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_rob_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_stq_idx, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_pdst, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs1, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs2, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs3, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ppred, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_prs1_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_prs2_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_prs3_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ppred_busy, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_exception, // @[tracegen.scala:22:14] input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_bypassable, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_mem_signed, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_fence, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_fencei, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_amo, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_uses_ldq, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_uses_stq, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_unique, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_flush_on_commit, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ldst_val, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_frs3_en, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_fp_val, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_fp_single, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_bp_debug_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc, // @[tracegen.scala:22:14] input [64:0] io_lsu_exe_0_fresp_bits_data, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_valid, // @[tracegen.scala:22:14] output [6:0] io_lsu_dis_uops_0_bits_uopc, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_ctrl_is_load, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_ctrl_is_sta, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_ctrl_is_std, // @[tracegen.scala:22:14] output [5:0] io_lsu_dis_uops_0_bits_rob_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_dis_uops_0_bits_stq_idx, // @[tracegen.scala:22:14] output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_is_amo, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_uses_ldq, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_uses_stq, // @[tracegen.scala:22:14] input [3:0] io_lsu_dis_ldq_idx_0, // @[tracegen.scala:22:14] input [3:0] io_lsu_dis_stq_idx_0, // @[tracegen.scala:22:14] input io_lsu_ldq_full_0, // @[tracegen.scala:22:14] input io_lsu_stq_full_0, // @[tracegen.scala:22:14] input io_lsu_fp_stdata_ready, // @[tracegen.scala:22:14] output io_lsu_commit_valids_0, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_uopc, // @[tracegen.scala:22:14] output [31:0] io_lsu_commit_uops_0_inst, // @[tracegen.scala:22:14] output [31:0] io_lsu_commit_uops_0_debug_inst, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_rvc, // @[tracegen.scala:22:14] output [33:0] io_lsu_commit_uops_0_debug_pc, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_iq_type, // @[tracegen.scala:22:14] output [9:0] io_lsu_commit_uops_0_fu_code, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ctrl_br_type, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel, // @[tracegen.scala:22:14] output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_fcn_dw, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_is_load, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_is_sta, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_is_std, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_iw_state, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_iw_p1_poisoned, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_iw_p2_poisoned, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_br, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_jalr, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_jal, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_sfb, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_br_mask, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_br_tag, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ftq_idx, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_edge_inst, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_pc_lob, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_taken, // @[tracegen.scala:22:14] output [19:0] io_lsu_commit_uops_0_imm_packed, // @[tracegen.scala:22:14] output [11:0] io_lsu_commit_uops_0_csr_addr, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_rob_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ldq_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_stq_idx, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_pdst, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_prs1, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_prs2, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_prs3, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ppred, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_prs1_busy, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_prs2_busy, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_prs3_busy, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ppred_busy, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_stale_pdst, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_exception, // @[tracegen.scala:22:14] output [63:0] io_lsu_commit_uops_0_exc_cause, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_bypassable, // @[tracegen.scala:22:14] output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_mem_size, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_mem_signed, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_fence, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_fencei, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_amo, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_uses_ldq, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_uses_stq, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_sys_pc2epc, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_unique, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_flush_on_commit, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ldst_is_rs1, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_ldst, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_lrs1, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_lrs2, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_lrs3, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ldst_val, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_frs3_en, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_fp_val, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_fp_single, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_xcpt_pf_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_xcpt_ae_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_xcpt_ma_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_bp_debug_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_bp_xcpt_if, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_debug_fsrc, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_debug_tsrc, // @[tracegen.scala:22:14] input io_lsu_clr_bsy_0_valid, // @[tracegen.scala:22:14] input [5:0] io_lsu_clr_bsy_0_bits, // @[tracegen.scala:22:14] input io_lsu_clr_bsy_1_valid, // @[tracegen.scala:22:14] input [5:0] io_lsu_clr_bsy_1_bits, // @[tracegen.scala:22:14] input [5:0] io_lsu_clr_unsafe_0_bits, // @[tracegen.scala:22:14] input io_lsu_spec_ld_wakeup_0_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_spec_ld_wakeup_0_bits, // @[tracegen.scala:22:14] input io_lsu_ld_miss, // @[tracegen.scala:22:14] output [5:0] io_lsu_rob_pnr_idx, // @[tracegen.scala:22:14] output [5:0] io_lsu_rob_head_idx, // @[tracegen.scala:22:14] input io_lsu_fencei_rdy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_uopc, // @[tracegen.scala:22:14] input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[tracegen.scala:22:14] input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_rvc, // @[tracegen.scala:22:14] input [33:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_iq_type, // @[tracegen.scala:22:14] input [9:0] io_lsu_lxcpt_bits_uop_fu_code, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14] input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_iw_state, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_br, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_jalr, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_jal, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_sfb, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_br_mask, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_br_tag, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_edge_inst, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_taken, // @[tracegen.scala:22:14] input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[tracegen.scala:22:14] input [11:0] io_lsu_lxcpt_bits_uop_csr_addr, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_pdst, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_prs1, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_prs2, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_prs3, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ppred, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_prs1_busy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_prs2_busy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_prs3_busy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ppred_busy, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_exception, // @[tracegen.scala:22:14] input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_bypassable, // @[tracegen.scala:22:14] input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_mem_signed, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_fence, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_fencei, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_amo, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_uses_ldq, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_uses_stq, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_unique, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ldst_val, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_frs3_en, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_fp_val, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_fp_single, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[tracegen.scala:22:14] input [4:0] io_lsu_lxcpt_bits_cause, // @[tracegen.scala:22:14] input [33:0] io_lsu_lxcpt_bits_badvaddr, // @[tracegen.scala:22:14] input io_lsu_perf_acquire, // @[tracegen.scala:22:14] input io_lsu_perf_release, // @[tracegen.scala:22:14] output io_tracegen_req_ready, // @[tracegen.scala:22:14] input io_tracegen_req_valid, // @[tracegen.scala:22:14] input [33:0] io_tracegen_req_bits_addr, // @[tracegen.scala:22:14] input [5:0] io_tracegen_req_bits_tag, // @[tracegen.scala:22:14] input [4:0] io_tracegen_req_bits_cmd, // @[tracegen.scala:22:14] input [63:0] io_tracegen_req_bits_data, // @[tracegen.scala:22:14] input [63:0] io_tracegen_s1_data_data, // @[tracegen.scala:22:14] output io_tracegen_resp_valid, // @[tracegen.scala:22:14] output [5:0] io_tracegen_resp_bits_tag, // @[tracegen.scala:22:14] output [1:0] io_tracegen_resp_bits_size, // @[tracegen.scala:22:14] output [63:0] io_tracegen_resp_bits_data, // @[tracegen.scala:22:14] output io_tracegen_ordered // @[tracegen.scala:22:14] ); wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc; // @[tracegen.scala:20:7] wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[tracegen.scala:20:7] wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[tracegen.scala:20:7] wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready; // @[tracegen.scala:20:7] wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[tracegen.scala:20:7] wire [5:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[tracegen.scala:20:7] wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[tracegen.scala:20:7] wire [5:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[tracegen.scala:20:7] wire [5:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[tracegen.scala:20:7] wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits; // @[tracegen.scala:20:7] wire io_lsu_ld_miss_0 = io_lsu_ld_miss; // @[tracegen.scala:20:7] wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc; // @[tracegen.scala:20:7] wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[tracegen.scala:20:7] wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:20:7] wire [33:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type; // @[tracegen.scala:20:7] wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7] wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[tracegen.scala:20:7] wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:20:7] wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[tracegen.scala:20:7] wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable; // @[tracegen.scala:20:7] wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:20:7] wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[tracegen.scala:20:7] wire [33:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[tracegen.scala:20:7] wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[tracegen.scala:20:7] wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[tracegen.scala:20:7] wire io_tracegen_req_valid_0 = io_tracegen_req_valid; // @[tracegen.scala:20:7] wire [33:0] io_tracegen_req_bits_addr_0 = io_tracegen_req_bits_addr; // @[tracegen.scala:20:7] wire [5:0] io_tracegen_req_bits_tag_0 = io_tracegen_req_bits_tag; // @[tracegen.scala:20:7] wire [4:0] io_tracegen_req_bits_cmd_0 = io_tracegen_req_bits_cmd; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_req_bits_data_0 = io_tracegen_req_bits_data; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_s1_data_data_0 = io_tracegen_s1_data_data; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_dis_uops_0_bits_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_dis_uops_0_bits_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_commit_uops_0_inst_0 = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_commit_uops_0_debug_inst_0 = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_commit_debug_insts_0 = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_tracegen_s2_paddr = 32'h0; // @[tracegen.scala:20:7] wire [31:0] _tracegen_uop_WIRE_inst = 32'h0; // @[tracegen.scala:57:45] wire [31:0] _tracegen_uop_WIRE_debug_inst = 32'h0; // @[tracegen.scala:57:45] wire [31:0] tracegen_uop_inst = 32'h0; // @[tracegen.scala:57:30] wire [31:0] tracegen_uop_debug_inst = 32'h0; // @[tracegen.scala:57:30] wire io_lsu_exe_0_req_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_mxcpt_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs2 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_asid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_arch_valids_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_rvc_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_fcn_dw_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_iw_p1_poisoned_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_iw_p2_poisoned_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_br_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_jalr_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_jal_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_sfb_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_edge_inst_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_taken_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_prs1_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_prs2_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_prs3_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ppred_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_exception_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_bypassable_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_mem_signed_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_fence_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_fencei_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_sys_pc2epc_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_unique_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_flush_on_commit_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ldst_is_rs1_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ldst_val_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_frs3_en_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_fp_val_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_fp_single_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_xcpt_pf_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_xcpt_ae_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_xcpt_ma_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_bp_debug_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_bp_xcpt_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_rbk_valids_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_rollback = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_load_at_rob_head = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fence_dmem = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_mispredict = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_tsc_reg = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_perf_tlbMiss = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_signed = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_dv = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_phys = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_no_resp = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_no_alloc = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_no_xcpt = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s1_kill = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_nack = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_nack_cause_raw = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_kill = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_uncached = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_signed = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_dv = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_replay = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_has_data = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_replay_next = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ma_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ma_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_pf_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_pf_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_gf_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_gf_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ae_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ae_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_gpa_is_pte = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_store_pending = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_acquire = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_release = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_grant = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_tlbMiss = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_blocked = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_canAcceptStoreThenLoad = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_canAcceptStoreThenRMW = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_canAcceptLoadThenLoad = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_storeBufferEmptyAfterLoad = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_storeBufferEmptyAfterStore = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_clock_enabled = 1'h0; // @[tracegen.scala:20:7] wire _rob_bsy_WIRE_0 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_1 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_2 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_3 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_4 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_5 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_6 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_7 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_8 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_9 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_10 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_11 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_12 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_13 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_14 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_15 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_16 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_17 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_18 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_19 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_20 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_21 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_22 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_23 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_24 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_25 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_26 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_27 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_28 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_29 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_30 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_31 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_32 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_33 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_34 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_35 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_36 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_37 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_38 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_39 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_40 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_41 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_42 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_43 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_44 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_45 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_46 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_47 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_48 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_49 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_50 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_51 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_52 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_53 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_54 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_55 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_56 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_57 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_58 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_59 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_60 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_61 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_62 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_63 = 1'h0; // @[tracegen.scala:35:33] wire _tracegen_uop_WIRE_is_rvc = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_is_load = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_is_sta = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_is_std = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_iw_p1_poisoned = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_iw_p2_poisoned = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_br = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_jalr = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_jal = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_sfb = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_edge_inst = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_taken = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_prs1_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_prs2_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_prs3_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ppred_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_exception = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_bypassable = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_mem_signed = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_fence = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_fencei = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_amo = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_uses_ldq = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_uses_stq = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_sys_pc2epc = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_unique = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_flush_on_commit = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ldst_is_rs1 = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ldst_val = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_frs3_en = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_fp_val = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_fp_single = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_xcpt_pf_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_xcpt_ae_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_xcpt_ma_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_bp_debug_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_bp_xcpt_if = 1'h0; // @[tracegen.scala:57:45] wire tracegen_uop_is_rvc = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_br = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_jalr = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_jal = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_sfb = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_edge_inst = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_taken = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_prs1_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_prs2_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_prs3_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ppred_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_exception = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_bypassable = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_mem_signed = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_fence = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_fencei = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_unique = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_flush_on_commit = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ldst_val = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_frs3_en = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_fp_val = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_fp_single = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_bp_debug_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:57:30] wire [33:0] io_lsu_exe_0_req_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_dis_uops_0_bits_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_fp_stdata_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_commit_uops_0_debug_pc_0 = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_tracegen_resp_bits_addr = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_tracegen_s2_gpa = 34'h0; // @[tracegen.scala:20:7] wire [33:0] _tracegen_uop_WIRE_debug_pc = 34'h0; // @[tracegen.scala:57:45] wire [33:0] tracegen_uop_debug_pc = 34'h0; // @[tracegen.scala:57:30] wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_iq_type_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] _tracegen_uop_WIRE_iq_type = 3'h0; // @[tracegen.scala:57:45] wire [2:0] _tracegen_uop_WIRE_ctrl_op2_sel = 3'h0; // @[tracegen.scala:57:45] wire [2:0] _tracegen_uop_WIRE_ctrl_imm_sel = 3'h0; // @[tracegen.scala:57:45] wire [2:0] _tracegen_uop_WIRE_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:57:45] wire [2:0] tracegen_uop_iq_type = 3'h0; // @[tracegen.scala:57:30] wire [2:0] tracegen_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:57:30] wire [2:0] tracegen_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:57:30] wire [2:0] tracegen_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:57:30] wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_dis_uops_0_bits_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_commit_uops_0_fu_code_0 = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_brupdate_b2_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] _tracegen_uop_WIRE_fu_code = 10'h0; // @[tracegen.scala:57:45] wire [9:0] tracegen_uop_fu_code = 10'h0; // @[tracegen.scala:57:30] wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_br_mask_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ftq_idx_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ppred_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] _tracegen_uop_WIRE_ctrl_br_type = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_br_mask = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_ftq_idx = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_ldq_idx = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_stq_idx = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_ppred = 4'h0; // @[tracegen.scala:57:45] wire [3:0] tracegen_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_br_mask = 4'h0; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_ftq_idx = 4'h0; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_ppred = 4'h0; // @[tracegen.scala:57:30] wire [3:0] _io_lsu_brupdate_b1_WIRE_resolve_mask = 4'h0; // @[tracegen.scala:153:39] wire [3:0] _io_lsu_brupdate_b1_WIRE_mispredict_mask = 4'h0; // @[tracegen.scala:153:39] wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_iw_state_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_br_tag_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_rxq_idx_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_dst_rtype_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_target_offset = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_tracegen_resp_bits_dprv = 2'h0; // @[tracegen.scala:20:7] wire [1:0] _tracegen_uop_WIRE_ctrl_op1_sel = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_iw_state = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_br_tag = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_rxq_idx = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_mem_size = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_dst_rtype = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_lrs1_rtype = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_lrs2_rtype = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_debug_fsrc = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_debug_tsrc = 2'h0; // @[tracegen.scala:57:45] wire [1:0] tracegen_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_iw_state = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_br_tag = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_rxq_idx = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_dst_rtype = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_debug_fsrc = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_debug_tsrc = 2'h0; // @[tracegen.scala:57:30] wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0 = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_commit_fflags_bits = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_tracegen_resp_bits_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] _tracegen_uop_WIRE_ctrl_op_fcn = 5'h0; // @[tracegen.scala:57:45] wire [4:0] _tracegen_uop_WIRE_mem_cmd = 5'h0; // @[tracegen.scala:57:45] wire [4:0] tracegen_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:57:30] wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_pc_lob_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_ldst_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_lrs1_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_lrs2_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_lrs3_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] _tracegen_uop_WIRE_pc_lob = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_rob_idx = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_ldst = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_lrs1 = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_lrs2 = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_lrs3 = 6'h0; // @[tracegen.scala:57:45] wire [5:0] tracegen_uop_pc_lob = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_ldst = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_lrs1 = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_lrs2 = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_lrs3 = 6'h0; // @[tracegen.scala:57:30] wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_dis_uops_0_bits_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_commit_uops_0_imm_packed_0 = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] _tracegen_uop_WIRE_imm_packed = 20'h0; // @[tracegen.scala:57:45] wire [19:0] tracegen_uop_imm_packed = 20'h0; // @[tracegen.scala:57:30] wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_dis_uops_0_bits_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_commit_uops_0_csr_addr_0 = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_brupdate_b2_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] _tracegen_uop_WIRE_csr_addr = 12'h0; // @[tracegen.scala:57:45] wire [11:0] tracegen_uop_csr_addr = 12'h0; // @[tracegen.scala:57:30] wire [6:0] io_lsu_exe_0_req_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_pdst_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_prs1_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_prs2_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_prs3_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_stale_pdst_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] _tracegen_uop_WIRE_uopc = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_pdst = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_prs1 = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_prs2 = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_prs3 = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_stale_pdst = 7'h0; // @[tracegen.scala:57:45] wire [6:0] tracegen_uop_pdst = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_prs1 = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_prs2 = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_prs3 = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_stale_pdst = 7'h0; // @[tracegen.scala:57:30] wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_dis_uops_0_bits_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_fp_stdata_bits_data = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_commit_uops_0_exc_cause_0 = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_commit_debug_wdata_0 = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_data_word_bypass = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_data_raw = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_store_data = 64'h0; // @[tracegen.scala:20:7] wire [63:0] _tracegen_uop_WIRE_exc_cause = 64'h0; // @[tracegen.scala:57:45] wire [63:0] tracegen_uop_exc_cause = 64'h0; // @[tracegen.scala:57:30] wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_mem_size = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_mem_size_0 = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_tracegen_req_bits_size = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_tracegen_req_bits_dprv = 2'h3; // @[tracegen.scala:20:7] wire [1:0] tracegen_uop_mem_size = 2'h3; // @[tracegen.scala:57:30] wire [7:0] io_tracegen_req_bits_mask = 8'hFF; // @[tracegen.scala:20:7] wire [7:0] io_tracegen_s1_data_mask = 8'hFF; // @[tracegen.scala:20:7] wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits = 25'h0; // @[tracegen.scala:20:7] wire [32:0] io_lsu_exe_0_req_bits_sfence_bits_addr = 33'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_ready = 1'h1; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_ready = 1'h1; // @[tracegen.scala:20:7] wire io_tracegen_keep_clock_enabled = 1'h1; // @[tracegen.scala:20:7] wire _rob_respd_T_1 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_2 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_3 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_4 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_5 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_6 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_7 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_8 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_9 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_10 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_11 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_12 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_13 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_14 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_15 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_16 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_17 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_18 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_19 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_20 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_21 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_22 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_23 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_24 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_25 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_26 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_27 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_28 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_29 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_30 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_31 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_32 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_33 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_34 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_35 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_36 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_37 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_38 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_39 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_40 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_41 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_42 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_43 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_44 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_45 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_46 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_47 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_48 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_49 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_50 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_51 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_52 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_53 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_54 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_55 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_56 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_57 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_58 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_59 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_60 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_61 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_62 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_63 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_64 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_WIRE_0 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_1 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_2 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_3 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_4 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_5 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_6 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_7 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_8 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_9 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_10 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_11 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_12 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_13 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_14 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_15 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_16 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_17 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_18 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_19 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_20 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_21 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_22 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_23 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_24 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_25 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_26 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_27 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_28 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_29 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_30 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_31 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_32 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_33 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_34 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_35 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_36 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_37 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_38 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_39 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_40 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_41 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_42 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_43 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_44 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_45 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_46 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_47 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_48 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_49 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_50 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_51 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_52 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_53 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_54 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_55 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_56 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_57 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_58 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_59 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_60 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_61 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_62 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_63 = 1'h1; // @[tracegen.scala:33:34] wire [7:0] io_tracegen_resp_bits_mask = 8'h0; // @[tracegen.scala:20:7] wire [63:0] _rob_respd_T = 64'hFFFFFFFFFFFFFFFF; // @[tracegen.scala:33:36] wire [1:0] io_tracegen_resp_bits_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size_0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_data_0 = io_lsu_exe_0_iresp_bits_data_0; // @[tracegen.scala:20:7] wire _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire [6:0] tracegen_uop_uopc; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_is_load; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_is_sta; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_is_std; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_rob_idx; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_ldq_idx; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_stq_idx; // @[tracegen.scala:57:30] wire [4:0] tracegen_uop_mem_cmd; // @[tracegen.scala:57:30] wire tracegen_uop_is_amo; // @[tracegen.scala:57:30] wire tracegen_uop_uses_ldq; // @[tracegen.scala:57:30] wire tracegen_uop_uses_stq; // @[tracegen.scala:57:30] assign tracegen_uop_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[tracegen.scala:20:7, :57:30] assign tracegen_uop_stq_idx = io_lsu_dis_stq_idx_0_0; // @[tracegen.scala:20:7, :57:30] wire _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:95:75] wire _io_tracegen_req_ready_T_86; // @[tracegen.scala:53:63] assign tracegen_uop_mem_cmd = io_tracegen_req_bits_cmd_0; // @[tracegen.scala:20:7, :57:30] wire _io_tracegen_ordered_T; // @[tracegen.scala:164:40] wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_rob_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_stq_idx_0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_amo_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_uses_ldq_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_uses_stq_0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_req_bits_data_0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_req_bits_addr_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_valid_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_is_load_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_is_std_0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_uopc_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_amo_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_valid_0; // @[tracegen.scala:20:7] wire io_lsu_commit_valids_0_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_is_load_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_is_sta_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_is_std_0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_uopc_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_rob_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_stq_idx_0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_amo_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_uses_ldq_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_uses_stq_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_rob_pnr_idx_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_rob_head_idx_0; // @[tracegen.scala:20:7] wire io_tracegen_req_ready_0; // @[tracegen.scala:20:7] wire [5:0] io_tracegen_resp_bits_tag_0; // @[tracegen.scala:20:7] wire io_tracegen_resp_valid_0; // @[tracegen.scala:20:7] wire io_tracegen_ordered_0; // @[tracegen.scala:20:7] reg [33:0] rob_0_addr; // @[tracegen.scala:32:16] reg [5:0] rob_0_tag; // @[tracegen.scala:32:16] reg [4:0] rob_0_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_0_data; // @[tracegen.scala:32:16] reg [33:0] rob_1_addr; // @[tracegen.scala:32:16] reg [5:0] rob_1_tag; // @[tracegen.scala:32:16] reg [4:0] rob_1_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_1_data; // @[tracegen.scala:32:16] reg [33:0] rob_2_addr; // @[tracegen.scala:32:16] reg [5:0] rob_2_tag; // @[tracegen.scala:32:16] reg [4:0] rob_2_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_2_data; // @[tracegen.scala:32:16] reg [33:0] rob_3_addr; // @[tracegen.scala:32:16] reg [5:0] rob_3_tag; // @[tracegen.scala:32:16] reg [4:0] rob_3_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_3_data; // @[tracegen.scala:32:16] reg [33:0] rob_4_addr; // @[tracegen.scala:32:16] reg [5:0] rob_4_tag; // @[tracegen.scala:32:16] reg [4:0] rob_4_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_4_data; // @[tracegen.scala:32:16] reg [33:0] rob_5_addr; // @[tracegen.scala:32:16] reg [5:0] rob_5_tag; // @[tracegen.scala:32:16] reg [4:0] rob_5_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_5_data; // @[tracegen.scala:32:16] reg [33:0] rob_6_addr; // @[tracegen.scala:32:16] reg [5:0] rob_6_tag; // @[tracegen.scala:32:16] reg [4:0] rob_6_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_6_data; // @[tracegen.scala:32:16] reg [33:0] rob_7_addr; // @[tracegen.scala:32:16] reg [5:0] rob_7_tag; // @[tracegen.scala:32:16] reg [4:0] rob_7_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_7_data; // @[tracegen.scala:32:16] reg [33:0] rob_8_addr; // @[tracegen.scala:32:16] reg [5:0] rob_8_tag; // @[tracegen.scala:32:16] reg [4:0] rob_8_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_8_data; // @[tracegen.scala:32:16] reg [33:0] rob_9_addr; // @[tracegen.scala:32:16] reg [5:0] rob_9_tag; // @[tracegen.scala:32:16] reg [4:0] rob_9_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_9_data; // @[tracegen.scala:32:16] reg [33:0] rob_10_addr; // @[tracegen.scala:32:16] reg [5:0] rob_10_tag; // @[tracegen.scala:32:16] reg [4:0] rob_10_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_10_data; // @[tracegen.scala:32:16] reg [33:0] rob_11_addr; // @[tracegen.scala:32:16] reg [5:0] rob_11_tag; // @[tracegen.scala:32:16] reg [4:0] rob_11_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_11_data; // @[tracegen.scala:32:16] reg [33:0] rob_12_addr; // @[tracegen.scala:32:16] reg [5:0] rob_12_tag; // @[tracegen.scala:32:16] reg [4:0] rob_12_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_12_data; // @[tracegen.scala:32:16] reg [33:0] rob_13_addr; // @[tracegen.scala:32:16] reg [5:0] rob_13_tag; // @[tracegen.scala:32:16] reg [4:0] rob_13_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_13_data; // @[tracegen.scala:32:16] reg [33:0] rob_14_addr; // @[tracegen.scala:32:16] reg [5:0] rob_14_tag; // @[tracegen.scala:32:16] reg [4:0] rob_14_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_14_data; // @[tracegen.scala:32:16] reg [33:0] rob_15_addr; // @[tracegen.scala:32:16] reg [5:0] rob_15_tag; // @[tracegen.scala:32:16] reg [4:0] rob_15_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_15_data; // @[tracegen.scala:32:16] reg [33:0] rob_16_addr; // @[tracegen.scala:32:16] reg [5:0] rob_16_tag; // @[tracegen.scala:32:16] reg [4:0] rob_16_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_16_data; // @[tracegen.scala:32:16] reg [33:0] rob_17_addr; // @[tracegen.scala:32:16] reg [5:0] rob_17_tag; // @[tracegen.scala:32:16] reg [4:0] rob_17_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_17_data; // @[tracegen.scala:32:16] reg [33:0] rob_18_addr; // @[tracegen.scala:32:16] reg [5:0] rob_18_tag; // @[tracegen.scala:32:16] reg [4:0] rob_18_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_18_data; // @[tracegen.scala:32:16] reg [33:0] rob_19_addr; // @[tracegen.scala:32:16] reg [5:0] rob_19_tag; // @[tracegen.scala:32:16] reg [4:0] rob_19_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_19_data; // @[tracegen.scala:32:16] reg [33:0] rob_20_addr; // @[tracegen.scala:32:16] reg [5:0] rob_20_tag; // @[tracegen.scala:32:16] reg [4:0] rob_20_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_20_data; // @[tracegen.scala:32:16] reg [33:0] rob_21_addr; // @[tracegen.scala:32:16] reg [5:0] rob_21_tag; // @[tracegen.scala:32:16] reg [4:0] rob_21_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_21_data; // @[tracegen.scala:32:16] reg [33:0] rob_22_addr; // @[tracegen.scala:32:16] reg [5:0] rob_22_tag; // @[tracegen.scala:32:16] reg [4:0] rob_22_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_22_data; // @[tracegen.scala:32:16] reg [33:0] rob_23_addr; // @[tracegen.scala:32:16] reg [5:0] rob_23_tag; // @[tracegen.scala:32:16] reg [4:0] rob_23_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_23_data; // @[tracegen.scala:32:16] reg [33:0] rob_24_addr; // @[tracegen.scala:32:16] reg [5:0] rob_24_tag; // @[tracegen.scala:32:16] reg [4:0] rob_24_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_24_data; // @[tracegen.scala:32:16] reg [33:0] rob_25_addr; // @[tracegen.scala:32:16] reg [5:0] rob_25_tag; // @[tracegen.scala:32:16] reg [4:0] rob_25_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_25_data; // @[tracegen.scala:32:16] reg [33:0] rob_26_addr; // @[tracegen.scala:32:16] reg [5:0] rob_26_tag; // @[tracegen.scala:32:16] reg [4:0] rob_26_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_26_data; // @[tracegen.scala:32:16] reg [33:0] rob_27_addr; // @[tracegen.scala:32:16] reg [5:0] rob_27_tag; // @[tracegen.scala:32:16] reg [4:0] rob_27_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_27_data; // @[tracegen.scala:32:16] reg [33:0] rob_28_addr; // @[tracegen.scala:32:16] reg [5:0] rob_28_tag; // @[tracegen.scala:32:16] reg [4:0] rob_28_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_28_data; // @[tracegen.scala:32:16] reg [33:0] rob_29_addr; // @[tracegen.scala:32:16] reg [5:0] rob_29_tag; // @[tracegen.scala:32:16] reg [4:0] rob_29_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_29_data; // @[tracegen.scala:32:16] reg [33:0] rob_30_addr; // @[tracegen.scala:32:16] reg [5:0] rob_30_tag; // @[tracegen.scala:32:16] reg [4:0] rob_30_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_30_data; // @[tracegen.scala:32:16] reg [33:0] rob_31_addr; // @[tracegen.scala:32:16] reg [5:0] rob_31_tag; // @[tracegen.scala:32:16] reg [4:0] rob_31_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_31_data; // @[tracegen.scala:32:16] reg [33:0] rob_32_addr; // @[tracegen.scala:32:16] reg [5:0] rob_32_tag; // @[tracegen.scala:32:16] reg [4:0] rob_32_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_32_data; // @[tracegen.scala:32:16] reg [33:0] rob_33_addr; // @[tracegen.scala:32:16] reg [5:0] rob_33_tag; // @[tracegen.scala:32:16] reg [4:0] rob_33_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_33_data; // @[tracegen.scala:32:16] reg [33:0] rob_34_addr; // @[tracegen.scala:32:16] reg [5:0] rob_34_tag; // @[tracegen.scala:32:16] reg [4:0] rob_34_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_34_data; // @[tracegen.scala:32:16] reg [33:0] rob_35_addr; // @[tracegen.scala:32:16] reg [5:0] rob_35_tag; // @[tracegen.scala:32:16] reg [4:0] rob_35_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_35_data; // @[tracegen.scala:32:16] reg [33:0] rob_36_addr; // @[tracegen.scala:32:16] reg [5:0] rob_36_tag; // @[tracegen.scala:32:16] reg [4:0] rob_36_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_36_data; // @[tracegen.scala:32:16] reg [33:0] rob_37_addr; // @[tracegen.scala:32:16] reg [5:0] rob_37_tag; // @[tracegen.scala:32:16] reg [4:0] rob_37_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_37_data; // @[tracegen.scala:32:16] reg [33:0] rob_38_addr; // @[tracegen.scala:32:16] reg [5:0] rob_38_tag; // @[tracegen.scala:32:16] reg [4:0] rob_38_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_38_data; // @[tracegen.scala:32:16] reg [33:0] rob_39_addr; // @[tracegen.scala:32:16] reg [5:0] rob_39_tag; // @[tracegen.scala:32:16] reg [4:0] rob_39_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_39_data; // @[tracegen.scala:32:16] reg [33:0] rob_40_addr; // @[tracegen.scala:32:16] reg [5:0] rob_40_tag; // @[tracegen.scala:32:16] reg [4:0] rob_40_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_40_data; // @[tracegen.scala:32:16] reg [33:0] rob_41_addr; // @[tracegen.scala:32:16] reg [5:0] rob_41_tag; // @[tracegen.scala:32:16] reg [4:0] rob_41_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_41_data; // @[tracegen.scala:32:16] reg [33:0] rob_42_addr; // @[tracegen.scala:32:16] reg [5:0] rob_42_tag; // @[tracegen.scala:32:16] reg [4:0] rob_42_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_42_data; // @[tracegen.scala:32:16] reg [33:0] rob_43_addr; // @[tracegen.scala:32:16] reg [5:0] rob_43_tag; // @[tracegen.scala:32:16] reg [4:0] rob_43_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_43_data; // @[tracegen.scala:32:16] reg [33:0] rob_44_addr; // @[tracegen.scala:32:16] reg [5:0] rob_44_tag; // @[tracegen.scala:32:16] reg [4:0] rob_44_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_44_data; // @[tracegen.scala:32:16] reg [33:0] rob_45_addr; // @[tracegen.scala:32:16] reg [5:0] rob_45_tag; // @[tracegen.scala:32:16] reg [4:0] rob_45_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_45_data; // @[tracegen.scala:32:16] reg [33:0] rob_46_addr; // @[tracegen.scala:32:16] reg [5:0] rob_46_tag; // @[tracegen.scala:32:16] reg [4:0] rob_46_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_46_data; // @[tracegen.scala:32:16] reg [33:0] rob_47_addr; // @[tracegen.scala:32:16] reg [5:0] rob_47_tag; // @[tracegen.scala:32:16] reg [4:0] rob_47_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_47_data; // @[tracegen.scala:32:16] reg [33:0] rob_48_addr; // @[tracegen.scala:32:16] reg [5:0] rob_48_tag; // @[tracegen.scala:32:16] reg [4:0] rob_48_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_48_data; // @[tracegen.scala:32:16] reg [33:0] rob_49_addr; // @[tracegen.scala:32:16] reg [5:0] rob_49_tag; // @[tracegen.scala:32:16] reg [4:0] rob_49_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_49_data; // @[tracegen.scala:32:16] reg [33:0] rob_50_addr; // @[tracegen.scala:32:16] reg [5:0] rob_50_tag; // @[tracegen.scala:32:16] reg [4:0] rob_50_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_50_data; // @[tracegen.scala:32:16] reg [33:0] rob_51_addr; // @[tracegen.scala:32:16] reg [5:0] rob_51_tag; // @[tracegen.scala:32:16] reg [4:0] rob_51_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_51_data; // @[tracegen.scala:32:16] reg [33:0] rob_52_addr; // @[tracegen.scala:32:16] reg [5:0] rob_52_tag; // @[tracegen.scala:32:16] reg [4:0] rob_52_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_52_data; // @[tracegen.scala:32:16] reg [33:0] rob_53_addr; // @[tracegen.scala:32:16] reg [5:0] rob_53_tag; // @[tracegen.scala:32:16] reg [4:0] rob_53_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_53_data; // @[tracegen.scala:32:16] reg [33:0] rob_54_addr; // @[tracegen.scala:32:16] reg [5:0] rob_54_tag; // @[tracegen.scala:32:16] reg [4:0] rob_54_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_54_data; // @[tracegen.scala:32:16] reg [33:0] rob_55_addr; // @[tracegen.scala:32:16] reg [5:0] rob_55_tag; // @[tracegen.scala:32:16] reg [4:0] rob_55_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_55_data; // @[tracegen.scala:32:16] reg [33:0] rob_56_addr; // @[tracegen.scala:32:16] reg [5:0] rob_56_tag; // @[tracegen.scala:32:16] reg [4:0] rob_56_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_56_data; // @[tracegen.scala:32:16] reg [33:0] rob_57_addr; // @[tracegen.scala:32:16] reg [5:0] rob_57_tag; // @[tracegen.scala:32:16] reg [4:0] rob_57_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_57_data; // @[tracegen.scala:32:16] reg [33:0] rob_58_addr; // @[tracegen.scala:32:16] reg [5:0] rob_58_tag; // @[tracegen.scala:32:16] reg [4:0] rob_58_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_58_data; // @[tracegen.scala:32:16] reg [33:0] rob_59_addr; // @[tracegen.scala:32:16] reg [5:0] rob_59_tag; // @[tracegen.scala:32:16] reg [4:0] rob_59_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_59_data; // @[tracegen.scala:32:16] reg [33:0] rob_60_addr; // @[tracegen.scala:32:16] reg [5:0] rob_60_tag; // @[tracegen.scala:32:16] reg [4:0] rob_60_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_60_data; // @[tracegen.scala:32:16] reg [33:0] rob_61_addr; // @[tracegen.scala:32:16] reg [5:0] rob_61_tag; // @[tracegen.scala:32:16] reg [4:0] rob_61_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_61_data; // @[tracegen.scala:32:16] reg [33:0] rob_62_addr; // @[tracegen.scala:32:16] reg [5:0] rob_62_tag; // @[tracegen.scala:32:16] reg [4:0] rob_62_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_62_data; // @[tracegen.scala:32:16] reg [33:0] rob_63_addr; // @[tracegen.scala:32:16] reg [5:0] rob_63_tag; // @[tracegen.scala:32:16] reg [4:0] rob_63_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_63_data; // @[tracegen.scala:32:16] reg rob_respd_0; // @[tracegen.scala:33:26] reg rob_respd_1; // @[tracegen.scala:33:26] reg rob_respd_2; // @[tracegen.scala:33:26] reg rob_respd_3; // @[tracegen.scala:33:26] reg rob_respd_4; // @[tracegen.scala:33:26] reg rob_respd_5; // @[tracegen.scala:33:26] reg rob_respd_6; // @[tracegen.scala:33:26] reg rob_respd_7; // @[tracegen.scala:33:26] reg rob_respd_8; // @[tracegen.scala:33:26] reg rob_respd_9; // @[tracegen.scala:33:26] reg rob_respd_10; // @[tracegen.scala:33:26] reg rob_respd_11; // @[tracegen.scala:33:26] reg rob_respd_12; // @[tracegen.scala:33:26] reg rob_respd_13; // @[tracegen.scala:33:26] reg rob_respd_14; // @[tracegen.scala:33:26] reg rob_respd_15; // @[tracegen.scala:33:26] reg rob_respd_16; // @[tracegen.scala:33:26] reg rob_respd_17; // @[tracegen.scala:33:26] reg rob_respd_18; // @[tracegen.scala:33:26] reg rob_respd_19; // @[tracegen.scala:33:26] reg rob_respd_20; // @[tracegen.scala:33:26] reg rob_respd_21; // @[tracegen.scala:33:26] reg rob_respd_22; // @[tracegen.scala:33:26] reg rob_respd_23; // @[tracegen.scala:33:26] reg rob_respd_24; // @[tracegen.scala:33:26] reg rob_respd_25; // @[tracegen.scala:33:26] reg rob_respd_26; // @[tracegen.scala:33:26] reg rob_respd_27; // @[tracegen.scala:33:26] reg rob_respd_28; // @[tracegen.scala:33:26] reg rob_respd_29; // @[tracegen.scala:33:26] reg rob_respd_30; // @[tracegen.scala:33:26] reg rob_respd_31; // @[tracegen.scala:33:26] reg rob_respd_32; // @[tracegen.scala:33:26] reg rob_respd_33; // @[tracegen.scala:33:26] reg rob_respd_34; // @[tracegen.scala:33:26] reg rob_respd_35; // @[tracegen.scala:33:26] reg rob_respd_36; // @[tracegen.scala:33:26] reg rob_respd_37; // @[tracegen.scala:33:26] reg rob_respd_38; // @[tracegen.scala:33:26] reg rob_respd_39; // @[tracegen.scala:33:26] reg rob_respd_40; // @[tracegen.scala:33:26] reg rob_respd_41; // @[tracegen.scala:33:26] reg rob_respd_42; // @[tracegen.scala:33:26] reg rob_respd_43; // @[tracegen.scala:33:26] reg rob_respd_44; // @[tracegen.scala:33:26] reg rob_respd_45; // @[tracegen.scala:33:26] reg rob_respd_46; // @[tracegen.scala:33:26] reg rob_respd_47; // @[tracegen.scala:33:26] reg rob_respd_48; // @[tracegen.scala:33:26] reg rob_respd_49; // @[tracegen.scala:33:26] reg rob_respd_50; // @[tracegen.scala:33:26] reg rob_respd_51; // @[tracegen.scala:33:26] reg rob_respd_52; // @[tracegen.scala:33:26] reg rob_respd_53; // @[tracegen.scala:33:26] reg rob_respd_54; // @[tracegen.scala:33:26] reg rob_respd_55; // @[tracegen.scala:33:26] reg rob_respd_56; // @[tracegen.scala:33:26] reg rob_respd_57; // @[tracegen.scala:33:26] reg rob_respd_58; // @[tracegen.scala:33:26] reg rob_respd_59; // @[tracegen.scala:33:26] reg rob_respd_60; // @[tracegen.scala:33:26] reg rob_respd_61; // @[tracegen.scala:33:26] reg rob_respd_62; // @[tracegen.scala:33:26] reg rob_respd_63; // @[tracegen.scala:33:26] reg [6:0] rob_uop_0_uopc; // @[tracegen.scala:34:20] reg rob_uop_0_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_0_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_0_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_0_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_0_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_0_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_0_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_0_is_amo; // @[tracegen.scala:34:20] reg rob_uop_0_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_0_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_1_uopc; // @[tracegen.scala:34:20] reg rob_uop_1_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_1_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_1_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_1_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_1_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_1_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_1_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_1_is_amo; // @[tracegen.scala:34:20] reg rob_uop_1_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_1_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_2_uopc; // @[tracegen.scala:34:20] reg rob_uop_2_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_2_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_2_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_2_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_2_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_2_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_2_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_2_is_amo; // @[tracegen.scala:34:20] reg rob_uop_2_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_2_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_3_uopc; // @[tracegen.scala:34:20] reg rob_uop_3_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_3_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_3_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_3_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_3_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_3_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_3_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_3_is_amo; // @[tracegen.scala:34:20] reg rob_uop_3_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_3_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_4_uopc; // @[tracegen.scala:34:20] reg rob_uop_4_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_4_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_4_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_4_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_4_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_4_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_4_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_4_is_amo; // @[tracegen.scala:34:20] reg rob_uop_4_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_4_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_5_uopc; // @[tracegen.scala:34:20] reg rob_uop_5_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_5_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_5_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_5_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_5_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_5_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_5_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_5_is_amo; // @[tracegen.scala:34:20] reg rob_uop_5_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_5_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_6_uopc; // @[tracegen.scala:34:20] reg rob_uop_6_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_6_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_6_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_6_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_6_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_6_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_6_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_6_is_amo; // @[tracegen.scala:34:20] reg rob_uop_6_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_6_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_7_uopc; // @[tracegen.scala:34:20] reg rob_uop_7_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_7_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_7_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_7_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_7_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_7_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_7_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_7_is_amo; // @[tracegen.scala:34:20] reg rob_uop_7_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_7_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_8_uopc; // @[tracegen.scala:34:20] reg rob_uop_8_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_8_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_8_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_8_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_8_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_8_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_8_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_8_is_amo; // @[tracegen.scala:34:20] reg rob_uop_8_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_8_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_9_uopc; // @[tracegen.scala:34:20] reg rob_uop_9_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_9_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_9_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_9_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_9_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_9_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_9_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_9_is_amo; // @[tracegen.scala:34:20] reg rob_uop_9_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_9_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_10_uopc; // @[tracegen.scala:34:20] reg rob_uop_10_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_10_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_10_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_10_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_10_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_10_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_10_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_10_is_amo; // @[tracegen.scala:34:20] reg rob_uop_10_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_10_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_11_uopc; // @[tracegen.scala:34:20] reg rob_uop_11_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_11_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_11_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_11_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_11_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_11_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_11_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_11_is_amo; // @[tracegen.scala:34:20] reg rob_uop_11_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_11_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_12_uopc; // @[tracegen.scala:34:20] reg rob_uop_12_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_12_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_12_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_12_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_12_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_12_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_12_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_12_is_amo; // @[tracegen.scala:34:20] reg rob_uop_12_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_12_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_13_uopc; // @[tracegen.scala:34:20] reg rob_uop_13_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_13_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_13_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_13_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_13_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_13_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_13_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_13_is_amo; // @[tracegen.scala:34:20] reg rob_uop_13_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_13_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_14_uopc; // @[tracegen.scala:34:20] reg rob_uop_14_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_14_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_14_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_14_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_14_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_14_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_14_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_14_is_amo; // @[tracegen.scala:34:20] reg rob_uop_14_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_14_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_15_uopc; // @[tracegen.scala:34:20] reg rob_uop_15_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_15_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_15_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_15_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_15_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_15_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_15_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_15_is_amo; // @[tracegen.scala:34:20] reg rob_uop_15_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_15_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_16_uopc; // @[tracegen.scala:34:20] reg rob_uop_16_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_16_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_16_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_16_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_16_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_16_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_16_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_16_is_amo; // @[tracegen.scala:34:20] reg rob_uop_16_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_16_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_17_uopc; // @[tracegen.scala:34:20] reg rob_uop_17_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_17_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_17_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_17_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_17_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_17_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_17_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_17_is_amo; // @[tracegen.scala:34:20] reg rob_uop_17_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_17_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_18_uopc; // @[tracegen.scala:34:20] reg rob_uop_18_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_18_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_18_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_18_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_18_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_18_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_18_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_18_is_amo; // @[tracegen.scala:34:20] reg rob_uop_18_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_18_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_19_uopc; // @[tracegen.scala:34:20] reg rob_uop_19_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_19_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_19_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_19_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_19_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_19_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_19_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_19_is_amo; // @[tracegen.scala:34:20] reg rob_uop_19_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_19_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_20_uopc; // @[tracegen.scala:34:20] reg rob_uop_20_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_20_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_20_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_20_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_20_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_20_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_20_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_20_is_amo; // @[tracegen.scala:34:20] reg rob_uop_20_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_20_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_21_uopc; // @[tracegen.scala:34:20] reg rob_uop_21_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_21_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_21_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_21_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_21_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_21_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_21_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_21_is_amo; // @[tracegen.scala:34:20] reg rob_uop_21_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_21_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_22_uopc; // @[tracegen.scala:34:20] reg rob_uop_22_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_22_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_22_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_22_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_22_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_22_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_22_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_22_is_amo; // @[tracegen.scala:34:20] reg rob_uop_22_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_22_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_23_uopc; // @[tracegen.scala:34:20] reg rob_uop_23_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_23_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_23_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_23_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_23_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_23_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_23_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_23_is_amo; // @[tracegen.scala:34:20] reg rob_uop_23_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_23_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_24_uopc; // @[tracegen.scala:34:20] reg rob_uop_24_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_24_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_24_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_24_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_24_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_24_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_24_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_24_is_amo; // @[tracegen.scala:34:20] reg rob_uop_24_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_24_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_25_uopc; // @[tracegen.scala:34:20] reg rob_uop_25_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_25_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_25_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_25_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_25_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_25_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_25_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_25_is_amo; // @[tracegen.scala:34:20] reg rob_uop_25_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_25_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_26_uopc; // @[tracegen.scala:34:20] reg rob_uop_26_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_26_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_26_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_26_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_26_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_26_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_26_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_26_is_amo; // @[tracegen.scala:34:20] reg rob_uop_26_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_26_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_27_uopc; // @[tracegen.scala:34:20] reg rob_uop_27_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_27_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_27_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_27_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_27_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_27_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_27_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_27_is_amo; // @[tracegen.scala:34:20] reg rob_uop_27_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_27_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_28_uopc; // @[tracegen.scala:34:20] reg rob_uop_28_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_28_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_28_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_28_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_28_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_28_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_28_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_28_is_amo; // @[tracegen.scala:34:20] reg rob_uop_28_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_28_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_29_uopc; // @[tracegen.scala:34:20] reg rob_uop_29_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_29_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_29_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_29_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_29_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_29_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_29_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_29_is_amo; // @[tracegen.scala:34:20] reg rob_uop_29_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_29_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_30_uopc; // @[tracegen.scala:34:20] reg rob_uop_30_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_30_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_30_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_30_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_30_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_30_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_30_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_30_is_amo; // @[tracegen.scala:34:20] reg rob_uop_30_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_30_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_31_uopc; // @[tracegen.scala:34:20] reg rob_uop_31_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_31_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_31_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_31_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_31_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_31_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_31_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_31_is_amo; // @[tracegen.scala:34:20] reg rob_uop_31_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_31_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_32_uopc; // @[tracegen.scala:34:20] reg rob_uop_32_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_32_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_32_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_32_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_32_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_32_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_32_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_32_is_amo; // @[tracegen.scala:34:20] reg rob_uop_32_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_32_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_33_uopc; // @[tracegen.scala:34:20] reg rob_uop_33_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_33_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_33_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_33_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_33_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_33_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_33_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_33_is_amo; // @[tracegen.scala:34:20] reg rob_uop_33_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_33_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_34_uopc; // @[tracegen.scala:34:20] reg rob_uop_34_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_34_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_34_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_34_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_34_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_34_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_34_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_34_is_amo; // @[tracegen.scala:34:20] reg rob_uop_34_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_34_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_35_uopc; // @[tracegen.scala:34:20] reg rob_uop_35_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_35_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_35_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_35_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_35_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_35_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_35_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_35_is_amo; // @[tracegen.scala:34:20] reg rob_uop_35_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_35_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_36_uopc; // @[tracegen.scala:34:20] reg rob_uop_36_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_36_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_36_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_36_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_36_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_36_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_36_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_36_is_amo; // @[tracegen.scala:34:20] reg rob_uop_36_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_36_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_37_uopc; // @[tracegen.scala:34:20] reg rob_uop_37_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_37_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_37_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_37_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_37_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_37_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_37_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_37_is_amo; // @[tracegen.scala:34:20] reg rob_uop_37_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_37_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_38_uopc; // @[tracegen.scala:34:20] reg rob_uop_38_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_38_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_38_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_38_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_38_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_38_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_38_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_38_is_amo; // @[tracegen.scala:34:20] reg rob_uop_38_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_38_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_39_uopc; // @[tracegen.scala:34:20] reg rob_uop_39_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_39_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_39_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_39_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_39_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_39_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_39_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_39_is_amo; // @[tracegen.scala:34:20] reg rob_uop_39_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_39_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_40_uopc; // @[tracegen.scala:34:20] reg rob_uop_40_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_40_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_40_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_40_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_40_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_40_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_40_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_40_is_amo; // @[tracegen.scala:34:20] reg rob_uop_40_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_40_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_41_uopc; // @[tracegen.scala:34:20] reg rob_uop_41_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_41_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_41_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_41_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_41_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_41_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_41_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_41_is_amo; // @[tracegen.scala:34:20] reg rob_uop_41_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_41_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_42_uopc; // @[tracegen.scala:34:20] reg rob_uop_42_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_42_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_42_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_42_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_42_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_42_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_42_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_42_is_amo; // @[tracegen.scala:34:20] reg rob_uop_42_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_42_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_43_uopc; // @[tracegen.scala:34:20] reg rob_uop_43_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_43_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_43_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_43_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_43_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_43_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_43_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_43_is_amo; // @[tracegen.scala:34:20] reg rob_uop_43_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_43_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_44_uopc; // @[tracegen.scala:34:20] reg rob_uop_44_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_44_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_44_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_44_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_44_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_44_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_44_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_44_is_amo; // @[tracegen.scala:34:20] reg rob_uop_44_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_44_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_45_uopc; // @[tracegen.scala:34:20] reg rob_uop_45_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_45_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_45_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_45_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_45_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_45_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_45_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_45_is_amo; // @[tracegen.scala:34:20] reg rob_uop_45_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_45_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_46_uopc; // @[tracegen.scala:34:20] reg rob_uop_46_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_46_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_46_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_46_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_46_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_46_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_46_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_46_is_amo; // @[tracegen.scala:34:20] reg rob_uop_46_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_46_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_47_uopc; // @[tracegen.scala:34:20] reg rob_uop_47_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_47_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_47_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_47_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_47_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_47_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_47_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_47_is_amo; // @[tracegen.scala:34:20] reg rob_uop_47_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_47_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_48_uopc; // @[tracegen.scala:34:20] reg rob_uop_48_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_48_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_48_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_48_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_48_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_48_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_48_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_48_is_amo; // @[tracegen.scala:34:20] reg rob_uop_48_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_48_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_49_uopc; // @[tracegen.scala:34:20] reg rob_uop_49_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_49_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_49_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_49_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_49_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_49_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_49_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_49_is_amo; // @[tracegen.scala:34:20] reg rob_uop_49_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_49_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_50_uopc; // @[tracegen.scala:34:20] reg rob_uop_50_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_50_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_50_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_50_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_50_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_50_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_50_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_50_is_amo; // @[tracegen.scala:34:20] reg rob_uop_50_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_50_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_51_uopc; // @[tracegen.scala:34:20] reg rob_uop_51_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_51_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_51_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_51_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_51_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_51_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_51_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_51_is_amo; // @[tracegen.scala:34:20] reg rob_uop_51_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_51_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_52_uopc; // @[tracegen.scala:34:20] reg rob_uop_52_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_52_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_52_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_52_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_52_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_52_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_52_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_52_is_amo; // @[tracegen.scala:34:20] reg rob_uop_52_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_52_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_53_uopc; // @[tracegen.scala:34:20] reg rob_uop_53_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_53_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_53_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_53_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_53_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_53_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_53_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_53_is_amo; // @[tracegen.scala:34:20] reg rob_uop_53_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_53_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_54_uopc; // @[tracegen.scala:34:20] reg rob_uop_54_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_54_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_54_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_54_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_54_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_54_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_54_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_54_is_amo; // @[tracegen.scala:34:20] reg rob_uop_54_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_54_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_55_uopc; // @[tracegen.scala:34:20] reg rob_uop_55_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_55_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_55_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_55_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_55_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_55_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_55_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_55_is_amo; // @[tracegen.scala:34:20] reg rob_uop_55_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_55_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_56_uopc; // @[tracegen.scala:34:20] reg rob_uop_56_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_56_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_56_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_56_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_56_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_56_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_56_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_56_is_amo; // @[tracegen.scala:34:20] reg rob_uop_56_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_56_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_57_uopc; // @[tracegen.scala:34:20] reg rob_uop_57_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_57_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_57_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_57_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_57_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_57_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_57_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_57_is_amo; // @[tracegen.scala:34:20] reg rob_uop_57_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_57_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_58_uopc; // @[tracegen.scala:34:20] reg rob_uop_58_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_58_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_58_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_58_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_58_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_58_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_58_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_58_is_amo; // @[tracegen.scala:34:20] reg rob_uop_58_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_58_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_59_uopc; // @[tracegen.scala:34:20] reg rob_uop_59_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_59_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_59_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_59_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_59_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_59_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_59_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_59_is_amo; // @[tracegen.scala:34:20] reg rob_uop_59_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_59_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_60_uopc; // @[tracegen.scala:34:20] reg rob_uop_60_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_60_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_60_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_60_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_60_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_60_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_60_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_60_is_amo; // @[tracegen.scala:34:20] reg rob_uop_60_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_60_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_61_uopc; // @[tracegen.scala:34:20] reg rob_uop_61_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_61_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_61_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_61_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_61_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_61_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_61_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_61_is_amo; // @[tracegen.scala:34:20] reg rob_uop_61_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_61_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_62_uopc; // @[tracegen.scala:34:20] reg rob_uop_62_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_62_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_62_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_62_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_62_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_62_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_62_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_62_is_amo; // @[tracegen.scala:34:20] reg rob_uop_62_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_62_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_63_uopc; // @[tracegen.scala:34:20] reg rob_uop_63_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_63_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_63_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_63_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_63_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_63_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_63_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_63_is_amo; // @[tracegen.scala:34:20] reg rob_uop_63_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_63_uses_stq; // @[tracegen.scala:34:20] reg rob_bsy_0; // @[tracegen.scala:35:25] reg rob_bsy_1; // @[tracegen.scala:35:25] reg rob_bsy_2; // @[tracegen.scala:35:25] reg rob_bsy_3; // @[tracegen.scala:35:25] reg rob_bsy_4; // @[tracegen.scala:35:25] reg rob_bsy_5; // @[tracegen.scala:35:25] reg rob_bsy_6; // @[tracegen.scala:35:25] reg rob_bsy_7; // @[tracegen.scala:35:25] reg rob_bsy_8; // @[tracegen.scala:35:25] reg rob_bsy_9; // @[tracegen.scala:35:25] reg rob_bsy_10; // @[tracegen.scala:35:25] reg rob_bsy_11; // @[tracegen.scala:35:25] reg rob_bsy_12; // @[tracegen.scala:35:25] reg rob_bsy_13; // @[tracegen.scala:35:25] reg rob_bsy_14; // @[tracegen.scala:35:25] reg rob_bsy_15; // @[tracegen.scala:35:25] reg rob_bsy_16; // @[tracegen.scala:35:25] reg rob_bsy_17; // @[tracegen.scala:35:25] reg rob_bsy_18; // @[tracegen.scala:35:25] reg rob_bsy_19; // @[tracegen.scala:35:25] reg rob_bsy_20; // @[tracegen.scala:35:25] reg rob_bsy_21; // @[tracegen.scala:35:25] reg rob_bsy_22; // @[tracegen.scala:35:25] reg rob_bsy_23; // @[tracegen.scala:35:25] reg rob_bsy_24; // @[tracegen.scala:35:25] reg rob_bsy_25; // @[tracegen.scala:35:25] reg rob_bsy_26; // @[tracegen.scala:35:25] reg rob_bsy_27; // @[tracegen.scala:35:25] reg rob_bsy_28; // @[tracegen.scala:35:25] reg rob_bsy_29; // @[tracegen.scala:35:25] reg rob_bsy_30; // @[tracegen.scala:35:25] reg rob_bsy_31; // @[tracegen.scala:35:25] reg rob_bsy_32; // @[tracegen.scala:35:25] reg rob_bsy_33; // @[tracegen.scala:35:25] reg rob_bsy_34; // @[tracegen.scala:35:25] reg rob_bsy_35; // @[tracegen.scala:35:25] reg rob_bsy_36; // @[tracegen.scala:35:25] reg rob_bsy_37; // @[tracegen.scala:35:25] reg rob_bsy_38; // @[tracegen.scala:35:25] reg rob_bsy_39; // @[tracegen.scala:35:25] reg rob_bsy_40; // @[tracegen.scala:35:25] reg rob_bsy_41; // @[tracegen.scala:35:25] reg rob_bsy_42; // @[tracegen.scala:35:25] reg rob_bsy_43; // @[tracegen.scala:35:25] reg rob_bsy_44; // @[tracegen.scala:35:25] reg rob_bsy_45; // @[tracegen.scala:35:25] reg rob_bsy_46; // @[tracegen.scala:35:25] reg rob_bsy_47; // @[tracegen.scala:35:25] reg rob_bsy_48; // @[tracegen.scala:35:25] reg rob_bsy_49; // @[tracegen.scala:35:25] reg rob_bsy_50; // @[tracegen.scala:35:25] reg rob_bsy_51; // @[tracegen.scala:35:25] reg rob_bsy_52; // @[tracegen.scala:35:25] reg rob_bsy_53; // @[tracegen.scala:35:25] reg rob_bsy_54; // @[tracegen.scala:35:25] reg rob_bsy_55; // @[tracegen.scala:35:25] reg rob_bsy_56; // @[tracegen.scala:35:25] reg rob_bsy_57; // @[tracegen.scala:35:25] reg rob_bsy_58; // @[tracegen.scala:35:25] reg rob_bsy_59; // @[tracegen.scala:35:25] reg rob_bsy_60; // @[tracegen.scala:35:25] reg rob_bsy_61; // @[tracegen.scala:35:25] reg rob_bsy_62; // @[tracegen.scala:35:25] reg rob_bsy_63; // @[tracegen.scala:35:25] reg [5:0] rob_head; // @[tracegen.scala:36:25] assign io_lsu_rob_head_idx_0 = rob_head; // @[tracegen.scala:20:7, :36:25] reg [5:0] rob_tail; // @[tracegen.scala:37:25] assign io_lsu_rob_pnr_idx_0 = rob_tail; // @[tracegen.scala:20:7, :37:25] assign tracegen_uop_rob_idx = rob_tail; // @[tracegen.scala:37:25, :57:30] reg rob_wait_till_empty; // @[tracegen.scala:38:36] wire _ready_for_amo_T = rob_tail == rob_head; // @[tracegen.scala:36:25, :37:25, :39:32] wire ready_for_amo = _ready_for_amo_T & io_lsu_fencei_rdy_0; // @[tracegen.scala:20:7, :39:{32,45}] wire [63:0] _GEN = {{rob_bsy_63}, {rob_bsy_62}, {rob_bsy_61}, {rob_bsy_60}, {rob_bsy_59}, {rob_bsy_58}, {rob_bsy_57}, {rob_bsy_56}, {rob_bsy_55}, {rob_bsy_54}, {rob_bsy_53}, {rob_bsy_52}, {rob_bsy_51}, {rob_bsy_50}, {rob_bsy_49}, {rob_bsy_48}, {rob_bsy_47}, {rob_bsy_46}, {rob_bsy_45}, {rob_bsy_44}, {rob_bsy_43}, {rob_bsy_42}, {rob_bsy_41}, {rob_bsy_40}, {rob_bsy_39}, {rob_bsy_38}, {rob_bsy_37}, {rob_bsy_36}, {rob_bsy_35}, {rob_bsy_34}, {rob_bsy_33}, {rob_bsy_32}, {rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[tracegen.scala:35:25, :49:29] wire _io_tracegen_req_ready_T = ~_GEN[rob_tail]; // @[tracegen.scala:37:25, :49:29] wire _io_tracegen_req_ready_T_1 = ~rob_wait_till_empty; // @[tracegen.scala:38:36, :50:5] wire _io_tracegen_req_ready_T_2 = _io_tracegen_req_ready_T & _io_tracegen_req_ready_T_1; // @[tracegen.scala:49:{29,48}, :50:5] wire _T_1 = io_tracegen_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_3; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_3 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_40; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_40 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_66; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_66 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_7 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_30; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_30 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_5; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_5 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_7; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_7 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_30; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_30 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_5; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_5 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_5; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_5 = _T_1; // @[package.scala:16:47] wire _T_2 = io_tracegen_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_4; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_4 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_41; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_41 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_67; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_67 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_8 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_31 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_6 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_1; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_1 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_8; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_8 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_31; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_31 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_6; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_6 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_6; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_6 = _T_2; // @[package.scala:16:47] wire _T_3 = io_tracegen_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_5; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_5 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_42; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_42 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_68; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_68 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_9 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_32 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_7 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_2; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_2 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_9; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_9 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_32; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_32 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_7; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_7 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_7; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_7 = _T_3; // @[package.scala:16:47] wire _T_4 = io_tracegen_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_6; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_6 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_43; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_43 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_69; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_69 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_10 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_33 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_8 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_3; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_3 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_10; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_10 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_33; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_33 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_8; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_8 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_8; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_8 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_7 = _io_tracegen_req_ready_T_3 \| _io_tracegen_req_ready_T_4; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_8 = _io_tracegen_req_ready_T_7 \| _io_tracegen_req_ready_T_5; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_9 = _io_tracegen_req_ready_T_8 \| _io_tracegen_req_ready_T_6; // @[package.scala:16:47, :81:59] wire _T_8 = io_tracegen_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_10; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_10 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_47; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_47 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_73; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_73 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_14 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_37; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_37 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_12; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_12 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_7; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_7 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_14; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_14 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_37; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_37 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_12; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_12 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_12; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_12 = _T_8; // @[package.scala:16:47] wire _T_9 = io_tracegen_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_11; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_11 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_48; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_48 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_74; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_74 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_15 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_38 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_13 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_8; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_8 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_15; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_15 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_38; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_38 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_13; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_13 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_13; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_13 = _T_9; // @[package.scala:16:47] wire _T_10 = io_tracegen_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_12; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_12 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_49; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_49 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_75; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_75 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_16 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_39 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_14 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_9; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_9 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_16; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_16 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_39; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_39 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_14; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_14 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_14; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_14 = _T_10; // @[package.scala:16:47] wire _T_11 = io_tracegen_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_13; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_13 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_50; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_50 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_76; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_76 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_17 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_40 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_15 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_10; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_10 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_17; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_17 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_40; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_40 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_15; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_15 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_15; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_15 = _T_11; // @[package.scala:16:47] wire _T_12 = io_tracegen_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_14; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_14 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_51; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_51 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_77; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_77 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_18 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_41 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_16 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_11; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_11 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_18; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_18 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_41; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_41 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_16; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_16 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_16; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_16 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_15 = _io_tracegen_req_ready_T_10 \| _io_tracegen_req_ready_T_11; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_16 = _io_tracegen_req_ready_T_15 \| _io_tracegen_req_ready_T_12; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_17 = _io_tracegen_req_ready_T_16 \| _io_tracegen_req_ready_T_13; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_18 = _io_tracegen_req_ready_T_17 \| _io_tracegen_req_ready_T_14; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_19 = _io_tracegen_req_ready_T_9 \| _io_tracegen_req_ready_T_18; // @[package.scala:81:59] wire _T_18 = io_tracegen_req_bits_cmd_0 == 5'h6; // @[tracegen.scala:20:7, :51:85] wire _io_tracegen_req_ready_T_20; // @[tracegen.scala:51:85] assign _io_tracegen_req_ready_T_20 = _T_18; // @[tracegen.scala:51:85] wire _io_tracegen_req_ready_T_35; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_35 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_2 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_2; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_2 = _T_18; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_21 = _io_tracegen_req_ready_T_19 \| _io_tracegen_req_ready_T_20; // @[Consts.scala:87:44] wire _T_20 = io_tracegen_req_bits_cmd_0 == 5'h7; // @[tracegen.scala:20:7, :51:123] wire _io_tracegen_req_ready_T_22; // @[tracegen.scala:51:123] assign _io_tracegen_req_ready_T_22 = _T_20; // @[tracegen.scala:51:123] wire _io_tracegen_req_ready_T_36; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_36 = _T_20; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_64; // @[Consts.scala:90:66] assign _io_tracegen_req_ready_T_64 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_3 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:66] assign _tracegen_uop_uses_ldq_T_28 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_uses_stq_T_3 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_is_amo_T_17; // @[tracegen.scala:67:92] assign _tracegen_uop_is_amo_T_17 = _T_20; // @[tracegen.scala:51:123, :67:92] wire _tracegen_uop_ctrl_is_load_T_3; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_3 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_28; // @[Consts.scala:90:66] assign _tracegen_uop_ctrl_is_load_T_28 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_ctrl_is_sta_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_ctrl_is_sta_T_3 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_ctrl_is_std_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_ctrl_is_std_T_3 = _T_20; // @[Consts.scala:90:66] wire _io_tracegen_req_ready_T_23 = _io_tracegen_req_ready_T_21 \| _io_tracegen_req_ready_T_22; // @[tracegen.scala:51:{57,95,123}] wire _io_tracegen_req_ready_T_24 = ~_io_tracegen_req_ready_T_23; // @[tracegen.scala:51:{23,95}] wire _io_tracegen_req_ready_T_25 = ready_for_amo \| _io_tracegen_req_ready_T_24; // @[tracegen.scala:39:45, :51:{20,23}] wire _io_tracegen_req_ready_T_26 = _io_tracegen_req_ready_T_2 & _io_tracegen_req_ready_T_25; // @[tracegen.scala:49:48, :50:26, :51:20] wire _io_tracegen_req_ready_T_27 = &rob_tail; // @[tracegen.scala:37:25, :45:13] wire [6:0] _GEN_0 = {1'h0, rob_tail} + 7'h1; // @[tracegen.scala:37:25, :45:37] wire [6:0] _io_tracegen_req_ready_T_28; // @[tracegen.scala:45:37] assign _io_tracegen_req_ready_T_28 = _GEN_0; // @[tracegen.scala:45:37] wire [6:0] _rob_tail_T_1; // @[tracegen.scala:45:37] assign _rob_tail_T_1 = _GEN_0; // @[tracegen.scala:45:37] wire [5:0] _io_tracegen_req_ready_T_29 = _io_tracegen_req_ready_T_28[5:0]; // @[tracegen.scala:45:37] wire [5:0] _io_tracegen_req_ready_T_30 = _io_tracegen_req_ready_T_27 ? 6'h0 : _io_tracegen_req_ready_T_29; // @[tracegen.scala:45:{8,13,37}] wire _io_tracegen_req_ready_T_31 = _io_tracegen_req_ready_T_30 != rob_head; // @[tracegen.scala:36:25, :45:8, :52:32] wire _io_tracegen_req_ready_T_32 = _io_tracegen_req_ready_T_26 & _io_tracegen_req_ready_T_31; // @[tracegen.scala:50:26, :51:135, :52:32] wire _GEN_1 = io_tracegen_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_33; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_33 = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T = _GEN_1; // @[package.scala:16:47] wire _GEN_2 = io_tracegen_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_34; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_34 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_1 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_1; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_1 = _GEN_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_37 = _io_tracegen_req_ready_T_33 \| _io_tracegen_req_ready_T_34; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_38 = _io_tracegen_req_ready_T_37 \| _io_tracegen_req_ready_T_35; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_39 = _io_tracegen_req_ready_T_38 \| _io_tracegen_req_ready_T_36; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_44 = _io_tracegen_req_ready_T_40 \| _io_tracegen_req_ready_T_41; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_45 = _io_tracegen_req_ready_T_44 \| _io_tracegen_req_ready_T_42; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_46 = _io_tracegen_req_ready_T_45 \| _io_tracegen_req_ready_T_43; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_52 = _io_tracegen_req_ready_T_47 \| _io_tracegen_req_ready_T_48; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_53 = _io_tracegen_req_ready_T_52 \| _io_tracegen_req_ready_T_49; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_54 = _io_tracegen_req_ready_T_53 \| _io_tracegen_req_ready_T_50; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_55 = _io_tracegen_req_ready_T_54 \| _io_tracegen_req_ready_T_51; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_56 = _io_tracegen_req_ready_T_46 \| _io_tracegen_req_ready_T_55; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_57 = _io_tracegen_req_ready_T_39 \| _io_tracegen_req_ready_T_56; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_58 = io_lsu_ldq_full_0_0 & _io_tracegen_req_ready_T_57; // @[Consts.scala:89:68] wire _io_tracegen_req_ready_T_59 = ~_io_tracegen_req_ready_T_58; // @[tracegen.scala:53:{5,26}] wire _io_tracegen_req_ready_T_60 = _io_tracegen_req_ready_T_32 & _io_tracegen_req_ready_T_59; // @[tracegen.scala:51:135, :52:46, :53:5] wire _GEN_3 = io_tracegen_req_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _io_tracegen_req_ready_T_61; // @[Consts.scala:90:32] assign _io_tracegen_req_ready_T_61 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_ldq_T_25; // @[Consts.scala:90:32] assign _tracegen_uop_uses_ldq_T_25 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_stq_T; // @[Consts.scala:90:32] assign _tracegen_uop_uses_stq_T = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_ctrl_is_load_T_25; // @[Consts.scala:90:32] assign _tracegen_uop_ctrl_is_load_T_25 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_ctrl_is_sta_T; // @[Consts.scala:90:32] assign _tracegen_uop_ctrl_is_sta_T = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_ctrl_is_std_T; // @[Consts.scala:90:32] assign _tracegen_uop_ctrl_is_std_T = _GEN_3; // @[Consts.scala:90:32] wire _GEN_4 = io_tracegen_req_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_62; // @[Consts.scala:90:49] assign _io_tracegen_req_ready_T_62 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:49] assign _tracegen_uop_uses_ldq_T_26 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_uses_stq_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_ctrl_is_load_T_26; // @[Consts.scala:90:49] assign _tracegen_uop_ctrl_is_load_T_26 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_ctrl_is_sta_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_ctrl_is_sta_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_ctrl_is_std_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_ctrl_is_std_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_63 = _io_tracegen_req_ready_T_61 \| _io_tracegen_req_ready_T_62; // @[Consts.scala:90:{32,42,49}] wire _io_tracegen_req_ready_T_65 = _io_tracegen_req_ready_T_63 \| _io_tracegen_req_ready_T_64; // @[Consts.scala:90:{42,59,66}] wire _io_tracegen_req_ready_T_70 = _io_tracegen_req_ready_T_66 \| _io_tracegen_req_ready_T_67; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_71 = _io_tracegen_req_ready_T_70 \| _io_tracegen_req_ready_T_68; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_72 = _io_tracegen_req_ready_T_71 \| _io_tracegen_req_ready_T_69; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_78 = _io_tracegen_req_ready_T_73 \| _io_tracegen_req_ready_T_74; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_79 = _io_tracegen_req_ready_T_78 \| _io_tracegen_req_ready_T_75; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_80 = _io_tracegen_req_ready_T_79 \| _io_tracegen_req_ready_T_76; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_81 = _io_tracegen_req_ready_T_80 \| _io_tracegen_req_ready_T_77; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_82 = _io_tracegen_req_ready_T_72 \| _io_tracegen_req_ready_T_81; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_83 = _io_tracegen_req_ready_T_65 \| _io_tracegen_req_ready_T_82; // @[Consts.scala:87:44, :90:{59,76}] wire _io_tracegen_req_ready_T_84 = io_lsu_stq_full_0_0 & _io_tracegen_req_ready_T_83; // @[Consts.scala:90:76] wire _io_tracegen_req_ready_T_85 = ~_io_tracegen_req_ready_T_84; // @[tracegen.scala:54:{5,26}] assign _io_tracegen_req_ready_T_86 = _io_tracegen_req_ready_T_60 & _io_tracegen_req_ready_T_85; // @[tracegen.scala:52:46, :53:63, :54:5] assign io_tracegen_req_ready_0 = _io_tracegen_req_ready_T_86; // @[tracegen.scala:20:7, :53:63] assign io_lsu_dis_uops_0_bits_uopc_0 = tracegen_uop_uopc; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_ctrl_is_load_T_49; // @[tracegen.scala:68:65] assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = tracegen_uop_ctrl_is_load; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_ctrl_is_sta_T_22; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = tracegen_uop_ctrl_is_sta; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_ctrl_is_std_T_22; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = tracegen_uop_ctrl_is_std; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_rob_idx_0 = tracegen_uop_rob_idx; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_ldq_idx_0 = tracegen_uop_ldq_idx; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_stq_idx_0 = tracegen_uop_stq_idx; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_mem_cmd_0 = tracegen_uop_mem_cmd; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_is_amo_T_18; // @[tracegen.scala:67:64] assign io_lsu_dis_uops_0_bits_is_amo_0 = tracegen_uop_is_amo; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_uses_ldq_T_49; // @[tracegen.scala:58:65] assign io_lsu_dis_uops_0_bits_uses_ldq_0 = tracegen_uop_uses_ldq; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_uses_stq_T_22; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_uses_stq_0 = tracegen_uop_uses_stq; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_uses_ldq_T_4 = _tracegen_uop_uses_ldq_T \| _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_5 = _tracegen_uop_uses_ldq_T_4 \| _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_6 = _tracegen_uop_uses_ldq_T_5 \| _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_11 = _tracegen_uop_uses_ldq_T_7 \| _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_12 = _tracegen_uop_uses_ldq_T_11 \| _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_13 = _tracegen_uop_uses_ldq_T_12 \| _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_19 = _tracegen_uop_uses_ldq_T_14 \| _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_20 = _tracegen_uop_uses_ldq_T_19 \| _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_21 = _tracegen_uop_uses_ldq_T_20 \| _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_22 = _tracegen_uop_uses_ldq_T_21 \| _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_23 = _tracegen_uop_uses_ldq_T_13 \| _tracegen_uop_uses_ldq_T_22; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_24 = _tracegen_uop_uses_ldq_T_6 \| _tracegen_uop_uses_ldq_T_23; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_27 = _tracegen_uop_uses_ldq_T_25 \| _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_ldq_T_29 = _tracegen_uop_uses_ldq_T_27 \| _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_ldq_T_34 = _tracegen_uop_uses_ldq_T_30 \| _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_35 = _tracegen_uop_uses_ldq_T_34 \| _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_36 = _tracegen_uop_uses_ldq_T_35 \| _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_42 = _tracegen_uop_uses_ldq_T_37 \| _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_43 = _tracegen_uop_uses_ldq_T_42 \| _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_44 = _tracegen_uop_uses_ldq_T_43 \| _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_45 = _tracegen_uop_uses_ldq_T_44 \| _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_46 = _tracegen_uop_uses_ldq_T_36 \| _tracegen_uop_uses_ldq_T_45; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_47 = _tracegen_uop_uses_ldq_T_29 \| _tracegen_uop_uses_ldq_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_uses_ldq_T_48 = ~_tracegen_uop_uses_ldq_T_47; // @[Consts.scala:90:76] assign _tracegen_uop_uses_ldq_T_49 = _tracegen_uop_uses_ldq_T_24 & _tracegen_uop_uses_ldq_T_48; // @[Consts.scala:89:68] assign tracegen_uop_uses_ldq = _tracegen_uop_uses_ldq_T_49; // @[tracegen.scala:57:30, :58:65] wire _tracegen_uop_uses_stq_T_2 = _tracegen_uop_uses_stq_T \| _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_stq_T_4 = _tracegen_uop_uses_stq_T_2 \| _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_stq_T_9 = _tracegen_uop_uses_stq_T_5 \| _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_10 = _tracegen_uop_uses_stq_T_9 \| _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_11 = _tracegen_uop_uses_stq_T_10 \| _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_17 = _tracegen_uop_uses_stq_T_12 \| _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_18 = _tracegen_uop_uses_stq_T_17 \| _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_19 = _tracegen_uop_uses_stq_T_18 \| _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_20 = _tracegen_uop_uses_stq_T_19 \| _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_21 = _tracegen_uop_uses_stq_T_11 \| _tracegen_uop_uses_stq_T_20; // @[package.scala:81:59] assign _tracegen_uop_uses_stq_T_22 = _tracegen_uop_uses_stq_T_4 \| _tracegen_uop_uses_stq_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_uses_stq = _tracegen_uop_uses_stq_T_22; // @[Consts.scala:90:76] assign tracegen_uop_uopc = {1'h0, io_tracegen_req_bits_tag_0}; // @[tracegen.scala:20:7, :57:30, :61:29] wire _tracegen_uop_is_amo_T_4 = _tracegen_uop_is_amo_T \| _tracegen_uop_is_amo_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_5 = _tracegen_uop_is_amo_T_4 \| _tracegen_uop_is_amo_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_6 = _tracegen_uop_is_amo_T_5 \| _tracegen_uop_is_amo_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_12 = _tracegen_uop_is_amo_T_7 \| _tracegen_uop_is_amo_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_13 = _tracegen_uop_is_amo_T_12 \| _tracegen_uop_is_amo_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_14 = _tracegen_uop_is_amo_T_13 \| _tracegen_uop_is_amo_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_15 = _tracegen_uop_is_amo_T_14 \| _tracegen_uop_is_amo_T_11; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_16 = _tracegen_uop_is_amo_T_6 \| _tracegen_uop_is_amo_T_15; // @[package.scala:81:59] assign _tracegen_uop_is_amo_T_18 = _tracegen_uop_is_amo_T_16 \| _tracegen_uop_is_amo_T_17; // @[Consts.scala:87:44] assign tracegen_uop_is_amo = _tracegen_uop_is_amo_T_18; // @[tracegen.scala:57:30, :67:64] wire _tracegen_uop_ctrl_is_load_T_4 = _tracegen_uop_ctrl_is_load_T \| _tracegen_uop_ctrl_is_load_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_5 = _tracegen_uop_ctrl_is_load_T_4 \| _tracegen_uop_ctrl_is_load_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_6 = _tracegen_uop_ctrl_is_load_T_5 \| _tracegen_uop_ctrl_is_load_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_11 = _tracegen_uop_ctrl_is_load_T_7 \| _tracegen_uop_ctrl_is_load_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_12 = _tracegen_uop_ctrl_is_load_T_11 \| _tracegen_uop_ctrl_is_load_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_13 = _tracegen_uop_ctrl_is_load_T_12 \| _tracegen_uop_ctrl_is_load_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_19 = _tracegen_uop_ctrl_is_load_T_14 \| _tracegen_uop_ctrl_is_load_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_20 = _tracegen_uop_ctrl_is_load_T_19 \| _tracegen_uop_ctrl_is_load_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_21 = _tracegen_uop_ctrl_is_load_T_20 \| _tracegen_uop_ctrl_is_load_T_17; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_22 = _tracegen_uop_ctrl_is_load_T_21 \| _tracegen_uop_ctrl_is_load_T_18; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_23 = _tracegen_uop_ctrl_is_load_T_13 \| _tracegen_uop_ctrl_is_load_T_22; // @[package.scala:81:59] wire _tracegen_uop_ctrl_is_load_T_24 = _tracegen_uop_ctrl_is_load_T_6 \| _tracegen_uop_ctrl_is_load_T_23; // @[package.scala:81:59] wire _tracegen_uop_ctrl_is_load_T_27 = _tracegen_uop_ctrl_is_load_T_25 \| _tracegen_uop_ctrl_is_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_ctrl_is_load_T_29 = _tracegen_uop_ctrl_is_load_T_27 \| _tracegen_uop_ctrl_is_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_ctrl_is_load_T_34 = _tracegen_uop_ctrl_is_load_T_30 \| _tracegen_uop_ctrl_is_load_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_35 = _tracegen_uop_ctrl_is_load_T_34 \| _tracegen_uop_ctrl_is_load_T_32; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_36 = _tracegen_uop_ctrl_is_load_T_35 \| _tracegen_uop_ctrl_is_load_T_33; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_42 = _tracegen_uop_ctrl_is_load_T_37 \| _tracegen_uop_ctrl_is_load_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_43 = _tracegen_uop_ctrl_is_load_T_42 \| _tracegen_uop_ctrl_is_load_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_44 = _tracegen_uop_ctrl_is_load_T_43 \| _tracegen_uop_ctrl_is_load_T_40; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_45 = _tracegen_uop_ctrl_is_load_T_44 \| _tracegen_uop_ctrl_is_load_T_41; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_46 = _tracegen_uop_ctrl_is_load_T_36 \| _tracegen_uop_ctrl_is_load_T_45; // @[package.scala:81:59] wire _tracegen_uop_ctrl_is_load_T_47 = _tracegen_uop_ctrl_is_load_T_29 \| _tracegen_uop_ctrl_is_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_ctrl_is_load_T_48 = ~_tracegen_uop_ctrl_is_load_T_47; // @[Consts.scala:90:76] assign _tracegen_uop_ctrl_is_load_T_49 = _tracegen_uop_ctrl_is_load_T_24 & _tracegen_uop_ctrl_is_load_T_48; // @[Consts.scala:89:68] assign tracegen_uop_ctrl_is_load = _tracegen_uop_ctrl_is_load_T_49; // @[tracegen.scala:57:30, :68:65] wire _tracegen_uop_ctrl_is_sta_T_2 = _tracegen_uop_ctrl_is_sta_T \| _tracegen_uop_ctrl_is_sta_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_ctrl_is_sta_T_4 = _tracegen_uop_ctrl_is_sta_T_2 \| _tracegen_uop_ctrl_is_sta_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_ctrl_is_sta_T_9 = _tracegen_uop_ctrl_is_sta_T_5 \| _tracegen_uop_ctrl_is_sta_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_10 = _tracegen_uop_ctrl_is_sta_T_9 \| _tracegen_uop_ctrl_is_sta_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_11 = _tracegen_uop_ctrl_is_sta_T_10 \| _tracegen_uop_ctrl_is_sta_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_17 = _tracegen_uop_ctrl_is_sta_T_12 \| _tracegen_uop_ctrl_is_sta_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_18 = _tracegen_uop_ctrl_is_sta_T_17 \| _tracegen_uop_ctrl_is_sta_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_19 = _tracegen_uop_ctrl_is_sta_T_18 \| _tracegen_uop_ctrl_is_sta_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_20 = _tracegen_uop_ctrl_is_sta_T_19 \| _tracegen_uop_ctrl_is_sta_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_21 = _tracegen_uop_ctrl_is_sta_T_11 \| _tracegen_uop_ctrl_is_sta_T_20; // @[package.scala:81:59] assign _tracegen_uop_ctrl_is_sta_T_22 = _tracegen_uop_ctrl_is_sta_T_4 \| _tracegen_uop_ctrl_is_sta_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_ctrl_is_sta = _tracegen_uop_ctrl_is_sta_T_22; // @[Consts.scala:90:76] wire _tracegen_uop_ctrl_is_std_T_2 = _tracegen_uop_ctrl_is_std_T \| _tracegen_uop_ctrl_is_std_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_ctrl_is_std_T_4 = _tracegen_uop_ctrl_is_std_T_2 \| _tracegen_uop_ctrl_is_std_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_ctrl_is_std_T_9 = _tracegen_uop_ctrl_is_std_T_5 \| _tracegen_uop_ctrl_is_std_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_10 = _tracegen_uop_ctrl_is_std_T_9 \| _tracegen_uop_ctrl_is_std_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_11 = _tracegen_uop_ctrl_is_std_T_10 \| _tracegen_uop_ctrl_is_std_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_17 = _tracegen_uop_ctrl_is_std_T_12 \| _tracegen_uop_ctrl_is_std_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_18 = _tracegen_uop_ctrl_is_std_T_17 \| _tracegen_uop_ctrl_is_std_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_19 = _tracegen_uop_ctrl_is_std_T_18 \| _tracegen_uop_ctrl_is_std_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_20 = _tracegen_uop_ctrl_is_std_T_19 \| _tracegen_uop_ctrl_is_std_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_21 = _tracegen_uop_ctrl_is_std_T_11 \| _tracegen_uop_ctrl_is_std_T_20; // @[package.scala:81:59] assign _tracegen_uop_ctrl_is_std_T_22 = _tracegen_uop_ctrl_is_std_T_4 \| _tracegen_uop_ctrl_is_std_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_ctrl_is_std = _tracegen_uop_ctrl_is_std_T_22; // @[Consts.scala:90:76] wire _T = io_tracegen_req_ready_0 & io_tracegen_req_valid_0; // @[Decoupled.scala:51:35] assign _io_lsu_dis_uops_0_valid_T = _T; // @[Decoupled.scala:51:35] wire _io_lsu_exe_0_req_valid_T; // @[Decoupled.scala:51:35] assign _io_lsu_exe_0_req_valid_T = _T; // @[Decoupled.scala:51:35] assign io_lsu_dis_uops_0_valid_0 = _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire _rob_tail_T = &rob_tail; // @[tracegen.scala:37:25, :45:13] wire [5:0] _rob_tail_T_2 = _rob_tail_T_1[5:0]; // @[tracegen.scala:45:37] wire [5:0] _rob_tail_T_3 = _rob_tail_T ? 6'h0 : _rob_tail_T_2; // @[tracegen.scala:45:{8,13,37}] wire _io_lsu_commit_valids_0_T = ~_GEN[rob_head]; // @[tracegen.scala:36:25, :49:29, :95:31] wire _io_lsu_commit_valids_0_T_1 = rob_head != rob_tail; // @[tracegen.scala:36:25, :37:25, :95:62] wire _io_lsu_commit_valids_0_T_2 = _io_lsu_commit_valids_0_T & _io_lsu_commit_valids_0_T_1; // @[tracegen.scala:95:{31,50,62}] wire [63:0] _GEN_5 = {{rob_respd_63}, {rob_respd_62}, {rob_respd_61}, {rob_respd_60}, {rob_respd_59}, {rob_respd_58}, {rob_respd_57}, {rob_respd_56}, {rob_respd_55}, {rob_respd_54}, {rob_respd_53}, {rob_respd_52}, {rob_respd_51}, {rob_respd_50}, {rob_respd_49}, {rob_respd_48}, {rob_respd_47}, {rob_respd_46}, {rob_respd_45}, {rob_respd_44}, {rob_respd_43}, {rob_respd_42}, {rob_respd_41}, {rob_respd_40}, {rob_respd_39}, {rob_respd_38}, {rob_respd_37}, {rob_respd_36}, {rob_respd_35}, {rob_respd_34}, {rob_respd_33}, {rob_respd_32}, {rob_respd_31}, {rob_respd_30}, {rob_respd_29}, {rob_respd_28}, {rob_respd_27}, {rob_respd_26}, {rob_respd_25}, {rob_respd_24}, {rob_respd_23}, {rob_respd_22}, {rob_respd_21}, {rob_respd_20}, {rob_respd_19}, {rob_respd_18}, {rob_respd_17}, {rob_respd_16}, {rob_respd_15}, {rob_respd_14}, {rob_respd_13}, {rob_respd_12}, {rob_respd_11}, {rob_respd_10}, {rob_respd_9}, {rob_respd_8}, {rob_respd_7}, {rob_respd_6}, {rob_respd_5}, {rob_respd_4}, {rob_respd_3}, {rob_respd_2}, {rob_respd_1}, {rob_respd_0}}; // @[tracegen.scala:33:26, :95:75] assign _io_lsu_commit_valids_0_T_3 = _io_lsu_commit_valids_0_T_2 & _GEN_5[rob_head]; // @[tracegen.scala:36:25, :95:{50,75}] assign io_lsu_commit_valids_0_0 = _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:20:7, :95:75] wire [63:0][6:0] _GEN_6 = {{rob_uop_63_uopc}, {rob_uop_62_uopc}, {rob_uop_61_uopc}, {rob_uop_60_uopc}, {rob_uop_59_uopc}, {rob_uop_58_uopc}, {rob_uop_57_uopc}, {rob_uop_56_uopc}, {rob_uop_55_uopc}, {rob_uop_54_uopc}, {rob_uop_53_uopc}, {rob_uop_52_uopc}, {rob_uop_51_uopc}, {rob_uop_50_uopc}, {rob_uop_49_uopc}, {rob_uop_48_uopc}, {rob_uop_47_uopc}, {rob_uop_46_uopc}, {rob_uop_45_uopc}, {rob_uop_44_uopc}, {rob_uop_43_uopc}, {rob_uop_42_uopc}, {rob_uop_41_uopc}, {rob_uop_40_uopc}, {rob_uop_39_uopc}, {rob_uop_38_uopc}, {rob_uop_37_uopc}, {rob_uop_36_uopc}, {rob_uop_35_uopc}, {rob_uop_34_uopc}, {rob_uop_33_uopc}, {rob_uop_32_uopc}, {rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_uopc_0 = _GEN_6[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_7 = {{rob_uop_63_ctrl_is_load}, {rob_uop_62_ctrl_is_load}, {rob_uop_61_ctrl_is_load}, {rob_uop_60_ctrl_is_load}, {rob_uop_59_ctrl_is_load}, {rob_uop_58_ctrl_is_load}, {rob_uop_57_ctrl_is_load}, {rob_uop_56_ctrl_is_load}, {rob_uop_55_ctrl_is_load}, {rob_uop_54_ctrl_is_load}, {rob_uop_53_ctrl_is_load}, {rob_uop_52_ctrl_is_load}, {rob_uop_51_ctrl_is_load}, {rob_uop_50_ctrl_is_load}, {rob_uop_49_ctrl_is_load}, {rob_uop_48_ctrl_is_load}, {rob_uop_47_ctrl_is_load}, {rob_uop_46_ctrl_is_load}, {rob_uop_45_ctrl_is_load}, {rob_uop_44_ctrl_is_load}, {rob_uop_43_ctrl_is_load}, {rob_uop_42_ctrl_is_load}, {rob_uop_41_ctrl_is_load}, {rob_uop_40_ctrl_is_load}, {rob_uop_39_ctrl_is_load}, {rob_uop_38_ctrl_is_load}, {rob_uop_37_ctrl_is_load}, {rob_uop_36_ctrl_is_load}, {rob_uop_35_ctrl_is_load}, {rob_uop_34_ctrl_is_load}, {rob_uop_33_ctrl_is_load}, {rob_uop_32_ctrl_is_load}, {rob_uop_31_ctrl_is_load}, {rob_uop_30_ctrl_is_load}, {rob_uop_29_ctrl_is_load}, {rob_uop_28_ctrl_is_load}, {rob_uop_27_ctrl_is_load}, {rob_uop_26_ctrl_is_load}, {rob_uop_25_ctrl_is_load}, {rob_uop_24_ctrl_is_load}, {rob_uop_23_ctrl_is_load}, {rob_uop_22_ctrl_is_load}, {rob_uop_21_ctrl_is_load}, {rob_uop_20_ctrl_is_load}, {rob_uop_19_ctrl_is_load}, {rob_uop_18_ctrl_is_load}, {rob_uop_17_ctrl_is_load}, {rob_uop_16_ctrl_is_load}, {rob_uop_15_ctrl_is_load}, {rob_uop_14_ctrl_is_load}, {rob_uop_13_ctrl_is_load}, {rob_uop_12_ctrl_is_load}, {rob_uop_11_ctrl_is_load}, {rob_uop_10_ctrl_is_load}, {rob_uop_9_ctrl_is_load}, {rob_uop_8_ctrl_is_load}, {rob_uop_7_ctrl_is_load}, {rob_uop_6_ctrl_is_load}, {rob_uop_5_ctrl_is_load}, {rob_uop_4_ctrl_is_load}, {rob_uop_3_ctrl_is_load}, {rob_uop_2_ctrl_is_load}, {rob_uop_1_ctrl_is_load}, {rob_uop_0_ctrl_is_load}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ctrl_is_load_0 = _GEN_7[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_8 = {{rob_uop_63_ctrl_is_sta}, {rob_uop_62_ctrl_is_sta}, {rob_uop_61_ctrl_is_sta}, {rob_uop_60_ctrl_is_sta}, {rob_uop_59_ctrl_is_sta}, {rob_uop_58_ctrl_is_sta}, {rob_uop_57_ctrl_is_sta}, {rob_uop_56_ctrl_is_sta}, {rob_uop_55_ctrl_is_sta}, {rob_uop_54_ctrl_is_sta}, {rob_uop_53_ctrl_is_sta}, {rob_uop_52_ctrl_is_sta}, {rob_uop_51_ctrl_is_sta}, {rob_uop_50_ctrl_is_sta}, {rob_uop_49_ctrl_is_sta}, {rob_uop_48_ctrl_is_sta}, {rob_uop_47_ctrl_is_sta}, {rob_uop_46_ctrl_is_sta}, {rob_uop_45_ctrl_is_sta}, {rob_uop_44_ctrl_is_sta}, {rob_uop_43_ctrl_is_sta}, {rob_uop_42_ctrl_is_sta}, {rob_uop_41_ctrl_is_sta}, {rob_uop_40_ctrl_is_sta}, {rob_uop_39_ctrl_is_sta}, {rob_uop_38_ctrl_is_sta}, {rob_uop_37_ctrl_is_sta}, {rob_uop_36_ctrl_is_sta}, {rob_uop_35_ctrl_is_sta}, {rob_uop_34_ctrl_is_sta}, {rob_uop_33_ctrl_is_sta}, {rob_uop_32_ctrl_is_sta}, {rob_uop_31_ctrl_is_sta}, {rob_uop_30_ctrl_is_sta}, {rob_uop_29_ctrl_is_sta}, {rob_uop_28_ctrl_is_sta}, {rob_uop_27_ctrl_is_sta}, {rob_uop_26_ctrl_is_sta}, {rob_uop_25_ctrl_is_sta}, {rob_uop_24_ctrl_is_sta}, {rob_uop_23_ctrl_is_sta}, {rob_uop_22_ctrl_is_sta}, {rob_uop_21_ctrl_is_sta}, {rob_uop_20_ctrl_is_sta}, {rob_uop_19_ctrl_is_sta}, {rob_uop_18_ctrl_is_sta}, {rob_uop_17_ctrl_is_sta}, {rob_uop_16_ctrl_is_sta}, {rob_uop_15_ctrl_is_sta}, {rob_uop_14_ctrl_is_sta}, {rob_uop_13_ctrl_is_sta}, {rob_uop_12_ctrl_is_sta}, {rob_uop_11_ctrl_is_sta}, {rob_uop_10_ctrl_is_sta}, {rob_uop_9_ctrl_is_sta}, {rob_uop_8_ctrl_is_sta}, {rob_uop_7_ctrl_is_sta}, {rob_uop_6_ctrl_is_sta}, {rob_uop_5_ctrl_is_sta}, {rob_uop_4_ctrl_is_sta}, {rob_uop_3_ctrl_is_sta}, {rob_uop_2_ctrl_is_sta}, {rob_uop_1_ctrl_is_sta}, {rob_uop_0_ctrl_is_sta}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ctrl_is_sta_0 = _GEN_8[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_9 = {{rob_uop_63_ctrl_is_std}, {rob_uop_62_ctrl_is_std}, {rob_uop_61_ctrl_is_std}, {rob_uop_60_ctrl_is_std}, {rob_uop_59_ctrl_is_std}, {rob_uop_58_ctrl_is_std}, {rob_uop_57_ctrl_is_std}, {rob_uop_56_ctrl_is_std}, {rob_uop_55_ctrl_is_std}, {rob_uop_54_ctrl_is_std}, {rob_uop_53_ctrl_is_std}, {rob_uop_52_ctrl_is_std}, {rob_uop_51_ctrl_is_std}, {rob_uop_50_ctrl_is_std}, {rob_uop_49_ctrl_is_std}, {rob_uop_48_ctrl_is_std}, {rob_uop_47_ctrl_is_std}, {rob_uop_46_ctrl_is_std}, {rob_uop_45_ctrl_is_std}, {rob_uop_44_ctrl_is_std}, {rob_uop_43_ctrl_is_std}, {rob_uop_42_ctrl_is_std}, {rob_uop_41_ctrl_is_std}, {rob_uop_40_ctrl_is_std}, {rob_uop_39_ctrl_is_std}, {rob_uop_38_ctrl_is_std}, {rob_uop_37_ctrl_is_std}, {rob_uop_36_ctrl_is_std}, {rob_uop_35_ctrl_is_std}, {rob_uop_34_ctrl_is_std}, {rob_uop_33_ctrl_is_std}, {rob_uop_32_ctrl_is_std}, {rob_uop_31_ctrl_is_std}, {rob_uop_30_ctrl_is_std}, {rob_uop_29_ctrl_is_std}, {rob_uop_28_ctrl_is_std}, {rob_uop_27_ctrl_is_std}, {rob_uop_26_ctrl_is_std}, {rob_uop_25_ctrl_is_std}, {rob_uop_24_ctrl_is_std}, {rob_uop_23_ctrl_is_std}, {rob_uop_22_ctrl_is_std}, {rob_uop_21_ctrl_is_std}, {rob_uop_20_ctrl_is_std}, {rob_uop_19_ctrl_is_std}, {rob_uop_18_ctrl_is_std}, {rob_uop_17_ctrl_is_std}, {rob_uop_16_ctrl_is_std}, {rob_uop_15_ctrl_is_std}, {rob_uop_14_ctrl_is_std}, {rob_uop_13_ctrl_is_std}, {rob_uop_12_ctrl_is_std}, {rob_uop_11_ctrl_is_std}, {rob_uop_10_ctrl_is_std}, {rob_uop_9_ctrl_is_std}, {rob_uop_8_ctrl_is_std}, {rob_uop_7_ctrl_is_std}, {rob_uop_6_ctrl_is_std}, {rob_uop_5_ctrl_is_std}, {rob_uop_4_ctrl_is_std}, {rob_uop_3_ctrl_is_std}, {rob_uop_2_ctrl_is_std}, {rob_uop_1_ctrl_is_std}, {rob_uop_0_ctrl_is_std}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ctrl_is_std_0 = _GEN_9[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][5:0] _GEN_10 = {{rob_uop_63_rob_idx}, {rob_uop_62_rob_idx}, {rob_uop_61_rob_idx}, {rob_uop_60_rob_idx}, {rob_uop_59_rob_idx}, {rob_uop_58_rob_idx}, {rob_uop_57_rob_idx}, {rob_uop_56_rob_idx}, {rob_uop_55_rob_idx}, {rob_uop_54_rob_idx}, {rob_uop_53_rob_idx}, {rob_uop_52_rob_idx}, {rob_uop_51_rob_idx}, {rob_uop_50_rob_idx}, {rob_uop_49_rob_idx}, {rob_uop_48_rob_idx}, {rob_uop_47_rob_idx}, {rob_uop_46_rob_idx}, {rob_uop_45_rob_idx}, {rob_uop_44_rob_idx}, {rob_uop_43_rob_idx}, {rob_uop_42_rob_idx}, {rob_uop_41_rob_idx}, {rob_uop_40_rob_idx}, {rob_uop_39_rob_idx}, {rob_uop_38_rob_idx}, {rob_uop_37_rob_idx}, {rob_uop_36_rob_idx}, {rob_uop_35_rob_idx}, {rob_uop_34_rob_idx}, {rob_uop_33_rob_idx}, {rob_uop_32_rob_idx}, {rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_rob_idx_0 = _GEN_10[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][3:0] _GEN_11 = {{rob_uop_63_ldq_idx}, {rob_uop_62_ldq_idx}, {rob_uop_61_ldq_idx}, {rob_uop_60_ldq_idx}, {rob_uop_59_ldq_idx}, {rob_uop_58_ldq_idx}, {rob_uop_57_ldq_idx}, {rob_uop_56_ldq_idx}, {rob_uop_55_ldq_idx}, {rob_uop_54_ldq_idx}, {rob_uop_53_ldq_idx}, {rob_uop_52_ldq_idx}, {rob_uop_51_ldq_idx}, {rob_uop_50_ldq_idx}, {rob_uop_49_ldq_idx}, {rob_uop_48_ldq_idx}, {rob_uop_47_ldq_idx}, {rob_uop_46_ldq_idx}, {rob_uop_45_ldq_idx}, {rob_uop_44_ldq_idx}, {rob_uop_43_ldq_idx}, {rob_uop_42_ldq_idx}, {rob_uop_41_ldq_idx}, {rob_uop_40_ldq_idx}, {rob_uop_39_ldq_idx}, {rob_uop_38_ldq_idx}, {rob_uop_37_ldq_idx}, {rob_uop_36_ldq_idx}, {rob_uop_35_ldq_idx}, {rob_uop_34_ldq_idx}, {rob_uop_33_ldq_idx}, {rob_uop_32_ldq_idx}, {rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ldq_idx_0 = _GEN_11[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][3:0] _GEN_12 = {{rob_uop_63_stq_idx}, {rob_uop_62_stq_idx}, {rob_uop_61_stq_idx}, {rob_uop_60_stq_idx}, {rob_uop_59_stq_idx}, {rob_uop_58_stq_idx}, {rob_uop_57_stq_idx}, {rob_uop_56_stq_idx}, {rob_uop_55_stq_idx}, {rob_uop_54_stq_idx}, {rob_uop_53_stq_idx}, {rob_uop_52_stq_idx}, {rob_uop_51_stq_idx}, {rob_uop_50_stq_idx}, {rob_uop_49_stq_idx}, {rob_uop_48_stq_idx}, {rob_uop_47_stq_idx}, {rob_uop_46_stq_idx}, {rob_uop_45_stq_idx}, {rob_uop_44_stq_idx}, {rob_uop_43_stq_idx}, {rob_uop_42_stq_idx}, {rob_uop_41_stq_idx}, {rob_uop_40_stq_idx}, {rob_uop_39_stq_idx}, {rob_uop_38_stq_idx}, {rob_uop_37_stq_idx}, {rob_uop_36_stq_idx}, {rob_uop_35_stq_idx}, {rob_uop_34_stq_idx}, {rob_uop_33_stq_idx}, {rob_uop_32_stq_idx}, {rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_stq_idx_0 = _GEN_12[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][4:0] _GEN_13 = {{rob_uop_63_mem_cmd}, {rob_uop_62_mem_cmd}, {rob_uop_61_mem_cmd}, {rob_uop_60_mem_cmd}, {rob_uop_59_mem_cmd}, {rob_uop_58_mem_cmd}, {rob_uop_57_mem_cmd}, {rob_uop_56_mem_cmd}, {rob_uop_55_mem_cmd}, {rob_uop_54_mem_cmd}, {rob_uop_53_mem_cmd}, {rob_uop_52_mem_cmd}, {rob_uop_51_mem_cmd}, {rob_uop_50_mem_cmd}, {rob_uop_49_mem_cmd}, {rob_uop_48_mem_cmd}, {rob_uop_47_mem_cmd}, {rob_uop_46_mem_cmd}, {rob_uop_45_mem_cmd}, {rob_uop_44_mem_cmd}, {rob_uop_43_mem_cmd}, {rob_uop_42_mem_cmd}, {rob_uop_41_mem_cmd}, {rob_uop_40_mem_cmd}, {rob_uop_39_mem_cmd}, {rob_uop_38_mem_cmd}, {rob_uop_37_mem_cmd}, {rob_uop_36_mem_cmd}, {rob_uop_35_mem_cmd}, {rob_uop_34_mem_cmd}, {rob_uop_33_mem_cmd}, {rob_uop_32_mem_cmd}, {rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_mem_cmd_0 = _GEN_13[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_14 = {{rob_uop_63_is_amo}, {rob_uop_62_is_amo}, {rob_uop_61_is_amo}, {rob_uop_60_is_amo}, {rob_uop_59_is_amo}, {rob_uop_58_is_amo}, {rob_uop_57_is_amo}, {rob_uop_56_is_amo}, {rob_uop_55_is_amo}, {rob_uop_54_is_amo}, {rob_uop_53_is_amo}, {rob_uop_52_is_amo}, {rob_uop_51_is_amo}, {rob_uop_50_is_amo}, {rob_uop_49_is_amo}, {rob_uop_48_is_amo}, {rob_uop_47_is_amo}, {rob_uop_46_is_amo}, {rob_uop_45_is_amo}, {rob_uop_44_is_amo}, {rob_uop_43_is_amo}, {rob_uop_42_is_amo}, {rob_uop_41_is_amo}, {rob_uop_40_is_amo}, {rob_uop_39_is_amo}, {rob_uop_38_is_amo}, {rob_uop_37_is_amo}, {rob_uop_36_is_amo}, {rob_uop_35_is_amo}, {rob_uop_34_is_amo}, {rob_uop_33_is_amo}, {rob_uop_32_is_amo}, {rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_is_amo_0 = _GEN_14[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_15 = {{rob_uop_63_uses_ldq}, {rob_uop_62_uses_ldq}, {rob_uop_61_uses_ldq}, {rob_uop_60_uses_ldq}, {rob_uop_59_uses_ldq}, {rob_uop_58_uses_ldq}, {rob_uop_57_uses_ldq}, {rob_uop_56_uses_ldq}, {rob_uop_55_uses_ldq}, {rob_uop_54_uses_ldq}, {rob_uop_53_uses_ldq}, {rob_uop_52_uses_ldq}, {rob_uop_51_uses_ldq}, {rob_uop_50_uses_ldq}, {rob_uop_49_uses_ldq}, {rob_uop_48_uses_ldq}, {rob_uop_47_uses_ldq}, {rob_uop_46_uses_ldq}, {rob_uop_45_uses_ldq}, {rob_uop_44_uses_ldq}, {rob_uop_43_uses_ldq}, {rob_uop_42_uses_ldq}, {rob_uop_41_uses_ldq}, {rob_uop_40_uses_ldq}, {rob_uop_39_uses_ldq}, {rob_uop_38_uses_ldq}, {rob_uop_37_uses_ldq}, {rob_uop_36_uses_ldq}, {rob_uop_35_uses_ldq}, {rob_uop_34_uses_ldq}, {rob_uop_33_uses_ldq}, {rob_uop_32_uses_ldq}, {rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_uses_ldq_0 = _GEN_15[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_16 = {{rob_uop_63_uses_stq}, {rob_uop_62_uses_stq}, {rob_uop_61_uses_stq}, {rob_uop_60_uses_stq}, {rob_uop_59_uses_stq}, {rob_uop_58_uses_stq}, {rob_uop_57_uses_stq}, {rob_uop_56_uses_stq}, {rob_uop_55_uses_stq}, {rob_uop_54_uses_stq}, {rob_uop_53_uses_stq}, {rob_uop_52_uses_stq}, {rob_uop_51_uses_stq}, {rob_uop_50_uses_stq}, {rob_uop_49_uses_stq}, {rob_uop_48_uses_stq}, {rob_uop_47_uses_stq}, {rob_uop_46_uses_stq}, {rob_uop_45_uses_stq}, {rob_uop_44_uses_stq}, {rob_uop_43_uses_stq}, {rob_uop_42_uses_stq}, {rob_uop_41_uses_stq}, {rob_uop_40_uses_stq}, {rob_uop_39_uses_stq}, {rob_uop_38_uses_stq}, {rob_uop_37_uses_stq}, {rob_uop_36_uses_stq}, {rob_uop_35_uses_stq}, {rob_uop_34_uses_stq}, {rob_uop_33_uses_stq}, {rob_uop_32_uses_stq}, {rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_uses_stq_0 = _GEN_16[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire _rob_head_T = &rob_head; // @[tracegen.scala:36:25, :45:13] wire [6:0] _rob_head_T_1 = {1'h0, rob_head} + 7'h1; // @[tracegen.scala:36:25, :45:37] wire [5:0] _rob_head_T_2 = _rob_head_T_1[5:0]; // @[tracegen.scala:45:37] wire [5:0] _rob_head_T_3 = _rob_head_T ? 6'h0 : _rob_head_T_2; // @[tracegen.scala:45:{8,13,37}]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_14 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_14 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_14 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_11 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_12 : connect states[2].g, UInt<3>(0h2) node _T_13 = and(io.router_req.ready, io.router_req.valid) when _T_13 : node _T_14 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_14, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_18 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_18 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_19 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_19 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_20 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_20 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.router_resp.vc_sel.`5` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_21 = and(io.router_req.ready, io.router_req.valid) when _T_21 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_22 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_23 = or(_T_22, vcalloc_vals[2]) when _T_23 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[3] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE_14[1], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_14[2], _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>[1] node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_18[0], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_18 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[1] node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE_1.`5`, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_22 wire _io_vcalloc_req_bits_WIRE_23 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_24 : UInt<2> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_23.egress_node_id, _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_87 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_85) wire _io_vcalloc_req_bits_WIRE_25 : UInt<4> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_87 connect _io_vcalloc_req_bits_WIRE_23.egress_node, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_88, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_26 : UInt<3> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_92 connect _io_vcalloc_req_bits_WIRE_23.ingress_node_id, _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_27 : UInt<4> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_23.ingress_node, _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_100) wire _io_vcalloc_req_bits_WIRE_28 : UInt<2> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_102 connect _io_vcalloc_req_bits_WIRE_23.vnet_id, _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_23 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`4`[0] invalidate vcalloc_reqs[0].vc_sel.`5`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, states[1].vc_sel.`5` connect vcalloc_reqs[1].flow, states[1].flow node _T_24 = bits(vcalloc_sel, 1, 1) node _T_25 = and(vcalloc_vals[1], _T_24) node _T_26 = and(_T_25, io.vcalloc_req.ready) when _T_26 : connect states[1].g, UInt<3>(0h3) node _T_27 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_27 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, states[2].vc_sel.`5` connect vcalloc_reqs[2].flow, states[2].flow node _T_28 = bits(vcalloc_sel, 2, 2) node _T_29 = and(vcalloc_vals[2], _T_28) node _T_30 = and(_T_29, io.vcalloc_req.ready) when _T_30 : connect states[2].g, UInt<3>(0h3) node _T_31 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_31 : connect vcalloc_vals[2], UInt<1>(0h1) connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, io.router_resp.vc_sel.`5` node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_32 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_32 : node _T_33 = bits(vcalloc_sel, 0, 0) when _T_33 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[0].g, UInt<3>(0h3) node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[1].g, UInt<3>(0h3) node _T_35 = bits(vcalloc_sel, 2, 2) when _T_35 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_35 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`5`[0] node credit_available_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[1].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[1].vc_sel.`1`[2], states[1].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[1].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[1].vc_sel.`2`[2], states[1].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[1].vc_sel.`2`[0]) node credit_available_hi_3 = cat(states[1].vc_sel.`3`[2], states[1].vc_sel.`3`[1]) node _credit_available_T_3 = cat(credit_available_hi_3, states[1].vc_sel.`3`[0]) node credit_available_lo_hi = cat(_credit_available_T_2, _credit_available_T_1) node credit_available_lo = cat(credit_available_lo_hi, _credit_available_T) node credit_available_hi_hi = cat(states[1].vc_sel.`5`[0], states[1].vc_sel.`4`[0]) node credit_available_hi_4 = cat(credit_available_hi_hi, _credit_available_T_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo) node credit_available_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`1`[0]) node credit_available_hi_7 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_7 = cat(credit_available_hi_7, io.out_credit_available.`2`[0]) node credit_available_hi_8 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_8 = cat(credit_available_hi_8, io.out_credit_available.`3`[0]) node credit_available_lo_hi_1 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_lo_1 = cat(credit_available_lo_hi_1, _credit_available_T_5) node credit_available_hi_hi_1 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_9 = cat(credit_available_hi_hi_1, _credit_available_T_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_1) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`5`[0], states[1].vc_sel.`5`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_36 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_37 = and(_T_36, input_buffer.io.deq[1].bits.tail) when _T_37 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_hi_10 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node _credit_available_T_11 = cat(credit_available_hi_10, states[2].vc_sel.`0`[0]) node credit_available_hi_11 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1]) node _credit_available_T_12 = cat(credit_available_hi_11, states[2].vc_sel.`1`[0]) node credit_available_hi_12 = cat(states[2].vc_sel.`2`[2], states[2].vc_sel.`2`[1]) node _credit_available_T_13 = cat(credit_available_hi_12, states[2].vc_sel.`2`[0]) node credit_available_hi_13 = cat(states[2].vc_sel.`3`[2], states[2].vc_sel.`3`[1]) node _credit_available_T_14 = cat(credit_available_hi_13, states[2].vc_sel.`3`[0]) node credit_available_lo_hi_2 = cat(_credit_available_T_13, _credit_available_T_12) node credit_available_lo_2 = cat(credit_available_lo_hi_2, _credit_available_T_11) node credit_available_hi_hi_2 = cat(states[2].vc_sel.`5`[0], states[2].vc_sel.`4`[0]) node credit_available_hi_14 = cat(credit_available_hi_hi_2, _credit_available_T_14) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_2) node credit_available_hi_15 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_16 = cat(credit_available_hi_15, io.out_credit_available.`0`[0]) node credit_available_hi_16 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_17 = cat(credit_available_hi_16, io.out_credit_available.`1`[0]) node credit_available_hi_17 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_18 = cat(credit_available_hi_17, io.out_credit_available.`2`[0]) node credit_available_hi_18 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_19 = cat(credit_available_hi_18, io.out_credit_available.`3`[0]) node credit_available_lo_hi_3 = cat(_credit_available_T_18, _credit_available_T_17) node credit_available_lo_3 = cat(credit_available_lo_hi_3, _credit_available_T_16) node credit_available_hi_hi_3 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_19 = cat(credit_available_hi_hi_3, _credit_available_T_19) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_3) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`5`[0], states[2].vc_sel.`5`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_38 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_39 = and(_T_38, input_buffer.io.deq[2].bits.tail) when _T_39 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[3] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_55) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_57 connect _vc_sel_WIRE_12[1], _vc_sel_WIRE_14 node _vc_sel_T_58 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_58, _vc_sel_T_59) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_60) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_62 connect _vc_sel_WIRE_12[2], _vc_sel_WIRE_15 connect vc_sel.`3`, _vc_sel_WIRE_12 wire _vc_sel_WIRE_16 : UInt<1>[1] node _vc_sel_T_63 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_66 = or(_vc_sel_T_63, _vc_sel_T_64) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_65) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_67 connect _vc_sel_WIRE_16[0], _vc_sel_WIRE_17 connect vc_sel.`4`, _vc_sel_WIRE_16 wire _vc_sel_WIRE_18 : UInt<1>[1] node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_71 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_72 = or(_vc_sel_T_71, _vc_sel_T_70) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_72 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 connect vc_sel.`5`, _vc_sel_WIRE_18 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node _channel_oh_T_3 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node channel_oh_3 = or(_channel_oh_T_3, vc_sel.`3`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node virt_channel_hi_6 = cat(vc_sel.`3`[2], vc_sel.`3`[1]) node _virt_channel_T_15 = cat(virt_channel_hi_6, vc_sel.`3`[0]) node virt_channel_hi_7 = bits(_virt_channel_T_15, 2, 2) node virt_channel_lo_3 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_3) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_21 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_22 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_23 = mux(channel_oh_3, _virt_channel_T_19, UInt<1>(0h0)) node _virt_channel_T_24 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_25 = mux(vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_26 = or(_virt_channel_T_20, _virt_channel_T_21) node _virt_channel_T_27 = or(_virt_channel_T_26, _virt_channel_T_22) node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_23) node _virt_channel_T_29 = or(_virt_channel_T_28, _virt_channel_T_24) node _virt_channel_T_30 = or(_virt_channel_T_29, _virt_channel_T_25) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_30 node _T_40 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_40 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`4`[0] invalidate states[0].vc_sel.`5`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[1], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) node _T_41 = asUInt(reset) when _T_41 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)	module InputUnit_14( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire _GEN_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_3_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_2_2; // @[MixedVec.scala:116:9] wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_1; // @[MixedVec.scala:116:9] wire _GEN_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_3_1; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_2_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_3 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_4 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_5 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_128 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_129 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_130 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 1 parameter FORMAT = "uart_tx=%d" parameter WIDTH = 32 extmodule plusarg_reader_131 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "uart_tx_printf=%d" parameter WIDTH = 32	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_Phit_19 : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<4> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_39 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<4> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) node _index_T = bits(ridx, 2, 0) node _index_T_1 = bits(ridx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w32_19 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset connect io_deq_bits_deq_bits_reg.io.d, io.async.mem[index].phit connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { phit : UInt<32>} wire _io_deq_bits_WIRE_1 : UInt<32> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 31, 0) connect _io_deq_bits_WIRE.phit, _io_deq_bits_T connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_180 inst sink_valid_1 of AsyncValidSync_181 inst source_extend of AsyncValidSync_182 inst source_valid of AsyncValidSync_183 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1	module AsyncQueueSink_Phit_19( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18] wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T \| _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T \| _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T \| _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_198 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_198( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_63 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_63( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_32 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_32( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Pipeline_4 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, busy : UInt<1>} reg stages : { data : UInt<128>, fromDMA : UInt<1>}[4], clock wire _valids_WIRE : UInt<1>[4] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) regreset valids : UInt<1>[4], clock, reset, _valids_WIRE wire stalling : UInt<1>[4] connect stalling[0], UInt<1>(0h0) connect stalling[1], UInt<1>(0h0) connect stalling[2], UInt<1>(0h0) connect stalling[3], UInt<1>(0h0) node _io_busy_T = or(valids[0], valids[1]) node _io_busy_T_1 = or(_io_busy_T, valids[2]) node _io_busy_T_2 = or(_io_busy_T_1, valids[3]) node _io_busy_T_3 = or(io.in.valid, _io_busy_T_2) connect io.busy, _io_busy_T_3 node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_3_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_3_T_1 = and(valids[3], _stalling_3_T) connect stalling[3], _stalling_3_T_1 node _stalling_0_T = and(valids[0], stalling[1]) connect stalling[0], _stalling_0_T node _stalling_1_T = and(valids[1], stalling[2]) connect stalling[1], _stalling_1_T node _stalling_2_T = and(valids[2], stalling[3]) connect stalling[2], _stalling_2_T connect io.out.valid, valids[3] when io.out.ready : connect valids[3], UInt<1>(0h0) node _T = eq(stalling[1], UInt<1>(0h0)) when _T : connect valids[0], UInt<1>(0h0) node _T_1 = eq(stalling[2], UInt<1>(0h0)) when _T_1 : connect valids[1], UInt<1>(0h0) node _T_2 = eq(stalling[3], UInt<1>(0h0)) when _T_2 : connect valids[2], UInt<1>(0h0) node _T_3 = and(io.in.ready, io.in.valid) when _T_3 : connect valids[0], UInt<1>(0h1) when valids[0] : connect valids[1], UInt<1>(0h1) when valids[1] : connect valids[2], UInt<1>(0h1) when valids[2] : connect valids[3], UInt<1>(0h1) node _T_4 = and(io.in.ready, io.in.valid) when _T_4 : connect stages[0], io.in.bits connect io.out.bits, stages[3] node _T_5 = eq(stalling[1], UInt<1>(0h0)) when _T_5 : connect stages[1], stages[0] node _T_6 = eq(stalling[2], UInt<1>(0h0)) when _T_6 : connect stages[2], stages[1] node _T_7 = eq(stalling[3], UInt<1>(0h0)) when _T_7 : connect stages[3], stages[2]	module Pipeline_4( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14] input io_in_bits_fromDMA, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_data, // @[Pipeline.scala:7:14] output io_out_bits_fromDMA // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7] wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_3; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7] wire io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [127:0] stages_0_data; // @[Pipeline.scala:21:21] reg stages_0_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_1_data; // @[Pipeline.scala:21:21] reg stages_1_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_2_data; // @[Pipeline.scala:21:21] reg stages_2_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_3_data; // @[Pipeline.scala:21:21] assign io_out_bits_data_0 = stages_3_data; // @[Pipeline.scala:6:7, :21:21] reg stages_3_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_fromDMA_0 = stages_3_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 \| valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T \| valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 \| valids_3; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_3 = io_in_valid_0 \| _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_4) begin // @[Decoupled.scala:51:35] stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_data <= stages_0_data; // @[Pipeline.scala:21:21] stages_1_fromDMA <= stages_0_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_data <= stages_1_data; // @[Pipeline.scala:21:21] stages_2_fromDMA <= stages_1_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_data <= stages_2_data; // @[Pipeline.scala:21:21] stages_3_fromDMA <= stages_2_fromDMA; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_4 \| stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 \| stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 \| stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 \| ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7] assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AXI4IdIndexer : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.echo.extra_id invalidate nodeOut.r.bits.echo.tl_state.source invalidate nodeOut.r.bits.echo.tl_state.size invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.echo.extra_id invalidate nodeOut.ar.bits.echo.tl_state.source invalidate nodeOut.ar.bits.echo.tl_state.size invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.echo.extra_id invalidate nodeOut.b.bits.echo.tl_state.source invalidate nodeOut.b.bits.echo.tl_state.size invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.echo.extra_id invalidate nodeOut.aw.bits.echo.tl_state.source invalidate nodeOut.aw.bits.echo.tl_state.size invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.ar.bits.echo.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect nodeOut.ar.bits.echo.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id connect nodeOut.ar.valid, nodeIn.ar.valid connect nodeIn.ar.ready, nodeOut.ar.ready connect nodeOut.aw.bits.echo.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect nodeOut.aw.bits.echo.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id connect nodeOut.aw.valid, nodeIn.aw.valid connect nodeIn.aw.ready, nodeOut.aw.ready connect nodeOut.w.bits.last, nodeIn.w.bits.last connect nodeOut.w.bits.strb, nodeIn.w.bits.strb connect nodeOut.w.bits.data, nodeIn.w.bits.data connect nodeOut.w.valid, nodeIn.w.valid connect nodeIn.w.ready, nodeOut.w.ready connect nodeIn.b.bits.echo.tl_state.source, nodeOut.b.bits.echo.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, nodeOut.b.bits.echo.tl_state.size connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.echo.tl_state.source, nodeOut.r.bits.echo.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, nodeOut.r.bits.echo.tl_state.size connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready node _nodeOut_ar_bits_echo_extra_id_T = shr(nodeIn.ar.bits.id, 4) connect nodeOut.ar.bits.echo.extra_id, _nodeOut_ar_bits_echo_extra_id_T node _nodeOut_aw_bits_echo_extra_id_T = shr(nodeIn.aw.bits.id, 4) connect nodeOut.aw.bits.echo.extra_id, _nodeOut_aw_bits_echo_extra_id_T node _nodeIn_r_bits_id_T = cat(nodeOut.r.bits.echo.extra_id, nodeOut.r.bits.id) connect nodeIn.r.bits.id, _nodeIn_r_bits_id_T node _nodeIn_b_bits_id_T = cat(nodeOut.b.bits.echo.extra_id, nodeOut.b.bits.id) connect nodeIn.b.bits.id, _nodeIn_b_bits_id_T extmodule plusarg_reader_126 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_127 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module AXI4IdIndexer( // @[IdIndexer.scala:63:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); assign auto_in_aw_ready = auto_out_aw_ready; // @[IdIndexer.scala:63:9] assign auto_in_w_ready = auto_out_w_ready; // @[IdIndexer.scala:63:9] assign auto_in_b_valid = auto_out_b_valid; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id = {auto_out_b_bits_echo_extra_id, auto_out_b_bits_id}; // @[IdIndexer.scala:63:9, :97:30] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready = auto_out_ar_ready; // @[IdIndexer.scala:63:9] assign auto_in_r_valid = auto_out_r_valid; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id = {auto_out_r_bits_echo_extra_id, auto_out_r_bits_id}; // @[IdIndexer.scala:63:9, :96:30] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last = auto_out_r_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_aw_valid = auto_in_aw_valid; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id = auto_in_aw_bits_id[3:0]; // @[IdIndexer.scala:63:9, :72:43] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_extra_id = auto_in_aw_bits_id[6:4]; // @[IdIndexer.scala:63:9, :88:56] assign auto_out_w_valid = auto_in_w_valid; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_b_ready = auto_in_b_ready; // @[IdIndexer.scala:63:9] assign auto_out_ar_valid = auto_in_ar_valid; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id = auto_in_ar_bits_id[3:0]; // @[IdIndexer.scala:63:9, :69:43] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_extra_id = auto_in_ar_bits_id[6:4]; // @[IdIndexer.scala:63:9, :87:56] assign auto_out_r_ready = auto_in_r_ready; // @[IdIndexer.scala:63:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_97 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_114 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_97( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_114 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IceNicController : input clock : Clock input reset : Reset output auto : { flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_xing_out : { sync : UInt<1>[2]}} output io : { send : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip comp : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}}, recv : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip comp : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}}, flip macAddr : UInt<48>, txcsumReq : { flip ready : UInt<1>, valid : UInt<1>, bits : { check : UInt<1>, offset : UInt<16>, start : UInt<16>, init : UInt<16>}}, flip rxcsumRes : { flip ready : UInt<1>, valid : UInt<1>, bits : { correct : UInt<1>, checked : UInt<1>}}, csumEnable : UInt<1>} inst intsource of IntSyncCrossingSource_n1x2_1 connect intsource.clock, clock connect intsource.reset, reset inst buffer of TLBuffer_a29d64s12k1z2u_1 connect buffer.clock, clock connect buffer.reset, reset wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_60 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire intnodeOut : UInt<1>[2] invalidate intnodeOut[0] invalidate intnodeOut[1] wire intXingOut : { sync : UInt<1>[2]} invalidate intXingOut.sync[0] invalidate intXingOut.sync[1] wire intXingIn : { sync : UInt<1>[2]} invalidate intXingIn.sync[0] invalidate intXingIn.sync[1] connect intXingOut, intXingIn wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn connect intsource.auto.in[0], intnodeOut[0] connect intsource.auto.in[1], intnodeOut[1] connect intXingIn, intsource.auto.out connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect auto.int_xing_out, intXingOut connect controlXingIn, auto.control_xing_in wire sendCompDown : UInt<1> connect sendCompDown, UInt<1>(0h0) inst sendReqQueue of HellaQueue connect sendReqQueue.clock, clock connect sendReqQueue.reset, reset node _sendReqCount_T = and(sendReqQueue.io.enq.ready, sendReqQueue.io.enq.valid) node _sendReqCount_T_1 = and(sendReqQueue.io.deq.ready, sendReqQueue.io.deq.valid) regreset sendReqCount : UInt<7>, clock, reset, UInt<7>(0h0) node _sendReqCount_T_2 = eq(_sendReqCount_T_1, UInt<1>(0h0)) node _sendReqCount_T_3 = and(_sendReqCount_T, _sendReqCount_T_2) when _sendReqCount_T_3 : node _sendReqCount_cnt_T = add(sendReqCount, UInt<1>(0h1)) node _sendReqCount_cnt_T_1 = tail(_sendReqCount_cnt_T, 1) connect sendReqCount, _sendReqCount_cnt_T_1 node _sendReqCount_T_4 = eq(_sendReqCount_T, UInt<1>(0h0)) node _sendReqCount_T_5 = and(_sendReqCount_T_1, _sendReqCount_T_4) when _sendReqCount_T_5 : node _sendReqCount_cnt_T_2 = sub(sendReqCount, UInt<1>(0h1)) node _sendReqCount_cnt_T_3 = tail(_sendReqCount_cnt_T_2, 1) connect sendReqCount, _sendReqCount_cnt_T_3 inst recvReqQueue of HellaQueue_1 connect recvReqQueue.clock, clock connect recvReqQueue.reset, reset node _recvReqCount_T = and(recvReqQueue.io.enq.ready, recvReqQueue.io.enq.valid) node _recvReqCount_T_1 = and(recvReqQueue.io.deq.ready, recvReqQueue.io.deq.valid) regreset recvReqCount : UInt<7>, clock, reset, UInt<7>(0h0) node _recvReqCount_T_2 = eq(_recvReqCount_T_1, UInt<1>(0h0)) node _recvReqCount_T_3 = and(_recvReqCount_T, _recvReqCount_T_2) when _recvReqCount_T_3 : node _recvReqCount_cnt_T = add(recvReqCount, UInt<1>(0h1)) node _recvReqCount_cnt_T_1 = tail(_recvReqCount_cnt_T, 1) connect recvReqCount, _recvReqCount_cnt_T_1 node _recvReqCount_T_4 = eq(_recvReqCount_T, UInt<1>(0h0)) node _recvReqCount_T_5 = and(_recvReqCount_T_1, _recvReqCount_T_4) when _recvReqCount_T_5 : node _recvReqCount_cnt_T_2 = sub(recvReqCount, UInt<1>(0h1)) node _recvReqCount_cnt_T_3 = tail(_recvReqCount_cnt_T_2, 1) connect recvReqCount, _recvReqCount_cnt_T_3 node _sendCompCount_T = and(io.send.comp.ready, io.send.comp.valid) regreset sendCompCount : UInt<7>, clock, reset, UInt<7>(0h0) node _sendCompCount_T_1 = eq(sendCompDown, UInt<1>(0h0)) node _sendCompCount_T_2 = and(_sendCompCount_T, _sendCompCount_T_1) when _sendCompCount_T_2 : node _sendCompCount_cnt_T = add(sendCompCount, UInt<1>(0h1)) node _sendCompCount_cnt_T_1 = tail(_sendCompCount_cnt_T, 1) connect sendCompCount, _sendCompCount_cnt_T_1 node _sendCompCount_T_3 = eq(_sendCompCount_T, UInt<1>(0h0)) node _sendCompCount_T_4 = and(sendCompDown, _sendCompCount_T_3) when _sendCompCount_T_4 : node _sendCompCount_cnt_T_2 = sub(sendCompCount, UInt<1>(0h1)) node _sendCompCount_cnt_T_3 = tail(_sendCompCount_cnt_T_2, 1) connect sendCompCount, _sendCompCount_cnt_T_3 inst recvCompQueue of HellaQueue_2 connect recvCompQueue.clock, clock connect recvCompQueue.reset, reset node _recvCompCount_T = and(recvCompQueue.io.enq.ready, recvCompQueue.io.enq.valid) node _recvCompCount_T_1 = and(recvCompQueue.io.deq.ready, recvCompQueue.io.deq.valid) regreset recvCompCount : UInt<7>, clock, reset, UInt<7>(0h0) node _recvCompCount_T_2 = eq(_recvCompCount_T_1, UInt<1>(0h0)) node _recvCompCount_T_3 = and(_recvCompCount_T, _recvCompCount_T_2) when _recvCompCount_T_3 : node _recvCompCount_cnt_T = add(recvCompCount, UInt<1>(0h1)) node _recvCompCount_cnt_T_1 = tail(_recvCompCount_cnt_T, 1) connect recvCompCount, _recvCompCount_cnt_T_1 node _recvCompCount_T_4 = eq(_recvCompCount_T, UInt<1>(0h0)) node _recvCompCount_T_5 = and(_recvCompCount_T_1, _recvCompCount_T_4) when _recvCompCount_T_5 : node _recvCompCount_cnt_T_2 = sub(recvCompCount, UInt<1>(0h1)) node _recvCompCount_cnt_T_3 = tail(_recvCompCount_cnt_T_2, 1) connect recvCompCount, _recvCompCount_cnt_T_3 node sendCompValid = gt(sendCompCount, UInt<1>(0h0)) regreset intMask : UInt<2>, clock, reset, UInt<2>(0h0) connect io.send.req.bits, sendReqQueue.io.deq.bits connect io.send.req.valid, sendReqQueue.io.deq.valid connect sendReqQueue.io.deq.ready, io.send.req.ready connect io.recv.req.bits, recvReqQueue.io.deq.bits connect io.recv.req.valid, recvReqQueue.io.deq.valid connect recvReqQueue.io.deq.ready, io.recv.req.ready node _io_send_comp_ready_T = lt(sendCompCount, UInt<7>(0h40)) connect io.send.comp.ready, _io_send_comp_ready_T connect recvCompQueue.io.enq, io.recv.comp node _intnodeOut_0_T = bits(intMask, 0, 0) node _intnodeOut_0_T_1 = and(sendCompValid, _intnodeOut_0_T) connect intnodeOut[0], _intnodeOut_0_T_1 node _intnodeOut_1_T = bits(intMask, 1, 1) node _intnodeOut_1_T_1 = and(recvCompQueue.io.deq.valid, _intnodeOut_1_T) connect intnodeOut[1], _intnodeOut_1_T_1 node _sendReqSpace_T = sub(UInt<7>(0h40), sendReqCount) node sendReqSpace = tail(_sendReqSpace_T, 1) node _recvReqSpace_T = sub(UInt<7>(0h40), recvReqCount) node recvReqSpace = tail(_recvReqSpace_T, 1) inst txcsumReqQueue of HellaQueue_3 connect txcsumReqQueue.clock, clock connect txcsumReqQueue.reset, reset inst rxcsumResQueue of HellaQueue_4 connect rxcsumResQueue.clock, clock connect rxcsumResQueue.reset, reset regreset csumEnable : UInt<1>, clock, reset, UInt<1>(0h0) connect io.txcsumReq.valid, txcsumReqQueue.io.deq.valid wire _io_txcsumReq_bits_WIRE : { check : UInt<1>, offset : UInt<16>, start : UInt<16>, init : UInt<16>} wire _io_txcsumReq_bits_WIRE_1 : UInt<49> connect _io_txcsumReq_bits_WIRE_1, txcsumReqQueue.io.deq.bits node _io_txcsumReq_bits_T = bits(_io_txcsumReq_bits_WIRE_1, 15, 0) connect _io_txcsumReq_bits_WIRE.init, _io_txcsumReq_bits_T node _io_txcsumReq_bits_T_1 = bits(_io_txcsumReq_bits_WIRE_1, 31, 16) connect _io_txcsumReq_bits_WIRE.start, _io_txcsumReq_bits_T_1 node _io_txcsumReq_bits_T_2 = bits(_io_txcsumReq_bits_WIRE_1, 47, 32) connect _io_txcsumReq_bits_WIRE.offset, _io_txcsumReq_bits_T_2 node _io_txcsumReq_bits_T_3 = bits(_io_txcsumReq_bits_WIRE_1, 48, 48) connect _io_txcsumReq_bits_WIRE.check, _io_txcsumReq_bits_T_3 connect io.txcsumReq.bits, _io_txcsumReq_bits_WIRE connect txcsumReqQueue.io.deq.ready, io.txcsumReq.ready connect rxcsumResQueue.io.enq.valid, io.rxcsumRes.valid node _rxcsumResQueue_io_enq_bits_T = cat(io.rxcsumRes.bits.correct, io.rxcsumRes.bits.checked) connect rxcsumResQueue.io.enq.bits, _rxcsumResQueue_io_enq_bits_T connect io.rxcsumRes.ready, rxcsumResQueue.io.enq.ready connect io.csumEnable, csumEnable wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h7)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) node _out_T_8 = eq(out_findex, UInt<9>(0h0)) node _out_T_9 = eq(out_bindex, UInt<9>(0h0)) node _out_T_10 = eq(out_findex, UInt<9>(0h0)) node _out_T_11 = eq(out_bindex, UInt<9>(0h0)) node _out_T_12 = eq(out_findex, UInt<9>(0h0)) node _out_T_13 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[13] wire out_wivalid : UInt<1>[13] wire out_roready : UInt<1>[13] wire out_woready : UInt<1>[13] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 63, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 63, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 63, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 63, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_14 = bits(out_front.bits.data, 63, 0) connect sendReqQueue.io.enq.valid, out_f_woready connect sendReqQueue.io.enq.bits, _out_T_14 node _out_T_15 = eq(out_rimask, UInt<1>(0h0)) node _out_T_16 = eq(out_wimask, UInt<1>(0h0)) node _out_T_17 = eq(out_romask, UInt<1>(0h0)) node _out_T_18 = eq(out_womask, UInt<1>(0h0)) node _out_T_19 = or(sendReqQueue.io.enq.ready, _out_T_18) node _out_T_20 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_21 = bits(_out_T_20, 63, 0) node _out_rimask_T_1 = bits(out_frontMask, 48, 0) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 48, 0) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 48, 0) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 48, 0) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_22 = bits(out_front.bits.data, 48, 0) connect txcsumReqQueue.io.enq.valid, out_f_woready_1 connect txcsumReqQueue.io.enq.bits, _out_T_22 node _out_T_23 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_24 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_25 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_26 = eq(out_womask_1, UInt<1>(0h0)) node _out_T_27 = or(txcsumReqQueue.io.enq.ready, _out_T_26) node _out_T_28 = or(UInt<1>(0h0), UInt<49>(0h0)) node _out_T_29 = bits(_out_T_28, 48, 0) node _out_rimask_T_2 = bits(out_frontMask, 63, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 63, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 63, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 63, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_30 = bits(out_front.bits.data, 63, 0) connect recvReqQueue.io.enq.valid, out_f_woready_2 connect recvReqQueue.io.enq.bits, _out_T_30 node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_35 = or(recvReqQueue.io.enq.ready, _out_T_34) node _out_T_36 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_37 = bits(_out_T_36, 63, 0) node _out_rimask_T_3 = bits(out_frontMask, 1, 0) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 1, 0) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 1, 0) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 1, 0) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxcsumResQueue.io.deq.ready, out_f_roready_3 node _out_T_38 = bits(out_front.bits.data, 1, 0) node _out_T_39 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_42 = or(rxcsumResQueue.io.deq.valid, _out_T_41) node _out_T_43 = eq(out_womask_3, UInt<1>(0h0)) node _out_T_44 = or(rxcsumResQueue.io.deq.bits, UInt<2>(0h0)) node _out_T_45 = bits(_out_T_44, 1, 0) node _out_rimask_T_4 = bits(out_frontMask, 8, 8) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 8, 8) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 8, 8) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 8, 8) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_46 = bits(out_front.bits.data, 8, 8) when out_f_woready_4 : connect csumEnable, _out_T_46 node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_45, UInt<8>(0h0)) node out_prepend = cat(csumEnable, _out_prepend_T) node _out_T_51 = or(out_prepend, UInt<9>(0h0)) node _out_T_52 = bits(_out_T_51, 8, 0) node _out_rimask_T_5 = bits(out_frontMask, 0, 0) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 0, 0) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 0, 0) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 0, 0) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_sendCompDown_T = and(sendCompValid, out_f_roready_5) connect sendCompDown, _out_sendCompDown_T node _out_T_53 = bits(out_front.bits.data, 0, 0) node _out_T_54 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_55 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_56 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_57 = or(sendCompValid, _out_T_56) node _out_T_58 = eq(out_womask_5, UInt<1>(0h0)) node _out_T_59 = or(UInt<1>(0h1), UInt<1>(0h0)) node _out_T_60 = bits(_out_T_59, 0, 0) node _out_rimask_T_6 = bits(out_frontMask, 31, 16) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 31, 16) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 31, 16) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 31, 16) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) connect recvCompQueue.io.deq.ready, out_f_roready_6 node _out_T_61 = bits(out_front.bits.data, 31, 16) node _out_T_62 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_63 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_64 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_65 = or(recvCompQueue.io.deq.valid, _out_T_64) node _out_T_66 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_60, UInt<16>(0h0)) node out_prepend_1 = cat(recvCompQueue.io.deq.bits, _out_prepend_T_1) node _out_T_67 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_68 = bits(_out_T_67, 31, 0) node _out_rimask_T_7 = bits(out_frontMask, 39, 32) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 39, 32) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 39, 32) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 39, 32) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_69 = bits(out_front.bits.data, 39, 32) node _out_T_70 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_71 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_72 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_73 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_68, UInt<32>(0h0)) node out_prepend_2 = cat(sendReqSpace, _out_prepend_T_2) node _out_T_74 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_75 = bits(_out_T_74, 39, 0) node _out_rimask_T_8 = bits(out_frontMask, 47, 40) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 47, 40) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 47, 40) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 47, 40) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_76 = bits(out_front.bits.data, 47, 40) node _out_T_77 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_78 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_79 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_80 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_75, UInt<40>(0h0)) node out_prepend_3 = cat(recvReqSpace, _out_prepend_T_3) node _out_T_81 = or(out_prepend_3, UInt<48>(0h0)) node _out_T_82 = bits(_out_T_81, 47, 0) node _out_rimask_T_9 = bits(out_frontMask, 55, 48) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 55, 48) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 55, 48) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 55, 48) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_83 = bits(out_front.bits.data, 55, 48) node _out_T_84 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_85 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_86 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_87 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_82, UInt<48>(0h0)) node out_prepend_4 = cat(sendCompCount, _out_prepend_T_4) node _out_T_88 = or(out_prepend_4, UInt<56>(0h0)) node _out_T_89 = bits(_out_T_88, 55, 0) node _out_rimask_T_10 = bits(out_frontMask, 63, 56) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 63, 56) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 63, 56) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 63, 56) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_90 = bits(out_front.bits.data, 63, 56) node _out_T_91 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_92 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_93 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_94 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_89, UInt<56>(0h0)) node out_prepend_5 = cat(recvCompCount, _out_prepend_T_5) node _out_T_95 = or(out_prepend_5, UInt<64>(0h0)) node _out_T_96 = bits(_out_T_95, 63, 0) node _out_rimask_T_11 = bits(out_frontMask, 47, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 47, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 47, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 47, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_97 = bits(out_front.bits.data, 47, 0) node _out_T_98 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_99 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_100 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_101 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_102 = or(io.macAddr, UInt<48>(0h0)) node _out_T_103 = bits(_out_T_102, 47, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 0) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 0) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 0) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 0) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_104 = bits(out_front.bits.data, 1, 0) when out_f_woready_12 : connect intMask, _out_T_104 node _out_T_105 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_106 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_107 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_108 = eq(out_womask_12, UInt<1>(0h0)) node _out_T_109 = or(intMask, UInt<2>(0h0)) node _out_T_110 = bits(_out_T_109, 1, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex_hi = cat(_out_iindex_T_2, _out_iindex_T_1) node out_iindex = cat(out_iindex_hi, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex_hi = cat(_out_oindex_T_2, _out_oindex_T_1) node out_oindex = cat(out_oindex_hi, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node out_backSel_4 = bits(_out_backSel_T, 4, 4) node out_backSel_5 = bits(_out_backSel_T, 5, 5) node out_backSel_6 = bits(_out_backSel_T, 6, 6) node out_backSel_7 = bits(_out_backSel_T, 7, 7) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[2], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_8) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_11 connect out_rivalid[9], _out_rifireMux_T_11 connect out_rivalid[8], _out_rifireMux_T_11 connect out_rivalid[7], _out_rifireMux_T_11 connect out_rivalid[6], _out_rifireMux_T_11 connect out_rivalid[5], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_8, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_10) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[11], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_10, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) wire out_rifireMux_out_4 : UInt<1> node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_12) connect out_rifireMux_out_4, UInt<1>(0h1) connect out_rivalid[12], _out_rifireMux_T_19 node _out_rifireMux_T_20 = eq(_out_T_12, UInt<1>(0h0)) node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) wire out_rifireMux_out_5 : UInt<1> node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, _out_T_2) connect out_rifireMux_out_5, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_23 node _out_rifireMux_T_24 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) wire out_rifireMux_out_6 : UInt<1> node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, _out_T_6) connect out_rifireMux_out_6, UInt<1>(0h1) connect out_rivalid[4], _out_rifireMux_T_27 connect out_rivalid[3], _out_rifireMux_T_27 node _out_rifireMux_T_28 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) wire out_rifireMux_out_7 : UInt<1> node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1)) connect out_rifireMux_out_7, UInt<1>(0h1) node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) node _out_rifireMux_T_34 = geq(out_iindex, UInt<4>(0h8)) wire _out_rifireMux_WIRE : UInt<1>[8] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 node out_rifireMux = mux(_out_rifireMux_T_34, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[2], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_8) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_12 connect out_wivalid[9], _out_wifireMux_T_12 connect out_wivalid[8], _out_wifireMux_T_12 connect out_wivalid[7], _out_wifireMux_T_12 connect out_wivalid[6], _out_wifireMux_T_12 connect out_wivalid[5], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_8, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_10) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[11], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_10, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) wire out_wifireMux_out_4 : UInt<1> node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_12) connect out_wifireMux_out_4, UInt<1>(0h1) connect out_wivalid[12], _out_wifireMux_T_20 node _out_wifireMux_T_21 = eq(_out_T_12, UInt<1>(0h0)) node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) wire out_wifireMux_out_5 : UInt<1> node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, _out_T_2) connect out_wifireMux_out_5, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_24 node _out_wifireMux_T_25 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) wire out_wifireMux_out_6 : UInt<1> node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, _out_T_6) connect out_wifireMux_out_6, UInt<1>(0h1) connect out_wivalid[4], _out_wifireMux_T_28 connect out_wivalid[3], _out_wifireMux_T_28 node _out_wifireMux_T_29 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) wire out_wifireMux_out_7 : UInt<1> node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1)) connect out_wifireMux_out_7, UInt<1>(0h1) node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) node _out_wifireMux_T_35 = geq(out_iindex, UInt<4>(0h8)) wire _out_wifireMux_WIRE : UInt<1>[8] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 node out_wifireMux = mux(_out_wifireMux_T_35, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[2], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_9) node out_rofireMux_out_0 = and(_out_T_65, _out_T_57) node out_rofireMux_out_1_1 = and(_out_rofireMux_T_11, _out_T_57) node out_rofireMux_out_2_1 = and(_out_rofireMux_T_11, _out_T_65) node _out_rofireMux_T_12 = and(_out_rofireMux_T_11, _out_T_65) node out_rofireMux_all = and(_out_rofireMux_T_12, _out_T_57) connect out_rofireMux_out_2, out_rofireMux_out_0 connect out_roready[10], out_rofireMux_all connect out_roready[9], out_rofireMux_all connect out_roready[8], out_rofireMux_all connect out_roready[7], out_rofireMux_all connect out_roready[6], out_rofireMux_out_1_1 connect out_roready[5], out_rofireMux_out_2_1 node _out_rofireMux_T_13 = eq(_out_T_9, UInt<1>(0h0)) node _out_rofireMux_T_14 = or(out_rofireMux_out_2, _out_rofireMux_T_13) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_15 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_16 = and(_out_rofireMux_T_15, _out_T_11) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[11], _out_rofireMux_T_16 node _out_rofireMux_T_17 = eq(_out_T_11, UInt<1>(0h0)) node _out_rofireMux_T_18 = or(out_rofireMux_out_3, _out_rofireMux_T_17) wire out_rofireMux_out_4 : UInt<1> node _out_rofireMux_T_19 = and(_out_rofireMux_T_1, out_backSel_4) node _out_rofireMux_T_20 = and(_out_rofireMux_T_19, _out_T_13) connect out_rofireMux_out_4, UInt<1>(0h1) connect out_roready[12], _out_rofireMux_T_20 node _out_rofireMux_T_21 = eq(_out_T_13, UInt<1>(0h0)) node _out_rofireMux_T_22 = or(out_rofireMux_out_4, _out_rofireMux_T_21) wire out_rofireMux_out_5 : UInt<1> node _out_rofireMux_T_23 = and(_out_rofireMux_T_1, out_backSel_5) node _out_rofireMux_T_24 = and(_out_rofireMux_T_23, _out_T_3) connect out_rofireMux_out_5, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_24 node _out_rofireMux_T_25 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_26 = or(out_rofireMux_out_5, _out_rofireMux_T_25) wire out_rofireMux_out_6 : UInt<1> node _out_rofireMux_T_27 = and(_out_rofireMux_T_1, out_backSel_6) node _out_rofireMux_T_28 = and(_out_rofireMux_T_27, _out_T_7) node out_rofireMux_all_1 = and(_out_rofireMux_T_28, _out_T_42) connect out_rofireMux_out_6, _out_T_42 connect out_roready[4], out_rofireMux_all_1 connect out_roready[3], _out_rofireMux_T_28 node _out_rofireMux_T_29 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_30 = or(out_rofireMux_out_6, _out_rofireMux_T_29) wire out_rofireMux_out_7 : UInt<1> node _out_rofireMux_T_31 = and(_out_rofireMux_T_1, out_backSel_7) node _out_rofireMux_T_32 = and(_out_rofireMux_T_31, UInt<1>(0h1)) connect out_rofireMux_out_7, UInt<1>(0h1) node _out_rofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_34 = or(out_rofireMux_out_7, _out_rofireMux_T_33) node _out_rofireMux_T_35 = geq(out_oindex, UInt<4>(0h8)) wire _out_rofireMux_WIRE : UInt<1>[8] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_14 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_18 connect _out_rofireMux_WIRE[4], _out_rofireMux_T_22 connect _out_rofireMux_WIRE[5], _out_rofireMux_T_26 connect _out_rofireMux_WIRE[6], _out_rofireMux_T_30 connect _out_rofireMux_WIRE[7], _out_rofireMux_T_34 node out_rofireMux = mux(_out_rofireMux_T_35, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) node out_wofireMux_all = and(_out_wofireMux_T_4, _out_T_19) connect out_wofireMux_out, _out_T_19 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) node out_wofireMux_all_1 = and(_out_wofireMux_T_8, _out_T_35) connect out_wofireMux_out_1, _out_T_35 connect out_woready[2], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_9) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_12 connect out_woready[9], _out_wofireMux_T_12 connect out_woready[8], _out_wofireMux_T_12 connect out_woready[7], _out_wofireMux_T_12 connect out_woready[6], _out_wofireMux_T_12 connect out_woready[5], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_9, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_11) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[11], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_11, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) wire out_wofireMux_out_4 : UInt<1> node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_13) connect out_wofireMux_out_4, UInt<1>(0h1) connect out_woready[12], _out_wofireMux_T_20 node _out_wofireMux_T_21 = eq(_out_T_13, UInt<1>(0h0)) node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) wire out_wofireMux_out_5 : UInt<1> node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, _out_T_3) node out_wofireMux_all_2 = and(_out_wofireMux_T_24, _out_T_27) connect out_wofireMux_out_5, _out_T_27 connect out_woready[1], _out_wofireMux_T_24 node _out_wofireMux_T_25 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) wire out_wofireMux_out_6 : UInt<1> node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, _out_T_7) connect out_wofireMux_out_6, UInt<1>(0h1) connect out_woready[4], _out_wofireMux_T_28 connect out_woready[3], _out_wofireMux_T_28 node _out_wofireMux_T_29 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) wire out_wofireMux_out_7 : UInt<1> node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1)) connect out_wofireMux_out_7, UInt<1>(0h1) node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) node _out_wofireMux_T_35 = geq(out_oindex, UInt<4>(0h8)) wire _out_wofireMux_WIRE : UInt<1>[8] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 node out_wofireMux = mux(_out_wofireMux_T_35, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<4>(0h8)) wire _out_out_bits_data_WIRE : UInt<1>[8] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_5 connect _out_out_bits_data_WIRE[2], _out_T_9 connect _out_out_bits_data_WIRE[3], _out_T_11 connect _out_out_bits_data_WIRE[4], _out_T_13 connect _out_out_bits_data_WIRE[5], _out_T_3 connect _out_out_bits_data_WIRE[6], _out_T_7 connect _out_out_bits_data_WIRE[7], UInt<1>(0h1) node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<4>(0h8)) wire _out_out_bits_data_WIRE_1 : UInt<64>[8] connect _out_out_bits_data_WIRE_1[0], _out_T_21 connect _out_out_bits_data_WIRE_1[1], _out_T_37 connect _out_out_bits_data_WIRE_1[2], _out_T_96 connect _out_out_bits_data_WIRE_1[3], _out_T_103 connect _out_out_bits_data_WIRE_1[4], _out_T_110 connect _out_out_bits_data_WIRE_1[5], _out_T_29 connect _out_out_bits_data_WIRE_1[6], _out_T_52 connect _out_out_bits_data_WIRE_1[7], UInt<1>(0h0) node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module IceNicController( // @[NIC.scala:112:7] input clock, // @[NIC.scala:112:7] input reset, // @[NIC.scala:112:7] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_xing_out_sync_1, // @[LazyModuleImp.scala:107:25] input io_send_req_ready, // @[NIC.scala:113:14] output io_send_req_valid, // @[NIC.scala:113:14] output [63:0] io_send_req_bits, // @[NIC.scala:113:14] output io_send_comp_ready, // @[NIC.scala:113:14] input io_send_comp_valid, // @[NIC.scala:113:14] input io_recv_req_ready, // @[NIC.scala:113:14] output io_recv_req_valid, // @[NIC.scala:113:14] output [63:0] io_recv_req_bits, // @[NIC.scala:113:14] output io_recv_comp_ready, // @[NIC.scala:113:14] input io_recv_comp_valid, // @[NIC.scala:113:14] input [15:0] io_recv_comp_bits, // @[NIC.scala:113:14] input [47:0] io_macAddr, // @[NIC.scala:113:14] input io_txcsumReq_ready, // @[NIC.scala:113:14] output io_txcsumReq_valid, // @[NIC.scala:113:14] output io_txcsumReq_bits_check, // @[NIC.scala:113:14] output [15:0] io_txcsumReq_bits_offset, // @[NIC.scala:113:14] output [15:0] io_txcsumReq_bits_start, // @[NIC.scala:113:14] output [15:0] io_txcsumReq_bits_init, // @[NIC.scala:113:14] output io_rxcsumRes_ready, // @[NIC.scala:113:14] input io_rxcsumRes_valid, // @[NIC.scala:113:14] input io_rxcsumRes_bits_correct, // @[NIC.scala:113:14] input io_rxcsumRes_bits_checked, // @[NIC.scala:113:14] output io_csumEnable // @[NIC.scala:113:14] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxcsumResQueue_io_deq_valid; // @[NIC.scala:155:30] wire _txcsumReqQueue_io_enq_ready; // @[NIC.scala:154:30] wire _recvCompQueue_io_enq_ready; // @[NIC.scala:132:29] wire _recvCompQueue_io_deq_valid; // @[NIC.scala:132:29] wire [15:0] _recvCompQueue_io_deq_bits; // @[NIC.scala:132:29] wire _recvReqQueue_io_enq_ready; // @[NIC.scala:127:28] wire _recvReqQueue_io_deq_valid; // @[NIC.scala:127:28] wire _sendReqQueue_io_enq_ready; // @[NIC.scala:124:28] wire _sendReqQueue_io_deq_valid; // @[NIC.scala:124:28] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[NIC.scala:112:7] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[NIC.scala:112:7] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[NIC.scala:112:7] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[NIC.scala:112:7] wire [11:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[NIC.scala:112:7] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[NIC.scala:112:7] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[NIC.scala:112:7] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[NIC.scala:112:7] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[NIC.scala:112:7] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[NIC.scala:112:7] wire io_send_req_ready_0 = io_send_req_ready; // @[NIC.scala:112:7] wire io_send_comp_valid_0 = io_send_comp_valid; // @[NIC.scala:112:7] wire io_recv_req_ready_0 = io_recv_req_ready; // @[NIC.scala:112:7] wire io_recv_comp_valid_0 = io_recv_comp_valid; // @[NIC.scala:112:7] wire [15:0] io_recv_comp_bits_0 = io_recv_comp_bits; // @[NIC.scala:112:7] wire [47:0] io_macAddr_0 = io_macAddr; // @[NIC.scala:112:7] wire io_txcsumReq_ready_0 = io_txcsumReq_ready; // @[NIC.scala:112:7] wire io_rxcsumRes_valid_0 = io_rxcsumRes_valid; // @[NIC.scala:112:7] wire io_rxcsumRes_bits_correct_0 = io_rxcsumRes_bits_correct; // @[NIC.scala:112:7] wire io_rxcsumRes_bits_checked_0 = io_rxcsumRes_bits_checked; // @[NIC.scala:112:7] wire [8:0] out_maskMatch = 9'h1F8; // @[RegisterRouter.scala:87:24] wire [48:0] _out_T_28 = 49'h0; // @[RegisterRouter.scala:87:24] wire [48:0] _out_T_29 = 49'h0; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h1; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_20 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_21 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_36 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_37 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_5 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_7 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[NIC.scala:112:7] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[NIC.scala:112:7] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[NIC.scala:112:7] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[NIC.scala:112:7] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire io_send_comp_bits = 1'h1; // @[NIC.scala:112:7] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire _out_T_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_T_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[NIC.scala:112:7] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[NIC.scala:112:7] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[NIC.scala:112:7] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[NIC.scala:112:7] wire [11:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[NIC.scala:112:7] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[NIC.scala:112:7] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[NIC.scala:112:7] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[NIC.scala:112:7] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[NIC.scala:112:7] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[NIC.scala:112:7] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire intXingOut_sync_1; // @[MixedNode.scala:542:17] wire _io_send_comp_ready_T; // @[NIC.scala:140:39] wire [47:0] _out_T_102 = io_macAddr_0; // @[RegisterRouter.scala:87:24] wire _io_txcsumReq_bits_WIRE_check; // @[NIC.scala:159:59] wire [15:0] _io_txcsumReq_bits_WIRE_offset; // @[NIC.scala:159:59] wire [15:0] _io_txcsumReq_bits_WIRE_start; // @[NIC.scala:159:59] wire [15:0] _io_txcsumReq_bits_WIRE_init; // @[NIC.scala:159:59] wire auto_control_xing_in_a_ready_0; // @[NIC.scala:112:7] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[NIC.scala:112:7] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[NIC.scala:112:7] wire [11:0] auto_control_xing_in_d_bits_source_0; // @[NIC.scala:112:7] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[NIC.scala:112:7] wire auto_control_xing_in_d_valid_0; // @[NIC.scala:112:7] wire auto_int_xing_out_sync_0_0; // @[NIC.scala:112:7] wire auto_int_xing_out_sync_1_0; // @[NIC.scala:112:7] wire io_send_req_valid_0; // @[NIC.scala:112:7] wire [63:0] io_send_req_bits_0; // @[NIC.scala:112:7] wire io_send_comp_ready_0; // @[NIC.scala:112:7] wire io_recv_req_valid_0; // @[NIC.scala:112:7] wire [63:0] io_recv_req_bits_0; // @[NIC.scala:112:7] wire io_recv_comp_ready_0; // @[NIC.scala:112:7] wire io_txcsumReq_bits_check_0; // @[NIC.scala:112:7] wire [15:0] io_txcsumReq_bits_offset_0; // @[NIC.scala:112:7] wire [15:0] io_txcsumReq_bits_start_0; // @[NIC.scala:112:7] wire [15:0] io_txcsumReq_bits_init_0; // @[NIC.scala:112:7] wire io_txcsumReq_valid_0; // @[NIC.scala:112:7] wire io_rxcsumRes_ready_0; // @[NIC.scala:112:7] wire io_csumEnable_0; // @[NIC.scala:112:7] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [11:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [11:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] wire _intnodeOut_0_T_1; // @[NIC.scala:143:40] wire _intnodeOut_1_T_1; // @[NIC.scala:144:53] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[NIC.scala:112:7] wire intXingIn_sync_1; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_1_0 = intXingOut_sync_1; // @[NIC.scala:112:7] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intXingOut_sync_1 = intXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[NIC.scala:112:7] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[NIC.scala:112:7] wire _out_sendCompDown_T; // @[NIC.scala:150:35] wire sendCompDown; // @[NIC.scala:115:30] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire _sendReqCount_T = _sendReqQueue_io_enq_ready & out_f_woready; // @[Decoupled.scala:51:35] wire _sendReqCount_T_1 = io_send_req_ready_0 & _sendReqQueue_io_deq_valid; // @[Decoupled.scala:51:35] reg [6:0] sendReqCount; // @[Counters.scala:34:22] wire _sendReqCount_T_2 = ~_sendReqCount_T_1; // @[Decoupled.scala:51:35] wire _sendReqCount_T_3 = _sendReqCount_T & _sendReqCount_T_2; // @[Decoupled.scala:51:35] wire [7:0] _GEN = {1'h0, sendReqCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _sendReqCount_cnt_T = _GEN + 8'h1; // @[Counters.scala:35:37] wire [6:0] _sendReqCount_cnt_T_1 = _sendReqCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _sendReqCount_T_4 = ~_sendReqCount_T; // @[Decoupled.scala:51:35] wire _sendReqCount_T_5 = _sendReqCount_T_1 & _sendReqCount_T_4; // @[Decoupled.scala:51:35] wire [7:0] _sendReqCount_cnt_T_2 = _GEN - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _sendReqCount_cnt_T_3 = _sendReqCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _recvReqCount_T = _recvReqQueue_io_enq_ready & out_f_woready_2; // @[Decoupled.scala:51:35] wire _recvReqCount_T_1 = io_recv_req_ready_0 & _recvReqQueue_io_deq_valid; // @[Decoupled.scala:51:35] reg [6:0] recvReqCount; // @[Counters.scala:34:22] wire _recvReqCount_T_2 = ~_recvReqCount_T_1; // @[Decoupled.scala:51:35] wire _recvReqCount_T_3 = _recvReqCount_T & _recvReqCount_T_2; // @[Decoupled.scala:51:35] wire [7:0] _GEN_0 = {1'h0, recvReqCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _recvReqCount_cnt_T = _GEN_0 + 8'h1; // @[Counters.scala:35:37] wire [6:0] _recvReqCount_cnt_T_1 = _recvReqCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _recvReqCount_T_4 = ~_recvReqCount_T; // @[Decoupled.scala:51:35] wire _recvReqCount_T_5 = _recvReqCount_T_1 & _recvReqCount_T_4; // @[Decoupled.scala:51:35] wire [7:0] _recvReqCount_cnt_T_2 = _GEN_0 - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _recvReqCount_cnt_T_3 = _recvReqCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire _sendCompCount_T = io_send_comp_ready_0 & io_send_comp_valid_0; // @[Decoupled.scala:51:35] reg [6:0] sendCompCount; // @[Counters.scala:34:22] wire _sendCompCount_T_1 = ~sendCompDown; // @[Counters.scala:35:17] wire _sendCompCount_T_2 = _sendCompCount_T & _sendCompCount_T_1; // @[Decoupled.scala:51:35] wire [7:0] _GEN_1 = {1'h0, sendCompCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _sendCompCount_cnt_T = _GEN_1 + 8'h1; // @[Counters.scala:35:37] wire [6:0] _sendCompCount_cnt_T_1 = _sendCompCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _sendCompCount_T_3 = ~_sendCompCount_T; // @[Decoupled.scala:51:35] wire _sendCompCount_T_4 = sendCompDown & _sendCompCount_T_3; // @[Counters.scala:36:{16,19}] wire [7:0] _sendCompCount_cnt_T_2 = _GEN_1 - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _sendCompCount_cnt_T_3 = _sendCompCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire _recvCompCount_T = _recvCompQueue_io_enq_ready & io_recv_comp_valid_0; // @[Decoupled.scala:51:35] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _recvCompCount_T_1 = out_f_roready_6 & _recvCompQueue_io_deq_valid; // @[Decoupled.scala:51:35] reg [6:0] recvCompCount; // @[Counters.scala:34:22] wire _recvCompCount_T_2 = ~_recvCompCount_T_1; // @[Decoupled.scala:51:35] wire _recvCompCount_T_3 = _recvCompCount_T & _recvCompCount_T_2; // @[Decoupled.scala:51:35] wire [7:0] _GEN_2 = {1'h0, recvCompCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _recvCompCount_cnt_T = _GEN_2 + 8'h1; // @[Counters.scala:35:37] wire [6:0] _recvCompCount_cnt_T_1 = _recvCompCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _recvCompCount_T_4 = ~_recvCompCount_T; // @[Decoupled.scala:51:35] wire _recvCompCount_T_5 = _recvCompCount_T_1 & _recvCompCount_T_4; // @[Decoupled.scala:51:35] wire [7:0] _recvCompCount_cnt_T_2 = _GEN_2 - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _recvCompCount_cnt_T_3 = _recvCompCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire sendCompValid = \|sendCompCount; // @[Counters.scala:34:22] reg [1:0] intMask; // @[NIC.scala:136:24] wire [1:0] _out_T_109 = intMask; // @[RegisterRouter.scala:87:24] assign _io_send_comp_ready_T = ~(sendCompCount[6]); // @[Counters.scala:34:22] assign io_send_comp_ready_0 = _io_send_comp_ready_T; // @[NIC.scala:112:7, :140:39] wire _intnodeOut_0_T = intMask[0]; // @[NIC.scala:136:24, :143:50] assign _intnodeOut_0_T_1 = sendCompValid & _intnodeOut_0_T; // @[NIC.scala:135:37, :143:{40,50}] assign intnodeOut_0 = _intnodeOut_0_T_1; // @[NIC.scala:143:40] wire _intnodeOut_1_T = intMask[1]; // @[NIC.scala:136:24, :144:63] assign _intnodeOut_1_T_1 = _recvCompQueue_io_deq_valid & _intnodeOut_1_T; // @[NIC.scala:132:29, :144:{53,63}] assign intnodeOut_1 = _intnodeOut_1_T_1; // @[NIC.scala:144:53] wire [7:0] _sendReqSpace_T = 8'h40 - _GEN; // @[Counters.scala:35:37] wire [6:0] sendReqSpace = _sendReqSpace_T[6:0]; // @[NIC.scala:146:32] wire [7:0] _recvReqSpace_T = 8'h40 - _GEN_0; // @[Counters.scala:35:37] wire [6:0] recvReqSpace = _recvReqSpace_T[6:0]; // @[NIC.scala:147:32] reg csumEnable; // @[NIC.scala:156:27] assign io_csumEnable_0 = csumEnable; // @[NIC.scala:112:7, :156:27] wire _io_txcsumReq_bits_T_3; // @[NIC.scala:159:59] assign io_txcsumReq_bits_check_0 = _io_txcsumReq_bits_WIRE_check; // @[NIC.scala:112:7, :159:59] wire [15:0] _io_txcsumReq_bits_T_2; // @[NIC.scala:159:59] assign io_txcsumReq_bits_offset_0 = _io_txcsumReq_bits_WIRE_offset; // @[NIC.scala:112:7, :159:59] wire [15:0] _io_txcsumReq_bits_T_1; // @[NIC.scala:159:59] assign io_txcsumReq_bits_start_0 = _io_txcsumReq_bits_WIRE_start; // @[NIC.scala:112:7, :159:59] wire [15:0] _io_txcsumReq_bits_T; // @[NIC.scala:159:59] assign io_txcsumReq_bits_init_0 = _io_txcsumReq_bits_WIRE_init; // @[NIC.scala:112:7, :159:59] wire [48:0] _io_txcsumReq_bits_WIRE_1; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T = _io_txcsumReq_bits_WIRE_1[15:0]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_init = _io_txcsumReq_bits_T; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T_1 = _io_txcsumReq_bits_WIRE_1[31:16]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_start = _io_txcsumReq_bits_T_1; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T_2 = _io_txcsumReq_bits_WIRE_1[47:32]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_offset = _io_txcsumReq_bits_T_2; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T_3 = _io_txcsumReq_bits_WIRE_1[48]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_check = _io_txcsumReq_bits_T_3; // @[NIC.scala:159:59] wire [1:0] _rxcsumResQueue_io_enq_bits_T = {io_rxcsumRes_bits_correct_0, io_rxcsumRes_bits_checked_0}; // @[NIC.scala:112:7, :163:51] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_14 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_30 = out_front_bits_data; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN_3 = out_front_bits_index & 9'h1F8; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN_3; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN_3; // @[RegisterRouter.scala:87:24] wire _GEN_4 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _GEN_5 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_5 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_6 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_9; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_3 = _out_T_11; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_4 = _out_T_13; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28; // @[RegisterRouter.scala:87:24] wire out_rofireMux_all_1; // @[ReduceOthers.scala:47:21] wire out_rofireMux_out_2_1; // @[ReduceOthers.scala:46:45] wire out_rofireMux_out_1_1; // @[ReduceOthers.scala:46:45] wire out_rofireMux_all; // @[ReduceOthers.scala:47:21] wire _out_rofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_2 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_2 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_2 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_2 = out_backMask; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_15 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_19 = _sendReqQueue_io_enq_ready \| _out_T_18; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out = _out_T_19; // @[RegisterRouter.scala:87:24] wire [48:0] _out_rimask_T_1 = out_frontMask[48:0]; // @[RegisterRouter.scala:87:24] wire [48:0] _out_wimask_T_1 = out_frontMask[48:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [48:0] _out_romask_T_1 = out_backMask[48:0]; // @[RegisterRouter.scala:87:24] wire [48:0] _out_womask_T_1 = out_backMask[48:0]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [48:0] _out_T_22 = out_front_bits_data[48:0]; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = _txcsumReqQueue_io_enq_ready \| _out_T_26; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = _out_T_27; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = _recvReqQueue_io_enq_ready \| _out_T_34; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_3 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_3 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_12 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_12 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_3 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_3 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_12 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_12 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_38 = out_front_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_104 = out_front_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_42 = _rxcsumResQueue_io_deq_valid \| _out_T_41; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = _out_T_42; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_44; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_45 = _out_T_44; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = {6'h0, _out_T_45}; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = {csumEnable, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_51 = out_prepend; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign _out_sendCompDown_T = sendCompValid & out_f_roready_5; // @[RegisterRouter.scala:87:24] assign sendCompDown = _out_sendCompDown_T; // @[NIC.scala:115:30, :150:35] wire _out_T_53 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = sendCompValid \| _out_T_56; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_6 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_6 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_6 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_6 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_61 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24] wire _out_T_62 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = _recvCompQueue_io_deq_valid \| _out_T_64; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {_recvCompQueue_io_deq_bits, 16'h1}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = _out_T_67; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_69 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_71 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_72 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [38:0] out_prepend_2 = {sendReqSpace, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_74 = {1'h0, out_prepend_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_75 = _out_T_74; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_75; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_76 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [46:0] out_prepend_3 = {recvReqSpace, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_81 = {1'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_82 = _out_T_81; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_4 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_83 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_85 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [54:0] out_prepend_4 = {sendCompCount, _out_prepend_T_4}; // @[Counters.scala:34:22] wire [55:0] _out_T_88 = {1'h0, out_prepend_4}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_5 = _out_T_89; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_90 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_93 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_94 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [62:0] out_prepend_5 = {recvCompCount, _out_prepend_T_5}; // @[Counters.scala:34:22] wire [63:0] _out_T_95 = {1'h0, out_prepend_5}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_96 = _out_T_95; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_96; // @[MuxLiteral.scala:49:48] wire [47:0] _out_rimask_T_11 = out_frontMask[47:0]; // @[RegisterRouter.scala:87:24] wire [47:0] _out_wimask_T_11 = out_frontMask[47:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire [47:0] _out_romask_T_11 = out_backMask[47:0]; // @[RegisterRouter.scala:87:24] wire [47:0] _out_womask_T_11 = out_backMask[47:0]; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_97 = out_front_bits_data[47:0]; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_103 = _out_T_102; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_105 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_110 = _out_T_109; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex = {out_iindex_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex = {out_oindex_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontSel_T = 8'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35] wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35] wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35] wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35] wire [7:0] _out_backSel_T = 8'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35] wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35] wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35] wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35] wire _GEN_6 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_31 = _out_rifireMux_T_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_32 = _out_wifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _GEN_7 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_0; // @[ReduceOthers.scala:46:45] wire out_rofireMux_out_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_rofireMux_out_0 = _out_T_65 & _out_T_57; // @[ReduceOthers.scala:46:45] assign out_rofireMux_out_2 = out_rofireMux_out_0; // @[ReduceOthers.scala:46:45] assign out_rofireMux_out_1_1 = _out_rofireMux_T_11 & _out_T_57; // @[ReduceOthers.scala:46:45] assign out_roready_6 = out_rofireMux_out_1_1; // @[ReduceOthers.scala:46:45] wire _GEN_8 = _out_rofireMux_T_11 & _out_T_65; // @[ReduceOthers.scala:46:45] assign out_rofireMux_out_2_1 = _GEN_8; // @[ReduceOthers.scala:46:45] wire _out_rofireMux_T_12; // @[ReduceOthers.scala:47:21] assign _out_rofireMux_T_12 = _GEN_8; // @[ReduceOthers.scala:46:45, :47:21] assign out_roready_5 = out_rofireMux_out_2_1; // @[ReduceOthers.scala:46:45] assign out_rofireMux_all = _out_rofireMux_T_12 & _out_T_57; // @[ReduceOthers.scala:47:21] assign out_roready_7 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] assign out_roready_8 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] assign out_roready_9 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] assign out_roready_10 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] wire _out_rofireMux_T_13 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = out_rofireMux_out_2 \| _out_rofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_2 = _out_rofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_T_15 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_16 = _out_rofireMux_T_15 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_20 = _out_rofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_24 = _out_rofireMux_T_23 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_27 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_28 = _out_rofireMux_T_27 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_rofireMux_all_1 = _out_rofireMux_T_28 & _out_T_42; // @[ReduceOthers.scala:47:21] assign out_roready_4 = out_rofireMux_all_1; // @[ReduceOthers.scala:47:21] wire _out_rofireMux_T_29 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_30 = out_rofireMux_out_6 \| _out_rofireMux_T_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_6 = _out_rofireMux_T_30; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_T_31 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire [7:0] _GEN_9 = {{1'h1}, {_out_rofireMux_WIRE_6}, {1'h1}, {1'h1}, {1'h1}, {_out_rofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_rofireMux = _GEN_9[out_oindex]; // @[MuxLiteral.scala:49:10] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_4 & _out_T_19; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = out_wofireMux_out \| _out_wofireMux_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = _out_wofireMux_T_6; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_8 & _out_T_35; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = out_wofireMux_out_1 \| _out_wofireMux_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_1 = _out_wofireMux_T_10; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_2 = _out_wofireMux_T_24 & _out_T_27; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_25 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = out_wofireMux_out_5 \| _out_wofireMux_T_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_5 = _out_wofireMux_T_26; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_32 = _out_wofireMux_T_31; // @[RegisterRouter.scala:87:24] wire [7:0] _GEN_10 = {{1'h1}, {1'h1}, {_out_wofireMux_WIRE_5}, {1'h1}, {1'h1}, {1'h1}, {_out_wofireMux_WIRE_1}, {_out_wofireMux_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_10[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_oready = out_front_bits_read ? out_rofireMux : out_wofireMux; // @[MuxLiteral.scala:49:10] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign _out_front_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [7:0] _GEN_11 = {{1'h1}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_11[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_3 = {16'h0, _out_T_103}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_4 = {62'h0, _out_T_110}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_6 = {55'h0, _out_T_52}; // @[MuxLiteral.scala:49:48] wire [7:0][63:0] _GEN_12 = {{64'h0}, {_out_out_bits_data_WIRE_1_6}, {64'h0}, {_out_out_bits_data_WIRE_1_4}, {_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {64'h0}, {64'h0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_12[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[NIC.scala:112:7] if (reset) begin // @[NIC.scala:112:7] sendReqCount <= 7'h0; // @[Counters.scala:34:22] recvReqCount <= 7'h0; // @[Counters.scala:34:22] sendCompCount <= 7'h0; // @[Counters.scala:34:22] recvCompCount <= 7'h0; // @[Counters.scala:34:22] intMask <= 2'h0; // @[NIC.scala:136:24] csumEnable <= 1'h0; // @[NIC.scala:156:27] end else begin // @[NIC.scala:112:7] if (_sendReqCount_T_5) // @[Counters.scala:36:16] sendReqCount <= _sendReqCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_sendReqCount_T_3) // @[Counters.scala:35:14] sendReqCount <= _sendReqCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (_recvReqCount_T_5) // @[Counters.scala:36:16] recvReqCount <= _recvReqCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_recvReqCount_T_3) // @[Counters.scala:35:14] recvReqCount <= _recvReqCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (_sendCompCount_T_4) // @[Counters.scala:36:16] sendCompCount <= _sendCompCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_sendCompCount_T_2) // @[Counters.scala:35:14] sendCompCount <= _sendCompCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (_recvCompCount_T_5) // @[Counters.scala:36:16] recvCompCount <= _recvCompCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_recvCompCount_T_3) // @[Counters.scala:35:14] recvCompCount <= _recvCompCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] intMask <= _out_T_104; // @[RegisterRouter.scala:87:24] if (out_f_woready_4) // @[RegisterRouter.scala:87:24] csumEnable <= _out_T_46; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x2_1 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_in_1 (intnodeOut_1), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0), .auto_out_sync_1 (intXingIn_sync_1) ); // @[Crossing.scala:29:31] TLMonitor_60 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] HellaQueue sendReqQueue ( // @[NIC.scala:124:28] .clock (clock), .reset (reset), .io_enq_ready (_sendReqQueue_io_enq_ready), .io_enq_valid (out_f_woready), // @[RegisterRouter.scala:87:24] .io_enq_bits (_out_T_14), // @[RegisterRouter.scala:87:24] .io_deq_ready (io_send_req_ready_0), // @[NIC.scala:112:7] .io_deq_valid (_sendReqQueue_io_deq_valid), .io_deq_bits (io_send_req_bits_0) ); // @[NIC.scala:124:28] assign io_send_req_valid_0 = _sendReqQueue_io_deq_valid; // @[NIC.scala:112:7, :124:28] HellaQueue_1 recvReqQueue ( // @[NIC.scala:127:28] .clock (clock), .reset (reset), .io_enq_ready (_recvReqQueue_io_enq_ready), .io_enq_valid (out_f_woready_2), // @[RegisterRouter.scala:87:24] .io_enq_bits (_out_T_30), // @[RegisterRouter.scala:87:24] .io_deq_ready (io_recv_req_ready_0), // @[NIC.scala:112:7] .io_deq_valid (_recvReqQueue_io_deq_valid), .io_deq_bits (io_recv_req_bits_0) ); // @[NIC.scala:127:28] assign io_recv_req_valid_0 = _recvReqQueue_io_deq_valid; // @[NIC.scala:112:7, :127:28] HellaQueue_2 recvCompQueue ( // @[NIC.scala:132:29] .clock (clock), .reset (reset), .io_enq_ready (_recvCompQueue_io_enq_ready), .io_enq_valid (io_recv_comp_valid_0), // @[NIC.scala:112:7] .io_enq_bits (io_recv_comp_bits_0), // @[NIC.scala:112:7] .io_deq_ready (out_f_roready_6), // @[RegisterRouter.scala:87:24] .io_deq_valid (_recvCompQueue_io_deq_valid), .io_deq_bits (_recvCompQueue_io_deq_bits) ); // @[NIC.scala:132:29] assign io_recv_comp_ready_0 = _recvCompQueue_io_enq_ready; // @[NIC.scala:112:7, :132:29] HellaQueue_3 txcsumReqQueue ( // @[NIC.scala:154:30] .clock (clock), .reset (reset), .io_enq_ready (_txcsumReqQueue_io_enq_ready), .io_enq_valid (out_f_woready_1), // @[RegisterRouter.scala:87:24] .io_enq_bits (_out_T_22), // @[RegisterRouter.scala:87:24] .io_deq_ready (io_txcsumReq_ready_0), // @[NIC.scala:112:7] .io_deq_valid (io_txcsumReq_valid_0), .io_deq_bits (_io_txcsumReq_bits_WIRE_1) ); // @[NIC.scala:154:30] HellaQueue_4 rxcsumResQueue ( // @[NIC.scala:155:30] .clock (clock), .reset (reset), .io_enq_ready (io_rxcsumRes_ready_0), .io_enq_valid (io_rxcsumRes_valid_0), // @[NIC.scala:112:7] .io_enq_bits (_rxcsumResQueue_io_enq_bits_T), // @[NIC.scala:163:51] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxcsumResQueue_io_deq_valid), .io_deq_bits (_out_T_44) ); // @[NIC.scala:155:30] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[NIC.scala:112:7] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[NIC.scala:112:7] assign auto_int_xing_out_sync_1 = auto_int_xing_out_sync_1_0; // @[NIC.scala:112:7] assign io_send_req_valid = io_send_req_valid_0; // @[NIC.scala:112:7] assign io_send_req_bits = io_send_req_bits_0; // @[NIC.scala:112:7] assign io_send_comp_ready = io_send_comp_ready_0; // @[NIC.scala:112:7] assign io_recv_req_valid = io_recv_req_valid_0; // @[NIC.scala:112:7] assign io_recv_req_bits = io_recv_req_bits_0; // @[NIC.scala:112:7] assign io_recv_comp_ready = io_recv_comp_ready_0; // @[NIC.scala:112:7] assign io_txcsumReq_valid = io_txcsumReq_valid_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_check = io_txcsumReq_bits_check_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_offset = io_txcsumReq_bits_offset_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_start = io_txcsumReq_bits_start_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_init = io_txcsumReq_bits_init_0; // @[NIC.scala:112:7] assign io_rxcsumRes_ready = io_rxcsumRes_ready_0; // @[NIC.scala:112:7] assign io_csumEnable = io_csumEnable_0; // @[NIC.scala:112:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_DebugInternalBundle : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]}}, flip async : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<1> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_31 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<1> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w21 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset node io_deq_bits_deq_bits_reg_io_d_lo = cat(io.async.mem[0].hrmask[1], io.async.mem[0].hrmask[0]) node io_deq_bits_deq_bits_reg_io_d_hi = cat(io.async.mem[0].hrmask[3], io.async.mem[0].hrmask[2]) node _io_deq_bits_deq_bits_reg_io_d_T = cat(io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo) node io_deq_bits_deq_bits_reg_io_d_lo_1 = cat(io.async.mem[0].hamask[1], io.async.mem[0].hamask[0]) node io_deq_bits_deq_bits_reg_io_d_hi_1 = cat(io.async.mem[0].hamask[3], io.async.mem[0].hamask[2]) node _io_deq_bits_deq_bits_reg_io_d_T_1 = cat(io_deq_bits_deq_bits_reg_io_d_hi_1, io_deq_bits_deq_bits_reg_io_d_lo_1) node io_deq_bits_deq_bits_reg_io_d_lo_hi = cat(io.async.mem[0].hasel, _io_deq_bits_deq_bits_reg_io_d_T_1) node io_deq_bits_deq_bits_reg_io_d_lo_2 = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi, _io_deq_bits_deq_bits_reg_io_d_T) node io_deq_bits_deq_bits_reg_io_d_hi_hi = cat(io.async.mem[0].resumereq, io.async.mem[0].hartsel) node io_deq_bits_deq_bits_reg_io_d_hi_2 = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi, io.async.mem[0].ackhavereset) node _io_deq_bits_deq_bits_reg_io_d_T_2 = cat(io_deq_bits_deq_bits_reg_io_d_hi_2, io_deq_bits_deq_bits_reg_io_d_lo_2) connect io_deq_bits_deq_bits_reg.io.d, _io_deq_bits_deq_bits_reg_io_d_T_2 connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]} wire _io_deq_bits_WIRE_1 : UInt<21> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 0, 0) connect _io_deq_bits_WIRE.hrmask[0], _io_deq_bits_T node _io_deq_bits_T_1 = bits(_io_deq_bits_WIRE_1, 1, 1) connect _io_deq_bits_WIRE.hrmask[1], _io_deq_bits_T_1 node _io_deq_bits_T_2 = bits(_io_deq_bits_WIRE_1, 2, 2) connect _io_deq_bits_WIRE.hrmask[2], _io_deq_bits_T_2 node _io_deq_bits_T_3 = bits(_io_deq_bits_WIRE_1, 3, 3) connect _io_deq_bits_WIRE.hrmask[3], _io_deq_bits_T_3 node _io_deq_bits_T_4 = bits(_io_deq_bits_WIRE_1, 4, 4) connect _io_deq_bits_WIRE.hamask[0], _io_deq_bits_T_4 node _io_deq_bits_T_5 = bits(_io_deq_bits_WIRE_1, 5, 5) connect _io_deq_bits_WIRE.hamask[1], _io_deq_bits_T_5 node _io_deq_bits_T_6 = bits(_io_deq_bits_WIRE_1, 6, 6) connect _io_deq_bits_WIRE.hamask[2], _io_deq_bits_T_6 node _io_deq_bits_T_7 = bits(_io_deq_bits_WIRE_1, 7, 7) connect _io_deq_bits_WIRE.hamask[3], _io_deq_bits_T_7 node _io_deq_bits_T_8 = bits(_io_deq_bits_WIRE_1, 8, 8) connect _io_deq_bits_WIRE.hasel, _io_deq_bits_T_8 node _io_deq_bits_T_9 = bits(_io_deq_bits_WIRE_1, 9, 9) connect _io_deq_bits_WIRE.ackhavereset, _io_deq_bits_T_9 node _io_deq_bits_T_10 = bits(_io_deq_bits_WIRE_1, 19, 10) connect _io_deq_bits_WIRE.hartsel, _io_deq_bits_T_10 node _io_deq_bits_T_11 = bits(_io_deq_bits_WIRE_1, 20, 20) connect _io_deq_bits_WIRE.resumereq, _io_deq_bits_T_11 connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_20 inst sink_valid_1 of AsyncValidSync_21 inst source_extend of AsyncValidSync_22 inst source_valid of AsyncValidSync_23 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1	module AsyncQueueSink_DebugInternalBundle( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] output io_deq_valid, // @[AsyncQueue.scala:139:14] output io_deq_bits_resumereq, // @[AsyncQueue.scala:139:14] output [9:0] io_deq_bits_hartsel, // @[AsyncQueue.scala:139:14] output io_deq_bits_ackhavereset, // @[AsyncQueue.scala:139:14] output io_deq_bits_hasel, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_0, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_1, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_2, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_3, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_0, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_1, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_2, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_3, // @[AsyncQueue.scala:139:14] input io_async_mem_0_resumereq, // @[AsyncQueue.scala:139:14] input [9:0] io_async_mem_0_hartsel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_ackhavereset, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hasel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_1, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_2, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_3, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_1, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_2, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_3, // @[AsyncQueue.scala:139:14] output io_async_ridx, // @[AsyncQueue.scala:139:14] input io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire io_deq_valid_0; // @[AsyncQueue.scala:166:29] wire _source_valid_io_out; // @[AsyncQueue.scala:176:31] wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire [20:0] _io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala:207:25] wire _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire ridx = _source_valid_io_out & ridx_ridx_bin + io_deq_valid_0; // @[AsyncQueue.scala:52:25, :53:{23,43}, :166:29, :176:31] wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg valid_reg; // @[AsyncQueue.scala:165:56] assign io_deq_valid_0 = valid_reg & _source_valid_io_out; // @[AsyncQueue.scala:165:56, :166:29, :176:31] reg ridx_gray; // @[AsyncQueue.scala:168:55] always @(posedge clock or posedge reset) begin // @[AsyncQueue.scala:136:7] if (reset) begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25, :136:7] valid_reg <= 1'h0; // @[AsyncQueue.scala:136:7, :165:56] ridx_gray <= 1'h0; // @[AsyncQueue.scala:136:7, :168:55] end else begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx; // @[AsyncQueue.scala:52:25, :53:23] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] ridx_gray <= ridx; // @[AsyncQueue.scala:53:23, :168:55] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_33 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_46 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_33( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_46 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_39 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_39( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_38 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1294 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = and(_T_1296, _T_1301) node _T_1303 = or(UInt<1>(0h0), _T_1302) node _T_1304 = and(_T_1292, _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_26 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(is_aligned, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1314 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_29 node _T_1318 = eq(io.in.a.bits.mask, mask) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_30 node _T_1322 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1322 : node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<1>(0h1)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h2)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1345 = shr(io.in.a.bits.source, 2) node _T_1346 = eq(_T_1345, UInt<2>(0h3)) node _T_1347 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1362 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1384 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1385 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1386 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1387 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1388 = or(_T_1326, _T_1332) node _T_1389 = or(_T_1388, _T_1338) node _T_1390 = or(_T_1389, _T_1344) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = or(_T_1425, _T_1385) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = and(_T_1325, _T_1428) node _T_1430 = or(UInt<1>(0h0), _T_1429) node _T_1431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(UInt<1>(0h0), _T_1433) node _T_1435 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<13>(0h1000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = and(_T_1434, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = and(_T_1430, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_31 node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(is_aligned, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1452 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_34 node _T_1456 = not(mask) node _T_1457 = and(io.in.a.bits.mask, _T_1456) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_35 node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1462 : node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1465 = and(_T_1463, _T_1464) node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<1>(0h1)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h2)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1485 = shr(io.in.a.bits.source, 2) node _T_1486 = eq(_T_1485, UInt<2>(0h3)) node _T_1487 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1488 = and(_T_1486, _T_1487) node _T_1489 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1497 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1498 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1499 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1500 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1501 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1502 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1521 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1522 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1523 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1524 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1526 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1527 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1528 = or(_T_1466, _T_1472) node _T_1529 = or(_T_1528, _T_1478) node _T_1530 = or(_T_1529, _T_1484) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = or(_T_1562, _T_1522) node _T_1564 = or(_T_1563, _T_1523) node _T_1565 = or(_T_1564, _T_1524) node _T_1566 = or(_T_1565, _T_1525) node _T_1567 = or(_T_1566, _T_1526) node _T_1568 = or(_T_1567, _T_1527) node _T_1569 = and(_T_1465, _T_1568) node _T_1570 = or(UInt<1>(0h0), _T_1569) node _T_1571 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1572 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1573 = cvt(_T_1572) node _T_1574 = and(_T_1573, asSInt(UInt<13>(0h1000))) node _T_1575 = asSInt(_T_1574) node _T_1576 = eq(_T_1575, asSInt(UInt<1>(0h0))) node _T_1577 = and(_T_1571, _T_1576) node _T_1578 = or(UInt<1>(0h0), _T_1577) node _T_1579 = and(_T_1570, _T_1578) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_36 node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(source_ok, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(is_aligned, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1589 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_39 node _T_1593 = eq(io.in.a.bits.mask, mask) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_40 node _T_1597 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1597 : node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<1>(0h1)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h2)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<2>(0h3)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1632 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1633 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1634 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1635 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1636 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1637 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1662 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1663 = or(_T_1601, _T_1607) node _T_1664 = or(_T_1663, _T_1613) node _T_1665 = or(_T_1664, _T_1619) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = or(_T_1697, _T_1657) node _T_1699 = or(_T_1698, _T_1658) node _T_1700 = or(_T_1699, _T_1659) node _T_1701 = or(_T_1700, _T_1660) node _T_1702 = or(_T_1701, _T_1661) node _T_1703 = or(_T_1702, _T_1662) node _T_1704 = and(_T_1600, _T_1703) node _T_1705 = or(UInt<1>(0h0), _T_1704) node _T_1706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1707 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = and(_T_1706, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = and(_T_1705, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_41 node _T_1718 = asUInt(reset) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) when _T_1719 : node _T_1720 = eq(source_ok, UInt<1>(0h0)) when _T_1720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(is_aligned, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1724 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1725 = asUInt(reset) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) when _T_1726 : node _T_1727 = eq(_T_1724, UInt<1>(0h0)) when _T_1727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1724, UInt<1>(0h1), "") : assert_44 node _T_1728 = eq(io.in.a.bits.mask, mask) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_45 node _T_1732 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1732 : node _T_1733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1735 = and(_T_1733, _T_1734) node _T_1736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<1>(0h1)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h2)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<2>(0h3)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1798 = or(_T_1736, _T_1742) node _T_1799 = or(_T_1798, _T_1748) node _T_1800 = or(_T_1799, _T_1754) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = or(_T_1832, _T_1792) node _T_1834 = or(_T_1833, _T_1793) node _T_1835 = or(_T_1834, _T_1794) node _T_1836 = or(_T_1835, _T_1795) node _T_1837 = or(_T_1836, _T_1796) node _T_1838 = or(_T_1837, _T_1797) node _T_1839 = and(_T_1735, _T_1838) node _T_1840 = or(UInt<1>(0h0), _T_1839) node _T_1841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1842 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1843 = cvt(_T_1842) node _T_1844 = and(_T_1843, asSInt(UInt<13>(0h1000))) node _T_1845 = asSInt(_T_1844) node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0))) node _T_1847 = and(_T_1841, _T_1846) node _T_1848 = or(UInt<1>(0h0), _T_1847) node _T_1849 = and(_T_1840, _T_1848) node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(_T_1849, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1849, UInt<1>(0h1), "") : assert_46 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(source_ok, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(is_aligned, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1859 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(_T_1859, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1859, UInt<1>(0h1), "") : assert_49 node _T_1863 = eq(io.in.a.bits.mask, mask) node _T_1864 = asUInt(reset) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) when _T_1865 : node _T_1866 = eq(_T_1863, UInt<1>(0h0)) when _T_1866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1863, UInt<1>(0h1), "") : assert_50 node _T_1867 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(_T_1867, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1867, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1871 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(_T_1871, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1871, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1875 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1875 : node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_1, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1879 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_54 node _T_1883 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_55 node _T_1887 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1888 = asUInt(reset) node _T_1889 = eq(_T_1888, UInt<1>(0h0)) when _T_1889 : node _T_1890 = eq(_T_1887, UInt<1>(0h0)) when _T_1890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1887, UInt<1>(0h1), "") : assert_56 node _T_1891 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1892 = asUInt(reset) node _T_1893 = eq(_T_1892, UInt<1>(0h0)) when _T_1893 : node _T_1894 = eq(_T_1891, UInt<1>(0h0)) when _T_1894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1891, UInt<1>(0h1), "") : assert_57 node _T_1895 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1895 : node _T_1896 = asUInt(reset) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) when _T_1897 : node _T_1898 = eq(source_ok_1, UInt<1>(0h0)) when _T_1898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(sink_ok, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1902 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(_T_1902, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1902, UInt<1>(0h1), "") : assert_60 node _T_1906 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_61 node _T_1910 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1911 = asUInt(reset) node _T_1912 = eq(_T_1911, UInt<1>(0h0)) when _T_1912 : node _T_1913 = eq(_T_1910, UInt<1>(0h0)) when _T_1913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1910, UInt<1>(0h1), "") : assert_62 node _T_1914 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_63 node _T_1918 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1919 = or(UInt<1>(0h0), _T_1918) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_64 node _T_1923 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1923 : node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(source_ok_1, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(sink_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_67 node _T_1934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(_T_1934, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1934, UInt<1>(0h1), "") : assert_68 node _T_1938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_69 node _T_1942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1943 = or(_T_1942, io.in.d.bits.corrupt) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_70 node _T_1947 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_71 node _T_1952 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(source_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1956 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1957 = asUInt(reset) node _T_1958 = eq(_T_1957, UInt<1>(0h0)) when _T_1958 : node _T_1959 = eq(_T_1956, UInt<1>(0h0)) when _T_1959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1956, UInt<1>(0h1), "") : assert_73 node _T_1960 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(_T_1960, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1960, UInt<1>(0h1), "") : assert_74 node _T_1964 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1965 = or(UInt<1>(0h0), _T_1964) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_75 node _T_1969 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1973 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1974 = asUInt(reset) node _T_1975 = eq(_T_1974, UInt<1>(0h0)) when _T_1975 : node _T_1976 = eq(_T_1973, UInt<1>(0h0)) when _T_1976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1973, UInt<1>(0h1), "") : assert_77 node _T_1977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1978 = or(_T_1977, io.in.d.bits.corrupt) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_78 node _T_1982 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1983 = or(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_79 node _T_1987 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1987 : node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(source_ok_1, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1991 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(_T_1991, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1991, UInt<1>(0h1), "") : assert_81 node _T_1995 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_82 node _T_1999 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2000 = or(UInt<1>(0h0), _T_1999) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2004 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2008 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2012 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2016 = eq(a_first, UInt<1>(0h0)) node _T_2017 = and(io.in.a.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.a.bits.opcode, opcode) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_87 node _T_2022 = eq(io.in.a.bits.param, param) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_88 node _T_2026 = eq(io.in.a.bits.size, size) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_89 node _T_2030 = eq(io.in.a.bits.source, source) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_90 node _T_2034 = eq(io.in.a.bits.address, address) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_91 node _T_2038 = and(io.in.a.ready, io.in.a.valid) node _T_2039 = and(_T_2038, a_first) when _T_2039 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2040 = eq(d_first, UInt<1>(0h0)) node _T_2041 = and(io.in.d.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.d.bits.opcode, opcode_1) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_92 node _T_2046 = eq(io.in.d.bits.param, param_1) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_93 node _T_2050 = eq(io.in.d.bits.size, size_1) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_94 node _T_2054 = eq(io.in.d.bits.source, source_1) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_95 node _T_2058 = eq(io.in.d.bits.sink, sink) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_96 node _T_2062 = eq(io.in.d.bits.denied, denied) node _T_2063 = asUInt(reset) node _T_2064 = eq(_T_2063, UInt<1>(0h0)) when _T_2064 : node _T_2065 = eq(_T_2062, UInt<1>(0h0)) when _T_2065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2062, UInt<1>(0h1), "") : assert_97 node _T_2066 = and(io.in.d.ready, io.in.d.valid) node _T_2067 = and(_T_2066, d_first) when _T_2067 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2068 = and(io.in.a.valid, a_first_1) node _T_2069 = and(_T_2068, UInt<1>(0h1)) when _T_2069 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2070 = and(io.in.a.ready, io.in.a.valid) node _T_2071 = and(_T_2070, a_first_1) node _T_2072 = and(_T_2071, UInt<1>(0h1)) when _T_2072 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2073 = dshr(inflight, io.in.a.bits.source) node _T_2074 = bits(_T_2073, 0, 0) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) node _T_2076 = asUInt(reset) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) when _T_2077 : node _T_2078 = eq(_T_2075, UInt<1>(0h0)) when _T_2078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2075, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2079 = and(io.in.d.valid, d_first_1) node _T_2080 = and(_T_2079, UInt<1>(0h1)) node _T_2081 = eq(d_release_ack, UInt<1>(0h0)) node _T_2082 = and(_T_2080, _T_2081) when _T_2082 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2083 = and(io.in.d.ready, io.in.d.valid) node _T_2084 = and(_T_2083, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2088 = and(io.in.d.valid, d_first_1) node _T_2089 = and(_T_2088, UInt<1>(0h1)) node _T_2090 = eq(d_release_ack, UInt<1>(0h0)) node _T_2091 = and(_T_2089, _T_2090) when _T_2091 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2092 = dshr(inflight, io.in.d.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = or(_T_2093, same_cycle_resp) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2098 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2099 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2100 = or(_T_2098, _T_2099) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_100 node _T_2104 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_101 else : node _T_2108 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2109 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2110 = or(_T_2108, _T_2109) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_102 node _T_2114 = eq(io.in.d.bits.size, a_size_lookup) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_103 node _T_2118 = and(io.in.d.valid, d_first_1) node _T_2119 = and(_T_2118, a_first_1) node _T_2120 = and(_T_2119, io.in.a.valid) node _T_2121 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2122 = and(_T_2120, _T_2121) node _T_2123 = eq(d_release_ack, UInt<1>(0h0)) node _T_2124 = and(_T_2122, _T_2123) when _T_2124 : node _T_2125 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2126 = or(_T_2125, io.in.a.ready) node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(_T_2126, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2126, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_108 node _T_2130 = orr(inflight) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) node _T_2132 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2133 = or(_T_2131, _T_2132) node _T_2134 = lt(watchdog, plusarg_reader.out) node _T_2135 = or(_T_2133, _T_2134) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2139 = and(io.in.a.ready, io.in.a.valid) node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = or(_T_2139, _T_2140) when _T_2141 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2142 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2143 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2147 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2148 = and(_T_2147, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2149 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2150 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2151 = and(_T_2149, _T_2150) node _T_2152 = and(_T_2148, _T_2151) when _T_2152 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2153 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2154 = bits(_T_2153, 0, 0) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = asUInt(reset) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) when _T_2157 : node _T_2158 = eq(_T_2155, UInt<1>(0h0)) when _T_2158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2155, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2159 = and(io.in.d.valid, d_first_2) node _T_2160 = and(_T_2159, UInt<1>(0h1)) node _T_2161 = and(_T_2160, d_release_ack_1) when _T_2161 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2162 = and(io.in.d.ready, io.in.d.valid) node _T_2163 = and(_T_2162, d_first_2) node _T_2164 = and(_T_2163, UInt<1>(0h1)) node _T_2165 = and(_T_2164, d_release_ack_1) when _T_2165 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2166 = and(io.in.d.valid, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2169 = dshr(inflight_1, io.in.d.bits.source) node _T_2170 = bits(_T_2169, 0, 0) node _T_2171 = or(_T_2170, same_cycle_resp_1) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2175 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_108 else : node _T_2179 = eq(io.in.d.bits.size, c_size_lookup) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_109 node _T_2183 = and(io.in.d.valid, d_first_2) node _T_2184 = and(_T_2183, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2185 = and(_T_2184, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2186 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = and(_T_2187, d_release_ack_1) node _T_2189 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : node _T_2191 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2192 = or(_T_2191, _WIRE_27.ready) node _T_2193 = asUInt(reset) node _T_2194 = eq(_T_2193, UInt<1>(0h0)) when _T_2194 : node _T_2195 = eq(_T_2192, UInt<1>(0h0)) when _T_2195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2192, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_109 node _T_2196 = orr(inflight_1) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) node _T_2198 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2199 = or(_T_2197, _T_2198) node _T_2200 = lt(watchdog_1, plusarg_reader_1.out) node _T_2201 = or(_T_2199, _T_2200) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2205 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2206 = and(io.in.d.ready, io.in.d.valid) node _T_2207 = or(_T_2205, _T_2206) when _T_2207 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_38( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_2 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node sAdjustedExp = add(io.in.sExp, asSInt(UInt<12>(0h900))) node _adjustedSig_T = bits(io.in.sig, 53, 28) node _adjustedSig_T_1 = bits(io.in.sig, 27, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(sAdjustedExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, UInt<1>(0h0)) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(sAdjustedExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(UInt<1>(0h0), _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(UInt<1>(0h0), _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_2( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [53:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [53:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [13:0] sAdjustedExp = {io_in_sExp_0[12], io_in_sExp_0} - 14'h700; // @[RoundAnyRawFNToRecFN.scala:48:5, :110:24] wire [25:0] _adjustedSig_T = io_in_sig_0[53:28]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [27:0] _adjustedSig_T_1 = io_in_sig_0[27:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = \|_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = sAdjustedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:110:24, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = _roundMask_T_73; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {{12{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:110:24, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [7:0] _common_overflow_T = sRoundedExp[14:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 8'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 15'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] wire [5:0] _common_underflow_T = sAdjustedExp[13:8]; // @[RoundAnyRawFNToRecFN.scala:110:24, :220:49] wire _common_underflow_T_1 = $signed(_common_underflow_T) < 6'sh1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:221:{30,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:223:39, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_12 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock inst q of Queue3_EgressFlit_12 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0hd), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_25 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_26 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0ha), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h19), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<6>(0h7), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<6>(0h13), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<6>(0h4), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_32 = or(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_33 = or(_q_io_enq_bits_ingress_id_T_32, _q_io_enq_bits_ingress_id_T_26) node _q_io_enq_bits_ingress_id_T_34 = or(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_27) node _q_io_enq_bits_ingress_id_T_35 = or(_q_io_enq_bits_ingress_id_T_34, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_35, _q_io_enq_bits_ingress_id_T_29) node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_30) node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_31) wire _q_io_enq_bits_ingress_id_WIRE : UInt<6> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_38 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow	module EgressUnit_12( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e11_s53_3 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e11_s53_3 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e11_s53_3 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<107>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<107>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_6 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFNPipe_l2_e11_s53_3( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [64:0] io_a, // @[FPU.scala:638:16] input [64:0] io_b, // @[FPU.scala:638:16] input [64:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [64:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [64:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [64:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [64:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [105:0] _mulAddResult_T = {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [106:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [12:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [55:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 \| roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e11_s53_3 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e11_s53_3 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e11_s53_6 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PhitDemux_p32_f32_n5 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}[5]} regreset beat : UInt<1>, clock, reset, UInt<1>(0h0) reg channel_vec : UInt<32>[1], clock node channel = bits(channel_vec[0], 2, 0) node _io_in_ready_T = lt(beat, UInt<1>(0h1)) wire _io_in_ready_WIRE : UInt<1>[5] connect _io_in_ready_WIRE[0], io.out[0].ready connect _io_in_ready_WIRE[1], io.out[1].ready connect _io_in_ready_WIRE[2], io.out[2].ready connect _io_in_ready_WIRE[3], io.out[3].ready connect _io_in_ready_WIRE[4], io.out[4].ready node _io_in_ready_T_1 = or(_io_in_ready_T, _io_in_ready_WIRE[channel]) connect io.in.ready, _io_in_ready_T_1 node _io_out_0_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_0_valid_T_1 = and(io.in.valid, _io_out_0_valid_T) node _io_out_0_valid_T_2 = eq(channel, UInt<1>(0h0)) node _io_out_0_valid_T_3 = and(_io_out_0_valid_T_1, _io_out_0_valid_T_2) connect io.out[0].valid, _io_out_0_valid_T_3 connect io.out[0].bits.phit, io.in.bits.phit node _io_out_1_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_1_valid_T_1 = and(io.in.valid, _io_out_1_valid_T) node _io_out_1_valid_T_2 = eq(channel, UInt<1>(0h1)) node _io_out_1_valid_T_3 = and(_io_out_1_valid_T_1, _io_out_1_valid_T_2) connect io.out[1].valid, _io_out_1_valid_T_3 connect io.out[1].bits.phit, io.in.bits.phit node _io_out_2_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_2_valid_T_1 = and(io.in.valid, _io_out_2_valid_T) node _io_out_2_valid_T_2 = eq(channel, UInt<2>(0h2)) node _io_out_2_valid_T_3 = and(_io_out_2_valid_T_1, _io_out_2_valid_T_2) connect io.out[2].valid, _io_out_2_valid_T_3 connect io.out[2].bits.phit, io.in.bits.phit node _io_out_3_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_3_valid_T_1 = and(io.in.valid, _io_out_3_valid_T) node _io_out_3_valid_T_2 = eq(channel, UInt<2>(0h3)) node _io_out_3_valid_T_3 = and(_io_out_3_valid_T_1, _io_out_3_valid_T_2) connect io.out[3].valid, _io_out_3_valid_T_3 connect io.out[3].bits.phit, io.in.bits.phit node _io_out_4_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_4_valid_T_1 = and(io.in.valid, _io_out_4_valid_T) node _io_out_4_valid_T_2 = eq(channel, UInt<3>(0h4)) node _io_out_4_valid_T_3 = and(_io_out_4_valid_T_1, _io_out_4_valid_T_2) connect io.out[4].valid, _io_out_4_valid_T_3 connect io.out[4].bits.phit, io.in.bits.phit node _T = and(io.in.ready, io.in.valid) when _T : node _beat_T = eq(beat, UInt<1>(0h1)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = lt(beat, UInt<1>(0h1)) when _T_1 : connect channel_vec[0], io.in.bits.phit	module PhitDemux_p32_f32_n5( // @[Serdes.scala:183:7] input clock, // @[Serdes.scala:183:7] input reset, // @[Serdes.scala:183:7] output io_in_ready, // @[Serdes.scala:185:14] input io_in_valid, // @[Serdes.scala:185:14] input [31:0] io_in_bits_phit, // @[Serdes.scala:185:14] input io_out_0_ready, // @[Serdes.scala:185:14] output io_out_0_valid, // @[Serdes.scala:185:14] output [31:0] io_out_0_bits_phit, // @[Serdes.scala:185:14] input io_out_1_ready, // @[Serdes.scala:185:14] output io_out_1_valid, // @[Serdes.scala:185:14] output [31:0] io_out_1_bits_phit, // @[Serdes.scala:185:14] input io_out_2_ready, // @[Serdes.scala:185:14] output io_out_2_valid, // @[Serdes.scala:185:14] output [31:0] io_out_2_bits_phit, // @[Serdes.scala:185:14] input io_out_3_ready, // @[Serdes.scala:185:14] output io_out_3_valid, // @[Serdes.scala:185:14] output [31:0] io_out_3_bits_phit, // @[Serdes.scala:185:14] input io_out_4_ready, // @[Serdes.scala:185:14] output io_out_4_valid, // @[Serdes.scala:185:14] output [31:0] io_out_4_bits_phit // @[Serdes.scala:185:14] ); reg beat; // @[Serdes.scala:196:23] reg [31:0] channel_vec_0; // @[Serdes.scala:197:26] wire [7:0] _GEN = {{io_out_0_ready}, {io_out_0_ready}, {io_out_0_ready}, {io_out_4_ready}, {io_out_3_ready}, {io_out_2_ready}, {io_out_1_ready}, {io_out_0_ready}}; // @[Serdes.scala:201:41] wire io_in_ready_0 = ~beat \| _GEN[channel_vec_0[2:0]]; // @[Serdes.scala:196:23, :197:26, :198:37, :201:{25,41}] wire _GEN_0 = io_in_ready_0 & io_in_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Serdes.scala:183:7] if (reset) // @[Serdes.scala:183:7] beat <= 1'h0; // @[Serdes.scala:183:7, :196:23] else if (_GEN_0) // @[Decoupled.scala:51:35] beat <= ~beat & beat - 1'h1; // @[Serdes.scala:196:23, :208:{18,51}] if (_GEN_0 & ~beat) // @[Decoupled.scala:51:35] channel_vec_0 <= io_in_bits_phit; // @[Serdes.scala:197:26] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_3 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [16] wire _valids_WIRE : UInt<1>[16] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) connect _valids_WIRE[15], UInt<1>(0h0) regreset valids : UInt<1>[16], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = and(valids[3], _valids_3_T_2) node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0)) node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5) connect valids[3], _valids_3_T_6 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = and(valids[4], _valids_4_T_2) node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0)) node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5) connect valids[4], _valids_4_T_6 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = and(valids[5], _valids_5_T_2) node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0)) node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5) connect valids[5], _valids_5_T_6 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = and(valids[6], _valids_6_T_2) node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0)) node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5) connect valids[6], _valids_6_T_6 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = and(valids[7], _valids_7_T_2) node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0)) node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5) connect valids[7], _valids_7_T_6 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = and(valids[8], _valids_8_T_2) node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0)) node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5) connect valids[8], _valids_8_T_6 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = and(valids[9], _valids_9_T_2) node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0)) node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5) connect valids[9], _valids_9_T_6 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = and(valids[10], _valids_10_T_2) node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0)) node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5) connect valids[10], _valids_10_T_6 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = and(valids[11], _valids_11_T_2) node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0)) node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5) connect valids[11], _valids_11_T_6 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = and(valids[12], _valids_12_T_2) node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0)) node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5) connect valids[12], _valids_12_T_6 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = and(valids[13], _valids_13_T_2) node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0)) node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5) connect valids[13], _valids_13_T_6 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = and(valids[14], _valids_14_T_2) node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0)) node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5) connect valids[14], _valids_14_T_6 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask) node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0)) node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0)) node _valids_15_T_3 = and(valids[15], _valids_15_T_2) node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq) node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0)) node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5) connect valids[15], _valids_15_T_6 when valids[15] : node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T) connect uops[15].br_mask, _uops_15_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0hf)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = cat(_io_count_T, ptr_diff) connect io.count, _io_count_T_1	module BranchKillableQueue_3( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [39:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [7:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [39:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_is_br, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14] input io_brupdate_b2_uop_taken, // @[util.scala:453:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14] input io_brupdate_b2_uop_exception, // @[util.scala:453:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14] input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14] input io_brupdate_b2_valid, // @[util.scala:453:14] input io_brupdate_b2_mispredict, // @[util.scala:453:14] input io_brupdate_b2_taken, // @[util.scala:453:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14] input io_flush, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [140:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7] wire io_flush_0 = io_flush; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _io_enq_ready_T; // @[util.scala:504:19] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [39:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [15:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [3:0] out_uop_br_tag; // @[util.scala:506:17] wire [4:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [6:0] out_uop_rob_idx; // @[util.scala:506:17] wire [4:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [4:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [4:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [39:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [19:0] out_old_meta_tag; // @[util.scala:506:17] wire [7:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] reg valids_1; // @[util.scala:465:24] reg valids_2; // @[util.scala:465:24] reg valids_3; // @[util.scala:465:24] reg valids_4; // @[util.scala:465:24] reg valids_5; // @[util.scala:465:24] reg valids_6; // @[util.scala:465:24] reg valids_7; // @[util.scala:465:24] reg valids_8; // @[util.scala:465:24] reg valids_9; // @[util.scala:465:24] reg valids_10; // @[util.scala:465:24] reg valids_11; // @[util.scala:465:24] reg valids_12; // @[util.scala:465:24] reg valids_13; // @[util.scala:465:24] reg valids_14; // @[util.scala:465:24] reg valids_15; // @[util.scala:465:24] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [39:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [15:0] uops_0_br_mask; // @[util.scala:466:20] reg [3:0] uops_0_br_tag; // @[util.scala:466:20] reg [4:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [6:0] uops_0_rob_idx; // @[util.scala:466:20] reg [4:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [4:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [39:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [15:0] uops_1_br_mask; // @[util.scala:466:20] reg [3:0] uops_1_br_tag; // @[util.scala:466:20] reg [4:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [6:0] uops_1_rob_idx; // @[util.scala:466:20] reg [4:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [4:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [39:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [15:0] uops_2_br_mask; // @[util.scala:466:20] reg [3:0] uops_2_br_tag; // @[util.scala:466:20] reg [4:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [6:0] uops_2_rob_idx; // @[util.scala:466:20] reg [4:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [4:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [39:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [15:0] uops_3_br_mask; // @[util.scala:466:20] reg [3:0] uops_3_br_tag; // @[util.scala:466:20] reg [4:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [6:0] uops_3_rob_idx; // @[util.scala:466:20] reg [4:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [4:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [39:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [15:0] uops_4_br_mask; // @[util.scala:466:20] reg [3:0] uops_4_br_tag; // @[util.scala:466:20] reg [4:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [6:0] uops_4_rob_idx; // @[util.scala:466:20] reg [4:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [4:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [39:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [15:0] uops_5_br_mask; // @[util.scala:466:20] reg [3:0] uops_5_br_tag; // @[util.scala:466:20] reg [4:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [6:0] uops_5_rob_idx; // @[util.scala:466:20] reg [4:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [4:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [39:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [15:0] uops_6_br_mask; // @[util.scala:466:20] reg [3:0] uops_6_br_tag; // @[util.scala:466:20] reg [4:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [6:0] uops_6_rob_idx; // @[util.scala:466:20] reg [4:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [4:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [39:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [15:0] uops_7_br_mask; // @[util.scala:466:20] reg [3:0] uops_7_br_tag; // @[util.scala:466:20] reg [4:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [6:0] uops_7_rob_idx; // @[util.scala:466:20] reg [4:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [4:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [39:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [15:0] uops_8_br_mask; // @[util.scala:466:20] reg [3:0] uops_8_br_tag; // @[util.scala:466:20] reg [4:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [6:0] uops_8_rob_idx; // @[util.scala:466:20] reg [4:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [4:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [39:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [15:0] uops_9_br_mask; // @[util.scala:466:20] reg [3:0] uops_9_br_tag; // @[util.scala:466:20] reg [4:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [6:0] uops_9_rob_idx; // @[util.scala:466:20] reg [4:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [4:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [39:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [15:0] uops_10_br_mask; // @[util.scala:466:20] reg [3:0] uops_10_br_tag; // @[util.scala:466:20] reg [4:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [6:0] uops_10_rob_idx; // @[util.scala:466:20] reg [4:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [4:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [39:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [15:0] uops_11_br_mask; // @[util.scala:466:20] reg [3:0] uops_11_br_tag; // @[util.scala:466:20] reg [4:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [6:0] uops_11_rob_idx; // @[util.scala:466:20] reg [4:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [4:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [39:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [15:0] uops_12_br_mask; // @[util.scala:466:20] reg [3:0] uops_12_br_tag; // @[util.scala:466:20] reg [4:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [6:0] uops_12_rob_idx; // @[util.scala:466:20] reg [4:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [4:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [39:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [15:0] uops_13_br_mask; // @[util.scala:466:20] reg [3:0] uops_13_br_tag; // @[util.scala:466:20] reg [4:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [6:0] uops_13_rob_idx; // @[util.scala:466:20] reg [4:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [4:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [39:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [15:0] uops_14_br_mask; // @[util.scala:466:20] reg [3:0] uops_14_br_tag; // @[util.scala:466:20] reg [4:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [6:0] uops_14_rob_idx; // @[util.scala:466:20] reg [4:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [4:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [39:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [15:0] uops_15_br_mask; // @[util.scala:466:20] reg [3:0] uops_15_br_tag; // @[util.scala:466:20] reg [4:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [6:0] uops_15_rob_idx; // @[util.scala:466:20] reg [4:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [4:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 \| _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_0_T_1 = \|_valids_0_T; // @[util.scala:118:{51,59}] wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32] wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_0_T_4 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}] wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_1_T_1 = \|_valids_1_T; // @[util.scala:118:{51,59}] wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32] wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_1_T_4 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}] wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_2_T_1 = \|_valids_2_T; // @[util.scala:118:{51,59}] wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32] wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_2_T_4 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}] wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_3_T_1 = \|_valids_3_T; // @[util.scala:118:{51,59}] wire _valids_3_T_2 = ~_valids_3_T_1; // @[util.scala:118:59, :481:32] wire _valids_3_T_3 = valids_3 & _valids_3_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_3_T_4 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_3_T_5 = ~_valids_3_T_4; // @[util.scala:481:{72,83}] wire _valids_3_T_6 = _valids_3_T_3 & _valids_3_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_4_T_1 = \|_valids_4_T; // @[util.scala:118:{51,59}] wire _valids_4_T_2 = ~_valids_4_T_1; // @[util.scala:118:59, :481:32] wire _valids_4_T_3 = valids_4 & _valids_4_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_4_T_4 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_4_T_5 = ~_valids_4_T_4; // @[util.scala:481:{72,83}] wire _valids_4_T_6 = _valids_4_T_3 & _valids_4_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_5_T_1 = \|_valids_5_T; // @[util.scala:118:{51,59}] wire _valids_5_T_2 = ~_valids_5_T_1; // @[util.scala:118:59, :481:32] wire _valids_5_T_3 = valids_5 & _valids_5_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_5_T_4 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_5_T_5 = ~_valids_5_T_4; // @[util.scala:481:{72,83}] wire _valids_5_T_6 = _valids_5_T_3 & _valids_5_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_6_T_1 = \|_valids_6_T; // @[util.scala:118:{51,59}] wire _valids_6_T_2 = ~_valids_6_T_1; // @[util.scala:118:59, :481:32] wire _valids_6_T_3 = valids_6 & _valids_6_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_6_T_4 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_6_T_5 = ~_valids_6_T_4; // @[util.scala:481:{72,83}] wire _valids_6_T_6 = _valids_6_T_3 & _valids_6_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_7_T_1 = \|_valids_7_T; // @[util.scala:118:{51,59}] wire _valids_7_T_2 = ~_valids_7_T_1; // @[util.scala:118:59, :481:32] wire _valids_7_T_3 = valids_7 & _valids_7_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_7_T_4 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_7_T_5 = ~_valids_7_T_4; // @[util.scala:481:{72,83}] wire _valids_7_T_6 = _valids_7_T_3 & _valids_7_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_8_T_1 = \|_valids_8_T; // @[util.scala:118:{51,59}] wire _valids_8_T_2 = ~_valids_8_T_1; // @[util.scala:118:59, :481:32] wire _valids_8_T_3 = valids_8 & _valids_8_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_8_T_4 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_8_T_5 = ~_valids_8_T_4; // @[util.scala:481:{72,83}] wire _valids_8_T_6 = _valids_8_T_3 & _valids_8_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_9_T_1 = \|_valids_9_T; // @[util.scala:118:{51,59}] wire _valids_9_T_2 = ~_valids_9_T_1; // @[util.scala:118:59, :481:32] wire _valids_9_T_3 = valids_9 & _valids_9_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_9_T_4 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_9_T_5 = ~_valids_9_T_4; // @[util.scala:481:{72,83}] wire _valids_9_T_6 = _valids_9_T_3 & _valids_9_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_10_T_1 = \|_valids_10_T; // @[util.scala:118:{51,59}] wire _valids_10_T_2 = ~_valids_10_T_1; // @[util.scala:118:59, :481:32] wire _valids_10_T_3 = valids_10 & _valids_10_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_10_T_4 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_10_T_5 = ~_valids_10_T_4; // @[util.scala:481:{72,83}] wire _valids_10_T_6 = _valids_10_T_3 & _valids_10_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_11_T_1 = \|_valids_11_T; // @[util.scala:118:{51,59}] wire _valids_11_T_2 = ~_valids_11_T_1; // @[util.scala:118:59, :481:32] wire _valids_11_T_3 = valids_11 & _valids_11_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_11_T_4 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_11_T_5 = ~_valids_11_T_4; // @[util.scala:481:{72,83}] wire _valids_11_T_6 = _valids_11_T_3 & _valids_11_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_12_T_1 = \|_valids_12_T; // @[util.scala:118:{51,59}] wire _valids_12_T_2 = ~_valids_12_T_1; // @[util.scala:118:59, :481:32] wire _valids_12_T_3 = valids_12 & _valids_12_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_12_T_4 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_12_T_5 = ~_valids_12_T_4; // @[util.scala:481:{72,83}] wire _valids_12_T_6 = _valids_12_T_3 & _valids_12_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_13_T_1 = \|_valids_13_T; // @[util.scala:118:{51,59}] wire _valids_13_T_2 = ~_valids_13_T_1; // @[util.scala:118:59, :481:32] wire _valids_13_T_3 = valids_13 & _valids_13_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_13_T_4 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_13_T_5 = ~_valids_13_T_4; // @[util.scala:481:{72,83}] wire _valids_13_T_6 = _valids_13_T_3 & _valids_13_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_14_T_1 = \|_valids_14_T; // @[util.scala:118:{51,59}] wire _valids_14_T_2 = ~_valids_14_T_1; // @[util.scala:118:59, :481:32] wire _valids_14_T_3 = valids_14 & _valids_14_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_14_T_4 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_14_T_5 = ~_valids_14_T_4; // @[util.scala:481:{72,83}] wire _valids_14_T_6 = _valids_14_T_3 & _valids_14_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_15_T = io_brupdate_b1_mispredict_mask_0 & uops_15_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_15_T_1 = \|_valids_15_T; // @[util.scala:118:{51,59}] wire _valids_15_T_2 = ~_valids_15_T_1; // @[util.scala:118:59, :481:32] wire _valids_15_T_3 = valids_15 & _valids_15_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_15_T_4 = io_flush_0 & uops_15_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_15_T_5 = ~_valids_15_T_4; // @[util.scala:481:{72,83}] wire _valids_15_T_6 = _valids_15_T_3 & _valids_15_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_15_br_mask_T_1 = uops_15_br_mask & _uops_15_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0] out_uop_br_mask; // @[util.scala:506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][39:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][15:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire [15:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17] wire _io_deq_valid_T_3 = \|_io_deq_valid_T_2; // @[util.scala:118:{51,59}] wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68] wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}] wire _io_deq_valid_T_6 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :509:122] wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] wire [15:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 \| _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 \| _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 \| _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 \| _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 \| _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 \| _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 \| _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 \| _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 \| _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 \| _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 \| _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 \| _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 \| _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 \| _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 \| _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 \| _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x141 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_135 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} wire _in_flight_WIRE : UInt<1>[10] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) connect _in_flight_WIRE[8], UInt<1>(0h0) connect _in_flight_WIRE[9], UInt<1>(0h0) regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = or(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_21, UInt<1>(0h1), "") : assert_4 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_26 = or(_T_25, UInt<1>(0h0)) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_26, UInt<1>(0h1), "") : assert_5 node _T_30 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_31 = or(_T_30, UInt<1>(0h0)) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_31, UInt<1>(0h1), "") : assert_6 node _T_35 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_36 = or(_T_35, UInt<1>(0h0)) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_36, UInt<1>(0h1), "") : assert_7 node _T_40 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_41 = or(_T_40, UInt<1>(0h0)) node _T_42 = asUInt(reset) node _T_43 = eq(_T_42, UInt<1>(0h0)) when _T_43 : node _T_44 = eq(_T_41, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_41, UInt<1>(0h1), "") : assert_8 node _T_45 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_46 = or(_T_45, UInt<1>(0h0)) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9 assert(clock, _T_46, UInt<1>(0h1), "") : assert_9 node _T_50 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3)) node _T_71 = and(_T_69, _T_70) node _T_72 = or(_T_57, _T_64) node _T_73 = or(_T_72, _T_71) node _T_74 = or(_T_50, _T_73) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10 assert(clock, _T_74, UInt<1>(0h1), "") : assert_10	module NoCMonitor_135( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 4'h3; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 4'h4; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 4'h5; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 4'h7; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 4'h8; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_88 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_88( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_107 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_124 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_107( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_124 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = and(_T_11, _T_24) node _T_105 = and(_T_104, _T_37) node _T_106 = and(_T_105, _T_50) node _T_107 = and(_T_106, _T_63) node _T_108 = and(_T_107, _T_71) node _T_109 = and(_T_108, _T_79) node _T_110 = and(_T_109, _T_87) node _T_111 = and(_T_110, _T_95) node _T_112 = and(_T_111, _T_103) node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(_T_112, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_112, UInt<1>(0h1), "") : assert_1 node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_116 : node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_4) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_127 = shr(io.in.a.bits.source, 2) node _T_128 = eq(_T_127, UInt<1>(0h1)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_5) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_132 = and(_T_130, _T_131) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_133 = shr(io.in.a.bits.source, 2) node _T_134 = eq(_T_133, UInt<2>(0h2)) node _T_135 = leq(UInt<1>(0h0), uncommonBits_6) node _T_136 = and(_T_134, _T_135) node _T_137 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<2>(0h3)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_7) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_120, _T_126) node _T_151 = or(_T_150, _T_132) node _T_152 = or(_T_151, _T_138) node _T_153 = or(_T_152, _T_144) node _T_154 = or(_T_153, _T_145) node _T_155 = or(_T_154, _T_146) node _T_156 = or(_T_155, _T_147) node _T_157 = or(_T_156, _T_148) node _T_158 = or(_T_157, _T_149) node _T_159 = and(_T_119, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<14>(0h2000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<11>(0h400))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<9>(0h100))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_178 = cvt(_T_177) node _T_179 = and(_T_178, asSInt(UInt<13>(0h1000))) node _T_180 = asSInt(_T_179) node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0))) node _T_182 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<17>(0h10000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_188 = cvt(_T_187) node _T_189 = and(_T_188, asSInt(UInt<18>(0h2f000))) node _T_190 = asSInt(_T_189) node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0))) node _T_192 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<17>(0h10000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<13>(0h1000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<27>(0h4000000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<13>(0h1000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = or(_T_166, _T_171) node _T_213 = or(_T_212, _T_176) node _T_214 = or(_T_213, _T_181) node _T_215 = or(_T_214, _T_186) node _T_216 = or(_T_215, _T_191) node _T_217 = or(_T_216, _T_196) node _T_218 = or(_T_217, _T_201) node _T_219 = or(_T_218, _T_206) node _T_220 = or(_T_219, _T_211) node _T_221 = and(_T_161, _T_220) node _T_222 = or(UInt<1>(0h0), _T_221) node _T_223 = and(_T_160, _T_222) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_223, UInt<1>(0h1), "") : assert_2 node _T_227 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_228 = shr(io.in.a.bits.source, 2) node _T_229 = eq(_T_228, UInt<1>(0h0)) node _T_230 = leq(UInt<1>(0h0), uncommonBits_8) node _T_231 = and(_T_229, _T_230) node _T_232 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_233 = and(_T_231, _T_232) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_234 = shr(io.in.a.bits.source, 2) node _T_235 = eq(_T_234, UInt<1>(0h1)) node _T_236 = leq(UInt<1>(0h0), uncommonBits_9) node _T_237 = and(_T_235, _T_236) node _T_238 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_240 = shr(io.in.a.bits.source, 2) node _T_241 = eq(_T_240, UInt<2>(0h2)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_10) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_245 = and(_T_243, _T_244) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_246 = shr(io.in.a.bits.source, 2) node _T_247 = eq(_T_246, UInt<2>(0h3)) node _T_248 = leq(UInt<1>(0h0), uncommonBits_11) node _T_249 = and(_T_247, _T_248) node _T_250 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_253 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_227 connect _WIRE[1], _T_233 connect _WIRE[2], _T_239 connect _WIRE[3], _T_245 connect _WIRE[4], _T_251 connect _WIRE[5], _T_252 connect _WIRE[6], _T_253 connect _WIRE[7], _T_254 connect _WIRE[8], _T_255 connect _WIRE[9], _T_256 node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_258 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_259 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_260 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_261 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_262 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_264 = mux(_WIRE[6], _T_257, UInt<1>(0h0)) node _T_265 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_266 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_267 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_268 = or(_T_258, _T_259) node _T_269 = or(_T_268, _T_260) node _T_270 = or(_T_269, _T_261) node _T_271 = or(_T_270, _T_262) node _T_272 = or(_T_271, _T_263) node _T_273 = or(_T_272, _T_264) node _T_274 = or(_T_273, _T_265) node _T_275 = or(_T_274, _T_266) node _T_276 = or(_T_275, _T_267) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_276 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<11>(0h400))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<9>(0h100))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<13>(0h1000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<18>(0h2f000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<13>(0h1000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<27>(0h4000000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = or(_T_285, _T_290) node _T_332 = or(_T_331, _T_295) node _T_333 = or(_T_332, _T_300) node _T_334 = or(_T_333, _T_305) node _T_335 = or(_T_334, _T_310) node _T_336 = or(_T_335, _T_315) node _T_337 = or(_T_336, _T_320) node _T_338 = or(_T_337, _T_325) node _T_339 = or(_T_338, _T_330) node _T_340 = and(_T_280, _T_339) node _T_341 = or(UInt<1>(0h0), _T_340) node _T_342 = and(_WIRE_1, _T_341) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_342, UInt<1>(0h1), "") : assert_3 node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(source_ok, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_349 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_349, UInt<1>(0h1), "") : assert_5 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(is_aligned, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_356 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_356, UInt<1>(0h1), "") : assert_7 node _T_360 = not(io.in.a.bits.mask) node _T_361 = eq(_T_360, UInt<1>(0h0)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_361, UInt<1>(0h1), "") : assert_8 node _T_365 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_365, UInt<1>(0h1), "") : assert_9 node _T_369 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_369 : node _T_370 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_371 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_374 = shr(io.in.a.bits.source, 2) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_12) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_379 = and(_T_377, _T_378) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_380 = shr(io.in.a.bits.source, 2) node _T_381 = eq(_T_380, UInt<1>(0h1)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_13) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_386 = shr(io.in.a.bits.source, 2) node _T_387 = eq(_T_386, UInt<2>(0h2)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_14) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_392 = shr(io.in.a.bits.source, 2) node _T_393 = eq(_T_392, UInt<2>(0h3)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_15) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_397 = and(_T_395, _T_396) node _T_398 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_401 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_402 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_403 = or(_T_373, _T_379) node _T_404 = or(_T_403, _T_385) node _T_405 = or(_T_404, _T_391) node _T_406 = or(_T_405, _T_397) node _T_407 = or(_T_406, _T_398) node _T_408 = or(_T_407, _T_399) node _T_409 = or(_T_408, _T_400) node _T_410 = or(_T_409, _T_401) node _T_411 = or(_T_410, _T_402) node _T_412 = and(_T_372, _T_411) node _T_413 = or(UInt<1>(0h0), _T_412) node _T_414 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_415 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<14>(0h2000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<11>(0h400))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_426 = cvt(_T_425) node _T_427 = and(_T_426, asSInt(UInt<9>(0h100))) node _T_428 = asSInt(_T_427) node _T_429 = eq(_T_428, asSInt(UInt<1>(0h0))) node _T_430 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<13>(0h1000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<17>(0h10000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_441 = cvt(_T_440) node _T_442 = and(_T_441, asSInt(UInt<18>(0h2f000))) node _T_443 = asSInt(_T_442) node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0))) node _T_445 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_446 = cvt(_T_445) node _T_447 = and(_T_446, asSInt(UInt<17>(0h10000))) node _T_448 = asSInt(_T_447) node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0))) node _T_450 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_451 = cvt(_T_450) node _T_452 = and(_T_451, asSInt(UInt<13>(0h1000))) node _T_453 = asSInt(_T_452) node _T_454 = eq(_T_453, asSInt(UInt<1>(0h0))) node _T_455 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<27>(0h4000000))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<13>(0h1000))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = or(_T_419, _T_424) node _T_466 = or(_T_465, _T_429) node _T_467 = or(_T_466, _T_434) node _T_468 = or(_T_467, _T_439) node _T_469 = or(_T_468, _T_444) node _T_470 = or(_T_469, _T_449) node _T_471 = or(_T_470, _T_454) node _T_472 = or(_T_471, _T_459) node _T_473 = or(_T_472, _T_464) node _T_474 = and(_T_414, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = and(_T_413, _T_475) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_476, UInt<1>(0h1), "") : assert_10 node _T_480 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_481 = shr(io.in.a.bits.source, 2) node _T_482 = eq(_T_481, UInt<1>(0h0)) node _T_483 = leq(UInt<1>(0h0), uncommonBits_16) node _T_484 = and(_T_482, _T_483) node _T_485 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_486 = and(_T_484, _T_485) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_487 = shr(io.in.a.bits.source, 2) node _T_488 = eq(_T_487, UInt<1>(0h1)) node _T_489 = leq(UInt<1>(0h0), uncommonBits_17) node _T_490 = and(_T_488, _T_489) node _T_491 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_492 = and(_T_490, _T_491) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_493 = shr(io.in.a.bits.source, 2) node _T_494 = eq(_T_493, UInt<2>(0h2)) node _T_495 = leq(UInt<1>(0h0), uncommonBits_18) node _T_496 = and(_T_494, _T_495) node _T_497 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_498 = and(_T_496, _T_497) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_499 = shr(io.in.a.bits.source, 2) node _T_500 = eq(_T_499, UInt<2>(0h3)) node _T_501 = leq(UInt<1>(0h0), uncommonBits_19) node _T_502 = and(_T_500, _T_501) node _T_503 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_504 = and(_T_502, _T_503) node _T_505 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_506 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_507 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_509 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_480 connect _WIRE_2[1], _T_486 connect _WIRE_2[2], _T_492 connect _WIRE_2[3], _T_498 connect _WIRE_2[4], _T_504 connect _WIRE_2[5], _T_505 connect _WIRE_2[6], _T_506 connect _WIRE_2[7], _T_507 connect _WIRE_2[8], _T_508 connect _WIRE_2[9], _T_509 node _T_510 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_511 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_512 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_513 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_515 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_516 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_517 = mux(_WIRE_2[6], _T_510, UInt<1>(0h0)) node _T_518 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_520 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_521 = or(_T_511, _T_512) node _T_522 = or(_T_521, _T_513) node _T_523 = or(_T_522, _T_514) node _T_524 = or(_T_523, _T_515) node _T_525 = or(_T_524, _T_516) node _T_526 = or(_T_525, _T_517) node _T_527 = or(_T_526, _T_518) node _T_528 = or(_T_527, _T_519) node _T_529 = or(_T_528, _T_520) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_529 node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_532 = and(_T_530, _T_531) node _T_533 = or(UInt<1>(0h0), _T_532) node _T_534 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<14>(0h2000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<11>(0h400))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<9>(0h100))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<13>(0h1000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<17>(0h10000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<18>(0h2f000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<13>(0h1000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<27>(0h4000000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = or(_T_538, _T_543) node _T_585 = or(_T_584, _T_548) node _T_586 = or(_T_585, _T_553) node _T_587 = or(_T_586, _T_558) node _T_588 = or(_T_587, _T_563) node _T_589 = or(_T_588, _T_568) node _T_590 = or(_T_589, _T_573) node _T_591 = or(_T_590, _T_578) node _T_592 = or(_T_591, _T_583) node _T_593 = and(_T_533, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_WIRE_3, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_595, UInt<1>(0h1), "") : assert_11 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_602 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_602, UInt<1>(0h1), "") : assert_13 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(is_aligned, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_609 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_610 = asUInt(reset) node _T_611 = eq(_T_610, UInt<1>(0h0)) when _T_611 : node _T_612 = eq(_T_609, UInt<1>(0h0)) when _T_612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_609, UInt<1>(0h1), "") : assert_15 node _T_613 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_613, UInt<1>(0h1), "") : assert_16 node _T_617 = not(io.in.a.bits.mask) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_618, UInt<1>(0h1), "") : assert_17 node _T_622 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_622, UInt<1>(0h1), "") : assert_18 node _T_626 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_626 : node _T_627 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_628 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_629 = and(_T_627, _T_628) node _T_630 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_631 = shr(io.in.a.bits.source, 2) node _T_632 = eq(_T_631, UInt<1>(0h0)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_20) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<1>(0h1)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_21) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<2>(0h2)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_22) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_649 = shr(io.in.a.bits.source, 2) node _T_650 = eq(_T_649, UInt<2>(0h3)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_23) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_656 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_657 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_658 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_659 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_660 = or(_T_630, _T_636) node _T_661 = or(_T_660, _T_642) node _T_662 = or(_T_661, _T_648) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_655) node _T_665 = or(_T_664, _T_656) node _T_666 = or(_T_665, _T_657) node _T_667 = or(_T_666, _T_658) node _T_668 = or(_T_667, _T_659) node _T_669 = and(_T_629, _T_668) node _T_670 = or(UInt<1>(0h0), _T_669) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_670, UInt<1>(0h1), "") : assert_19 node _T_674 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_675 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_676 = and(_T_674, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = and(_T_677, _T_682) node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_686 = and(_T_684, _T_685) node _T_687 = or(UInt<1>(0h0), _T_686) node _T_688 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<14>(0h2000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<11>(0h400))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<9>(0h100))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<17>(0h10000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<27>(0h4000000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = or(_T_692, _T_697) node _T_734 = or(_T_733, _T_702) node _T_735 = or(_T_734, _T_707) node _T_736 = or(_T_735, _T_712) node _T_737 = or(_T_736, _T_717) node _T_738 = or(_T_737, _T_722) node _T_739 = or(_T_738, _T_727) node _T_740 = or(_T_739, _T_732) node _T_741 = and(_T_687, _T_740) node _T_742 = or(UInt<1>(0h0), _T_683) node _T_743 = or(_T_742, _T_741) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_743, UInt<1>(0h1), "") : assert_20 node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(source_ok, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(is_aligned, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_753 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_754 = asUInt(reset) node _T_755 = eq(_T_754, UInt<1>(0h0)) when _T_755 : node _T_756 = eq(_T_753, UInt<1>(0h0)) when _T_756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_753, UInt<1>(0h1), "") : assert_23 node _T_757 = eq(io.in.a.bits.mask, mask) node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(_T_757, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_757, UInt<1>(0h1), "") : assert_24 node _T_761 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_761, UInt<1>(0h1), "") : assert_25 node _T_765 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<1>(0h0)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_24) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<1>(0h1)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_25) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<2>(0h2)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_26) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<2>(0h3)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_27) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_795 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_798 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_799 = or(_T_769, _T_775) node _T_800 = or(_T_799, _T_781) node _T_801 = or(_T_800, _T_787) node _T_802 = or(_T_801, _T_793) node _T_803 = or(_T_802, _T_794) node _T_804 = or(_T_803, _T_795) node _T_805 = or(_T_804, _T_796) node _T_806 = or(_T_805, _T_797) node _T_807 = or(_T_806, _T_798) node _T_808 = and(_T_768, _T_807) node _T_809 = or(UInt<1>(0h0), _T_808) node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_811 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_812 = and(_T_810, _T_811) node _T_813 = or(UInt<1>(0h0), _T_812) node _T_814 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_815 = cvt(_T_814) node _T_816 = and(_T_815, asSInt(UInt<13>(0h1000))) node _T_817 = asSInt(_T_816) node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0))) node _T_819 = and(_T_813, _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<14>(0h2000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<11>(0h400))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<9>(0h100))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<18>(0h2f000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<27>(0h4000000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<13>(0h1000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_828, _T_833) node _T_865 = or(_T_864, _T_838) node _T_866 = or(_T_865, _T_843) node _T_867 = or(_T_866, _T_848) node _T_868 = or(_T_867, _T_853) node _T_869 = or(_T_868, _T_858) node _T_870 = or(_T_869, _T_863) node _T_871 = and(_T_823, _T_870) node _T_872 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_873 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<17>(0h10000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = and(_T_872, _T_877) node _T_879 = or(UInt<1>(0h0), _T_819) node _T_880 = or(_T_879, _T_871) node _T_881 = or(_T_880, _T_878) node _T_882 = and(_T_809, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_882, UInt<1>(0h1), "") : assert_26 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_892 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_892, UInt<1>(0h1), "") : assert_29 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_896, UInt<1>(0h1), "") : assert_30 node _T_900 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_905 = shr(io.in.a.bits.source, 2) node _T_906 = eq(_T_905, UInt<1>(0h0)) node _T_907 = leq(UInt<1>(0h0), uncommonBits_28) node _T_908 = and(_T_906, _T_907) node _T_909 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_910 = and(_T_908, _T_909) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_911 = shr(io.in.a.bits.source, 2) node _T_912 = eq(_T_911, UInt<1>(0h1)) node _T_913 = leq(UInt<1>(0h0), uncommonBits_29) node _T_914 = and(_T_912, _T_913) node _T_915 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_916 = and(_T_914, _T_915) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_917 = shr(io.in.a.bits.source, 2) node _T_918 = eq(_T_917, UInt<2>(0h2)) node _T_919 = leq(UInt<1>(0h0), uncommonBits_30) node _T_920 = and(_T_918, _T_919) node _T_921 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_922 = and(_T_920, _T_921) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_923 = shr(io.in.a.bits.source, 2) node _T_924 = eq(_T_923, UInt<2>(0h3)) node _T_925 = leq(UInt<1>(0h0), uncommonBits_31) node _T_926 = and(_T_924, _T_925) node _T_927 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_928 = and(_T_926, _T_927) node _T_929 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_930 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_931 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_932 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_933 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_934 = or(_T_904, _T_910) node _T_935 = or(_T_934, _T_916) node _T_936 = or(_T_935, _T_922) node _T_937 = or(_T_936, _T_928) node _T_938 = or(_T_937, _T_929) node _T_939 = or(_T_938, _T_930) node _T_940 = or(_T_939, _T_931) node _T_941 = or(_T_940, _T_932) node _T_942 = or(_T_941, _T_933) node _T_943 = and(_T_903, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_947 = and(_T_945, _T_946) node _T_948 = or(UInt<1>(0h0), _T_947) node _T_949 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_950 = cvt(_T_949) node _T_951 = and(_T_950, asSInt(UInt<13>(0h1000))) node _T_952 = asSInt(_T_951) node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0))) node _T_954 = and(_T_948, _T_953) node _T_955 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_956 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_957 = and(_T_955, _T_956) node _T_958 = or(UInt<1>(0h0), _T_957) node _T_959 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_960 = cvt(_T_959) node _T_961 = and(_T_960, asSInt(UInt<14>(0h2000))) node _T_962 = asSInt(_T_961) node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0))) node _T_964 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_965 = cvt(_T_964) node _T_966 = and(_T_965, asSInt(UInt<11>(0h400))) node _T_967 = asSInt(_T_966) node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0))) node _T_969 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_970 = cvt(_T_969) node _T_971 = and(_T_970, asSInt(UInt<9>(0h100))) node _T_972 = asSInt(_T_971) node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0))) node _T_974 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_975 = cvt(_T_974) node _T_976 = and(_T_975, asSInt(UInt<18>(0h2f000))) node _T_977 = asSInt(_T_976) node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0))) node _T_979 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<17>(0h10000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_985 = cvt(_T_984) node _T_986 = and(_T_985, asSInt(UInt<13>(0h1000))) node _T_987 = asSInt(_T_986) node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0))) node _T_989 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<27>(0h4000000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<13>(0h1000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = or(_T_963, _T_968) node _T_1000 = or(_T_999, _T_973) node _T_1001 = or(_T_1000, _T_978) node _T_1002 = or(_T_1001, _T_983) node _T_1003 = or(_T_1002, _T_988) node _T_1004 = or(_T_1003, _T_993) node _T_1005 = or(_T_1004, _T_998) node _T_1006 = and(_T_958, _T_1005) node _T_1007 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1008 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<17>(0h10000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = and(_T_1007, _T_1012) node _T_1014 = or(UInt<1>(0h0), _T_954) node _T_1015 = or(_T_1014, _T_1006) node _T_1016 = or(_T_1015, _T_1013) node _T_1017 = and(_T_944, _T_1016) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_31 node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(source_ok, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1027 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_34 node _T_1031 = not(mask) node _T_1032 = and(io.in.a.bits.mask, _T_1031) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_35 node _T_1037 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1039 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1042 = shr(io.in.a.bits.source, 2) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) node _T_1044 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1045 = and(_T_1043, _T_1044) node _T_1046 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1047 = and(_T_1045, _T_1046) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1048 = shr(io.in.a.bits.source, 2) node _T_1049 = eq(_T_1048, UInt<1>(0h1)) node _T_1050 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1053 = and(_T_1051, _T_1052) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<2>(0h2)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<2>(0h3)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _T_1066 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1071 = or(_T_1041, _T_1047) node _T_1072 = or(_T_1071, _T_1053) node _T_1073 = or(_T_1072, _T_1059) node _T_1074 = or(_T_1073, _T_1065) node _T_1075 = or(_T_1074, _T_1066) node _T_1076 = or(_T_1075, _T_1067) node _T_1077 = or(_T_1076, _T_1068) node _T_1078 = or(_T_1077, _T_1069) node _T_1079 = or(_T_1078, _T_1070) node _T_1080 = and(_T_1040, _T_1079) node _T_1081 = or(UInt<1>(0h0), _T_1080) node _T_1082 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1083 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<14>(0h2000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_1092 = cvt(_T_1091) node _T_1093 = and(_T_1092, asSInt(UInt<11>(0h400))) node _T_1094 = asSInt(_T_1093) node _T_1095 = eq(_T_1094, asSInt(UInt<1>(0h0))) node _T_1096 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_1097 = cvt(_T_1096) node _T_1098 = and(_T_1097, asSInt(UInt<9>(0h100))) node _T_1099 = asSInt(_T_1098) node _T_1100 = eq(_T_1099, asSInt(UInt<1>(0h0))) node _T_1101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1102 = cvt(_T_1101) node _T_1103 = and(_T_1102, asSInt(UInt<13>(0h1000))) node _T_1104 = asSInt(_T_1103) node _T_1105 = eq(_T_1104, asSInt(UInt<1>(0h0))) node _T_1106 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<18>(0h2f000))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1112 = cvt(_T_1111) node _T_1113 = and(_T_1112, asSInt(UInt<17>(0h10000))) node _T_1114 = asSInt(_T_1113) node _T_1115 = eq(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1117 = cvt(_T_1116) node _T_1118 = and(_T_1117, asSInt(UInt<13>(0h1000))) node _T_1119 = asSInt(_T_1118) node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0))) node _T_1121 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<27>(0h4000000))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1127 = cvt(_T_1126) node _T_1128 = and(_T_1127, asSInt(UInt<13>(0h1000))) node _T_1129 = asSInt(_T_1128) node _T_1130 = eq(_T_1129, asSInt(UInt<1>(0h0))) node _T_1131 = or(_T_1090, _T_1095) node _T_1132 = or(_T_1131, _T_1100) node _T_1133 = or(_T_1132, _T_1105) node _T_1134 = or(_T_1133, _T_1110) node _T_1135 = or(_T_1134, _T_1115) node _T_1136 = or(_T_1135, _T_1120) node _T_1137 = or(_T_1136, _T_1125) node _T_1138 = or(_T_1137, _T_1130) node _T_1139 = and(_T_1085, _T_1138) node _T_1140 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1141 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<17>(0h10000))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = and(_T_1140, _T_1145) node _T_1147 = or(UInt<1>(0h0), _T_1139) node _T_1148 = or(_T_1147, _T_1146) node _T_1149 = and(_T_1081, _T_1148) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_36 node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(source_ok, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(is_aligned, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1159 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_39 node _T_1163 = eq(io.in.a.bits.mask, mask) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_40 node _T_1167 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1167 : node _T_1168 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1169 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1170 = and(_T_1168, _T_1169) node _T_1171 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1172 = shr(io.in.a.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1178 = shr(io.in.a.bits.source, 2) node _T_1179 = eq(_T_1178, UInt<1>(0h1)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1184 = shr(io.in.a.bits.source, 2) node _T_1185 = eq(_T_1184, UInt<2>(0h2)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1190 = shr(io.in.a.bits.source, 2) node _T_1191 = eq(_T_1190, UInt<2>(0h3)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1200 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1201 = or(_T_1171, _T_1177) node _T_1202 = or(_T_1201, _T_1183) node _T_1203 = or(_T_1202, _T_1189) node _T_1204 = or(_T_1203, _T_1195) node _T_1205 = or(_T_1204, _T_1196) node _T_1206 = or(_T_1205, _T_1197) node _T_1207 = or(_T_1206, _T_1198) node _T_1208 = or(_T_1207, _T_1199) node _T_1209 = or(_T_1208, _T_1200) node _T_1210 = and(_T_1170, _T_1209) node _T_1211 = or(UInt<1>(0h0), _T_1210) node _T_1212 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1213 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = or(UInt<1>(0h0), _T_1214) node _T_1216 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1217 = cvt(_T_1216) node _T_1218 = and(_T_1217, asSInt(UInt<14>(0h2000))) node _T_1219 = asSInt(_T_1218) node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_1222 = cvt(_T_1221) node _T_1223 = and(_T_1222, asSInt(UInt<11>(0h400))) node _T_1224 = asSInt(_T_1223) node _T_1225 = eq(_T_1224, asSInt(UInt<1>(0h0))) node _T_1226 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_1227 = cvt(_T_1226) node _T_1228 = and(_T_1227, asSInt(UInt<9>(0h100))) node _T_1229 = asSInt(_T_1228) node _T_1230 = eq(_T_1229, asSInt(UInt<1>(0h0))) node _T_1231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1232 = cvt(_T_1231) node _T_1233 = and(_T_1232, asSInt(UInt<13>(0h1000))) node _T_1234 = asSInt(_T_1233) node _T_1235 = eq(_T_1234, asSInt(UInt<1>(0h0))) node _T_1236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1237 = cvt(_T_1236) node _T_1238 = and(_T_1237, asSInt(UInt<18>(0h2f000))) node _T_1239 = asSInt(_T_1238) node _T_1240 = eq(_T_1239, asSInt(UInt<1>(0h0))) node _T_1241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1242 = cvt(_T_1241) node _T_1243 = and(_T_1242, asSInt(UInt<17>(0h10000))) node _T_1244 = asSInt(_T_1243) node _T_1245 = eq(_T_1244, asSInt(UInt<1>(0h0))) node _T_1246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1247 = cvt(_T_1246) node _T_1248 = and(_T_1247, asSInt(UInt<13>(0h1000))) node _T_1249 = asSInt(_T_1248) node _T_1250 = eq(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1252 = cvt(_T_1251) node _T_1253 = and(_T_1252, asSInt(UInt<27>(0h4000000))) node _T_1254 = asSInt(_T_1253) node _T_1255 = eq(_T_1254, asSInt(UInt<1>(0h0))) node _T_1256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1257 = cvt(_T_1256) node _T_1258 = and(_T_1257, asSInt(UInt<13>(0h1000))) node _T_1259 = asSInt(_T_1258) node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = or(_T_1220, _T_1225) node _T_1262 = or(_T_1261, _T_1230) node _T_1263 = or(_T_1262, _T_1235) node _T_1264 = or(_T_1263, _T_1240) node _T_1265 = or(_T_1264, _T_1245) node _T_1266 = or(_T_1265, _T_1250) node _T_1267 = or(_T_1266, _T_1255) node _T_1268 = or(_T_1267, _T_1260) node _T_1269 = and(_T_1215, _T_1268) node _T_1270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1271 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1272 = cvt(_T_1271) node _T_1273 = and(_T_1272, asSInt(UInt<17>(0h10000))) node _T_1274 = asSInt(_T_1273) node _T_1275 = eq(_T_1274, asSInt(UInt<1>(0h0))) node _T_1276 = and(_T_1270, _T_1275) node _T_1277 = or(UInt<1>(0h0), _T_1269) node _T_1278 = or(_T_1277, _T_1276) node _T_1279 = and(_T_1211, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_41 node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(source_ok, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(is_aligned, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1289 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_44 node _T_1293 = eq(io.in.a.bits.mask, mask) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_45 node _T_1297 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1297 : node _T_1298 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1299 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1300 = and(_T_1298, _T_1299) node _T_1301 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1302 = shr(io.in.a.bits.source, 2) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1307 = and(_T_1305, _T_1306) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1308 = shr(io.in.a.bits.source, 2) node _T_1309 = eq(_T_1308, UInt<1>(0h1)) node _T_1310 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1313 = and(_T_1311, _T_1312) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1314 = shr(io.in.a.bits.source, 2) node _T_1315 = eq(_T_1314, UInt<2>(0h2)) node _T_1316 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1317 = and(_T_1315, _T_1316) node _T_1318 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1319 = and(_T_1317, _T_1318) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1320 = shr(io.in.a.bits.source, 2) node _T_1321 = eq(_T_1320, UInt<2>(0h3)) node _T_1322 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_1327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1330 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1331 = or(_T_1301, _T_1307) node _T_1332 = or(_T_1331, _T_1313) node _T_1333 = or(_T_1332, _T_1319) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = or(_T_1334, _T_1326) node _T_1336 = or(_T_1335, _T_1327) node _T_1337 = or(_T_1336, _T_1328) node _T_1338 = or(_T_1337, _T_1329) node _T_1339 = or(_T_1338, _T_1330) node _T_1340 = and(_T_1300, _T_1339) node _T_1341 = or(UInt<1>(0h0), _T_1340) node _T_1342 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1343 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1344 = and(_T_1342, _T_1343) node _T_1345 = or(UInt<1>(0h0), _T_1344) node _T_1346 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1347 = cvt(_T_1346) node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000))) node _T_1349 = asSInt(_T_1348) node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0))) node _T_1351 = and(_T_1345, _T_1350) node _T_1352 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1353 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1354 = cvt(_T_1353) node _T_1355 = and(_T_1354, asSInt(UInt<14>(0h2000))) node _T_1356 = asSInt(_T_1355) node _T_1357 = eq(_T_1356, asSInt(UInt<1>(0h0))) node _T_1358 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_1359 = cvt(_T_1358) node _T_1360 = and(_T_1359, asSInt(UInt<11>(0h400))) node _T_1361 = asSInt(_T_1360) node _T_1362 = eq(_T_1361, asSInt(UInt<1>(0h0))) node _T_1363 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_1364 = cvt(_T_1363) node _T_1365 = and(_T_1364, asSInt(UInt<9>(0h100))) node _T_1366 = asSInt(_T_1365) node _T_1367 = eq(_T_1366, asSInt(UInt<1>(0h0))) node _T_1368 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1369 = cvt(_T_1368) node _T_1370 = and(_T_1369, asSInt(UInt<17>(0h10000))) node _T_1371 = asSInt(_T_1370) node _T_1372 = eq(_T_1371, asSInt(UInt<1>(0h0))) node _T_1373 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1374 = cvt(_T_1373) node _T_1375 = and(_T_1374, asSInt(UInt<18>(0h2f000))) node _T_1376 = asSInt(_T_1375) node _T_1377 = eq(_T_1376, asSInt(UInt<1>(0h0))) node _T_1378 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1379 = cvt(_T_1378) node _T_1380 = and(_T_1379, asSInt(UInt<17>(0h10000))) node _T_1381 = asSInt(_T_1380) node _T_1382 = eq(_T_1381, asSInt(UInt<1>(0h0))) node _T_1383 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1384 = cvt(_T_1383) node _T_1385 = and(_T_1384, asSInt(UInt<13>(0h1000))) node _T_1386 = asSInt(_T_1385) node _T_1387 = eq(_T_1386, asSInt(UInt<1>(0h0))) node _T_1388 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1389 = cvt(_T_1388) node _T_1390 = and(_T_1389, asSInt(UInt<27>(0h4000000))) node _T_1391 = asSInt(_T_1390) node _T_1392 = eq(_T_1391, asSInt(UInt<1>(0h0))) node _T_1393 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1394 = cvt(_T_1393) node _T_1395 = and(_T_1394, asSInt(UInt<13>(0h1000))) node _T_1396 = asSInt(_T_1395) node _T_1397 = eq(_T_1396, asSInt(UInt<1>(0h0))) node _T_1398 = or(_T_1357, _T_1362) node _T_1399 = or(_T_1398, _T_1367) node _T_1400 = or(_T_1399, _T_1372) node _T_1401 = or(_T_1400, _T_1377) node _T_1402 = or(_T_1401, _T_1382) node _T_1403 = or(_T_1402, _T_1387) node _T_1404 = or(_T_1403, _T_1392) node _T_1405 = or(_T_1404, _T_1397) node _T_1406 = and(_T_1352, _T_1405) node _T_1407 = or(UInt<1>(0h0), _T_1351) node _T_1408 = or(_T_1407, _T_1406) node _T_1409 = and(_T_1341, _T_1408) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_46 node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(source_ok, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(is_aligned, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1419 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(_T_1419, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1419, UInt<1>(0h1), "") : assert_49 node _T_1423 = eq(io.in.a.bits.mask, mask) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_50 node _T_1427 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1431 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_52 node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_38 connect _source_ok_WIRE_1[1], _source_ok_T_44 connect _source_ok_WIRE_1[2], _source_ok_T_50 connect _source_ok_WIRE_1[3], _source_ok_T_56 connect _source_ok_WIRE_1[4], _source_ok_T_62 connect _source_ok_WIRE_1[5], _source_ok_T_63 connect _source_ok_WIRE_1[6], _source_ok_T_64 connect _source_ok_WIRE_1[7], _source_ok_T_65 connect _source_ok_WIRE_1[8], _source_ok_T_66 connect _source_ok_WIRE_1[9], _source_ok_T_67 node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1435 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1435 : node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(source_ok_1, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1439 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_54 node _T_1443 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_55 node _T_1447 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_56 node _T_1451 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_57 node _T_1455 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1455 : node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(source_ok_1, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(sink_ok, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1462 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_60 node _T_1466 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_61 node _T_1470 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_62 node _T_1474 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_63 node _T_1478 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1479 = or(UInt<1>(0h1), _T_1478) node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(_T_1479, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1479, UInt<1>(0h1), "") : assert_64 node _T_1483 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1483 : node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(source_ok_1, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(sink_ok, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1490 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(_T_1490, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1490, UInt<1>(0h1), "") : assert_67 node _T_1494 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_68 node _T_1498 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_69 node _T_1502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1503 = or(_T_1502, io.in.d.bits.corrupt) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_70 node _T_1507 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1508 = or(UInt<1>(0h1), _T_1507) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_71 node _T_1512 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1512 : node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(source_ok_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1516 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_73 node _T_1520 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_74 node _T_1524 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1525 = or(UInt<1>(0h1), _T_1524) node _T_1526 = asUInt(reset) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) when _T_1527 : node _T_1528 = eq(_T_1525, UInt<1>(0h0)) when _T_1528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1525, UInt<1>(0h1), "") : assert_75 node _T_1529 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1529 : node _T_1530 = asUInt(reset) node _T_1531 = eq(_T_1530, UInt<1>(0h0)) when _T_1531 : node _T_1532 = eq(source_ok_1, UInt<1>(0h0)) when _T_1532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1533 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_77 node _T_1537 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1538 = or(_T_1537, io.in.d.bits.corrupt) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_78 node _T_1542 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1543 = or(UInt<1>(0h1), _T_1542) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_79 node _T_1547 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1547 : node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(source_ok_1, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1551 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_81 node _T_1555 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_82 node _T_1559 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1560 = or(UInt<1>(0h1), _T_1559) node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(_T_1560, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1560, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1564 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(_T_1564, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1564, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1568 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1572 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1576 = eq(a_first, UInt<1>(0h0)) node _T_1577 = and(io.in.a.valid, _T_1576) when _T_1577 : node _T_1578 = eq(io.in.a.bits.opcode, opcode) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_87 node _T_1582 = eq(io.in.a.bits.param, param) node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(_T_1582, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1582, UInt<1>(0h1), "") : assert_88 node _T_1586 = eq(io.in.a.bits.size, size) node _T_1587 = asUInt(reset) node _T_1588 = eq(_T_1587, UInt<1>(0h0)) when _T_1588 : node _T_1589 = eq(_T_1586, UInt<1>(0h0)) when _T_1589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1586, UInt<1>(0h1), "") : assert_89 node _T_1590 = eq(io.in.a.bits.source, source) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_90 node _T_1594 = eq(io.in.a.bits.address, address) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_91 node _T_1598 = and(io.in.a.ready, io.in.a.valid) node _T_1599 = and(_T_1598, a_first) when _T_1599 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1600 = eq(d_first, UInt<1>(0h0)) node _T_1601 = and(io.in.d.valid, _T_1600) when _T_1601 : node _T_1602 = eq(io.in.d.bits.opcode, opcode_1) node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(_T_1602, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1602, UInt<1>(0h1), "") : assert_92 node _T_1606 = eq(io.in.d.bits.param, param_1) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_93 node _T_1610 = eq(io.in.d.bits.size, size_1) node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(_T_1610, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1610, UInt<1>(0h1), "") : assert_94 node _T_1614 = eq(io.in.d.bits.source, source_1) node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(_T_1614, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1614, UInt<1>(0h1), "") : assert_95 node _T_1618 = eq(io.in.d.bits.sink, sink) node _T_1619 = asUInt(reset) node _T_1620 = eq(_T_1619, UInt<1>(0h0)) when _T_1620 : node _T_1621 = eq(_T_1618, UInt<1>(0h0)) when _T_1621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1618, UInt<1>(0h1), "") : assert_96 node _T_1622 = eq(io.in.d.bits.denied, denied) node _T_1623 = asUInt(reset) node _T_1624 = eq(_T_1623, UInt<1>(0h0)) when _T_1624 : node _T_1625 = eq(_T_1622, UInt<1>(0h0)) when _T_1625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1622, UInt<1>(0h1), "") : assert_97 node _T_1626 = and(io.in.d.ready, io.in.d.valid) node _T_1627 = and(_T_1626, d_first) when _T_1627 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1628 = and(io.in.a.valid, a_first_1) node _T_1629 = and(_T_1628, UInt<1>(0h1)) when _T_1629 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1630 = and(io.in.a.ready, io.in.a.valid) node _T_1631 = and(_T_1630, a_first_1) node _T_1632 = and(_T_1631, UInt<1>(0h1)) when _T_1632 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1633 = dshr(inflight, io.in.a.bits.source) node _T_1634 = bits(_T_1633, 0, 0) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(_T_1635, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1635, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1639 = and(io.in.d.valid, d_first_1) node _T_1640 = and(_T_1639, UInt<1>(0h1)) node _T_1641 = eq(d_release_ack, UInt<1>(0h0)) node _T_1642 = and(_T_1640, _T_1641) when _T_1642 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1643 = and(io.in.d.ready, io.in.d.valid) node _T_1644 = and(_T_1643, d_first_1) node _T_1645 = and(_T_1644, UInt<1>(0h1)) node _T_1646 = eq(d_release_ack, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1648 = and(io.in.d.valid, d_first_1) node _T_1649 = and(_T_1648, UInt<1>(0h1)) node _T_1650 = eq(d_release_ack, UInt<1>(0h0)) node _T_1651 = and(_T_1649, _T_1650) when _T_1651 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1652 = dshr(inflight, io.in.d.bits.source) node _T_1653 = bits(_T_1652, 0, 0) node _T_1654 = or(_T_1653, same_cycle_resp) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1658 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1659 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1660 = or(_T_1658, _T_1659) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_100 node _T_1664 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_101 else : node _T_1668 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1669 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1670 = or(_T_1668, _T_1669) node _T_1671 = asUInt(reset) node _T_1672 = eq(_T_1671, UInt<1>(0h0)) when _T_1672 : node _T_1673 = eq(_T_1670, UInt<1>(0h0)) when _T_1673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1670, UInt<1>(0h1), "") : assert_102 node _T_1674 = eq(io.in.d.bits.size, a_size_lookup) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_103 node _T_1678 = and(io.in.d.valid, d_first_1) node _T_1679 = and(_T_1678, a_first_1) node _T_1680 = and(_T_1679, io.in.a.valid) node _T_1681 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = eq(d_release_ack, UInt<1>(0h0)) node _T_1684 = and(_T_1682, _T_1683) when _T_1684 : node _T_1685 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1686 = or(_T_1685, io.in.a.ready) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_104 node _T_1690 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1691 = orr(a_set_wo_ready) node _T_1692 = eq(_T_1691, UInt<1>(0h0)) node _T_1693 = or(_T_1690, _T_1692) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_38 node _T_1697 = orr(inflight) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) node _T_1699 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1700 = or(_T_1698, _T_1699) node _T_1701 = lt(watchdog, plusarg_reader.out) node _T_1702 = or(_T_1700, _T_1701) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1706 = and(io.in.a.ready, io.in.a.valid) node _T_1707 = and(io.in.d.ready, io.in.d.valid) node _T_1708 = or(_T_1706, _T_1707) when _T_1708 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1709 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1710 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1711 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1712 = and(_T_1710, _T_1711) node _T_1713 = and(_T_1709, _T_1712) when _T_1713 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1714 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1715 = and(_T_1714, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1716 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1717 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1718 = and(_T_1716, _T_1717) node _T_1719 = and(_T_1715, _T_1718) when _T_1719 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1720 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1721 = bits(_T_1720, 0, 0) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(_T_1722, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1722, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1726 = and(io.in.d.valid, d_first_2) node _T_1727 = and(_T_1726, UInt<1>(0h1)) node _T_1728 = and(_T_1727, d_release_ack_1) when _T_1728 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1729 = and(io.in.d.ready, io.in.d.valid) node _T_1730 = and(_T_1729, d_first_2) node _T_1731 = and(_T_1730, UInt<1>(0h1)) node _T_1732 = and(_T_1731, d_release_ack_1) when _T_1732 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1733 = and(io.in.d.valid, d_first_2) node _T_1734 = and(_T_1733, UInt<1>(0h1)) node _T_1735 = and(_T_1734, d_release_ack_1) when _T_1735 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1736 = dshr(inflight_1, io.in.d.bits.source) node _T_1737 = bits(_T_1736, 0, 0) node _T_1738 = or(_T_1737, same_cycle_resp_1) node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(_T_1738, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1738, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1742 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(_T_1742, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1742, UInt<1>(0h1), "") : assert_109 else : node _T_1746 = eq(io.in.d.bits.size, c_size_lookup) node _T_1747 = asUInt(reset) node _T_1748 = eq(_T_1747, UInt<1>(0h0)) when _T_1748 : node _T_1749 = eq(_T_1746, UInt<1>(0h0)) when _T_1749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1746, UInt<1>(0h1), "") : assert_110 node _T_1750 = and(io.in.d.valid, d_first_2) node _T_1751 = and(_T_1750, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1752 = and(_T_1751, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1753 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1754 = and(_T_1752, _T_1753) node _T_1755 = and(_T_1754, d_release_ack_1) node _T_1756 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1757 = and(_T_1755, _T_1756) when _T_1757 : node _T_1758 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1759 = or(_T_1758, _WIRE_27.ready) node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(_T_1759, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1759, UInt<1>(0h1), "") : assert_111 node _T_1763 = orr(c_set_wo_ready) when _T_1763 : node _T_1764 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1765 = asUInt(reset) node _T_1766 = eq(_T_1765, UInt<1>(0h0)) when _T_1766 : node _T_1767 = eq(_T_1764, UInt<1>(0h0)) when _T_1767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1764, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_39 node _T_1768 = orr(inflight_1) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = lt(watchdog_1, plusarg_reader_1.out) node _T_1773 = or(_T_1771, _T_1772) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1777 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1778 = and(io.in.d.ready, io.in.d.valid) node _T_1779 = or(_T_1777, _T_1778) when _T_1779 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_1 : output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51) node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0)) node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1) connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2 connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RecFNToRecFN_1( // @[RecFNToRecFN.scala:44:5] input [64:0] io_in, // @[RecFNToRecFN.scala:48:16] input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out, // @[RecFNToRecFN.scala:48:16] output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16] ); wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (rawIn_isNaN & ~(io_in[51])), // @[rawFloatFromRecFN.scala:56:33] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:56:33] .io_in_isInf ((&(io_in[63:62])) & ~(io_in[61])), // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}] .io_in_isZero (~(\|(io_in[63:61]))), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}] .io_in_sign (io_in[64]), // @[rawFloatFromRecFN.scala:59:25] .io_in_sExp ({1'h0, io_in[63:52]}), // @[rawFloatFromRecFN.scala:51:21, :60:27] .io_in_sig ({1'h0, \|(io_in[63:61]), io_in[51:0]}), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}] .io_roundingMode (io_roundingMode), .io_out (io_out), .io_exceptionFlags (io_exceptionFlags) ); // @[RecFNToRecFN.scala:72:19] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHRFile : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}[1], flip req_is_probe : UInt<1>[1], resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, secondary_miss : UInt<1>[1], block_hit : UInt<1>[1], flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, prefetch : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<2>, param : UInt<3>, way_en : UInt<4>, voluntary : UInt<1>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, flip clear_all : UInt<1>, flip wb_resp : UInt<1>, fence_rdy : UInt<1>, probe_rdy : UInt<1>} wire req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}} connect req.bits, io.req[0].bits connect req.valid, io.req[0].valid connect req.ready, io.req[0].ready connect io.req[0].ready, UInt<1>(0h0) inst prefetcher of NullPrefetcher connect prefetcher.clock, clock connect prefetcher.reset, reset connect io.prefetch.bits, prefetcher.io.prefetch.bits connect io.prefetch.valid, prefetcher.io.prefetch.valid connect prefetcher.io.prefetch.ready, io.prefetch.ready node _cacheable_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _cacheable_T_1 = xor(req.bits.addr, UInt<1>(0h0)) node _cacheable_T_2 = cvt(_cacheable_T_1) node _cacheable_T_3 = and(_cacheable_T_2, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_4 = asSInt(_cacheable_T_3) node _cacheable_T_5 = eq(_cacheable_T_4, asSInt(UInt<1>(0h0))) node _cacheable_T_6 = xor(req.bits.addr, UInt<17>(0h10000)) node _cacheable_T_7 = cvt(_cacheable_T_6) node _cacheable_T_8 = and(_cacheable_T_7, asSInt(UInt<33>(0h8c011000))) node _cacheable_T_9 = asSInt(_cacheable_T_8) node _cacheable_T_10 = eq(_cacheable_T_9, asSInt(UInt<1>(0h0))) node _cacheable_T_11 = xor(req.bits.addr, UInt<28>(0hc000000)) node _cacheable_T_12 = cvt(_cacheable_T_11) node _cacheable_T_13 = and(_cacheable_T_12, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_14 = asSInt(_cacheable_T_13) node _cacheable_T_15 = eq(_cacheable_T_14, asSInt(UInt<1>(0h0))) node _cacheable_T_16 = or(_cacheable_T_5, _cacheable_T_10) node _cacheable_T_17 = or(_cacheable_T_16, _cacheable_T_15) node _cacheable_T_18 = and(_cacheable_T, _cacheable_T_17) node _cacheable_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _cacheable_T_20 = or(UInt<1>(0h0), _cacheable_T_19) node _cacheable_T_21 = xor(req.bits.addr, UInt<28>(0h8000000)) node _cacheable_T_22 = cvt(_cacheable_T_21) node _cacheable_T_23 = and(_cacheable_T_22, asSInt(UInt<33>(0h8c010000))) node _cacheable_T_24 = asSInt(_cacheable_T_23) node _cacheable_T_25 = eq(_cacheable_T_24, asSInt(UInt<1>(0h0))) node _cacheable_T_26 = xor(req.bits.addr, UInt<32>(0h80000000)) node _cacheable_T_27 = cvt(_cacheable_T_26) node _cacheable_T_28 = and(_cacheable_T_27, asSInt(UInt<33>(0h80000000))) node _cacheable_T_29 = asSInt(_cacheable_T_28) node _cacheable_T_30 = eq(_cacheable_T_29, asSInt(UInt<1>(0h0))) node _cacheable_T_31 = or(_cacheable_T_25, _cacheable_T_30) node _cacheable_T_32 = and(_cacheable_T_20, _cacheable_T_31) node _cacheable_T_33 = or(UInt<1>(0h0), _cacheable_T_18) node cacheable = or(_cacheable_T_33, _cacheable_T_32) regreset sdq_val : UInt<17>, clock, reset, UInt<17>(0h0) node _sdq_alloc_id_T = bits(sdq_val, 16, 0) node _sdq_alloc_id_T_1 = not(_sdq_alloc_id_T) node _sdq_alloc_id_T_2 = bits(_sdq_alloc_id_T_1, 0, 0) node _sdq_alloc_id_T_3 = bits(_sdq_alloc_id_T_1, 1, 1) node _sdq_alloc_id_T_4 = bits(_sdq_alloc_id_T_1, 2, 2) node _sdq_alloc_id_T_5 = bits(_sdq_alloc_id_T_1, 3, 3) node _sdq_alloc_id_T_6 = bits(_sdq_alloc_id_T_1, 4, 4) node _sdq_alloc_id_T_7 = bits(_sdq_alloc_id_T_1, 5, 5) node _sdq_alloc_id_T_8 = bits(_sdq_alloc_id_T_1, 6, 6) node _sdq_alloc_id_T_9 = bits(_sdq_alloc_id_T_1, 7, 7) node _sdq_alloc_id_T_10 = bits(_sdq_alloc_id_T_1, 8, 8) node _sdq_alloc_id_T_11 = bits(_sdq_alloc_id_T_1, 9, 9) node _sdq_alloc_id_T_12 = bits(_sdq_alloc_id_T_1, 10, 10) node _sdq_alloc_id_T_13 = bits(_sdq_alloc_id_T_1, 11, 11) node _sdq_alloc_id_T_14 = bits(_sdq_alloc_id_T_1, 12, 12) node _sdq_alloc_id_T_15 = bits(_sdq_alloc_id_T_1, 13, 13) node _sdq_alloc_id_T_16 = bits(_sdq_alloc_id_T_1, 14, 14) node _sdq_alloc_id_T_17 = bits(_sdq_alloc_id_T_1, 15, 15) node _sdq_alloc_id_T_18 = bits(_sdq_alloc_id_T_1, 16, 16) node _sdq_alloc_id_T_19 = mux(_sdq_alloc_id_T_17, UInt<4>(0hf), UInt<5>(0h10)) node _sdq_alloc_id_T_20 = mux(_sdq_alloc_id_T_16, UInt<4>(0he), _sdq_alloc_id_T_19) node _sdq_alloc_id_T_21 = mux(_sdq_alloc_id_T_15, UInt<4>(0hd), _sdq_alloc_id_T_20) node _sdq_alloc_id_T_22 = mux(_sdq_alloc_id_T_14, UInt<4>(0hc), _sdq_alloc_id_T_21) node _sdq_alloc_id_T_23 = mux(_sdq_alloc_id_T_13, UInt<4>(0hb), _sdq_alloc_id_T_22) node _sdq_alloc_id_T_24 = mux(_sdq_alloc_id_T_12, UInt<4>(0ha), _sdq_alloc_id_T_23) node _sdq_alloc_id_T_25 = mux(_sdq_alloc_id_T_11, UInt<4>(0h9), _sdq_alloc_id_T_24) node _sdq_alloc_id_T_26 = mux(_sdq_alloc_id_T_10, UInt<4>(0h8), _sdq_alloc_id_T_25) node _sdq_alloc_id_T_27 = mux(_sdq_alloc_id_T_9, UInt<3>(0h7), _sdq_alloc_id_T_26) node _sdq_alloc_id_T_28 = mux(_sdq_alloc_id_T_8, UInt<3>(0h6), _sdq_alloc_id_T_27) node _sdq_alloc_id_T_29 = mux(_sdq_alloc_id_T_7, UInt<3>(0h5), _sdq_alloc_id_T_28) node _sdq_alloc_id_T_30 = mux(_sdq_alloc_id_T_6, UInt<3>(0h4), _sdq_alloc_id_T_29) node _sdq_alloc_id_T_31 = mux(_sdq_alloc_id_T_5, UInt<2>(0h3), _sdq_alloc_id_T_30) node _sdq_alloc_id_T_32 = mux(_sdq_alloc_id_T_4, UInt<2>(0h2), _sdq_alloc_id_T_31) node _sdq_alloc_id_T_33 = mux(_sdq_alloc_id_T_3, UInt<1>(0h1), _sdq_alloc_id_T_32) node sdq_alloc_id = mux(_sdq_alloc_id_T_2, UInt<1>(0h0), _sdq_alloc_id_T_33) node _sdq_rdy_T = andr(sdq_val) node sdq_rdy = eq(_sdq_rdy_T, UInt<1>(0h0)) node _sdq_enq_T = and(req.ready, req.valid) node _sdq_enq_T_1 = and(_sdq_enq_T, cacheable) node _sdq_enq_T_2 = eq(req.bits.uop.mem_cmd, UInt<1>(0h1)) node _sdq_enq_T_3 = eq(req.bits.uop.mem_cmd, UInt<5>(0h11)) node _sdq_enq_T_4 = or(_sdq_enq_T_2, _sdq_enq_T_3) node _sdq_enq_T_5 = eq(req.bits.uop.mem_cmd, UInt<3>(0h7)) node _sdq_enq_T_6 = or(_sdq_enq_T_4, _sdq_enq_T_5) node _sdq_enq_T_7 = eq(req.bits.uop.mem_cmd, UInt<3>(0h4)) node _sdq_enq_T_8 = eq(req.bits.uop.mem_cmd, UInt<4>(0h9)) node _sdq_enq_T_9 = eq(req.bits.uop.mem_cmd, UInt<4>(0ha)) node _sdq_enq_T_10 = eq(req.bits.uop.mem_cmd, UInt<4>(0hb)) node _sdq_enq_T_11 = or(_sdq_enq_T_7, _sdq_enq_T_8) node _sdq_enq_T_12 = or(_sdq_enq_T_11, _sdq_enq_T_9) node _sdq_enq_T_13 = or(_sdq_enq_T_12, _sdq_enq_T_10) node _sdq_enq_T_14 = eq(req.bits.uop.mem_cmd, UInt<4>(0h8)) node _sdq_enq_T_15 = eq(req.bits.uop.mem_cmd, UInt<4>(0hc)) node _sdq_enq_T_16 = eq(req.bits.uop.mem_cmd, UInt<4>(0hd)) node _sdq_enq_T_17 = eq(req.bits.uop.mem_cmd, UInt<4>(0he)) node _sdq_enq_T_18 = eq(req.bits.uop.mem_cmd, UInt<4>(0hf)) node _sdq_enq_T_19 = or(_sdq_enq_T_14, _sdq_enq_T_15) node _sdq_enq_T_20 = or(_sdq_enq_T_19, _sdq_enq_T_16) node _sdq_enq_T_21 = or(_sdq_enq_T_20, _sdq_enq_T_17) node _sdq_enq_T_22 = or(_sdq_enq_T_21, _sdq_enq_T_18) node _sdq_enq_T_23 = or(_sdq_enq_T_13, _sdq_enq_T_22) node _sdq_enq_T_24 = or(_sdq_enq_T_6, _sdq_enq_T_23) node sdq_enq = and(_sdq_enq_T_1, _sdq_enq_T_24) cmem sdq : UInt<64> [17] when sdq_enq : infer mport MPORT = sdq[sdq_alloc_id], clock connect MPORT, req.bits.data reg lb : UInt<64>[8][2], clock wire idx_matches : UInt<1>[2][1] wire tag_matches : UInt<1>[2][1] wire way_matches : UInt<1>[2][1] node _tag_match_T = mux(idx_matches[0][0], tag_matches[0][0], UInt<1>(0h0)) node _tag_match_T_1 = mux(idx_matches[0][1], tag_matches[0][1], UInt<1>(0h0)) node _tag_match_T_2 = or(_tag_match_T, _tag_match_T_1) wire _tag_match_WIRE : UInt<1> connect _tag_match_WIRE, _tag_match_T_2 wire tag_match : UInt<1>[1] connect tag_match[0], _tag_match_WIRE node _idx_match_T = or(idx_matches[0][0], idx_matches[0][1]) wire idx_match : UInt<1>[1] connect idx_match[0], _idx_match_T node _way_match_T = mux(idx_matches[0][0], way_matches[0][0], UInt<1>(0h0)) node _way_match_T_1 = mux(idx_matches[0][1], way_matches[0][1], UInt<1>(0h0)) node _way_match_T_2 = or(_way_match_T, _way_match_T_1) wire _way_match_WIRE : UInt<1> connect _way_match_WIRE, _way_match_T_2 wire way_match : UInt<1>[1] connect way_match[0], _way_match_WIRE wire wb_tag_list : UInt<20>[2] inst meta_write_arb of Arbiter2_L1MetaWriteReq connect meta_write_arb.clock, clock connect meta_write_arb.reset, reset inst meta_read_arb of Arbiter2_L1MetaReadReq connect meta_read_arb.clock, clock connect meta_read_arb.reset, reset inst wb_req_arb of Arbiter2_WritebackReq connect wb_req_arb.clock, clock connect wb_req_arb.reset, reset inst replay_arb of Arbiter2_BoomDCacheReqInternal connect replay_arb.clock, clock connect replay_arb.reset, reset inst resp_arb of Arbiter3_BoomDCacheResp connect resp_arb.clock, clock connect resp_arb.reset, reset inst refill_arb of Arbiter2_L1DataWriteReq connect refill_arb.clock, clock connect refill_arb.reset, reset wire commit_vals : UInt<1>[2] wire commit_addrs : UInt<40>[2] wire commit_cohs : { state : UInt<2>}[2] connect io.fence_rdy, UInt<1>(0h1) connect io.probe_rdy, UInt<1>(0h1) connect io.mem_grant.ready, UInt<1>(0h0) wire mshr_alloc_idx : UInt wire pri_rdy : UInt<1> connect pri_rdy, UInt<1>(0h0) node _pri_val_T = and(req.valid, sdq_rdy) node _pri_val_T_1 = and(_pri_val_T, cacheable) node _pri_val_T_2 = eq(idx_match[0], UInt<1>(0h0)) node pri_val = and(_pri_val_T_1, _pri_val_T_2) inst mshrs_0 of BoomMSHR connect mshrs_0.clock, clock connect mshrs_0.reset, reset connect mshrs_0.io.id, UInt<1>(0h0) node _idx_matches_0_0_T = bits(io.req[0].bits.addr, 11, 6) node _idx_matches_0_0_T_1 = eq(mshrs_0.io.idx.bits, _idx_matches_0_0_T) node _idx_matches_0_0_T_2 = and(mshrs_0.io.idx.valid, _idx_matches_0_0_T_1) connect idx_matches[0][0], _idx_matches_0_0_T_2 node _tag_matches_0_0_T = shr(io.req[0].bits.addr, 12) node _tag_matches_0_0_T_1 = eq(mshrs_0.io.tag.bits, _tag_matches_0_0_T) node _tag_matches_0_0_T_2 = and(mshrs_0.io.tag.valid, _tag_matches_0_0_T_1) connect tag_matches[0][0], _tag_matches_0_0_T_2 node _way_matches_0_0_T = eq(mshrs_0.io.way.bits, io.req[0].bits.way_en) node _way_matches_0_0_T_1 = and(mshrs_0.io.way.valid, _way_matches_0_0_T) connect way_matches[0][0], _way_matches_0_0_T_1 connect wb_tag_list[0], mshrs_0.io.wb_req.bits.tag node _mshr_io_req_pri_val_T = eq(UInt<1>(0h0), mshr_alloc_idx) node _mshr_io_req_pri_val_T_1 = and(_mshr_io_req_pri_val_T, pri_val) connect mshrs_0.io.req_pri_val, _mshr_io_req_pri_val_T_1 node _T = eq(UInt<1>(0h0), mshr_alloc_idx) when _T : connect pri_rdy, mshrs_0.io.req_pri_rdy node _mshr_io_req_sec_val_T = and(req.valid, sdq_rdy) node _mshr_io_req_sec_val_T_1 = and(_mshr_io_req_sec_val_T, tag_match[0]) node _mshr_io_req_sec_val_T_2 = and(_mshr_io_req_sec_val_T_1, idx_matches[0][0]) node _mshr_io_req_sec_val_T_3 = and(_mshr_io_req_sec_val_T_2, cacheable) connect mshrs_0.io.req_sec_val, _mshr_io_req_sec_val_T_3 connect mshrs_0.io.req.sdq_id, req.bits.sdq_id connect mshrs_0.io.req.way_en, req.bits.way_en connect mshrs_0.io.req.old_meta.tag, req.bits.old_meta.tag connect mshrs_0.io.req.old_meta.coh.state, req.bits.old_meta.coh.state connect mshrs_0.io.req.tag_match, req.bits.tag_match connect mshrs_0.io.req.is_hella, req.bits.is_hella connect mshrs_0.io.req.data, req.bits.data connect mshrs_0.io.req.addr, req.bits.addr connect mshrs_0.io.req.uop.debug_tsrc, req.bits.uop.debug_tsrc connect mshrs_0.io.req.uop.debug_fsrc, req.bits.uop.debug_fsrc connect mshrs_0.io.req.uop.bp_xcpt_if, req.bits.uop.bp_xcpt_if connect mshrs_0.io.req.uop.bp_debug_if, req.bits.uop.bp_debug_if connect mshrs_0.io.req.uop.xcpt_ma_if, req.bits.uop.xcpt_ma_if connect mshrs_0.io.req.uop.xcpt_ae_if, req.bits.uop.xcpt_ae_if connect mshrs_0.io.req.uop.xcpt_pf_if, req.bits.uop.xcpt_pf_if connect mshrs_0.io.req.uop.fp_typ, req.bits.uop.fp_typ connect mshrs_0.io.req.uop.fp_rm, req.bits.uop.fp_rm connect mshrs_0.io.req.uop.fp_val, req.bits.uop.fp_val connect mshrs_0.io.req.uop.fcn_op, req.bits.uop.fcn_op connect mshrs_0.io.req.uop.fcn_dw, req.bits.uop.fcn_dw connect mshrs_0.io.req.uop.frs3_en, req.bits.uop.frs3_en connect mshrs_0.io.req.uop.lrs2_rtype, req.bits.uop.lrs2_rtype connect mshrs_0.io.req.uop.lrs1_rtype, req.bits.uop.lrs1_rtype connect mshrs_0.io.req.uop.dst_rtype, req.bits.uop.dst_rtype connect mshrs_0.io.req.uop.lrs3, req.bits.uop.lrs3 connect mshrs_0.io.req.uop.lrs2, req.bits.uop.lrs2 connect mshrs_0.io.req.uop.lrs1, req.bits.uop.lrs1 connect mshrs_0.io.req.uop.ldst, req.bits.uop.ldst connect mshrs_0.io.req.uop.ldst_is_rs1, req.bits.uop.ldst_is_rs1 connect mshrs_0.io.req.uop.csr_cmd, req.bits.uop.csr_cmd connect mshrs_0.io.req.uop.flush_on_commit, req.bits.uop.flush_on_commit connect mshrs_0.io.req.uop.is_unique, req.bits.uop.is_unique connect mshrs_0.io.req.uop.uses_stq, req.bits.uop.uses_stq connect mshrs_0.io.req.uop.uses_ldq, req.bits.uop.uses_ldq connect mshrs_0.io.req.uop.mem_signed, req.bits.uop.mem_signed connect mshrs_0.io.req.uop.mem_size, req.bits.uop.mem_size connect mshrs_0.io.req.uop.mem_cmd, req.bits.uop.mem_cmd connect mshrs_0.io.req.uop.exc_cause, req.bits.uop.exc_cause connect mshrs_0.io.req.uop.exception, req.bits.uop.exception connect mshrs_0.io.req.uop.stale_pdst, req.bits.uop.stale_pdst connect mshrs_0.io.req.uop.ppred_busy, req.bits.uop.ppred_busy connect mshrs_0.io.req.uop.prs3_busy, req.bits.uop.prs3_busy connect mshrs_0.io.req.uop.prs2_busy, req.bits.uop.prs2_busy connect mshrs_0.io.req.uop.prs1_busy, req.bits.uop.prs1_busy connect mshrs_0.io.req.uop.ppred, req.bits.uop.ppred connect mshrs_0.io.req.uop.prs3, req.bits.uop.prs3 connect mshrs_0.io.req.uop.prs2, req.bits.uop.prs2 connect mshrs_0.io.req.uop.prs1, req.bits.uop.prs1 connect mshrs_0.io.req.uop.pdst, req.bits.uop.pdst connect mshrs_0.io.req.uop.rxq_idx, req.bits.uop.rxq_idx connect mshrs_0.io.req.uop.stq_idx, req.bits.uop.stq_idx connect mshrs_0.io.req.uop.ldq_idx, req.bits.uop.ldq_idx connect mshrs_0.io.req.uop.rob_idx, req.bits.uop.rob_idx connect mshrs_0.io.req.uop.fp_ctrl.vec, req.bits.uop.fp_ctrl.vec connect mshrs_0.io.req.uop.fp_ctrl.wflags, req.bits.uop.fp_ctrl.wflags connect mshrs_0.io.req.uop.fp_ctrl.sqrt, req.bits.uop.fp_ctrl.sqrt connect mshrs_0.io.req.uop.fp_ctrl.div, req.bits.uop.fp_ctrl.div connect mshrs_0.io.req.uop.fp_ctrl.fma, req.bits.uop.fp_ctrl.fma connect mshrs_0.io.req.uop.fp_ctrl.fastpipe, req.bits.uop.fp_ctrl.fastpipe connect mshrs_0.io.req.uop.fp_ctrl.toint, req.bits.uop.fp_ctrl.toint connect mshrs_0.io.req.uop.fp_ctrl.fromint, req.bits.uop.fp_ctrl.fromint connect mshrs_0.io.req.uop.fp_ctrl.typeTagOut, req.bits.uop.fp_ctrl.typeTagOut connect mshrs_0.io.req.uop.fp_ctrl.typeTagIn, req.bits.uop.fp_ctrl.typeTagIn connect mshrs_0.io.req.uop.fp_ctrl.swap23, req.bits.uop.fp_ctrl.swap23 connect mshrs_0.io.req.uop.fp_ctrl.swap12, req.bits.uop.fp_ctrl.swap12 connect mshrs_0.io.req.uop.fp_ctrl.ren3, req.bits.uop.fp_ctrl.ren3 connect mshrs_0.io.req.uop.fp_ctrl.ren2, req.bits.uop.fp_ctrl.ren2 connect mshrs_0.io.req.uop.fp_ctrl.ren1, req.bits.uop.fp_ctrl.ren1 connect mshrs_0.io.req.uop.fp_ctrl.wen, req.bits.uop.fp_ctrl.wen connect mshrs_0.io.req.uop.fp_ctrl.ldst, req.bits.uop.fp_ctrl.ldst connect mshrs_0.io.req.uop.op2_sel, req.bits.uop.op2_sel connect mshrs_0.io.req.uop.op1_sel, req.bits.uop.op1_sel connect mshrs_0.io.req.uop.imm_packed, req.bits.uop.imm_packed connect mshrs_0.io.req.uop.pimm, req.bits.uop.pimm connect mshrs_0.io.req.uop.imm_sel, req.bits.uop.imm_sel connect mshrs_0.io.req.uop.imm_rename, req.bits.uop.imm_rename connect mshrs_0.io.req.uop.taken, req.bits.uop.taken connect mshrs_0.io.req.uop.pc_lob, req.bits.uop.pc_lob connect mshrs_0.io.req.uop.edge_inst, req.bits.uop.edge_inst connect mshrs_0.io.req.uop.ftq_idx, req.bits.uop.ftq_idx connect mshrs_0.io.req.uop.is_mov, req.bits.uop.is_mov connect mshrs_0.io.req.uop.is_rocc, req.bits.uop.is_rocc connect mshrs_0.io.req.uop.is_sys_pc2epc, req.bits.uop.is_sys_pc2epc connect mshrs_0.io.req.uop.is_eret, req.bits.uop.is_eret connect mshrs_0.io.req.uop.is_amo, req.bits.uop.is_amo connect mshrs_0.io.req.uop.is_sfence, req.bits.uop.is_sfence connect mshrs_0.io.req.uop.is_fencei, req.bits.uop.is_fencei connect mshrs_0.io.req.uop.is_fence, req.bits.uop.is_fence connect mshrs_0.io.req.uop.is_sfb, req.bits.uop.is_sfb connect mshrs_0.io.req.uop.br_type, req.bits.uop.br_type connect mshrs_0.io.req.uop.br_tag, req.bits.uop.br_tag connect mshrs_0.io.req.uop.br_mask, req.bits.uop.br_mask connect mshrs_0.io.req.uop.dis_col_sel, req.bits.uop.dis_col_sel connect mshrs_0.io.req.uop.iw_p3_bypass_hint, req.bits.uop.iw_p3_bypass_hint connect mshrs_0.io.req.uop.iw_p2_bypass_hint, req.bits.uop.iw_p2_bypass_hint connect mshrs_0.io.req.uop.iw_p1_bypass_hint, req.bits.uop.iw_p1_bypass_hint connect mshrs_0.io.req.uop.iw_p2_speculative_child, req.bits.uop.iw_p2_speculative_child connect mshrs_0.io.req.uop.iw_p1_speculative_child, req.bits.uop.iw_p1_speculative_child connect mshrs_0.io.req.uop.iw_issued_partial_dgen, req.bits.uop.iw_issued_partial_dgen connect mshrs_0.io.req.uop.iw_issued_partial_agen, req.bits.uop.iw_issued_partial_agen connect mshrs_0.io.req.uop.iw_issued, req.bits.uop.iw_issued connect mshrs_0.io.req.uop.fu_code[0], req.bits.uop.fu_code[0] connect mshrs_0.io.req.uop.fu_code[1], req.bits.uop.fu_code[1] connect mshrs_0.io.req.uop.fu_code[2], req.bits.uop.fu_code[2] connect mshrs_0.io.req.uop.fu_code[3], req.bits.uop.fu_code[3] connect mshrs_0.io.req.uop.fu_code[4], req.bits.uop.fu_code[4] connect mshrs_0.io.req.uop.fu_code[5], req.bits.uop.fu_code[5] connect mshrs_0.io.req.uop.fu_code[6], req.bits.uop.fu_code[6] connect mshrs_0.io.req.uop.fu_code[7], req.bits.uop.fu_code[7] connect mshrs_0.io.req.uop.fu_code[8], req.bits.uop.fu_code[8] connect mshrs_0.io.req.uop.fu_code[9], req.bits.uop.fu_code[9] connect mshrs_0.io.req.uop.iq_type[0], req.bits.uop.iq_type[0] connect mshrs_0.io.req.uop.iq_type[1], req.bits.uop.iq_type[1] connect mshrs_0.io.req.uop.iq_type[2], req.bits.uop.iq_type[2] connect mshrs_0.io.req.uop.iq_type[3], req.bits.uop.iq_type[3] connect mshrs_0.io.req.uop.debug_pc, req.bits.uop.debug_pc connect mshrs_0.io.req.uop.is_rvc, req.bits.uop.is_rvc connect mshrs_0.io.req.uop.debug_inst, req.bits.uop.debug_inst connect mshrs_0.io.req.uop.inst, req.bits.uop.inst connect mshrs_0.io.req_is_probe, io.req_is_probe[0] connect mshrs_0.io.req.sdq_id, sdq_alloc_id node _mshr_io_clear_prefetch_T = eq(req.valid, UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_1 = and(io.clear_all, _mshr_io_clear_prefetch_T) node _mshr_io_clear_prefetch_T_2 = and(req.valid, idx_matches[0][0]) node _mshr_io_clear_prefetch_T_3 = and(_mshr_io_clear_prefetch_T_2, cacheable) node _mshr_io_clear_prefetch_T_4 = eq(tag_match[0], UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_5 = and(_mshr_io_clear_prefetch_T_3, _mshr_io_clear_prefetch_T_4) node _mshr_io_clear_prefetch_T_6 = or(_mshr_io_clear_prefetch_T_1, _mshr_io_clear_prefetch_T_5) node _mshr_io_clear_prefetch_T_7 = and(io.req_is_probe[0], idx_matches[0][0]) node _mshr_io_clear_prefetch_T_8 = or(_mshr_io_clear_prefetch_T_6, _mshr_io_clear_prefetch_T_7) connect mshrs_0.io.clear_prefetch, _mshr_io_clear_prefetch_T_8 connect mshrs_0.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect mshrs_0.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect mshrs_0.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect mshrs_0.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect mshrs_0.io.brupdate.b2.taken, io.brupdate.b2.taken connect mshrs_0.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect mshrs_0.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect mshrs_0.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect mshrs_0.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect mshrs_0.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect mshrs_0.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect mshrs_0.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect mshrs_0.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect mshrs_0.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect mshrs_0.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect mshrs_0.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect mshrs_0.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect mshrs_0.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect mshrs_0.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect mshrs_0.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect mshrs_0.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect mshrs_0.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect mshrs_0.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect mshrs_0.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect mshrs_0.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect mshrs_0.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect mshrs_0.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect mshrs_0.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect mshrs_0.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect mshrs_0.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect mshrs_0.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect mshrs_0.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect mshrs_0.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect mshrs_0.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect mshrs_0.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect mshrs_0.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect mshrs_0.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect mshrs_0.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect mshrs_0.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect mshrs_0.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect mshrs_0.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect mshrs_0.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect mshrs_0.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect mshrs_0.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect mshrs_0.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect mshrs_0.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect mshrs_0.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect mshrs_0.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect mshrs_0.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect mshrs_0.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect mshrs_0.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect mshrs_0.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect mshrs_0.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect mshrs_0.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect mshrs_0.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect mshrs_0.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect mshrs_0.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect mshrs_0.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect mshrs_0.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect mshrs_0.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect mshrs_0.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect mshrs_0.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect mshrs_0.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect mshrs_0.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect mshrs_0.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect mshrs_0.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect mshrs_0.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect mshrs_0.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect mshrs_0.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect mshrs_0.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect mshrs_0.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect mshrs_0.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect mshrs_0.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect mshrs_0.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect mshrs_0.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect mshrs_0.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect mshrs_0.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect mshrs_0.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect mshrs_0.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect mshrs_0.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect mshrs_0.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect mshrs_0.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect mshrs_0.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect mshrs_0.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect mshrs_0.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect mshrs_0.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect mshrs_0.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect mshrs_0.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect mshrs_0.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect mshrs_0.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect mshrs_0.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect mshrs_0.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect mshrs_0.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect mshrs_0.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect mshrs_0.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect mshrs_0.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect mshrs_0.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect mshrs_0.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect mshrs_0.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect mshrs_0.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect mshrs_0.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect mshrs_0.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect mshrs_0.io.exception, io.exception connect mshrs_0.io.rob_pnr_idx, io.rob_pnr_idx connect mshrs_0.io.rob_head_idx, io.rob_head_idx connect mshrs_0.io.prober_state.bits, io.prober_state.bits connect mshrs_0.io.prober_state.valid, io.prober_state.valid connect mshrs_0.io.wb_resp, io.wb_resp connect meta_write_arb.io.in[0], mshrs_0.io.meta_write connect meta_read_arb.io.in[0], mshrs_0.io.meta_read connect mshrs_0.io.meta_resp.bits.tag, io.meta_resp.bits.tag connect mshrs_0.io.meta_resp.bits.coh.state, io.meta_resp.bits.coh.state connect mshrs_0.io.meta_resp.valid, io.meta_resp.valid connect wb_req_arb.io.in[0], mshrs_0.io.wb_req connect replay_arb.io.in[0], mshrs_0.io.replay connect refill_arb.io.in[0], mshrs_0.io.refill connect mshrs_0.io.lb_resp, lb[0][mshrs_0.io.lb_read.offset] when mshrs_0.io.lb_write.valid : connect lb[0][mshrs_0.io.lb_write.bits.offset], mshrs_0.io.lb_write.bits.data connect commit_vals[0], mshrs_0.io.commit_val connect commit_addrs[0], mshrs_0.io.commit_addr connect commit_cohs[0], mshrs_0.io.commit_coh connect mshrs_0.io.mem_grant.valid, UInt<1>(0h0) invalidate mshrs_0.io.mem_grant.bits.corrupt invalidate mshrs_0.io.mem_grant.bits.data invalidate mshrs_0.io.mem_grant.bits.denied invalidate mshrs_0.io.mem_grant.bits.sink invalidate mshrs_0.io.mem_grant.bits.source invalidate mshrs_0.io.mem_grant.bits.size invalidate mshrs_0.io.mem_grant.bits.param invalidate mshrs_0.io.mem_grant.bits.opcode node _T_1 = eq(io.mem_grant.bits.source, UInt<1>(0h0)) when _T_1 : connect mshrs_0.io.mem_grant, io.mem_grant node _T_2 = and(mshrs_0.io.req_sec_rdy, mshrs_0.io.req_sec_val) node _T_3 = or(UInt<1>(0h0), _T_2) connect resp_arb.io.in[0], mshrs_0.io.resp node _T_4 = eq(mshrs_0.io.req_pri_rdy, UInt<1>(0h0)) when _T_4 : connect io.fence_rdy, UInt<1>(0h0) node _T_5 = eq(mshrs_0.io.probe_rdy, UInt<1>(0h0)) node _T_6 = and(_T_5, idx_matches[0][0]) node _T_7 = and(_T_6, io.req_is_probe[0]) when _T_7 : connect io.probe_rdy, UInt<1>(0h0) inst mshrs_1 of BoomMSHR_1 connect mshrs_1.clock, clock connect mshrs_1.reset, reset connect mshrs_1.io.id, UInt<1>(0h1) node _idx_matches_0_1_T = bits(io.req[0].bits.addr, 11, 6) node _idx_matches_0_1_T_1 = eq(mshrs_1.io.idx.bits, _idx_matches_0_1_T) node _idx_matches_0_1_T_2 = and(mshrs_1.io.idx.valid, _idx_matches_0_1_T_1) connect idx_matches[0][1], _idx_matches_0_1_T_2 node _tag_matches_0_1_T = shr(io.req[0].bits.addr, 12) node _tag_matches_0_1_T_1 = eq(mshrs_1.io.tag.bits, _tag_matches_0_1_T) node _tag_matches_0_1_T_2 = and(mshrs_1.io.tag.valid, _tag_matches_0_1_T_1) connect tag_matches[0][1], _tag_matches_0_1_T_2 node _way_matches_0_1_T = eq(mshrs_1.io.way.bits, io.req[0].bits.way_en) node _way_matches_0_1_T_1 = and(mshrs_1.io.way.valid, _way_matches_0_1_T) connect way_matches[0][1], _way_matches_0_1_T_1 connect wb_tag_list[1], mshrs_1.io.wb_req.bits.tag node _mshr_io_req_pri_val_T_2 = eq(UInt<1>(0h1), mshr_alloc_idx) node _mshr_io_req_pri_val_T_3 = and(_mshr_io_req_pri_val_T_2, pri_val) connect mshrs_1.io.req_pri_val, _mshr_io_req_pri_val_T_3 node _T_8 = eq(UInt<1>(0h1), mshr_alloc_idx) when _T_8 : connect pri_rdy, mshrs_1.io.req_pri_rdy node _mshr_io_req_sec_val_T_4 = and(req.valid, sdq_rdy) node _mshr_io_req_sec_val_T_5 = and(_mshr_io_req_sec_val_T_4, tag_match[0]) node _mshr_io_req_sec_val_T_6 = and(_mshr_io_req_sec_val_T_5, idx_matches[0][1]) node _mshr_io_req_sec_val_T_7 = and(_mshr_io_req_sec_val_T_6, cacheable) connect mshrs_1.io.req_sec_val, _mshr_io_req_sec_val_T_7 connect mshrs_1.io.req.sdq_id, req.bits.sdq_id connect mshrs_1.io.req.way_en, req.bits.way_en connect mshrs_1.io.req.old_meta.tag, req.bits.old_meta.tag connect mshrs_1.io.req.old_meta.coh.state, req.bits.old_meta.coh.state connect mshrs_1.io.req.tag_match, req.bits.tag_match connect mshrs_1.io.req.is_hella, req.bits.is_hella connect mshrs_1.io.req.data, req.bits.data connect mshrs_1.io.req.addr, req.bits.addr connect mshrs_1.io.req.uop.debug_tsrc, req.bits.uop.debug_tsrc connect mshrs_1.io.req.uop.debug_fsrc, req.bits.uop.debug_fsrc connect mshrs_1.io.req.uop.bp_xcpt_if, req.bits.uop.bp_xcpt_if connect mshrs_1.io.req.uop.bp_debug_if, req.bits.uop.bp_debug_if connect mshrs_1.io.req.uop.xcpt_ma_if, req.bits.uop.xcpt_ma_if connect mshrs_1.io.req.uop.xcpt_ae_if, req.bits.uop.xcpt_ae_if connect mshrs_1.io.req.uop.xcpt_pf_if, req.bits.uop.xcpt_pf_if connect mshrs_1.io.req.uop.fp_typ, req.bits.uop.fp_typ connect mshrs_1.io.req.uop.fp_rm, req.bits.uop.fp_rm connect mshrs_1.io.req.uop.fp_val, req.bits.uop.fp_val connect mshrs_1.io.req.uop.fcn_op, req.bits.uop.fcn_op connect mshrs_1.io.req.uop.fcn_dw, req.bits.uop.fcn_dw connect mshrs_1.io.req.uop.frs3_en, req.bits.uop.frs3_en connect mshrs_1.io.req.uop.lrs2_rtype, req.bits.uop.lrs2_rtype connect mshrs_1.io.req.uop.lrs1_rtype, req.bits.uop.lrs1_rtype connect mshrs_1.io.req.uop.dst_rtype, req.bits.uop.dst_rtype connect mshrs_1.io.req.uop.lrs3, req.bits.uop.lrs3 connect mshrs_1.io.req.uop.lrs2, req.bits.uop.lrs2 connect mshrs_1.io.req.uop.lrs1, req.bits.uop.lrs1 connect mshrs_1.io.req.uop.ldst, req.bits.uop.ldst connect mshrs_1.io.req.uop.ldst_is_rs1, req.bits.uop.ldst_is_rs1 connect mshrs_1.io.req.uop.csr_cmd, req.bits.uop.csr_cmd connect mshrs_1.io.req.uop.flush_on_commit, req.bits.uop.flush_on_commit connect mshrs_1.io.req.uop.is_unique, req.bits.uop.is_unique connect mshrs_1.io.req.uop.uses_stq, req.bits.uop.uses_stq connect mshrs_1.io.req.uop.uses_ldq, req.bits.uop.uses_ldq connect mshrs_1.io.req.uop.mem_signed, req.bits.uop.mem_signed connect mshrs_1.io.req.uop.mem_size, req.bits.uop.mem_size connect mshrs_1.io.req.uop.mem_cmd, req.bits.uop.mem_cmd connect mshrs_1.io.req.uop.exc_cause, req.bits.uop.exc_cause connect mshrs_1.io.req.uop.exception, req.bits.uop.exception connect mshrs_1.io.req.uop.stale_pdst, req.bits.uop.stale_pdst connect mshrs_1.io.req.uop.ppred_busy, req.bits.uop.ppred_busy connect mshrs_1.io.req.uop.prs3_busy, req.bits.uop.prs3_busy connect mshrs_1.io.req.uop.prs2_busy, req.bits.uop.prs2_busy connect mshrs_1.io.req.uop.prs1_busy, req.bits.uop.prs1_busy connect mshrs_1.io.req.uop.ppred, req.bits.uop.ppred connect mshrs_1.io.req.uop.prs3, req.bits.uop.prs3 connect mshrs_1.io.req.uop.prs2, req.bits.uop.prs2 connect mshrs_1.io.req.uop.prs1, req.bits.uop.prs1 connect mshrs_1.io.req.uop.pdst, req.bits.uop.pdst connect mshrs_1.io.req.uop.rxq_idx, req.bits.uop.rxq_idx connect mshrs_1.io.req.uop.stq_idx, req.bits.uop.stq_idx connect mshrs_1.io.req.uop.ldq_idx, req.bits.uop.ldq_idx connect mshrs_1.io.req.uop.rob_idx, req.bits.uop.rob_idx connect mshrs_1.io.req.uop.fp_ctrl.vec, req.bits.uop.fp_ctrl.vec connect mshrs_1.io.req.uop.fp_ctrl.wflags, req.bits.uop.fp_ctrl.wflags connect mshrs_1.io.req.uop.fp_ctrl.sqrt, req.bits.uop.fp_ctrl.sqrt connect mshrs_1.io.req.uop.fp_ctrl.div, req.bits.uop.fp_ctrl.div connect mshrs_1.io.req.uop.fp_ctrl.fma, req.bits.uop.fp_ctrl.fma connect mshrs_1.io.req.uop.fp_ctrl.fastpipe, req.bits.uop.fp_ctrl.fastpipe connect mshrs_1.io.req.uop.fp_ctrl.toint, req.bits.uop.fp_ctrl.toint connect mshrs_1.io.req.uop.fp_ctrl.fromint, req.bits.uop.fp_ctrl.fromint connect mshrs_1.io.req.uop.fp_ctrl.typeTagOut, req.bits.uop.fp_ctrl.typeTagOut connect mshrs_1.io.req.uop.fp_ctrl.typeTagIn, req.bits.uop.fp_ctrl.typeTagIn connect mshrs_1.io.req.uop.fp_ctrl.swap23, req.bits.uop.fp_ctrl.swap23 connect mshrs_1.io.req.uop.fp_ctrl.swap12, req.bits.uop.fp_ctrl.swap12 connect mshrs_1.io.req.uop.fp_ctrl.ren3, req.bits.uop.fp_ctrl.ren3 connect mshrs_1.io.req.uop.fp_ctrl.ren2, req.bits.uop.fp_ctrl.ren2 connect mshrs_1.io.req.uop.fp_ctrl.ren1, req.bits.uop.fp_ctrl.ren1 connect mshrs_1.io.req.uop.fp_ctrl.wen, req.bits.uop.fp_ctrl.wen connect mshrs_1.io.req.uop.fp_ctrl.ldst, req.bits.uop.fp_ctrl.ldst connect mshrs_1.io.req.uop.op2_sel, req.bits.uop.op2_sel connect mshrs_1.io.req.uop.op1_sel, req.bits.uop.op1_sel connect mshrs_1.io.req.uop.imm_packed, req.bits.uop.imm_packed connect mshrs_1.io.req.uop.pimm, req.bits.uop.pimm connect mshrs_1.io.req.uop.imm_sel, req.bits.uop.imm_sel connect mshrs_1.io.req.uop.imm_rename, req.bits.uop.imm_rename connect mshrs_1.io.req.uop.taken, req.bits.uop.taken connect mshrs_1.io.req.uop.pc_lob, req.bits.uop.pc_lob connect mshrs_1.io.req.uop.edge_inst, req.bits.uop.edge_inst connect mshrs_1.io.req.uop.ftq_idx, req.bits.uop.ftq_idx connect mshrs_1.io.req.uop.is_mov, req.bits.uop.is_mov connect mshrs_1.io.req.uop.is_rocc, req.bits.uop.is_rocc connect mshrs_1.io.req.uop.is_sys_pc2epc, req.bits.uop.is_sys_pc2epc connect mshrs_1.io.req.uop.is_eret, req.bits.uop.is_eret connect mshrs_1.io.req.uop.is_amo, req.bits.uop.is_amo connect mshrs_1.io.req.uop.is_sfence, req.bits.uop.is_sfence connect mshrs_1.io.req.uop.is_fencei, req.bits.uop.is_fencei connect mshrs_1.io.req.uop.is_fence, req.bits.uop.is_fence connect mshrs_1.io.req.uop.is_sfb, req.bits.uop.is_sfb connect mshrs_1.io.req.uop.br_type, req.bits.uop.br_type connect mshrs_1.io.req.uop.br_tag, req.bits.uop.br_tag connect mshrs_1.io.req.uop.br_mask, req.bits.uop.br_mask connect mshrs_1.io.req.uop.dis_col_sel, req.bits.uop.dis_col_sel connect mshrs_1.io.req.uop.iw_p3_bypass_hint, req.bits.uop.iw_p3_bypass_hint connect mshrs_1.io.req.uop.iw_p2_bypass_hint, req.bits.uop.iw_p2_bypass_hint connect mshrs_1.io.req.uop.iw_p1_bypass_hint, req.bits.uop.iw_p1_bypass_hint connect mshrs_1.io.req.uop.iw_p2_speculative_child, req.bits.uop.iw_p2_speculative_child connect mshrs_1.io.req.uop.iw_p1_speculative_child, req.bits.uop.iw_p1_speculative_child connect mshrs_1.io.req.uop.iw_issued_partial_dgen, req.bits.uop.iw_issued_partial_dgen connect mshrs_1.io.req.uop.iw_issued_partial_agen, req.bits.uop.iw_issued_partial_agen connect mshrs_1.io.req.uop.iw_issued, req.bits.uop.iw_issued connect mshrs_1.io.req.uop.fu_code[0], req.bits.uop.fu_code[0] connect mshrs_1.io.req.uop.fu_code[1], req.bits.uop.fu_code[1] connect mshrs_1.io.req.uop.fu_code[2], req.bits.uop.fu_code[2] connect mshrs_1.io.req.uop.fu_code[3], req.bits.uop.fu_code[3] connect mshrs_1.io.req.uop.fu_code[4], req.bits.uop.fu_code[4] connect mshrs_1.io.req.uop.fu_code[5], req.bits.uop.fu_code[5] connect mshrs_1.io.req.uop.fu_code[6], req.bits.uop.fu_code[6] connect mshrs_1.io.req.uop.fu_code[7], req.bits.uop.fu_code[7] connect mshrs_1.io.req.uop.fu_code[8], req.bits.uop.fu_code[8] connect mshrs_1.io.req.uop.fu_code[9], req.bits.uop.fu_code[9] connect mshrs_1.io.req.uop.iq_type[0], req.bits.uop.iq_type[0] connect mshrs_1.io.req.uop.iq_type[1], req.bits.uop.iq_type[1] connect mshrs_1.io.req.uop.iq_type[2], req.bits.uop.iq_type[2] connect mshrs_1.io.req.uop.iq_type[3], req.bits.uop.iq_type[3] connect mshrs_1.io.req.uop.debug_pc, req.bits.uop.debug_pc connect mshrs_1.io.req.uop.is_rvc, req.bits.uop.is_rvc connect mshrs_1.io.req.uop.debug_inst, req.bits.uop.debug_inst connect mshrs_1.io.req.uop.inst, req.bits.uop.inst connect mshrs_1.io.req_is_probe, io.req_is_probe[0] connect mshrs_1.io.req.sdq_id, sdq_alloc_id node _mshr_io_clear_prefetch_T_9 = eq(req.valid, UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_10 = and(io.clear_all, _mshr_io_clear_prefetch_T_9) node _mshr_io_clear_prefetch_T_11 = and(req.valid, idx_matches[0][1]) node _mshr_io_clear_prefetch_T_12 = and(_mshr_io_clear_prefetch_T_11, cacheable) node _mshr_io_clear_prefetch_T_13 = eq(tag_match[0], UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_14 = and(_mshr_io_clear_prefetch_T_12, _mshr_io_clear_prefetch_T_13) node _mshr_io_clear_prefetch_T_15 = or(_mshr_io_clear_prefetch_T_10, _mshr_io_clear_prefetch_T_14) node _mshr_io_clear_prefetch_T_16 = and(io.req_is_probe[0], idx_matches[0][1]) node _mshr_io_clear_prefetch_T_17 = or(_mshr_io_clear_prefetch_T_15, _mshr_io_clear_prefetch_T_16) connect mshrs_1.io.clear_prefetch, _mshr_io_clear_prefetch_T_17 connect mshrs_1.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect mshrs_1.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect mshrs_1.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect mshrs_1.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect mshrs_1.io.brupdate.b2.taken, io.brupdate.b2.taken connect mshrs_1.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect mshrs_1.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect mshrs_1.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect mshrs_1.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect mshrs_1.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect mshrs_1.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect mshrs_1.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect mshrs_1.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect mshrs_1.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect mshrs_1.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect mshrs_1.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect mshrs_1.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect mshrs_1.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect mshrs_1.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect mshrs_1.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect mshrs_1.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect mshrs_1.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect mshrs_1.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect mshrs_1.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect mshrs_1.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect mshrs_1.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect mshrs_1.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect mshrs_1.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect mshrs_1.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect mshrs_1.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect mshrs_1.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect mshrs_1.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect mshrs_1.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect mshrs_1.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect mshrs_1.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect mshrs_1.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect mshrs_1.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect mshrs_1.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect mshrs_1.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect mshrs_1.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect mshrs_1.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect mshrs_1.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect mshrs_1.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect mshrs_1.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect mshrs_1.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect mshrs_1.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect mshrs_1.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect mshrs_1.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect mshrs_1.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect mshrs_1.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect mshrs_1.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect mshrs_1.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect mshrs_1.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect mshrs_1.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect mshrs_1.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect mshrs_1.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect mshrs_1.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect mshrs_1.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect mshrs_1.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect mshrs_1.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect mshrs_1.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect mshrs_1.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect mshrs_1.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect mshrs_1.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect mshrs_1.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect mshrs_1.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect mshrs_1.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect mshrs_1.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect mshrs_1.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect mshrs_1.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect mshrs_1.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect mshrs_1.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect mshrs_1.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect mshrs_1.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect mshrs_1.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect mshrs_1.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect mshrs_1.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect mshrs_1.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect mshrs_1.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect mshrs_1.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect mshrs_1.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect mshrs_1.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect mshrs_1.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect mshrs_1.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect mshrs_1.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect mshrs_1.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect mshrs_1.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect mshrs_1.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect mshrs_1.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect mshrs_1.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect mshrs_1.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect mshrs_1.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect mshrs_1.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect mshrs_1.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect mshrs_1.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect mshrs_1.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect mshrs_1.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect mshrs_1.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect mshrs_1.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect mshrs_1.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect mshrs_1.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect mshrs_1.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect mshrs_1.io.exception, io.exception connect mshrs_1.io.rob_pnr_idx, io.rob_pnr_idx connect mshrs_1.io.rob_head_idx, io.rob_head_idx connect mshrs_1.io.prober_state.bits, io.prober_state.bits connect mshrs_1.io.prober_state.valid, io.prober_state.valid connect mshrs_1.io.wb_resp, io.wb_resp connect meta_write_arb.io.in[1], mshrs_1.io.meta_write connect meta_read_arb.io.in[1], mshrs_1.io.meta_read connect mshrs_1.io.meta_resp.bits.tag, io.meta_resp.bits.tag connect mshrs_1.io.meta_resp.bits.coh.state, io.meta_resp.bits.coh.state connect mshrs_1.io.meta_resp.valid, io.meta_resp.valid connect wb_req_arb.io.in[1], mshrs_1.io.wb_req connect replay_arb.io.in[1], mshrs_1.io.replay connect refill_arb.io.in[1], mshrs_1.io.refill connect mshrs_1.io.lb_resp, lb[1][mshrs_1.io.lb_read.offset] when mshrs_1.io.lb_write.valid : connect lb[1][mshrs_1.io.lb_write.bits.offset], mshrs_1.io.lb_write.bits.data connect commit_vals[1], mshrs_1.io.commit_val connect commit_addrs[1], mshrs_1.io.commit_addr connect commit_cohs[1], mshrs_1.io.commit_coh connect mshrs_1.io.mem_grant.valid, UInt<1>(0h0) invalidate mshrs_1.io.mem_grant.bits.corrupt invalidate mshrs_1.io.mem_grant.bits.data invalidate mshrs_1.io.mem_grant.bits.denied invalidate mshrs_1.io.mem_grant.bits.sink invalidate mshrs_1.io.mem_grant.bits.source invalidate mshrs_1.io.mem_grant.bits.size invalidate mshrs_1.io.mem_grant.bits.param invalidate mshrs_1.io.mem_grant.bits.opcode node _T_9 = eq(io.mem_grant.bits.source, UInt<1>(0h1)) when _T_9 : connect mshrs_1.io.mem_grant, io.mem_grant node _T_10 = and(mshrs_1.io.req_sec_rdy, mshrs_1.io.req_sec_val) node _T_11 = or(_T_3, _T_10) connect resp_arb.io.in[1], mshrs_1.io.resp node _T_12 = eq(mshrs_1.io.req_pri_rdy, UInt<1>(0h0)) when _T_12 : connect io.fence_rdy, UInt<1>(0h0) node _T_13 = eq(mshrs_1.io.probe_rdy, UInt<1>(0h0)) node _T_14 = and(_T_13, idx_matches[0][1]) node _T_15 = and(_T_14, io.req_is_probe[0]) when _T_15 : connect io.probe_rdy, UInt<1>(0h0) regreset mshr_head : UInt<1>, clock, reset, UInt<1>(0h0) node _mshr_alloc_idx_temp_vec_T = geq(UInt<1>(0h0), mshr_head) node mshr_alloc_idx_temp_vec_0 = and(mshrs_0.io.req_pri_rdy, _mshr_alloc_idx_temp_vec_T) node _mshr_alloc_idx_temp_vec_T_1 = geq(UInt<1>(0h1), mshr_head) node mshr_alloc_idx_temp_vec_1 = and(mshrs_1.io.req_pri_rdy, _mshr_alloc_idx_temp_vec_T_1) node _mshr_alloc_idx_idx_T = mux(mshrs_0.io.req_pri_rdy, UInt<2>(0h2), UInt<2>(0h3)) node _mshr_alloc_idx_idx_T_1 = mux(mshr_alloc_idx_temp_vec_1, UInt<1>(0h1), _mshr_alloc_idx_idx_T) node mshr_alloc_idx_idx = mux(mshr_alloc_idx_temp_vec_0, UInt<1>(0h0), _mshr_alloc_idx_idx_T_1) node _mshr_alloc_idx_T = bits(mshr_alloc_idx_idx, 0, 0) reg mshr_alloc_idx_REG : UInt, clock connect mshr_alloc_idx_REG, _mshr_alloc_idx_T connect mshr_alloc_idx, mshr_alloc_idx_REG node _T_16 = and(pri_rdy, pri_val) when _T_16 : node _mshr_head_T = add(mshr_head, UInt<1>(0h1)) node _mshr_head_T_1 = tail(_mshr_head_T, 1) node _mshr_head_T_2 = bits(_mshr_head_T_1, 0, 0) connect mshr_head, _mshr_head_T_2 connect io.meta_write.bits, meta_write_arb.io.out.bits connect io.meta_write.valid, meta_write_arb.io.out.valid connect meta_write_arb.io.out.ready, io.meta_write.ready connect io.meta_read.bits, meta_read_arb.io.out.bits connect io.meta_read.valid, meta_read_arb.io.out.valid connect meta_read_arb.io.out.ready, io.meta_read.ready connect io.wb_req.bits, wb_req_arb.io.out.bits connect io.wb_req.valid, wb_req_arb.io.out.valid connect wb_req_arb.io.out.ready, io.wb_req.ready inst mmio_alloc_arb of Arbiter1_Bool connect mmio_alloc_arb.clock, clock connect mmio_alloc_arb.reset, reset inst mmios_0 of BoomIOMSHR connect mmios_0.clock, clock connect mmios_0.reset, reset connect mmio_alloc_arb.io.in[0].valid, mmios_0.io.req.ready invalidate mmio_alloc_arb.io.in[0].bits connect mmios_0.io.req.valid, mmio_alloc_arb.io.in[0].ready connect mmios_0.io.req.bits.is_hella, req.bits.is_hella connect mmios_0.io.req.bits.data, req.bits.data connect mmios_0.io.req.bits.addr, req.bits.addr connect mmios_0.io.req.bits.uop.debug_tsrc, req.bits.uop.debug_tsrc connect mmios_0.io.req.bits.uop.debug_fsrc, req.bits.uop.debug_fsrc connect mmios_0.io.req.bits.uop.bp_xcpt_if, req.bits.uop.bp_xcpt_if connect mmios_0.io.req.bits.uop.bp_debug_if, req.bits.uop.bp_debug_if connect mmios_0.io.req.bits.uop.xcpt_ma_if, req.bits.uop.xcpt_ma_if connect mmios_0.io.req.bits.uop.xcpt_ae_if, req.bits.uop.xcpt_ae_if connect mmios_0.io.req.bits.uop.xcpt_pf_if, req.bits.uop.xcpt_pf_if connect mmios_0.io.req.bits.uop.fp_typ, req.bits.uop.fp_typ connect mmios_0.io.req.bits.uop.fp_rm, req.bits.uop.fp_rm connect mmios_0.io.req.bits.uop.fp_val, req.bits.uop.fp_val connect mmios_0.io.req.bits.uop.fcn_op, req.bits.uop.fcn_op connect mmios_0.io.req.bits.uop.fcn_dw, req.bits.uop.fcn_dw connect mmios_0.io.req.bits.uop.frs3_en, req.bits.uop.frs3_en connect mmios_0.io.req.bits.uop.lrs2_rtype, req.bits.uop.lrs2_rtype connect mmios_0.io.req.bits.uop.lrs1_rtype, req.bits.uop.lrs1_rtype connect mmios_0.io.req.bits.uop.dst_rtype, req.bits.uop.dst_rtype connect mmios_0.io.req.bits.uop.lrs3, req.bits.uop.lrs3 connect mmios_0.io.req.bits.uop.lrs2, req.bits.uop.lrs2 connect mmios_0.io.req.bits.uop.lrs1, req.bits.uop.lrs1 connect mmios_0.io.req.bits.uop.ldst, req.bits.uop.ldst connect mmios_0.io.req.bits.uop.ldst_is_rs1, req.bits.uop.ldst_is_rs1 connect mmios_0.io.req.bits.uop.csr_cmd, req.bits.uop.csr_cmd connect mmios_0.io.req.bits.uop.flush_on_commit, req.bits.uop.flush_on_commit connect mmios_0.io.req.bits.uop.is_unique, req.bits.uop.is_unique connect mmios_0.io.req.bits.uop.uses_stq, req.bits.uop.uses_stq connect mmios_0.io.req.bits.uop.uses_ldq, req.bits.uop.uses_ldq connect mmios_0.io.req.bits.uop.mem_signed, req.bits.uop.mem_signed connect mmios_0.io.req.bits.uop.mem_size, req.bits.uop.mem_size connect mmios_0.io.req.bits.uop.mem_cmd, req.bits.uop.mem_cmd connect mmios_0.io.req.bits.uop.exc_cause, req.bits.uop.exc_cause connect mmios_0.io.req.bits.uop.exception, req.bits.uop.exception connect mmios_0.io.req.bits.uop.stale_pdst, req.bits.uop.stale_pdst connect mmios_0.io.req.bits.uop.ppred_busy, req.bits.uop.ppred_busy connect mmios_0.io.req.bits.uop.prs3_busy, req.bits.uop.prs3_busy connect mmios_0.io.req.bits.uop.prs2_busy, req.bits.uop.prs2_busy connect mmios_0.io.req.bits.uop.prs1_busy, req.bits.uop.prs1_busy connect mmios_0.io.req.bits.uop.ppred, req.bits.uop.ppred connect mmios_0.io.req.bits.uop.prs3, req.bits.uop.prs3 connect mmios_0.io.req.bits.uop.prs2, req.bits.uop.prs2 connect mmios_0.io.req.bits.uop.prs1, req.bits.uop.prs1 connect mmios_0.io.req.bits.uop.pdst, req.bits.uop.pdst connect mmios_0.io.req.bits.uop.rxq_idx, req.bits.uop.rxq_idx connect mmios_0.io.req.bits.uop.stq_idx, req.bits.uop.stq_idx connect mmios_0.io.req.bits.uop.ldq_idx, req.bits.uop.ldq_idx connect mmios_0.io.req.bits.uop.rob_idx, req.bits.uop.rob_idx connect mmios_0.io.req.bits.uop.fp_ctrl.vec, req.bits.uop.fp_ctrl.vec connect mmios_0.io.req.bits.uop.fp_ctrl.wflags, req.bits.uop.fp_ctrl.wflags connect mmios_0.io.req.bits.uop.fp_ctrl.sqrt, req.bits.uop.fp_ctrl.sqrt connect mmios_0.io.req.bits.uop.fp_ctrl.div, req.bits.uop.fp_ctrl.div connect mmios_0.io.req.bits.uop.fp_ctrl.fma, req.bits.uop.fp_ctrl.fma connect mmios_0.io.req.bits.uop.fp_ctrl.fastpipe, req.bits.uop.fp_ctrl.fastpipe connect mmios_0.io.req.bits.uop.fp_ctrl.toint, req.bits.uop.fp_ctrl.toint connect mmios_0.io.req.bits.uop.fp_ctrl.fromint, req.bits.uop.fp_ctrl.fromint connect mmios_0.io.req.bits.uop.fp_ctrl.typeTagOut, req.bits.uop.fp_ctrl.typeTagOut connect mmios_0.io.req.bits.uop.fp_ctrl.typeTagIn, req.bits.uop.fp_ctrl.typeTagIn connect mmios_0.io.req.bits.uop.fp_ctrl.swap23, req.bits.uop.fp_ctrl.swap23 connect mmios_0.io.req.bits.uop.fp_ctrl.swap12, req.bits.uop.fp_ctrl.swap12 connect mmios_0.io.req.bits.uop.fp_ctrl.ren3, req.bits.uop.fp_ctrl.ren3 connect mmios_0.io.req.bits.uop.fp_ctrl.ren2, req.bits.uop.fp_ctrl.ren2 connect mmios_0.io.req.bits.uop.fp_ctrl.ren1, req.bits.uop.fp_ctrl.ren1 connect mmios_0.io.req.bits.uop.fp_ctrl.wen, req.bits.uop.fp_ctrl.wen connect mmios_0.io.req.bits.uop.fp_ctrl.ldst, req.bits.uop.fp_ctrl.ldst connect mmios_0.io.req.bits.uop.op2_sel, req.bits.uop.op2_sel connect mmios_0.io.req.bits.uop.op1_sel, req.bits.uop.op1_sel connect mmios_0.io.req.bits.uop.imm_packed, req.bits.uop.imm_packed connect mmios_0.io.req.bits.uop.pimm, req.bits.uop.pimm connect mmios_0.io.req.bits.uop.imm_sel, req.bits.uop.imm_sel connect mmios_0.io.req.bits.uop.imm_rename, req.bits.uop.imm_rename connect mmios_0.io.req.bits.uop.taken, req.bits.uop.taken connect mmios_0.io.req.bits.uop.pc_lob, req.bits.uop.pc_lob connect mmios_0.io.req.bits.uop.edge_inst, req.bits.uop.edge_inst connect mmios_0.io.req.bits.uop.ftq_idx, req.bits.uop.ftq_idx connect mmios_0.io.req.bits.uop.is_mov, req.bits.uop.is_mov connect mmios_0.io.req.bits.uop.is_rocc, req.bits.uop.is_rocc connect mmios_0.io.req.bits.uop.is_sys_pc2epc, req.bits.uop.is_sys_pc2epc connect mmios_0.io.req.bits.uop.is_eret, req.bits.uop.is_eret connect mmios_0.io.req.bits.uop.is_amo, req.bits.uop.is_amo connect mmios_0.io.req.bits.uop.is_sfence, req.bits.uop.is_sfence connect mmios_0.io.req.bits.uop.is_fencei, req.bits.uop.is_fencei connect mmios_0.io.req.bits.uop.is_fence, req.bits.uop.is_fence connect mmios_0.io.req.bits.uop.is_sfb, req.bits.uop.is_sfb connect mmios_0.io.req.bits.uop.br_type, req.bits.uop.br_type connect mmios_0.io.req.bits.uop.br_tag, req.bits.uop.br_tag connect mmios_0.io.req.bits.uop.br_mask, req.bits.uop.br_mask connect mmios_0.io.req.bits.uop.dis_col_sel, req.bits.uop.dis_col_sel connect mmios_0.io.req.bits.uop.iw_p3_bypass_hint, req.bits.uop.iw_p3_bypass_hint connect mmios_0.io.req.bits.uop.iw_p2_bypass_hint, req.bits.uop.iw_p2_bypass_hint connect mmios_0.io.req.bits.uop.iw_p1_bypass_hint, req.bits.uop.iw_p1_bypass_hint connect mmios_0.io.req.bits.uop.iw_p2_speculative_child, req.bits.uop.iw_p2_speculative_child connect mmios_0.io.req.bits.uop.iw_p1_speculative_child, req.bits.uop.iw_p1_speculative_child connect mmios_0.io.req.bits.uop.iw_issued_partial_dgen, req.bits.uop.iw_issued_partial_dgen connect mmios_0.io.req.bits.uop.iw_issued_partial_agen, req.bits.uop.iw_issued_partial_agen connect mmios_0.io.req.bits.uop.iw_issued, req.bits.uop.iw_issued connect mmios_0.io.req.bits.uop.fu_code[0], req.bits.uop.fu_code[0] connect mmios_0.io.req.bits.uop.fu_code[1], req.bits.uop.fu_code[1] connect mmios_0.io.req.bits.uop.fu_code[2], req.bits.uop.fu_code[2] connect mmios_0.io.req.bits.uop.fu_code[3], req.bits.uop.fu_code[3] connect mmios_0.io.req.bits.uop.fu_code[4], req.bits.uop.fu_code[4] connect mmios_0.io.req.bits.uop.fu_code[5], req.bits.uop.fu_code[5] connect mmios_0.io.req.bits.uop.fu_code[6], req.bits.uop.fu_code[6] connect mmios_0.io.req.bits.uop.fu_code[7], req.bits.uop.fu_code[7] connect mmios_0.io.req.bits.uop.fu_code[8], req.bits.uop.fu_code[8] connect mmios_0.io.req.bits.uop.fu_code[9], req.bits.uop.fu_code[9] connect mmios_0.io.req.bits.uop.iq_type[0], req.bits.uop.iq_type[0] connect mmios_0.io.req.bits.uop.iq_type[1], req.bits.uop.iq_type[1] connect mmios_0.io.req.bits.uop.iq_type[2], req.bits.uop.iq_type[2] connect mmios_0.io.req.bits.uop.iq_type[3], req.bits.uop.iq_type[3] connect mmios_0.io.req.bits.uop.debug_pc, req.bits.uop.debug_pc connect mmios_0.io.req.bits.uop.is_rvc, req.bits.uop.is_rvc connect mmios_0.io.req.bits.uop.debug_inst, req.bits.uop.debug_inst connect mmios_0.io.req.bits.uop.inst, req.bits.uop.inst node _T_17 = or(UInt<1>(0h0), mmios_0.io.req.ready) connect mmios_0.io.mem_ack.bits.corrupt, io.mem_grant.bits.corrupt connect mmios_0.io.mem_ack.bits.data, io.mem_grant.bits.data connect mmios_0.io.mem_ack.bits.denied, io.mem_grant.bits.denied connect mmios_0.io.mem_ack.bits.sink, io.mem_grant.bits.sink connect mmios_0.io.mem_ack.bits.source, io.mem_grant.bits.source connect mmios_0.io.mem_ack.bits.size, io.mem_grant.bits.size connect mmios_0.io.mem_ack.bits.param, io.mem_grant.bits.param connect mmios_0.io.mem_ack.bits.opcode, io.mem_grant.bits.opcode node _mshr_io_mem_ack_valid_T = eq(io.mem_grant.bits.source, UInt<2>(0h3)) node _mshr_io_mem_ack_valid_T_1 = and(io.mem_grant.valid, _mshr_io_mem_ack_valid_T) connect mmios_0.io.mem_ack.valid, _mshr_io_mem_ack_valid_T_1 node _T_18 = eq(io.mem_grant.bits.source, UInt<2>(0h3)) when _T_18 : connect io.mem_grant.ready, UInt<1>(0h1) connect resp_arb.io.in[2], mmios_0.io.resp node _T_19 = eq(mmios_0.io.req.ready, UInt<1>(0h0)) when _T_19 : connect io.fence_rdy, UInt<1>(0h0) node _mmio_alloc_arb_io_out_ready_T = eq(cacheable, UInt<1>(0h0)) node _mmio_alloc_arb_io_out_ready_T_1 = and(req.valid, _mmio_alloc_arb_io_out_ready_T) connect mmio_alloc_arb.io.out.ready, _mmio_alloc_arb_io_out_ready_T_1 node _decode_T = dshl(UInt<12>(0hfff), mshrs_0.io.mem_acquire.bits.size) node _decode_T_1 = bits(_decode_T, 11, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(mshrs_0.io.mem_acquire.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_20 = mux(opdata, decode, UInt<1>(0h0)) node _decode_T_3 = dshl(UInt<12>(0hfff), mshrs_1.io.mem_acquire.bits.size) node _decode_T_4 = bits(_decode_T_3, 11, 0) node _decode_T_5 = not(_decode_T_4) node decode_1 = shr(_decode_T_5, 3) node _opdata_T_1 = bits(mshrs_1.io.mem_acquire.bits.opcode, 2, 2) node opdata_1 = eq(_opdata_T_1, UInt<1>(0h0)) node _T_21 = mux(opdata_1, decode_1, UInt<1>(0h0)) node _decode_T_6 = dshl(UInt<12>(0hfff), mmios_0.io.mem_access.bits.size) node _decode_T_7 = bits(_decode_T_6, 11, 0) node _decode_T_8 = not(_decode_T_7) node decode_2 = shr(_decode_T_8, 3) node _opdata_T_2 = bits(mmios_0.io.mem_access.bits.opcode, 2, 2) node opdata_2 = eq(_opdata_T_2, UInt<1>(0h0)) node _T_22 = mux(opdata_2, decode_2, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, io.mem_acquire.ready) node readys_hi = cat(mmios_0.io.mem_access.valid, mshrs_1.io.mem_acquire.valid) node _readys_T = cat(readys_hi, mshrs_0.io.mem_acquire.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 2, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = shl(_readys_T_3, 2) node _readys_T_5 = bits(_readys_T_4, 2, 0) node _readys_T_6 = or(_readys_T_3, _readys_T_5) node _readys_T_7 = bits(_readys_T_6, 2, 0) node _readys_T_8 = shl(_readys_T_7, 1) node _readys_T_9 = bits(_readys_T_8, 2, 0) node _readys_T_10 = not(_readys_T_9) node _readys_T_11 = bits(_readys_T_10, 0, 0) node _readys_T_12 = bits(_readys_T_10, 1, 1) node _readys_T_13 = bits(_readys_T_10, 2, 2) wire readys : UInt<1>[3] connect readys[0], _readys_T_11 connect readys[1], _readys_T_12 connect readys[2], _readys_T_13 node _winner_T = and(readys[0], mshrs_0.io.mem_acquire.valid) node _winner_T_1 = and(readys[1], mshrs_1.io.mem_acquire.valid) node _winner_T_2 = and(readys[2], mmios_0.io.mem_access.valid) wire winner : UInt<1>[3] connect winner[0], _winner_T connect winner[1], _winner_T_1 connect winner[2], _winner_T_2 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node prefixOR_2 = or(prefixOR_1, winner[1]) node _prefixOR_T = or(prefixOR_2, winner[2]) node _T_23 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_24 = eq(winner[0], UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = eq(prefixOR_1, UInt<1>(0h0)) node _T_27 = eq(winner[1], UInt<1>(0h0)) node _T_28 = or(_T_26, _T_27) node _T_29 = eq(prefixOR_2, UInt<1>(0h0)) node _T_30 = eq(winner[2], UInt<1>(0h0)) node _T_31 = or(_T_29, _T_30) node _T_32 = and(_T_25, _T_28) node _T_33 = and(_T_32, _T_31) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_33, UInt<1>(0h1), "") : assert node _T_37 = or(mshrs_0.io.mem_acquire.valid, mshrs_1.io.mem_acquire.valid) node _T_38 = or(_T_37, mmios_0.io.mem_access.valid) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = or(winner[0], winner[1]) node _T_41 = or(_T_40, winner[2]) node _T_42 = or(_T_39, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_42, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], _T_20, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_21, UInt<1>(0h0)) node maskedBeats_2 = mux(winner[2], _T_22, UInt<1>(0h0)) node _initBeats_T = or(maskedBeats_0, maskedBeats_1) node initBeats = or(_initBeats_T, maskedBeats_2) node _beatsLeft_T = and(io.mem_acquire.ready, io.mem_acquire.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[3] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) connect _state_WIRE[2], UInt<1>(0h0) regreset state : UInt<1>[3], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _mshrs_0_io_mem_acquire_ready_T = and(io.mem_acquire.ready, allowed[0]) connect mshrs_0.io.mem_acquire.ready, _mshrs_0_io_mem_acquire_ready_T node _mshrs_1_io_mem_acquire_ready_T = and(io.mem_acquire.ready, allowed[1]) connect mshrs_1.io.mem_acquire.ready, _mshrs_1_io_mem_acquire_ready_T node _mmios_0_io_mem_access_ready_T = and(io.mem_acquire.ready, allowed[2]) connect mmios_0.io.mem_access.ready, _mmios_0_io_mem_access_ready_T node _io_mem_acquire_valid_T = or(mshrs_0.io.mem_acquire.valid, mshrs_1.io.mem_acquire.valid) node _io_mem_acquire_valid_T_1 = or(_io_mem_acquire_valid_T, mmios_0.io.mem_access.valid) node _io_mem_acquire_valid_T_2 = mux(state[0], mshrs_0.io.mem_acquire.valid, UInt<1>(0h0)) node _io_mem_acquire_valid_T_3 = mux(state[1], mshrs_1.io.mem_acquire.valid, UInt<1>(0h0)) node _io_mem_acquire_valid_T_4 = mux(state[2], mmios_0.io.mem_access.valid, UInt<1>(0h0)) node _io_mem_acquire_valid_T_5 = or(_io_mem_acquire_valid_T_2, _io_mem_acquire_valid_T_3) node _io_mem_acquire_valid_T_6 = or(_io_mem_acquire_valid_T_5, _io_mem_acquire_valid_T_4) wire _io_mem_acquire_valid_WIRE : UInt<1> connect _io_mem_acquire_valid_WIRE, _io_mem_acquire_valid_T_6 node _io_mem_acquire_valid_T_7 = mux(idle, _io_mem_acquire_valid_T_1, _io_mem_acquire_valid_WIRE) connect io.mem_acquire.valid, _io_mem_acquire_valid_T_7 wire _io_mem_acquire_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _io_mem_acquire_bits_T = mux(muxState[0], mshrs_0.io.mem_acquire.bits.corrupt, UInt<1>(0h0)) node _io_mem_acquire_bits_T_1 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.corrupt, UInt<1>(0h0)) node _io_mem_acquire_bits_T_2 = mux(muxState[2], mmios_0.io.mem_access.bits.corrupt, UInt<1>(0h0)) node _io_mem_acquire_bits_T_3 = or(_io_mem_acquire_bits_T, _io_mem_acquire_bits_T_1) node _io_mem_acquire_bits_T_4 = or(_io_mem_acquire_bits_T_3, _io_mem_acquire_bits_T_2) wire _io_mem_acquire_bits_WIRE_1 : UInt<1> connect _io_mem_acquire_bits_WIRE_1, _io_mem_acquire_bits_T_4 connect _io_mem_acquire_bits_WIRE.corrupt, _io_mem_acquire_bits_WIRE_1 node _io_mem_acquire_bits_T_5 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.data, UInt<1>(0h0)) node _io_mem_acquire_bits_T_6 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.data, UInt<1>(0h0)) node _io_mem_acquire_bits_T_7 = mux(muxState[2], mmios_0.io.mem_access.bits.data, UInt<1>(0h0)) node _io_mem_acquire_bits_T_8 = or(_io_mem_acquire_bits_T_5, _io_mem_acquire_bits_T_6) node _io_mem_acquire_bits_T_9 = or(_io_mem_acquire_bits_T_8, _io_mem_acquire_bits_T_7) wire _io_mem_acquire_bits_WIRE_2 : UInt<64> connect _io_mem_acquire_bits_WIRE_2, _io_mem_acquire_bits_T_9 connect _io_mem_acquire_bits_WIRE.data, _io_mem_acquire_bits_WIRE_2 node _io_mem_acquire_bits_T_10 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.mask, UInt<1>(0h0)) node _io_mem_acquire_bits_T_11 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.mask, UInt<1>(0h0)) node _io_mem_acquire_bits_T_12 = mux(muxState[2], mmios_0.io.mem_access.bits.mask, UInt<1>(0h0)) node _io_mem_acquire_bits_T_13 = or(_io_mem_acquire_bits_T_10, _io_mem_acquire_bits_T_11) node _io_mem_acquire_bits_T_14 = or(_io_mem_acquire_bits_T_13, _io_mem_acquire_bits_T_12) wire _io_mem_acquire_bits_WIRE_3 : UInt<8> connect _io_mem_acquire_bits_WIRE_3, _io_mem_acquire_bits_T_14 connect _io_mem_acquire_bits_WIRE.mask, _io_mem_acquire_bits_WIRE_3 wire _io_mem_acquire_bits_WIRE_4 : { } connect _io_mem_acquire_bits_WIRE.echo, _io_mem_acquire_bits_WIRE_4 wire _io_mem_acquire_bits_WIRE_5 : { } connect _io_mem_acquire_bits_WIRE.user, _io_mem_acquire_bits_WIRE_5 node _io_mem_acquire_bits_T_15 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.address, UInt<1>(0h0)) node _io_mem_acquire_bits_T_16 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.address, UInt<1>(0h0)) node _io_mem_acquire_bits_T_17 = mux(muxState[2], mmios_0.io.mem_access.bits.address, UInt<1>(0h0)) node _io_mem_acquire_bits_T_18 = or(_io_mem_acquire_bits_T_15, _io_mem_acquire_bits_T_16) node _io_mem_acquire_bits_T_19 = or(_io_mem_acquire_bits_T_18, _io_mem_acquire_bits_T_17) wire _io_mem_acquire_bits_WIRE_6 : UInt<32> connect _io_mem_acquire_bits_WIRE_6, _io_mem_acquire_bits_T_19 connect _io_mem_acquire_bits_WIRE.address, _io_mem_acquire_bits_WIRE_6 node _io_mem_acquire_bits_T_20 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.source, UInt<1>(0h0)) node _io_mem_acquire_bits_T_21 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.source, UInt<1>(0h0)) node _io_mem_acquire_bits_T_22 = mux(muxState[2], mmios_0.io.mem_access.bits.source, UInt<1>(0h0)) node _io_mem_acquire_bits_T_23 = or(_io_mem_acquire_bits_T_20, _io_mem_acquire_bits_T_21) node _io_mem_acquire_bits_T_24 = or(_io_mem_acquire_bits_T_23, _io_mem_acquire_bits_T_22) wire _io_mem_acquire_bits_WIRE_7 : UInt<2> connect _io_mem_acquire_bits_WIRE_7, _io_mem_acquire_bits_T_24 connect _io_mem_acquire_bits_WIRE.source, _io_mem_acquire_bits_WIRE_7 node _io_mem_acquire_bits_T_25 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.size, UInt<1>(0h0)) node _io_mem_acquire_bits_T_26 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.size, UInt<1>(0h0)) node _io_mem_acquire_bits_T_27 = mux(muxState[2], mmios_0.io.mem_access.bits.size, UInt<1>(0h0)) node _io_mem_acquire_bits_T_28 = or(_io_mem_acquire_bits_T_25, _io_mem_acquire_bits_T_26) node _io_mem_acquire_bits_T_29 = or(_io_mem_acquire_bits_T_28, _io_mem_acquire_bits_T_27) wire _io_mem_acquire_bits_WIRE_8 : UInt<4> connect _io_mem_acquire_bits_WIRE_8, _io_mem_acquire_bits_T_29 connect _io_mem_acquire_bits_WIRE.size, _io_mem_acquire_bits_WIRE_8 node _io_mem_acquire_bits_T_30 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.param, UInt<1>(0h0)) node _io_mem_acquire_bits_T_31 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.param, UInt<1>(0h0)) node _io_mem_acquire_bits_T_32 = mux(muxState[2], mmios_0.io.mem_access.bits.param, UInt<1>(0h0)) node _io_mem_acquire_bits_T_33 = or(_io_mem_acquire_bits_T_30, _io_mem_acquire_bits_T_31) node _io_mem_acquire_bits_T_34 = or(_io_mem_acquire_bits_T_33, _io_mem_acquire_bits_T_32) wire _io_mem_acquire_bits_WIRE_9 : UInt<3> connect _io_mem_acquire_bits_WIRE_9, _io_mem_acquire_bits_T_34 connect _io_mem_acquire_bits_WIRE.param, _io_mem_acquire_bits_WIRE_9 node _io_mem_acquire_bits_T_35 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.opcode, UInt<1>(0h0)) node _io_mem_acquire_bits_T_36 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.opcode, UInt<1>(0h0)) node _io_mem_acquire_bits_T_37 = mux(muxState[2], mmios_0.io.mem_access.bits.opcode, UInt<1>(0h0)) node _io_mem_acquire_bits_T_38 = or(_io_mem_acquire_bits_T_35, _io_mem_acquire_bits_T_36) node _io_mem_acquire_bits_T_39 = or(_io_mem_acquire_bits_T_38, _io_mem_acquire_bits_T_37) wire _io_mem_acquire_bits_WIRE_10 : UInt<3> connect _io_mem_acquire_bits_WIRE_10, _io_mem_acquire_bits_T_39 connect _io_mem_acquire_bits_WIRE.opcode, _io_mem_acquire_bits_WIRE_10 connect io.mem_acquire.bits.corrupt, _io_mem_acquire_bits_WIRE.corrupt connect io.mem_acquire.bits.data, _io_mem_acquire_bits_WIRE.data connect io.mem_acquire.bits.mask, _io_mem_acquire_bits_WIRE.mask connect io.mem_acquire.bits.address, _io_mem_acquire_bits_WIRE.address connect io.mem_acquire.bits.source, _io_mem_acquire_bits_WIRE.source connect io.mem_acquire.bits.size, _io_mem_acquire_bits_WIRE.size connect io.mem_acquire.bits.param, _io_mem_acquire_bits_WIRE.param connect io.mem_acquire.bits.opcode, _io_mem_acquire_bits_WIRE.opcode regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, io.mem_finish.ready) node _readys_T_14 = cat(mshrs_1.io.mem_finish.valid, mshrs_0.io.mem_finish.valid) node _readys_T_15 = shl(_readys_T_14, 1) node _readys_T_16 = bits(_readys_T_15, 1, 0) node _readys_T_17 = or(_readys_T_14, _readys_T_16) node _readys_T_18 = bits(_readys_T_17, 1, 0) node _readys_T_19 = shl(_readys_T_18, 1) node _readys_T_20 = bits(_readys_T_19, 1, 0) node _readys_T_21 = not(_readys_T_20) node _readys_T_22 = bits(_readys_T_21, 0, 0) node _readys_T_23 = bits(_readys_T_21, 1, 1) wire readys_1 : UInt<1>[2] connect readys_1[0], _readys_T_22 connect readys_1[1], _readys_T_23 node _winner_T_3 = and(readys_1[0], mshrs_0.io.mem_finish.valid) node _winner_T_4 = and(readys_1[1], mshrs_1.io.mem_finish.valid) wire winner_1 : UInt<1>[2] connect winner_1[0], _winner_T_3 connect winner_1[1], _winner_T_4 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node _prefixOR_T_1 = or(prefixOR_1_1, winner_1[1]) node _T_46 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_47 = eq(winner_1[0], UInt<1>(0h0)) node _T_48 = or(_T_46, _T_47) node _T_49 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_50 = eq(winner_1[1], UInt<1>(0h0)) node _T_51 = or(_T_49, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_52, UInt<1>(0h1), "") : assert_2 node _T_56 = or(mshrs_0.io.mem_finish.valid, mshrs_1.io.mem_finish.valid) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = or(winner_1[0], winner_1[1]) node _T_59 = or(_T_57, _T_58) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_3 assert(clock, _T_59, UInt<1>(0h1), "") : assert_3 node maskedBeats_0_1 = mux(winner_1[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], UInt<1>(0h0), UInt<1>(0h0)) node initBeats_1 = or(maskedBeats_0_1, maskedBeats_1_1) node _beatsLeft_T_4 = and(io.mem_finish.ready, io.mem_finish.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[2] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) regreset state_1 : UInt<1>[2], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _mshrs_0_io_mem_finish_ready_T = and(io.mem_finish.ready, allowed_1[0]) connect mshrs_0.io.mem_finish.ready, _mshrs_0_io_mem_finish_ready_T node _mshrs_1_io_mem_finish_ready_T = and(io.mem_finish.ready, allowed_1[1]) connect mshrs_1.io.mem_finish.ready, _mshrs_1_io_mem_finish_ready_T node _io_mem_finish_valid_T = or(mshrs_0.io.mem_finish.valid, mshrs_1.io.mem_finish.valid) node _io_mem_finish_valid_T_1 = mux(state_1[0], mshrs_0.io.mem_finish.valid, UInt<1>(0h0)) node _io_mem_finish_valid_T_2 = mux(state_1[1], mshrs_1.io.mem_finish.valid, UInt<1>(0h0)) node _io_mem_finish_valid_T_3 = or(_io_mem_finish_valid_T_1, _io_mem_finish_valid_T_2) wire _io_mem_finish_valid_WIRE : UInt<1> connect _io_mem_finish_valid_WIRE, _io_mem_finish_valid_T_3 node _io_mem_finish_valid_T_4 = mux(idle_1, _io_mem_finish_valid_T, _io_mem_finish_valid_WIRE) connect io.mem_finish.valid, _io_mem_finish_valid_T_4 wire _io_mem_finish_bits_WIRE : { sink : UInt<3>} node _io_mem_finish_bits_T = mux(muxState_1[0], mshrs_0.io.mem_finish.bits.sink, UInt<1>(0h0)) node _io_mem_finish_bits_T_1 = mux(muxState_1[1], mshrs_1.io.mem_finish.bits.sink, UInt<1>(0h0)) node _io_mem_finish_bits_T_2 = or(_io_mem_finish_bits_T, _io_mem_finish_bits_T_1) wire _io_mem_finish_bits_WIRE_1 : UInt<3> connect _io_mem_finish_bits_WIRE_1, _io_mem_finish_bits_T_2 connect _io_mem_finish_bits_WIRE.sink, _io_mem_finish_bits_WIRE_1 connect io.mem_finish.bits.sink, _io_mem_finish_bits_WIRE.sink inst respq of BranchKillableQueue_4 connect respq.clock, clock connect respq.reset, reset connect respq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect respq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect respq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect respq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect respq.io.brupdate.b2.taken, io.brupdate.b2.taken connect respq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect respq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect respq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect respq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect respq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect respq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect respq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect respq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect respq.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect respq.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect respq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect respq.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect respq.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect respq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect respq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect respq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect respq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect respq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect respq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect respq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect respq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect respq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect respq.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect respq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect respq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect respq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect respq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect respq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect respq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect respq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect respq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect respq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect respq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect respq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect respq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect respq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect respq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect respq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect respq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect respq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect respq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect respq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect respq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect respq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect respq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect respq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect respq.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect respq.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect respq.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect respq.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect respq.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect respq.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect respq.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect respq.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect respq.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect respq.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect respq.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect respq.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect respq.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect respq.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect respq.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect respq.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect respq.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect respq.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect respq.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect respq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect respq.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect respq.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect respq.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect respq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect respq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect respq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect respq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect respq.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect respq.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect respq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect respq.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect respq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect respq.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect respq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect respq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect respq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect respq.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect respq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect respq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect respq.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect respq.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect respq.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect respq.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect respq.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect respq.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect respq.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect respq.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect respq.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect respq.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect respq.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect respq.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect respq.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect respq.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect respq.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect respq.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect respq.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect respq.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect respq.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect respq.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect respq.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect respq.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect respq.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect respq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect respq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect respq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect respq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect respq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect respq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect respq.io.flush, io.exception connect respq.io.enq, resp_arb.io.out connect io.resp.bits, respq.io.deq.bits connect io.resp.valid, respq.io.deq.valid connect respq.io.deq.ready, io.resp.ready node _io_req_0_ready_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _io_req_0_ready_T_1 = eq(cacheable, UInt<1>(0h0)) node _io_req_0_ready_T_2 = and(tag_match[0], _T_11) node _io_req_0_ready_T_3 = mux(idx_match[0], _io_req_0_ready_T_2, pri_rdy) node _io_req_0_ready_T_4 = and(sdq_rdy, _io_req_0_ready_T_3) node _io_req_0_ready_T_5 = mux(_io_req_0_ready_T_1, _T_17, _io_req_0_ready_T_4) node _io_req_0_ready_T_6 = and(_io_req_0_ready_T, _io_req_0_ready_T_5) connect io.req[0].ready, _io_req_0_ready_T_6 node _io_secondary_miss_0_T = and(idx_match[0], way_match[0]) node _io_secondary_miss_0_T_1 = eq(tag_match[0], UInt<1>(0h0)) node _io_secondary_miss_0_T_2 = and(_io_secondary_miss_0_T, _io_secondary_miss_0_T_1) connect io.secondary_miss[0], _io_secondary_miss_0_T_2 node _io_block_hit_0_T = and(idx_match[0], tag_match[0]) connect io.block_hit[0], _io_block_hit_0_T connect io.refill.bits, refill_arb.io.out.bits connect io.refill.valid, refill_arb.io.out.valid connect refill_arb.io.out.ready, io.refill.ready node _free_sdq_T = and(io.replay.ready, io.replay.valid) node _free_sdq_T_1 = eq(io.replay.bits.uop.mem_cmd, UInt<1>(0h1)) node _free_sdq_T_2 = eq(io.replay.bits.uop.mem_cmd, UInt<5>(0h11)) node _free_sdq_T_3 = or(_free_sdq_T_1, _free_sdq_T_2) node _free_sdq_T_4 = eq(io.replay.bits.uop.mem_cmd, UInt<3>(0h7)) node _free_sdq_T_5 = or(_free_sdq_T_3, _free_sdq_T_4) node _free_sdq_T_6 = eq(io.replay.bits.uop.mem_cmd, UInt<3>(0h4)) node _free_sdq_T_7 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0h9)) node _free_sdq_T_8 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0ha)) node _free_sdq_T_9 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hb)) node _free_sdq_T_10 = or(_free_sdq_T_6, _free_sdq_T_7) node _free_sdq_T_11 = or(_free_sdq_T_10, _free_sdq_T_8) node _free_sdq_T_12 = or(_free_sdq_T_11, _free_sdq_T_9) node _free_sdq_T_13 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0h8)) node _free_sdq_T_14 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hc)) node _free_sdq_T_15 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hd)) node _free_sdq_T_16 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0he)) node _free_sdq_T_17 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hf)) node _free_sdq_T_18 = or(_free_sdq_T_13, _free_sdq_T_14) node _free_sdq_T_19 = or(_free_sdq_T_18, _free_sdq_T_15) node _free_sdq_T_20 = or(_free_sdq_T_19, _free_sdq_T_16) node _free_sdq_T_21 = or(_free_sdq_T_20, _free_sdq_T_17) node _free_sdq_T_22 = or(_free_sdq_T_12, _free_sdq_T_21) node _free_sdq_T_23 = or(_free_sdq_T_5, _free_sdq_T_22) node free_sdq = and(_free_sdq_T, _free_sdq_T_23) connect io.replay.bits, replay_arb.io.out.bits connect io.replay.valid, replay_arb.io.out.valid connect replay_arb.io.out.ready, io.replay.ready infer mport io_replay_bits_data_MPORT = sdq[replay_arb.io.out.bits.sdq_id], clock connect io.replay.bits.data, io_replay_bits_data_MPORT node _T_63 = or(io.replay.valid, sdq_enq) when _T_63 : node _sdq_val_T = dshl(UInt<1>(0h1), replay_arb.io.out.bits.sdq_id) node _sdq_val_T_1 = mux(free_sdq, UInt<17>(0h1ffff), UInt<17>(0h0)) node _sdq_val_T_2 = and(_sdq_val_T, _sdq_val_T_1) node _sdq_val_T_3 = not(_sdq_val_T_2) node _sdq_val_T_4 = and(sdq_val, _sdq_val_T_3) node _sdq_val_T_5 = bits(sdq_val, 16, 0) node _sdq_val_T_6 = not(_sdq_val_T_5) node _sdq_val_T_7 = bits(_sdq_val_T_6, 0, 0) node _sdq_val_T_8 = bits(_sdq_val_T_6, 1, 1) node _sdq_val_T_9 = bits(_sdq_val_T_6, 2, 2) node _sdq_val_T_10 = bits(_sdq_val_T_6, 3, 3) node _sdq_val_T_11 = bits(_sdq_val_T_6, 4, 4) node _sdq_val_T_12 = bits(_sdq_val_T_6, 5, 5) node _sdq_val_T_13 = bits(_sdq_val_T_6, 6, 6) node _sdq_val_T_14 = bits(_sdq_val_T_6, 7, 7) node _sdq_val_T_15 = bits(_sdq_val_T_6, 8, 8) node _sdq_val_T_16 = bits(_sdq_val_T_6, 9, 9) node _sdq_val_T_17 = bits(_sdq_val_T_6, 10, 10) node _sdq_val_T_18 = bits(_sdq_val_T_6, 11, 11) node _sdq_val_T_19 = bits(_sdq_val_T_6, 12, 12) node _sdq_val_T_20 = bits(_sdq_val_T_6, 13, 13) node _sdq_val_T_21 = bits(_sdq_val_T_6, 14, 14) node _sdq_val_T_22 = bits(_sdq_val_T_6, 15, 15) node _sdq_val_T_23 = bits(_sdq_val_T_6, 16, 16) node _sdq_val_T_24 = mux(_sdq_val_T_23, UInt<17>(0h10000), UInt<17>(0h0)) node _sdq_val_T_25 = mux(_sdq_val_T_22, UInt<17>(0h8000), _sdq_val_T_24) node _sdq_val_T_26 = mux(_sdq_val_T_21, UInt<17>(0h4000), _sdq_val_T_25) node _sdq_val_T_27 = mux(_sdq_val_T_20, UInt<17>(0h2000), _sdq_val_T_26) node _sdq_val_T_28 = mux(_sdq_val_T_19, UInt<17>(0h1000), _sdq_val_T_27) node _sdq_val_T_29 = mux(_sdq_val_T_18, UInt<17>(0h800), _sdq_val_T_28) node _sdq_val_T_30 = mux(_sdq_val_T_17, UInt<17>(0h400), _sdq_val_T_29) node _sdq_val_T_31 = mux(_sdq_val_T_16, UInt<17>(0h200), _sdq_val_T_30) node _sdq_val_T_32 = mux(_sdq_val_T_15, UInt<17>(0h100), _sdq_val_T_31) node _sdq_val_T_33 = mux(_sdq_val_T_14, UInt<17>(0h80), _sdq_val_T_32) node _sdq_val_T_34 = mux(_sdq_val_T_13, UInt<17>(0h40), _sdq_val_T_33) node _sdq_val_T_35 = mux(_sdq_val_T_12, UInt<17>(0h20), _sdq_val_T_34) node _sdq_val_T_36 = mux(_sdq_val_T_11, UInt<17>(0h10), _sdq_val_T_35) node _sdq_val_T_37 = mux(_sdq_val_T_10, UInt<17>(0h8), _sdq_val_T_36) node _sdq_val_T_38 = mux(_sdq_val_T_9, UInt<17>(0h4), _sdq_val_T_37) node _sdq_val_T_39 = mux(_sdq_val_T_8, UInt<17>(0h2), _sdq_val_T_38) node _sdq_val_T_40 = mux(_sdq_val_T_7, UInt<17>(0h1), _sdq_val_T_39) node _sdq_val_T_41 = mux(sdq_enq, UInt<17>(0h1ffff), UInt<17>(0h0)) node _sdq_val_T_42 = and(_sdq_val_T_40, _sdq_val_T_41) node _sdq_val_T_43 = or(_sdq_val_T_4, _sdq_val_T_42) connect sdq_val, _sdq_val_T_43 reg prefetcher_io_mshr_avail_REG : UInt<1>, clock connect prefetcher_io_mshr_avail_REG, pri_rdy connect prefetcher.io.mshr_avail, prefetcher_io_mshr_avail_REG node _prefetcher_io_req_val_T = or(commit_vals[0], commit_vals[1]) reg prefetcher_io_req_val_REG : UInt<1>, clock connect prefetcher_io_req_val_REG, _prefetcher_io_req_val_T connect prefetcher.io.req_val, prefetcher_io_req_val_REG node _prefetcher_io_req_addr_T = mux(commit_vals[0], commit_addrs[0], UInt<1>(0h0)) node _prefetcher_io_req_addr_T_1 = mux(commit_vals[1], commit_addrs[1], UInt<1>(0h0)) node _prefetcher_io_req_addr_T_2 = or(_prefetcher_io_req_addr_T, _prefetcher_io_req_addr_T_1) wire _prefetcher_io_req_addr_WIRE : UInt<40> connect _prefetcher_io_req_addr_WIRE, _prefetcher_io_req_addr_T_2 reg prefetcher_io_req_addr_REG : UInt, clock connect prefetcher_io_req_addr_REG, _prefetcher_io_req_addr_WIRE connect prefetcher.io.req_addr, prefetcher_io_req_addr_REG wire _prefetcher_io_req_coh_WIRE : { state : UInt<2>} node _prefetcher_io_req_coh_T = mux(commit_vals[0], commit_cohs[0].state, UInt<1>(0h0)) node _prefetcher_io_req_coh_T_1 = mux(commit_vals[1], commit_cohs[1].state, UInt<1>(0h0)) node _prefetcher_io_req_coh_T_2 = or(_prefetcher_io_req_coh_T, _prefetcher_io_req_coh_T_1) wire _prefetcher_io_req_coh_WIRE_1 : UInt<2> connect _prefetcher_io_req_coh_WIRE_1, _prefetcher_io_req_coh_T_2 connect _prefetcher_io_req_coh_WIRE.state, _prefetcher_io_req_coh_WIRE_1 reg prefetcher_io_req_coh_REG : { state : UInt<2>}, clock connect prefetcher_io_req_coh_REG, _prefetcher_io_req_coh_WIRE connect prefetcher.io.req_coh.state, prefetcher_io_req_coh_REG.state	module BoomMSHRFile( // @[mshrs.scala:498:7] input clock, // @[mshrs.scala:498:7] input reset, // @[mshrs.scala:498:7] output io_req_0_ready, // @[mshrs.scala:501:14] input io_req_0_valid, // @[mshrs.scala:501:14] input [31:0] io_req_0_bits_uop_inst, // @[mshrs.scala:501:14] input [31:0] io_req_0_bits_uop_debug_inst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_rvc, // @[mshrs.scala:501:14] input [39:0] io_req_0_bits_uop_debug_pc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_0, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_0, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_4, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_5, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_6, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_7, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_8, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_9, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] input [11:0] io_req_0_bits_uop_br_mask, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_br_tag, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_br_type, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sfb, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_fence, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_fencei, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sfence, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_amo, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_eret, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_rocc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_mov, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_ftq_idx, // @[mshrs.scala:501:14] input io_req_0_bits_uop_edge_inst, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_pc_lob, // @[mshrs.scala:501:14] input io_req_0_bits_uop_taken, // @[mshrs.scala:501:14] input io_req_0_bits_uop_imm_rename, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_imm_sel, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_pimm, // @[mshrs.scala:501:14] input [19:0] io_req_0_bits_uop_imm_packed, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_op1_sel, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_op2_sel, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_rob_idx, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_ldq_idx, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_stq_idx, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_rxq_idx, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_pdst, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs1, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs2, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs3, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_ppred, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs1_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs2_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs3_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_ppred_busy, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_stale_pdst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_exception, // @[mshrs.scala:501:14] input [63:0] io_req_0_bits_uop_exc_cause, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_mem_cmd, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_mem_size, // @[mshrs.scala:501:14] input io_req_0_bits_uop_mem_signed, // @[mshrs.scala:501:14] input io_req_0_bits_uop_uses_ldq, // @[mshrs.scala:501:14] input io_req_0_bits_uop_uses_stq, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_unique, // @[mshrs.scala:501:14] input io_req_0_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_csr_cmd, // @[mshrs.scala:501:14] input io_req_0_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_ldst, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs1, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs2, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs3, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_dst_rtype, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] input io_req_0_bits_uop_frs3_en, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fcn_dw, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_fcn_op, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_val, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_fp_rm, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_typ, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] input [39:0] io_req_0_bits_addr, // @[mshrs.scala:501:14] input [63:0] io_req_0_bits_data, // @[mshrs.scala:501:14] input io_req_0_bits_is_hella, // @[mshrs.scala:501:14] input io_req_0_bits_tag_match, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_old_meta_coh_state, // @[mshrs.scala:501:14] input [19:0] io_req_0_bits_old_meta_tag, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_way_en, // @[mshrs.scala:501:14] input io_req_is_probe_0, // @[mshrs.scala:501:14] input io_resp_ready, // @[mshrs.scala:501:14] output io_resp_valid, // @[mshrs.scala:501:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:501:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:501:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] output [11:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sfence, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_eret, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_rocc, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_mov, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:501:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:501:14] output io_resp_bits_uop_taken, // @[mshrs.scala:501:14] output io_resp_bits_uop_imm_rename, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:501:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:501:14] output io_resp_bits_uop_exception, // @[mshrs.scala:501:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:501:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:501:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:501:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:501:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:501:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:501:14] output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:501:14] output io_resp_bits_is_hella, // @[mshrs.scala:501:14] output io_secondary_miss_0, // @[mshrs.scala:501:14] output io_block_hit_0, // @[mshrs.scala:501:14] input [11:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:501:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:501:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:501:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:501:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_0, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_0, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_4, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_5, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_6, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_7, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_8, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_9, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[mshrs.scala:501:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_br_type, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sfence, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_eret, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_rocc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_mov, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_imm_rename, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_pimm, // @[mshrs.scala:501:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:501:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fcn_dw, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:501:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:501:14] input io_brupdate_b2_taken, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:501:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:501:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:501:14] input io_exception, // @[mshrs.scala:501:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:501:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:501:14] input io_mem_acquire_ready, // @[mshrs.scala:501:14] output io_mem_acquire_valid, // @[mshrs.scala:501:14] output [2:0] io_mem_acquire_bits_opcode, // @[mshrs.scala:501:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:501:14] output [3:0] io_mem_acquire_bits_size, // @[mshrs.scala:501:14] output [1:0] io_mem_acquire_bits_source, // @[mshrs.scala:501:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:501:14] output [7:0] io_mem_acquire_bits_mask, // @[mshrs.scala:501:14] output [63:0] io_mem_acquire_bits_data, // @[mshrs.scala:501:14] output io_mem_grant_ready, // @[mshrs.scala:501:14] input io_mem_grant_valid, // @[mshrs.scala:501:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:501:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:501:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:501:14] input [1:0] io_mem_grant_bits_source, // @[mshrs.scala:501:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:501:14] input io_mem_grant_bits_denied, // @[mshrs.scala:501:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:501:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:501:14] input io_mem_finish_ready, // @[mshrs.scala:501:14] output io_mem_finish_valid, // @[mshrs.scala:501:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:501:14] input io_refill_ready, // @[mshrs.scala:501:14] output io_refill_valid, // @[mshrs.scala:501:14] output [3:0] io_refill_bits_way_en, // @[mshrs.scala:501:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:501:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:501:14] input io_meta_write_ready, // @[mshrs.scala:501:14] output io_meta_write_valid, // @[mshrs.scala:501:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:501:14] output [3:0] io_meta_write_bits_way_en, // @[mshrs.scala:501:14] output [19:0] io_meta_write_bits_tag, // @[mshrs.scala:501:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:501:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:501:14] input io_meta_read_ready, // @[mshrs.scala:501:14] output io_meta_read_valid, // @[mshrs.scala:501:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:501:14] output [3:0] io_meta_read_bits_way_en, // @[mshrs.scala:501:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:501:14] input io_meta_resp_valid, // @[mshrs.scala:501:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:501:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:501:14] input io_replay_ready, // @[mshrs.scala:501:14] output io_replay_valid, // @[mshrs.scala:501:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:501:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:501:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] output [11:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sfence, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_eret, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_rocc, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_mov, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:501:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:501:14] output io_replay_bits_uop_taken, // @[mshrs.scala:501:14] output io_replay_bits_uop_imm_rename, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:501:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:501:14] output io_replay_bits_uop_exception, // @[mshrs.scala:501:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:501:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:501:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:501:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:501:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:501:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:501:14] output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:501:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:501:14] output io_replay_bits_is_hella, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_way_en, // @[mshrs.scala:501:14] input io_prefetch_ready, // @[mshrs.scala:501:14] input io_wb_req_ready, // @[mshrs.scala:501:14] output io_wb_req_valid, // @[mshrs.scala:501:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:501:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:501:14] output [1:0] io_wb_req_bits_source, // @[mshrs.scala:501:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:501:14] output [3:0] io_wb_req_bits_way_en, // @[mshrs.scala:501:14] input io_prober_state_valid, // @[mshrs.scala:501:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:501:14] input io_clear_all, // @[mshrs.scala:501:14] input io_wb_resp, // @[mshrs.scala:501:14] output io_fence_rdy, // @[mshrs.scala:501:14] output io_probe_rdy // @[mshrs.scala:501:14] ); wire io_req_0_ready_0; // @[mshrs.scala:498:7] wire _respq_io_enq_ready; // @[mshrs.scala:720:21] wire _mmios_0_io_req_ready; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_valid; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_resp_bits_uop_inst; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_resp_bits_uop_debug_inst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_rvc; // @[mshrs.scala:693:22] wire [39:0] _mmios_0_io_resp_bits_uop_debug_pc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:693:22] wire [11:0] _mmios_0_io_resp_bits_uop_br_mask; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_br_tag; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_br_type; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sfb; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_fence; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_fencei; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sfence; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_amo; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_eret; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_rocc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_mov; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_edge_inst; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_pc_lob; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_taken; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_imm_rename; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_imm_sel; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_pimm; // @[mshrs.scala:693:22] wire [19:0] _mmios_0_io_resp_bits_uop_imm_packed; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_op1_sel; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_op2_sel; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_rob_idx; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_stq_idx; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_pdst; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs1; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs2; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs3; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_ppred; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_exception; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_resp_bits_uop_exc_cause; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_mem_size; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_mem_signed; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_uses_stq; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_unique; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_ldst; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs1; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs2; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs3; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_frs3_en; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_fcn_op; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_val; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_fp_rm; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_typ; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_resp_bits_data; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_is_hella; // @[mshrs.scala:693:22] wire _mmios_0_io_mem_access_valid; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_mem_access_bits_opcode; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_mem_access_bits_param; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_mem_access_bits_size; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_mem_access_bits_source; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_mem_access_bits_address; // @[mshrs.scala:693:22] wire [7:0] _mmios_0_io_mem_access_bits_mask; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_mem_access_bits_data; // @[mshrs.scala:693:22] wire _mmio_alloc_arb_io_in_0_ready; // @[mshrs.scala:686:30] wire _mshrs_1_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_1_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_1_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_way_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_1_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_1_io_refill_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_1_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_1_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_1_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_1_io_lb_write_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_1_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_1_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_1_io_probe_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_way_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_0_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_0_io_refill_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_0_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_0_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_0_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_0_io_lb_write_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_0_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_0_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_0_io_probe_rdy; // @[mshrs.scala:602:22] wire _refill_arb_io_in_0_ready; // @[mshrs.scala:586:30] wire _refill_arb_io_in_1_ready; // @[mshrs.scala:586:30] wire _resp_arb_io_in_0_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_1_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_2_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_out_valid; // @[mshrs.scala:585:30] wire [31:0] _resp_arb_io_out_bits_uop_inst; // @[mshrs.scala:585:30] wire [31:0] _resp_arb_io_out_bits_uop_debug_inst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_rvc; // @[mshrs.scala:585:30] wire [39:0] _resp_arb_io_out_bits_uop_debug_pc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_0; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_0; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_4; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_5; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_6; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_7; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_8; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_9; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_dis_col_sel; // @[mshrs.scala:585:30] wire [11:0] _resp_arb_io_out_bits_uop_br_mask; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_br_tag; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_br_type; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sfb; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_fence; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_fencei; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sfence; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_amo; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_eret; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sys_pc2epc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_rocc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_mov; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_ftq_idx; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_edge_inst; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_pc_lob; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_taken; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_imm_rename; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_imm_sel; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_pimm; // @[mshrs.scala:585:30] wire [19:0] _resp_arb_io_out_bits_uop_imm_packed; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_op1_sel; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_op2_sel; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_wen; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_toint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fma; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_div; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_vec; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_rob_idx; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_ldq_idx; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_stq_idx; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_rxq_idx; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_pdst; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs1; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs2; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs3; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_ppred; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs1_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs2_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs3_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_ppred_busy; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_stale_pdst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_exception; // @[mshrs.scala:585:30] wire [63:0] _resp_arb_io_out_bits_uop_exc_cause; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_mem_cmd; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_mem_size; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_mem_signed; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_uses_ldq; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_uses_stq; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_unique; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_flush_on_commit; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_csr_cmd; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_ldst_is_rs1; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_ldst; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs1; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs2; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs3; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_dst_rtype; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_lrs1_rtype; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_lrs2_rtype; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_frs3_en; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fcn_dw; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_fcn_op; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_val; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_fp_rm; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_typ; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_pf_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_ae_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_ma_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_bp_debug_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_bp_xcpt_if; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_debug_fsrc; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_debug_tsrc; // @[mshrs.scala:585:30] wire [63:0] _resp_arb_io_out_bits_data; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_is_hella; // @[mshrs.scala:585:30] wire _replay_arb_io_in_0_ready; // @[mshrs.scala:584:30] wire _replay_arb_io_in_1_ready; // @[mshrs.scala:584:30] wire [4:0] _replay_arb_io_out_bits_sdq_id; // @[mshrs.scala:584:30] wire _wb_req_arb_io_in_0_ready; // @[mshrs.scala:583:30] wire _wb_req_arb_io_in_1_ready; // @[mshrs.scala:583:30] wire _meta_read_arb_io_in_0_ready; // @[mshrs.scala:582:30] wire _meta_read_arb_io_in_1_ready; // @[mshrs.scala:582:30] wire _meta_write_arb_io_in_0_ready; // @[mshrs.scala:581:30] wire _meta_write_arb_io_in_1_ready; // @[mshrs.scala:581:30] wire io_req_0_valid_0 = io_req_0_valid; // @[mshrs.scala:498:7] wire [31:0] io_req_0_bits_uop_inst_0 = io_req_0_bits_uop_inst; // @[mshrs.scala:498:7] wire [31:0] io_req_0_bits_uop_debug_inst_0 = io_req_0_bits_uop_debug_inst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_rvc_0 = io_req_0_bits_uop_is_rvc; // @[mshrs.scala:498:7] wire [39:0] io_req_0_bits_uop_debug_pc_0 = io_req_0_bits_uop_debug_pc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_0_0 = io_req_0_bits_uop_iq_type_0; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_1_0 = io_req_0_bits_uop_iq_type_1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_2_0 = io_req_0_bits_uop_iq_type_2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_3_0 = io_req_0_bits_uop_iq_type_3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_0_0 = io_req_0_bits_uop_fu_code_0; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_1_0 = io_req_0_bits_uop_fu_code_1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_2_0 = io_req_0_bits_uop_fu_code_2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_3_0 = io_req_0_bits_uop_fu_code_3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_4_0 = io_req_0_bits_uop_fu_code_4; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_5_0 = io_req_0_bits_uop_fu_code_5; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_6_0 = io_req_0_bits_uop_fu_code_6; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_7_0 = io_req_0_bits_uop_fu_code_7; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_8_0 = io_req_0_bits_uop_fu_code_8; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_9_0 = io_req_0_bits_uop_fu_code_9; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_0 = io_req_0_bits_uop_iw_issued; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_partial_agen_0 = io_req_0_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_partial_dgen_0 = io_req_0_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_iw_p1_speculative_child_0 = io_req_0_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_iw_p2_speculative_child_0 = io_req_0_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p1_bypass_hint_0 = io_req_0_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p2_bypass_hint_0 = io_req_0_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p3_bypass_hint_0 = io_req_0_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_dis_col_sel_0 = io_req_0_bits_uop_dis_col_sel; // @[mshrs.scala:498:7] wire [11:0] io_req_0_bits_uop_br_mask_0 = io_req_0_bits_uop_br_mask; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_br_tag_0 = io_req_0_bits_uop_br_tag; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_br_type_0 = io_req_0_bits_uop_br_type; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sfb_0 = io_req_0_bits_uop_is_sfb; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_fence_0 = io_req_0_bits_uop_is_fence; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_fencei_0 = io_req_0_bits_uop_is_fencei; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sfence_0 = io_req_0_bits_uop_is_sfence; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_amo_0 = io_req_0_bits_uop_is_amo; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_eret_0 = io_req_0_bits_uop_is_eret; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sys_pc2epc_0 = io_req_0_bits_uop_is_sys_pc2epc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_rocc_0 = io_req_0_bits_uop_is_rocc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_mov_0 = io_req_0_bits_uop_is_mov; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_ftq_idx_0 = io_req_0_bits_uop_ftq_idx; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_edge_inst_0 = io_req_0_bits_uop_edge_inst; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_pc_lob_0 = io_req_0_bits_uop_pc_lob; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_taken_0 = io_req_0_bits_uop_taken; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_imm_rename_0 = io_req_0_bits_uop_imm_rename; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_imm_sel_0 = io_req_0_bits_uop_imm_sel; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_pimm_0 = io_req_0_bits_uop_pimm; // @[mshrs.scala:498:7] wire [19:0] io_req_0_bits_uop_imm_packed_0 = io_req_0_bits_uop_imm_packed; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_op1_sel_0 = io_req_0_bits_uop_op1_sel; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_op2_sel_0 = io_req_0_bits_uop_op2_sel; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ldst_0 = io_req_0_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_wen_0 = io_req_0_bits_uop_fp_ctrl_wen; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren1_0 = io_req_0_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren2_0 = io_req_0_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren3_0 = io_req_0_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_swap12_0 = io_req_0_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_swap23_0 = io_req_0_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_ctrl_typeTagIn_0 = io_req_0_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_ctrl_typeTagOut_0 = io_req_0_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fromint_0 = io_req_0_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_toint_0 = io_req_0_bits_uop_fp_ctrl_toint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fastpipe_0 = io_req_0_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fma_0 = io_req_0_bits_uop_fp_ctrl_fma; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_div_0 = io_req_0_bits_uop_fp_ctrl_div; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_sqrt_0 = io_req_0_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_wflags_0 = io_req_0_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_vec_0 = io_req_0_bits_uop_fp_ctrl_vec; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_rob_idx_0 = io_req_0_bits_uop_rob_idx; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_ldq_idx_0 = io_req_0_bits_uop_ldq_idx; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_stq_idx_0 = io_req_0_bits_uop_stq_idx; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_rxq_idx_0 = io_req_0_bits_uop_rxq_idx; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_pdst_0 = io_req_0_bits_uop_pdst; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs1_0 = io_req_0_bits_uop_prs1; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs2_0 = io_req_0_bits_uop_prs2; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs3_0 = io_req_0_bits_uop_prs3; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_ppred_0 = io_req_0_bits_uop_ppred; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs1_busy_0 = io_req_0_bits_uop_prs1_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs2_busy_0 = io_req_0_bits_uop_prs2_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs3_busy_0 = io_req_0_bits_uop_prs3_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_ppred_busy_0 = io_req_0_bits_uop_ppred_busy; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_stale_pdst_0 = io_req_0_bits_uop_stale_pdst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_exception_0 = io_req_0_bits_uop_exception; // @[mshrs.scala:498:7] wire [63:0] io_req_0_bits_uop_exc_cause_0 = io_req_0_bits_uop_exc_cause; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_mem_cmd_0 = io_req_0_bits_uop_mem_cmd; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_mem_size_0 = io_req_0_bits_uop_mem_size; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_mem_signed_0 = io_req_0_bits_uop_mem_signed; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_uses_ldq_0 = io_req_0_bits_uop_uses_ldq; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_uses_stq_0 = io_req_0_bits_uop_uses_stq; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_unique_0 = io_req_0_bits_uop_is_unique; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_flush_on_commit_0 = io_req_0_bits_uop_flush_on_commit; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_csr_cmd_0 = io_req_0_bits_uop_csr_cmd; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_ldst_is_rs1_0 = io_req_0_bits_uop_ldst_is_rs1; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_ldst_0 = io_req_0_bits_uop_ldst; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs1_0 = io_req_0_bits_uop_lrs1; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs2_0 = io_req_0_bits_uop_lrs2; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs3_0 = io_req_0_bits_uop_lrs3; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_dst_rtype_0 = io_req_0_bits_uop_dst_rtype; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_lrs1_rtype_0 = io_req_0_bits_uop_lrs1_rtype; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_lrs2_rtype_0 = io_req_0_bits_uop_lrs2_rtype; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_frs3_en_0 = io_req_0_bits_uop_frs3_en; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fcn_dw_0 = io_req_0_bits_uop_fcn_dw; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_fcn_op_0 = io_req_0_bits_uop_fcn_op; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_val_0 = io_req_0_bits_uop_fp_val; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_fp_rm_0 = io_req_0_bits_uop_fp_rm; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_typ_0 = io_req_0_bits_uop_fp_typ; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_pf_if_0 = io_req_0_bits_uop_xcpt_pf_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_ae_if_0 = io_req_0_bits_uop_xcpt_ae_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_ma_if_0 = io_req_0_bits_uop_xcpt_ma_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_bp_debug_if_0 = io_req_0_bits_uop_bp_debug_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_bp_xcpt_if_0 = io_req_0_bits_uop_bp_xcpt_if; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_debug_fsrc_0 = io_req_0_bits_uop_debug_fsrc; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_debug_tsrc_0 = io_req_0_bits_uop_debug_tsrc; // @[mshrs.scala:498:7] wire [39:0] io_req_0_bits_addr_0 = io_req_0_bits_addr; // @[mshrs.scala:498:7] wire [63:0] io_req_0_bits_data_0 = io_req_0_bits_data; // @[mshrs.scala:498:7] wire io_req_0_bits_is_hella_0 = io_req_0_bits_is_hella; // @[mshrs.scala:498:7] wire io_req_0_bits_tag_match_0 = io_req_0_bits_tag_match; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_old_meta_coh_state_0 = io_req_0_bits_old_meta_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_req_0_bits_old_meta_tag_0 = io_req_0_bits_old_meta_tag; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_way_en_0 = io_req_0_bits_way_en; // @[mshrs.scala:498:7] wire io_req_is_probe_0_0 = io_req_is_probe_0; // @[mshrs.scala:498:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:498:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:498:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:498:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:498:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:498:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[mshrs.scala:498:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[mshrs.scala:498:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:498:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:498:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:498:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:498:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:498:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:498:7] wire io_exception_0 = io_exception; // @[mshrs.scala:498:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:498:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:498:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:498:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:498:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:498:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:498:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:498:7] wire [1:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:498:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:498:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:498:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:498:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:498:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:498:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:498:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:498:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:498:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:498:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:498:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:498:7] wire io_prefetch_ready_0 = io_prefetch_ready; // @[mshrs.scala:498:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:498:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:498:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:498:7] wire io_clear_all_0 = io_clear_all; // @[mshrs.scala:498:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:498:7] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:498:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:498:7] wire _cacheable_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _cacheable_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _mshr_alloc_idx_temp_vec_T_1 = 1'h1; // @[util.scala:352:72] wire _opdata_T = 1'h1; // @[Edges.scala:92:37] wire _opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _io_req_0_ready_T = 1'h1; // @[mshrs.scala:498:7, :727:34] wire [4:0] io_req_0_bits_sdq_id = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_ftq_idx = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_pimm = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_ppred = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_mem_cmd = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_fcn_op = 5'h0; // @[mshrs.scala:498:7] wire [4:0] req_bits_sdq_id = 5'h0; // @[mshrs.scala:536:25] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_valid = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_rvc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_0 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_0 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_4 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_5 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_6 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_7 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_8 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_9 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued_partial_agen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued_partial_dgen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p1_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p2_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p3_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sfb = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_fence = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_fencei = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sfence = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_amo = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_eret = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_rocc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_mov = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_edge_inst = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_taken = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_imm_rename = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ldst = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_wen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_swap12 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_swap23 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fromint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_toint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fma = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_div = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_sqrt = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_wflags = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_vec = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs1_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs2_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs3_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_ppred_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_exception = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_mem_signed = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_uses_ldq = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_uses_stq = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_unique = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_flush_on_commit = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_frs3_en = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fcn_dw = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_val = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_bp_debug_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_is_hella = 1'h0; // @[mshrs.scala:498:7] wire _cacheable_T = 1'h0; // @[Parameters.scala:684:29] wire _cacheable_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _cacheable_T_33 = 1'h0; // @[Parameters.scala:686:26] wire opdata = 1'h0; // @[Edges.scala:92:28] wire opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34] wire _io_mem_acquire_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_3 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_4 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire maskedBeats_0_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1_1 = 1'h0; // @[Arbiter.scala:82:69] wire initBeats_1 = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire [31:0] io_prefetch_bits_uop_inst = 32'h0; // @[mshrs.scala:498:7] wire [31:0] io_prefetch_bits_uop_debug_inst = 32'h0; // @[mshrs.scala:498:7] wire [39:0] io_prefetch_bits_uop_debug_pc = 40'h0; // @[mshrs.scala:498:7] wire [39:0] io_prefetch_bits_addr = 40'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_iw_p1_speculative_child = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_iw_p2_speculative_child = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_dis_col_sel = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_op1_sel = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_rxq_idx = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_mem_size = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_dst_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_typ = 2'h0; // @[mshrs.scala:498:7] wire [1:0] _io_mem_acquire_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [11:0] io_prefetch_bits_uop_br_mask = 12'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_br_tag = 4'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_br_type = 4'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_ldq_idx = 4'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_stq_idx = 4'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_pc_lob = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_rob_idx = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_ldst = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs1 = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs2 = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs3 = 6'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_imm_sel = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_op2_sel = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_csr_cmd = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_fp_rm = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_debug_fsrc = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_debug_tsrc = 3'h0; // @[mshrs.scala:498:7] wire [19:0] io_prefetch_bits_uop_imm_packed = 20'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_pdst = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs1 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs2 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs3 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_stale_pdst = 7'h0; // @[mshrs.scala:498:7] wire [63:0] io_prefetch_bits_uop_exc_cause = 64'h0; // @[mshrs.scala:498:7] wire [63:0] io_prefetch_bits_data = 64'h0; // @[mshrs.scala:498:7] wire [63:0] _io_mem_acquire_bits_T_5 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_6 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_8 = 64'h0; // @[Mux.scala:30:73] wire [8:0] maskedBeats_0 = 9'h0; // @[Arbiter.scala:82:69] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [8:0] _initBeats_T = 9'h0; // @[Arbiter.scala:84:44] wire [8:0] decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire _io_req_0_ready_T_6; // @[mshrs.scala:727:47] wire req_ready = io_req_0_ready_0; // @[mshrs.scala:498:7, :536:25] wire req_valid = io_req_0_valid_0; // @[mshrs.scala:498:7, :536:25] wire [31:0] req_bits_uop_inst = io_req_0_bits_uop_inst_0; // @[mshrs.scala:498:7, :536:25] wire [31:0] req_bits_uop_debug_inst = io_req_0_bits_uop_debug_inst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_rvc = io_req_0_bits_uop_is_rvc_0; // @[mshrs.scala:498:7, :536:25] wire [39:0] req_bits_uop_debug_pc = io_req_0_bits_uop_debug_pc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_0 = io_req_0_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_1 = io_req_0_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_2 = io_req_0_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_3 = io_req_0_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_0 = io_req_0_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_1 = io_req_0_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_2 = io_req_0_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_3 = io_req_0_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_4 = io_req_0_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_5 = io_req_0_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_6 = io_req_0_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_7 = io_req_0_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_8 = io_req_0_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_9 = io_req_0_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued = io_req_0_bits_uop_iw_issued_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued_partial_agen = io_req_0_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued_partial_dgen = io_req_0_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_iw_p1_speculative_child = io_req_0_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_iw_p2_speculative_child = io_req_0_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p1_bypass_hint = io_req_0_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p2_bypass_hint = io_req_0_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p3_bypass_hint = io_req_0_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_dis_col_sel = io_req_0_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7, :536:25] wire [11:0] req_bits_uop_br_mask = io_req_0_bits_uop_br_mask_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_br_tag = io_req_0_bits_uop_br_tag_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_br_type = io_req_0_bits_uop_br_type_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sfb = io_req_0_bits_uop_is_sfb_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_fence = io_req_0_bits_uop_is_fence_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_fencei = io_req_0_bits_uop_is_fencei_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sfence = io_req_0_bits_uop_is_sfence_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_amo = io_req_0_bits_uop_is_amo_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_eret = io_req_0_bits_uop_is_eret_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sys_pc2epc = io_req_0_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_rocc = io_req_0_bits_uop_is_rocc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_mov = io_req_0_bits_uop_is_mov_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_ftq_idx = io_req_0_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_edge_inst = io_req_0_bits_uop_edge_inst_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_pc_lob = io_req_0_bits_uop_pc_lob_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_taken = io_req_0_bits_uop_taken_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_imm_rename = io_req_0_bits_uop_imm_rename_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_imm_sel = io_req_0_bits_uop_imm_sel_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_pimm = io_req_0_bits_uop_pimm_0; // @[mshrs.scala:498:7, :536:25] wire [19:0] req_bits_uop_imm_packed = io_req_0_bits_uop_imm_packed_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_op1_sel = io_req_0_bits_uop_op1_sel_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_op2_sel = io_req_0_bits_uop_op2_sel_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ldst = io_req_0_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_wen = io_req_0_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren1 = io_req_0_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren2 = io_req_0_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren3 = io_req_0_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_swap12 = io_req_0_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_swap23 = io_req_0_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_ctrl_typeTagIn = io_req_0_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_ctrl_typeTagOut = io_req_0_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fromint = io_req_0_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_toint = io_req_0_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fastpipe = io_req_0_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fma = io_req_0_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_div = io_req_0_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_sqrt = io_req_0_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_wflags = io_req_0_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_vec = io_req_0_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_rob_idx = io_req_0_bits_uop_rob_idx_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_ldq_idx = io_req_0_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_stq_idx = io_req_0_bits_uop_stq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_rxq_idx = io_req_0_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_pdst = io_req_0_bits_uop_pdst_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs1 = io_req_0_bits_uop_prs1_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs2 = io_req_0_bits_uop_prs2_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs3 = io_req_0_bits_uop_prs3_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_ppred = io_req_0_bits_uop_ppred_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs1_busy = io_req_0_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs2_busy = io_req_0_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs3_busy = io_req_0_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_ppred_busy = io_req_0_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_stale_pdst = io_req_0_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_exception = io_req_0_bits_uop_exception_0; // @[mshrs.scala:498:7, :536:25] wire [63:0] req_bits_uop_exc_cause = io_req_0_bits_uop_exc_cause_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_mem_cmd = io_req_0_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_mem_size = io_req_0_bits_uop_mem_size_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_mem_signed = io_req_0_bits_uop_mem_signed_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_uses_ldq = io_req_0_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_uses_stq = io_req_0_bits_uop_uses_stq_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_unique = io_req_0_bits_uop_is_unique_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_flush_on_commit = io_req_0_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_csr_cmd = io_req_0_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_ldst_is_rs1 = io_req_0_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_ldst = io_req_0_bits_uop_ldst_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs1 = io_req_0_bits_uop_lrs1_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs2 = io_req_0_bits_uop_lrs2_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs3 = io_req_0_bits_uop_lrs3_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_dst_rtype = io_req_0_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_lrs1_rtype = io_req_0_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_lrs2_rtype = io_req_0_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_frs3_en = io_req_0_bits_uop_frs3_en_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fcn_dw = io_req_0_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_fcn_op = io_req_0_bits_uop_fcn_op_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_val = io_req_0_bits_uop_fp_val_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_fp_rm = io_req_0_bits_uop_fp_rm_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_typ = io_req_0_bits_uop_fp_typ_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_pf_if = io_req_0_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_ae_if = io_req_0_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_ma_if = io_req_0_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_bp_debug_if = io_req_0_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_bp_xcpt_if = io_req_0_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_debug_fsrc = io_req_0_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_debug_tsrc = io_req_0_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7, :536:25] wire [39:0] req_bits_addr = io_req_0_bits_addr_0; // @[mshrs.scala:498:7, :536:25] wire [63:0] req_bits_data = io_req_0_bits_data_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_is_hella = io_req_0_bits_is_hella_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_tag_match = io_req_0_bits_tag_match_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_old_meta_coh_state = io_req_0_bits_old_meta_coh_state_0; // @[mshrs.scala:498:7, :536:25] wire [19:0] req_bits_old_meta_tag = io_req_0_bits_old_meta_tag_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_way_en = io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :536:25] wire _io_secondary_miss_0_T_2; // @[mshrs.scala:729:58] wire _io_block_hit_0_T; // @[mshrs.scala:730:42] wire _io_mem_acquire_valid_T_7; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_acquire_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_WIRE_size; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_WIRE_data; // @[Mux.scala:30:73] wire _io_mem_finish_valid_T_4; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_finish_bits_WIRE_sink; // @[Mux.scala:30:73] wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:498:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:498:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7] wire [11:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:498:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:498:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:498:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:498:7] wire io_resp_valid_0; // @[mshrs.scala:498:7] wire io_secondary_miss_0_0; // @[mshrs.scala:498:7] wire io_block_hit_0_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_acquire_bits_opcode_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:498:7] wire [3:0] io_mem_acquire_bits_size_0; // @[mshrs.scala:498:7] wire [1:0] io_mem_acquire_bits_source_0; // @[mshrs.scala:498:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:498:7] wire [7:0] io_mem_acquire_bits_mask_0; // @[mshrs.scala:498:7] wire [63:0] io_mem_acquire_bits_data_0; // @[mshrs.scala:498:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:498:7] wire io_mem_grant_ready_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:498:7] wire io_mem_finish_valid_0; // @[mshrs.scala:498:7] wire [3:0] io_refill_bits_way_en_0; // @[mshrs.scala:498:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:498:7] wire [63:0] io_refill_bits_data_0; // @[mshrs.scala:498:7] wire io_refill_valid_0; // @[mshrs.scala:498:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:498:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_write_bits_tag_0; // @[mshrs.scala:498:7] wire io_meta_write_valid_0; // @[mshrs.scala:498:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:498:7] wire io_meta_read_valid_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:498:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:498:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7] wire [11:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:498:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:498:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_old_meta_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_replay_bits_old_meta_tag; // @[mshrs.scala:498:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:498:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:498:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:498:7] wire io_replay_bits_tag_match; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_way_en_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_sdq_id; // @[mshrs.scala:498:7] wire io_replay_valid_0; // @[mshrs.scala:498:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:498:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_wb_req_bits_source_0; // @[mshrs.scala:498:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:498:7] wire [3:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:498:7] wire io_wb_req_valid_0; // @[mshrs.scala:498:7] wire io_fence_rdy_0; // @[mshrs.scala:498:7] wire io_probe_rdy_0; // @[mshrs.scala:498:7] wire [39:0] _cacheable_T_1 = req_bits_addr; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_2 = {1'h0, _cacheable_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_3 = _cacheable_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_4 = _cacheable_T_3; // @[Parameters.scala:137:46] wire _cacheable_T_5 = _cacheable_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_6 = {req_bits_addr[39:17], req_bits_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_7 = {1'h0, _cacheable_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_8 = _cacheable_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_9 = _cacheable_T_8; // @[Parameters.scala:137:46] wire _cacheable_T_10 = _cacheable_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_11 = {req_bits_addr[39:28], req_bits_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_12 = {1'h0, _cacheable_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_13 = _cacheable_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_14 = _cacheable_T_13; // @[Parameters.scala:137:46] wire _cacheable_T_15 = _cacheable_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_16 = _cacheable_T_5 \| _cacheable_T_10; // @[Parameters.scala:685:42] wire _cacheable_T_17 = _cacheable_T_16 \| _cacheable_T_15; // @[Parameters.scala:685:42] wire [39:0] _cacheable_T_21 = {req_bits_addr[39:28], req_bits_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_22 = {1'h0, _cacheable_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_23 = _cacheable_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_24 = _cacheable_T_23; // @[Parameters.scala:137:46] wire _cacheable_T_25 = _cacheable_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_26 = {req_bits_addr[39:32], req_bits_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_27 = {1'h0, _cacheable_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_28 = _cacheable_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_29 = _cacheable_T_28; // @[Parameters.scala:137:46] wire _cacheable_T_30 = _cacheable_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_31 = _cacheable_T_25 \| _cacheable_T_30; // @[Parameters.scala:685:42] wire _cacheable_T_32 = _cacheable_T_31; // @[Parameters.scala:684:54, :685:42] wire cacheable = _cacheable_T_32; // @[Parameters.scala:684:54, :686:26] reg [16:0] sdq_val; // @[mshrs.scala:552:29] wire [16:0] _sdq_alloc_id_T = sdq_val; // @[mshrs.scala:552:29, :553:46] wire [16:0] _sdq_val_T_5 = sdq_val; // @[mshrs.scala:552:29, :741:33] wire [16:0] _sdq_alloc_id_T_1 = ~_sdq_alloc_id_T; // @[mshrs.scala:553:{38,46}] wire _sdq_alloc_id_T_2 = _sdq_alloc_id_T_1[0]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_3 = _sdq_alloc_id_T_1[1]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_4 = _sdq_alloc_id_T_1[2]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_5 = _sdq_alloc_id_T_1[3]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_6 = _sdq_alloc_id_T_1[4]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_7 = _sdq_alloc_id_T_1[5]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_8 = _sdq_alloc_id_T_1[6]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_9 = _sdq_alloc_id_T_1[7]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_10 = _sdq_alloc_id_T_1[8]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_11 = _sdq_alloc_id_T_1[9]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_12 = _sdq_alloc_id_T_1[10]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_13 = _sdq_alloc_id_T_1[11]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_14 = _sdq_alloc_id_T_1[12]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_15 = _sdq_alloc_id_T_1[13]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_16 = _sdq_alloc_id_T_1[14]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_17 = _sdq_alloc_id_T_1[15]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_18 = _sdq_alloc_id_T_1[16]; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_19 = _sdq_alloc_id_T_17 ? 5'hF : 5'h10; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_20 = _sdq_alloc_id_T_16 ? 5'hE : _sdq_alloc_id_T_19; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_21 = _sdq_alloc_id_T_15 ? 5'hD : _sdq_alloc_id_T_20; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_22 = _sdq_alloc_id_T_14 ? 5'hC : _sdq_alloc_id_T_21; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_23 = _sdq_alloc_id_T_13 ? 5'hB : _sdq_alloc_id_T_22; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_24 = _sdq_alloc_id_T_12 ? 5'hA : _sdq_alloc_id_T_23; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_25 = _sdq_alloc_id_T_11 ? 5'h9 : _sdq_alloc_id_T_24; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_26 = _sdq_alloc_id_T_10 ? 5'h8 : _sdq_alloc_id_T_25; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_27 = _sdq_alloc_id_T_9 ? 5'h7 : _sdq_alloc_id_T_26; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_28 = _sdq_alloc_id_T_8 ? 5'h6 : _sdq_alloc_id_T_27; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_29 = _sdq_alloc_id_T_7 ? 5'h5 : _sdq_alloc_id_T_28; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_30 = _sdq_alloc_id_T_6 ? 5'h4 : _sdq_alloc_id_T_29; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_31 = _sdq_alloc_id_T_5 ? 5'h3 : _sdq_alloc_id_T_30; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_32 = _sdq_alloc_id_T_4 ? 5'h2 : _sdq_alloc_id_T_31; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_33 = _sdq_alloc_id_T_3 ? 5'h1 : _sdq_alloc_id_T_32; // @[OneHot.scala:48:45] wire [4:0] sdq_alloc_id = _sdq_alloc_id_T_2 ? 5'h0 : _sdq_alloc_id_T_33; // @[OneHot.scala:48:45] wire _sdq_rdy_T = &sdq_val; // @[mshrs.scala:552:29, :554:31] wire sdq_rdy = ~_sdq_rdy_T; // @[mshrs.scala:554:{22,31}] wire _sdq_enq_T = req_ready & req_valid; // @[Decoupled.scala:51:35] wire _sdq_enq_T_1 = _sdq_enq_T & cacheable; // @[Decoupled.scala:51:35] wire _sdq_enq_T_2 = req_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _sdq_enq_T_3 = req_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _sdq_enq_T_4 = _sdq_enq_T_2 \| _sdq_enq_T_3; // @[Consts.scala:90:{32,42,49}] wire _sdq_enq_T_5 = req_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _sdq_enq_T_6 = _sdq_enq_T_4 \| _sdq_enq_T_5; // @[Consts.scala:90:{42,59,66}] wire _sdq_enq_T_7 = req_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _sdq_enq_T_8 = req_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _sdq_enq_T_9 = req_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _sdq_enq_T_10 = req_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _sdq_enq_T_11 = _sdq_enq_T_7 \| _sdq_enq_T_8; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_12 = _sdq_enq_T_11 \| _sdq_enq_T_9; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_13 = _sdq_enq_T_12 \| _sdq_enq_T_10; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_14 = req_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _sdq_enq_T_15 = req_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _sdq_enq_T_16 = req_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _sdq_enq_T_17 = req_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _sdq_enq_T_18 = req_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _sdq_enq_T_19 = _sdq_enq_T_14 \| _sdq_enq_T_15; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_20 = _sdq_enq_T_19 \| _sdq_enq_T_16; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_21 = _sdq_enq_T_20 \| _sdq_enq_T_17; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_22 = _sdq_enq_T_21 \| _sdq_enq_T_18; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_23 = _sdq_enq_T_13 \| _sdq_enq_T_22; // @[package.scala:81:59] wire _sdq_enq_T_24 = _sdq_enq_T_6 \| _sdq_enq_T_23; // @[Consts.scala:87:44, :90:{59,76}] wire sdq_enq = _sdq_enq_T_1 & _sdq_enq_T_24; // @[Consts.scala:90:76] reg [63:0] lb_0_0; // @[mshrs.scala:565:15] reg [63:0] lb_0_1; // @[mshrs.scala:565:15] reg [63:0] lb_0_2; // @[mshrs.scala:565:15] reg [63:0] lb_0_3; // @[mshrs.scala:565:15] reg [63:0] lb_0_4; // @[mshrs.scala:565:15] reg [63:0] lb_0_5; // @[mshrs.scala:565:15] reg [63:0] lb_0_6; // @[mshrs.scala:565:15] reg [63:0] lb_0_7; // @[mshrs.scala:565:15] reg [63:0] lb_1_0; // @[mshrs.scala:565:15] reg [63:0] lb_1_1; // @[mshrs.scala:565:15] reg [63:0] lb_1_2; // @[mshrs.scala:565:15] reg [63:0] lb_1_3; // @[mshrs.scala:565:15] reg [63:0] lb_1_4; // @[mshrs.scala:565:15] reg [63:0] lb_1_5; // @[mshrs.scala:565:15] reg [63:0] lb_1_6; // @[mshrs.scala:565:15] reg [63:0] lb_1_7; // @[mshrs.scala:565:15] wire _idx_matches_0_0_T_2; // @[mshrs.scala:606:46] wire _idx_matches_0_1_T_2; // @[mshrs.scala:606:46] wire idx_matches_0_0; // @[mshrs.scala:571:25] wire idx_matches_0_1; // @[mshrs.scala:571:25] wire _tag_matches_0_0_T_2; // @[mshrs.scala:607:46] wire _tag_matches_0_1_T_2; // @[mshrs.scala:607:46] wire tag_matches_0_0; // @[mshrs.scala:572:25] wire tag_matches_0_1; // @[mshrs.scala:572:25] wire _way_matches_0_0_T_1; // @[mshrs.scala:608:46] wire _way_matches_0_1_T_1; // @[mshrs.scala:608:46] wire way_matches_0_0; // @[mshrs.scala:573:25] wire way_matches_0_1; // @[mshrs.scala:573:25] wire _tag_match_T = idx_matches_0_0 & tag_matches_0_0; // @[Mux.scala:30:73] wire _tag_match_T_1 = idx_matches_0_1 & tag_matches_0_1; // @[Mux.scala:30:73] wire _tag_match_T_2 = _tag_match_T \| _tag_match_T_1; // @[Mux.scala:30:73] wire _tag_match_WIRE = _tag_match_T_2; // @[Mux.scala:30:73] wire tag_match_0 = _tag_match_WIRE; // @[Mux.scala:30:73] wire _idx_match_T = idx_matches_0_0 \| idx_matches_0_1; // @[mshrs.scala:571:25, :576:58] wire idx_match_0 = _idx_match_T; // @[mshrs.scala:566:49, :576:58] wire _way_match_T = idx_matches_0_0 & way_matches_0_0; // @[Mux.scala:30:73] wire _way_match_T_1 = idx_matches_0_1 & way_matches_0_1; // @[Mux.scala:30:73] wire _way_match_T_2 = _way_match_T \| _way_match_T_1; // @[Mux.scala:30:73] wire _way_match_WIRE = _way_match_T_2; // @[Mux.scala:30:73] wire way_match_0 = _way_match_WIRE; // @[Mux.scala:30:73] wire [19:0] wb_tag_list_0; // @[mshrs.scala:579:25] wire [19:0] wb_tag_list_1; // @[mshrs.scala:579:25] wire commit_vals_0; // @[mshrs.scala:588:28] wire commit_vals_1; // @[mshrs.scala:588:28] wire [39:0] commit_addrs_0; // @[mshrs.scala:589:28] wire [39:0] commit_addrs_1; // @[mshrs.scala:589:28] wire [1:0] commit_cohs_0_state; // @[mshrs.scala:590:28] wire [1:0] commit_cohs_1_state; // @[mshrs.scala:590:28] wire mshr_alloc_idx; // @[mshrs.scala:598:28] wire _mshr_io_req_pri_val_T_2 = mshr_alloc_idx; // @[mshrs.scala:598:28, :614:34] wire pri_rdy; // @[mshrs.scala:599:25] wire _GEN = req_valid & sdq_rdy; // @[mshrs.scala:536:25, :554:22, :600:27] wire _pri_val_T; // @[mshrs.scala:600:27] assign _pri_val_T = _GEN; // @[mshrs.scala:600:27] wire _mshr_io_req_sec_val_T; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T = _GEN; // @[mshrs.scala:600:27, :619:39] wire _mshr_io_req_sec_val_T_4; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T_4 = _GEN; // @[mshrs.scala:600:27, :619:39] wire _pri_val_T_1 = _pri_val_T & cacheable; // @[Parameters.scala:686:26] wire _pri_val_T_2 = ~idx_match_0; // @[mshrs.scala:566:49, :600:54] wire pri_val = _pri_val_T_1 & _pri_val_T_2; // @[mshrs.scala:600:{38,51,54}] wire [5:0] _idx_matches_0_0_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire [5:0] _idx_matches_0_1_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire _idx_matches_0_0_T_1 = _mshrs_0_io_idx_bits == _idx_matches_0_0_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_0_T_2 = _mshrs_0_io_idx_valid & _idx_matches_0_0_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_0 = _idx_matches_0_0_T_2; // @[mshrs.scala:571:25, :606:46] wire [27:0] _tag_matches_0_0_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire [27:0] _tag_matches_0_1_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire _tag_matches_0_0_T_1 = _mshrs_0_io_tag_bits == _tag_matches_0_0_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_0_T_2 = _mshrs_0_io_tag_valid & _tag_matches_0_0_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_0 = _tag_matches_0_0_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_0_T = _mshrs_0_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_0_T_1 = _mshrs_0_io_way_valid & _way_matches_0_0_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_0 = _way_matches_0_0_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T = ~mshr_alloc_idx; // @[mshrs.scala:598:28, :614:34] wire _mshr_io_req_pri_val_T_1 = _mshr_io_req_pri_val_T & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] wire _mshr_io_req_sec_val_T_1 = _mshr_io_req_sec_val_T & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_2 = _mshr_io_req_sec_val_T_1 & idx_matches_0_0; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_3 = _mshr_io_req_sec_val_T_2 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_1 = io_clear_all_0 & _mshr_io_clear_prefetch_T; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_2 = req_valid & idx_matches_0_0; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_3 = _mshr_io_clear_prefetch_T_2 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_4 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_5 = _mshr_io_clear_prefetch_T_3 & _mshr_io_clear_prefetch_T_4; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_6 = _mshr_io_clear_prefetch_T_1 \| _mshr_io_clear_prefetch_T_5; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_7 = io_req_is_probe_0_0 & idx_matches_0_0; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_8 = _mshr_io_clear_prefetch_T_6 \| _mshr_io_clear_prefetch_T_7; // @[mshrs.scala:626:60, :627:82, :628:21] wire [7:0][63:0] _GEN_0 = {{lb_0_7}, {lb_0_6}, {lb_0_5}, {lb_0_4}, {lb_0_3}, {lb_0_2}, {lb_0_1}, {lb_0_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_1 = io_mem_grant_bits_source_0 == 2'h0; // @[mshrs.scala:498:7, :656:36] wire _idx_matches_0_1_T_1 = _mshrs_1_io_idx_bits == _idx_matches_0_1_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_1_T_2 = _mshrs_1_io_idx_valid & _idx_matches_0_1_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_1 = _idx_matches_0_1_T_2; // @[mshrs.scala:571:25, :606:46] wire _tag_matches_0_1_T_1 = _mshrs_1_io_tag_bits == _tag_matches_0_1_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_1_T_2 = _mshrs_1_io_tag_valid & _tag_matches_0_1_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_1 = _tag_matches_0_1_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_1_T = _mshrs_1_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_1_T_1 = _mshrs_1_io_way_valid & _way_matches_0_1_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_1 = _way_matches_0_1_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T_3 = _mshr_io_req_pri_val_T_2 & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] assign pri_rdy = mshr_alloc_idx ? _mshrs_1_io_req_pri_rdy : ~mshr_alloc_idx & _mshrs_0_io_req_pri_rdy; // @[mshrs.scala:598:28, :599:25, :602:22, :614:34, :615:35, :616:15] wire _mshr_io_req_sec_val_T_5 = _mshr_io_req_sec_val_T_4 & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_6 = _mshr_io_req_sec_val_T_5 & idx_matches_0_1; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_7 = _mshr_io_req_sec_val_T_6 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_9 = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_10 = io_clear_all_0 & _mshr_io_clear_prefetch_T_9; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_11 = req_valid & idx_matches_0_1; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_12 = _mshr_io_clear_prefetch_T_11 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_13 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_14 = _mshr_io_clear_prefetch_T_12 & _mshr_io_clear_prefetch_T_13; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_15 = _mshr_io_clear_prefetch_T_10 \| _mshr_io_clear_prefetch_T_14; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_16 = io_req_is_probe_0_0 & idx_matches_0_1; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_17 = _mshr_io_clear_prefetch_T_15 \| _mshr_io_clear_prefetch_T_16; // @[mshrs.scala:626:60, :627:82, :628:21] wire [7:0][63:0] _GEN_1 = {{lb_1_7}, {lb_1_6}, {lb_1_5}, {lb_1_4}, {lb_1_3}, {lb_1_2}, {lb_1_1}, {lb_1_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_9 = io_mem_grant_bits_source_0 == 2'h1; // @[mshrs.scala:498:7, :656:36] assign io_probe_rdy_0 = ~(~_mshrs_1_io_probe_rdy & idx_matches_0_1 & io_req_is_probe_0_0 \| ~_mshrs_0_io_probe_rdy & idx_matches_0_0 & io_req_is_probe_0_0); // @[mshrs.scala:498:7, :571:25, :595:16, :602:22, :667:{13,32,53,76}, :668:22] reg mshr_head; // @[mshrs.scala:676:31] wire _mshr_alloc_idx_temp_vec_T = ~mshr_head; // @[util.scala:352:72] wire mshr_alloc_idx_temp_vec_0 = _mshrs_0_io_req_pri_rdy & _mshr_alloc_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire mshr_alloc_idx_temp_vec_1; // @[util.scala:352:65] wire [1:0] _mshr_alloc_idx_idx_T = {1'h1, ~_mshrs_0_io_req_pri_rdy}; // @[Mux.scala:50:70] wire [1:0] _mshr_alloc_idx_idx_T_1 = mshr_alloc_idx_temp_vec_1 ? 2'h1 : _mshr_alloc_idx_idx_T; // @[Mux.scala:50:70] wire [1:0] mshr_alloc_idx_idx = mshr_alloc_idx_temp_vec_0 ? 2'h0 : _mshr_alloc_idx_idx_T_1; // @[Mux.scala:50:70] wire _mshr_alloc_idx_T = mshr_alloc_idx_idx[0]; // @[Mux.scala:50:70] reg mshr_alloc_idx_REG; // @[mshrs.scala:677:31] assign mshr_alloc_idx = mshr_alloc_idx_REG; // @[mshrs.scala:598:28, :677:31] wire [1:0] _mshr_head_T = {1'h0, mshr_head} + 2'h1; // @[util.scala:211:14] wire _mshr_head_T_1 = _mshr_head_T[0]; // @[util.scala:211:14] wire _mshr_head_T_2 = _mshr_head_T_1; // @[util.scala:211:{14,20}] wire _mshr_io_mem_ack_valid_T = &io_mem_grant_bits_source_0; // @[mshrs.scala:498:7, :703:77] wire _mshr_io_mem_ack_valid_T_1 = io_mem_grant_valid_0 & _mshr_io_mem_ack_valid_T; // @[mshrs.scala:498:7, :703:{49,77}] assign io_mem_grant_ready_0 = (&io_mem_grant_bits_source_0) \| (_T_9 ? _mshrs_1_io_mem_grant_ready : _T_1 & _mshrs_0_io_mem_grant_ready); // @[mshrs.scala:498:7, :596:22, :602:22, :656:{36,45}, :657:25, :703:77, :704:46, :705:26] assign io_fence_rdy_0 = ~(~_mmios_0_io_req_ready \| ~_mshrs_1_io_req_pri_rdy \| ~_mshrs_0_io_req_pri_rdy); // @[mshrs.scala:498:7, :594:16, :602:22, :663:{11,33}, :664:20, :693:22, :709:{11,31}, :710:20] wire _mmio_alloc_arb_io_out_ready_T = ~cacheable; // @[Parameters.scala:686:26] wire _mmio_alloc_arb_io_out_ready_T_1 = req_valid & _mmio_alloc_arb_io_out_ready_T; // @[mshrs.scala:536:25, :715:{44,47}] wire [26:0] _decode_T_6 = 27'hFFF << _mmios_0_io_mem_access_bits_size; // @[package.scala:243:71] wire [11:0] _decode_T_7 = _decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _decode_T_8 = ~_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] decode_2 = _decode_T_8[11:3]; // @[package.scala:243:46] wire _opdata_T_2 = _mmios_0_io_mem_access_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata_2 = ~_opdata_T_2; // @[Edges.scala:92:{28,37}] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & io_mem_acquire_ready_0; // @[Arbiter.scala:61:28, :62:24] wire [1:0] readys_hi = {_mmios_0_io_mem_access_valid, _mshrs_1_io_mem_acquire_valid}; // @[Arbiter.scala:68:51] wire [2:0] _readys_T = {readys_hi, _mshrs_0_io_mem_acquire_valid}; // @[Arbiter.scala:68:51] wire [3:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [2:0] _readys_T_2 = _readys_T_1[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_3 = _readys_T \| _readys_T_2; // @[package.scala:253:{43,53}] wire [4:0] _readys_T_4 = {_readys_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [2:0] _readys_T_5 = _readys_T_4[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_6 = _readys_T_3 \| _readys_T_5; // @[package.scala:253:{43,53}] wire [2:0] _readys_T_7 = _readys_T_6; // @[package.scala:253:43, :254:17] wire [3:0] _readys_T_8 = {_readys_T_7, 1'h0}; // @[package.scala:254:17] wire [2:0] _readys_T_9 = _readys_T_8[2:0]; // @[Arbiter.scala:16:{78,83}] wire [2:0] _readys_T_10 = ~_readys_T_9; // @[Arbiter.scala:16:{61,83}] wire _readys_T_11 = _readys_T_10[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_11; // @[Arbiter.scala:68:{27,76}] wire _readys_T_12 = _readys_T_10[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_12; // @[Arbiter.scala:68:{27,76}] wire _readys_T_13 = _readys_T_10[2]; // @[Arbiter.scala:16:61, :68:76] wire readys_2 = _readys_T_13; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & _mshrs_0_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & _mshrs_1_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire _winner_T_2 = readys_2 & _mmios_0_io_mem_access_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_2 \| winner_2; // @[Arbiter.scala:71:27, :76:48] wire _io_mem_acquire_valid_T = _mshrs_0_io_mem_acquire_valid \| _mshrs_1_io_mem_acquire_valid; // @[Arbiter.scala:79:31, :96:46] wire [8:0] maskedBeats_2 = winner_2 & opdata_2 ? decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [8:0] initBeats = maskedBeats_2; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = io_mem_acquire_ready_0 & io_mem_acquire_valid_0; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52] wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] reg state_2; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire _mshrs_0_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_0; // @[Arbiter.scala:92:24, :94:31] wire _mshrs_1_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_1; // @[Arbiter.scala:92:24, :94:31] wire _mmios_0_io_mem_access_ready_T = io_mem_acquire_ready_0 & allowed_2; // @[Arbiter.scala:92:24, :94:31] wire _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T \| _mmios_0_io_mem_access_valid; // @[Arbiter.scala:96:46] wire _io_mem_acquire_valid_T_2 = state_0 & _mshrs_0_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_3 = state_1 & _mshrs_1_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_4 = state_2 & _mmios_0_io_mem_access_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_5 = _io_mem_acquire_valid_T_2 \| _io_mem_acquire_valid_T_3; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_6 = _io_mem_acquire_valid_T_5 \| _io_mem_acquire_valid_T_4; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_WIRE = _io_mem_acquire_valid_T_6; // @[Mux.scala:30:73] assign _io_mem_acquire_valid_T_7 = idle ? _io_mem_acquire_valid_T_1 : _io_mem_acquire_valid_WIRE; // @[Mux.scala:30:73] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_7; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_acquire_bits_WIRE_10; // @[Mux.scala:30:73] assign io_mem_acquire_bits_opcode_0 = _io_mem_acquire_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_9; // @[Mux.scala:30:73] assign io_mem_acquire_bits_param_0 = _io_mem_acquire_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_WIRE_8; // @[Mux.scala:30:73] assign io_mem_acquire_bits_size_0 = _io_mem_acquire_bits_WIRE_size; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_WIRE_7; // @[Mux.scala:30:73] assign io_mem_acquire_bits_source_0 = _io_mem_acquire_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_WIRE_6; // @[Mux.scala:30:73] assign io_mem_acquire_bits_address_0 = _io_mem_acquire_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_WIRE_3; // @[Mux.scala:30:73] assign io_mem_acquire_bits_mask_0 = _io_mem_acquire_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_WIRE_2; // @[Mux.scala:30:73] assign io_mem_acquire_bits_data_0 = _io_mem_acquire_bits_WIRE_data; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_7 = muxState_2 ? _mmios_0_io_mem_access_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_9 = _io_mem_acquire_bits_T_7; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_2 = _io_mem_acquire_bits_T_9; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_data = _io_mem_acquire_bits_WIRE_2; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_10 = {8{muxState_0}}; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_11 = {8{muxState_1}}; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_12 = muxState_2 ? _mmios_0_io_mem_access_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_13 = _io_mem_acquire_bits_T_10 \| _io_mem_acquire_bits_T_11; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_14 = _io_mem_acquire_bits_T_13 \| _io_mem_acquire_bits_T_12; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_3 = _io_mem_acquire_bits_T_14; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_mask = _io_mem_acquire_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_15 = muxState_0 ? _mshrs_0_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_16 = muxState_1 ? _mshrs_1_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_17 = muxState_2 ? _mmios_0_io_mem_access_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_18 = _io_mem_acquire_bits_T_15 \| _io_mem_acquire_bits_T_16; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_19 = _io_mem_acquire_bits_T_18 \| _io_mem_acquire_bits_T_17; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_6 = _io_mem_acquire_bits_T_19; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_address = _io_mem_acquire_bits_WIRE_6; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_21 = {1'h0, muxState_1}; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_23 = _io_mem_acquire_bits_T_21; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_22 = muxState_2 ? _mmios_0_io_mem_access_bits_source : 2'h0; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_24 = _io_mem_acquire_bits_T_23 \| _io_mem_acquire_bits_T_22; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_7 = _io_mem_acquire_bits_T_24; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_source = _io_mem_acquire_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_25 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_26 = muxState_1 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_27 = muxState_2 ? _mmios_0_io_mem_access_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_28 = _io_mem_acquire_bits_T_25 \| _io_mem_acquire_bits_T_26; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_29 = _io_mem_acquire_bits_T_28 \| _io_mem_acquire_bits_T_27; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_8 = _io_mem_acquire_bits_T_29; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_size = _io_mem_acquire_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_30 = muxState_0 ? _mshrs_0_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_31 = muxState_1 ? _mshrs_1_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_32 = muxState_2 ? _mmios_0_io_mem_access_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_33 = _io_mem_acquire_bits_T_30 \| _io_mem_acquire_bits_T_31; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_34 = _io_mem_acquire_bits_T_33 \| _io_mem_acquire_bits_T_32; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_9 = _io_mem_acquire_bits_T_34; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_param = _io_mem_acquire_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_35 = muxState_0 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_36 = muxState_1 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_37 = muxState_2 ? _mmios_0_io_mem_access_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_38 = _io_mem_acquire_bits_T_35 \| _io_mem_acquire_bits_T_36; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_39 = _io_mem_acquire_bits_T_38 \| _io_mem_acquire_bits_T_37; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_10 = _io_mem_acquire_bits_T_39; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_opcode = _io_mem_acquire_bits_WIRE_10; // @[Mux.scala:30:73] reg beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = ~beatsLeft_1; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & io_mem_finish_ready_0; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T_14 = {_mshrs_1_io_mem_finish_valid, _mshrs_0_io_mem_finish_valid}; // @[Arbiter.scala:68:51] wire [2:0] _readys_T_15 = {_readys_T_14, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_16 = _readys_T_15[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_17 = _readys_T_14 \| _readys_T_16; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_18 = _readys_T_17; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_19 = {_readys_T_18, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_20 = _readys_T_19[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_21 = ~_readys_T_20; // @[Arbiter.scala:16:{61,83}] wire _readys_T_22 = _readys_T_21[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_0 = _readys_T_22; // @[Arbiter.scala:68:{27,76}] wire _readys_T_23 = _readys_T_21[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_1 = _readys_T_23; // @[Arbiter.scala:68:{27,76}] wire _winner_T_3 = readys_1_0 & _mshrs_0_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_0 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_1_1 & _mshrs_1_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_1 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_1_1 \| winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _io_mem_finish_valid_T = _mshrs_0_io_mem_finish_valid \| _mshrs_1_io_mem_finish_valid; // @[Arbiter.scala:79:31, :96:46]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_181 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_181( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_111 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_111( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_39 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_47 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_39( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_47 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueue_11 : output io : { flip enq_clock : Clock, flip enq_reset : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip deq_clock : Clock, flip deq_reset : UInt<1>, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}} inst source of AsyncQueueSource_Phit_11 connect source.clock, io.enq_clock connect source.reset, io.enq_reset inst sink of AsyncQueueSink_Phit_11 connect sink.clock, io.deq_clock connect sink.reset, io.deq_reset connect source.io.enq, io.enq connect io.deq.bits, sink.io.deq.bits connect io.deq.valid, sink.io.deq.valid connect sink.io.deq.ready, io.deq.ready connect sink.io.async, source.io.async	module AsyncQueue_11( // @[AsyncQueue.scala:226:7] input io_enq_clock, // @[AsyncQueue.scala:227:14] input io_enq_reset, // @[AsyncQueue.scala:227:14] output io_enq_ready, // @[AsyncQueue.scala:227:14] input io_enq_valid, // @[AsyncQueue.scala:227:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14] input io_deq_clock, // @[AsyncQueue.scala:227:14] input io_deq_reset, // @[AsyncQueue.scala:227:14] input io_deq_ready, // @[AsyncQueue.scala:227:14] output io_deq_valid, // @[AsyncQueue.scala:227:14] output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14] ); wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70] wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70] wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70] wire io_enq_clock_0 = io_enq_clock; // @[AsyncQueue.scala:226:7] wire io_enq_reset_0 = io_enq_reset; // @[AsyncQueue.scala:226:7] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:226:7] wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:226:7] wire io_deq_clock_0 = io_deq_clock; // @[AsyncQueue.scala:226:7] wire io_deq_reset_0 = io_deq_reset; // @[AsyncQueue.scala:226:7] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:226:7] wire io_enq_ready_0; // @[AsyncQueue.scala:226:7] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7] wire io_deq_valid_0; // @[AsyncQueue.scala:226:7] AsyncQueueSource_Phit_11 source ( // @[AsyncQueue.scala:228:70] .clock (io_enq_clock_0), // @[AsyncQueue.scala:226:7] .reset (io_enq_reset_0), // @[AsyncQueue.scala:226:7] .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[AsyncQueue.scala:226:7] .io_enq_bits_phit (io_enq_bits_phit_0), // @[AsyncQueue.scala:226:7] .io_async_mem_0_phit (_source_io_async_mem_0_phit), .io_async_mem_1_phit (_source_io_async_mem_1_phit), .io_async_mem_2_phit (_source_io_async_mem_2_phit), .io_async_mem_3_phit (_source_io_async_mem_3_phit), .io_async_mem_4_phit (_source_io_async_mem_4_phit), .io_async_mem_5_phit (_source_io_async_mem_5_phit), .io_async_mem_6_phit (_source_io_async_mem_6_phit), .io_async_mem_7_phit (_source_io_async_mem_7_phit), .io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70] .io_async_widx (_source_io_async_widx), .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70] .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70] ); // @[AsyncQueue.scala:228:70] AsyncQueueSink_Phit_11 sink ( // @[AsyncQueue.scala:229:70] .clock (io_deq_clock_0), // @[AsyncQueue.scala:226:7] .reset (io_deq_reset_0), // @[AsyncQueue.scala:226:7] .io_deq_ready (io_deq_ready_0), // @[AsyncQueue.scala:226:7] .io_deq_valid (io_deq_valid_0), .io_deq_bits_phit (io_deq_bits_phit_0), .io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70] .io_async_ridx (_sink_io_async_ridx), .io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70] .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70] .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70] .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) ); // @[AsyncQueue.scala:229:70] assign io_enq_ready = io_enq_ready_0; // @[AsyncQueue.scala:226:7] assign io_deq_valid = io_deq_valid_0; // @[AsyncQueue.scala:226:7] assign io_deq_bits_phit = io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _T_1085 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1086 = orr(a_set_wo_ready) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) node _T_1088 = or(_T_1085, _T_1087) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_44 node _T_1092 = orr(inflight) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) node _T_1094 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1095 = or(_T_1093, _T_1094) node _T_1096 = lt(watchdog, plusarg_reader.out) node _T_1097 = or(_T_1095, _T_1096) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1101 = and(io.in.a.ready, io.in.a.valid) node _T_1102 = and(io.in.d.ready, io.in.d.valid) node _T_1103 = or(_T_1101, _T_1102) when _T_1103 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1104 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1105 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1106 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = and(_T_1104, _T_1107) when _T_1108 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1109 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1110 = and(_T_1109, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1111 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1112 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1113 = and(_T_1111, _T_1112) node _T_1114 = and(_T_1110, _T_1113) when _T_1114 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1115 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1116 = bits(_T_1115, 0, 0) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1124 = and(io.in.d.ready, io.in.d.valid) node _T_1125 = and(_T_1124, d_first_2) node _T_1126 = and(_T_1125, UInt<1>(0h1)) node _T_1127 = and(_T_1126, d_release_ack_1) when _T_1127 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1128 = and(io.in.d.valid, d_first_2) node _T_1129 = and(_T_1128, UInt<1>(0h1)) node _T_1130 = and(_T_1129, d_release_ack_1) when _T_1130 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1131 = dshr(inflight_1, io.in.d.bits.source) node _T_1132 = bits(_T_1131, 0, 0) node _T_1133 = or(_T_1132, same_cycle_resp_1) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1137 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_109 else : node _T_1141 = eq(io.in.d.bits.size, c_size_lookup) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_110 node _T_1145 = and(io.in.d.valid, d_first_2) node _T_1146 = and(_T_1145, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1147 = and(_T_1146, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1148 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = and(_T_1149, d_release_ack_1) node _T_1151 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1152 = and(_T_1150, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1154 = or(_T_1153, _WIRE_27.ready) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_111 node _T_1158 = orr(c_set_wo_ready) when _T_1158 : node _T_1159 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_45 node _T_1163 = orr(inflight_1) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) node _T_1165 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = lt(watchdog_1, plusarg_reader_1.out) node _T_1168 = or(_T_1166, _T_1167) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1172 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1173 = and(io.in.d.ready, io.in.d.valid) node _T_1174 = or(_T_1172, _T_1173) when _T_1174 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_188 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_444 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_188( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_444 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_46 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_59 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_46( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_59 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_62 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_890 = orr(a_set_wo_ready) node _T_891 = eq(_T_890, UInt<1>(0h0)) node _T_892 = or(_T_889, _T_891) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_892, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_125 node _T_896 = orr(inflight) node _T_897 = eq(_T_896, UInt<1>(0h0)) node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_899 = or(_T_897, _T_898) node _T_900 = lt(watchdog, plusarg_reader.out) node _T_901 = or(_T_899, _T_900) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_901, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_905 = and(io.in.a.ready, io.in.a.valid) node _T_906 = and(io.in.d.ready, io.in.d.valid) node _T_907 = or(_T_905, _T_906) when _T_907 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_908 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_911 = and(_T_909, _T_910) node _T_912 = and(_T_908, _T_911) when _T_912 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_914 = and(_T_913, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_917 = and(_T_915, _T_916) node _T_918 = and(_T_914, _T_917) when _T_918 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_919 = dshr(inflight_1, _WIRE_15.bits.source) node _T_920 = bits(_T_919, 0, 0) node _T_921 = eq(_T_920, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_921, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_928 = and(io.in.d.ready, io.in.d.valid) node _T_929 = and(_T_928, d_first_2) node _T_930 = and(_T_929, UInt<1>(0h1)) node _T_931 = and(_T_930, d_release_ack_1) when _T_931 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_932 = and(io.in.d.valid, d_first_2) node _T_933 = and(_T_932, UInt<1>(0h1)) node _T_934 = and(_T_933, d_release_ack_1) when _T_934 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_935 = dshr(inflight_1, io.in.d.bits.source) node _T_936 = bits(_T_935, 0, 0) node _T_937 = or(_T_936, same_cycle_resp_1) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_937, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_941, UInt<1>(0h1), "") : assert_109 else : node _T_945 = eq(io.in.d.bits.size, c_size_lookup) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_945, UInt<1>(0h1), "") : assert_110 node _T_949 = and(io.in.d.valid, d_first_2) node _T_950 = and(_T_949, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_951 = and(_T_950, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_953 = and(_T_951, _T_952) node _T_954 = and(_T_953, d_release_ack_1) node _T_955 = eq(c_probe_ack, UInt<1>(0h0)) node _T_956 = and(_T_954, _T_955) when _T_956 : node _T_957 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_958 = or(_T_957, _WIRE_23.ready) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_958, UInt<1>(0h1), "") : assert_111 node _T_962 = orr(c_set_wo_ready) when _T_962 : node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_963, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_126 node _T_967 = orr(inflight_1) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_970 = or(_T_968, _T_969) node _T_971 = lt(watchdog_1, plusarg_reader_1.out) node _T_972 = or(_T_970, _T_971) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_972, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_977 = and(io.in.d.ready, io.in.d.valid) node _T_978 = or(_T_976, _T_977) when _T_978 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_62( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_905 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_905; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_905; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_978 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_978; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_905 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_978 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_949 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_949 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_931 = _T_978 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_931 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_931 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_931 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_77 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_77( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_pbus_to_bootaddressreg : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_BootAddrReg connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready extmodule plusarg_reader_24 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_25 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLInterconnectCoupler_pbus_to_bootaddressreg( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [12:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [12:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_BootAddrReg fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_138 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_138( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_84 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_85 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14] wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27] wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25] wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28] wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :673:46, :674:74, :678:{25,70}] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_2; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :783:46, :788:{25,70}] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module BoomFrontend_1 : input clock : Clock input reset : Reset output auto : { icache_master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip reset_vector_sink_in : UInt<32>} output io : { flip cpu : { flip fetchpacket : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[3]}}, flip get_pc : { flip ftq_idx : UInt<5>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}[2], debug_ftq_idx : UInt<5>[3], flip debug_fetch_pc : UInt<40>[3], status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], mcontext : UInt<0>, scontext : UInt<0>, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, redirect_flush : UInt<1>, redirect_val : UInt<1>, redirect_pc : UInt, redirect_ftq_idx : UInt, redirect_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, commit : { valid : UInt<1>, bits : UInt<32>}, flush_icache : UInt<1>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}} inst icache of ICache_3 connect icache.clock, clock connect icache.reset, reset wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn connect resetVectorSinkNodeIn, auto.reset_vector_sink_in connect icache.auto.master_out.d, auto.icache_master_out.d connect auto.icache_master_out.a.bits, icache.auto.master_out.a.bits connect auto.icache_master_out.a.valid, icache.auto.master_out.a.valid connect icache.auto.master_out.a.ready, auto.icache_master_out.a.ready inst bpd of BranchPredictor_1 connect bpd.clock, clock connect bpd.reset, reset connect bpd.io.f3_fire, UInt<1>(0h0) inst ras of BoomRAS_1 connect ras.clock, clock connect ras.reset, reset connect icache.io.invalidate, io.cpu.flush_icache inst tlb of ITLB_3 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T connect io.cpu.perf.acquire, icache.io.perf.acquire wire s0_vpc : UInt<40> connect s0_vpc, UInt<40>(0h0) wire _s0_ghist_WIRE : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _s0_ghist_WIRE.ras_idx, UInt<5>(0h0) connect _s0_ghist_WIRE.new_saw_branch_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.new_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.current_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.old_history, UInt<64>(0h0) wire s0_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect s0_ghist, _s0_ghist_WIRE wire s0_tsrc : UInt<2> connect s0_tsrc, UInt<2>(0h0) wire s0_valid : UInt<1> connect s0_valid, UInt<1>(0h0) wire s0_is_replay : UInt<1> connect s0_is_replay, UInt<1>(0h0) wire s0_is_sfence : UInt<1> connect s0_is_sfence, UInt<1>(0h0) wire s0_replay_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>} wire s0_replay_bpd_resp : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]} wire s0_replay_ppc : UInt wire s0_s1_use_f3_bpd_resp : UInt<1> connect s0_s1_use_f3_bpd_resp, UInt<1>(0h0) node _T = asUInt(reset) reg REG : UInt<1>, clock connect REG, _T node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = and(REG, _T_2) when _T_3 : connect s0_valid, UInt<1>(0h1) connect s0_vpc, resetVectorSinkNodeIn wire _s0_ghist_WIRE_1 : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _s0_ghist_WIRE_1.ras_idx, UInt<5>(0h0) connect _s0_ghist_WIRE_1.new_saw_branch_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.new_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.current_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.old_history, UInt<64>(0h0) connect s0_ghist, _s0_ghist_WIRE_1 connect s0_tsrc, UInt<2>(0h3) connect icache.io.req.valid, s0_valid connect icache.io.req.bits.addr, s0_vpc connect bpd.io.f0_req.valid, s0_valid connect bpd.io.f0_req.bits.pc, s0_vpc connect bpd.io.f0_req.bits.ghist.ras_idx, s0_ghist.ras_idx connect bpd.io.f0_req.bits.ghist.new_saw_branch_taken, s0_ghist.new_saw_branch_taken connect bpd.io.f0_req.bits.ghist.new_saw_branch_not_taken, s0_ghist.new_saw_branch_not_taken connect bpd.io.f0_req.bits.ghist.current_saw_branch_not_taken, s0_ghist.current_saw_branch_not_taken connect bpd.io.f0_req.bits.ghist.old_history, s0_ghist.old_history reg s1_vpc : UInt, clock connect s1_vpc, s0_vpc regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s1_valid, s0_valid reg s1_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, clock connect s1_ghist, s0_ghist reg s1_is_replay : UInt<1>, clock connect s1_is_replay, s0_is_replay reg s1_is_sfence : UInt<1>, clock connect s1_is_sfence, s0_is_sfence wire f1_clear : UInt<1> connect f1_clear, UInt<1>(0h0) reg s1_tsrc : UInt, clock connect s1_tsrc, s0_tsrc node _tlb_io_req_valid_T = eq(s1_is_replay, UInt<1>(0h0)) node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T) node _tlb_io_req_valid_T_2 = eq(f1_clear, UInt<1>(0h0)) node _tlb_io_req_valid_T_3 = and(_tlb_io_req_valid_T_1, _tlb_io_req_valid_T_2) node _tlb_io_req_valid_T_4 = or(_tlb_io_req_valid_T_3, s1_is_sfence) connect tlb.io.req.valid, _tlb_io_req_valid_T_4 invalidate tlb.io.req.bits.cmd connect tlb.io.req.bits.vaddr, s1_vpc connect tlb.io.req.bits.passthrough, UInt<1>(0h0) connect tlb.io.req.bits.size, UInt<3>(0h4) connect tlb.io.req.bits.v, io.ptw.status.v connect tlb.io.req.bits.prv, io.ptw.status.prv reg tlb_io_sfence_REG : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, clock connect tlb_io_sfence_REG, io.cpu.sfence connect tlb.io.sfence.bits.hg, tlb_io_sfence_REG.bits.hg connect tlb.io.sfence.bits.hv, tlb_io_sfence_REG.bits.hv connect tlb.io.sfence.bits.asid, tlb_io_sfence_REG.bits.asid connect tlb.io.sfence.bits.addr, tlb_io_sfence_REG.bits.addr connect tlb.io.sfence.bits.rs2, tlb_io_sfence_REG.bits.rs2 connect tlb.io.sfence.bits.rs1, tlb_io_sfence_REG.bits.rs1 connect tlb.io.sfence.valid, tlb_io_sfence_REG.valid connect tlb.io.kill, UInt<1>(0h0) node _s1_tlb_miss_T = eq(s1_is_replay, UInt<1>(0h0)) node s1_tlb_miss = and(_s1_tlb_miss_T, tlb.io.resp.miss) reg s1_tlb_resp_REG : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>}, clock connect s1_tlb_resp_REG, s0_replay_resp node s1_tlb_resp = mux(s1_is_replay, s1_tlb_resp_REG, tlb.io.resp) reg s1_ppc_REG : UInt, clock connect s1_ppc_REG, s0_replay_ppc node s1_ppc = mux(s1_is_replay, s1_ppc_REG, tlb.io.resp.paddr) connect icache.io.s1_paddr, s1_ppc node _icache_io_s1_kill_T = or(tlb.io.resp.miss, f1_clear) connect icache.io.s1_kill, _icache_io_s1_kill_T node f1_mask_idx = bits(s1_vpc, 3, 1) node f1_mask_shamt = bits(f1_mask_idx, 1, 0) node _f1_mask_end_mask_T = bits(s1_vpc, 5, 3) node _f1_mask_end_mask_T_1 = eq(_f1_mask_end_mask_T, UInt<3>(0h7)) node _f1_mask_end_mask_T_2 = and(UInt<1>(0h1), _f1_mask_end_mask_T_1) node _f1_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _f1_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node f1_mask_end_mask = mux(_f1_mask_end_mask_T_2, _f1_mask_end_mask_T_3, _f1_mask_end_mask_T_4) node _f1_mask_T = dshl(UInt<8>(0hff), f1_mask_shamt) node f1_mask = and(_f1_mask_T, f1_mask_end_mask) node _f1_redirects_T = bits(f1_mask, 0, 0) node _f1_redirects_T_1 = and(s1_valid, _f1_redirects_T) node _f1_redirects_T_2 = and(_f1_redirects_T_1, bpd.io.resp.f1.preds[0].predicted_pc.valid) node _f1_redirects_T_3 = and(bpd.io.resp.f1.preds[0].is_br, bpd.io.resp.f1.preds[0].taken) node _f1_redirects_T_4 = or(bpd.io.resp.f1.preds[0].is_jal, _f1_redirects_T_3) node f1_redirects_0 = and(_f1_redirects_T_2, _f1_redirects_T_4) node _f1_redirects_T_5 = bits(f1_mask, 1, 1) node _f1_redirects_T_6 = and(s1_valid, _f1_redirects_T_5) node _f1_redirects_T_7 = and(_f1_redirects_T_6, bpd.io.resp.f1.preds[1].predicted_pc.valid) node _f1_redirects_T_8 = and(bpd.io.resp.f1.preds[1].is_br, bpd.io.resp.f1.preds[1].taken) node _f1_redirects_T_9 = or(bpd.io.resp.f1.preds[1].is_jal, _f1_redirects_T_8) node f1_redirects_1 = and(_f1_redirects_T_7, _f1_redirects_T_9) node _f1_redirects_T_10 = bits(f1_mask, 2, 2) node _f1_redirects_T_11 = and(s1_valid, _f1_redirects_T_10) node _f1_redirects_T_12 = and(_f1_redirects_T_11, bpd.io.resp.f1.preds[2].predicted_pc.valid) node _f1_redirects_T_13 = and(bpd.io.resp.f1.preds[2].is_br, bpd.io.resp.f1.preds[2].taken) node _f1_redirects_T_14 = or(bpd.io.resp.f1.preds[2].is_jal, _f1_redirects_T_13) node f1_redirects_2 = and(_f1_redirects_T_12, _f1_redirects_T_14) node _f1_redirects_T_15 = bits(f1_mask, 3, 3) node _f1_redirects_T_16 = and(s1_valid, _f1_redirects_T_15) node _f1_redirects_T_17 = and(_f1_redirects_T_16, bpd.io.resp.f1.preds[3].predicted_pc.valid) node _f1_redirects_T_18 = and(bpd.io.resp.f1.preds[3].is_br, bpd.io.resp.f1.preds[3].taken) node _f1_redirects_T_19 = or(bpd.io.resp.f1.preds[3].is_jal, _f1_redirects_T_18) node f1_redirects_3 = and(_f1_redirects_T_17, _f1_redirects_T_19) node _f1_redirects_T_20 = bits(f1_mask, 4, 4) node _f1_redirects_T_21 = and(s1_valid, _f1_redirects_T_20) node _f1_redirects_T_22 = and(_f1_redirects_T_21, bpd.io.resp.f1.preds[4].predicted_pc.valid) node _f1_redirects_T_23 = and(bpd.io.resp.f1.preds[4].is_br, bpd.io.resp.f1.preds[4].taken) node _f1_redirects_T_24 = or(bpd.io.resp.f1.preds[4].is_jal, _f1_redirects_T_23) node f1_redirects_4 = and(_f1_redirects_T_22, _f1_redirects_T_24) node _f1_redirects_T_25 = bits(f1_mask, 5, 5) node _f1_redirects_T_26 = and(s1_valid, _f1_redirects_T_25) node _f1_redirects_T_27 = and(_f1_redirects_T_26, bpd.io.resp.f1.preds[5].predicted_pc.valid) node _f1_redirects_T_28 = and(bpd.io.resp.f1.preds[5].is_br, bpd.io.resp.f1.preds[5].taken) node _f1_redirects_T_29 = or(bpd.io.resp.f1.preds[5].is_jal, _f1_redirects_T_28) node f1_redirects_5 = and(_f1_redirects_T_27, _f1_redirects_T_29) node _f1_redirects_T_30 = bits(f1_mask, 6, 6) node _f1_redirects_T_31 = and(s1_valid, _f1_redirects_T_30) node _f1_redirects_T_32 = and(_f1_redirects_T_31, bpd.io.resp.f1.preds[6].predicted_pc.valid) node _f1_redirects_T_33 = and(bpd.io.resp.f1.preds[6].is_br, bpd.io.resp.f1.preds[6].taken) node _f1_redirects_T_34 = or(bpd.io.resp.f1.preds[6].is_jal, _f1_redirects_T_33) node f1_redirects_6 = and(_f1_redirects_T_32, _f1_redirects_T_34) node _f1_redirects_T_35 = bits(f1_mask, 7, 7) node _f1_redirects_T_36 = and(s1_valid, _f1_redirects_T_35) node _f1_redirects_T_37 = and(_f1_redirects_T_36, bpd.io.resp.f1.preds[7].predicted_pc.valid) node _f1_redirects_T_38 = and(bpd.io.resp.f1.preds[7].is_br, bpd.io.resp.f1.preds[7].taken) node _f1_redirects_T_39 = or(bpd.io.resp.f1.preds[7].is_jal, _f1_redirects_T_38) node f1_redirects_7 = and(_f1_redirects_T_37, _f1_redirects_T_39) node _f1_redirect_idx_T = mux(f1_redirects_6, UInt<3>(0h6), UInt<3>(0h7)) node _f1_redirect_idx_T_1 = mux(f1_redirects_5, UInt<3>(0h5), _f1_redirect_idx_T) node _f1_redirect_idx_T_2 = mux(f1_redirects_4, UInt<3>(0h4), _f1_redirect_idx_T_1) node _f1_redirect_idx_T_3 = mux(f1_redirects_3, UInt<2>(0h3), _f1_redirect_idx_T_2) node _f1_redirect_idx_T_4 = mux(f1_redirects_2, UInt<2>(0h2), _f1_redirect_idx_T_3) node _f1_redirect_idx_T_5 = mux(f1_redirects_1, UInt<1>(0h1), _f1_redirect_idx_T_4) node f1_redirect_idx = mux(f1_redirects_0, UInt<1>(0h0), _f1_redirect_idx_T_5) node _f1_do_redirect_T = or(f1_redirects_0, f1_redirects_1) node _f1_do_redirect_T_1 = or(_f1_do_redirect_T, f1_redirects_2) node _f1_do_redirect_T_2 = or(_f1_do_redirect_T_1, f1_redirects_3) node _f1_do_redirect_T_3 = or(_f1_do_redirect_T_2, f1_redirects_4) node _f1_do_redirect_T_4 = or(_f1_do_redirect_T_3, f1_redirects_5) node _f1_do_redirect_T_5 = or(_f1_do_redirect_T_4, f1_redirects_6) node _f1_do_redirect_T_6 = or(_f1_do_redirect_T_5, f1_redirects_7) node f1_do_redirect = and(_f1_do_redirect_T_6, UInt<1>(0h1)) node _f1_predicted_target_T = eq(f1_redirect_idx, UInt<1>(0h1)) node _f1_predicted_target_T_1 = mux(_f1_predicted_target_T, bpd.io.resp.f1.preds[1].predicted_pc.bits, bpd.io.resp.f1.preds[0].predicted_pc.bits) node _f1_predicted_target_T_2 = eq(f1_redirect_idx, UInt<2>(0h2)) node _f1_predicted_target_T_3 = mux(_f1_predicted_target_T_2, bpd.io.resp.f1.preds[2].predicted_pc.bits, _f1_predicted_target_T_1) node _f1_predicted_target_T_4 = eq(f1_redirect_idx, UInt<2>(0h3)) node _f1_predicted_target_T_5 = mux(_f1_predicted_target_T_4, bpd.io.resp.f1.preds[3].predicted_pc.bits, _f1_predicted_target_T_3) node _f1_predicted_target_T_6 = eq(f1_redirect_idx, UInt<3>(0h4)) node _f1_predicted_target_T_7 = mux(_f1_predicted_target_T_6, bpd.io.resp.f1.preds[4].predicted_pc.bits, _f1_predicted_target_T_5) node _f1_predicted_target_T_8 = eq(f1_redirect_idx, UInt<3>(0h5)) node _f1_predicted_target_T_9 = mux(_f1_predicted_target_T_8, bpd.io.resp.f1.preds[5].predicted_pc.bits, _f1_predicted_target_T_7) node _f1_predicted_target_T_10 = eq(f1_redirect_idx, UInt<3>(0h6)) node _f1_predicted_target_T_11 = mux(_f1_predicted_target_T_10, bpd.io.resp.f1.preds[6].predicted_pc.bits, _f1_predicted_target_T_9) node _f1_predicted_target_T_12 = eq(f1_redirect_idx, UInt<3>(0h7)) node _f1_predicted_target_T_13 = mux(_f1_predicted_target_T_12, bpd.io.resp.f1.preds[7].predicted_pc.bits, _f1_predicted_target_T_11) node _f1_predicted_target_T_14 = not(s1_vpc) node _f1_predicted_target_T_15 = or(_f1_predicted_target_T_14, UInt<3>(0h7)) node _f1_predicted_target_T_16 = not(_f1_predicted_target_T_15) node _f1_predicted_target_T_17 = bits(s1_vpc, 5, 3) node _f1_predicted_target_T_18 = eq(_f1_predicted_target_T_17, UInt<3>(0h7)) node _f1_predicted_target_T_19 = and(UInt<1>(0h1), _f1_predicted_target_T_18) node _f1_predicted_target_T_20 = mux(_f1_predicted_target_T_19, UInt<4>(0h8), UInt<5>(0h10)) node _f1_predicted_target_T_21 = add(_f1_predicted_target_T_16, _f1_predicted_target_T_20) node _f1_predicted_target_T_22 = tail(_f1_predicted_target_T_21, 1) node f1_predicted_target = mux(f1_do_redirect, _f1_predicted_target_T_13, _f1_predicted_target_T_22) node _f1_predicted_ghist_T = and(bpd.io.resp.f1.preds[0].is_br, bpd.io.resp.f1.preds[0].predicted_pc.valid) node _f1_predicted_ghist_T_1 = and(bpd.io.resp.f1.preds[1].is_br, bpd.io.resp.f1.preds[1].predicted_pc.valid) node _f1_predicted_ghist_T_2 = and(bpd.io.resp.f1.preds[2].is_br, bpd.io.resp.f1.preds[2].predicted_pc.valid) node _f1_predicted_ghist_T_3 = and(bpd.io.resp.f1.preds[3].is_br, bpd.io.resp.f1.preds[3].predicted_pc.valid) node _f1_predicted_ghist_T_4 = and(bpd.io.resp.f1.preds[4].is_br, bpd.io.resp.f1.preds[4].predicted_pc.valid) node _f1_predicted_ghist_T_5 = and(bpd.io.resp.f1.preds[5].is_br, bpd.io.resp.f1.preds[5].predicted_pc.valid) node _f1_predicted_ghist_T_6 = and(bpd.io.resp.f1.preds[6].is_br, bpd.io.resp.f1.preds[6].predicted_pc.valid) node _f1_predicted_ghist_T_7 = and(bpd.io.resp.f1.preds[7].is_br, bpd.io.resp.f1.preds[7].predicted_pc.valid) node f1_predicted_ghist_lo_lo = cat(_f1_predicted_ghist_T_1, _f1_predicted_ghist_T) node f1_predicted_ghist_lo_hi = cat(_f1_predicted_ghist_T_3, _f1_predicted_ghist_T_2) node f1_predicted_ghist_lo = cat(f1_predicted_ghist_lo_hi, f1_predicted_ghist_lo_lo) node f1_predicted_ghist_hi_lo = cat(_f1_predicted_ghist_T_5, _f1_predicted_ghist_T_4) node f1_predicted_ghist_hi_hi = cat(_f1_predicted_ghist_T_7, _f1_predicted_ghist_T_6) node f1_predicted_ghist_hi = cat(f1_predicted_ghist_hi_hi, f1_predicted_ghist_hi_lo) node _f1_predicted_ghist_T_8 = cat(f1_predicted_ghist_hi, f1_predicted_ghist_lo) node _f1_predicted_ghist_T_9 = and(_f1_predicted_ghist_T_8, f1_mask) node _f1_predicted_ghist_T_10 = and(bpd.io.resp.f1.preds[f1_redirect_idx].taken, f1_do_redirect) node f1_predicted_ghist_cfi_idx_fixed = bits(f1_redirect_idx, 2, 0) node f1_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f1_predicted_ghist_cfi_idx_fixed) wire f1_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f1_predicted_ghist_not_taken_branches_T = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_1 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f1_predicted_ghist_not_taken_branches_T_2 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f1_predicted_ghist_not_taken_branches_T_3 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f1_predicted_ghist_not_taken_branches_T_4 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h4)) node _f1_predicted_ghist_not_taken_branches_T_5 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h5)) node _f1_predicted_ghist_not_taken_branches_T_6 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h6)) node _f1_predicted_ghist_not_taken_branches_T_7 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h7)) node _f1_predicted_ghist_not_taken_branches_T_8 = or(_f1_predicted_ghist_not_taken_branches_T, _f1_predicted_ghist_not_taken_branches_T_1) node _f1_predicted_ghist_not_taken_branches_T_9 = or(_f1_predicted_ghist_not_taken_branches_T_8, _f1_predicted_ghist_not_taken_branches_T_2) node _f1_predicted_ghist_not_taken_branches_T_10 = or(_f1_predicted_ghist_not_taken_branches_T_9, _f1_predicted_ghist_not_taken_branches_T_3) node _f1_predicted_ghist_not_taken_branches_T_11 = or(_f1_predicted_ghist_not_taken_branches_T_10, _f1_predicted_ghist_not_taken_branches_T_4) node _f1_predicted_ghist_not_taken_branches_T_12 = or(_f1_predicted_ghist_not_taken_branches_T_11, _f1_predicted_ghist_not_taken_branches_T_5) node _f1_predicted_ghist_not_taken_branches_T_13 = or(_f1_predicted_ghist_not_taken_branches_T_12, _f1_predicted_ghist_not_taken_branches_T_6) node _f1_predicted_ghist_not_taken_branches_T_14 = or(_f1_predicted_ghist_not_taken_branches_T_13, _f1_predicted_ghist_not_taken_branches_T_7) node _f1_predicted_ghist_not_taken_branches_T_15 = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, _f1_predicted_ghist_T_10) node _f1_predicted_ghist_not_taken_branches_T_16 = mux(_f1_predicted_ghist_not_taken_branches_T_15, f1_predicted_ghist_cfi_idx_oh, UInt<8>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_17 = not(_f1_predicted_ghist_not_taken_branches_T_16) node _f1_predicted_ghist_not_taken_branches_T_18 = and(_f1_predicted_ghist_not_taken_branches_T_14, _f1_predicted_ghist_not_taken_branches_T_17) node _f1_predicted_ghist_not_taken_branches_T_19 = not(UInt<8>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_20 = mux(f1_do_redirect, _f1_predicted_ghist_not_taken_branches_T_18, _f1_predicted_ghist_not_taken_branches_T_19) node f1_predicted_ghist_not_taken_branches = and(_f1_predicted_ghist_T_9, _f1_predicted_ghist_not_taken_branches_T_20) node _f1_predicted_ghist_base_T = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_base_T_1 = or(_f1_predicted_ghist_base_T, UInt<1>(0h1)) node _f1_predicted_ghist_base_T_2 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_base_T_3 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_base_T_2, s1_ghist.old_history) node f1_predicted_ghist_base = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_base_T_1, _f1_predicted_ghist_base_T_3) node _f1_predicted_ghist_cfi_in_bank_0_T = and(f1_do_redirect, _f1_predicted_ghist_T_10) node _f1_predicted_ghist_cfi_in_bank_0_T_1 = lt(f1_predicted_ghist_cfi_idx_fixed, UInt<3>(0h4)) node f1_predicted_ghist_cfi_in_bank_0 = and(_f1_predicted_ghist_cfi_in_bank_0_T, _f1_predicted_ghist_cfi_in_bank_0_T_1) node _f1_predicted_ghist_ignore_second_bank_T = bits(s1_vpc, 5, 3) node _f1_predicted_ghist_ignore_second_bank_T_1 = eq(_f1_predicted_ghist_ignore_second_bank_T, UInt<3>(0h7)) node _f1_predicted_ghist_ignore_second_bank_T_2 = and(UInt<1>(0h1), _f1_predicted_ghist_ignore_second_bank_T_1) node f1_predicted_ghist_ignore_second_bank = or(f1_predicted_ghist_cfi_in_bank_0, _f1_predicted_ghist_ignore_second_bank_T_2) node _f1_predicted_ghist_first_bank_saw_not_taken_T = bits(f1_predicted_ghist_not_taken_branches, 3, 0) node _f1_predicted_ghist_first_bank_saw_not_taken_T_1 = neq(_f1_predicted_ghist_first_bank_saw_not_taken_T, UInt<1>(0h0)) node f1_predicted_ghist_first_bank_saw_not_taken = or(_f1_predicted_ghist_first_bank_saw_not_taken_T_1, s1_ghist.current_saw_branch_not_taken) connect f1_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) when f1_predicted_ghist_ignore_second_bank : node _f1_predicted_ghist_new_history_old_history_T = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_1 = or(_f1_predicted_ghist_new_history_old_history_T, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_2 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_3 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_2, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_4 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_1, _f1_predicted_ghist_new_history_old_history_T_3) connect f1_predicted_ghist.old_history, _f1_predicted_ghist_new_history_old_history_T_4 connect f1_predicted_ghist.new_saw_branch_not_taken, f1_predicted_ghist_first_bank_saw_not_taken node _f1_predicted_ghist_new_history_new_saw_branch_taken_T = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, f1_predicted_ghist_cfi_in_bank_0) connect f1_predicted_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_new_saw_branch_taken_T else : node _f1_predicted_ghist_new_history_old_history_T_5 = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, f1_predicted_ghist_cfi_in_bank_0) node _f1_predicted_ghist_new_history_old_history_T_6 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_7 = or(_f1_predicted_ghist_new_history_old_history_T_6, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_8 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_9 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_8, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_10 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_7, _f1_predicted_ghist_new_history_old_history_T_9) node _f1_predicted_ghist_new_history_old_history_T_11 = shl(_f1_predicted_ghist_new_history_old_history_T_10, 1) node _f1_predicted_ghist_new_history_old_history_T_12 = or(_f1_predicted_ghist_new_history_old_history_T_11, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_13 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_14 = or(_f1_predicted_ghist_new_history_old_history_T_13, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_15 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_16 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_15, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_17 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_14, _f1_predicted_ghist_new_history_old_history_T_16) node _f1_predicted_ghist_new_history_old_history_T_18 = shl(_f1_predicted_ghist_new_history_old_history_T_17, 1) node _f1_predicted_ghist_new_history_old_history_T_19 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_20 = or(_f1_predicted_ghist_new_history_old_history_T_19, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_21 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_22 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_21, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_23 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_20, _f1_predicted_ghist_new_history_old_history_T_22) node _f1_predicted_ghist_new_history_old_history_T_24 = mux(f1_predicted_ghist_first_bank_saw_not_taken, _f1_predicted_ghist_new_history_old_history_T_18, _f1_predicted_ghist_new_history_old_history_T_23) node _f1_predicted_ghist_new_history_old_history_T_25 = mux(_f1_predicted_ghist_new_history_old_history_T_5, _f1_predicted_ghist_new_history_old_history_T_12, _f1_predicted_ghist_new_history_old_history_T_24) connect f1_predicted_ghist.old_history, _f1_predicted_ghist_new_history_old_history_T_25 node _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T = bits(f1_predicted_ghist_not_taken_branches, 7, 4) node _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = neq(_f1_predicted_ghist_new_history_new_saw_branch_not_taken_T, UInt<1>(0h0)) connect f1_predicted_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1 = and(f1_do_redirect, _f1_predicted_ghist_T_10) node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_2 = and(_f1_predicted_ghist_new_history_new_saw_branch_taken_T_1, bpd.io.resp.f1.preds[f1_redirect_idx].is_br) node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3 = eq(f1_predicted_ghist_cfi_in_bank_0, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4 = and(_f1_predicted_ghist_new_history_new_saw_branch_taken_T_2, _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3) connect f1_predicted_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4 node _f1_predicted_ghist_new_history_ras_idx_T = and(f1_do_redirect, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_ras_idx_T_1 = add(s1_ghist.ras_idx, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_ras_idx_T_2 = tail(_f1_predicted_ghist_new_history_ras_idx_T_1, 1) node _f1_predicted_ghist_new_history_ras_idx_T_3 = bits(_f1_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f1_predicted_ghist_new_history_ras_idx_T_4 = and(f1_do_redirect, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_ras_idx_T_5 = sub(s1_ghist.ras_idx, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_ras_idx_T_6 = tail(_f1_predicted_ghist_new_history_ras_idx_T_5, 1) node _f1_predicted_ghist_new_history_ras_idx_T_7 = bits(_f1_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f1_predicted_ghist_new_history_ras_idx_T_8 = mux(_f1_predicted_ghist_new_history_ras_idx_T_4, _f1_predicted_ghist_new_history_ras_idx_T_7, s1_ghist.ras_idx) node _f1_predicted_ghist_new_history_ras_idx_T_9 = mux(_f1_predicted_ghist_new_history_ras_idx_T, _f1_predicted_ghist_new_history_ras_idx_T_3, _f1_predicted_ghist_new_history_ras_idx_T_8) connect f1_predicted_ghist.ras_idx, _f1_predicted_ghist_new_history_ras_idx_T_9 node _T_4 = eq(s1_tlb_miss, UInt<1>(0h0)) node _T_5 = and(s1_valid, _T_4) when _T_5 : node _s0_valid_T = or(s1_tlb_resp.ae.inst, s1_tlb_resp.pf.inst) node _s0_valid_T_1 = eq(_s0_valid_T, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_1 connect s0_tsrc, UInt<2>(0h0) connect s0_vpc, f1_predicted_target connect s0_ghist, f1_predicted_ghist connect s0_is_replay, UInt<1>(0h0) node _s2_valid_T = eq(f1_clear, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_valid, _s2_valid_T_1 reg s2_vpc : UInt, clock connect s2_vpc, s1_vpc reg s2_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, clock connect s2_ghist, s1_ghist reg s2_ppc : UInt, clock connect s2_ppc, s1_ppc reg s2_tsrc : UInt, clock connect s2_tsrc, s1_tsrc wire s2_fsrc : UInt<2> connect s2_fsrc, UInt<2>(0h0) wire f2_clear : UInt<1> connect f2_clear, UInt<1>(0h0) reg s2_tlb_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>}, clock connect s2_tlb_resp, s1_tlb_resp reg s2_tlb_miss : UInt<1>, clock connect s2_tlb_miss, s1_tlb_miss reg s2_is_replay_REG : UInt<1>, clock connect s2_is_replay_REG, s1_is_replay node s2_is_replay = and(s2_is_replay_REG, s2_valid) node _s2_xcpt_T = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _s2_xcpt_T_1 = and(s2_valid, _s2_xcpt_T) node _s2_xcpt_T_2 = eq(s2_is_replay, UInt<1>(0h0)) node s2_xcpt = and(_s2_xcpt_T_1, _s2_xcpt_T_2) wire f3_ready : UInt<1> connect icache.io.s2_kill, s2_xcpt node f2_mask_idx = bits(s2_vpc, 3, 1) node f2_mask_shamt = bits(f2_mask_idx, 1, 0) node _f2_mask_end_mask_T = bits(s2_vpc, 5, 3) node _f2_mask_end_mask_T_1 = eq(_f2_mask_end_mask_T, UInt<3>(0h7)) node _f2_mask_end_mask_T_2 = and(UInt<1>(0h1), _f2_mask_end_mask_T_1) node _f2_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _f2_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node f2_mask_end_mask = mux(_f2_mask_end_mask_T_2, _f2_mask_end_mask_T_3, _f2_mask_end_mask_T_4) node _f2_mask_T = dshl(UInt<8>(0hff), f2_mask_shamt) node f2_mask = and(_f2_mask_T, f2_mask_end_mask) node _f2_redirects_T = bits(f2_mask, 0, 0) node _f2_redirects_T_1 = and(s2_valid, _f2_redirects_T) node _f2_redirects_T_2 = and(_f2_redirects_T_1, bpd.io.resp.f2.preds[0].predicted_pc.valid) node _f2_redirects_T_3 = and(bpd.io.resp.f2.preds[0].is_br, bpd.io.resp.f2.preds[0].taken) node _f2_redirects_T_4 = or(bpd.io.resp.f2.preds[0].is_jal, _f2_redirects_T_3) node f2_redirects_0 = and(_f2_redirects_T_2, _f2_redirects_T_4) node _f2_redirects_T_5 = bits(f2_mask, 1, 1) node _f2_redirects_T_6 = and(s2_valid, _f2_redirects_T_5) node _f2_redirects_T_7 = and(_f2_redirects_T_6, bpd.io.resp.f2.preds[1].predicted_pc.valid) node _f2_redirects_T_8 = and(bpd.io.resp.f2.preds[1].is_br, bpd.io.resp.f2.preds[1].taken) node _f2_redirects_T_9 = or(bpd.io.resp.f2.preds[1].is_jal, _f2_redirects_T_8) node f2_redirects_1 = and(_f2_redirects_T_7, _f2_redirects_T_9) node _f2_redirects_T_10 = bits(f2_mask, 2, 2) node _f2_redirects_T_11 = and(s2_valid, _f2_redirects_T_10) node _f2_redirects_T_12 = and(_f2_redirects_T_11, bpd.io.resp.f2.preds[2].predicted_pc.valid) node _f2_redirects_T_13 = and(bpd.io.resp.f2.preds[2].is_br, bpd.io.resp.f2.preds[2].taken) node _f2_redirects_T_14 = or(bpd.io.resp.f2.preds[2].is_jal, _f2_redirects_T_13) node f2_redirects_2 = and(_f2_redirects_T_12, _f2_redirects_T_14) node _f2_redirects_T_15 = bits(f2_mask, 3, 3) node _f2_redirects_T_16 = and(s2_valid, _f2_redirects_T_15) node _f2_redirects_T_17 = and(_f2_redirects_T_16, bpd.io.resp.f2.preds[3].predicted_pc.valid) node _f2_redirects_T_18 = and(bpd.io.resp.f2.preds[3].is_br, bpd.io.resp.f2.preds[3].taken) node _f2_redirects_T_19 = or(bpd.io.resp.f2.preds[3].is_jal, _f2_redirects_T_18) node f2_redirects_3 = and(_f2_redirects_T_17, _f2_redirects_T_19) node _f2_redirects_T_20 = bits(f2_mask, 4, 4) node _f2_redirects_T_21 = and(s2_valid, _f2_redirects_T_20) node _f2_redirects_T_22 = and(_f2_redirects_T_21, bpd.io.resp.f2.preds[4].predicted_pc.valid) node _f2_redirects_T_23 = and(bpd.io.resp.f2.preds[4].is_br, bpd.io.resp.f2.preds[4].taken) node _f2_redirects_T_24 = or(bpd.io.resp.f2.preds[4].is_jal, _f2_redirects_T_23) node f2_redirects_4 = and(_f2_redirects_T_22, _f2_redirects_T_24) node _f2_redirects_T_25 = bits(f2_mask, 5, 5) node _f2_redirects_T_26 = and(s2_valid, _f2_redirects_T_25) node _f2_redirects_T_27 = and(_f2_redirects_T_26, bpd.io.resp.f2.preds[5].predicted_pc.valid) node _f2_redirects_T_28 = and(bpd.io.resp.f2.preds[5].is_br, bpd.io.resp.f2.preds[5].taken) node _f2_redirects_T_29 = or(bpd.io.resp.f2.preds[5].is_jal, _f2_redirects_T_28) node f2_redirects_5 = and(_f2_redirects_T_27, _f2_redirects_T_29) node _f2_redirects_T_30 = bits(f2_mask, 6, 6) node _f2_redirects_T_31 = and(s2_valid, _f2_redirects_T_30) node _f2_redirects_T_32 = and(_f2_redirects_T_31, bpd.io.resp.f2.preds[6].predicted_pc.valid) node _f2_redirects_T_33 = and(bpd.io.resp.f2.preds[6].is_br, bpd.io.resp.f2.preds[6].taken) node _f2_redirects_T_34 = or(bpd.io.resp.f2.preds[6].is_jal, _f2_redirects_T_33) node f2_redirects_6 = and(_f2_redirects_T_32, _f2_redirects_T_34) node _f2_redirects_T_35 = bits(f2_mask, 7, 7) node _f2_redirects_T_36 = and(s2_valid, _f2_redirects_T_35) node _f2_redirects_T_37 = and(_f2_redirects_T_36, bpd.io.resp.f2.preds[7].predicted_pc.valid) node _f2_redirects_T_38 = and(bpd.io.resp.f2.preds[7].is_br, bpd.io.resp.f2.preds[7].taken) node _f2_redirects_T_39 = or(bpd.io.resp.f2.preds[7].is_jal, _f2_redirects_T_38) node f2_redirects_7 = and(_f2_redirects_T_37, _f2_redirects_T_39) node _f2_redirect_idx_T = mux(f2_redirects_6, UInt<3>(0h6), UInt<3>(0h7)) node _f2_redirect_idx_T_1 = mux(f2_redirects_5, UInt<3>(0h5), _f2_redirect_idx_T) node _f2_redirect_idx_T_2 = mux(f2_redirects_4, UInt<3>(0h4), _f2_redirect_idx_T_1) node _f2_redirect_idx_T_3 = mux(f2_redirects_3, UInt<2>(0h3), _f2_redirect_idx_T_2) node _f2_redirect_idx_T_4 = mux(f2_redirects_2, UInt<2>(0h2), _f2_redirect_idx_T_3) node _f2_redirect_idx_T_5 = mux(f2_redirects_1, UInt<1>(0h1), _f2_redirect_idx_T_4) node f2_redirect_idx = mux(f2_redirects_0, UInt<1>(0h0), _f2_redirect_idx_T_5) node _f2_do_redirect_T = or(f2_redirects_0, f2_redirects_1) node _f2_do_redirect_T_1 = or(_f2_do_redirect_T, f2_redirects_2) node _f2_do_redirect_T_2 = or(_f2_do_redirect_T_1, f2_redirects_3) node _f2_do_redirect_T_3 = or(_f2_do_redirect_T_2, f2_redirects_4) node _f2_do_redirect_T_4 = or(_f2_do_redirect_T_3, f2_redirects_5) node _f2_do_redirect_T_5 = or(_f2_do_redirect_T_4, f2_redirects_6) node _f2_do_redirect_T_6 = or(_f2_do_redirect_T_5, f2_redirects_7) node f2_do_redirect = and(_f2_do_redirect_T_6, UInt<1>(0h1)) node _f2_predicted_target_T = eq(f2_redirect_idx, UInt<1>(0h1)) node _f2_predicted_target_T_1 = mux(_f2_predicted_target_T, bpd.io.resp.f2.preds[1].predicted_pc.bits, bpd.io.resp.f2.preds[0].predicted_pc.bits) node _f2_predicted_target_T_2 = eq(f2_redirect_idx, UInt<2>(0h2)) node _f2_predicted_target_T_3 = mux(_f2_predicted_target_T_2, bpd.io.resp.f2.preds[2].predicted_pc.bits, _f2_predicted_target_T_1) node _f2_predicted_target_T_4 = eq(f2_redirect_idx, UInt<2>(0h3)) node _f2_predicted_target_T_5 = mux(_f2_predicted_target_T_4, bpd.io.resp.f2.preds[3].predicted_pc.bits, _f2_predicted_target_T_3) node _f2_predicted_target_T_6 = eq(f2_redirect_idx, UInt<3>(0h4)) node _f2_predicted_target_T_7 = mux(_f2_predicted_target_T_6, bpd.io.resp.f2.preds[4].predicted_pc.bits, _f2_predicted_target_T_5) node _f2_predicted_target_T_8 = eq(f2_redirect_idx, UInt<3>(0h5)) node _f2_predicted_target_T_9 = mux(_f2_predicted_target_T_8, bpd.io.resp.f2.preds[5].predicted_pc.bits, _f2_predicted_target_T_7) node _f2_predicted_target_T_10 = eq(f2_redirect_idx, UInt<3>(0h6)) node _f2_predicted_target_T_11 = mux(_f2_predicted_target_T_10, bpd.io.resp.f2.preds[6].predicted_pc.bits, _f2_predicted_target_T_9) node _f2_predicted_target_T_12 = eq(f2_redirect_idx, UInt<3>(0h7)) node _f2_predicted_target_T_13 = mux(_f2_predicted_target_T_12, bpd.io.resp.f2.preds[7].predicted_pc.bits, _f2_predicted_target_T_11) node _f2_predicted_target_T_14 = not(s2_vpc) node _f2_predicted_target_T_15 = or(_f2_predicted_target_T_14, UInt<3>(0h7)) node _f2_predicted_target_T_16 = not(_f2_predicted_target_T_15) node _f2_predicted_target_T_17 = bits(s2_vpc, 5, 3) node _f2_predicted_target_T_18 = eq(_f2_predicted_target_T_17, UInt<3>(0h7)) node _f2_predicted_target_T_19 = and(UInt<1>(0h1), _f2_predicted_target_T_18) node _f2_predicted_target_T_20 = mux(_f2_predicted_target_T_19, UInt<4>(0h8), UInt<5>(0h10)) node _f2_predicted_target_T_21 = add(_f2_predicted_target_T_16, _f2_predicted_target_T_20) node _f2_predicted_target_T_22 = tail(_f2_predicted_target_T_21, 1) node f2_predicted_target = mux(f2_do_redirect, _f2_predicted_target_T_13, _f2_predicted_target_T_22) node _f2_predicted_ghist_T = and(bpd.io.resp.f2.preds[0].is_br, bpd.io.resp.f2.preds[0].predicted_pc.valid) node _f2_predicted_ghist_T_1 = and(bpd.io.resp.f2.preds[1].is_br, bpd.io.resp.f2.preds[1].predicted_pc.valid) node _f2_predicted_ghist_T_2 = and(bpd.io.resp.f2.preds[2].is_br, bpd.io.resp.f2.preds[2].predicted_pc.valid) node _f2_predicted_ghist_T_3 = and(bpd.io.resp.f2.preds[3].is_br, bpd.io.resp.f2.preds[3].predicted_pc.valid) node _f2_predicted_ghist_T_4 = and(bpd.io.resp.f2.preds[4].is_br, bpd.io.resp.f2.preds[4].predicted_pc.valid) node _f2_predicted_ghist_T_5 = and(bpd.io.resp.f2.preds[5].is_br, bpd.io.resp.f2.preds[5].predicted_pc.valid) node _f2_predicted_ghist_T_6 = and(bpd.io.resp.f2.preds[6].is_br, bpd.io.resp.f2.preds[6].predicted_pc.valid) node _f2_predicted_ghist_T_7 = and(bpd.io.resp.f2.preds[7].is_br, bpd.io.resp.f2.preds[7].predicted_pc.valid) node f2_predicted_ghist_lo_lo = cat(_f2_predicted_ghist_T_1, _f2_predicted_ghist_T) node f2_predicted_ghist_lo_hi = cat(_f2_predicted_ghist_T_3, _f2_predicted_ghist_T_2) node f2_predicted_ghist_lo = cat(f2_predicted_ghist_lo_hi, f2_predicted_ghist_lo_lo) node f2_predicted_ghist_hi_lo = cat(_f2_predicted_ghist_T_5, _f2_predicted_ghist_T_4) node f2_predicted_ghist_hi_hi = cat(_f2_predicted_ghist_T_7, _f2_predicted_ghist_T_6) node f2_predicted_ghist_hi = cat(f2_predicted_ghist_hi_hi, f2_predicted_ghist_hi_lo) node _f2_predicted_ghist_T_8 = cat(f2_predicted_ghist_hi, f2_predicted_ghist_lo) node _f2_predicted_ghist_T_9 = and(_f2_predicted_ghist_T_8, f2_mask) node _f2_predicted_ghist_T_10 = and(bpd.io.resp.f2.preds[f2_redirect_idx].taken, f2_do_redirect) node f2_predicted_ghist_cfi_idx_fixed = bits(f2_redirect_idx, 2, 0) node f2_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f2_predicted_ghist_cfi_idx_fixed) wire f2_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f2_predicted_ghist_not_taken_branches_T = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_1 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f2_predicted_ghist_not_taken_branches_T_2 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f2_predicted_ghist_not_taken_branches_T_3 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f2_predicted_ghist_not_taken_branches_T_4 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h4)) node _f2_predicted_ghist_not_taken_branches_T_5 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h5)) node _f2_predicted_ghist_not_taken_branches_T_6 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h6)) node _f2_predicted_ghist_not_taken_branches_T_7 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h7)) node _f2_predicted_ghist_not_taken_branches_T_8 = or(_f2_predicted_ghist_not_taken_branches_T, _f2_predicted_ghist_not_taken_branches_T_1) node _f2_predicted_ghist_not_taken_branches_T_9 = or(_f2_predicted_ghist_not_taken_branches_T_8, _f2_predicted_ghist_not_taken_branches_T_2) node _f2_predicted_ghist_not_taken_branches_T_10 = or(_f2_predicted_ghist_not_taken_branches_T_9, _f2_predicted_ghist_not_taken_branches_T_3) node _f2_predicted_ghist_not_taken_branches_T_11 = or(_f2_predicted_ghist_not_taken_branches_T_10, _f2_predicted_ghist_not_taken_branches_T_4) node _f2_predicted_ghist_not_taken_branches_T_12 = or(_f2_predicted_ghist_not_taken_branches_T_11, _f2_predicted_ghist_not_taken_branches_T_5) node _f2_predicted_ghist_not_taken_branches_T_13 = or(_f2_predicted_ghist_not_taken_branches_T_12, _f2_predicted_ghist_not_taken_branches_T_6) node _f2_predicted_ghist_not_taken_branches_T_14 = or(_f2_predicted_ghist_not_taken_branches_T_13, _f2_predicted_ghist_not_taken_branches_T_7) node _f2_predicted_ghist_not_taken_branches_T_15 = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, _f2_predicted_ghist_T_10) node _f2_predicted_ghist_not_taken_branches_T_16 = mux(_f2_predicted_ghist_not_taken_branches_T_15, f2_predicted_ghist_cfi_idx_oh, UInt<8>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_17 = not(_f2_predicted_ghist_not_taken_branches_T_16) node _f2_predicted_ghist_not_taken_branches_T_18 = and(_f2_predicted_ghist_not_taken_branches_T_14, _f2_predicted_ghist_not_taken_branches_T_17) node _f2_predicted_ghist_not_taken_branches_T_19 = not(UInt<8>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_20 = mux(f2_do_redirect, _f2_predicted_ghist_not_taken_branches_T_18, _f2_predicted_ghist_not_taken_branches_T_19) node f2_predicted_ghist_not_taken_branches = and(_f2_predicted_ghist_T_9, _f2_predicted_ghist_not_taken_branches_T_20) node _f2_predicted_ghist_base_T = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_base_T_1 = or(_f2_predicted_ghist_base_T, UInt<1>(0h1)) node _f2_predicted_ghist_base_T_2 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_base_T_3 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_base_T_2, s2_ghist.old_history) node f2_predicted_ghist_base = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_base_T_1, _f2_predicted_ghist_base_T_3) node _f2_predicted_ghist_cfi_in_bank_0_T = and(f2_do_redirect, _f2_predicted_ghist_T_10) node _f2_predicted_ghist_cfi_in_bank_0_T_1 = lt(f2_predicted_ghist_cfi_idx_fixed, UInt<3>(0h4)) node f2_predicted_ghist_cfi_in_bank_0 = and(_f2_predicted_ghist_cfi_in_bank_0_T, _f2_predicted_ghist_cfi_in_bank_0_T_1) node _f2_predicted_ghist_ignore_second_bank_T = bits(s2_vpc, 5, 3) node _f2_predicted_ghist_ignore_second_bank_T_1 = eq(_f2_predicted_ghist_ignore_second_bank_T, UInt<3>(0h7)) node _f2_predicted_ghist_ignore_second_bank_T_2 = and(UInt<1>(0h1), _f2_predicted_ghist_ignore_second_bank_T_1) node f2_predicted_ghist_ignore_second_bank = or(f2_predicted_ghist_cfi_in_bank_0, _f2_predicted_ghist_ignore_second_bank_T_2) node _f2_predicted_ghist_first_bank_saw_not_taken_T = bits(f2_predicted_ghist_not_taken_branches, 3, 0) node _f2_predicted_ghist_first_bank_saw_not_taken_T_1 = neq(_f2_predicted_ghist_first_bank_saw_not_taken_T, UInt<1>(0h0)) node f2_predicted_ghist_first_bank_saw_not_taken = or(_f2_predicted_ghist_first_bank_saw_not_taken_T_1, s2_ghist.current_saw_branch_not_taken) connect f2_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) when f2_predicted_ghist_ignore_second_bank : node _f2_predicted_ghist_new_history_old_history_T = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_1 = or(_f2_predicted_ghist_new_history_old_history_T, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_2 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_3 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_2, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_4 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_1, _f2_predicted_ghist_new_history_old_history_T_3) connect f2_predicted_ghist.old_history, _f2_predicted_ghist_new_history_old_history_T_4 connect f2_predicted_ghist.new_saw_branch_not_taken, f2_predicted_ghist_first_bank_saw_not_taken node _f2_predicted_ghist_new_history_new_saw_branch_taken_T = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, f2_predicted_ghist_cfi_in_bank_0) connect f2_predicted_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_new_saw_branch_taken_T else : node _f2_predicted_ghist_new_history_old_history_T_5 = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, f2_predicted_ghist_cfi_in_bank_0) node _f2_predicted_ghist_new_history_old_history_T_6 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_7 = or(_f2_predicted_ghist_new_history_old_history_T_6, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_8 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_9 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_8, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_10 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_7, _f2_predicted_ghist_new_history_old_history_T_9) node _f2_predicted_ghist_new_history_old_history_T_11 = shl(_f2_predicted_ghist_new_history_old_history_T_10, 1) node _f2_predicted_ghist_new_history_old_history_T_12 = or(_f2_predicted_ghist_new_history_old_history_T_11, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_13 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_14 = or(_f2_predicted_ghist_new_history_old_history_T_13, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_15 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_16 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_15, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_17 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_14, _f2_predicted_ghist_new_history_old_history_T_16) node _f2_predicted_ghist_new_history_old_history_T_18 = shl(_f2_predicted_ghist_new_history_old_history_T_17, 1) node _f2_predicted_ghist_new_history_old_history_T_19 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_20 = or(_f2_predicted_ghist_new_history_old_history_T_19, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_21 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_22 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_21, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_23 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_20, _f2_predicted_ghist_new_history_old_history_T_22) node _f2_predicted_ghist_new_history_old_history_T_24 = mux(f2_predicted_ghist_first_bank_saw_not_taken, _f2_predicted_ghist_new_history_old_history_T_18, _f2_predicted_ghist_new_history_old_history_T_23) node _f2_predicted_ghist_new_history_old_history_T_25 = mux(_f2_predicted_ghist_new_history_old_history_T_5, _f2_predicted_ghist_new_history_old_history_T_12, _f2_predicted_ghist_new_history_old_history_T_24) connect f2_predicted_ghist.old_history, _f2_predicted_ghist_new_history_old_history_T_25 node _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T = bits(f2_predicted_ghist_not_taken_branches, 7, 4) node _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = neq(_f2_predicted_ghist_new_history_new_saw_branch_not_taken_T, UInt<1>(0h0)) connect f2_predicted_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1 = and(f2_do_redirect, _f2_predicted_ghist_T_10) node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_2 = and(_f2_predicted_ghist_new_history_new_saw_branch_taken_T_1, bpd.io.resp.f2.preds[f2_redirect_idx].is_br) node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3 = eq(f2_predicted_ghist_cfi_in_bank_0, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4 = and(_f2_predicted_ghist_new_history_new_saw_branch_taken_T_2, _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3) connect f2_predicted_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4 node _f2_predicted_ghist_new_history_ras_idx_T = and(f2_do_redirect, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_ras_idx_T_1 = add(s2_ghist.ras_idx, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_ras_idx_T_2 = tail(_f2_predicted_ghist_new_history_ras_idx_T_1, 1) node _f2_predicted_ghist_new_history_ras_idx_T_3 = bits(_f2_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f2_predicted_ghist_new_history_ras_idx_T_4 = and(f2_do_redirect, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_ras_idx_T_5 = sub(s2_ghist.ras_idx, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_ras_idx_T_6 = tail(_f2_predicted_ghist_new_history_ras_idx_T_5, 1) node _f2_predicted_ghist_new_history_ras_idx_T_7 = bits(_f2_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f2_predicted_ghist_new_history_ras_idx_T_8 = mux(_f2_predicted_ghist_new_history_ras_idx_T_4, _f2_predicted_ghist_new_history_ras_idx_T_7, s2_ghist.ras_idx) node _f2_predicted_ghist_new_history_ras_idx_T_9 = mux(_f2_predicted_ghist_new_history_ras_idx_T, _f2_predicted_ghist_new_history_ras_idx_T_3, _f2_predicted_ghist_new_history_ras_idx_T_8) connect f2_predicted_ghist.ras_idx, _f2_predicted_ghist_new_history_ras_idx_T_9 node _f2_correct_f1_ghist_T = eq(s1_ghist.old_history, f2_predicted_ghist.old_history) node _f2_correct_f1_ghist_T_1 = eq(s1_ghist.new_saw_branch_not_taken, f2_predicted_ghist.new_saw_branch_not_taken) node _f2_correct_f1_ghist_T_2 = and(_f2_correct_f1_ghist_T, _f2_correct_f1_ghist_T_1) node _f2_correct_f1_ghist_T_3 = eq(s1_ghist.new_saw_branch_taken, f2_predicted_ghist.new_saw_branch_taken) node _f2_correct_f1_ghist_T_4 = and(_f2_correct_f1_ghist_T_2, _f2_correct_f1_ghist_T_3) node _f2_correct_f1_ghist_T_5 = eq(_f2_correct_f1_ghist_T_4, UInt<1>(0h0)) node f2_correct_f1_ghist = and(_f2_correct_f1_ghist_T_5, UInt<1>(0h1)) node _T_6 = eq(icache.io.resp.valid, UInt<1>(0h0)) node _T_7 = and(s2_valid, _T_6) node _T_8 = and(s2_valid, icache.io.resp.valid) node _T_9 = eq(f3_ready, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = or(_T_7, _T_10) when _T_11 : node _s0_valid_T_2 = eq(s2_tlb_resp.ae.inst, UInt<1>(0h0)) node _s0_valid_T_3 = eq(s2_tlb_resp.pf.inst, UInt<1>(0h0)) node _s0_valid_T_4 = and(_s0_valid_T_2, _s0_valid_T_3) node _s0_valid_T_5 = or(_s0_valid_T_4, s2_is_replay) node _s0_valid_T_6 = or(_s0_valid_T_5, s2_tlb_miss) connect s0_valid, _s0_valid_T_6 connect s0_vpc, s2_vpc node _s0_is_replay_T = and(s2_valid, icache.io.resp.valid) connect s0_is_replay, _s0_is_replay_T node _s0_s1_use_f3_bpd_resp_T = eq(s2_is_replay, UInt<1>(0h0)) connect s0_s1_use_f3_bpd_resp, _s0_s1_use_f3_bpd_resp_T connect s0_ghist, s2_ghist connect s0_tsrc, s2_tsrc connect f1_clear, UInt<1>(0h1) else : node _T_12 = and(s2_valid, f3_ready) when _T_12 : node _T_13 = eq(s1_vpc, f2_predicted_target) node _T_14 = and(s1_valid, _T_13) node _T_15 = eq(f2_correct_f1_ghist, UInt<1>(0h0)) node _T_16 = and(_T_14, _T_15) when _T_16 : connect s2_ghist, f2_predicted_ghist node _T_17 = neq(s1_vpc, f2_predicted_target) node _T_18 = or(_T_17, f2_correct_f1_ghist) node _T_19 = and(s1_valid, _T_18) node _T_20 = eq(s1_valid, UInt<1>(0h0)) node _T_21 = or(_T_19, _T_20) when _T_21 : connect f1_clear, UInt<1>(0h1) node _s0_valid_T_7 = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _s0_valid_T_8 = eq(s2_is_replay, UInt<1>(0h0)) node _s0_valid_T_9 = and(_s0_valid_T_7, _s0_valid_T_8) node _s0_valid_T_10 = eq(_s0_valid_T_9, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_10 connect s0_vpc, f2_predicted_target connect s0_is_replay, UInt<1>(0h0) connect s0_ghist, f2_predicted_ghist connect s2_fsrc, UInt<2>(0h1) connect s0_tsrc, UInt<2>(0h1) connect s0_replay_bpd_resp.lhist, bpd.io.resp.f2.lhist connect s0_replay_bpd_resp.meta, bpd.io.resp.f2.meta connect s0_replay_bpd_resp.preds[0].predicted_pc, bpd.io.resp.f2.preds[0].predicted_pc connect s0_replay_bpd_resp.preds[0].is_jal, bpd.io.resp.f2.preds[0].is_jal connect s0_replay_bpd_resp.preds[0].is_br, bpd.io.resp.f2.preds[0].is_br connect s0_replay_bpd_resp.preds[0].taken, bpd.io.resp.f2.preds[0].taken connect s0_replay_bpd_resp.preds[1].predicted_pc, bpd.io.resp.f2.preds[1].predicted_pc connect s0_replay_bpd_resp.preds[1].is_jal, bpd.io.resp.f2.preds[1].is_jal connect s0_replay_bpd_resp.preds[1].is_br, bpd.io.resp.f2.preds[1].is_br connect s0_replay_bpd_resp.preds[1].taken, bpd.io.resp.f2.preds[1].taken connect s0_replay_bpd_resp.preds[2].predicted_pc, bpd.io.resp.f2.preds[2].predicted_pc connect s0_replay_bpd_resp.preds[2].is_jal, bpd.io.resp.f2.preds[2].is_jal connect s0_replay_bpd_resp.preds[2].is_br, bpd.io.resp.f2.preds[2].is_br connect s0_replay_bpd_resp.preds[2].taken, bpd.io.resp.f2.preds[2].taken connect s0_replay_bpd_resp.preds[3].predicted_pc, bpd.io.resp.f2.preds[3].predicted_pc connect s0_replay_bpd_resp.preds[3].is_jal, bpd.io.resp.f2.preds[3].is_jal connect s0_replay_bpd_resp.preds[3].is_br, bpd.io.resp.f2.preds[3].is_br connect s0_replay_bpd_resp.preds[3].taken, bpd.io.resp.f2.preds[3].taken connect s0_replay_bpd_resp.preds[4].predicted_pc, bpd.io.resp.f2.preds[4].predicted_pc connect s0_replay_bpd_resp.preds[4].is_jal, bpd.io.resp.f2.preds[4].is_jal connect s0_replay_bpd_resp.preds[4].is_br, bpd.io.resp.f2.preds[4].is_br connect s0_replay_bpd_resp.preds[4].taken, bpd.io.resp.f2.preds[4].taken connect s0_replay_bpd_resp.preds[5].predicted_pc, bpd.io.resp.f2.preds[5].predicted_pc connect s0_replay_bpd_resp.preds[5].is_jal, bpd.io.resp.f2.preds[5].is_jal connect s0_replay_bpd_resp.preds[5].is_br, bpd.io.resp.f2.preds[5].is_br connect s0_replay_bpd_resp.preds[5].taken, bpd.io.resp.f2.preds[5].taken connect s0_replay_bpd_resp.preds[6].predicted_pc, bpd.io.resp.f2.preds[6].predicted_pc connect s0_replay_bpd_resp.preds[6].is_jal, bpd.io.resp.f2.preds[6].is_jal connect s0_replay_bpd_resp.preds[6].is_br, bpd.io.resp.f2.preds[6].is_br connect s0_replay_bpd_resp.preds[6].taken, bpd.io.resp.f2.preds[6].taken connect s0_replay_bpd_resp.preds[7].predicted_pc, bpd.io.resp.f2.preds[7].predicted_pc connect s0_replay_bpd_resp.preds[7].is_jal, bpd.io.resp.f2.preds[7].is_jal connect s0_replay_bpd_resp.preds[7].is_br, bpd.io.resp.f2.preds[7].is_br connect s0_replay_bpd_resp.preds[7].taken, bpd.io.resp.f2.preds[7].taken connect s0_replay_bpd_resp.pc, bpd.io.resp.f2.pc connect s0_replay_resp, s2_tlb_resp connect s0_replay_ppc, s2_ppc wire f3_clear : UInt<1> connect f3_clear, UInt<1>(0h0) node _T_22 = asUInt(reset) node _T_23 = or(_T_22, f3_clear) inst f3 of Queue1_FrontendResp_1 connect f3.clock, clock connect f3.reset, _T_23 node _T_24 = asUInt(reset) node _T_25 = or(_T_24, f3_clear) inst f3_bpd_resp of Queue1_BranchPredictionBundle_1 connect f3_bpd_resp.clock, clock connect f3_bpd_resp.reset, _T_25 wire f4_ready : UInt<1> connect f3_ready, f3.io.enq.ready node _f3_io_enq_valid_T = eq(f2_clear, UInt<1>(0h0)) node _f3_io_enq_valid_T_1 = and(s2_valid, _f3_io_enq_valid_T) node _f3_io_enq_valid_T_2 = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _f3_io_enq_valid_T_3 = eq(s2_tlb_miss, UInt<1>(0h0)) node _f3_io_enq_valid_T_4 = and(_f3_io_enq_valid_T_2, _f3_io_enq_valid_T_3) node _f3_io_enq_valid_T_5 = or(icache.io.resp.valid, _f3_io_enq_valid_T_4) node _f3_io_enq_valid_T_6 = and(_f3_io_enq_valid_T_1, _f3_io_enq_valid_T_5) connect f3.io.enq.valid, _f3_io_enq_valid_T_6 connect f3.io.enq.bits.pc, s2_vpc node _f3_io_enq_bits_data_T = mux(s2_xcpt, UInt<1>(0h0), icache.io.resp.bits.data) connect f3.io.enq.bits.data, _f3_io_enq_bits_data_T connect f3.io.enq.bits.ghist.ras_idx, s2_ghist.ras_idx connect f3.io.enq.bits.ghist.new_saw_branch_taken, s2_ghist.new_saw_branch_taken connect f3.io.enq.bits.ghist.new_saw_branch_not_taken, s2_ghist.new_saw_branch_not_taken connect f3.io.enq.bits.ghist.current_saw_branch_not_taken, s2_ghist.current_saw_branch_not_taken connect f3.io.enq.bits.ghist.old_history, s2_ghist.old_history node f3_io_enq_bits_mask_idx = bits(s2_vpc, 3, 1) node f3_io_enq_bits_mask_shamt = bits(f3_io_enq_bits_mask_idx, 1, 0) node _f3_io_enq_bits_mask_end_mask_T = bits(s2_vpc, 5, 3) node _f3_io_enq_bits_mask_end_mask_T_1 = eq(_f3_io_enq_bits_mask_end_mask_T, UInt<3>(0h7)) node _f3_io_enq_bits_mask_end_mask_T_2 = and(UInt<1>(0h1), _f3_io_enq_bits_mask_end_mask_T_1) node _f3_io_enq_bits_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _f3_io_enq_bits_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node f3_io_enq_bits_mask_end_mask = mux(_f3_io_enq_bits_mask_end_mask_T_2, _f3_io_enq_bits_mask_end_mask_T_3, _f3_io_enq_bits_mask_end_mask_T_4) node _f3_io_enq_bits_mask_T = dshl(UInt<8>(0hff), f3_io_enq_bits_mask_shamt) node _f3_io_enq_bits_mask_T_1 = and(_f3_io_enq_bits_mask_T, f3_io_enq_bits_mask_end_mask) connect f3.io.enq.bits.mask, _f3_io_enq_bits_mask_T_1 connect f3.io.enq.bits.xcpt.ae.inst, s2_tlb_resp.ae.inst connect f3.io.enq.bits.xcpt.gf.inst, s2_tlb_resp.gf.inst connect f3.io.enq.bits.xcpt.pf.inst, s2_tlb_resp.pf.inst connect f3.io.enq.bits.fsrc, s2_fsrc connect f3.io.enq.bits.tsrc, s2_tsrc regreset ras_read_idx : UInt<5>, clock, reset, UInt<5>(0h0) connect ras.io.read_idx, ras_read_idx node _T_26 = and(f3.io.enq.ready, f3.io.enq.valid) when _T_26 : connect ras_read_idx, f3.io.enq.bits.ghist.ras_idx connect ras.io.read_idx, f3.io.enq.bits.ghist.ras_idx reg f3_bpd_resp_io_enq_valid_REG : UInt<1>, clock connect f3_bpd_resp_io_enq_valid_REG, f3.io.enq.ready node _f3_bpd_resp_io_enq_valid_T = and(f3.io.deq.valid, f3_bpd_resp_io_enq_valid_REG) connect f3_bpd_resp.io.enq.valid, _f3_bpd_resp_io_enq_valid_T connect f3_bpd_resp.io.enq.bits.lhist[0], bpd.io.resp.f3.lhist[0] connect f3_bpd_resp.io.enq.bits.lhist[1], bpd.io.resp.f3.lhist[1] connect f3_bpd_resp.io.enq.bits.meta[0], bpd.io.resp.f3.meta[0] connect f3_bpd_resp.io.enq.bits.meta[1], bpd.io.resp.f3.meta[1] connect f3_bpd_resp.io.enq.bits.preds[0].predicted_pc.bits, bpd.io.resp.f3.preds[0].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[0].predicted_pc.valid, bpd.io.resp.f3.preds[0].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[0].is_jal, bpd.io.resp.f3.preds[0].is_jal connect f3_bpd_resp.io.enq.bits.preds[0].is_br, bpd.io.resp.f3.preds[0].is_br connect f3_bpd_resp.io.enq.bits.preds[0].taken, bpd.io.resp.f3.preds[0].taken connect f3_bpd_resp.io.enq.bits.preds[1].predicted_pc.bits, bpd.io.resp.f3.preds[1].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[1].predicted_pc.valid, bpd.io.resp.f3.preds[1].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[1].is_jal, bpd.io.resp.f3.preds[1].is_jal connect f3_bpd_resp.io.enq.bits.preds[1].is_br, bpd.io.resp.f3.preds[1].is_br connect f3_bpd_resp.io.enq.bits.preds[1].taken, bpd.io.resp.f3.preds[1].taken connect f3_bpd_resp.io.enq.bits.preds[2].predicted_pc.bits, bpd.io.resp.f3.preds[2].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[2].predicted_pc.valid, bpd.io.resp.f3.preds[2].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[2].is_jal, bpd.io.resp.f3.preds[2].is_jal connect f3_bpd_resp.io.enq.bits.preds[2].is_br, bpd.io.resp.f3.preds[2].is_br connect f3_bpd_resp.io.enq.bits.preds[2].taken, bpd.io.resp.f3.preds[2].taken connect f3_bpd_resp.io.enq.bits.preds[3].predicted_pc.bits, bpd.io.resp.f3.preds[3].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[3].predicted_pc.valid, bpd.io.resp.f3.preds[3].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[3].is_jal, bpd.io.resp.f3.preds[3].is_jal connect f3_bpd_resp.io.enq.bits.preds[3].is_br, bpd.io.resp.f3.preds[3].is_br connect f3_bpd_resp.io.enq.bits.preds[3].taken, bpd.io.resp.f3.preds[3].taken connect f3_bpd_resp.io.enq.bits.preds[4].predicted_pc.bits, bpd.io.resp.f3.preds[4].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[4].predicted_pc.valid, bpd.io.resp.f3.preds[4].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[4].is_jal, bpd.io.resp.f3.preds[4].is_jal connect f3_bpd_resp.io.enq.bits.preds[4].is_br, bpd.io.resp.f3.preds[4].is_br connect f3_bpd_resp.io.enq.bits.preds[4].taken, bpd.io.resp.f3.preds[4].taken connect f3_bpd_resp.io.enq.bits.preds[5].predicted_pc.bits, bpd.io.resp.f3.preds[5].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[5].predicted_pc.valid, bpd.io.resp.f3.preds[5].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[5].is_jal, bpd.io.resp.f3.preds[5].is_jal connect f3_bpd_resp.io.enq.bits.preds[5].is_br, bpd.io.resp.f3.preds[5].is_br connect f3_bpd_resp.io.enq.bits.preds[5].taken, bpd.io.resp.f3.preds[5].taken connect f3_bpd_resp.io.enq.bits.preds[6].predicted_pc.bits, bpd.io.resp.f3.preds[6].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[6].predicted_pc.valid, bpd.io.resp.f3.preds[6].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[6].is_jal, bpd.io.resp.f3.preds[6].is_jal connect f3_bpd_resp.io.enq.bits.preds[6].is_br, bpd.io.resp.f3.preds[6].is_br connect f3_bpd_resp.io.enq.bits.preds[6].taken, bpd.io.resp.f3.preds[6].taken connect f3_bpd_resp.io.enq.bits.preds[7].predicted_pc.bits, bpd.io.resp.f3.preds[7].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[7].predicted_pc.valid, bpd.io.resp.f3.preds[7].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[7].is_jal, bpd.io.resp.f3.preds[7].is_jal connect f3_bpd_resp.io.enq.bits.preds[7].is_br, bpd.io.resp.f3.preds[7].is_br connect f3_bpd_resp.io.enq.bits.preds[7].taken, bpd.io.resp.f3.preds[7].taken connect f3_bpd_resp.io.enq.bits.pc, bpd.io.resp.f3.pc node _T_27 = and(f3_bpd_resp.io.enq.ready, f3_bpd_resp.io.enq.valid) when _T_27 : connect bpd.io.f3_fire, UInt<1>(0h1) connect f3.io.deq.ready, f4_ready connect f3_bpd_resp.io.deq.ready, f4_ready node f3_bank_mask_idx = bits(f3.io.deq.bits.pc, 3, 1) node _f3_bank_mask_T = bits(f3.io.deq.bits.pc, 5, 3) node _f3_bank_mask_T_1 = eq(_f3_bank_mask_T, UInt<3>(0h7)) node _f3_bank_mask_T_2 = and(UInt<1>(0h1), _f3_bank_mask_T_1) node f3_bank_mask = mux(_f3_bank_mask_T_2, UInt<2>(0h1), UInt<2>(0h3)) node _f3_aligned_pc_T = not(f3.io.deq.bits.pc) node _f3_aligned_pc_T_1 = or(_f3_aligned_pc_T, UInt<3>(0h7)) node f3_aligned_pc = not(_f3_aligned_pc_T_1) node _f3_is_last_bank_in_block_T = bits(f3_aligned_pc, 5, 3) node _f3_is_last_bank_in_block_T_1 = eq(_f3_is_last_bank_in_block_T, UInt<3>(0h7)) node f3_is_last_bank_in_block = and(UInt<1>(0h1), _f3_is_last_bank_in_block_T_1) wire f3_is_rvc : UInt<1>[8] wire f3_redirects : UInt<1>[8] wire f3_targs : UInt<40>[8] wire f3_cfi_types : UInt<3>[8] wire f3_shadowed_mask : UInt<1>[8] wire f3_fetch_bundle : { pc : UInt<40>, next_pc : UInt<40>, edge_inst : UInt<1>[2], insts : UInt<32>[8], exp_insts : UInt<32>[8], sfbs : UInt<1>[8], sfb_masks : UInt<16>[8], sfb_dests : UInt<5>[8], shadowable_mask : UInt<1>[8], shadowed_mask : UInt<1>[8], cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_type : UInt<3>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ftq_idx : UInt<5>, mask : UInt<8>, br_mask : UInt<8>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[2], xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, bp_debug_if_oh : UInt<1>[8], bp_xcpt_if_oh : UInt<1>[8], end_half : { valid : UInt<1>, bits : UInt<16>}, bpd_meta : UInt[2], fsrc : UInt<2>, tsrc : UInt<2>} wire f3_mask : UInt<1>[8] wire f3_br_mask : UInt<1>[8] wire f3_call_mask : UInt<1>[8] wire f3_ret_mask : UInt<1>[8] wire f3_npc_plus4_mask : UInt<1>[8] wire f3_btb_mispredicts : UInt<1>[8] node f3_fetch_bundle_mask_lo_lo = cat(f3_mask[1], f3_mask[0]) node f3_fetch_bundle_mask_lo_hi = cat(f3_mask[3], f3_mask[2]) node f3_fetch_bundle_mask_lo = cat(f3_fetch_bundle_mask_lo_hi, f3_fetch_bundle_mask_lo_lo) node f3_fetch_bundle_mask_hi_lo = cat(f3_mask[5], f3_mask[4]) node f3_fetch_bundle_mask_hi_hi = cat(f3_mask[7], f3_mask[6]) node f3_fetch_bundle_mask_hi = cat(f3_fetch_bundle_mask_hi_hi, f3_fetch_bundle_mask_hi_lo) node _f3_fetch_bundle_mask_T = cat(f3_fetch_bundle_mask_hi, f3_fetch_bundle_mask_lo) connect f3_fetch_bundle.mask, _f3_fetch_bundle_mask_T node f3_fetch_bundle_br_mask_lo_lo = cat(f3_br_mask[1], f3_br_mask[0]) node f3_fetch_bundle_br_mask_lo_hi = cat(f3_br_mask[3], f3_br_mask[2]) node f3_fetch_bundle_br_mask_lo = cat(f3_fetch_bundle_br_mask_lo_hi, f3_fetch_bundle_br_mask_lo_lo) node f3_fetch_bundle_br_mask_hi_lo = cat(f3_br_mask[5], f3_br_mask[4]) node f3_fetch_bundle_br_mask_hi_hi = cat(f3_br_mask[7], f3_br_mask[6]) node f3_fetch_bundle_br_mask_hi = cat(f3_fetch_bundle_br_mask_hi_hi, f3_fetch_bundle_br_mask_hi_lo) node _f3_fetch_bundle_br_mask_T = cat(f3_fetch_bundle_br_mask_hi, f3_fetch_bundle_br_mask_lo) connect f3_fetch_bundle.br_mask, _f3_fetch_bundle_br_mask_T connect f3_fetch_bundle.pc, f3.io.deq.bits.pc connect f3_fetch_bundle.ftq_idx, UInt<1>(0h0) connect f3_fetch_bundle.xcpt_pf_if, f3.io.deq.bits.xcpt.pf.inst connect f3_fetch_bundle.xcpt_ae_if, f3.io.deq.bits.xcpt.ae.inst connect f3_fetch_bundle.fsrc, f3.io.deq.bits.fsrc connect f3_fetch_bundle.tsrc, f3.io.deq.bits.tsrc connect f3_fetch_bundle.shadowed_mask, f3_shadowed_mask reg f3_prev_half : UInt<16>, clock regreset f3_prev_is_half : UInt<1>, clock, reset, UInt<1>(0h0) node bank_data = bits(f3.io.deq.bits.data, 63, 0) wire bank_mask : UInt<1>[4] wire bank_insts : UInt<32>[4] wire valid : UInt<1> inst bpu of BreakpointUnit_11 connect bpu.clock, clock connect bpu.reset, reset connect bpu.io.status.uie, io.cpu.status.uie connect bpu.io.status.sie, io.cpu.status.sie connect bpu.io.status.hie, io.cpu.status.hie connect bpu.io.status.mie, io.cpu.status.mie connect bpu.io.status.upie, io.cpu.status.upie connect bpu.io.status.spie, io.cpu.status.spie connect bpu.io.status.ube, io.cpu.status.ube connect bpu.io.status.mpie, io.cpu.status.mpie connect bpu.io.status.spp, io.cpu.status.spp connect bpu.io.status.vs, io.cpu.status.vs connect bpu.io.status.mpp, io.cpu.status.mpp connect bpu.io.status.fs, io.cpu.status.fs connect bpu.io.status.xs, io.cpu.status.xs connect bpu.io.status.mprv, io.cpu.status.mprv connect bpu.io.status.sum, io.cpu.status.sum connect bpu.io.status.mxr, io.cpu.status.mxr connect bpu.io.status.tvm, io.cpu.status.tvm connect bpu.io.status.tw, io.cpu.status.tw connect bpu.io.status.tsr, io.cpu.status.tsr connect bpu.io.status.zero1, io.cpu.status.zero1 connect bpu.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu.io.status.uxl, io.cpu.status.uxl connect bpu.io.status.sxl, io.cpu.status.sxl connect bpu.io.status.sbe, io.cpu.status.sbe connect bpu.io.status.mbe, io.cpu.status.mbe connect bpu.io.status.gva, io.cpu.status.gva connect bpu.io.status.mpv, io.cpu.status.mpv connect bpu.io.status.zero2, io.cpu.status.zero2 connect bpu.io.status.sd, io.cpu.status.sd connect bpu.io.status.v, io.cpu.status.v connect bpu.io.status.prv, io.cpu.status.prv connect bpu.io.status.dv, io.cpu.status.dv connect bpu.io.status.dprv, io.cpu.status.dprv connect bpu.io.status.isa, io.cpu.status.isa connect bpu.io.status.wfi, io.cpu.status.wfi connect bpu.io.status.cease, io.cpu.status.cease connect bpu.io.status.debug, io.cpu.status.debug invalidate bpu.io.ea connect bpu.io.mcontext, io.cpu.mcontext connect bpu.io.scontext, io.cpu.scontext wire brsigs : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} node _inst0_T = bits(bank_data, 15, 0) node inst0 = cat(_inst0_T, f3_prev_half) node inst1 = bits(bank_data, 31, 0) inst exp_inst0_rvc_exp of RVCExpander_13 connect exp_inst0_rvc_exp.clock, clock connect exp_inst0_rvc_exp.reset, reset connect exp_inst0_rvc_exp.io.in, inst0 node exp_inst0 = mux(exp_inst0_rvc_exp.io.rvc, exp_inst0_rvc_exp.io.out.bits, inst0) inst exp_inst1_rvc_exp of RVCExpander_14 connect exp_inst1_rvc_exp.clock, clock connect exp_inst1_rvc_exp.reset, reset connect exp_inst1_rvc_exp.io.in, inst1 node exp_inst1 = mux(exp_inst1_rvc_exp.io.rvc, exp_inst1_rvc_exp.io.out.bits, inst1) node _pc0_T = add(f3_aligned_pc, UInt<1>(0h0)) node _pc0_T_1 = tail(_pc0_T, 1) node _pc0_T_2 = sub(_pc0_T_1, UInt<2>(0h2)) node pc0 = tail(_pc0_T_2, 1) node _pc1_T = add(f3_aligned_pc, UInt<1>(0h0)) node pc1 = tail(_pc1_T, 1) inst bpd_decoder0 of BranchDecode_11 connect bpd_decoder0.clock, clock connect bpd_decoder0.reset, reset connect bpd_decoder0.io.inst, exp_inst0 connect bpd_decoder0.io.pc, pc0 inst bpd_decoder1 of BranchDecode_12 connect bpd_decoder1.clock, clock connect bpd_decoder1.reset, reset connect bpd_decoder1.io.inst, exp_inst1 connect bpd_decoder1.io.pc, pc1 when f3_prev_is_half : connect bank_insts[0], inst0 connect f3_fetch_bundle.insts[0], inst0 connect f3_fetch_bundle.exp_insts[0], exp_inst0 connect bpu.io.pc, pc0 connect brsigs.shadowable, bpd_decoder0.io.out.shadowable connect brsigs.sfb_offset, bpd_decoder0.io.out.sfb_offset connect brsigs.cfi_type, bpd_decoder0.io.out.cfi_type connect brsigs.target, bpd_decoder0.io.out.target connect brsigs.is_call, bpd_decoder0.io.out.is_call connect brsigs.is_ret, bpd_decoder0.io.out.is_ret connect f3_fetch_bundle.edge_inst[0], UInt<1>(0h1) else : connect bank_insts[0], inst1 connect f3_fetch_bundle.insts[0], inst1 connect f3_fetch_bundle.exp_insts[0], exp_inst1 connect bpu.io.pc, pc1 connect brsigs.shadowable, bpd_decoder1.io.out.shadowable connect brsigs.sfb_offset, bpd_decoder1.io.out.sfb_offset connect brsigs.cfi_type, bpd_decoder1.io.out.cfi_type connect brsigs.target, bpd_decoder1.io.out.target connect brsigs.is_call, bpd_decoder1.io.out.is_call connect brsigs.is_ret, bpd_decoder1.io.out.is_ret connect f3_fetch_bundle.edge_inst[0], UInt<1>(0h0) connect valid, UInt<1>(0h1) node _f3_is_rvc_0_T = bits(bank_insts[0], 1, 0) node _f3_is_rvc_0_T_1 = neq(_f3_is_rvc_0_T, UInt<2>(0h3)) connect f3_is_rvc[0], _f3_is_rvc_0_T_1 node _bank_mask_0_T = bits(f3.io.deq.bits.mask, 0, 0) node _bank_mask_0_T_1 = and(f3.io.deq.valid, _bank_mask_0_T) node _bank_mask_0_T_2 = and(_bank_mask_0_T_1, valid) node _bank_mask_0_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bank_mask_0_T_4 = and(_bank_mask_0_T_2, _bank_mask_0_T_3) connect bank_mask[0], _bank_mask_0_T_4 node _f3_mask_0_T = bits(f3.io.deq.bits.mask, 0, 0) node _f3_mask_0_T_1 = and(f3.io.deq.valid, _f3_mask_0_T) node _f3_mask_0_T_2 = and(_f3_mask_0_T_1, valid) node _f3_mask_0_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _f3_mask_0_T_4 = and(_f3_mask_0_T_2, _f3_mask_0_T_3) connect f3_mask[0], _f3_mask_0_T_4 node _f3_targs_0_T = eq(brsigs.cfi_type, UInt<3>(0h3)) node _f3_targs_0_T_1 = mux(_f3_targs_0_T, f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.bits, brsigs.target) connect f3_targs[0], _f3_targs_0_T_1 node _f3_btb_mispredicts_0_T = eq(brsigs.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_0_T_1 = and(_f3_btb_mispredicts_0_T, valid) node _f3_btb_mispredicts_0_T_2 = and(_f3_btb_mispredicts_0_T_1, f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.valid) node _f3_btb_mispredicts_0_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.bits, brsigs.target) node _f3_btb_mispredicts_0_T_4 = and(_f3_btb_mispredicts_0_T_2, _f3_btb_mispredicts_0_T_3) connect f3_btb_mispredicts[0], _f3_btb_mispredicts_0_T_4 node _f3_npc_plus4_mask_0_T = eq(f3_is_rvc[0], UInt<1>(0h0)) node _f3_npc_plus4_mask_0_T_1 = eq(f3_prev_is_half, UInt<1>(0h0)) node _f3_npc_plus4_mask_0_T_2 = and(_f3_npc_plus4_mask_0_T, _f3_npc_plus4_mask_0_T_1) connect f3_npc_plus4_mask[0], _f3_npc_plus4_mask_0_T_2 node _offset_from_aligned_pc_T = add(UInt<7>(0h0), brsigs.sfb_offset.bits) node _offset_from_aligned_pc_T_1 = tail(_offset_from_aligned_pc_T, 1) node _offset_from_aligned_pc_T_2 = and(f3_prev_is_half, UInt<1>(0h1)) node _offset_from_aligned_pc_T_3 = mux(_offset_from_aligned_pc_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_4 = sub(_offset_from_aligned_pc_T_1, _offset_from_aligned_pc_T_3) node offset_from_aligned_pc = tail(_offset_from_aligned_pc_T_4, 1) wire lower_mask : UInt<16> wire upper_mask : UInt<16> node _lower_mask_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) connect lower_mask, _lower_mask_T node _upper_mask_T = bits(offset_from_aligned_pc, 5, 1) node _upper_mask_T_1 = dshl(UInt<1>(0h1), _upper_mask_T) node _upper_mask_T_2 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_3 = dshl(_upper_mask_T_1, _upper_mask_T_2) connect upper_mask, _upper_mask_T_3 node _f3_fetch_bundle_sfbs_0_T = and(f3_mask[0], brsigs.sfb_offset.valid) node _f3_fetch_bundle_sfbs_0_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_0_T_2 = leq(offset_from_aligned_pc, _f3_fetch_bundle_sfbs_0_T_1) node _f3_fetch_bundle_sfbs_0_T_3 = and(_f3_fetch_bundle_sfbs_0_T, _f3_fetch_bundle_sfbs_0_T_2) connect f3_fetch_bundle.sfbs[0], _f3_fetch_bundle_sfbs_0_T_3 node _f3_fetch_bundle_sfb_masks_0_T = dshr(lower_mask, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_0_T_1 = dshr(lower_mask, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_0_T_2 = dshr(lower_mask, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_0_T_3 = dshr(lower_mask, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_0_T_4 = dshr(lower_mask, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_0_T_5 = dshr(lower_mask, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_0_T_6 = dshr(lower_mask, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_0_T_7 = dshr(lower_mask, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_0_T_8 = dshr(lower_mask, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_0_T_9 = dshr(lower_mask, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_0_T_10 = dshr(lower_mask, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_0_T_11 = dshr(lower_mask, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_0_T_12 = dshr(lower_mask, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_0_T_13 = dshr(lower_mask, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_0_T_14 = dshr(lower_mask, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_0_T_15 = dshr(lower_mask, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_0_T_16 = or(_f3_fetch_bundle_sfb_masks_0_T, _f3_fetch_bundle_sfb_masks_0_T_1) node _f3_fetch_bundle_sfb_masks_0_T_17 = or(_f3_fetch_bundle_sfb_masks_0_T_16, _f3_fetch_bundle_sfb_masks_0_T_2) node _f3_fetch_bundle_sfb_masks_0_T_18 = or(_f3_fetch_bundle_sfb_masks_0_T_17, _f3_fetch_bundle_sfb_masks_0_T_3) node _f3_fetch_bundle_sfb_masks_0_T_19 = or(_f3_fetch_bundle_sfb_masks_0_T_18, _f3_fetch_bundle_sfb_masks_0_T_4) node _f3_fetch_bundle_sfb_masks_0_T_20 = or(_f3_fetch_bundle_sfb_masks_0_T_19, _f3_fetch_bundle_sfb_masks_0_T_5) node _f3_fetch_bundle_sfb_masks_0_T_21 = or(_f3_fetch_bundle_sfb_masks_0_T_20, _f3_fetch_bundle_sfb_masks_0_T_6) node _f3_fetch_bundle_sfb_masks_0_T_22 = or(_f3_fetch_bundle_sfb_masks_0_T_21, _f3_fetch_bundle_sfb_masks_0_T_7) node _f3_fetch_bundle_sfb_masks_0_T_23 = or(_f3_fetch_bundle_sfb_masks_0_T_22, _f3_fetch_bundle_sfb_masks_0_T_8) node _f3_fetch_bundle_sfb_masks_0_T_24 = or(_f3_fetch_bundle_sfb_masks_0_T_23, _f3_fetch_bundle_sfb_masks_0_T_9) node _f3_fetch_bundle_sfb_masks_0_T_25 = or(_f3_fetch_bundle_sfb_masks_0_T_24, _f3_fetch_bundle_sfb_masks_0_T_10) node _f3_fetch_bundle_sfb_masks_0_T_26 = or(_f3_fetch_bundle_sfb_masks_0_T_25, _f3_fetch_bundle_sfb_masks_0_T_11) node _f3_fetch_bundle_sfb_masks_0_T_27 = or(_f3_fetch_bundle_sfb_masks_0_T_26, _f3_fetch_bundle_sfb_masks_0_T_12) node _f3_fetch_bundle_sfb_masks_0_T_28 = or(_f3_fetch_bundle_sfb_masks_0_T_27, _f3_fetch_bundle_sfb_masks_0_T_13) node _f3_fetch_bundle_sfb_masks_0_T_29 = or(_f3_fetch_bundle_sfb_masks_0_T_28, _f3_fetch_bundle_sfb_masks_0_T_14) node _f3_fetch_bundle_sfb_masks_0_T_30 = or(_f3_fetch_bundle_sfb_masks_0_T_29, _f3_fetch_bundle_sfb_masks_0_T_15) node _f3_fetch_bundle_sfb_masks_0_T_31 = not(_f3_fetch_bundle_sfb_masks_0_T_30) node _f3_fetch_bundle_sfb_masks_0_T_32 = dshl(upper_mask, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_0_T_33 = bits(_f3_fetch_bundle_sfb_masks_0_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_34 = dshl(upper_mask, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_0_T_35 = bits(_f3_fetch_bundle_sfb_masks_0_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_36 = dshl(upper_mask, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_0_T_37 = bits(_f3_fetch_bundle_sfb_masks_0_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_38 = dshl(upper_mask, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_0_T_39 = bits(_f3_fetch_bundle_sfb_masks_0_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_40 = dshl(upper_mask, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_0_T_41 = bits(_f3_fetch_bundle_sfb_masks_0_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_42 = dshl(upper_mask, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_0_T_43 = bits(_f3_fetch_bundle_sfb_masks_0_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_44 = dshl(upper_mask, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_0_T_45 = bits(_f3_fetch_bundle_sfb_masks_0_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_46 = dshl(upper_mask, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_0_T_47 = bits(_f3_fetch_bundle_sfb_masks_0_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_48 = dshl(upper_mask, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_0_T_49 = bits(_f3_fetch_bundle_sfb_masks_0_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_50 = dshl(upper_mask, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_0_T_51 = bits(_f3_fetch_bundle_sfb_masks_0_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_52 = dshl(upper_mask, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_0_T_53 = bits(_f3_fetch_bundle_sfb_masks_0_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_54 = dshl(upper_mask, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_0_T_55 = bits(_f3_fetch_bundle_sfb_masks_0_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_56 = dshl(upper_mask, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_0_T_57 = bits(_f3_fetch_bundle_sfb_masks_0_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_58 = dshl(upper_mask, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_0_T_59 = bits(_f3_fetch_bundle_sfb_masks_0_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_60 = dshl(upper_mask, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_0_T_61 = bits(_f3_fetch_bundle_sfb_masks_0_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_62 = dshl(upper_mask, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_0_T_63 = bits(_f3_fetch_bundle_sfb_masks_0_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_64 = or(_f3_fetch_bundle_sfb_masks_0_T_33, _f3_fetch_bundle_sfb_masks_0_T_35) node _f3_fetch_bundle_sfb_masks_0_T_65 = or(_f3_fetch_bundle_sfb_masks_0_T_64, _f3_fetch_bundle_sfb_masks_0_T_37) node _f3_fetch_bundle_sfb_masks_0_T_66 = or(_f3_fetch_bundle_sfb_masks_0_T_65, _f3_fetch_bundle_sfb_masks_0_T_39) node _f3_fetch_bundle_sfb_masks_0_T_67 = or(_f3_fetch_bundle_sfb_masks_0_T_66, _f3_fetch_bundle_sfb_masks_0_T_41) node _f3_fetch_bundle_sfb_masks_0_T_68 = or(_f3_fetch_bundle_sfb_masks_0_T_67, _f3_fetch_bundle_sfb_masks_0_T_43) node _f3_fetch_bundle_sfb_masks_0_T_69 = or(_f3_fetch_bundle_sfb_masks_0_T_68, _f3_fetch_bundle_sfb_masks_0_T_45) node _f3_fetch_bundle_sfb_masks_0_T_70 = or(_f3_fetch_bundle_sfb_masks_0_T_69, _f3_fetch_bundle_sfb_masks_0_T_47) node _f3_fetch_bundle_sfb_masks_0_T_71 = or(_f3_fetch_bundle_sfb_masks_0_T_70, _f3_fetch_bundle_sfb_masks_0_T_49) node _f3_fetch_bundle_sfb_masks_0_T_72 = or(_f3_fetch_bundle_sfb_masks_0_T_71, _f3_fetch_bundle_sfb_masks_0_T_51) node _f3_fetch_bundle_sfb_masks_0_T_73 = or(_f3_fetch_bundle_sfb_masks_0_T_72, _f3_fetch_bundle_sfb_masks_0_T_53) node _f3_fetch_bundle_sfb_masks_0_T_74 = or(_f3_fetch_bundle_sfb_masks_0_T_73, _f3_fetch_bundle_sfb_masks_0_T_55) node _f3_fetch_bundle_sfb_masks_0_T_75 = or(_f3_fetch_bundle_sfb_masks_0_T_74, _f3_fetch_bundle_sfb_masks_0_T_57) node _f3_fetch_bundle_sfb_masks_0_T_76 = or(_f3_fetch_bundle_sfb_masks_0_T_75, _f3_fetch_bundle_sfb_masks_0_T_59) node _f3_fetch_bundle_sfb_masks_0_T_77 = or(_f3_fetch_bundle_sfb_masks_0_T_76, _f3_fetch_bundle_sfb_masks_0_T_61) node _f3_fetch_bundle_sfb_masks_0_T_78 = or(_f3_fetch_bundle_sfb_masks_0_T_77, _f3_fetch_bundle_sfb_masks_0_T_63) node _f3_fetch_bundle_sfb_masks_0_T_79 = not(_f3_fetch_bundle_sfb_masks_0_T_78) node _f3_fetch_bundle_sfb_masks_0_T_80 = and(_f3_fetch_bundle_sfb_masks_0_T_31, _f3_fetch_bundle_sfb_masks_0_T_79) connect f3_fetch_bundle.sfb_masks[0], _f3_fetch_bundle_sfb_masks_0_T_80 node _f3_fetch_bundle_shadowable_mask_0_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_0_T_1 = or(_f3_fetch_bundle_shadowable_mask_0_T, bpu.io.debug_if) node _f3_fetch_bundle_shadowable_mask_0_T_2 = or(_f3_fetch_bundle_shadowable_mask_0_T_1, bpu.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_0_T_3 = eq(_f3_fetch_bundle_shadowable_mask_0_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_0_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_0_T_5 = and(_f3_fetch_bundle_shadowable_mask_0_T_3, _f3_fetch_bundle_shadowable_mask_0_T_4) node _f3_fetch_bundle_shadowable_mask_0_T_6 = eq(f3_mask[0], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_0_T_7 = or(brsigs.shadowable, _f3_fetch_bundle_shadowable_mask_0_T_6) node _f3_fetch_bundle_shadowable_mask_0_T_8 = and(_f3_fetch_bundle_shadowable_mask_0_T_5, _f3_fetch_bundle_shadowable_mask_0_T_7) connect f3_fetch_bundle.shadowable_mask[0], _f3_fetch_bundle_shadowable_mask_0_T_8 connect f3_fetch_bundle.sfb_dests[0], offset_from_aligned_pc node _f3_redirects_0_T = eq(brsigs.cfi_type, UInt<3>(0h2)) node _f3_redirects_0_T_1 = eq(brsigs.cfi_type, UInt<3>(0h3)) node _f3_redirects_0_T_2 = or(_f3_redirects_0_T, _f3_redirects_0_T_1) node _f3_redirects_0_T_3 = eq(brsigs.cfi_type, UInt<3>(0h1)) node _f3_redirects_0_T_4 = and(_f3_redirects_0_T_3, f3_bpd_resp.io.deq.bits.preds[0].taken) node _f3_redirects_0_T_5 = and(_f3_redirects_0_T_4, UInt<1>(0h1)) node _f3_redirects_0_T_6 = or(_f3_redirects_0_T_2, _f3_redirects_0_T_5) node _f3_redirects_0_T_7 = and(f3_mask[0], _f3_redirects_0_T_6) connect f3_redirects[0], _f3_redirects_0_T_7 node _f3_br_mask_0_T = eq(brsigs.cfi_type, UInt<3>(0h1)) node _f3_br_mask_0_T_1 = and(f3_mask[0], _f3_br_mask_0_T) connect f3_br_mask[0], _f3_br_mask_0_T_1 connect f3_cfi_types[0], brsigs.cfi_type connect f3_call_mask[0], brsigs.is_call connect f3_ret_mask[0], brsigs.is_ret connect f3_fetch_bundle.bp_debug_if_oh[0], bpu.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[0], bpu.io.xcpt_if node _T_28 = or(UInt<1>(0h0), f3_redirects[0]) wire valid_1 : UInt<1> inst bpu_1 of BreakpointUnit_12 connect bpu_1.clock, clock connect bpu_1.reset, reset connect bpu_1.io.status.uie, io.cpu.status.uie connect bpu_1.io.status.sie, io.cpu.status.sie connect bpu_1.io.status.hie, io.cpu.status.hie connect bpu_1.io.status.mie, io.cpu.status.mie connect bpu_1.io.status.upie, io.cpu.status.upie connect bpu_1.io.status.spie, io.cpu.status.spie connect bpu_1.io.status.ube, io.cpu.status.ube connect bpu_1.io.status.mpie, io.cpu.status.mpie connect bpu_1.io.status.spp, io.cpu.status.spp connect bpu_1.io.status.vs, io.cpu.status.vs connect bpu_1.io.status.mpp, io.cpu.status.mpp connect bpu_1.io.status.fs, io.cpu.status.fs connect bpu_1.io.status.xs, io.cpu.status.xs connect bpu_1.io.status.mprv, io.cpu.status.mprv connect bpu_1.io.status.sum, io.cpu.status.sum connect bpu_1.io.status.mxr, io.cpu.status.mxr connect bpu_1.io.status.tvm, io.cpu.status.tvm connect bpu_1.io.status.tw, io.cpu.status.tw connect bpu_1.io.status.tsr, io.cpu.status.tsr connect bpu_1.io.status.zero1, io.cpu.status.zero1 connect bpu_1.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_1.io.status.uxl, io.cpu.status.uxl connect bpu_1.io.status.sxl, io.cpu.status.sxl connect bpu_1.io.status.sbe, io.cpu.status.sbe connect bpu_1.io.status.mbe, io.cpu.status.mbe connect bpu_1.io.status.gva, io.cpu.status.gva connect bpu_1.io.status.mpv, io.cpu.status.mpv connect bpu_1.io.status.zero2, io.cpu.status.zero2 connect bpu_1.io.status.sd, io.cpu.status.sd connect bpu_1.io.status.v, io.cpu.status.v connect bpu_1.io.status.prv, io.cpu.status.prv connect bpu_1.io.status.dv, io.cpu.status.dv connect bpu_1.io.status.dprv, io.cpu.status.dprv connect bpu_1.io.status.isa, io.cpu.status.isa connect bpu_1.io.status.wfi, io.cpu.status.wfi connect bpu_1.io.status.cease, io.cpu.status.cease connect bpu_1.io.status.debug, io.cpu.status.debug invalidate bpu_1.io.ea connect bpu_1.io.mcontext, io.cpu.mcontext connect bpu_1.io.scontext, io.cpu.scontext wire brsigs_1 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst : UInt<32> inst exp_inst_rvc_exp of RVCExpander_15 connect exp_inst_rvc_exp.clock, clock connect exp_inst_rvc_exp.reset, reset connect exp_inst_rvc_exp.io.in, inst node exp_inst = mux(exp_inst_rvc_exp.io.rvc, exp_inst_rvc_exp.io.out.bits, inst) node _pc_T = add(f3_aligned_pc, UInt<2>(0h2)) node pc = tail(_pc_T, 1) inst bpd_decoder of BranchDecode_13 connect bpd_decoder.clock, clock connect bpd_decoder.reset, reset connect bpd_decoder.io.inst, exp_inst connect bpd_decoder.io.pc, pc connect bank_insts[1], inst connect f3_fetch_bundle.insts[1], inst connect f3_fetch_bundle.exp_insts[1], exp_inst connect bpu_1.io.pc, pc connect brsigs_1.shadowable, bpd_decoder.io.out.shadowable connect brsigs_1.sfb_offset, bpd_decoder.io.out.sfb_offset connect brsigs_1.cfi_type, bpd_decoder.io.out.cfi_type connect brsigs_1.target, bpd_decoder.io.out.target connect brsigs_1.is_call, bpd_decoder.io.out.is_call connect brsigs_1.is_ret, bpd_decoder.io.out.is_ret node _inst_T = bits(bank_data, 47, 16) connect inst, _inst_T node _valid_T = bits(bank_insts[0], 1, 0) node _valid_T_1 = neq(_valid_T, UInt<2>(0h3)) node _valid_T_2 = eq(_valid_T_1, UInt<1>(0h0)) node _valid_T_3 = and(bank_mask[0], _valid_T_2) node _valid_T_4 = eq(_valid_T_3, UInt<1>(0h0)) node _valid_T_5 = or(f3_prev_is_half, _valid_T_4) connect valid_1, _valid_T_5 node _f3_is_rvc_1_T = bits(bank_insts[1], 1, 0) node _f3_is_rvc_1_T_1 = neq(_f3_is_rvc_1_T, UInt<2>(0h3)) connect f3_is_rvc[1], _f3_is_rvc_1_T_1 node _bank_mask_1_T = bits(f3.io.deq.bits.mask, 1, 1) node _bank_mask_1_T_1 = and(f3.io.deq.valid, _bank_mask_1_T) node _bank_mask_1_T_2 = and(_bank_mask_1_T_1, valid_1) node _bank_mask_1_T_3 = eq(_T_28, UInt<1>(0h0)) node _bank_mask_1_T_4 = and(_bank_mask_1_T_2, _bank_mask_1_T_3) connect bank_mask[1], _bank_mask_1_T_4 node _f3_mask_1_T = bits(f3.io.deq.bits.mask, 1, 1) node _f3_mask_1_T_1 = and(f3.io.deq.valid, _f3_mask_1_T) node _f3_mask_1_T_2 = and(_f3_mask_1_T_1, valid_1) node _f3_mask_1_T_3 = eq(_T_28, UInt<1>(0h0)) node _f3_mask_1_T_4 = and(_f3_mask_1_T_2, _f3_mask_1_T_3) connect f3_mask[1], _f3_mask_1_T_4 node _f3_targs_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h3)) node _f3_targs_1_T_1 = mux(_f3_targs_1_T, f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.bits, brsigs_1.target) connect f3_targs[1], _f3_targs_1_T_1 node _f3_btb_mispredicts_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_1_T_1 = and(_f3_btb_mispredicts_1_T, valid_1) node _f3_btb_mispredicts_1_T_2 = and(_f3_btb_mispredicts_1_T_1, f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.valid) node _f3_btb_mispredicts_1_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.bits, brsigs_1.target) node _f3_btb_mispredicts_1_T_4 = and(_f3_btb_mispredicts_1_T_2, _f3_btb_mispredicts_1_T_3) connect f3_btb_mispredicts[1], _f3_btb_mispredicts_1_T_4 node _f3_npc_plus4_mask_1_T = eq(f3_is_rvc[1], UInt<1>(0h0)) connect f3_npc_plus4_mask[1], _f3_npc_plus4_mask_1_T node _offset_from_aligned_pc_T_5 = add(UInt<7>(0h2), brsigs_1.sfb_offset.bits) node _offset_from_aligned_pc_T_6 = tail(_offset_from_aligned_pc_T_5, 1) node _offset_from_aligned_pc_T_7 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_8 = mux(_offset_from_aligned_pc_T_7, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_9 = sub(_offset_from_aligned_pc_T_6, _offset_from_aligned_pc_T_8) node offset_from_aligned_pc_1 = tail(_offset_from_aligned_pc_T_9, 1) wire lower_mask_1 : UInt<16> wire upper_mask_1 : UInt<16> node _lower_mask_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1)) connect lower_mask_1, _lower_mask_T_1 node _upper_mask_T_4 = bits(offset_from_aligned_pc_1, 5, 1) node _upper_mask_T_5 = dshl(UInt<1>(0h1), _upper_mask_T_4) node _upper_mask_T_6 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_7 = dshl(_upper_mask_T_5, _upper_mask_T_6) connect upper_mask_1, _upper_mask_T_7 node _f3_fetch_bundle_sfbs_1_T = and(f3_mask[1], brsigs_1.sfb_offset.valid) node _f3_fetch_bundle_sfbs_1_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_1_T_2 = leq(offset_from_aligned_pc_1, _f3_fetch_bundle_sfbs_1_T_1) node _f3_fetch_bundle_sfbs_1_T_3 = and(_f3_fetch_bundle_sfbs_1_T, _f3_fetch_bundle_sfbs_1_T_2) connect f3_fetch_bundle.sfbs[1], _f3_fetch_bundle_sfbs_1_T_3 node _f3_fetch_bundle_sfb_masks_1_T = dshr(lower_mask_1, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_1_T_1 = dshr(lower_mask_1, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_1_T_2 = dshr(lower_mask_1, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_1_T_3 = dshr(lower_mask_1, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_1_T_4 = dshr(lower_mask_1, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_1_T_5 = dshr(lower_mask_1, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_1_T_6 = dshr(lower_mask_1, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_1_T_7 = dshr(lower_mask_1, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_1_T_8 = dshr(lower_mask_1, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_1_T_9 = dshr(lower_mask_1, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_1_T_10 = dshr(lower_mask_1, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_1_T_11 = dshr(lower_mask_1, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_1_T_12 = dshr(lower_mask_1, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_1_T_13 = dshr(lower_mask_1, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_1_T_14 = dshr(lower_mask_1, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_1_T_15 = dshr(lower_mask_1, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_1_T_16 = or(_f3_fetch_bundle_sfb_masks_1_T, _f3_fetch_bundle_sfb_masks_1_T_1) node _f3_fetch_bundle_sfb_masks_1_T_17 = or(_f3_fetch_bundle_sfb_masks_1_T_16, _f3_fetch_bundle_sfb_masks_1_T_2) node _f3_fetch_bundle_sfb_masks_1_T_18 = or(_f3_fetch_bundle_sfb_masks_1_T_17, _f3_fetch_bundle_sfb_masks_1_T_3) node _f3_fetch_bundle_sfb_masks_1_T_19 = or(_f3_fetch_bundle_sfb_masks_1_T_18, _f3_fetch_bundle_sfb_masks_1_T_4) node _f3_fetch_bundle_sfb_masks_1_T_20 = or(_f3_fetch_bundle_sfb_masks_1_T_19, _f3_fetch_bundle_sfb_masks_1_T_5) node _f3_fetch_bundle_sfb_masks_1_T_21 = or(_f3_fetch_bundle_sfb_masks_1_T_20, _f3_fetch_bundle_sfb_masks_1_T_6) node _f3_fetch_bundle_sfb_masks_1_T_22 = or(_f3_fetch_bundle_sfb_masks_1_T_21, _f3_fetch_bundle_sfb_masks_1_T_7) node _f3_fetch_bundle_sfb_masks_1_T_23 = or(_f3_fetch_bundle_sfb_masks_1_T_22, _f3_fetch_bundle_sfb_masks_1_T_8) node _f3_fetch_bundle_sfb_masks_1_T_24 = or(_f3_fetch_bundle_sfb_masks_1_T_23, _f3_fetch_bundle_sfb_masks_1_T_9) node _f3_fetch_bundle_sfb_masks_1_T_25 = or(_f3_fetch_bundle_sfb_masks_1_T_24, _f3_fetch_bundle_sfb_masks_1_T_10) node _f3_fetch_bundle_sfb_masks_1_T_26 = or(_f3_fetch_bundle_sfb_masks_1_T_25, _f3_fetch_bundle_sfb_masks_1_T_11) node _f3_fetch_bundle_sfb_masks_1_T_27 = or(_f3_fetch_bundle_sfb_masks_1_T_26, _f3_fetch_bundle_sfb_masks_1_T_12) node _f3_fetch_bundle_sfb_masks_1_T_28 = or(_f3_fetch_bundle_sfb_masks_1_T_27, _f3_fetch_bundle_sfb_masks_1_T_13) node _f3_fetch_bundle_sfb_masks_1_T_29 = or(_f3_fetch_bundle_sfb_masks_1_T_28, _f3_fetch_bundle_sfb_masks_1_T_14) node _f3_fetch_bundle_sfb_masks_1_T_30 = or(_f3_fetch_bundle_sfb_masks_1_T_29, _f3_fetch_bundle_sfb_masks_1_T_15) node _f3_fetch_bundle_sfb_masks_1_T_31 = not(_f3_fetch_bundle_sfb_masks_1_T_30) node _f3_fetch_bundle_sfb_masks_1_T_32 = dshl(upper_mask_1, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_1_T_33 = bits(_f3_fetch_bundle_sfb_masks_1_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_34 = dshl(upper_mask_1, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_1_T_35 = bits(_f3_fetch_bundle_sfb_masks_1_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_36 = dshl(upper_mask_1, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_1_T_37 = bits(_f3_fetch_bundle_sfb_masks_1_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_38 = dshl(upper_mask_1, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_1_T_39 = bits(_f3_fetch_bundle_sfb_masks_1_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_40 = dshl(upper_mask_1, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_1_T_41 = bits(_f3_fetch_bundle_sfb_masks_1_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_42 = dshl(upper_mask_1, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_1_T_43 = bits(_f3_fetch_bundle_sfb_masks_1_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_44 = dshl(upper_mask_1, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_1_T_45 = bits(_f3_fetch_bundle_sfb_masks_1_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_46 = dshl(upper_mask_1, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_1_T_47 = bits(_f3_fetch_bundle_sfb_masks_1_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_48 = dshl(upper_mask_1, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_1_T_49 = bits(_f3_fetch_bundle_sfb_masks_1_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_50 = dshl(upper_mask_1, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_1_T_51 = bits(_f3_fetch_bundle_sfb_masks_1_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_52 = dshl(upper_mask_1, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_1_T_53 = bits(_f3_fetch_bundle_sfb_masks_1_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_54 = dshl(upper_mask_1, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_1_T_55 = bits(_f3_fetch_bundle_sfb_masks_1_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_56 = dshl(upper_mask_1, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_1_T_57 = bits(_f3_fetch_bundle_sfb_masks_1_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_58 = dshl(upper_mask_1, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_1_T_59 = bits(_f3_fetch_bundle_sfb_masks_1_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_60 = dshl(upper_mask_1, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_1_T_61 = bits(_f3_fetch_bundle_sfb_masks_1_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_62 = dshl(upper_mask_1, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_1_T_63 = bits(_f3_fetch_bundle_sfb_masks_1_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_64 = or(_f3_fetch_bundle_sfb_masks_1_T_33, _f3_fetch_bundle_sfb_masks_1_T_35) node _f3_fetch_bundle_sfb_masks_1_T_65 = or(_f3_fetch_bundle_sfb_masks_1_T_64, _f3_fetch_bundle_sfb_masks_1_T_37) node _f3_fetch_bundle_sfb_masks_1_T_66 = or(_f3_fetch_bundle_sfb_masks_1_T_65, _f3_fetch_bundle_sfb_masks_1_T_39) node _f3_fetch_bundle_sfb_masks_1_T_67 = or(_f3_fetch_bundle_sfb_masks_1_T_66, _f3_fetch_bundle_sfb_masks_1_T_41) node _f3_fetch_bundle_sfb_masks_1_T_68 = or(_f3_fetch_bundle_sfb_masks_1_T_67, _f3_fetch_bundle_sfb_masks_1_T_43) node _f3_fetch_bundle_sfb_masks_1_T_69 = or(_f3_fetch_bundle_sfb_masks_1_T_68, _f3_fetch_bundle_sfb_masks_1_T_45) node _f3_fetch_bundle_sfb_masks_1_T_70 = or(_f3_fetch_bundle_sfb_masks_1_T_69, _f3_fetch_bundle_sfb_masks_1_T_47) node _f3_fetch_bundle_sfb_masks_1_T_71 = or(_f3_fetch_bundle_sfb_masks_1_T_70, _f3_fetch_bundle_sfb_masks_1_T_49) node _f3_fetch_bundle_sfb_masks_1_T_72 = or(_f3_fetch_bundle_sfb_masks_1_T_71, _f3_fetch_bundle_sfb_masks_1_T_51) node _f3_fetch_bundle_sfb_masks_1_T_73 = or(_f3_fetch_bundle_sfb_masks_1_T_72, _f3_fetch_bundle_sfb_masks_1_T_53) node _f3_fetch_bundle_sfb_masks_1_T_74 = or(_f3_fetch_bundle_sfb_masks_1_T_73, _f3_fetch_bundle_sfb_masks_1_T_55) node _f3_fetch_bundle_sfb_masks_1_T_75 = or(_f3_fetch_bundle_sfb_masks_1_T_74, _f3_fetch_bundle_sfb_masks_1_T_57) node _f3_fetch_bundle_sfb_masks_1_T_76 = or(_f3_fetch_bundle_sfb_masks_1_T_75, _f3_fetch_bundle_sfb_masks_1_T_59) node _f3_fetch_bundle_sfb_masks_1_T_77 = or(_f3_fetch_bundle_sfb_masks_1_T_76, _f3_fetch_bundle_sfb_masks_1_T_61) node _f3_fetch_bundle_sfb_masks_1_T_78 = or(_f3_fetch_bundle_sfb_masks_1_T_77, _f3_fetch_bundle_sfb_masks_1_T_63) node _f3_fetch_bundle_sfb_masks_1_T_79 = not(_f3_fetch_bundle_sfb_masks_1_T_78) node _f3_fetch_bundle_sfb_masks_1_T_80 = and(_f3_fetch_bundle_sfb_masks_1_T_31, _f3_fetch_bundle_sfb_masks_1_T_79) connect f3_fetch_bundle.sfb_masks[1], _f3_fetch_bundle_sfb_masks_1_T_80 node _f3_fetch_bundle_shadowable_mask_1_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_1_T_1 = or(_f3_fetch_bundle_shadowable_mask_1_T, bpu_1.io.debug_if) node _f3_fetch_bundle_shadowable_mask_1_T_2 = or(_f3_fetch_bundle_shadowable_mask_1_T_1, bpu_1.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_1_T_3 = eq(_f3_fetch_bundle_shadowable_mask_1_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_1_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_1_T_5 = and(_f3_fetch_bundle_shadowable_mask_1_T_3, _f3_fetch_bundle_shadowable_mask_1_T_4) node _f3_fetch_bundle_shadowable_mask_1_T_6 = eq(f3_mask[1], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_1_T_7 = or(brsigs_1.shadowable, _f3_fetch_bundle_shadowable_mask_1_T_6) node _f3_fetch_bundle_shadowable_mask_1_T_8 = and(_f3_fetch_bundle_shadowable_mask_1_T_5, _f3_fetch_bundle_shadowable_mask_1_T_7) connect f3_fetch_bundle.shadowable_mask[1], _f3_fetch_bundle_shadowable_mask_1_T_8 connect f3_fetch_bundle.sfb_dests[1], offset_from_aligned_pc_1 node _f3_redirects_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h2)) node _f3_redirects_1_T_1 = eq(brsigs_1.cfi_type, UInt<3>(0h3)) node _f3_redirects_1_T_2 = or(_f3_redirects_1_T, _f3_redirects_1_T_1) node _f3_redirects_1_T_3 = eq(brsigs_1.cfi_type, UInt<3>(0h1)) node _f3_redirects_1_T_4 = and(_f3_redirects_1_T_3, f3_bpd_resp.io.deq.bits.preds[1].taken) node _f3_redirects_1_T_5 = and(_f3_redirects_1_T_4, UInt<1>(0h1)) node _f3_redirects_1_T_6 = or(_f3_redirects_1_T_2, _f3_redirects_1_T_5) node _f3_redirects_1_T_7 = and(f3_mask[1], _f3_redirects_1_T_6) connect f3_redirects[1], _f3_redirects_1_T_7 node _f3_br_mask_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h1)) node _f3_br_mask_1_T_1 = and(f3_mask[1], _f3_br_mask_1_T) connect f3_br_mask[1], _f3_br_mask_1_T_1 connect f3_cfi_types[1], brsigs_1.cfi_type connect f3_call_mask[1], brsigs_1.is_call connect f3_ret_mask[1], brsigs_1.is_ret connect f3_fetch_bundle.bp_debug_if_oh[1], bpu_1.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[1], bpu_1.io.xcpt_if node _T_29 = or(_T_28, f3_redirects[1]) wire valid_2 : UInt<1> inst bpu_2 of BreakpointUnit_13 connect bpu_2.clock, clock connect bpu_2.reset, reset connect bpu_2.io.status.uie, io.cpu.status.uie connect bpu_2.io.status.sie, io.cpu.status.sie connect bpu_2.io.status.hie, io.cpu.status.hie connect bpu_2.io.status.mie, io.cpu.status.mie connect bpu_2.io.status.upie, io.cpu.status.upie connect bpu_2.io.status.spie, io.cpu.status.spie connect bpu_2.io.status.ube, io.cpu.status.ube connect bpu_2.io.status.mpie, io.cpu.status.mpie connect bpu_2.io.status.spp, io.cpu.status.spp connect bpu_2.io.status.vs, io.cpu.status.vs connect bpu_2.io.status.mpp, io.cpu.status.mpp connect bpu_2.io.status.fs, io.cpu.status.fs connect bpu_2.io.status.xs, io.cpu.status.xs connect bpu_2.io.status.mprv, io.cpu.status.mprv connect bpu_2.io.status.sum, io.cpu.status.sum connect bpu_2.io.status.mxr, io.cpu.status.mxr connect bpu_2.io.status.tvm, io.cpu.status.tvm connect bpu_2.io.status.tw, io.cpu.status.tw connect bpu_2.io.status.tsr, io.cpu.status.tsr connect bpu_2.io.status.zero1, io.cpu.status.zero1 connect bpu_2.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_2.io.status.uxl, io.cpu.status.uxl connect bpu_2.io.status.sxl, io.cpu.status.sxl connect bpu_2.io.status.sbe, io.cpu.status.sbe connect bpu_2.io.status.mbe, io.cpu.status.mbe connect bpu_2.io.status.gva, io.cpu.status.gva connect bpu_2.io.status.mpv, io.cpu.status.mpv connect bpu_2.io.status.zero2, io.cpu.status.zero2 connect bpu_2.io.status.sd, io.cpu.status.sd connect bpu_2.io.status.v, io.cpu.status.v connect bpu_2.io.status.prv, io.cpu.status.prv connect bpu_2.io.status.dv, io.cpu.status.dv connect bpu_2.io.status.dprv, io.cpu.status.dprv connect bpu_2.io.status.isa, io.cpu.status.isa connect bpu_2.io.status.wfi, io.cpu.status.wfi connect bpu_2.io.status.cease, io.cpu.status.cease connect bpu_2.io.status.debug, io.cpu.status.debug invalidate bpu_2.io.ea connect bpu_2.io.mcontext, io.cpu.mcontext connect bpu_2.io.scontext, io.cpu.scontext wire brsigs_2 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_1 : UInt<32> inst exp_inst_rvc_exp_1 of RVCExpander_16 connect exp_inst_rvc_exp_1.clock, clock connect exp_inst_rvc_exp_1.reset, reset connect exp_inst_rvc_exp_1.io.in, inst_1 node exp_inst_1 = mux(exp_inst_rvc_exp_1.io.rvc, exp_inst_rvc_exp_1.io.out.bits, inst_1) node _pc_T_1 = add(f3_aligned_pc, UInt<3>(0h4)) node pc_1 = tail(_pc_T_1, 1) inst bpd_decoder_1 of BranchDecode_14 connect bpd_decoder_1.clock, clock connect bpd_decoder_1.reset, reset connect bpd_decoder_1.io.inst, exp_inst_1 connect bpd_decoder_1.io.pc, pc_1 connect bank_insts[2], inst_1 connect f3_fetch_bundle.insts[2], inst_1 connect f3_fetch_bundle.exp_insts[2], exp_inst_1 connect bpu_2.io.pc, pc_1 connect brsigs_2.shadowable, bpd_decoder_1.io.out.shadowable connect brsigs_2.sfb_offset, bpd_decoder_1.io.out.sfb_offset connect brsigs_2.cfi_type, bpd_decoder_1.io.out.cfi_type connect brsigs_2.target, bpd_decoder_1.io.out.target connect brsigs_2.is_call, bpd_decoder_1.io.out.is_call connect brsigs_2.is_ret, bpd_decoder_1.io.out.is_ret node _inst_T_1 = bits(bank_data, 63, 32) connect inst_1, _inst_T_1 node _valid_T_6 = bits(bank_insts[1], 1, 0) node _valid_T_7 = neq(_valid_T_6, UInt<2>(0h3)) node _valid_T_8 = eq(_valid_T_7, UInt<1>(0h0)) node _valid_T_9 = and(bank_mask[1], _valid_T_8) node _valid_T_10 = eq(_valid_T_9, UInt<1>(0h0)) connect valid_2, _valid_T_10 node _f3_is_rvc_2_T = bits(bank_insts[2], 1, 0) node _f3_is_rvc_2_T_1 = neq(_f3_is_rvc_2_T, UInt<2>(0h3)) connect f3_is_rvc[2], _f3_is_rvc_2_T_1 node _bank_mask_2_T = bits(f3.io.deq.bits.mask, 2, 2) node _bank_mask_2_T_1 = and(f3.io.deq.valid, _bank_mask_2_T) node _bank_mask_2_T_2 = and(_bank_mask_2_T_1, valid_2) node _bank_mask_2_T_3 = eq(_T_29, UInt<1>(0h0)) node _bank_mask_2_T_4 = and(_bank_mask_2_T_2, _bank_mask_2_T_3) connect bank_mask[2], _bank_mask_2_T_4 node _f3_mask_2_T = bits(f3.io.deq.bits.mask, 2, 2) node _f3_mask_2_T_1 = and(f3.io.deq.valid, _f3_mask_2_T) node _f3_mask_2_T_2 = and(_f3_mask_2_T_1, valid_2) node _f3_mask_2_T_3 = eq(_T_29, UInt<1>(0h0)) node _f3_mask_2_T_4 = and(_f3_mask_2_T_2, _f3_mask_2_T_3) connect f3_mask[2], _f3_mask_2_T_4 node _f3_targs_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h3)) node _f3_targs_2_T_1 = mux(_f3_targs_2_T, f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.bits, brsigs_2.target) connect f3_targs[2], _f3_targs_2_T_1 node _f3_btb_mispredicts_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_2_T_1 = and(_f3_btb_mispredicts_2_T, valid_2) node _f3_btb_mispredicts_2_T_2 = and(_f3_btb_mispredicts_2_T_1, f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.valid) node _f3_btb_mispredicts_2_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.bits, brsigs_2.target) node _f3_btb_mispredicts_2_T_4 = and(_f3_btb_mispredicts_2_T_2, _f3_btb_mispredicts_2_T_3) connect f3_btb_mispredicts[2], _f3_btb_mispredicts_2_T_4 node _f3_npc_plus4_mask_2_T = eq(f3_is_rvc[2], UInt<1>(0h0)) connect f3_npc_plus4_mask[2], _f3_npc_plus4_mask_2_T node _offset_from_aligned_pc_T_10 = add(UInt<7>(0h4), brsigs_2.sfb_offset.bits) node _offset_from_aligned_pc_T_11 = tail(_offset_from_aligned_pc_T_10, 1) node _offset_from_aligned_pc_T_12 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_13 = mux(_offset_from_aligned_pc_T_12, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_14 = sub(_offset_from_aligned_pc_T_11, _offset_from_aligned_pc_T_13) node offset_from_aligned_pc_2 = tail(_offset_from_aligned_pc_T_14, 1) wire lower_mask_2 : UInt<16> wire upper_mask_2 : UInt<16> node _lower_mask_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) connect lower_mask_2, _lower_mask_T_2 node _upper_mask_T_8 = bits(offset_from_aligned_pc_2, 5, 1) node _upper_mask_T_9 = dshl(UInt<1>(0h1), _upper_mask_T_8) node _upper_mask_T_10 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_11 = dshl(_upper_mask_T_9, _upper_mask_T_10) connect upper_mask_2, _upper_mask_T_11 node _f3_fetch_bundle_sfbs_2_T = and(f3_mask[2], brsigs_2.sfb_offset.valid) node _f3_fetch_bundle_sfbs_2_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_2_T_2 = leq(offset_from_aligned_pc_2, _f3_fetch_bundle_sfbs_2_T_1) node _f3_fetch_bundle_sfbs_2_T_3 = and(_f3_fetch_bundle_sfbs_2_T, _f3_fetch_bundle_sfbs_2_T_2) connect f3_fetch_bundle.sfbs[2], _f3_fetch_bundle_sfbs_2_T_3 node _f3_fetch_bundle_sfb_masks_2_T = dshr(lower_mask_2, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_2_T_1 = dshr(lower_mask_2, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_2_T_2 = dshr(lower_mask_2, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_2_T_3 = dshr(lower_mask_2, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_2_T_4 = dshr(lower_mask_2, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_2_T_5 = dshr(lower_mask_2, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_2_T_6 = dshr(lower_mask_2, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_2_T_7 = dshr(lower_mask_2, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_2_T_8 = dshr(lower_mask_2, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_2_T_9 = dshr(lower_mask_2, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_2_T_10 = dshr(lower_mask_2, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_2_T_11 = dshr(lower_mask_2, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_2_T_12 = dshr(lower_mask_2, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_2_T_13 = dshr(lower_mask_2, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_2_T_14 = dshr(lower_mask_2, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_2_T_15 = dshr(lower_mask_2, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_2_T_16 = or(_f3_fetch_bundle_sfb_masks_2_T, _f3_fetch_bundle_sfb_masks_2_T_1) node _f3_fetch_bundle_sfb_masks_2_T_17 = or(_f3_fetch_bundle_sfb_masks_2_T_16, _f3_fetch_bundle_sfb_masks_2_T_2) node _f3_fetch_bundle_sfb_masks_2_T_18 = or(_f3_fetch_bundle_sfb_masks_2_T_17, _f3_fetch_bundle_sfb_masks_2_T_3) node _f3_fetch_bundle_sfb_masks_2_T_19 = or(_f3_fetch_bundle_sfb_masks_2_T_18, _f3_fetch_bundle_sfb_masks_2_T_4) node _f3_fetch_bundle_sfb_masks_2_T_20 = or(_f3_fetch_bundle_sfb_masks_2_T_19, _f3_fetch_bundle_sfb_masks_2_T_5) node _f3_fetch_bundle_sfb_masks_2_T_21 = or(_f3_fetch_bundle_sfb_masks_2_T_20, _f3_fetch_bundle_sfb_masks_2_T_6) node _f3_fetch_bundle_sfb_masks_2_T_22 = or(_f3_fetch_bundle_sfb_masks_2_T_21, _f3_fetch_bundle_sfb_masks_2_T_7) node _f3_fetch_bundle_sfb_masks_2_T_23 = or(_f3_fetch_bundle_sfb_masks_2_T_22, _f3_fetch_bundle_sfb_masks_2_T_8) node _f3_fetch_bundle_sfb_masks_2_T_24 = or(_f3_fetch_bundle_sfb_masks_2_T_23, _f3_fetch_bundle_sfb_masks_2_T_9) node _f3_fetch_bundle_sfb_masks_2_T_25 = or(_f3_fetch_bundle_sfb_masks_2_T_24, _f3_fetch_bundle_sfb_masks_2_T_10) node _f3_fetch_bundle_sfb_masks_2_T_26 = or(_f3_fetch_bundle_sfb_masks_2_T_25, _f3_fetch_bundle_sfb_masks_2_T_11) node _f3_fetch_bundle_sfb_masks_2_T_27 = or(_f3_fetch_bundle_sfb_masks_2_T_26, _f3_fetch_bundle_sfb_masks_2_T_12) node _f3_fetch_bundle_sfb_masks_2_T_28 = or(_f3_fetch_bundle_sfb_masks_2_T_27, _f3_fetch_bundle_sfb_masks_2_T_13) node _f3_fetch_bundle_sfb_masks_2_T_29 = or(_f3_fetch_bundle_sfb_masks_2_T_28, _f3_fetch_bundle_sfb_masks_2_T_14) node _f3_fetch_bundle_sfb_masks_2_T_30 = or(_f3_fetch_bundle_sfb_masks_2_T_29, _f3_fetch_bundle_sfb_masks_2_T_15) node _f3_fetch_bundle_sfb_masks_2_T_31 = not(_f3_fetch_bundle_sfb_masks_2_T_30) node _f3_fetch_bundle_sfb_masks_2_T_32 = dshl(upper_mask_2, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_2_T_33 = bits(_f3_fetch_bundle_sfb_masks_2_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_34 = dshl(upper_mask_2, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_2_T_35 = bits(_f3_fetch_bundle_sfb_masks_2_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_36 = dshl(upper_mask_2, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_2_T_37 = bits(_f3_fetch_bundle_sfb_masks_2_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_38 = dshl(upper_mask_2, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_2_T_39 = bits(_f3_fetch_bundle_sfb_masks_2_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_40 = dshl(upper_mask_2, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_2_T_41 = bits(_f3_fetch_bundle_sfb_masks_2_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_42 = dshl(upper_mask_2, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_2_T_43 = bits(_f3_fetch_bundle_sfb_masks_2_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_44 = dshl(upper_mask_2, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_2_T_45 = bits(_f3_fetch_bundle_sfb_masks_2_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_46 = dshl(upper_mask_2, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_2_T_47 = bits(_f3_fetch_bundle_sfb_masks_2_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_48 = dshl(upper_mask_2, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_2_T_49 = bits(_f3_fetch_bundle_sfb_masks_2_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_50 = dshl(upper_mask_2, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_2_T_51 = bits(_f3_fetch_bundle_sfb_masks_2_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_52 = dshl(upper_mask_2, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_2_T_53 = bits(_f3_fetch_bundle_sfb_masks_2_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_54 = dshl(upper_mask_2, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_2_T_55 = bits(_f3_fetch_bundle_sfb_masks_2_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_56 = dshl(upper_mask_2, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_2_T_57 = bits(_f3_fetch_bundle_sfb_masks_2_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_58 = dshl(upper_mask_2, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_2_T_59 = bits(_f3_fetch_bundle_sfb_masks_2_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_60 = dshl(upper_mask_2, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_2_T_61 = bits(_f3_fetch_bundle_sfb_masks_2_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_62 = dshl(upper_mask_2, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_2_T_63 = bits(_f3_fetch_bundle_sfb_masks_2_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_64 = or(_f3_fetch_bundle_sfb_masks_2_T_33, _f3_fetch_bundle_sfb_masks_2_T_35) node _f3_fetch_bundle_sfb_masks_2_T_65 = or(_f3_fetch_bundle_sfb_masks_2_T_64, _f3_fetch_bundle_sfb_masks_2_T_37) node _f3_fetch_bundle_sfb_masks_2_T_66 = or(_f3_fetch_bundle_sfb_masks_2_T_65, _f3_fetch_bundle_sfb_masks_2_T_39) node _f3_fetch_bundle_sfb_masks_2_T_67 = or(_f3_fetch_bundle_sfb_masks_2_T_66, _f3_fetch_bundle_sfb_masks_2_T_41) node _f3_fetch_bundle_sfb_masks_2_T_68 = or(_f3_fetch_bundle_sfb_masks_2_T_67, _f3_fetch_bundle_sfb_masks_2_T_43) node _f3_fetch_bundle_sfb_masks_2_T_69 = or(_f3_fetch_bundle_sfb_masks_2_T_68, _f3_fetch_bundle_sfb_masks_2_T_45) node _f3_fetch_bundle_sfb_masks_2_T_70 = or(_f3_fetch_bundle_sfb_masks_2_T_69, _f3_fetch_bundle_sfb_masks_2_T_47) node _f3_fetch_bundle_sfb_masks_2_T_71 = or(_f3_fetch_bundle_sfb_masks_2_T_70, _f3_fetch_bundle_sfb_masks_2_T_49) node _f3_fetch_bundle_sfb_masks_2_T_72 = or(_f3_fetch_bundle_sfb_masks_2_T_71, _f3_fetch_bundle_sfb_masks_2_T_51) node _f3_fetch_bundle_sfb_masks_2_T_73 = or(_f3_fetch_bundle_sfb_masks_2_T_72, _f3_fetch_bundle_sfb_masks_2_T_53) node _f3_fetch_bundle_sfb_masks_2_T_74 = or(_f3_fetch_bundle_sfb_masks_2_T_73, _f3_fetch_bundle_sfb_masks_2_T_55) node _f3_fetch_bundle_sfb_masks_2_T_75 = or(_f3_fetch_bundle_sfb_masks_2_T_74, _f3_fetch_bundle_sfb_masks_2_T_57) node _f3_fetch_bundle_sfb_masks_2_T_76 = or(_f3_fetch_bundle_sfb_masks_2_T_75, _f3_fetch_bundle_sfb_masks_2_T_59) node _f3_fetch_bundle_sfb_masks_2_T_77 = or(_f3_fetch_bundle_sfb_masks_2_T_76, _f3_fetch_bundle_sfb_masks_2_T_61) node _f3_fetch_bundle_sfb_masks_2_T_78 = or(_f3_fetch_bundle_sfb_masks_2_T_77, _f3_fetch_bundle_sfb_masks_2_T_63) node _f3_fetch_bundle_sfb_masks_2_T_79 = not(_f3_fetch_bundle_sfb_masks_2_T_78) node _f3_fetch_bundle_sfb_masks_2_T_80 = and(_f3_fetch_bundle_sfb_masks_2_T_31, _f3_fetch_bundle_sfb_masks_2_T_79) connect f3_fetch_bundle.sfb_masks[2], _f3_fetch_bundle_sfb_masks_2_T_80 node _f3_fetch_bundle_shadowable_mask_2_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_2_T_1 = or(_f3_fetch_bundle_shadowable_mask_2_T, bpu_2.io.debug_if) node _f3_fetch_bundle_shadowable_mask_2_T_2 = or(_f3_fetch_bundle_shadowable_mask_2_T_1, bpu_2.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_2_T_3 = eq(_f3_fetch_bundle_shadowable_mask_2_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_2_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_2_T_5 = and(_f3_fetch_bundle_shadowable_mask_2_T_3, _f3_fetch_bundle_shadowable_mask_2_T_4) node _f3_fetch_bundle_shadowable_mask_2_T_6 = eq(f3_mask[2], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_2_T_7 = or(brsigs_2.shadowable, _f3_fetch_bundle_shadowable_mask_2_T_6) node _f3_fetch_bundle_shadowable_mask_2_T_8 = and(_f3_fetch_bundle_shadowable_mask_2_T_5, _f3_fetch_bundle_shadowable_mask_2_T_7) connect f3_fetch_bundle.shadowable_mask[2], _f3_fetch_bundle_shadowable_mask_2_T_8 connect f3_fetch_bundle.sfb_dests[2], offset_from_aligned_pc_2 node _f3_redirects_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h2)) node _f3_redirects_2_T_1 = eq(brsigs_2.cfi_type, UInt<3>(0h3)) node _f3_redirects_2_T_2 = or(_f3_redirects_2_T, _f3_redirects_2_T_1) node _f3_redirects_2_T_3 = eq(brsigs_2.cfi_type, UInt<3>(0h1)) node _f3_redirects_2_T_4 = and(_f3_redirects_2_T_3, f3_bpd_resp.io.deq.bits.preds[2].taken) node _f3_redirects_2_T_5 = and(_f3_redirects_2_T_4, UInt<1>(0h1)) node _f3_redirects_2_T_6 = or(_f3_redirects_2_T_2, _f3_redirects_2_T_5) node _f3_redirects_2_T_7 = and(f3_mask[2], _f3_redirects_2_T_6) connect f3_redirects[2], _f3_redirects_2_T_7 node _f3_br_mask_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h1)) node _f3_br_mask_2_T_1 = and(f3_mask[2], _f3_br_mask_2_T) connect f3_br_mask[2], _f3_br_mask_2_T_1 connect f3_cfi_types[2], brsigs_2.cfi_type connect f3_call_mask[2], brsigs_2.is_call connect f3_ret_mask[2], brsigs_2.is_ret connect f3_fetch_bundle.bp_debug_if_oh[2], bpu_2.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[2], bpu_2.io.xcpt_if node _T_30 = or(_T_29, f3_redirects[2]) wire valid_3 : UInt<1> inst bpu_3 of BreakpointUnit_14 connect bpu_3.clock, clock connect bpu_3.reset, reset connect bpu_3.io.status.uie, io.cpu.status.uie connect bpu_3.io.status.sie, io.cpu.status.sie connect bpu_3.io.status.hie, io.cpu.status.hie connect bpu_3.io.status.mie, io.cpu.status.mie connect bpu_3.io.status.upie, io.cpu.status.upie connect bpu_3.io.status.spie, io.cpu.status.spie connect bpu_3.io.status.ube, io.cpu.status.ube connect bpu_3.io.status.mpie, io.cpu.status.mpie connect bpu_3.io.status.spp, io.cpu.status.spp connect bpu_3.io.status.vs, io.cpu.status.vs connect bpu_3.io.status.mpp, io.cpu.status.mpp connect bpu_3.io.status.fs, io.cpu.status.fs connect bpu_3.io.status.xs, io.cpu.status.xs connect bpu_3.io.status.mprv, io.cpu.status.mprv connect bpu_3.io.status.sum, io.cpu.status.sum connect bpu_3.io.status.mxr, io.cpu.status.mxr connect bpu_3.io.status.tvm, io.cpu.status.tvm connect bpu_3.io.status.tw, io.cpu.status.tw connect bpu_3.io.status.tsr, io.cpu.status.tsr connect bpu_3.io.status.zero1, io.cpu.status.zero1 connect bpu_3.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_3.io.status.uxl, io.cpu.status.uxl connect bpu_3.io.status.sxl, io.cpu.status.sxl connect bpu_3.io.status.sbe, io.cpu.status.sbe connect bpu_3.io.status.mbe, io.cpu.status.mbe connect bpu_3.io.status.gva, io.cpu.status.gva connect bpu_3.io.status.mpv, io.cpu.status.mpv connect bpu_3.io.status.zero2, io.cpu.status.zero2 connect bpu_3.io.status.sd, io.cpu.status.sd connect bpu_3.io.status.v, io.cpu.status.v connect bpu_3.io.status.prv, io.cpu.status.prv connect bpu_3.io.status.dv, io.cpu.status.dv connect bpu_3.io.status.dprv, io.cpu.status.dprv connect bpu_3.io.status.isa, io.cpu.status.isa connect bpu_3.io.status.wfi, io.cpu.status.wfi connect bpu_3.io.status.cease, io.cpu.status.cease connect bpu_3.io.status.debug, io.cpu.status.debug invalidate bpu_3.io.ea connect bpu_3.io.mcontext, io.cpu.mcontext connect bpu_3.io.scontext, io.cpu.scontext wire brsigs_3 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_2 : UInt<32> inst exp_inst_rvc_exp_2 of RVCExpander_17 connect exp_inst_rvc_exp_2.clock, clock connect exp_inst_rvc_exp_2.reset, reset connect exp_inst_rvc_exp_2.io.in, inst_2 node exp_inst_2 = mux(exp_inst_rvc_exp_2.io.rvc, exp_inst_rvc_exp_2.io.out.bits, inst_2) node _pc_T_2 = add(f3_aligned_pc, UInt<3>(0h6)) node pc_2 = tail(_pc_T_2, 1) inst bpd_decoder_2 of BranchDecode_15 connect bpd_decoder_2.clock, clock connect bpd_decoder_2.reset, reset connect bpd_decoder_2.io.inst, exp_inst_2 connect bpd_decoder_2.io.pc, pc_2 connect bank_insts[3], inst_2 connect f3_fetch_bundle.insts[3], inst_2 connect f3_fetch_bundle.exp_insts[3], exp_inst_2 connect bpu_3.io.pc, pc_2 connect brsigs_3.shadowable, bpd_decoder_2.io.out.shadowable connect brsigs_3.sfb_offset, bpd_decoder_2.io.out.sfb_offset connect brsigs_3.cfi_type, bpd_decoder_2.io.out.cfi_type connect brsigs_3.target, bpd_decoder_2.io.out.target connect brsigs_3.is_call, bpd_decoder_2.io.out.is_call connect brsigs_3.is_ret, bpd_decoder_2.io.out.is_ret node _inst_T_2 = bits(bank_data, 63, 48) node _inst_T_3 = cat(UInt<16>(0h0), _inst_T_2) connect inst_2, _inst_T_3 node _valid_T_11 = bits(bank_insts[2], 1, 0) node _valid_T_12 = neq(_valid_T_11, UInt<2>(0h3)) node _valid_T_13 = eq(_valid_T_12, UInt<1>(0h0)) node _valid_T_14 = and(bank_mask[2], _valid_T_13) node _valid_T_15 = bits(inst_2, 1, 0) node _valid_T_16 = neq(_valid_T_15, UInt<2>(0h3)) node _valid_T_17 = eq(_valid_T_16, UInt<1>(0h0)) node _valid_T_18 = or(_valid_T_14, _valid_T_17) node _valid_T_19 = eq(_valid_T_18, UInt<1>(0h0)) connect valid_3, _valid_T_19 node _f3_is_rvc_3_T = bits(bank_insts[3], 1, 0) node _f3_is_rvc_3_T_1 = neq(_f3_is_rvc_3_T, UInt<2>(0h3)) connect f3_is_rvc[3], _f3_is_rvc_3_T_1 node _bank_mask_3_T = bits(f3.io.deq.bits.mask, 3, 3) node _bank_mask_3_T_1 = and(f3.io.deq.valid, _bank_mask_3_T) node _bank_mask_3_T_2 = and(_bank_mask_3_T_1, valid_3) node _bank_mask_3_T_3 = eq(_T_30, UInt<1>(0h0)) node _bank_mask_3_T_4 = and(_bank_mask_3_T_2, _bank_mask_3_T_3) connect bank_mask[3], _bank_mask_3_T_4 node _f3_mask_3_T = bits(f3.io.deq.bits.mask, 3, 3) node _f3_mask_3_T_1 = and(f3.io.deq.valid, _f3_mask_3_T) node _f3_mask_3_T_2 = and(_f3_mask_3_T_1, valid_3) node _f3_mask_3_T_3 = eq(_T_30, UInt<1>(0h0)) node _f3_mask_3_T_4 = and(_f3_mask_3_T_2, _f3_mask_3_T_3) connect f3_mask[3], _f3_mask_3_T_4 node _f3_targs_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h3)) node _f3_targs_3_T_1 = mux(_f3_targs_3_T, f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.bits, brsigs_3.target) connect f3_targs[3], _f3_targs_3_T_1 node _f3_btb_mispredicts_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_3_T_1 = and(_f3_btb_mispredicts_3_T, valid_3) node _f3_btb_mispredicts_3_T_2 = and(_f3_btb_mispredicts_3_T_1, f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.valid) node _f3_btb_mispredicts_3_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.bits, brsigs_3.target) node _f3_btb_mispredicts_3_T_4 = and(_f3_btb_mispredicts_3_T_2, _f3_btb_mispredicts_3_T_3) connect f3_btb_mispredicts[3], _f3_btb_mispredicts_3_T_4 node _f3_npc_plus4_mask_3_T = eq(f3_is_rvc[3], UInt<1>(0h0)) connect f3_npc_plus4_mask[3], _f3_npc_plus4_mask_3_T node _offset_from_aligned_pc_T_15 = add(UInt<7>(0h6), brsigs_3.sfb_offset.bits) node _offset_from_aligned_pc_T_16 = tail(_offset_from_aligned_pc_T_15, 1) node _offset_from_aligned_pc_T_17 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_18 = mux(_offset_from_aligned_pc_T_17, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_19 = sub(_offset_from_aligned_pc_T_16, _offset_from_aligned_pc_T_18) node offset_from_aligned_pc_3 = tail(_offset_from_aligned_pc_T_19, 1) wire lower_mask_3 : UInt<16> wire upper_mask_3 : UInt<16> node _lower_mask_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3)) connect lower_mask_3, _lower_mask_T_3 node _upper_mask_T_12 = bits(offset_from_aligned_pc_3, 5, 1) node _upper_mask_T_13 = dshl(UInt<1>(0h1), _upper_mask_T_12) node _upper_mask_T_14 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_15 = dshl(_upper_mask_T_13, _upper_mask_T_14) connect upper_mask_3, _upper_mask_T_15 node _f3_fetch_bundle_sfbs_3_T = and(f3_mask[3], brsigs_3.sfb_offset.valid) node _f3_fetch_bundle_sfbs_3_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_3_T_2 = leq(offset_from_aligned_pc_3, _f3_fetch_bundle_sfbs_3_T_1) node _f3_fetch_bundle_sfbs_3_T_3 = and(_f3_fetch_bundle_sfbs_3_T, _f3_fetch_bundle_sfbs_3_T_2) connect f3_fetch_bundle.sfbs[3], _f3_fetch_bundle_sfbs_3_T_3 node _f3_fetch_bundle_sfb_masks_3_T = dshr(lower_mask_3, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_3_T_1 = dshr(lower_mask_3, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_3_T_2 = dshr(lower_mask_3, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_3_T_3 = dshr(lower_mask_3, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_3_T_4 = dshr(lower_mask_3, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_3_T_5 = dshr(lower_mask_3, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_3_T_6 = dshr(lower_mask_3, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_3_T_7 = dshr(lower_mask_3, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_3_T_8 = dshr(lower_mask_3, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_3_T_9 = dshr(lower_mask_3, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_3_T_10 = dshr(lower_mask_3, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_3_T_11 = dshr(lower_mask_3, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_3_T_12 = dshr(lower_mask_3, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_3_T_13 = dshr(lower_mask_3, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_3_T_14 = dshr(lower_mask_3, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_3_T_15 = dshr(lower_mask_3, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_3_T_16 = or(_f3_fetch_bundle_sfb_masks_3_T, _f3_fetch_bundle_sfb_masks_3_T_1) node _f3_fetch_bundle_sfb_masks_3_T_17 = or(_f3_fetch_bundle_sfb_masks_3_T_16, _f3_fetch_bundle_sfb_masks_3_T_2) node _f3_fetch_bundle_sfb_masks_3_T_18 = or(_f3_fetch_bundle_sfb_masks_3_T_17, _f3_fetch_bundle_sfb_masks_3_T_3) node _f3_fetch_bundle_sfb_masks_3_T_19 = or(_f3_fetch_bundle_sfb_masks_3_T_18, _f3_fetch_bundle_sfb_masks_3_T_4) node _f3_fetch_bundle_sfb_masks_3_T_20 = or(_f3_fetch_bundle_sfb_masks_3_T_19, _f3_fetch_bundle_sfb_masks_3_T_5) node _f3_fetch_bundle_sfb_masks_3_T_21 = or(_f3_fetch_bundle_sfb_masks_3_T_20, _f3_fetch_bundle_sfb_masks_3_T_6) node _f3_fetch_bundle_sfb_masks_3_T_22 = or(_f3_fetch_bundle_sfb_masks_3_T_21, _f3_fetch_bundle_sfb_masks_3_T_7) node _f3_fetch_bundle_sfb_masks_3_T_23 = or(_f3_fetch_bundle_sfb_masks_3_T_22, _f3_fetch_bundle_sfb_masks_3_T_8) node _f3_fetch_bundle_sfb_masks_3_T_24 = or(_f3_fetch_bundle_sfb_masks_3_T_23, _f3_fetch_bundle_sfb_masks_3_T_9) node _f3_fetch_bundle_sfb_masks_3_T_25 = or(_f3_fetch_bundle_sfb_masks_3_T_24, _f3_fetch_bundle_sfb_masks_3_T_10) node _f3_fetch_bundle_sfb_masks_3_T_26 = or(_f3_fetch_bundle_sfb_masks_3_T_25, _f3_fetch_bundle_sfb_masks_3_T_11) node _f3_fetch_bundle_sfb_masks_3_T_27 = or(_f3_fetch_bundle_sfb_masks_3_T_26, _f3_fetch_bundle_sfb_masks_3_T_12) node _f3_fetch_bundle_sfb_masks_3_T_28 = or(_f3_fetch_bundle_sfb_masks_3_T_27, _f3_fetch_bundle_sfb_masks_3_T_13) node _f3_fetch_bundle_sfb_masks_3_T_29 = or(_f3_fetch_bundle_sfb_masks_3_T_28, _f3_fetch_bundle_sfb_masks_3_T_14) node _f3_fetch_bundle_sfb_masks_3_T_30 = or(_f3_fetch_bundle_sfb_masks_3_T_29, _f3_fetch_bundle_sfb_masks_3_T_15) node _f3_fetch_bundle_sfb_masks_3_T_31 = not(_f3_fetch_bundle_sfb_masks_3_T_30) node _f3_fetch_bundle_sfb_masks_3_T_32 = dshl(upper_mask_3, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_3_T_33 = bits(_f3_fetch_bundle_sfb_masks_3_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_34 = dshl(upper_mask_3, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_3_T_35 = bits(_f3_fetch_bundle_sfb_masks_3_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_36 = dshl(upper_mask_3, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_3_T_37 = bits(_f3_fetch_bundle_sfb_masks_3_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_38 = dshl(upper_mask_3, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_3_T_39 = bits(_f3_fetch_bundle_sfb_masks_3_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_40 = dshl(upper_mask_3, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_3_T_41 = bits(_f3_fetch_bundle_sfb_masks_3_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_42 = dshl(upper_mask_3, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_3_T_43 = bits(_f3_fetch_bundle_sfb_masks_3_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_44 = dshl(upper_mask_3, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_3_T_45 = bits(_f3_fetch_bundle_sfb_masks_3_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_46 = dshl(upper_mask_3, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_3_T_47 = bits(_f3_fetch_bundle_sfb_masks_3_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_48 = dshl(upper_mask_3, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_3_T_49 = bits(_f3_fetch_bundle_sfb_masks_3_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_50 = dshl(upper_mask_3, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_3_T_51 = bits(_f3_fetch_bundle_sfb_masks_3_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_52 = dshl(upper_mask_3, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_3_T_53 = bits(_f3_fetch_bundle_sfb_masks_3_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_54 = dshl(upper_mask_3, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_3_T_55 = bits(_f3_fetch_bundle_sfb_masks_3_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_56 = dshl(upper_mask_3, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_3_T_57 = bits(_f3_fetch_bundle_sfb_masks_3_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_58 = dshl(upper_mask_3, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_3_T_59 = bits(_f3_fetch_bundle_sfb_masks_3_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_60 = dshl(upper_mask_3, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_3_T_61 = bits(_f3_fetch_bundle_sfb_masks_3_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_62 = dshl(upper_mask_3, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_3_T_63 = bits(_f3_fetch_bundle_sfb_masks_3_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_64 = or(_f3_fetch_bundle_sfb_masks_3_T_33, _f3_fetch_bundle_sfb_masks_3_T_35) node _f3_fetch_bundle_sfb_masks_3_T_65 = or(_f3_fetch_bundle_sfb_masks_3_T_64, _f3_fetch_bundle_sfb_masks_3_T_37) node _f3_fetch_bundle_sfb_masks_3_T_66 = or(_f3_fetch_bundle_sfb_masks_3_T_65, _f3_fetch_bundle_sfb_masks_3_T_39) node _f3_fetch_bundle_sfb_masks_3_T_67 = or(_f3_fetch_bundle_sfb_masks_3_T_66, _f3_fetch_bundle_sfb_masks_3_T_41) node _f3_fetch_bundle_sfb_masks_3_T_68 = or(_f3_fetch_bundle_sfb_masks_3_T_67, _f3_fetch_bundle_sfb_masks_3_T_43) node _f3_fetch_bundle_sfb_masks_3_T_69 = or(_f3_fetch_bundle_sfb_masks_3_T_68, _f3_fetch_bundle_sfb_masks_3_T_45) node _f3_fetch_bundle_sfb_masks_3_T_70 = or(_f3_fetch_bundle_sfb_masks_3_T_69, _f3_fetch_bundle_sfb_masks_3_T_47) node _f3_fetch_bundle_sfb_masks_3_T_71 = or(_f3_fetch_bundle_sfb_masks_3_T_70, _f3_fetch_bundle_sfb_masks_3_T_49) node _f3_fetch_bundle_sfb_masks_3_T_72 = or(_f3_fetch_bundle_sfb_masks_3_T_71, _f3_fetch_bundle_sfb_masks_3_T_51) node _f3_fetch_bundle_sfb_masks_3_T_73 = or(_f3_fetch_bundle_sfb_masks_3_T_72, _f3_fetch_bundle_sfb_masks_3_T_53) node _f3_fetch_bundle_sfb_masks_3_T_74 = or(_f3_fetch_bundle_sfb_masks_3_T_73, _f3_fetch_bundle_sfb_masks_3_T_55) node _f3_fetch_bundle_sfb_masks_3_T_75 = or(_f3_fetch_bundle_sfb_masks_3_T_74, _f3_fetch_bundle_sfb_masks_3_T_57) node _f3_fetch_bundle_sfb_masks_3_T_76 = or(_f3_fetch_bundle_sfb_masks_3_T_75, _f3_fetch_bundle_sfb_masks_3_T_59) node _f3_fetch_bundle_sfb_masks_3_T_77 = or(_f3_fetch_bundle_sfb_masks_3_T_76, _f3_fetch_bundle_sfb_masks_3_T_61) node _f3_fetch_bundle_sfb_masks_3_T_78 = or(_f3_fetch_bundle_sfb_masks_3_T_77, _f3_fetch_bundle_sfb_masks_3_T_63) node _f3_fetch_bundle_sfb_masks_3_T_79 = not(_f3_fetch_bundle_sfb_masks_3_T_78) node _f3_fetch_bundle_sfb_masks_3_T_80 = and(_f3_fetch_bundle_sfb_masks_3_T_31, _f3_fetch_bundle_sfb_masks_3_T_79) connect f3_fetch_bundle.sfb_masks[3], _f3_fetch_bundle_sfb_masks_3_T_80 node _f3_fetch_bundle_shadowable_mask_3_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_3_T_1 = or(_f3_fetch_bundle_shadowable_mask_3_T, bpu_3.io.debug_if) node _f3_fetch_bundle_shadowable_mask_3_T_2 = or(_f3_fetch_bundle_shadowable_mask_3_T_1, bpu_3.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_3_T_3 = eq(_f3_fetch_bundle_shadowable_mask_3_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_3_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_3_T_5 = and(_f3_fetch_bundle_shadowable_mask_3_T_3, _f3_fetch_bundle_shadowable_mask_3_T_4) node _f3_fetch_bundle_shadowable_mask_3_T_6 = eq(f3_mask[3], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_3_T_7 = or(brsigs_3.shadowable, _f3_fetch_bundle_shadowable_mask_3_T_6) node _f3_fetch_bundle_shadowable_mask_3_T_8 = and(_f3_fetch_bundle_shadowable_mask_3_T_5, _f3_fetch_bundle_shadowable_mask_3_T_7) connect f3_fetch_bundle.shadowable_mask[3], _f3_fetch_bundle_shadowable_mask_3_T_8 connect f3_fetch_bundle.sfb_dests[3], offset_from_aligned_pc_3 node _f3_redirects_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h2)) node _f3_redirects_3_T_1 = eq(brsigs_3.cfi_type, UInt<3>(0h3)) node _f3_redirects_3_T_2 = or(_f3_redirects_3_T, _f3_redirects_3_T_1) node _f3_redirects_3_T_3 = eq(brsigs_3.cfi_type, UInt<3>(0h1)) node _f3_redirects_3_T_4 = and(_f3_redirects_3_T_3, f3_bpd_resp.io.deq.bits.preds[3].taken) node _f3_redirects_3_T_5 = and(_f3_redirects_3_T_4, UInt<1>(0h1)) node _f3_redirects_3_T_6 = or(_f3_redirects_3_T_2, _f3_redirects_3_T_5) node _f3_redirects_3_T_7 = and(f3_mask[3], _f3_redirects_3_T_6) connect f3_redirects[3], _f3_redirects_3_T_7 node _f3_br_mask_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h1)) node _f3_br_mask_3_T_1 = and(f3_mask[3], _f3_br_mask_3_T) connect f3_br_mask[3], _f3_br_mask_3_T_1 connect f3_cfi_types[3], brsigs_3.cfi_type connect f3_call_mask[3], brsigs_3.is_call connect f3_ret_mask[3], brsigs_3.is_ret connect f3_fetch_bundle.bp_debug_if_oh[3], bpu_3.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[3], bpu_3.io.xcpt_if node _T_31 = or(_T_30, f3_redirects[3]) node _T_32 = bits(bank_insts[3], 15, 0) node _T_33 = bits(f3_bank_mask, 0, 0) node _T_34 = bits(bank_insts[2], 1, 0) node _T_35 = neq(_T_34, UInt<2>(0h3)) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = and(bank_mask[2], _T_36) node _T_38 = eq(_T_37, UInt<1>(0h0)) node _T_39 = bits(_T_32, 1, 0) node _T_40 = neq(_T_39, UInt<2>(0h3)) node _T_41 = eq(_T_40, UInt<1>(0h0)) node _T_42 = and(_T_38, _T_41) node _T_43 = mux(_T_33, _T_42, f3_prev_is_half) node _T_44 = bits(f3_bank_mask, 0, 0) node _T_45 = bits(_T_32, 15, 0) node _T_46 = mux(_T_44, _T_45, f3_prev_half) node bank_data_1 = bits(f3.io.deq.bits.data, 127, 64) wire bank_mask_1 : UInt<1>[4] wire bank_insts_1 : UInt<32>[4] wire valid_4 : UInt<1> inst bpu_4 of BreakpointUnit_15 connect bpu_4.clock, clock connect bpu_4.reset, reset connect bpu_4.io.status.uie, io.cpu.status.uie connect bpu_4.io.status.sie, io.cpu.status.sie connect bpu_4.io.status.hie, io.cpu.status.hie connect bpu_4.io.status.mie, io.cpu.status.mie connect bpu_4.io.status.upie, io.cpu.status.upie connect bpu_4.io.status.spie, io.cpu.status.spie connect bpu_4.io.status.ube, io.cpu.status.ube connect bpu_4.io.status.mpie, io.cpu.status.mpie connect bpu_4.io.status.spp, io.cpu.status.spp connect bpu_4.io.status.vs, io.cpu.status.vs connect bpu_4.io.status.mpp, io.cpu.status.mpp connect bpu_4.io.status.fs, io.cpu.status.fs connect bpu_4.io.status.xs, io.cpu.status.xs connect bpu_4.io.status.mprv, io.cpu.status.mprv connect bpu_4.io.status.sum, io.cpu.status.sum connect bpu_4.io.status.mxr, io.cpu.status.mxr connect bpu_4.io.status.tvm, io.cpu.status.tvm connect bpu_4.io.status.tw, io.cpu.status.tw connect bpu_4.io.status.tsr, io.cpu.status.tsr connect bpu_4.io.status.zero1, io.cpu.status.zero1 connect bpu_4.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_4.io.status.uxl, io.cpu.status.uxl connect bpu_4.io.status.sxl, io.cpu.status.sxl connect bpu_4.io.status.sbe, io.cpu.status.sbe connect bpu_4.io.status.mbe, io.cpu.status.mbe connect bpu_4.io.status.gva, io.cpu.status.gva connect bpu_4.io.status.mpv, io.cpu.status.mpv connect bpu_4.io.status.zero2, io.cpu.status.zero2 connect bpu_4.io.status.sd, io.cpu.status.sd connect bpu_4.io.status.v, io.cpu.status.v connect bpu_4.io.status.prv, io.cpu.status.prv connect bpu_4.io.status.dv, io.cpu.status.dv connect bpu_4.io.status.dprv, io.cpu.status.dprv connect bpu_4.io.status.isa, io.cpu.status.isa connect bpu_4.io.status.wfi, io.cpu.status.wfi connect bpu_4.io.status.cease, io.cpu.status.cease connect bpu_4.io.status.debug, io.cpu.status.debug invalidate bpu_4.io.ea connect bpu_4.io.mcontext, io.cpu.mcontext connect bpu_4.io.scontext, io.cpu.scontext wire brsigs_4 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} node _inst0_T_1 = bits(bank_data_1, 15, 0) node inst0_1 = cat(_inst0_T_1, f3_prev_half) node inst1_1 = bits(bank_data_1, 31, 0) inst exp_inst0_rvc_exp_1 of RVCExpander_18 connect exp_inst0_rvc_exp_1.clock, clock connect exp_inst0_rvc_exp_1.reset, reset connect exp_inst0_rvc_exp_1.io.in, inst0_1 node exp_inst0_1 = mux(exp_inst0_rvc_exp_1.io.rvc, exp_inst0_rvc_exp_1.io.out.bits, inst0_1) inst exp_inst1_rvc_exp_1 of RVCExpander_19 connect exp_inst1_rvc_exp_1.clock, clock connect exp_inst1_rvc_exp_1.reset, reset connect exp_inst1_rvc_exp_1.io.in, inst1_1 node exp_inst1_1 = mux(exp_inst1_rvc_exp_1.io.rvc, exp_inst1_rvc_exp_1.io.out.bits, inst1_1) node _pc0_T_3 = add(f3_aligned_pc, UInt<4>(0h8)) node _pc0_T_4 = tail(_pc0_T_3, 1) node _pc0_T_5 = sub(_pc0_T_4, UInt<2>(0h2)) node pc0_1 = tail(_pc0_T_5, 1) node _pc1_T_1 = add(f3_aligned_pc, UInt<4>(0h8)) node pc1_1 = tail(_pc1_T_1, 1) inst bpd_decoder0_1 of BranchDecode_16 connect bpd_decoder0_1.clock, clock connect bpd_decoder0_1.reset, reset connect bpd_decoder0_1.io.inst, exp_inst0_1 connect bpd_decoder0_1.io.pc, pc0_1 inst bpd_decoder1_1 of BranchDecode_17 connect bpd_decoder1_1.clock, clock connect bpd_decoder1_1.reset, reset connect bpd_decoder1_1.io.inst, exp_inst1_1 connect bpd_decoder1_1.io.pc, pc1_1 when _T_43 : connect bank_insts_1[0], inst0_1 connect f3_fetch_bundle.insts[4], inst0_1 connect f3_fetch_bundle.exp_insts[4], exp_inst0_1 connect bpu_4.io.pc, pc0_1 connect brsigs_4.shadowable, bpd_decoder0_1.io.out.shadowable connect brsigs_4.sfb_offset, bpd_decoder0_1.io.out.sfb_offset connect brsigs_4.cfi_type, bpd_decoder0_1.io.out.cfi_type connect brsigs_4.target, bpd_decoder0_1.io.out.target connect brsigs_4.is_call, bpd_decoder0_1.io.out.is_call connect brsigs_4.is_ret, bpd_decoder0_1.io.out.is_ret connect f3_fetch_bundle.edge_inst[1], UInt<1>(0h1) node _inst0b_T = bits(bank_data_1, 15, 0) node inst0b = cat(_inst0b_T, _T_32) inst exp_inst0b_rvc_exp of RVCExpander_20 connect exp_inst0b_rvc_exp.clock, clock connect exp_inst0b_rvc_exp.reset, reset connect exp_inst0b_rvc_exp.io.in, inst0b node exp_inst0b = mux(exp_inst0b_rvc_exp.io.rvc, exp_inst0b_rvc_exp.io.out.bits, inst0b) inst bpd_decoder0b of BranchDecode_18 connect bpd_decoder0b.clock, clock connect bpd_decoder0b.reset, reset connect bpd_decoder0b.io.inst, exp_inst0b connect bpd_decoder0b.io.pc, pc0_1 node _T_47 = bits(f3_bank_mask, 0, 0) when _T_47 : connect bank_insts_1[0], inst0b connect f3_fetch_bundle.insts[4], inst0b connect f3_fetch_bundle.exp_insts[4], exp_inst0b connect brsigs_4.shadowable, bpd_decoder0b.io.out.shadowable connect brsigs_4.sfb_offset, bpd_decoder0b.io.out.sfb_offset connect brsigs_4.cfi_type, bpd_decoder0b.io.out.cfi_type connect brsigs_4.target, bpd_decoder0b.io.out.target connect brsigs_4.is_call, bpd_decoder0b.io.out.is_call connect brsigs_4.is_ret, bpd_decoder0b.io.out.is_ret else : connect bank_insts_1[0], inst1_1 connect f3_fetch_bundle.insts[4], inst1_1 connect f3_fetch_bundle.exp_insts[4], exp_inst1_1 connect bpu_4.io.pc, pc1_1 connect brsigs_4.shadowable, bpd_decoder1_1.io.out.shadowable connect brsigs_4.sfb_offset, bpd_decoder1_1.io.out.sfb_offset connect brsigs_4.cfi_type, bpd_decoder1_1.io.out.cfi_type connect brsigs_4.target, bpd_decoder1_1.io.out.target connect brsigs_4.is_call, bpd_decoder1_1.io.out.is_call connect brsigs_4.is_ret, bpd_decoder1_1.io.out.is_ret connect f3_fetch_bundle.edge_inst[1], UInt<1>(0h0) connect valid_4, UInt<1>(0h1) node _f3_is_rvc_4_T = bits(bank_insts_1[0], 1, 0) node _f3_is_rvc_4_T_1 = neq(_f3_is_rvc_4_T, UInt<2>(0h3)) connect f3_is_rvc[4], _f3_is_rvc_4_T_1 node _bank_mask_0_T_5 = bits(f3.io.deq.bits.mask, 4, 4) node _bank_mask_0_T_6 = and(f3.io.deq.valid, _bank_mask_0_T_5) node _bank_mask_0_T_7 = and(_bank_mask_0_T_6, valid_4) node _bank_mask_0_T_8 = eq(_T_31, UInt<1>(0h0)) node _bank_mask_0_T_9 = and(_bank_mask_0_T_7, _bank_mask_0_T_8) connect bank_mask_1[0], _bank_mask_0_T_9 node _f3_mask_4_T = bits(f3.io.deq.bits.mask, 4, 4) node _f3_mask_4_T_1 = and(f3.io.deq.valid, _f3_mask_4_T) node _f3_mask_4_T_2 = and(_f3_mask_4_T_1, valid_4) node _f3_mask_4_T_3 = eq(_T_31, UInt<1>(0h0)) node _f3_mask_4_T_4 = and(_f3_mask_4_T_2, _f3_mask_4_T_3) connect f3_mask[4], _f3_mask_4_T_4 node _f3_targs_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h3)) node _f3_targs_4_T_1 = mux(_f3_targs_4_T, f3_bpd_resp.io.deq.bits.preds[4].predicted_pc.bits, brsigs_4.target) connect f3_targs[4], _f3_targs_4_T_1 node _f3_btb_mispredicts_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_4_T_1 = and(_f3_btb_mispredicts_4_T, valid_4) node _f3_btb_mispredicts_4_T_2 = and(_f3_btb_mispredicts_4_T_1, f3_bpd_resp.io.deq.bits.preds[4].predicted_pc.valid) node _f3_btb_mispredicts_4_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[4].predicted_pc.bits, brsigs_4.target) node _f3_btb_mispredicts_4_T_4 = and(_f3_btb_mispredicts_4_T_2, _f3_btb_mispredicts_4_T_3) connect f3_btb_mispredicts[4], _f3_btb_mispredicts_4_T_4 node _f3_npc_plus4_mask_4_T = eq(f3_is_rvc[4], UInt<1>(0h0)) node _f3_npc_plus4_mask_4_T_1 = eq(_T_43, UInt<1>(0h0)) node _f3_npc_plus4_mask_4_T_2 = and(_f3_npc_plus4_mask_4_T, _f3_npc_plus4_mask_4_T_1) connect f3_npc_plus4_mask[4], _f3_npc_plus4_mask_4_T_2 node _offset_from_aligned_pc_T_20 = add(UInt<7>(0h8), brsigs_4.sfb_offset.bits) node _offset_from_aligned_pc_T_21 = tail(_offset_from_aligned_pc_T_20, 1) node _offset_from_aligned_pc_T_22 = and(_T_43, UInt<1>(0h1)) node _offset_from_aligned_pc_T_23 = mux(_offset_from_aligned_pc_T_22, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_24 = sub(_offset_from_aligned_pc_T_21, _offset_from_aligned_pc_T_23) node offset_from_aligned_pc_4 = tail(_offset_from_aligned_pc_T_24, 1) wire lower_mask_4 : UInt<16> wire upper_mask_4 : UInt<16> node _lower_mask_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4)) connect lower_mask_4, _lower_mask_T_4 node _upper_mask_T_16 = bits(offset_from_aligned_pc_4, 5, 1) node _upper_mask_T_17 = dshl(UInt<1>(0h1), _upper_mask_T_16) node _upper_mask_T_18 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_19 = dshl(_upper_mask_T_17, _upper_mask_T_18) connect upper_mask_4, _upper_mask_T_19 node _f3_fetch_bundle_sfbs_4_T = and(f3_mask[4], brsigs_4.sfb_offset.valid) node _f3_fetch_bundle_sfbs_4_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_4_T_2 = leq(offset_from_aligned_pc_4, _f3_fetch_bundle_sfbs_4_T_1) node _f3_fetch_bundle_sfbs_4_T_3 = and(_f3_fetch_bundle_sfbs_4_T, _f3_fetch_bundle_sfbs_4_T_2) connect f3_fetch_bundle.sfbs[4], _f3_fetch_bundle_sfbs_4_T_3 node _f3_fetch_bundle_sfb_masks_4_T = dshr(lower_mask_4, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_4_T_1 = dshr(lower_mask_4, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_4_T_2 = dshr(lower_mask_4, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_4_T_3 = dshr(lower_mask_4, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_4_T_4 = dshr(lower_mask_4, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_4_T_5 = dshr(lower_mask_4, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_4_T_6 = dshr(lower_mask_4, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_4_T_7 = dshr(lower_mask_4, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_4_T_8 = dshr(lower_mask_4, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_4_T_9 = dshr(lower_mask_4, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_4_T_10 = dshr(lower_mask_4, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_4_T_11 = dshr(lower_mask_4, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_4_T_12 = dshr(lower_mask_4, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_4_T_13 = dshr(lower_mask_4, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_4_T_14 = dshr(lower_mask_4, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_4_T_15 = dshr(lower_mask_4, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_4_T_16 = or(_f3_fetch_bundle_sfb_masks_4_T, _f3_fetch_bundle_sfb_masks_4_T_1) node _f3_fetch_bundle_sfb_masks_4_T_17 = or(_f3_fetch_bundle_sfb_masks_4_T_16, _f3_fetch_bundle_sfb_masks_4_T_2) node _f3_fetch_bundle_sfb_masks_4_T_18 = or(_f3_fetch_bundle_sfb_masks_4_T_17, _f3_fetch_bundle_sfb_masks_4_T_3) node _f3_fetch_bundle_sfb_masks_4_T_19 = or(_f3_fetch_bundle_sfb_masks_4_T_18, _f3_fetch_bundle_sfb_masks_4_T_4) node _f3_fetch_bundle_sfb_masks_4_T_20 = or(_f3_fetch_bundle_sfb_masks_4_T_19, _f3_fetch_bundle_sfb_masks_4_T_5) node _f3_fetch_bundle_sfb_masks_4_T_21 = or(_f3_fetch_bundle_sfb_masks_4_T_20, _f3_fetch_bundle_sfb_masks_4_T_6) node _f3_fetch_bundle_sfb_masks_4_T_22 = or(_f3_fetch_bundle_sfb_masks_4_T_21, _f3_fetch_bundle_sfb_masks_4_T_7) node _f3_fetch_bundle_sfb_masks_4_T_23 = or(_f3_fetch_bundle_sfb_masks_4_T_22, _f3_fetch_bundle_sfb_masks_4_T_8) node _f3_fetch_bundle_sfb_masks_4_T_24 = or(_f3_fetch_bundle_sfb_masks_4_T_23, _f3_fetch_bundle_sfb_masks_4_T_9) node _f3_fetch_bundle_sfb_masks_4_T_25 = or(_f3_fetch_bundle_sfb_masks_4_T_24, _f3_fetch_bundle_sfb_masks_4_T_10) node _f3_fetch_bundle_sfb_masks_4_T_26 = or(_f3_fetch_bundle_sfb_masks_4_T_25, _f3_fetch_bundle_sfb_masks_4_T_11) node _f3_fetch_bundle_sfb_masks_4_T_27 = or(_f3_fetch_bundle_sfb_masks_4_T_26, _f3_fetch_bundle_sfb_masks_4_T_12) node _f3_fetch_bundle_sfb_masks_4_T_28 = or(_f3_fetch_bundle_sfb_masks_4_T_27, _f3_fetch_bundle_sfb_masks_4_T_13) node _f3_fetch_bundle_sfb_masks_4_T_29 = or(_f3_fetch_bundle_sfb_masks_4_T_28, _f3_fetch_bundle_sfb_masks_4_T_14) node _f3_fetch_bundle_sfb_masks_4_T_30 = or(_f3_fetch_bundle_sfb_masks_4_T_29, _f3_fetch_bundle_sfb_masks_4_T_15) node _f3_fetch_bundle_sfb_masks_4_T_31 = not(_f3_fetch_bundle_sfb_masks_4_T_30) node _f3_fetch_bundle_sfb_masks_4_T_32 = dshl(upper_mask_4, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_4_T_33 = bits(_f3_fetch_bundle_sfb_masks_4_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_34 = dshl(upper_mask_4, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_4_T_35 = bits(_f3_fetch_bundle_sfb_masks_4_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_36 = dshl(upper_mask_4, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_4_T_37 = bits(_f3_fetch_bundle_sfb_masks_4_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_38 = dshl(upper_mask_4, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_4_T_39 = bits(_f3_fetch_bundle_sfb_masks_4_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_40 = dshl(upper_mask_4, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_4_T_41 = bits(_f3_fetch_bundle_sfb_masks_4_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_42 = dshl(upper_mask_4, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_4_T_43 = bits(_f3_fetch_bundle_sfb_masks_4_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_44 = dshl(upper_mask_4, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_4_T_45 = bits(_f3_fetch_bundle_sfb_masks_4_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_46 = dshl(upper_mask_4, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_4_T_47 = bits(_f3_fetch_bundle_sfb_masks_4_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_48 = dshl(upper_mask_4, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_4_T_49 = bits(_f3_fetch_bundle_sfb_masks_4_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_50 = dshl(upper_mask_4, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_4_T_51 = bits(_f3_fetch_bundle_sfb_masks_4_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_52 = dshl(upper_mask_4, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_4_T_53 = bits(_f3_fetch_bundle_sfb_masks_4_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_54 = dshl(upper_mask_4, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_4_T_55 = bits(_f3_fetch_bundle_sfb_masks_4_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_56 = dshl(upper_mask_4, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_4_T_57 = bits(_f3_fetch_bundle_sfb_masks_4_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_58 = dshl(upper_mask_4, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_4_T_59 = bits(_f3_fetch_bundle_sfb_masks_4_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_60 = dshl(upper_mask_4, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_4_T_61 = bits(_f3_fetch_bundle_sfb_masks_4_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_62 = dshl(upper_mask_4, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_4_T_63 = bits(_f3_fetch_bundle_sfb_masks_4_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_64 = or(_f3_fetch_bundle_sfb_masks_4_T_33, _f3_fetch_bundle_sfb_masks_4_T_35) node _f3_fetch_bundle_sfb_masks_4_T_65 = or(_f3_fetch_bundle_sfb_masks_4_T_64, _f3_fetch_bundle_sfb_masks_4_T_37) node _f3_fetch_bundle_sfb_masks_4_T_66 = or(_f3_fetch_bundle_sfb_masks_4_T_65, _f3_fetch_bundle_sfb_masks_4_T_39) node _f3_fetch_bundle_sfb_masks_4_T_67 = or(_f3_fetch_bundle_sfb_masks_4_T_66, _f3_fetch_bundle_sfb_masks_4_T_41) node _f3_fetch_bundle_sfb_masks_4_T_68 = or(_f3_fetch_bundle_sfb_masks_4_T_67, _f3_fetch_bundle_sfb_masks_4_T_43) node _f3_fetch_bundle_sfb_masks_4_T_69 = or(_f3_fetch_bundle_sfb_masks_4_T_68, _f3_fetch_bundle_sfb_masks_4_T_45) node _f3_fetch_bundle_sfb_masks_4_T_70 = or(_f3_fetch_bundle_sfb_masks_4_T_69, _f3_fetch_bundle_sfb_masks_4_T_47) node _f3_fetch_bundle_sfb_masks_4_T_71 = or(_f3_fetch_bundle_sfb_masks_4_T_70, _f3_fetch_bundle_sfb_masks_4_T_49) node _f3_fetch_bundle_sfb_masks_4_T_72 = or(_f3_fetch_bundle_sfb_masks_4_T_71, _f3_fetch_bundle_sfb_masks_4_T_51) node _f3_fetch_bundle_sfb_masks_4_T_73 = or(_f3_fetch_bundle_sfb_masks_4_T_72, _f3_fetch_bundle_sfb_masks_4_T_53) node _f3_fetch_bundle_sfb_masks_4_T_74 = or(_f3_fetch_bundle_sfb_masks_4_T_73, _f3_fetch_bundle_sfb_masks_4_T_55) node _f3_fetch_bundle_sfb_masks_4_T_75 = or(_f3_fetch_bundle_sfb_masks_4_T_74, _f3_fetch_bundle_sfb_masks_4_T_57) node _f3_fetch_bundle_sfb_masks_4_T_76 = or(_f3_fetch_bundle_sfb_masks_4_T_75, _f3_fetch_bundle_sfb_masks_4_T_59) node _f3_fetch_bundle_sfb_masks_4_T_77 = or(_f3_fetch_bundle_sfb_masks_4_T_76, _f3_fetch_bundle_sfb_masks_4_T_61) node _f3_fetch_bundle_sfb_masks_4_T_78 = or(_f3_fetch_bundle_sfb_masks_4_T_77, _f3_fetch_bundle_sfb_masks_4_T_63) node _f3_fetch_bundle_sfb_masks_4_T_79 = not(_f3_fetch_bundle_sfb_masks_4_T_78) node _f3_fetch_bundle_sfb_masks_4_T_80 = and(_f3_fetch_bundle_sfb_masks_4_T_31, _f3_fetch_bundle_sfb_masks_4_T_79) connect f3_fetch_bundle.sfb_masks[4], _f3_fetch_bundle_sfb_masks_4_T_80 node _f3_fetch_bundle_shadowable_mask_4_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_4_T_1 = or(_f3_fetch_bundle_shadowable_mask_4_T, bpu_4.io.debug_if) node _f3_fetch_bundle_shadowable_mask_4_T_2 = or(_f3_fetch_bundle_shadowable_mask_4_T_1, bpu_4.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_4_T_3 = eq(_f3_fetch_bundle_shadowable_mask_4_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_4_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_4_T_5 = and(_f3_fetch_bundle_shadowable_mask_4_T_3, _f3_fetch_bundle_shadowable_mask_4_T_4) node _f3_fetch_bundle_shadowable_mask_4_T_6 = eq(f3_mask[4], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_4_T_7 = or(brsigs_4.shadowable, _f3_fetch_bundle_shadowable_mask_4_T_6) node _f3_fetch_bundle_shadowable_mask_4_T_8 = and(_f3_fetch_bundle_shadowable_mask_4_T_5, _f3_fetch_bundle_shadowable_mask_4_T_7) connect f3_fetch_bundle.shadowable_mask[4], _f3_fetch_bundle_shadowable_mask_4_T_8 connect f3_fetch_bundle.sfb_dests[4], offset_from_aligned_pc_4 node _f3_redirects_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h2)) node _f3_redirects_4_T_1 = eq(brsigs_4.cfi_type, UInt<3>(0h3)) node _f3_redirects_4_T_2 = or(_f3_redirects_4_T, _f3_redirects_4_T_1) node _f3_redirects_4_T_3 = eq(brsigs_4.cfi_type, UInt<3>(0h1)) node _f3_redirects_4_T_4 = and(_f3_redirects_4_T_3, f3_bpd_resp.io.deq.bits.preds[4].taken) node _f3_redirects_4_T_5 = and(_f3_redirects_4_T_4, UInt<1>(0h1)) node _f3_redirects_4_T_6 = or(_f3_redirects_4_T_2, _f3_redirects_4_T_5) node _f3_redirects_4_T_7 = and(f3_mask[4], _f3_redirects_4_T_6) connect f3_redirects[4], _f3_redirects_4_T_7 node _f3_br_mask_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h1)) node _f3_br_mask_4_T_1 = and(f3_mask[4], _f3_br_mask_4_T) connect f3_br_mask[4], _f3_br_mask_4_T_1 connect f3_cfi_types[4], brsigs_4.cfi_type connect f3_call_mask[4], brsigs_4.is_call connect f3_ret_mask[4], brsigs_4.is_ret connect f3_fetch_bundle.bp_debug_if_oh[4], bpu_4.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[4], bpu_4.io.xcpt_if node _T_48 = or(_T_31, f3_redirects[4]) wire valid_5 : UInt<1> inst bpu_5 of BreakpointUnit_16 connect bpu_5.clock, clock connect bpu_5.reset, reset connect bpu_5.io.status.uie, io.cpu.status.uie connect bpu_5.io.status.sie, io.cpu.status.sie connect bpu_5.io.status.hie, io.cpu.status.hie connect bpu_5.io.status.mie, io.cpu.status.mie connect bpu_5.io.status.upie, io.cpu.status.upie connect bpu_5.io.status.spie, io.cpu.status.spie connect bpu_5.io.status.ube, io.cpu.status.ube connect bpu_5.io.status.mpie, io.cpu.status.mpie connect bpu_5.io.status.spp, io.cpu.status.spp connect bpu_5.io.status.vs, io.cpu.status.vs connect bpu_5.io.status.mpp, io.cpu.status.mpp connect bpu_5.io.status.fs, io.cpu.status.fs connect bpu_5.io.status.xs, io.cpu.status.xs connect bpu_5.io.status.mprv, io.cpu.status.mprv connect bpu_5.io.status.sum, io.cpu.status.sum connect bpu_5.io.status.mxr, io.cpu.status.mxr connect bpu_5.io.status.tvm, io.cpu.status.tvm connect bpu_5.io.status.tw, io.cpu.status.tw connect bpu_5.io.status.tsr, io.cpu.status.tsr connect bpu_5.io.status.zero1, io.cpu.status.zero1 connect bpu_5.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_5.io.status.uxl, io.cpu.status.uxl connect bpu_5.io.status.sxl, io.cpu.status.sxl connect bpu_5.io.status.sbe, io.cpu.status.sbe connect bpu_5.io.status.mbe, io.cpu.status.mbe connect bpu_5.io.status.gva, io.cpu.status.gva connect bpu_5.io.status.mpv, io.cpu.status.mpv connect bpu_5.io.status.zero2, io.cpu.status.zero2 connect bpu_5.io.status.sd, io.cpu.status.sd connect bpu_5.io.status.v, io.cpu.status.v connect bpu_5.io.status.prv, io.cpu.status.prv connect bpu_5.io.status.dv, io.cpu.status.dv connect bpu_5.io.status.dprv, io.cpu.status.dprv connect bpu_5.io.status.isa, io.cpu.status.isa connect bpu_5.io.status.wfi, io.cpu.status.wfi connect bpu_5.io.status.cease, io.cpu.status.cease connect bpu_5.io.status.debug, io.cpu.status.debug invalidate bpu_5.io.ea connect bpu_5.io.mcontext, io.cpu.mcontext connect bpu_5.io.scontext, io.cpu.scontext wire brsigs_5 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_3 : UInt<32> inst exp_inst_rvc_exp_3 of RVCExpander_21 connect exp_inst_rvc_exp_3.clock, clock connect exp_inst_rvc_exp_3.reset, reset connect exp_inst_rvc_exp_3.io.in, inst_3 node exp_inst_3 = mux(exp_inst_rvc_exp_3.io.rvc, exp_inst_rvc_exp_3.io.out.bits, inst_3) node _pc_T_3 = add(f3_aligned_pc, UInt<4>(0ha)) node pc_3 = tail(_pc_T_3, 1) inst bpd_decoder_3 of BranchDecode_19 connect bpd_decoder_3.clock, clock connect bpd_decoder_3.reset, reset connect bpd_decoder_3.io.inst, exp_inst_3 connect bpd_decoder_3.io.pc, pc_3 connect bank_insts_1[1], inst_3 connect f3_fetch_bundle.insts[5], inst_3 connect f3_fetch_bundle.exp_insts[5], exp_inst_3 connect bpu_5.io.pc, pc_3 connect brsigs_5.shadowable, bpd_decoder_3.io.out.shadowable connect brsigs_5.sfb_offset, bpd_decoder_3.io.out.sfb_offset connect brsigs_5.cfi_type, bpd_decoder_3.io.out.cfi_type connect brsigs_5.target, bpd_decoder_3.io.out.target connect brsigs_5.is_call, bpd_decoder_3.io.out.is_call connect brsigs_5.is_ret, bpd_decoder_3.io.out.is_ret node _inst_T_4 = bits(bank_data_1, 47, 16) connect inst_3, _inst_T_4 node _valid_T_20 = bits(bank_insts_1[0], 1, 0) node _valid_T_21 = neq(_valid_T_20, UInt<2>(0h3)) node _valid_T_22 = eq(_valid_T_21, UInt<1>(0h0)) node _valid_T_23 = and(bank_mask_1[0], _valid_T_22) node _valid_T_24 = eq(_valid_T_23, UInt<1>(0h0)) node _valid_T_25 = or(_T_43, _valid_T_24) connect valid_5, _valid_T_25 node _f3_is_rvc_5_T = bits(bank_insts_1[1], 1, 0) node _f3_is_rvc_5_T_1 = neq(_f3_is_rvc_5_T, UInt<2>(0h3)) connect f3_is_rvc[5], _f3_is_rvc_5_T_1 node _bank_mask_1_T_5 = bits(f3.io.deq.bits.mask, 5, 5) node _bank_mask_1_T_6 = and(f3.io.deq.valid, _bank_mask_1_T_5) node _bank_mask_1_T_7 = and(_bank_mask_1_T_6, valid_5) node _bank_mask_1_T_8 = eq(_T_48, UInt<1>(0h0)) node _bank_mask_1_T_9 = and(_bank_mask_1_T_7, _bank_mask_1_T_8) connect bank_mask_1[1], _bank_mask_1_T_9 node _f3_mask_5_T = bits(f3.io.deq.bits.mask, 5, 5) node _f3_mask_5_T_1 = and(f3.io.deq.valid, _f3_mask_5_T) node _f3_mask_5_T_2 = and(_f3_mask_5_T_1, valid_5) node _f3_mask_5_T_3 = eq(_T_48, UInt<1>(0h0)) node _f3_mask_5_T_4 = and(_f3_mask_5_T_2, _f3_mask_5_T_3) connect f3_mask[5], _f3_mask_5_T_4 node _f3_targs_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h3)) node _f3_targs_5_T_1 = mux(_f3_targs_5_T, f3_bpd_resp.io.deq.bits.preds[5].predicted_pc.bits, brsigs_5.target) connect f3_targs[5], _f3_targs_5_T_1 node _f3_btb_mispredicts_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_5_T_1 = and(_f3_btb_mispredicts_5_T, valid_5) node _f3_btb_mispredicts_5_T_2 = and(_f3_btb_mispredicts_5_T_1, f3_bpd_resp.io.deq.bits.preds[5].predicted_pc.valid) node _f3_btb_mispredicts_5_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[5].predicted_pc.bits, brsigs_5.target) node _f3_btb_mispredicts_5_T_4 = and(_f3_btb_mispredicts_5_T_2, _f3_btb_mispredicts_5_T_3) connect f3_btb_mispredicts[5], _f3_btb_mispredicts_5_T_4 node _f3_npc_plus4_mask_5_T = eq(f3_is_rvc[5], UInt<1>(0h0)) connect f3_npc_plus4_mask[5], _f3_npc_plus4_mask_5_T node _offset_from_aligned_pc_T_25 = add(UInt<7>(0ha), brsigs_5.sfb_offset.bits) node _offset_from_aligned_pc_T_26 = tail(_offset_from_aligned_pc_T_25, 1) node _offset_from_aligned_pc_T_27 = and(_T_43, UInt<1>(0h0)) node _offset_from_aligned_pc_T_28 = mux(_offset_from_aligned_pc_T_27, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_29 = sub(_offset_from_aligned_pc_T_26, _offset_from_aligned_pc_T_28) node offset_from_aligned_pc_5 = tail(_offset_from_aligned_pc_T_29, 1) wire lower_mask_5 : UInt<16> wire upper_mask_5 : UInt<16> node _lower_mask_T_5 = dshl(UInt<1>(0h1), UInt<3>(0h5)) connect lower_mask_5, _lower_mask_T_5 node _upper_mask_T_20 = bits(offset_from_aligned_pc_5, 5, 1) node _upper_mask_T_21 = dshl(UInt<1>(0h1), _upper_mask_T_20) node _upper_mask_T_22 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_23 = dshl(_upper_mask_T_21, _upper_mask_T_22) connect upper_mask_5, _upper_mask_T_23 node _f3_fetch_bundle_sfbs_5_T = and(f3_mask[5], brsigs_5.sfb_offset.valid) node _f3_fetch_bundle_sfbs_5_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_5_T_2 = leq(offset_from_aligned_pc_5, _f3_fetch_bundle_sfbs_5_T_1) node _f3_fetch_bundle_sfbs_5_T_3 = and(_f3_fetch_bundle_sfbs_5_T, _f3_fetch_bundle_sfbs_5_T_2) connect f3_fetch_bundle.sfbs[5], _f3_fetch_bundle_sfbs_5_T_3 node _f3_fetch_bundle_sfb_masks_5_T = dshr(lower_mask_5, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_5_T_1 = dshr(lower_mask_5, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_5_T_2 = dshr(lower_mask_5, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_5_T_3 = dshr(lower_mask_5, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_5_T_4 = dshr(lower_mask_5, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_5_T_5 = dshr(lower_mask_5, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_5_T_6 = dshr(lower_mask_5, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_5_T_7 = dshr(lower_mask_5, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_5_T_8 = dshr(lower_mask_5, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_5_T_9 = dshr(lower_mask_5, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_5_T_10 = dshr(lower_mask_5, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_5_T_11 = dshr(lower_mask_5, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_5_T_12 = dshr(lower_mask_5, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_5_T_13 = dshr(lower_mask_5, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_5_T_14 = dshr(lower_mask_5, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_5_T_15 = dshr(lower_mask_5, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_5_T_16 = or(_f3_fetch_bundle_sfb_masks_5_T, _f3_fetch_bundle_sfb_masks_5_T_1) node _f3_fetch_bundle_sfb_masks_5_T_17 = or(_f3_fetch_bundle_sfb_masks_5_T_16, _f3_fetch_bundle_sfb_masks_5_T_2) node _f3_fetch_bundle_sfb_masks_5_T_18 = or(_f3_fetch_bundle_sfb_masks_5_T_17, _f3_fetch_bundle_sfb_masks_5_T_3) node _f3_fetch_bundle_sfb_masks_5_T_19 = or(_f3_fetch_bundle_sfb_masks_5_T_18, _f3_fetch_bundle_sfb_masks_5_T_4) node _f3_fetch_bundle_sfb_masks_5_T_20 = or(_f3_fetch_bundle_sfb_masks_5_T_19, _f3_fetch_bundle_sfb_masks_5_T_5) node _f3_fetch_bundle_sfb_masks_5_T_21 = or(_f3_fetch_bundle_sfb_masks_5_T_20, _f3_fetch_bundle_sfb_masks_5_T_6) node _f3_fetch_bundle_sfb_masks_5_T_22 = or(_f3_fetch_bundle_sfb_masks_5_T_21, _f3_fetch_bundle_sfb_masks_5_T_7) node _f3_fetch_bundle_sfb_masks_5_T_23 = or(_f3_fetch_bundle_sfb_masks_5_T_22, _f3_fetch_bundle_sfb_masks_5_T_8) node _f3_fetch_bundle_sfb_masks_5_T_24 = or(_f3_fetch_bundle_sfb_masks_5_T_23, _f3_fetch_bundle_sfb_masks_5_T_9) node _f3_fetch_bundle_sfb_masks_5_T_25 = or(_f3_fetch_bundle_sfb_masks_5_T_24, _f3_fetch_bundle_sfb_masks_5_T_10) node _f3_fetch_bundle_sfb_masks_5_T_26 = or(_f3_fetch_bundle_sfb_masks_5_T_25, _f3_fetch_bundle_sfb_masks_5_T_11) node _f3_fetch_bundle_sfb_masks_5_T_27 = or(_f3_fetch_bundle_sfb_masks_5_T_26, _f3_fetch_bundle_sfb_masks_5_T_12) node _f3_fetch_bundle_sfb_masks_5_T_28 = or(_f3_fetch_bundle_sfb_masks_5_T_27, _f3_fetch_bundle_sfb_masks_5_T_13) node _f3_fetch_bundle_sfb_masks_5_T_29 = or(_f3_fetch_bundle_sfb_masks_5_T_28, _f3_fetch_bundle_sfb_masks_5_T_14) node _f3_fetch_bundle_sfb_masks_5_T_30 = or(_f3_fetch_bundle_sfb_masks_5_T_29, _f3_fetch_bundle_sfb_masks_5_T_15) node _f3_fetch_bundle_sfb_masks_5_T_31 = not(_f3_fetch_bundle_sfb_masks_5_T_30) node _f3_fetch_bundle_sfb_masks_5_T_32 = dshl(upper_mask_5, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_5_T_33 = bits(_f3_fetch_bundle_sfb_masks_5_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_34 = dshl(upper_mask_5, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_5_T_35 = bits(_f3_fetch_bundle_sfb_masks_5_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_36 = dshl(upper_mask_5, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_5_T_37 = bits(_f3_fetch_bundle_sfb_masks_5_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_38 = dshl(upper_mask_5, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_5_T_39 = bits(_f3_fetch_bundle_sfb_masks_5_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_40 = dshl(upper_mask_5, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_5_T_41 = bits(_f3_fetch_bundle_sfb_masks_5_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_42 = dshl(upper_mask_5, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_5_T_43 = bits(_f3_fetch_bundle_sfb_masks_5_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_44 = dshl(upper_mask_5, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_5_T_45 = bits(_f3_fetch_bundle_sfb_masks_5_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_46 = dshl(upper_mask_5, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_5_T_47 = bits(_f3_fetch_bundle_sfb_masks_5_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_48 = dshl(upper_mask_5, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_5_T_49 = bits(_f3_fetch_bundle_sfb_masks_5_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_50 = dshl(upper_mask_5, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_5_T_51 = bits(_f3_fetch_bundle_sfb_masks_5_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_52 = dshl(upper_mask_5, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_5_T_53 = bits(_f3_fetch_bundle_sfb_masks_5_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_54 = dshl(upper_mask_5, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_5_T_55 = bits(_f3_fetch_bundle_sfb_masks_5_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_56 = dshl(upper_mask_5, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_5_T_57 = bits(_f3_fetch_bundle_sfb_masks_5_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_58 = dshl(upper_mask_5, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_5_T_59 = bits(_f3_fetch_bundle_sfb_masks_5_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_60 = dshl(upper_mask_5, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_5_T_61 = bits(_f3_fetch_bundle_sfb_masks_5_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_62 = dshl(upper_mask_5, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_5_T_63 = bits(_f3_fetch_bundle_sfb_masks_5_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_64 = or(_f3_fetch_bundle_sfb_masks_5_T_33, _f3_fetch_bundle_sfb_masks_5_T_35) node _f3_fetch_bundle_sfb_masks_5_T_65 = or(_f3_fetch_bundle_sfb_masks_5_T_64, _f3_fetch_bundle_sfb_masks_5_T_37) node _f3_fetch_bundle_sfb_masks_5_T_66 = or(_f3_fetch_bundle_sfb_masks_5_T_65, _f3_fetch_bundle_sfb_masks_5_T_39) node _f3_fetch_bundle_sfb_masks_5_T_67 = or(_f3_fetch_bundle_sfb_masks_5_T_66, _f3_fetch_bundle_sfb_masks_5_T_41) node _f3_fetch_bundle_sfb_masks_5_T_68 = or(_f3_fetch_bundle_sfb_masks_5_T_67, _f3_fetch_bundle_sfb_masks_5_T_43) node _f3_fetch_bundle_sfb_masks_5_T_69 = or(_f3_fetch_bundle_sfb_masks_5_T_68, _f3_fetch_bundle_sfb_masks_5_T_45) node _f3_fetch_bundle_sfb_masks_5_T_70 = or(_f3_fetch_bundle_sfb_masks_5_T_69, _f3_fetch_bundle_sfb_masks_5_T_47) node _f3_fetch_bundle_sfb_masks_5_T_71 = or(_f3_fetch_bundle_sfb_masks_5_T_70, _f3_fetch_bundle_sfb_masks_5_T_49) node _f3_fetch_bundle_sfb_masks_5_T_72 = or(_f3_fetch_bundle_sfb_masks_5_T_71, _f3_fetch_bundle_sfb_masks_5_T_51) node _f3_fetch_bundle_sfb_masks_5_T_73 = or(_f3_fetch_bundle_sfb_masks_5_T_72, _f3_fetch_bundle_sfb_masks_5_T_53) node _f3_fetch_bundle_sfb_masks_5_T_74 = or(_f3_fetch_bundle_sfb_masks_5_T_73, _f3_fetch_bundle_sfb_masks_5_T_55) node _f3_fetch_bundle_sfb_masks_5_T_75 = or(_f3_fetch_bundle_sfb_masks_5_T_74, _f3_fetch_bundle_sfb_masks_5_T_57) node _f3_fetch_bundle_sfb_masks_5_T_76 = or(_f3_fetch_bundle_sfb_masks_5_T_75, _f3_fetch_bundle_sfb_masks_5_T_59) node _f3_fetch_bundle_sfb_masks_5_T_77 = or(_f3_fetch_bundle_sfb_masks_5_T_76, _f3_fetch_bundle_sfb_masks_5_T_61) node _f3_fetch_bundle_sfb_masks_5_T_78 = or(_f3_fetch_bundle_sfb_masks_5_T_77, _f3_fetch_bundle_sfb_masks_5_T_63) node _f3_fetch_bundle_sfb_masks_5_T_79 = not(_f3_fetch_bundle_sfb_masks_5_T_78) node _f3_fetch_bundle_sfb_masks_5_T_80 = and(_f3_fetch_bundle_sfb_masks_5_T_31, _f3_fetch_bundle_sfb_masks_5_T_79) connect f3_fetch_bundle.sfb_masks[5], _f3_fetch_bundle_sfb_masks_5_T_80 node _f3_fetch_bundle_shadowable_mask_5_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_5_T_1 = or(_f3_fetch_bundle_shadowable_mask_5_T, bpu_5.io.debug_if) node _f3_fetch_bundle_shadowable_mask_5_T_2 = or(_f3_fetch_bundle_shadowable_mask_5_T_1, bpu_5.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_5_T_3 = eq(_f3_fetch_bundle_shadowable_mask_5_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_5_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_5_T_5 = and(_f3_fetch_bundle_shadowable_mask_5_T_3, _f3_fetch_bundle_shadowable_mask_5_T_4) node _f3_fetch_bundle_shadowable_mask_5_T_6 = eq(f3_mask[5], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_5_T_7 = or(brsigs_5.shadowable, _f3_fetch_bundle_shadowable_mask_5_T_6) node _f3_fetch_bundle_shadowable_mask_5_T_8 = and(_f3_fetch_bundle_shadowable_mask_5_T_5, _f3_fetch_bundle_shadowable_mask_5_T_7) connect f3_fetch_bundle.shadowable_mask[5], _f3_fetch_bundle_shadowable_mask_5_T_8 connect f3_fetch_bundle.sfb_dests[5], offset_from_aligned_pc_5 node _f3_redirects_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h2)) node _f3_redirects_5_T_1 = eq(brsigs_5.cfi_type, UInt<3>(0h3)) node _f3_redirects_5_T_2 = or(_f3_redirects_5_T, _f3_redirects_5_T_1) node _f3_redirects_5_T_3 = eq(brsigs_5.cfi_type, UInt<3>(0h1)) node _f3_redirects_5_T_4 = and(_f3_redirects_5_T_3, f3_bpd_resp.io.deq.bits.preds[5].taken) node _f3_redirects_5_T_5 = and(_f3_redirects_5_T_4, UInt<1>(0h1)) node _f3_redirects_5_T_6 = or(_f3_redirects_5_T_2, _f3_redirects_5_T_5) node _f3_redirects_5_T_7 = and(f3_mask[5], _f3_redirects_5_T_6) connect f3_redirects[5], _f3_redirects_5_T_7 node _f3_br_mask_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h1)) node _f3_br_mask_5_T_1 = and(f3_mask[5], _f3_br_mask_5_T) connect f3_br_mask[5], _f3_br_mask_5_T_1 connect f3_cfi_types[5], brsigs_5.cfi_type connect f3_call_mask[5], brsigs_5.is_call connect f3_ret_mask[5], brsigs_5.is_ret connect f3_fetch_bundle.bp_debug_if_oh[5], bpu_5.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[5], bpu_5.io.xcpt_if node _T_49 = or(_T_48, f3_redirects[5]) wire valid_6 : UInt<1> inst bpu_6 of BreakpointUnit_17 connect bpu_6.clock, clock connect bpu_6.reset, reset connect bpu_6.io.status.uie, io.cpu.status.uie connect bpu_6.io.status.sie, io.cpu.status.sie connect bpu_6.io.status.hie, io.cpu.status.hie connect bpu_6.io.status.mie, io.cpu.status.mie connect bpu_6.io.status.upie, io.cpu.status.upie connect bpu_6.io.status.spie, io.cpu.status.spie connect bpu_6.io.status.ube, io.cpu.status.ube connect bpu_6.io.status.mpie, io.cpu.status.mpie connect bpu_6.io.status.spp, io.cpu.status.spp connect bpu_6.io.status.vs, io.cpu.status.vs connect bpu_6.io.status.mpp, io.cpu.status.mpp connect bpu_6.io.status.fs, io.cpu.status.fs connect bpu_6.io.status.xs, io.cpu.status.xs connect bpu_6.io.status.mprv, io.cpu.status.mprv connect bpu_6.io.status.sum, io.cpu.status.sum connect bpu_6.io.status.mxr, io.cpu.status.mxr connect bpu_6.io.status.tvm, io.cpu.status.tvm connect bpu_6.io.status.tw, io.cpu.status.tw connect bpu_6.io.status.tsr, io.cpu.status.tsr connect bpu_6.io.status.zero1, io.cpu.status.zero1 connect bpu_6.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_6.io.status.uxl, io.cpu.status.uxl connect bpu_6.io.status.sxl, io.cpu.status.sxl connect bpu_6.io.status.sbe, io.cpu.status.sbe connect bpu_6.io.status.mbe, io.cpu.status.mbe connect bpu_6.io.status.gva, io.cpu.status.gva connect bpu_6.io.status.mpv, io.cpu.status.mpv connect bpu_6.io.status.zero2, io.cpu.status.zero2 connect bpu_6.io.status.sd, io.cpu.status.sd connect bpu_6.io.status.v, io.cpu.status.v connect bpu_6.io.status.prv, io.cpu.status.prv connect bpu_6.io.status.dv, io.cpu.status.dv connect bpu_6.io.status.dprv, io.cpu.status.dprv connect bpu_6.io.status.isa, io.cpu.status.isa connect bpu_6.io.status.wfi, io.cpu.status.wfi connect bpu_6.io.status.cease, io.cpu.status.cease connect bpu_6.io.status.debug, io.cpu.status.debug invalidate bpu_6.io.ea connect bpu_6.io.mcontext, io.cpu.mcontext connect bpu_6.io.scontext, io.cpu.scontext wire brsigs_6 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_4 : UInt<32> inst exp_inst_rvc_exp_4 of RVCExpander_22 connect exp_inst_rvc_exp_4.clock, clock connect exp_inst_rvc_exp_4.reset, reset connect exp_inst_rvc_exp_4.io.in, inst_4 node exp_inst_4 = mux(exp_inst_rvc_exp_4.io.rvc, exp_inst_rvc_exp_4.io.out.bits, inst_4) node _pc_T_4 = add(f3_aligned_pc, UInt<4>(0hc)) node pc_4 = tail(_pc_T_4, 1) inst bpd_decoder_4 of BranchDecode_20 connect bpd_decoder_4.clock, clock connect bpd_decoder_4.reset, reset connect bpd_decoder_4.io.inst, exp_inst_4 connect bpd_decoder_4.io.pc, pc_4 connect bank_insts_1[2], inst_4 connect f3_fetch_bundle.insts[6], inst_4 connect f3_fetch_bundle.exp_insts[6], exp_inst_4 connect bpu_6.io.pc, pc_4 connect brsigs_6.shadowable, bpd_decoder_4.io.out.shadowable connect brsigs_6.sfb_offset, bpd_decoder_4.io.out.sfb_offset connect brsigs_6.cfi_type, bpd_decoder_4.io.out.cfi_type connect brsigs_6.target, bpd_decoder_4.io.out.target connect brsigs_6.is_call, bpd_decoder_4.io.out.is_call connect brsigs_6.is_ret, bpd_decoder_4.io.out.is_ret node _inst_T_5 = bits(bank_data_1, 63, 32) connect inst_4, _inst_T_5 node _valid_T_26 = bits(bank_insts_1[1], 1, 0) node _valid_T_27 = neq(_valid_T_26, UInt<2>(0h3)) node _valid_T_28 = eq(_valid_T_27, UInt<1>(0h0)) node _valid_T_29 = and(bank_mask_1[1], _valid_T_28) node _valid_T_30 = eq(_valid_T_29, UInt<1>(0h0)) connect valid_6, _valid_T_30 node _f3_is_rvc_6_T = bits(bank_insts_1[2], 1, 0) node _f3_is_rvc_6_T_1 = neq(_f3_is_rvc_6_T, UInt<2>(0h3)) connect f3_is_rvc[6], _f3_is_rvc_6_T_1 node _bank_mask_2_T_5 = bits(f3.io.deq.bits.mask, 6, 6) node _bank_mask_2_T_6 = and(f3.io.deq.valid, _bank_mask_2_T_5) node _bank_mask_2_T_7 = and(_bank_mask_2_T_6, valid_6) node _bank_mask_2_T_8 = eq(_T_49, UInt<1>(0h0)) node _bank_mask_2_T_9 = and(_bank_mask_2_T_7, _bank_mask_2_T_8) connect bank_mask_1[2], _bank_mask_2_T_9 node _f3_mask_6_T = bits(f3.io.deq.bits.mask, 6, 6) node _f3_mask_6_T_1 = and(f3.io.deq.valid, _f3_mask_6_T) node _f3_mask_6_T_2 = and(_f3_mask_6_T_1, valid_6) node _f3_mask_6_T_3 = eq(_T_49, UInt<1>(0h0)) node _f3_mask_6_T_4 = and(_f3_mask_6_T_2, _f3_mask_6_T_3) connect f3_mask[6], _f3_mask_6_T_4 node _f3_targs_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h3)) node _f3_targs_6_T_1 = mux(_f3_targs_6_T, f3_bpd_resp.io.deq.bits.preds[6].predicted_pc.bits, brsigs_6.target) connect f3_targs[6], _f3_targs_6_T_1 node _f3_btb_mispredicts_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_6_T_1 = and(_f3_btb_mispredicts_6_T, valid_6) node _f3_btb_mispredicts_6_T_2 = and(_f3_btb_mispredicts_6_T_1, f3_bpd_resp.io.deq.bits.preds[6].predicted_pc.valid) node _f3_btb_mispredicts_6_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[6].predicted_pc.bits, brsigs_6.target) node _f3_btb_mispredicts_6_T_4 = and(_f3_btb_mispredicts_6_T_2, _f3_btb_mispredicts_6_T_3) connect f3_btb_mispredicts[6], _f3_btb_mispredicts_6_T_4 node _f3_npc_plus4_mask_6_T = eq(f3_is_rvc[6], UInt<1>(0h0)) connect f3_npc_plus4_mask[6], _f3_npc_plus4_mask_6_T node _offset_from_aligned_pc_T_30 = add(UInt<7>(0hc), brsigs_6.sfb_offset.bits) node _offset_from_aligned_pc_T_31 = tail(_offset_from_aligned_pc_T_30, 1) node _offset_from_aligned_pc_T_32 = and(_T_43, UInt<1>(0h0)) node _offset_from_aligned_pc_T_33 = mux(_offset_from_aligned_pc_T_32, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_34 = sub(_offset_from_aligned_pc_T_31, _offset_from_aligned_pc_T_33) node offset_from_aligned_pc_6 = tail(_offset_from_aligned_pc_T_34, 1) wire lower_mask_6 : UInt<16> wire upper_mask_6 : UInt<16> node _lower_mask_T_6 = dshl(UInt<1>(0h1), UInt<3>(0h6)) connect lower_mask_6, _lower_mask_T_6 node _upper_mask_T_24 = bits(offset_from_aligned_pc_6, 5, 1) node _upper_mask_T_25 = dshl(UInt<1>(0h1), _upper_mask_T_24) node _upper_mask_T_26 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_27 = dshl(_upper_mask_T_25, _upper_mask_T_26) connect upper_mask_6, _upper_mask_T_27 node _f3_fetch_bundle_sfbs_6_T = and(f3_mask[6], brsigs_6.sfb_offset.valid) node _f3_fetch_bundle_sfbs_6_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_6_T_2 = leq(offset_from_aligned_pc_6, _f3_fetch_bundle_sfbs_6_T_1) node _f3_fetch_bundle_sfbs_6_T_3 = and(_f3_fetch_bundle_sfbs_6_T, _f3_fetch_bundle_sfbs_6_T_2) connect f3_fetch_bundle.sfbs[6], _f3_fetch_bundle_sfbs_6_T_3 node _f3_fetch_bundle_sfb_masks_6_T = dshr(lower_mask_6, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_6_T_1 = dshr(lower_mask_6, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_6_T_2 = dshr(lower_mask_6, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_6_T_3 = dshr(lower_mask_6, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_6_T_4 = dshr(lower_mask_6, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_6_T_5 = dshr(lower_mask_6, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_6_T_6 = dshr(lower_mask_6, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_6_T_7 = dshr(lower_mask_6, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_6_T_8 = dshr(lower_mask_6, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_6_T_9 = dshr(lower_mask_6, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_6_T_10 = dshr(lower_mask_6, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_6_T_11 = dshr(lower_mask_6, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_6_T_12 = dshr(lower_mask_6, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_6_T_13 = dshr(lower_mask_6, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_6_T_14 = dshr(lower_mask_6, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_6_T_15 = dshr(lower_mask_6, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_6_T_16 = or(_f3_fetch_bundle_sfb_masks_6_T, _f3_fetch_bundle_sfb_masks_6_T_1) node _f3_fetch_bundle_sfb_masks_6_T_17 = or(_f3_fetch_bundle_sfb_masks_6_T_16, _f3_fetch_bundle_sfb_masks_6_T_2) node _f3_fetch_bundle_sfb_masks_6_T_18 = or(_f3_fetch_bundle_sfb_masks_6_T_17, _f3_fetch_bundle_sfb_masks_6_T_3) node _f3_fetch_bundle_sfb_masks_6_T_19 = or(_f3_fetch_bundle_sfb_masks_6_T_18, _f3_fetch_bundle_sfb_masks_6_T_4) node _f3_fetch_bundle_sfb_masks_6_T_20 = or(_f3_fetch_bundle_sfb_masks_6_T_19, _f3_fetch_bundle_sfb_masks_6_T_5) node _f3_fetch_bundle_sfb_masks_6_T_21 = or(_f3_fetch_bundle_sfb_masks_6_T_20, _f3_fetch_bundle_sfb_masks_6_T_6) node _f3_fetch_bundle_sfb_masks_6_T_22 = or(_f3_fetch_bundle_sfb_masks_6_T_21, _f3_fetch_bundle_sfb_masks_6_T_7) node _f3_fetch_bundle_sfb_masks_6_T_23 = or(_f3_fetch_bundle_sfb_masks_6_T_22, _f3_fetch_bundle_sfb_masks_6_T_8) node _f3_fetch_bundle_sfb_masks_6_T_24 = or(_f3_fetch_bundle_sfb_masks_6_T_23, _f3_fetch_bundle_sfb_masks_6_T_9) node _f3_fetch_bundle_sfb_masks_6_T_25 = or(_f3_fetch_bundle_sfb_masks_6_T_24, _f3_fetch_bundle_sfb_masks_6_T_10) node _f3_fetch_bundle_sfb_masks_6_T_26 = or(_f3_fetch_bundle_sfb_masks_6_T_25, _f3_fetch_bundle_sfb_masks_6_T_11) node _f3_fetch_bundle_sfb_masks_6_T_27 = or(_f3_fetch_bundle_sfb_masks_6_T_26, _f3_fetch_bundle_sfb_masks_6_T_12) node _f3_fetch_bundle_sfb_masks_6_T_28 = or(_f3_fetch_bundle_sfb_masks_6_T_27, _f3_fetch_bundle_sfb_masks_6_T_13) node _f3_fetch_bundle_sfb_masks_6_T_29 = or(_f3_fetch_bundle_sfb_masks_6_T_28, _f3_fetch_bundle_sfb_masks_6_T_14) node _f3_fetch_bundle_sfb_masks_6_T_30 = or(_f3_fetch_bundle_sfb_masks_6_T_29, _f3_fetch_bundle_sfb_masks_6_T_15) node _f3_fetch_bundle_sfb_masks_6_T_31 = not(_f3_fetch_bundle_sfb_masks_6_T_30) node _f3_fetch_bundle_sfb_masks_6_T_32 = dshl(upper_mask_6, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_6_T_33 = bits(_f3_fetch_bundle_sfb_masks_6_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_34 = dshl(upper_mask_6, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_6_T_35 = bits(_f3_fetch_bundle_sfb_masks_6_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_36 = dshl(upper_mask_6, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_6_T_37 = bits(_f3_fetch_bundle_sfb_masks_6_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_38 = dshl(upper_mask_6, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_6_T_39 = bits(_f3_fetch_bundle_sfb_masks_6_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_40 = dshl(upper_mask_6, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_6_T_41 = bits(_f3_fetch_bundle_sfb_masks_6_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_42 = dshl(upper_mask_6, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_6_T_43 = bits(_f3_fetch_bundle_sfb_masks_6_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_44 = dshl(upper_mask_6, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_6_T_45 = bits(_f3_fetch_bundle_sfb_masks_6_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_46 = dshl(upper_mask_6, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_6_T_47 = bits(_f3_fetch_bundle_sfb_masks_6_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_48 = dshl(upper_mask_6, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_6_T_49 = bits(_f3_fetch_bundle_sfb_masks_6_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_50 = dshl(upper_mask_6, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_6_T_51 = bits(_f3_fetch_bundle_sfb_masks_6_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_52 = dshl(upper_mask_6, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_6_T_53 = bits(_f3_fetch_bundle_sfb_masks_6_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_54 = dshl(upper_mask_6, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_6_T_55 = bits(_f3_fetch_bundle_sfb_masks_6_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_56 = dshl(upper_mask_6, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_6_T_57 = bits(_f3_fetch_bundle_sfb_masks_6_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_58 = dshl(upper_mask_6, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_6_T_59 = bits(_f3_fetch_bundle_sfb_masks_6_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_60 = dshl(upper_mask_6, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_6_T_61 = bits(_f3_fetch_bundle_sfb_masks_6_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_62 = dshl(upper_mask_6, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_6_T_63 = bits(_f3_fetch_bundle_sfb_masks_6_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_64 = or(_f3_fetch_bundle_sfb_masks_6_T_33, _f3_fetch_bundle_sfb_masks_6_T_35) node _f3_fetch_bundle_sfb_masks_6_T_65 = or(_f3_fetch_bundle_sfb_masks_6_T_64, _f3_fetch_bundle_sfb_masks_6_T_37) node _f3_fetch_bundle_sfb_masks_6_T_66 = or(_f3_fetch_bundle_sfb_masks_6_T_65, _f3_fetch_bundle_sfb_masks_6_T_39) node _f3_fetch_bundle_sfb_masks_6_T_67 = or(_f3_fetch_bundle_sfb_masks_6_T_66, _f3_fetch_bundle_sfb_masks_6_T_41) node _f3_fetch_bundle_sfb_masks_6_T_68 = or(_f3_fetch_bundle_sfb_masks_6_T_67, _f3_fetch_bundle_sfb_masks_6_T_43) node _f3_fetch_bundle_sfb_masks_6_T_69 = or(_f3_fetch_bundle_sfb_masks_6_T_68, _f3_fetch_bundle_sfb_masks_6_T_45) node _f3_fetch_bundle_sfb_masks_6_T_70 = or(_f3_fetch_bundle_sfb_masks_6_T_69, _f3_fetch_bundle_sfb_masks_6_T_47) node _f3_fetch_bundle_sfb_masks_6_T_71 = or(_f3_fetch_bundle_sfb_masks_6_T_70, _f3_fetch_bundle_sfb_masks_6_T_49) node _f3_fetch_bundle_sfb_masks_6_T_72 = or(_f3_fetch_bundle_sfb_masks_6_T_71, _f3_fetch_bundle_sfb_masks_6_T_51) node _f3_fetch_bundle_sfb_masks_6_T_73 = or(_f3_fetch_bundle_sfb_masks_6_T_72, _f3_fetch_bundle_sfb_masks_6_T_53) node _f3_fetch_bundle_sfb_masks_6_T_74 = or(_f3_fetch_bundle_sfb_masks_6_T_73, _f3_fetch_bundle_sfb_masks_6_T_55) node _f3_fetch_bundle_sfb_masks_6_T_75 = or(_f3_fetch_bundle_sfb_masks_6_T_74, _f3_fetch_bundle_sfb_masks_6_T_57) node _f3_fetch_bundle_sfb_masks_6_T_76 = or(_f3_fetch_bundle_sfb_masks_6_T_75, _f3_fetch_bundle_sfb_masks_6_T_59) node _f3_fetch_bundle_sfb_masks_6_T_77 = or(_f3_fetch_bundle_sfb_masks_6_T_76, _f3_fetch_bundle_sfb_masks_6_T_61) node _f3_fetch_bundle_sfb_masks_6_T_78 = or(_f3_fetch_bundle_sfb_masks_6_T_77, _f3_fetch_bundle_sfb_masks_6_T_63) node _f3_fetch_bundle_sfb_masks_6_T_79 = not(_f3_fetch_bundle_sfb_masks_6_T_78) node _f3_fetch_bundle_sfb_masks_6_T_80 = and(_f3_fetch_bundle_sfb_masks_6_T_31, _f3_fetch_bundle_sfb_masks_6_T_79) connect f3_fetch_bundle.sfb_masks[6], _f3_fetch_bundle_sfb_masks_6_T_80 node _f3_fetch_bundle_shadowable_mask_6_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_6_T_1 = or(_f3_fetch_bundle_shadowable_mask_6_T, bpu_6.io.debug_if) node _f3_fetch_bundle_shadowable_mask_6_T_2 = or(_f3_fetch_bundle_shadowable_mask_6_T_1, bpu_6.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_6_T_3 = eq(_f3_fetch_bundle_shadowable_mask_6_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_6_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_6_T_5 = and(_f3_fetch_bundle_shadowable_mask_6_T_3, _f3_fetch_bundle_shadowable_mask_6_T_4) node _f3_fetch_bundle_shadowable_mask_6_T_6 = eq(f3_mask[6], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_6_T_7 = or(brsigs_6.shadowable, _f3_fetch_bundle_shadowable_mask_6_T_6) node _f3_fetch_bundle_shadowable_mask_6_T_8 = and(_f3_fetch_bundle_shadowable_mask_6_T_5, _f3_fetch_bundle_shadowable_mask_6_T_7) connect f3_fetch_bundle.shadowable_mask[6], _f3_fetch_bundle_shadowable_mask_6_T_8 connect f3_fetch_bundle.sfb_dests[6], offset_from_aligned_pc_6 node _f3_redirects_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h2)) node _f3_redirects_6_T_1 = eq(brsigs_6.cfi_type, UInt<3>(0h3)) node _f3_redirects_6_T_2 = or(_f3_redirects_6_T, _f3_redirects_6_T_1) node _f3_redirects_6_T_3 = eq(brsigs_6.cfi_type, UInt<3>(0h1)) node _f3_redirects_6_T_4 = and(_f3_redirects_6_T_3, f3_bpd_resp.io.deq.bits.preds[6].taken) node _f3_redirects_6_T_5 = and(_f3_redirects_6_T_4, UInt<1>(0h1)) node _f3_redirects_6_T_6 = or(_f3_redirects_6_T_2, _f3_redirects_6_T_5) node _f3_redirects_6_T_7 = and(f3_mask[6], _f3_redirects_6_T_6) connect f3_redirects[6], _f3_redirects_6_T_7 node _f3_br_mask_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h1)) node _f3_br_mask_6_T_1 = and(f3_mask[6], _f3_br_mask_6_T) connect f3_br_mask[6], _f3_br_mask_6_T_1 connect f3_cfi_types[6], brsigs_6.cfi_type connect f3_call_mask[6], brsigs_6.is_call connect f3_ret_mask[6], brsigs_6.is_ret connect f3_fetch_bundle.bp_debug_if_oh[6], bpu_6.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[6], bpu_6.io.xcpt_if node _T_50 = or(_T_49, f3_redirects[6]) wire valid_7 : UInt<1> inst bpu_7 of BreakpointUnit_18 connect bpu_7.clock, clock connect bpu_7.reset, reset connect bpu_7.io.status.uie, io.cpu.status.uie connect bpu_7.io.status.sie, io.cpu.status.sie connect bpu_7.io.status.hie, io.cpu.status.hie connect bpu_7.io.status.mie, io.cpu.status.mie connect bpu_7.io.status.upie, io.cpu.status.upie connect bpu_7.io.status.spie, io.cpu.status.spie connect bpu_7.io.status.ube, io.cpu.status.ube connect bpu_7.io.status.mpie, io.cpu.status.mpie connect bpu_7.io.status.spp, io.cpu.status.spp connect bpu_7.io.status.vs, io.cpu.status.vs connect bpu_7.io.status.mpp, io.cpu.status.mpp connect bpu_7.io.status.fs, io.cpu.status.fs connect bpu_7.io.status.xs, io.cpu.status.xs connect bpu_7.io.status.mprv, io.cpu.status.mprv connect bpu_7.io.status.sum, io.cpu.status.sum connect bpu_7.io.status.mxr, io.cpu.status.mxr connect bpu_7.io.status.tvm, io.cpu.status.tvm connect bpu_7.io.status.tw, io.cpu.status.tw connect bpu_7.io.status.tsr, io.cpu.status.tsr connect bpu_7.io.status.zero1, io.cpu.status.zero1 connect bpu_7.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_7.io.status.uxl, io.cpu.status.uxl connect bpu_7.io.status.sxl, io.cpu.status.sxl connect bpu_7.io.status.sbe, io.cpu.status.sbe connect bpu_7.io.status.mbe, io.cpu.status.mbe connect bpu_7.io.status.gva, io.cpu.status.gva connect bpu_7.io.status.mpv, io.cpu.status.mpv connect bpu_7.io.status.zero2, io.cpu.status.zero2 connect bpu_7.io.status.sd, io.cpu.status.sd connect bpu_7.io.status.v, io.cpu.status.v connect bpu_7.io.status.prv, io.cpu.status.prv connect bpu_7.io.status.dv, io.cpu.status.dv connect bpu_7.io.status.dprv, io.cpu.status.dprv connect bpu_7.io.status.isa, io.cpu.status.isa connect bpu_7.io.status.wfi, io.cpu.status.wfi connect bpu_7.io.status.cease, io.cpu.status.cease connect bpu_7.io.status.debug, io.cpu.status.debug invalidate bpu_7.io.ea connect bpu_7.io.mcontext, io.cpu.mcontext connect bpu_7.io.scontext, io.cpu.scontext wire brsigs_7 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_5 : UInt<32> inst exp_inst_rvc_exp_5 of RVCExpander_23 connect exp_inst_rvc_exp_5.clock, clock connect exp_inst_rvc_exp_5.reset, reset connect exp_inst_rvc_exp_5.io.in, inst_5 node exp_inst_5 = mux(exp_inst_rvc_exp_5.io.rvc, exp_inst_rvc_exp_5.io.out.bits, inst_5) node _pc_T_5 = add(f3_aligned_pc, UInt<4>(0he)) node pc_5 = tail(_pc_T_5, 1) inst bpd_decoder_5 of BranchDecode_21 connect bpd_decoder_5.clock, clock connect bpd_decoder_5.reset, reset connect bpd_decoder_5.io.inst, exp_inst_5 connect bpd_decoder_5.io.pc, pc_5 connect bank_insts_1[3], inst_5 connect f3_fetch_bundle.insts[7], inst_5 connect f3_fetch_bundle.exp_insts[7], exp_inst_5 connect bpu_7.io.pc, pc_5 connect brsigs_7.shadowable, bpd_decoder_5.io.out.shadowable connect brsigs_7.sfb_offset, bpd_decoder_5.io.out.sfb_offset connect brsigs_7.cfi_type, bpd_decoder_5.io.out.cfi_type connect brsigs_7.target, bpd_decoder_5.io.out.target connect brsigs_7.is_call, bpd_decoder_5.io.out.is_call connect brsigs_7.is_ret, bpd_decoder_5.io.out.is_ret node _inst_T_6 = bits(bank_data_1, 63, 48) node _inst_T_7 = cat(UInt<16>(0h0), _inst_T_6) connect inst_5, _inst_T_7 node _valid_T_31 = bits(bank_insts_1[2], 1, 0) node _valid_T_32 = neq(_valid_T_31, UInt<2>(0h3)) node _valid_T_33 = eq(_valid_T_32, UInt<1>(0h0)) node _valid_T_34 = and(bank_mask_1[2], _valid_T_33) node _valid_T_35 = bits(inst_5, 1, 0) node _valid_T_36 = neq(_valid_T_35, UInt<2>(0h3)) node _valid_T_37 = eq(_valid_T_36, UInt<1>(0h0)) node _valid_T_38 = or(_valid_T_34, _valid_T_37) node _valid_T_39 = eq(_valid_T_38, UInt<1>(0h0)) connect valid_7, _valid_T_39 node _f3_is_rvc_7_T = bits(bank_insts_1[3], 1, 0) node _f3_is_rvc_7_T_1 = neq(_f3_is_rvc_7_T, UInt<2>(0h3)) connect f3_is_rvc[7], _f3_is_rvc_7_T_1 node _bank_mask_3_T_5 = bits(f3.io.deq.bits.mask, 7, 7) node _bank_mask_3_T_6 = and(f3.io.deq.valid, _bank_mask_3_T_5) node _bank_mask_3_T_7 = and(_bank_mask_3_T_6, valid_7) node _bank_mask_3_T_8 = eq(_T_50, UInt<1>(0h0)) node _bank_mask_3_T_9 = and(_bank_mask_3_T_7, _bank_mask_3_T_8) connect bank_mask_1[3], _bank_mask_3_T_9 node _f3_mask_7_T = bits(f3.io.deq.bits.mask, 7, 7) node _f3_mask_7_T_1 = and(f3.io.deq.valid, _f3_mask_7_T) node _f3_mask_7_T_2 = and(_f3_mask_7_T_1, valid_7) node _f3_mask_7_T_3 = eq(_T_50, UInt<1>(0h0)) node _f3_mask_7_T_4 = and(_f3_mask_7_T_2, _f3_mask_7_T_3) connect f3_mask[7], _f3_mask_7_T_4 node _f3_targs_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h3)) node _f3_targs_7_T_1 = mux(_f3_targs_7_T, f3_bpd_resp.io.deq.bits.preds[7].predicted_pc.bits, brsigs_7.target) connect f3_targs[7], _f3_targs_7_T_1 node _f3_btb_mispredicts_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_7_T_1 = and(_f3_btb_mispredicts_7_T, valid_7) node _f3_btb_mispredicts_7_T_2 = and(_f3_btb_mispredicts_7_T_1, f3_bpd_resp.io.deq.bits.preds[7].predicted_pc.valid) node _f3_btb_mispredicts_7_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[7].predicted_pc.bits, brsigs_7.target) node _f3_btb_mispredicts_7_T_4 = and(_f3_btb_mispredicts_7_T_2, _f3_btb_mispredicts_7_T_3) connect f3_btb_mispredicts[7], _f3_btb_mispredicts_7_T_4 node _f3_npc_plus4_mask_7_T = eq(f3_is_rvc[7], UInt<1>(0h0)) connect f3_npc_plus4_mask[7], _f3_npc_plus4_mask_7_T node _offset_from_aligned_pc_T_35 = add(UInt<7>(0he), brsigs_7.sfb_offset.bits) node _offset_from_aligned_pc_T_36 = tail(_offset_from_aligned_pc_T_35, 1) node _offset_from_aligned_pc_T_37 = and(_T_43, UInt<1>(0h0)) node _offset_from_aligned_pc_T_38 = mux(_offset_from_aligned_pc_T_37, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_39 = sub(_offset_from_aligned_pc_T_36, _offset_from_aligned_pc_T_38) node offset_from_aligned_pc_7 = tail(_offset_from_aligned_pc_T_39, 1) wire lower_mask_7 : UInt<16> wire upper_mask_7 : UInt<16> node _lower_mask_T_7 = dshl(UInt<1>(0h1), UInt<3>(0h7)) connect lower_mask_7, _lower_mask_T_7 node _upper_mask_T_28 = bits(offset_from_aligned_pc_7, 5, 1) node _upper_mask_T_29 = dshl(UInt<1>(0h1), _upper_mask_T_28) node _upper_mask_T_30 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_31 = dshl(_upper_mask_T_29, _upper_mask_T_30) connect upper_mask_7, _upper_mask_T_31 node _f3_fetch_bundle_sfbs_7_T = and(f3_mask[7], brsigs_7.sfb_offset.valid) node _f3_fetch_bundle_sfbs_7_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_7_T_2 = leq(offset_from_aligned_pc_7, _f3_fetch_bundle_sfbs_7_T_1) node _f3_fetch_bundle_sfbs_7_T_3 = and(_f3_fetch_bundle_sfbs_7_T, _f3_fetch_bundle_sfbs_7_T_2) connect f3_fetch_bundle.sfbs[7], _f3_fetch_bundle_sfbs_7_T_3 node _f3_fetch_bundle_sfb_masks_7_T = dshr(lower_mask_7, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_7_T_1 = dshr(lower_mask_7, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_7_T_2 = dshr(lower_mask_7, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_7_T_3 = dshr(lower_mask_7, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_7_T_4 = dshr(lower_mask_7, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_7_T_5 = dshr(lower_mask_7, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_7_T_6 = dshr(lower_mask_7, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_7_T_7 = dshr(lower_mask_7, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_7_T_8 = dshr(lower_mask_7, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_7_T_9 = dshr(lower_mask_7, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_7_T_10 = dshr(lower_mask_7, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_7_T_11 = dshr(lower_mask_7, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_7_T_12 = dshr(lower_mask_7, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_7_T_13 = dshr(lower_mask_7, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_7_T_14 = dshr(lower_mask_7, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_7_T_15 = dshr(lower_mask_7, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_7_T_16 = or(_f3_fetch_bundle_sfb_masks_7_T, _f3_fetch_bundle_sfb_masks_7_T_1) node _f3_fetch_bundle_sfb_masks_7_T_17 = or(_f3_fetch_bundle_sfb_masks_7_T_16, _f3_fetch_bundle_sfb_masks_7_T_2) node _f3_fetch_bundle_sfb_masks_7_T_18 = or(_f3_fetch_bundle_sfb_masks_7_T_17, _f3_fetch_bundle_sfb_masks_7_T_3) node _f3_fetch_bundle_sfb_masks_7_T_19 = or(_f3_fetch_bundle_sfb_masks_7_T_18, _f3_fetch_bundle_sfb_masks_7_T_4) node _f3_fetch_bundle_sfb_masks_7_T_20 = or(_f3_fetch_bundle_sfb_masks_7_T_19, _f3_fetch_bundle_sfb_masks_7_T_5) node _f3_fetch_bundle_sfb_masks_7_T_21 = or(_f3_fetch_bundle_sfb_masks_7_T_20, _f3_fetch_bundle_sfb_masks_7_T_6) node _f3_fetch_bundle_sfb_masks_7_T_22 = or(_f3_fetch_bundle_sfb_masks_7_T_21, _f3_fetch_bundle_sfb_masks_7_T_7) node _f3_fetch_bundle_sfb_masks_7_T_23 = or(_f3_fetch_bundle_sfb_masks_7_T_22, _f3_fetch_bundle_sfb_masks_7_T_8) node _f3_fetch_bundle_sfb_masks_7_T_24 = or(_f3_fetch_bundle_sfb_masks_7_T_23, _f3_fetch_bundle_sfb_masks_7_T_9) node _f3_fetch_bundle_sfb_masks_7_T_25 = or(_f3_fetch_bundle_sfb_masks_7_T_24, _f3_fetch_bundle_sfb_masks_7_T_10) node _f3_fetch_bundle_sfb_masks_7_T_26 = or(_f3_fetch_bundle_sfb_masks_7_T_25, _f3_fetch_bundle_sfb_masks_7_T_11) node _f3_fetch_bundle_sfb_masks_7_T_27 = or(_f3_fetch_bundle_sfb_masks_7_T_26, _f3_fetch_bundle_sfb_masks_7_T_12) node _f3_fetch_bundle_sfb_masks_7_T_28 = or(_f3_fetch_bundle_sfb_masks_7_T_27, _f3_fetch_bundle_sfb_masks_7_T_13) node _f3_fetch_bundle_sfb_masks_7_T_29 = or(_f3_fetch_bundle_sfb_masks_7_T_28, _f3_fetch_bundle_sfb_masks_7_T_14) node _f3_fetch_bundle_sfb_masks_7_T_30 = or(_f3_fetch_bundle_sfb_masks_7_T_29, _f3_fetch_bundle_sfb_masks_7_T_15) node _f3_fetch_bundle_sfb_masks_7_T_31 = not(_f3_fetch_bundle_sfb_masks_7_T_30) node _f3_fetch_bundle_sfb_masks_7_T_32 = dshl(upper_mask_7, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_7_T_33 = bits(_f3_fetch_bundle_sfb_masks_7_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_34 = dshl(upper_mask_7, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_7_T_35 = bits(_f3_fetch_bundle_sfb_masks_7_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_36 = dshl(upper_mask_7, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_7_T_37 = bits(_f3_fetch_bundle_sfb_masks_7_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_38 = dshl(upper_mask_7, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_7_T_39 = bits(_f3_fetch_bundle_sfb_masks_7_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_40 = dshl(upper_mask_7, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_7_T_41 = bits(_f3_fetch_bundle_sfb_masks_7_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_42 = dshl(upper_mask_7, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_7_T_43 = bits(_f3_fetch_bundle_sfb_masks_7_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_44 = dshl(upper_mask_7, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_7_T_45 = bits(_f3_fetch_bundle_sfb_masks_7_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_46 = dshl(upper_mask_7, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_7_T_47 = bits(_f3_fetch_bundle_sfb_masks_7_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_48 = dshl(upper_mask_7, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_7_T_49 = bits(_f3_fetch_bundle_sfb_masks_7_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_50 = dshl(upper_mask_7, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_7_T_51 = bits(_f3_fetch_bundle_sfb_masks_7_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_52 = dshl(upper_mask_7, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_7_T_53 = bits(_f3_fetch_bundle_sfb_masks_7_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_54 = dshl(upper_mask_7, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_7_T_55 = bits(_f3_fetch_bundle_sfb_masks_7_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_56 = dshl(upper_mask_7, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_7_T_57 = bits(_f3_fetch_bundle_sfb_masks_7_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_58 = dshl(upper_mask_7, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_7_T_59 = bits(_f3_fetch_bundle_sfb_masks_7_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_60 = dshl(upper_mask_7, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_7_T_61 = bits(_f3_fetch_bundle_sfb_masks_7_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_62 = dshl(upper_mask_7, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_7_T_63 = bits(_f3_fetch_bundle_sfb_masks_7_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_64 = or(_f3_fetch_bundle_sfb_masks_7_T_33, _f3_fetch_bundle_sfb_masks_7_T_35) node _f3_fetch_bundle_sfb_masks_7_T_65 = or(_f3_fetch_bundle_sfb_masks_7_T_64, _f3_fetch_bundle_sfb_masks_7_T_37) node _f3_fetch_bundle_sfb_masks_7_T_66 = or(_f3_fetch_bundle_sfb_masks_7_T_65, _f3_fetch_bundle_sfb_masks_7_T_39) node _f3_fetch_bundle_sfb_masks_7_T_67 = or(_f3_fetch_bundle_sfb_masks_7_T_66, _f3_fetch_bundle_sfb_masks_7_T_41) node _f3_fetch_bundle_sfb_masks_7_T_68 = or(_f3_fetch_bundle_sfb_masks_7_T_67, _f3_fetch_bundle_sfb_masks_7_T_43) node _f3_fetch_bundle_sfb_masks_7_T_69 = or(_f3_fetch_bundle_sfb_masks_7_T_68, _f3_fetch_bundle_sfb_masks_7_T_45) node _f3_fetch_bundle_sfb_masks_7_T_70 = or(_f3_fetch_bundle_sfb_masks_7_T_69, _f3_fetch_bundle_sfb_masks_7_T_47) node _f3_fetch_bundle_sfb_masks_7_T_71 = or(_f3_fetch_bundle_sfb_masks_7_T_70, _f3_fetch_bundle_sfb_masks_7_T_49) node _f3_fetch_bundle_sfb_masks_7_T_72 = or(_f3_fetch_bundle_sfb_masks_7_T_71, _f3_fetch_bundle_sfb_masks_7_T_51) node _f3_fetch_bundle_sfb_masks_7_T_73 = or(_f3_fetch_bundle_sfb_masks_7_T_72, _f3_fetch_bundle_sfb_masks_7_T_53) node _f3_fetch_bundle_sfb_masks_7_T_74 = or(_f3_fetch_bundle_sfb_masks_7_T_73, _f3_fetch_bundle_sfb_masks_7_T_55) node _f3_fetch_bundle_sfb_masks_7_T_75 = or(_f3_fetch_bundle_sfb_masks_7_T_74, _f3_fetch_bundle_sfb_masks_7_T_57) node _f3_fetch_bundle_sfb_masks_7_T_76 = or(_f3_fetch_bundle_sfb_masks_7_T_75, _f3_fetch_bundle_sfb_masks_7_T_59) node _f3_fetch_bundle_sfb_masks_7_T_77 = or(_f3_fetch_bundle_sfb_masks_7_T_76, _f3_fetch_bundle_sfb_masks_7_T_61) node _f3_fetch_bundle_sfb_masks_7_T_78 = or(_f3_fetch_bundle_sfb_masks_7_T_77, _f3_fetch_bundle_sfb_masks_7_T_63) node _f3_fetch_bundle_sfb_masks_7_T_79 = not(_f3_fetch_bundle_sfb_masks_7_T_78) node _f3_fetch_bundle_sfb_masks_7_T_80 = and(_f3_fetch_bundle_sfb_masks_7_T_31, _f3_fetch_bundle_sfb_masks_7_T_79) connect f3_fetch_bundle.sfb_masks[7], _f3_fetch_bundle_sfb_masks_7_T_80 node _f3_fetch_bundle_shadowable_mask_7_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_7_T_1 = or(_f3_fetch_bundle_shadowable_mask_7_T, bpu_7.io.debug_if) node _f3_fetch_bundle_shadowable_mask_7_T_2 = or(_f3_fetch_bundle_shadowable_mask_7_T_1, bpu_7.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_7_T_3 = eq(_f3_fetch_bundle_shadowable_mask_7_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_7_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_7_T_5 = and(_f3_fetch_bundle_shadowable_mask_7_T_3, _f3_fetch_bundle_shadowable_mask_7_T_4) node _f3_fetch_bundle_shadowable_mask_7_T_6 = eq(f3_mask[7], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_7_T_7 = or(brsigs_7.shadowable, _f3_fetch_bundle_shadowable_mask_7_T_6) node _f3_fetch_bundle_shadowable_mask_7_T_8 = and(_f3_fetch_bundle_shadowable_mask_7_T_5, _f3_fetch_bundle_shadowable_mask_7_T_7) connect f3_fetch_bundle.shadowable_mask[7], _f3_fetch_bundle_shadowable_mask_7_T_8 connect f3_fetch_bundle.sfb_dests[7], offset_from_aligned_pc_7 node _f3_redirects_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h2)) node _f3_redirects_7_T_1 = eq(brsigs_7.cfi_type, UInt<3>(0h3)) node _f3_redirects_7_T_2 = or(_f3_redirects_7_T, _f3_redirects_7_T_1) node _f3_redirects_7_T_3 = eq(brsigs_7.cfi_type, UInt<3>(0h1)) node _f3_redirects_7_T_4 = and(_f3_redirects_7_T_3, f3_bpd_resp.io.deq.bits.preds[7].taken) node _f3_redirects_7_T_5 = and(_f3_redirects_7_T_4, UInt<1>(0h1)) node _f3_redirects_7_T_6 = or(_f3_redirects_7_T_2, _f3_redirects_7_T_5) node _f3_redirects_7_T_7 = and(f3_mask[7], _f3_redirects_7_T_6) connect f3_redirects[7], _f3_redirects_7_T_7 node _f3_br_mask_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h1)) node _f3_br_mask_7_T_1 = and(f3_mask[7], _f3_br_mask_7_T) connect f3_br_mask[7], _f3_br_mask_7_T_1 connect f3_cfi_types[7], brsigs_7.cfi_type connect f3_call_mask[7], brsigs_7.is_call connect f3_ret_mask[7], brsigs_7.is_ret connect f3_fetch_bundle.bp_debug_if_oh[7], bpu_7.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[7], bpu_7.io.xcpt_if node _T_51 = or(_T_50, f3_redirects[7]) node _T_52 = bits(bank_insts_1[3], 15, 0) node _T_53 = bits(f3_bank_mask, 1, 1) node _T_54 = bits(bank_insts_1[2], 1, 0) node _T_55 = neq(_T_54, UInt<2>(0h3)) node _T_56 = eq(_T_55, UInt<1>(0h0)) node _T_57 = and(bank_mask_1[2], _T_56) node _T_58 = eq(_T_57, UInt<1>(0h0)) node _T_59 = bits(_T_52, 1, 0) node _T_60 = neq(_T_59, UInt<2>(0h3)) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(_T_58, _T_61) node _T_63 = mux(_T_53, _T_62, _T_43) node _T_64 = bits(f3_bank_mask, 1, 1) node _T_65 = bits(_T_52, 15, 0) node _T_66 = mux(_T_64, _T_65, _T_46) connect f3_fetch_bundle.cfi_type, f3_cfi_types[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_is_call, f3_call_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_is_ret, f3_ret_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_npc_plus4, f3_npc_plus4_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.ghist, f3.io.deq.bits.ghist connect f3_fetch_bundle.lhist, f3_bpd_resp.io.deq.bits.lhist connect f3_fetch_bundle.bpd_meta, f3_bpd_resp.io.deq.bits.meta connect f3_fetch_bundle.end_half.valid, _T_63 connect f3_fetch_bundle.end_half.bits, _T_66 node _T_67 = and(f3.io.deq.ready, f3.io.deq.valid) when _T_67 : connect f3_prev_is_half, _T_63 connect f3_prev_half, _T_66 node _T_68 = eq(f3_bpd_resp.io.deq.bits.pc, f3_fetch_bundle.pc) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed\n at frontend.scala:770 assert(f3_bpd_resp.io.deq.bits.pc === f3_fetch_bundle.pc)\n") : printf assert(clock, _T_68, UInt<1>(0h1), "") : assert when f3_clear : connect f3_prev_is_half, UInt<1>(0h0) node _f3_fetch_bundle_cfi_idx_valid_T = or(f3_redirects[0], f3_redirects[1]) node _f3_fetch_bundle_cfi_idx_valid_T_1 = or(_f3_fetch_bundle_cfi_idx_valid_T, f3_redirects[2]) node _f3_fetch_bundle_cfi_idx_valid_T_2 = or(_f3_fetch_bundle_cfi_idx_valid_T_1, f3_redirects[3]) node _f3_fetch_bundle_cfi_idx_valid_T_3 = or(_f3_fetch_bundle_cfi_idx_valid_T_2, f3_redirects[4]) node _f3_fetch_bundle_cfi_idx_valid_T_4 = or(_f3_fetch_bundle_cfi_idx_valid_T_3, f3_redirects[5]) node _f3_fetch_bundle_cfi_idx_valid_T_5 = or(_f3_fetch_bundle_cfi_idx_valid_T_4, f3_redirects[6]) node _f3_fetch_bundle_cfi_idx_valid_T_6 = or(_f3_fetch_bundle_cfi_idx_valid_T_5, f3_redirects[7]) connect f3_fetch_bundle.cfi_idx.valid, _f3_fetch_bundle_cfi_idx_valid_T_6 node _f3_fetch_bundle_cfi_idx_bits_T = mux(f3_redirects[6], UInt<3>(0h6), UInt<3>(0h7)) node _f3_fetch_bundle_cfi_idx_bits_T_1 = mux(f3_redirects[5], UInt<3>(0h5), _f3_fetch_bundle_cfi_idx_bits_T) node _f3_fetch_bundle_cfi_idx_bits_T_2 = mux(f3_redirects[4], UInt<3>(0h4), _f3_fetch_bundle_cfi_idx_bits_T_1) node _f3_fetch_bundle_cfi_idx_bits_T_3 = mux(f3_redirects[3], UInt<2>(0h3), _f3_fetch_bundle_cfi_idx_bits_T_2) node _f3_fetch_bundle_cfi_idx_bits_T_4 = mux(f3_redirects[2], UInt<2>(0h2), _f3_fetch_bundle_cfi_idx_bits_T_3) node _f3_fetch_bundle_cfi_idx_bits_T_5 = mux(f3_redirects[1], UInt<1>(0h1), _f3_fetch_bundle_cfi_idx_bits_T_4) node _f3_fetch_bundle_cfi_idx_bits_T_6 = mux(f3_redirects[0], UInt<1>(0h0), _f3_fetch_bundle_cfi_idx_bits_T_5) connect f3_fetch_bundle.cfi_idx.bits, _f3_fetch_bundle_cfi_idx_bits_T_6 connect f3_fetch_bundle.ras_top, ras.io.read_addr node _f3_predicted_target_T = or(f3_redirects[0], f3_redirects[1]) node _f3_predicted_target_T_1 = or(_f3_predicted_target_T, f3_redirects[2]) node _f3_predicted_target_T_2 = or(_f3_predicted_target_T_1, f3_redirects[3]) node _f3_predicted_target_T_3 = or(_f3_predicted_target_T_2, f3_redirects[4]) node _f3_predicted_target_T_4 = or(_f3_predicted_target_T_3, f3_redirects[5]) node _f3_predicted_target_T_5 = or(_f3_predicted_target_T_4, f3_redirects[6]) node _f3_predicted_target_T_6 = or(_f3_predicted_target_T_5, f3_redirects[7]) node _f3_predicted_target_T_7 = and(f3_fetch_bundle.cfi_is_ret, UInt<1>(0h1)) node _f3_predicted_target_T_8 = and(_f3_predicted_target_T_7, UInt<1>(0h1)) node _f3_predicted_target_T_9 = mux(f3_redirects[6], UInt<3>(0h6), UInt<3>(0h7)) node _f3_predicted_target_T_10 = mux(f3_redirects[5], UInt<3>(0h5), _f3_predicted_target_T_9) node _f3_predicted_target_T_11 = mux(f3_redirects[4], UInt<3>(0h4), _f3_predicted_target_T_10) node _f3_predicted_target_T_12 = mux(f3_redirects[3], UInt<2>(0h3), _f3_predicted_target_T_11) node _f3_predicted_target_T_13 = mux(f3_redirects[2], UInt<2>(0h2), _f3_predicted_target_T_12) node _f3_predicted_target_T_14 = mux(f3_redirects[1], UInt<1>(0h1), _f3_predicted_target_T_13) node _f3_predicted_target_T_15 = mux(f3_redirects[0], UInt<1>(0h0), _f3_predicted_target_T_14) node _f3_predicted_target_T_16 = mux(_f3_predicted_target_T_8, ras.io.read_addr, f3_targs[_f3_predicted_target_T_15]) node _f3_predicted_target_T_17 = not(f3_fetch_bundle.pc) node _f3_predicted_target_T_18 = or(_f3_predicted_target_T_17, UInt<3>(0h7)) node _f3_predicted_target_T_19 = not(_f3_predicted_target_T_18) node _f3_predicted_target_T_20 = bits(f3_fetch_bundle.pc, 5, 3) node _f3_predicted_target_T_21 = eq(_f3_predicted_target_T_20, UInt<3>(0h7)) node _f3_predicted_target_T_22 = and(UInt<1>(0h1), _f3_predicted_target_T_21) node _f3_predicted_target_T_23 = mux(_f3_predicted_target_T_22, UInt<4>(0h8), UInt<5>(0h10)) node _f3_predicted_target_T_24 = add(_f3_predicted_target_T_19, _f3_predicted_target_T_23) node _f3_predicted_target_T_25 = tail(_f3_predicted_target_T_24, 1) node f3_predicted_target = mux(_f3_predicted_target_T_6, _f3_predicted_target_T_16, _f3_predicted_target_T_25) connect f3_fetch_bundle.next_pc, f3_predicted_target node _f3_predicted_ghist_T = dshr(f3_fetch_bundle.br_mask, f3_fetch_bundle.cfi_idx.bits) node _f3_predicted_ghist_T_1 = bits(_f3_predicted_ghist_T, 0, 0) node f3_predicted_ghist_cfi_idx_fixed = bits(f3_fetch_bundle.cfi_idx.bits, 2, 0) node f3_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f3_predicted_ghist_cfi_idx_fixed) wire f3_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f3_predicted_ghist_not_taken_branches_T = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_1 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f3_predicted_ghist_not_taken_branches_T_2 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f3_predicted_ghist_not_taken_branches_T_3 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f3_predicted_ghist_not_taken_branches_T_4 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h4)) node _f3_predicted_ghist_not_taken_branches_T_5 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h5)) node _f3_predicted_ghist_not_taken_branches_T_6 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h6)) node _f3_predicted_ghist_not_taken_branches_T_7 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h7)) node _f3_predicted_ghist_not_taken_branches_T_8 = or(_f3_predicted_ghist_not_taken_branches_T, _f3_predicted_ghist_not_taken_branches_T_1) node _f3_predicted_ghist_not_taken_branches_T_9 = or(_f3_predicted_ghist_not_taken_branches_T_8, _f3_predicted_ghist_not_taken_branches_T_2) node _f3_predicted_ghist_not_taken_branches_T_10 = or(_f3_predicted_ghist_not_taken_branches_T_9, _f3_predicted_ghist_not_taken_branches_T_3) node _f3_predicted_ghist_not_taken_branches_T_11 = or(_f3_predicted_ghist_not_taken_branches_T_10, _f3_predicted_ghist_not_taken_branches_T_4) node _f3_predicted_ghist_not_taken_branches_T_12 = or(_f3_predicted_ghist_not_taken_branches_T_11, _f3_predicted_ghist_not_taken_branches_T_5) node _f3_predicted_ghist_not_taken_branches_T_13 = or(_f3_predicted_ghist_not_taken_branches_T_12, _f3_predicted_ghist_not_taken_branches_T_6) node _f3_predicted_ghist_not_taken_branches_T_14 = or(_f3_predicted_ghist_not_taken_branches_T_13, _f3_predicted_ghist_not_taken_branches_T_7) node _f3_predicted_ghist_not_taken_branches_T_15 = and(_f3_predicted_ghist_T_1, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_not_taken_branches_T_16 = mux(_f3_predicted_ghist_not_taken_branches_T_15, f3_predicted_ghist_cfi_idx_oh, UInt<8>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_17 = not(_f3_predicted_ghist_not_taken_branches_T_16) node _f3_predicted_ghist_not_taken_branches_T_18 = and(_f3_predicted_ghist_not_taken_branches_T_14, _f3_predicted_ghist_not_taken_branches_T_17) node _f3_predicted_ghist_not_taken_branches_T_19 = not(UInt<8>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_20 = mux(f3_fetch_bundle.cfi_idx.valid, _f3_predicted_ghist_not_taken_branches_T_18, _f3_predicted_ghist_not_taken_branches_T_19) node f3_predicted_ghist_not_taken_branches = and(f3_fetch_bundle.br_mask, _f3_predicted_ghist_not_taken_branches_T_20) node _f3_predicted_ghist_base_T = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_base_T_1 = or(_f3_predicted_ghist_base_T, UInt<1>(0h1)) node _f3_predicted_ghist_base_T_2 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_base_T_3 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_base_T_2, f3_fetch_bundle.ghist.old_history) node f3_predicted_ghist_base = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_base_T_1, _f3_predicted_ghist_base_T_3) node _f3_predicted_ghist_cfi_in_bank_0_T = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_cfi_in_bank_0_T_1 = lt(f3_predicted_ghist_cfi_idx_fixed, UInt<3>(0h4)) node f3_predicted_ghist_cfi_in_bank_0 = and(_f3_predicted_ghist_cfi_in_bank_0_T, _f3_predicted_ghist_cfi_in_bank_0_T_1) node _f3_predicted_ghist_ignore_second_bank_T = bits(f3_fetch_bundle.pc, 5, 3) node _f3_predicted_ghist_ignore_second_bank_T_1 = eq(_f3_predicted_ghist_ignore_second_bank_T, UInt<3>(0h7)) node _f3_predicted_ghist_ignore_second_bank_T_2 = and(UInt<1>(0h1), _f3_predicted_ghist_ignore_second_bank_T_1) node f3_predicted_ghist_ignore_second_bank = or(f3_predicted_ghist_cfi_in_bank_0, _f3_predicted_ghist_ignore_second_bank_T_2) node _f3_predicted_ghist_first_bank_saw_not_taken_T = bits(f3_predicted_ghist_not_taken_branches, 3, 0) node _f3_predicted_ghist_first_bank_saw_not_taken_T_1 = neq(_f3_predicted_ghist_first_bank_saw_not_taken_T, UInt<1>(0h0)) node f3_predicted_ghist_first_bank_saw_not_taken = or(_f3_predicted_ghist_first_bank_saw_not_taken_T_1, f3_fetch_bundle.ghist.current_saw_branch_not_taken) connect f3_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) when f3_predicted_ghist_ignore_second_bank : node _f3_predicted_ghist_new_history_old_history_T = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_1 = or(_f3_predicted_ghist_new_history_old_history_T, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_2 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_3 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_2, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_4 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_1, _f3_predicted_ghist_new_history_old_history_T_3) connect f3_predicted_ghist.old_history, _f3_predicted_ghist_new_history_old_history_T_4 connect f3_predicted_ghist.new_saw_branch_not_taken, f3_predicted_ghist_first_bank_saw_not_taken node _f3_predicted_ghist_new_history_new_saw_branch_taken_T = and(_f3_predicted_ghist_T_1, f3_predicted_ghist_cfi_in_bank_0) connect f3_predicted_ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_new_saw_branch_taken_T else : node _f3_predicted_ghist_new_history_old_history_T_5 = and(_f3_predicted_ghist_T_1, f3_predicted_ghist_cfi_in_bank_0) node _f3_predicted_ghist_new_history_old_history_T_6 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_7 = or(_f3_predicted_ghist_new_history_old_history_T_6, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_8 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_9 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_8, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_10 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_7, _f3_predicted_ghist_new_history_old_history_T_9) node _f3_predicted_ghist_new_history_old_history_T_11 = shl(_f3_predicted_ghist_new_history_old_history_T_10, 1) node _f3_predicted_ghist_new_history_old_history_T_12 = or(_f3_predicted_ghist_new_history_old_history_T_11, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_13 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_14 = or(_f3_predicted_ghist_new_history_old_history_T_13, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_15 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_16 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_15, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_17 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_14, _f3_predicted_ghist_new_history_old_history_T_16) node _f3_predicted_ghist_new_history_old_history_T_18 = shl(_f3_predicted_ghist_new_history_old_history_T_17, 1) node _f3_predicted_ghist_new_history_old_history_T_19 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_20 = or(_f3_predicted_ghist_new_history_old_history_T_19, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_21 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_22 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_21, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_23 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_20, _f3_predicted_ghist_new_history_old_history_T_22) node _f3_predicted_ghist_new_history_old_history_T_24 = mux(f3_predicted_ghist_first_bank_saw_not_taken, _f3_predicted_ghist_new_history_old_history_T_18, _f3_predicted_ghist_new_history_old_history_T_23) node _f3_predicted_ghist_new_history_old_history_T_25 = mux(_f3_predicted_ghist_new_history_old_history_T_5, _f3_predicted_ghist_new_history_old_history_T_12, _f3_predicted_ghist_new_history_old_history_T_24) connect f3_predicted_ghist.old_history, _f3_predicted_ghist_new_history_old_history_T_25 node _f3_predicted_ghist_new_history_new_saw_branch_not_taken_T = bits(f3_predicted_ghist_not_taken_branches, 7, 4) node _f3_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = neq(_f3_predicted_ghist_new_history_new_saw_branch_not_taken_T, UInt<1>(0h0)) connect f3_predicted_ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_1 = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_2 = and(_f3_predicted_ghist_new_history_new_saw_branch_taken_T_1, _f3_predicted_ghist_T_1) node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_3 = eq(f3_predicted_ghist_cfi_in_bank_0, UInt<1>(0h0)) node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_4 = and(_f3_predicted_ghist_new_history_new_saw_branch_taken_T_2, _f3_predicted_ghist_new_history_new_saw_branch_taken_T_3) connect f3_predicted_ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_new_saw_branch_taken_T_4 node _f3_predicted_ghist_new_history_ras_idx_T = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_is_call) node _f3_predicted_ghist_new_history_ras_idx_T_1 = add(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_ras_idx_T_2 = tail(_f3_predicted_ghist_new_history_ras_idx_T_1, 1) node _f3_predicted_ghist_new_history_ras_idx_T_3 = bits(_f3_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f3_predicted_ghist_new_history_ras_idx_T_4 = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_is_ret) node _f3_predicted_ghist_new_history_ras_idx_T_5 = sub(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_ras_idx_T_6 = tail(_f3_predicted_ghist_new_history_ras_idx_T_5, 1) node _f3_predicted_ghist_new_history_ras_idx_T_7 = bits(_f3_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f3_predicted_ghist_new_history_ras_idx_T_8 = mux(_f3_predicted_ghist_new_history_ras_idx_T_4, _f3_predicted_ghist_new_history_ras_idx_T_7, f3_fetch_bundle.ghist.ras_idx) node _f3_predicted_ghist_new_history_ras_idx_T_9 = mux(_f3_predicted_ghist_new_history_ras_idx_T, _f3_predicted_ghist_new_history_ras_idx_T_3, _f3_predicted_ghist_new_history_ras_idx_T_8) connect f3_predicted_ghist.ras_idx, _f3_predicted_ghist_new_history_ras_idx_T_9 connect ras.io.write_valid, UInt<1>(0h0) node _ras_io_write_addr_T = shl(f3_fetch_bundle.cfi_idx.bits, 1) node _ras_io_write_addr_T_1 = add(f3_aligned_pc, _ras_io_write_addr_T) node _ras_io_write_addr_T_2 = tail(_ras_io_write_addr_T_1, 1) node _ras_io_write_addr_T_3 = mux(f3_fetch_bundle.cfi_npc_plus4, UInt<3>(0h4), UInt<2>(0h2)) node _ras_io_write_addr_T_4 = add(_ras_io_write_addr_T_2, _ras_io_write_addr_T_3) node _ras_io_write_addr_T_5 = tail(_ras_io_write_addr_T_4, 1) connect ras.io.write_addr, _ras_io_write_addr_T_5 node _ras_io_write_idx_T = add(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _ras_io_write_idx_T_1 = tail(_ras_io_write_idx_T, 1) node _ras_io_write_idx_T_2 = bits(_ras_io_write_idx_T_1, 4, 0) connect ras.io.write_idx, _ras_io_write_idx_T_2 node _f3_correct_f1_ghist_T = eq(s1_ghist.old_history, f3_predicted_ghist.old_history) node _f3_correct_f1_ghist_T_1 = eq(s1_ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken) node _f3_correct_f1_ghist_T_2 = and(_f3_correct_f1_ghist_T, _f3_correct_f1_ghist_T_1) node _f3_correct_f1_ghist_T_3 = eq(s1_ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken) node _f3_correct_f1_ghist_T_4 = and(_f3_correct_f1_ghist_T_2, _f3_correct_f1_ghist_T_3) node _f3_correct_f1_ghist_T_5 = eq(_f3_correct_f1_ghist_T_4, UInt<1>(0h0)) node f3_correct_f1_ghist = and(_f3_correct_f1_ghist_T_5, UInt<1>(0h1)) node _f3_correct_f2_ghist_T = eq(s2_ghist.old_history, f3_predicted_ghist.old_history) node _f3_correct_f2_ghist_T_1 = eq(s2_ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken) node _f3_correct_f2_ghist_T_2 = and(_f3_correct_f2_ghist_T, _f3_correct_f2_ghist_T_1) node _f3_correct_f2_ghist_T_3 = eq(s2_ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken) node _f3_correct_f2_ghist_T_4 = and(_f3_correct_f2_ghist_T_2, _f3_correct_f2_ghist_T_3) node _f3_correct_f2_ghist_T_5 = eq(_f3_correct_f2_ghist_T_4, UInt<1>(0h0)) node f3_correct_f2_ghist = and(_f3_correct_f2_ghist_T_5, UInt<1>(0h1)) node _T_72 = and(f3.io.deq.valid, f4_ready) when _T_72 : node _T_73 = and(f3_fetch_bundle.cfi_is_call, f3_fetch_bundle.cfi_idx.valid) when _T_73 : connect ras.io.write_valid, UInt<1>(0h1) node _T_74 = or(f3_redirects[0], f3_redirects[1]) node _T_75 = or(_T_74, f3_redirects[2]) node _T_76 = or(_T_75, f3_redirects[3]) node _T_77 = or(_T_76, f3_redirects[4]) node _T_78 = or(_T_77, f3_redirects[5]) node _T_79 = or(_T_78, f3_redirects[6]) node _T_80 = or(_T_79, f3_redirects[7]) when _T_80 : connect f3_prev_is_half, UInt<1>(0h0) node _T_81 = eq(s2_vpc, f3_predicted_target) node _T_82 = and(s2_valid, _T_81) node _T_83 = eq(f3_correct_f2_ghist, UInt<1>(0h0)) node _T_84 = and(_T_82, _T_83) when _T_84 : connect f3.io.enq.bits.ghist.ras_idx, f3_predicted_ghist.ras_idx connect f3.io.enq.bits.ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken connect f3.io.enq.bits.ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken connect f3.io.enq.bits.ghist.current_saw_branch_not_taken, f3_predicted_ghist.current_saw_branch_not_taken connect f3.io.enq.bits.ghist.old_history, f3_predicted_ghist.old_history else : node _T_85 = eq(s2_valid, UInt<1>(0h0)) node _T_86 = and(_T_85, s1_valid) node _T_87 = eq(s1_vpc, f3_predicted_target) node _T_88 = and(_T_86, _T_87) node _T_89 = eq(f3_correct_f1_ghist, UInt<1>(0h0)) node _T_90 = and(_T_88, _T_89) when _T_90 : connect s2_ghist, f3_predicted_ghist else : node _T_91 = neq(s2_vpc, f3_predicted_target) node _T_92 = or(_T_91, f3_correct_f2_ghist) node _T_93 = and(s2_valid, _T_92) node _T_94 = eq(s2_valid, UInt<1>(0h0)) node _T_95 = and(_T_94, s1_valid) node _T_96 = neq(s1_vpc, f3_predicted_target) node _T_97 = or(_T_96, f3_correct_f1_ghist) node _T_98 = and(_T_95, _T_97) node _T_99 = or(_T_93, _T_98) node _T_100 = eq(s2_valid, UInt<1>(0h0)) node _T_101 = eq(s1_valid, UInt<1>(0h0)) node _T_102 = and(_T_100, _T_101) node _T_103 = or(_T_99, _T_102) when _T_103 : connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) node _s0_valid_T_11 = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _s0_valid_T_12 = eq(_s0_valid_T_11, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_12 connect s0_vpc, f3_predicted_target connect s0_is_replay, UInt<1>(0h0) connect s0_ghist, f3_predicted_ghist connect s0_tsrc, UInt<2>(0h2) connect f3_fetch_bundle.fsrc, UInt<2>(0h2) inst f4_btb_corrections of Queue2_BranchPredictionUpdate_1 connect f4_btb_corrections.clock, clock connect f4_btb_corrections.reset, reset node _f4_btb_corrections_io_enq_valid_T = and(f3.io.deq.ready, f3.io.deq.valid) node _f4_btb_corrections_io_enq_valid_T_1 = or(f3_btb_mispredicts[0], f3_btb_mispredicts[1]) node _f4_btb_corrections_io_enq_valid_T_2 = or(_f4_btb_corrections_io_enq_valid_T_1, f3_btb_mispredicts[2]) node _f4_btb_corrections_io_enq_valid_T_3 = or(_f4_btb_corrections_io_enq_valid_T_2, f3_btb_mispredicts[3]) node _f4_btb_corrections_io_enq_valid_T_4 = or(_f4_btb_corrections_io_enq_valid_T_3, f3_btb_mispredicts[4]) node _f4_btb_corrections_io_enq_valid_T_5 = or(_f4_btb_corrections_io_enq_valid_T_4, f3_btb_mispredicts[5]) node _f4_btb_corrections_io_enq_valid_T_6 = or(_f4_btb_corrections_io_enq_valid_T_5, f3_btb_mispredicts[6]) node _f4_btb_corrections_io_enq_valid_T_7 = or(_f4_btb_corrections_io_enq_valid_T_6, f3_btb_mispredicts[7]) node _f4_btb_corrections_io_enq_valid_T_8 = and(_f4_btb_corrections_io_enq_valid_T, _f4_btb_corrections_io_enq_valid_T_7) node _f4_btb_corrections_io_enq_valid_T_9 = and(_f4_btb_corrections_io_enq_valid_T_8, UInt<1>(0h1)) connect f4_btb_corrections.io.enq.valid, _f4_btb_corrections_io_enq_valid_T_9 invalidate f4_btb_corrections.io.enq.bits.meta[0] invalidate f4_btb_corrections.io.enq.bits.meta[1] invalidate f4_btb_corrections.io.enq.bits.target invalidate f4_btb_corrections.io.enq.bits.lhist[0] invalidate f4_btb_corrections.io.enq.bits.lhist[1] invalidate f4_btb_corrections.io.enq.bits.ghist.ras_idx invalidate f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_taken invalidate f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_not_taken invalidate f4_btb_corrections.io.enq.bits.ghist.current_saw_branch_not_taken invalidate f4_btb_corrections.io.enq.bits.ghist.old_history invalidate f4_btb_corrections.io.enq.bits.cfi_is_jalr invalidate f4_btb_corrections.io.enq.bits.cfi_is_jal invalidate f4_btb_corrections.io.enq.bits.cfi_is_br invalidate f4_btb_corrections.io.enq.bits.cfi_mispredicted invalidate f4_btb_corrections.io.enq.bits.cfi_taken invalidate f4_btb_corrections.io.enq.bits.cfi_idx.bits invalidate f4_btb_corrections.io.enq.bits.cfi_idx.valid invalidate f4_btb_corrections.io.enq.bits.br_mask invalidate f4_btb_corrections.io.enq.bits.pc invalidate f4_btb_corrections.io.enq.bits.btb_mispredicts invalidate f4_btb_corrections.io.enq.bits.is_repair_update invalidate f4_btb_corrections.io.enq.bits.is_mispredict_update connect f4_btb_corrections.io.enq.bits.is_mispredict_update, UInt<1>(0h0) connect f4_btb_corrections.io.enq.bits.is_repair_update, UInt<1>(0h0) node f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_lo = cat(f3_btb_mispredicts[1], f3_btb_mispredicts[0]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_hi = cat(f3_btb_mispredicts[3], f3_btb_mispredicts[2]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_lo = cat(f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_hi, f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_lo) node f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_lo = cat(f3_btb_mispredicts[5], f3_btb_mispredicts[4]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_hi = cat(f3_btb_mispredicts[7], f3_btb_mispredicts[6]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_hi = cat(f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_hi, f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_lo) node _f4_btb_corrections_io_enq_bits_btb_mispredicts_T = cat(f4_btb_corrections_io_enq_bits_btb_mispredicts_hi, f4_btb_corrections_io_enq_bits_btb_mispredicts_lo) connect f4_btb_corrections.io.enq.bits.btb_mispredicts, _f4_btb_corrections_io_enq_bits_btb_mispredicts_T connect f4_btb_corrections.io.enq.bits.pc, f3_fetch_bundle.pc connect f4_btb_corrections.io.enq.bits.ghist.ras_idx, f3_fetch_bundle.ghist.ras_idx connect f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_taken, f3_fetch_bundle.ghist.new_saw_branch_taken connect f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_not_taken, f3_fetch_bundle.ghist.new_saw_branch_not_taken connect f4_btb_corrections.io.enq.bits.ghist.current_saw_branch_not_taken, f3_fetch_bundle.ghist.current_saw_branch_not_taken connect f4_btb_corrections.io.enq.bits.ghist.old_history, f3_fetch_bundle.ghist.old_history connect f4_btb_corrections.io.enq.bits.lhist[0], f3_fetch_bundle.lhist[0] connect f4_btb_corrections.io.enq.bits.lhist[1], f3_fetch_bundle.lhist[1] connect f4_btb_corrections.io.enq.bits.meta[0], f3_fetch_bundle.bpd_meta[0] connect f4_btb_corrections.io.enq.bits.meta[1], f3_fetch_bundle.bpd_meta[1] wire f4_clear : UInt<1> connect f4_clear, UInt<1>(0h0) node _T_104 = asUInt(reset) node _T_105 = or(_T_104, f4_clear) inst f4 of Queue1_FetchBundle_1 connect f4.clock, clock connect f4.reset, _T_105 inst fb of FetchBuffer_1 connect fb.clock, clock connect fb.reset, reset inst ftq of FetchTargetQueue_1 connect ftq.clock, clock connect ftq.reset, reset node f4_shadowable_masks_lo_lo = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo = cat(f4_shadowable_masks_lo_hi, f4_shadowable_masks_lo_lo) node f4_shadowable_masks_hi_lo = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi = cat(f4_shadowable_masks_hi_hi, f4_shadowable_masks_hi_lo) node _f4_shadowable_masks_T = cat(f4_shadowable_masks_hi, f4_shadowable_masks_lo) node _f4_shadowable_masks_T_1 = bits(f4.io.deq.bits.sfb_masks[0], 7, 0) node _f4_shadowable_masks_T_2 = not(_f4_shadowable_masks_T_1) node _f4_shadowable_masks_T_3 = or(_f4_shadowable_masks_T, _f4_shadowable_masks_T_2) node f4_shadowable_masks_lo_lo_1 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_1 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_1 = cat(f4_shadowable_masks_lo_hi_1, f4_shadowable_masks_lo_lo_1) node f4_shadowable_masks_hi_lo_1 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_1 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_1 = cat(f4_shadowable_masks_hi_hi_1, f4_shadowable_masks_hi_lo_1) node _f4_shadowable_masks_T_4 = cat(f4_shadowable_masks_hi_1, f4_shadowable_masks_lo_1) node _f4_shadowable_masks_T_5 = bits(f4.io.deq.bits.sfb_masks[1], 7, 0) node _f4_shadowable_masks_T_6 = not(_f4_shadowable_masks_T_5) node _f4_shadowable_masks_T_7 = or(_f4_shadowable_masks_T_4, _f4_shadowable_masks_T_6) node f4_shadowable_masks_lo_lo_2 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_2 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_2 = cat(f4_shadowable_masks_lo_hi_2, f4_shadowable_masks_lo_lo_2) node f4_shadowable_masks_hi_lo_2 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_2 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_2 = cat(f4_shadowable_masks_hi_hi_2, f4_shadowable_masks_hi_lo_2) node _f4_shadowable_masks_T_8 = cat(f4_shadowable_masks_hi_2, f4_shadowable_masks_lo_2) node _f4_shadowable_masks_T_9 = bits(f4.io.deq.bits.sfb_masks[2], 7, 0) node _f4_shadowable_masks_T_10 = not(_f4_shadowable_masks_T_9) node _f4_shadowable_masks_T_11 = or(_f4_shadowable_masks_T_8, _f4_shadowable_masks_T_10) node f4_shadowable_masks_lo_lo_3 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_3 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_3 = cat(f4_shadowable_masks_lo_hi_3, f4_shadowable_masks_lo_lo_3) node f4_shadowable_masks_hi_lo_3 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_3 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_3 = cat(f4_shadowable_masks_hi_hi_3, f4_shadowable_masks_hi_lo_3) node _f4_shadowable_masks_T_12 = cat(f4_shadowable_masks_hi_3, f4_shadowable_masks_lo_3) node _f4_shadowable_masks_T_13 = bits(f4.io.deq.bits.sfb_masks[3], 7, 0) node _f4_shadowable_masks_T_14 = not(_f4_shadowable_masks_T_13) node _f4_shadowable_masks_T_15 = or(_f4_shadowable_masks_T_12, _f4_shadowable_masks_T_14) node f4_shadowable_masks_lo_lo_4 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_4 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_4 = cat(f4_shadowable_masks_lo_hi_4, f4_shadowable_masks_lo_lo_4) node f4_shadowable_masks_hi_lo_4 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_4 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_4 = cat(f4_shadowable_masks_hi_hi_4, f4_shadowable_masks_hi_lo_4) node _f4_shadowable_masks_T_16 = cat(f4_shadowable_masks_hi_4, f4_shadowable_masks_lo_4) node _f4_shadowable_masks_T_17 = bits(f4.io.deq.bits.sfb_masks[4], 7, 0) node _f4_shadowable_masks_T_18 = not(_f4_shadowable_masks_T_17) node _f4_shadowable_masks_T_19 = or(_f4_shadowable_masks_T_16, _f4_shadowable_masks_T_18) node f4_shadowable_masks_lo_lo_5 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_5 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_5 = cat(f4_shadowable_masks_lo_hi_5, f4_shadowable_masks_lo_lo_5) node f4_shadowable_masks_hi_lo_5 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_5 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_5 = cat(f4_shadowable_masks_hi_hi_5, f4_shadowable_masks_hi_lo_5) node _f4_shadowable_masks_T_20 = cat(f4_shadowable_masks_hi_5, f4_shadowable_masks_lo_5) node _f4_shadowable_masks_T_21 = bits(f4.io.deq.bits.sfb_masks[5], 7, 0) node _f4_shadowable_masks_T_22 = not(_f4_shadowable_masks_T_21) node _f4_shadowable_masks_T_23 = or(_f4_shadowable_masks_T_20, _f4_shadowable_masks_T_22) node f4_shadowable_masks_lo_lo_6 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_6 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_6 = cat(f4_shadowable_masks_lo_hi_6, f4_shadowable_masks_lo_lo_6) node f4_shadowable_masks_hi_lo_6 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_6 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_6 = cat(f4_shadowable_masks_hi_hi_6, f4_shadowable_masks_hi_lo_6) node _f4_shadowable_masks_T_24 = cat(f4_shadowable_masks_hi_6, f4_shadowable_masks_lo_6) node _f4_shadowable_masks_T_25 = bits(f4.io.deq.bits.sfb_masks[6], 7, 0) node _f4_shadowable_masks_T_26 = not(_f4_shadowable_masks_T_25) node _f4_shadowable_masks_T_27 = or(_f4_shadowable_masks_T_24, _f4_shadowable_masks_T_26) node f4_shadowable_masks_lo_lo_7 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_7 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_7 = cat(f4_shadowable_masks_lo_hi_7, f4_shadowable_masks_lo_lo_7) node f4_shadowable_masks_hi_lo_7 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_7 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_7 = cat(f4_shadowable_masks_hi_hi_7, f4_shadowable_masks_hi_lo_7) node _f4_shadowable_masks_T_28 = cat(f4_shadowable_masks_hi_7, f4_shadowable_masks_lo_7) node _f4_shadowable_masks_T_29 = bits(f4.io.deq.bits.sfb_masks[7], 7, 0) node _f4_shadowable_masks_T_30 = not(_f4_shadowable_masks_T_29) node _f4_shadowable_masks_T_31 = or(_f4_shadowable_masks_T_28, _f4_shadowable_masks_T_30) wire f4_shadowable_masks : UInt<8>[8] connect f4_shadowable_masks[0], _f4_shadowable_masks_T_3 connect f4_shadowable_masks[1], _f4_shadowable_masks_T_7 connect f4_shadowable_masks[2], _f4_shadowable_masks_T_11 connect f4_shadowable_masks[3], _f4_shadowable_masks_T_15 connect f4_shadowable_masks[4], _f4_shadowable_masks_T_19 connect f4_shadowable_masks[5], _f4_shadowable_masks_T_23 connect f4_shadowable_masks[6], _f4_shadowable_masks_T_27 connect f4_shadowable_masks[7], _f4_shadowable_masks_T_31 node f3_shadowable_masks_lo_lo = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo = cat(f3_shadowable_masks_lo_hi, f3_shadowable_masks_lo_lo) node f3_shadowable_masks_hi_lo = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi = cat(f3_shadowable_masks_hi_hi, f3_shadowable_masks_hi_lo) node _f3_shadowable_masks_T = cat(f3_shadowable_masks_hi, f3_shadowable_masks_lo) node _f3_shadowable_masks_T_1 = mux(f4.io.enq.valid, _f3_shadowable_masks_T, UInt<1>(0h0)) node _f3_shadowable_masks_T_2 = bits(f4.io.deq.bits.sfb_masks[0], 15, 8) node _f3_shadowable_masks_T_3 = not(_f3_shadowable_masks_T_2) node _f3_shadowable_masks_T_4 = or(_f3_shadowable_masks_T_1, _f3_shadowable_masks_T_3) node f3_shadowable_masks_lo_lo_1 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_1 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_1 = cat(f3_shadowable_masks_lo_hi_1, f3_shadowable_masks_lo_lo_1) node f3_shadowable_masks_hi_lo_1 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_1 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_1 = cat(f3_shadowable_masks_hi_hi_1, f3_shadowable_masks_hi_lo_1) node _f3_shadowable_masks_T_5 = cat(f3_shadowable_masks_hi_1, f3_shadowable_masks_lo_1) node _f3_shadowable_masks_T_6 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_5, UInt<1>(0h0)) node _f3_shadowable_masks_T_7 = bits(f4.io.deq.bits.sfb_masks[1], 15, 8) node _f3_shadowable_masks_T_8 = not(_f3_shadowable_masks_T_7) node _f3_shadowable_masks_T_9 = or(_f3_shadowable_masks_T_6, _f3_shadowable_masks_T_8) node f3_shadowable_masks_lo_lo_2 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_2 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_2 = cat(f3_shadowable_masks_lo_hi_2, f3_shadowable_masks_lo_lo_2) node f3_shadowable_masks_hi_lo_2 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_2 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_2 = cat(f3_shadowable_masks_hi_hi_2, f3_shadowable_masks_hi_lo_2) node _f3_shadowable_masks_T_10 = cat(f3_shadowable_masks_hi_2, f3_shadowable_masks_lo_2) node _f3_shadowable_masks_T_11 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_10, UInt<1>(0h0)) node _f3_shadowable_masks_T_12 = bits(f4.io.deq.bits.sfb_masks[2], 15, 8) node _f3_shadowable_masks_T_13 = not(_f3_shadowable_masks_T_12) node _f3_shadowable_masks_T_14 = or(_f3_shadowable_masks_T_11, _f3_shadowable_masks_T_13) node f3_shadowable_masks_lo_lo_3 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_3 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_3 = cat(f3_shadowable_masks_lo_hi_3, f3_shadowable_masks_lo_lo_3) node f3_shadowable_masks_hi_lo_3 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_3 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_3 = cat(f3_shadowable_masks_hi_hi_3, f3_shadowable_masks_hi_lo_3) node _f3_shadowable_masks_T_15 = cat(f3_shadowable_masks_hi_3, f3_shadowable_masks_lo_3) node _f3_shadowable_masks_T_16 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_15, UInt<1>(0h0)) node _f3_shadowable_masks_T_17 = bits(f4.io.deq.bits.sfb_masks[3], 15, 8) node _f3_shadowable_masks_T_18 = not(_f3_shadowable_masks_T_17) node _f3_shadowable_masks_T_19 = or(_f3_shadowable_masks_T_16, _f3_shadowable_masks_T_18) node f3_shadowable_masks_lo_lo_4 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_4 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_4 = cat(f3_shadowable_masks_lo_hi_4, f3_shadowable_masks_lo_lo_4) node f3_shadowable_masks_hi_lo_4 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_4 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_4 = cat(f3_shadowable_masks_hi_hi_4, f3_shadowable_masks_hi_lo_4) node _f3_shadowable_masks_T_20 = cat(f3_shadowable_masks_hi_4, f3_shadowable_masks_lo_4) node _f3_shadowable_masks_T_21 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_20, UInt<1>(0h0)) node _f3_shadowable_masks_T_22 = bits(f4.io.deq.bits.sfb_masks[4], 15, 8) node _f3_shadowable_masks_T_23 = not(_f3_shadowable_masks_T_22) node _f3_shadowable_masks_T_24 = or(_f3_shadowable_masks_T_21, _f3_shadowable_masks_T_23) node f3_shadowable_masks_lo_lo_5 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_5 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_5 = cat(f3_shadowable_masks_lo_hi_5, f3_shadowable_masks_lo_lo_5) node f3_shadowable_masks_hi_lo_5 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_5 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_5 = cat(f3_shadowable_masks_hi_hi_5, f3_shadowable_masks_hi_lo_5) node _f3_shadowable_masks_T_25 = cat(f3_shadowable_masks_hi_5, f3_shadowable_masks_lo_5) node _f3_shadowable_masks_T_26 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_25, UInt<1>(0h0)) node _f3_shadowable_masks_T_27 = bits(f4.io.deq.bits.sfb_masks[5], 15, 8) node _f3_shadowable_masks_T_28 = not(_f3_shadowable_masks_T_27) node _f3_shadowable_masks_T_29 = or(_f3_shadowable_masks_T_26, _f3_shadowable_masks_T_28) node f3_shadowable_masks_lo_lo_6 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_6 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_6 = cat(f3_shadowable_masks_lo_hi_6, f3_shadowable_masks_lo_lo_6) node f3_shadowable_masks_hi_lo_6 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_6 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_6 = cat(f3_shadowable_masks_hi_hi_6, f3_shadowable_masks_hi_lo_6) node _f3_shadowable_masks_T_30 = cat(f3_shadowable_masks_hi_6, f3_shadowable_masks_lo_6) node _f3_shadowable_masks_T_31 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_30, UInt<1>(0h0)) node _f3_shadowable_masks_T_32 = bits(f4.io.deq.bits.sfb_masks[6], 15, 8) node _f3_shadowable_masks_T_33 = not(_f3_shadowable_masks_T_32) node _f3_shadowable_masks_T_34 = or(_f3_shadowable_masks_T_31, _f3_shadowable_masks_T_33) node f3_shadowable_masks_lo_lo_7 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_7 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_7 = cat(f3_shadowable_masks_lo_hi_7, f3_shadowable_masks_lo_lo_7) node f3_shadowable_masks_hi_lo_7 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_7 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_7 = cat(f3_shadowable_masks_hi_hi_7, f3_shadowable_masks_hi_lo_7) node _f3_shadowable_masks_T_35 = cat(f3_shadowable_masks_hi_7, f3_shadowable_masks_lo_7) node _f3_shadowable_masks_T_36 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_35, UInt<1>(0h0)) node _f3_shadowable_masks_T_37 = bits(f4.io.deq.bits.sfb_masks[7], 15, 8) node _f3_shadowable_masks_T_38 = not(_f3_shadowable_masks_T_37) node _f3_shadowable_masks_T_39 = or(_f3_shadowable_masks_T_36, _f3_shadowable_masks_T_38) wire f3_shadowable_masks : UInt<8>[8] connect f3_shadowable_masks[0], _f3_shadowable_masks_T_4 connect f3_shadowable_masks[1], _f3_shadowable_masks_T_9 connect f3_shadowable_masks[2], _f3_shadowable_masks_T_14 connect f3_shadowable_masks[3], _f3_shadowable_masks_T_19 connect f3_shadowable_masks[4], _f3_shadowable_masks_T_24 connect f3_shadowable_masks[5], _f3_shadowable_masks_T_29 connect f3_shadowable_masks[6], _f3_shadowable_masks_T_34 connect f3_shadowable_masks[7], _f3_shadowable_masks_T_39 node _f4_sfbs_T = not(f4_shadowable_masks[0]) node _f4_sfbs_T_1 = eq(_f4_sfbs_T, UInt<1>(0h0)) node _f4_sfbs_T_2 = not(f3_shadowable_masks[0]) node _f4_sfbs_T_3 = eq(_f4_sfbs_T_2, UInt<1>(0h0)) node _f4_sfbs_T_4 = and(_f4_sfbs_T_1, _f4_sfbs_T_3) node _f4_sfbs_T_5 = and(_f4_sfbs_T_4, f4.io.deq.bits.sfbs[0]) node _f4_sfbs_T_6 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<1>(0h0)) node _f4_sfbs_T_7 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_6) node _f4_sfbs_T_8 = eq(_f4_sfbs_T_7, UInt<1>(0h0)) node _f4_sfbs_T_9 = and(_f4_sfbs_T_5, _f4_sfbs_T_8) node _f4_sfbs_T_10 = eq(f4.io.deq.bits.sfb_dests[0], UInt<1>(0h0)) node _f4_sfbs_T_11 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_12 = eq(f4.io.deq.bits.sfb_dests[0], UInt<5>(0h10)) node _f4_sfbs_T_13 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_14 = mux(_f4_sfbs_T_12, _f4_sfbs_T_13, UInt<1>(0h1)) node _f4_sfbs_T_15 = mux(_f4_sfbs_T_10, _f4_sfbs_T_11, _f4_sfbs_T_14) node _f4_sfbs_T_16 = and(_f4_sfbs_T_9, _f4_sfbs_T_15) node _f4_sfbs_T_17 = and(UInt<1>(0h0), _f4_sfbs_T_16) node _f4_sfbs_T_18 = not(f4_shadowable_masks[1]) node _f4_sfbs_T_19 = eq(_f4_sfbs_T_18, UInt<1>(0h0)) node _f4_sfbs_T_20 = not(f3_shadowable_masks[1]) node _f4_sfbs_T_21 = eq(_f4_sfbs_T_20, UInt<1>(0h0)) node _f4_sfbs_T_22 = and(_f4_sfbs_T_19, _f4_sfbs_T_21) node _f4_sfbs_T_23 = and(_f4_sfbs_T_22, f4.io.deq.bits.sfbs[1]) node _f4_sfbs_T_24 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<1>(0h1)) node _f4_sfbs_T_25 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_24) node _f4_sfbs_T_26 = eq(_f4_sfbs_T_25, UInt<1>(0h0)) node _f4_sfbs_T_27 = and(_f4_sfbs_T_23, _f4_sfbs_T_26) node _f4_sfbs_T_28 = eq(f4.io.deq.bits.sfb_dests[1], UInt<1>(0h0)) node _f4_sfbs_T_29 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_30 = eq(f4.io.deq.bits.sfb_dests[1], UInt<5>(0h10)) node _f4_sfbs_T_31 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_32 = mux(_f4_sfbs_T_30, _f4_sfbs_T_31, UInt<1>(0h1)) node _f4_sfbs_T_33 = mux(_f4_sfbs_T_28, _f4_sfbs_T_29, _f4_sfbs_T_32) node _f4_sfbs_T_34 = and(_f4_sfbs_T_27, _f4_sfbs_T_33) node _f4_sfbs_T_35 = and(UInt<1>(0h0), _f4_sfbs_T_34) node _f4_sfbs_T_36 = not(f4_shadowable_masks[2]) node _f4_sfbs_T_37 = eq(_f4_sfbs_T_36, UInt<1>(0h0)) node _f4_sfbs_T_38 = not(f3_shadowable_masks[2]) node _f4_sfbs_T_39 = eq(_f4_sfbs_T_38, UInt<1>(0h0)) node _f4_sfbs_T_40 = and(_f4_sfbs_T_37, _f4_sfbs_T_39) node _f4_sfbs_T_41 = and(_f4_sfbs_T_40, f4.io.deq.bits.sfbs[2]) node _f4_sfbs_T_42 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<2>(0h2)) node _f4_sfbs_T_43 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_42) node _f4_sfbs_T_44 = eq(_f4_sfbs_T_43, UInt<1>(0h0)) node _f4_sfbs_T_45 = and(_f4_sfbs_T_41, _f4_sfbs_T_44) node _f4_sfbs_T_46 = eq(f4.io.deq.bits.sfb_dests[2], UInt<1>(0h0)) node _f4_sfbs_T_47 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_48 = eq(f4.io.deq.bits.sfb_dests[2], UInt<5>(0h10)) node _f4_sfbs_T_49 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_50 = mux(_f4_sfbs_T_48, _f4_sfbs_T_49, UInt<1>(0h1)) node _f4_sfbs_T_51 = mux(_f4_sfbs_T_46, _f4_sfbs_T_47, _f4_sfbs_T_50) node _f4_sfbs_T_52 = and(_f4_sfbs_T_45, _f4_sfbs_T_51) node _f4_sfbs_T_53 = and(UInt<1>(0h0), _f4_sfbs_T_52) node _f4_sfbs_T_54 = not(f4_shadowable_masks[3]) node _f4_sfbs_T_55 = eq(_f4_sfbs_T_54, UInt<1>(0h0)) node _f4_sfbs_T_56 = not(f3_shadowable_masks[3]) node _f4_sfbs_T_57 = eq(_f4_sfbs_T_56, UInt<1>(0h0)) node _f4_sfbs_T_58 = and(_f4_sfbs_T_55, _f4_sfbs_T_57) node _f4_sfbs_T_59 = and(_f4_sfbs_T_58, f4.io.deq.bits.sfbs[3]) node _f4_sfbs_T_60 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<2>(0h3)) node _f4_sfbs_T_61 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_60) node _f4_sfbs_T_62 = eq(_f4_sfbs_T_61, UInt<1>(0h0)) node _f4_sfbs_T_63 = and(_f4_sfbs_T_59, _f4_sfbs_T_62) node _f4_sfbs_T_64 = eq(f4.io.deq.bits.sfb_dests[3], UInt<1>(0h0)) node _f4_sfbs_T_65 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_66 = eq(f4.io.deq.bits.sfb_dests[3], UInt<5>(0h10)) node _f4_sfbs_T_67 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_68 = mux(_f4_sfbs_T_66, _f4_sfbs_T_67, UInt<1>(0h1)) node _f4_sfbs_T_69 = mux(_f4_sfbs_T_64, _f4_sfbs_T_65, _f4_sfbs_T_68) node _f4_sfbs_T_70 = and(_f4_sfbs_T_63, _f4_sfbs_T_69) node _f4_sfbs_T_71 = and(UInt<1>(0h0), _f4_sfbs_T_70) node _f4_sfbs_T_72 = not(f4_shadowable_masks[4]) node _f4_sfbs_T_73 = eq(_f4_sfbs_T_72, UInt<1>(0h0)) node _f4_sfbs_T_74 = not(f3_shadowable_masks[4]) node _f4_sfbs_T_75 = eq(_f4_sfbs_T_74, UInt<1>(0h0)) node _f4_sfbs_T_76 = and(_f4_sfbs_T_73, _f4_sfbs_T_75) node _f4_sfbs_T_77 = and(_f4_sfbs_T_76, f4.io.deq.bits.sfbs[4]) node _f4_sfbs_T_78 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h4)) node _f4_sfbs_T_79 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_78) node _f4_sfbs_T_80 = eq(_f4_sfbs_T_79, UInt<1>(0h0)) node _f4_sfbs_T_81 = and(_f4_sfbs_T_77, _f4_sfbs_T_80) node _f4_sfbs_T_82 = eq(f4.io.deq.bits.sfb_dests[4], UInt<1>(0h0)) node _f4_sfbs_T_83 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_84 = eq(f4.io.deq.bits.sfb_dests[4], UInt<5>(0h10)) node _f4_sfbs_T_85 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_86 = mux(_f4_sfbs_T_84, _f4_sfbs_T_85, UInt<1>(0h1)) node _f4_sfbs_T_87 = mux(_f4_sfbs_T_82, _f4_sfbs_T_83, _f4_sfbs_T_86) node _f4_sfbs_T_88 = and(_f4_sfbs_T_81, _f4_sfbs_T_87) node _f4_sfbs_T_89 = and(UInt<1>(0h0), _f4_sfbs_T_88) node _f4_sfbs_T_90 = not(f4_shadowable_masks[5]) node _f4_sfbs_T_91 = eq(_f4_sfbs_T_90, UInt<1>(0h0)) node _f4_sfbs_T_92 = not(f3_shadowable_masks[5]) node _f4_sfbs_T_93 = eq(_f4_sfbs_T_92, UInt<1>(0h0)) node _f4_sfbs_T_94 = and(_f4_sfbs_T_91, _f4_sfbs_T_93) node _f4_sfbs_T_95 = and(_f4_sfbs_T_94, f4.io.deq.bits.sfbs[5]) node _f4_sfbs_T_96 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h5)) node _f4_sfbs_T_97 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_96) node _f4_sfbs_T_98 = eq(_f4_sfbs_T_97, UInt<1>(0h0)) node _f4_sfbs_T_99 = and(_f4_sfbs_T_95, _f4_sfbs_T_98) node _f4_sfbs_T_100 = eq(f4.io.deq.bits.sfb_dests[5], UInt<1>(0h0)) node _f4_sfbs_T_101 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_102 = eq(f4.io.deq.bits.sfb_dests[5], UInt<5>(0h10)) node _f4_sfbs_T_103 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_104 = mux(_f4_sfbs_T_102, _f4_sfbs_T_103, UInt<1>(0h1)) node _f4_sfbs_T_105 = mux(_f4_sfbs_T_100, _f4_sfbs_T_101, _f4_sfbs_T_104) node _f4_sfbs_T_106 = and(_f4_sfbs_T_99, _f4_sfbs_T_105) node _f4_sfbs_T_107 = and(UInt<1>(0h0), _f4_sfbs_T_106) node _f4_sfbs_T_108 = not(f4_shadowable_masks[6]) node _f4_sfbs_T_109 = eq(_f4_sfbs_T_108, UInt<1>(0h0)) node _f4_sfbs_T_110 = not(f3_shadowable_masks[6]) node _f4_sfbs_T_111 = eq(_f4_sfbs_T_110, UInt<1>(0h0)) node _f4_sfbs_T_112 = and(_f4_sfbs_T_109, _f4_sfbs_T_111) node _f4_sfbs_T_113 = and(_f4_sfbs_T_112, f4.io.deq.bits.sfbs[6]) node _f4_sfbs_T_114 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h6)) node _f4_sfbs_T_115 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_114) node _f4_sfbs_T_116 = eq(_f4_sfbs_T_115, UInt<1>(0h0)) node _f4_sfbs_T_117 = and(_f4_sfbs_T_113, _f4_sfbs_T_116) node _f4_sfbs_T_118 = eq(f4.io.deq.bits.sfb_dests[6], UInt<1>(0h0)) node _f4_sfbs_T_119 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_120 = eq(f4.io.deq.bits.sfb_dests[6], UInt<5>(0h10)) node _f4_sfbs_T_121 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_122 = mux(_f4_sfbs_T_120, _f4_sfbs_T_121, UInt<1>(0h1)) node _f4_sfbs_T_123 = mux(_f4_sfbs_T_118, _f4_sfbs_T_119, _f4_sfbs_T_122) node _f4_sfbs_T_124 = and(_f4_sfbs_T_117, _f4_sfbs_T_123) node _f4_sfbs_T_125 = and(UInt<1>(0h0), _f4_sfbs_T_124) node _f4_sfbs_T_126 = not(f4_shadowable_masks[7]) node _f4_sfbs_T_127 = eq(_f4_sfbs_T_126, UInt<1>(0h0)) node _f4_sfbs_T_128 = not(f3_shadowable_masks[7]) node _f4_sfbs_T_129 = eq(_f4_sfbs_T_128, UInt<1>(0h0)) node _f4_sfbs_T_130 = and(_f4_sfbs_T_127, _f4_sfbs_T_129) node _f4_sfbs_T_131 = and(_f4_sfbs_T_130, f4.io.deq.bits.sfbs[7]) node _f4_sfbs_T_132 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h7)) node _f4_sfbs_T_133 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_132) node _f4_sfbs_T_134 = eq(_f4_sfbs_T_133, UInt<1>(0h0)) node _f4_sfbs_T_135 = and(_f4_sfbs_T_131, _f4_sfbs_T_134) node _f4_sfbs_T_136 = eq(f4.io.deq.bits.sfb_dests[7], UInt<1>(0h0)) node _f4_sfbs_T_137 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_138 = eq(f4.io.deq.bits.sfb_dests[7], UInt<5>(0h10)) node _f4_sfbs_T_139 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_140 = mux(_f4_sfbs_T_138, _f4_sfbs_T_139, UInt<1>(0h1)) node _f4_sfbs_T_141 = mux(_f4_sfbs_T_136, _f4_sfbs_T_137, _f4_sfbs_T_140) node _f4_sfbs_T_142 = and(_f4_sfbs_T_135, _f4_sfbs_T_141) node _f4_sfbs_T_143 = and(UInt<1>(0h0), _f4_sfbs_T_142) wire f4_sfbs : UInt<1>[8] connect f4_sfbs[0], _f4_sfbs_T_17 connect f4_sfbs[1], _f4_sfbs_T_35 connect f4_sfbs[2], _f4_sfbs_T_53 connect f4_sfbs[3], _f4_sfbs_T_71 connect f4_sfbs[4], _f4_sfbs_T_89 connect f4_sfbs[5], _f4_sfbs_T_107 connect f4_sfbs[6], _f4_sfbs_T_125 connect f4_sfbs[7], _f4_sfbs_T_143 node _f4_sfb_valid_T = or(f4_sfbs[0], f4_sfbs[1]) node _f4_sfb_valid_T_1 = or(_f4_sfb_valid_T, f4_sfbs[2]) node _f4_sfb_valid_T_2 = or(_f4_sfb_valid_T_1, f4_sfbs[3]) node _f4_sfb_valid_T_3 = or(_f4_sfb_valid_T_2, f4_sfbs[4]) node _f4_sfb_valid_T_4 = or(_f4_sfb_valid_T_3, f4_sfbs[5]) node _f4_sfb_valid_T_5 = or(_f4_sfb_valid_T_4, f4_sfbs[6]) node _f4_sfb_valid_T_6 = or(_f4_sfb_valid_T_5, f4_sfbs[7]) node f4_sfb_valid = and(_f4_sfb_valid_T_6, f4.io.deq.valid) node _f4_sfb_idx_T = mux(f4_sfbs[6], UInt<3>(0h6), UInt<3>(0h7)) node _f4_sfb_idx_T_1 = mux(f4_sfbs[5], UInt<3>(0h5), _f4_sfb_idx_T) node _f4_sfb_idx_T_2 = mux(f4_sfbs[4], UInt<3>(0h4), _f4_sfb_idx_T_1) node _f4_sfb_idx_T_3 = mux(f4_sfbs[3], UInt<2>(0h3), _f4_sfb_idx_T_2) node _f4_sfb_idx_T_4 = mux(f4_sfbs[2], UInt<2>(0h2), _f4_sfb_idx_T_3) node _f4_sfb_idx_T_5 = mux(f4_sfbs[1], UInt<1>(0h1), _f4_sfb_idx_T_4) node f4_sfb_idx = mux(f4_sfbs[0], UInt<1>(0h0), _f4_sfb_idx_T_5) node _f4_delay_T = or(f4.io.deq.bits.sfbs[0], f4.io.deq.bits.sfbs[1]) node _f4_delay_T_1 = or(_f4_delay_T, f4.io.deq.bits.sfbs[2]) node _f4_delay_T_2 = or(_f4_delay_T_1, f4.io.deq.bits.sfbs[3]) node _f4_delay_T_3 = or(_f4_delay_T_2, f4.io.deq.bits.sfbs[4]) node _f4_delay_T_4 = or(_f4_delay_T_3, f4.io.deq.bits.sfbs[5]) node _f4_delay_T_5 = or(_f4_delay_T_4, f4.io.deq.bits.sfbs[6]) node _f4_delay_T_6 = or(_f4_delay_T_5, f4.io.deq.bits.sfbs[7]) node _f4_delay_T_7 = eq(f4.io.deq.bits.cfi_idx.valid, UInt<1>(0h0)) node _f4_delay_T_8 = and(_f4_delay_T_6, _f4_delay_T_7) node _f4_delay_T_9 = eq(f4.io.enq.valid, UInt<1>(0h0)) node _f4_delay_T_10 = and(_f4_delay_T_8, _f4_delay_T_9) node _f4_delay_T_11 = eq(f4.io.deq.bits.xcpt_pf_if, UInt<1>(0h0)) node _f4_delay_T_12 = and(_f4_delay_T_10, _f4_delay_T_11) node _f4_delay_T_13 = eq(f4.io.deq.bits.xcpt_ae_if, UInt<1>(0h0)) node f4_delay = and(_f4_delay_T_12, _f4_delay_T_13) when f4_sfb_valid : node _T_106 = bits(f4.io.deq.bits.sfb_masks[f4_sfb_idx], 15, 8) node _T_107 = bits(_T_106, 0, 0) node _T_108 = bits(_T_106, 1, 1) node _T_109 = bits(_T_106, 2, 2) node _T_110 = bits(_T_106, 3, 3) node _T_111 = bits(_T_106, 4, 4) node _T_112 = bits(_T_106, 5, 5) node _T_113 = bits(_T_106, 6, 6) node _T_114 = bits(_T_106, 7, 7) connect f3_shadowed_mask[0], _T_107 connect f3_shadowed_mask[1], _T_108 connect f3_shadowed_mask[2], _T_109 connect f3_shadowed_mask[3], _T_110 connect f3_shadowed_mask[4], _T_111 connect f3_shadowed_mask[5], _T_112 connect f3_shadowed_mask[6], _T_113 connect f3_shadowed_mask[7], _T_114 else : wire _WIRE : UInt<1>[8] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect f3_shadowed_mask, _WIRE connect f4_ready, f4.io.enq.ready node _f4_io_enq_valid_T = eq(f3_clear, UInt<1>(0h0)) node _f4_io_enq_valid_T_1 = and(f3.io.deq.valid, _f4_io_enq_valid_T) connect f4.io.enq.valid, _f4_io_enq_valid_T_1 connect f4.io.enq.bits.tsrc, f3_fetch_bundle.tsrc connect f4.io.enq.bits.fsrc, f3_fetch_bundle.fsrc connect f4.io.enq.bits.bpd_meta[0], f3_fetch_bundle.bpd_meta[0] connect f4.io.enq.bits.bpd_meta[1], f3_fetch_bundle.bpd_meta[1] connect f4.io.enq.bits.end_half.bits, f3_fetch_bundle.end_half.bits connect f4.io.enq.bits.end_half.valid, f3_fetch_bundle.end_half.valid connect f4.io.enq.bits.bp_xcpt_if_oh[0], f3_fetch_bundle.bp_xcpt_if_oh[0] connect f4.io.enq.bits.bp_xcpt_if_oh[1], f3_fetch_bundle.bp_xcpt_if_oh[1] connect f4.io.enq.bits.bp_xcpt_if_oh[2], f3_fetch_bundle.bp_xcpt_if_oh[2] connect f4.io.enq.bits.bp_xcpt_if_oh[3], f3_fetch_bundle.bp_xcpt_if_oh[3] connect f4.io.enq.bits.bp_xcpt_if_oh[4], f3_fetch_bundle.bp_xcpt_if_oh[4] connect f4.io.enq.bits.bp_xcpt_if_oh[5], f3_fetch_bundle.bp_xcpt_if_oh[5] connect f4.io.enq.bits.bp_xcpt_if_oh[6], f3_fetch_bundle.bp_xcpt_if_oh[6] connect f4.io.enq.bits.bp_xcpt_if_oh[7], f3_fetch_bundle.bp_xcpt_if_oh[7] connect f4.io.enq.bits.bp_debug_if_oh[0], f3_fetch_bundle.bp_debug_if_oh[0] connect f4.io.enq.bits.bp_debug_if_oh[1], f3_fetch_bundle.bp_debug_if_oh[1] connect f4.io.enq.bits.bp_debug_if_oh[2], f3_fetch_bundle.bp_debug_if_oh[2] connect f4.io.enq.bits.bp_debug_if_oh[3], f3_fetch_bundle.bp_debug_if_oh[3] connect f4.io.enq.bits.bp_debug_if_oh[4], f3_fetch_bundle.bp_debug_if_oh[4] connect f4.io.enq.bits.bp_debug_if_oh[5], f3_fetch_bundle.bp_debug_if_oh[5] connect f4.io.enq.bits.bp_debug_if_oh[6], f3_fetch_bundle.bp_debug_if_oh[6] connect f4.io.enq.bits.bp_debug_if_oh[7], f3_fetch_bundle.bp_debug_if_oh[7] connect f4.io.enq.bits.xcpt_ae_if, f3_fetch_bundle.xcpt_ae_if connect f4.io.enq.bits.xcpt_pf_if, f3_fetch_bundle.xcpt_pf_if connect f4.io.enq.bits.lhist[0], f3_fetch_bundle.lhist[0] connect f4.io.enq.bits.lhist[1], f3_fetch_bundle.lhist[1] connect f4.io.enq.bits.ghist.ras_idx, f3_fetch_bundle.ghist.ras_idx connect f4.io.enq.bits.ghist.new_saw_branch_taken, f3_fetch_bundle.ghist.new_saw_branch_taken connect f4.io.enq.bits.ghist.new_saw_branch_not_taken, f3_fetch_bundle.ghist.new_saw_branch_not_taken connect f4.io.enq.bits.ghist.current_saw_branch_not_taken, f3_fetch_bundle.ghist.current_saw_branch_not_taken connect f4.io.enq.bits.ghist.old_history, f3_fetch_bundle.ghist.old_history connect f4.io.enq.bits.br_mask, f3_fetch_bundle.br_mask connect f4.io.enq.bits.mask, f3_fetch_bundle.mask connect f4.io.enq.bits.ftq_idx, f3_fetch_bundle.ftq_idx connect f4.io.enq.bits.ras_top, f3_fetch_bundle.ras_top connect f4.io.enq.bits.cfi_npc_plus4, f3_fetch_bundle.cfi_npc_plus4 connect f4.io.enq.bits.cfi_is_ret, f3_fetch_bundle.cfi_is_ret connect f4.io.enq.bits.cfi_is_call, f3_fetch_bundle.cfi_is_call connect f4.io.enq.bits.cfi_type, f3_fetch_bundle.cfi_type connect f4.io.enq.bits.cfi_idx.bits, f3_fetch_bundle.cfi_idx.bits connect f4.io.enq.bits.cfi_idx.valid, f3_fetch_bundle.cfi_idx.valid connect f4.io.enq.bits.shadowed_mask[0], f3_fetch_bundle.shadowed_mask[0] connect f4.io.enq.bits.shadowed_mask[1], f3_fetch_bundle.shadowed_mask[1] connect f4.io.enq.bits.shadowed_mask[2], f3_fetch_bundle.shadowed_mask[2] connect f4.io.enq.bits.shadowed_mask[3], f3_fetch_bundle.shadowed_mask[3] connect f4.io.enq.bits.shadowed_mask[4], f3_fetch_bundle.shadowed_mask[4] connect f4.io.enq.bits.shadowed_mask[5], f3_fetch_bundle.shadowed_mask[5] connect f4.io.enq.bits.shadowed_mask[6], f3_fetch_bundle.shadowed_mask[6] connect f4.io.enq.bits.shadowed_mask[7], f3_fetch_bundle.shadowed_mask[7] connect f4.io.enq.bits.shadowable_mask[0], f3_fetch_bundle.shadowable_mask[0] connect f4.io.enq.bits.shadowable_mask[1], f3_fetch_bundle.shadowable_mask[1] connect f4.io.enq.bits.shadowable_mask[2], f3_fetch_bundle.shadowable_mask[2] connect f4.io.enq.bits.shadowable_mask[3], f3_fetch_bundle.shadowable_mask[3] connect f4.io.enq.bits.shadowable_mask[4], f3_fetch_bundle.shadowable_mask[4] connect f4.io.enq.bits.shadowable_mask[5], f3_fetch_bundle.shadowable_mask[5] connect f4.io.enq.bits.shadowable_mask[6], f3_fetch_bundle.shadowable_mask[6] connect f4.io.enq.bits.shadowable_mask[7], f3_fetch_bundle.shadowable_mask[7] connect f4.io.enq.bits.sfb_dests[0], f3_fetch_bundle.sfb_dests[0] connect f4.io.enq.bits.sfb_dests[1], f3_fetch_bundle.sfb_dests[1] connect f4.io.enq.bits.sfb_dests[2], f3_fetch_bundle.sfb_dests[2] connect f4.io.enq.bits.sfb_dests[3], f3_fetch_bundle.sfb_dests[3] connect f4.io.enq.bits.sfb_dests[4], f3_fetch_bundle.sfb_dests[4] connect f4.io.enq.bits.sfb_dests[5], f3_fetch_bundle.sfb_dests[5] connect f4.io.enq.bits.sfb_dests[6], f3_fetch_bundle.sfb_dests[6] connect f4.io.enq.bits.sfb_dests[7], f3_fetch_bundle.sfb_dests[7] connect f4.io.enq.bits.sfb_masks[0], f3_fetch_bundle.sfb_masks[0] connect f4.io.enq.bits.sfb_masks[1], f3_fetch_bundle.sfb_masks[1] connect f4.io.enq.bits.sfb_masks[2], f3_fetch_bundle.sfb_masks[2] connect f4.io.enq.bits.sfb_masks[3], f3_fetch_bundle.sfb_masks[3] connect f4.io.enq.bits.sfb_masks[4], f3_fetch_bundle.sfb_masks[4] connect f4.io.enq.bits.sfb_masks[5], f3_fetch_bundle.sfb_masks[5] connect f4.io.enq.bits.sfb_masks[6], f3_fetch_bundle.sfb_masks[6] connect f4.io.enq.bits.sfb_masks[7], f3_fetch_bundle.sfb_masks[7] connect f4.io.enq.bits.sfbs[0], f3_fetch_bundle.sfbs[0] connect f4.io.enq.bits.sfbs[1], f3_fetch_bundle.sfbs[1] connect f4.io.enq.bits.sfbs[2], f3_fetch_bundle.sfbs[2] connect f4.io.enq.bits.sfbs[3], f3_fetch_bundle.sfbs[3] connect f4.io.enq.bits.sfbs[4], f3_fetch_bundle.sfbs[4] connect f4.io.enq.bits.sfbs[5], f3_fetch_bundle.sfbs[5] connect f4.io.enq.bits.sfbs[6], f3_fetch_bundle.sfbs[6] connect f4.io.enq.bits.sfbs[7], f3_fetch_bundle.sfbs[7] connect f4.io.enq.bits.exp_insts[0], f3_fetch_bundle.exp_insts[0] connect f4.io.enq.bits.exp_insts[1], f3_fetch_bundle.exp_insts[1] connect f4.io.enq.bits.exp_insts[2], f3_fetch_bundle.exp_insts[2] connect f4.io.enq.bits.exp_insts[3], f3_fetch_bundle.exp_insts[3] connect f4.io.enq.bits.exp_insts[4], f3_fetch_bundle.exp_insts[4] connect f4.io.enq.bits.exp_insts[5], f3_fetch_bundle.exp_insts[5] connect f4.io.enq.bits.exp_insts[6], f3_fetch_bundle.exp_insts[6] connect f4.io.enq.bits.exp_insts[7], f3_fetch_bundle.exp_insts[7] connect f4.io.enq.bits.insts[0], f3_fetch_bundle.insts[0] connect f4.io.enq.bits.insts[1], f3_fetch_bundle.insts[1] connect f4.io.enq.bits.insts[2], f3_fetch_bundle.insts[2] connect f4.io.enq.bits.insts[3], f3_fetch_bundle.insts[3] connect f4.io.enq.bits.insts[4], f3_fetch_bundle.insts[4] connect f4.io.enq.bits.insts[5], f3_fetch_bundle.insts[5] connect f4.io.enq.bits.insts[6], f3_fetch_bundle.insts[6] connect f4.io.enq.bits.insts[7], f3_fetch_bundle.insts[7] connect f4.io.enq.bits.edge_inst[0], f3_fetch_bundle.edge_inst[0] connect f4.io.enq.bits.edge_inst[1], f3_fetch_bundle.edge_inst[1] connect f4.io.enq.bits.next_pc, f3_fetch_bundle.next_pc connect f4.io.enq.bits.pc, f3_fetch_bundle.pc node _f4_io_deq_ready_T = and(fb.io.enq.ready, ftq.io.enq.ready) node _f4_io_deq_ready_T_1 = eq(f4_delay, UInt<1>(0h0)) node _f4_io_deq_ready_T_2 = and(_f4_io_deq_ready_T, _f4_io_deq_ready_T_1) connect f4.io.deq.ready, _f4_io_deq_ready_T_2 node _fb_io_enq_valid_T = and(f4.io.deq.valid, ftq.io.enq.ready) node _fb_io_enq_valid_T_1 = eq(f4_delay, UInt<1>(0h0)) node _fb_io_enq_valid_T_2 = and(_fb_io_enq_valid_T, _fb_io_enq_valid_T_1) connect fb.io.enq.valid, _fb_io_enq_valid_T_2 connect fb.io.enq.bits.tsrc, f4.io.deq.bits.tsrc connect fb.io.enq.bits.fsrc, f4.io.deq.bits.fsrc connect fb.io.enq.bits.bpd_meta[0], f4.io.deq.bits.bpd_meta[0] connect fb.io.enq.bits.bpd_meta[1], f4.io.deq.bits.bpd_meta[1] connect fb.io.enq.bits.end_half.bits, f4.io.deq.bits.end_half.bits connect fb.io.enq.bits.end_half.valid, f4.io.deq.bits.end_half.valid connect fb.io.enq.bits.bp_xcpt_if_oh[0], f4.io.deq.bits.bp_xcpt_if_oh[0] connect fb.io.enq.bits.bp_xcpt_if_oh[1], f4.io.deq.bits.bp_xcpt_if_oh[1] connect fb.io.enq.bits.bp_xcpt_if_oh[2], f4.io.deq.bits.bp_xcpt_if_oh[2] connect fb.io.enq.bits.bp_xcpt_if_oh[3], f4.io.deq.bits.bp_xcpt_if_oh[3] connect fb.io.enq.bits.bp_xcpt_if_oh[4], f4.io.deq.bits.bp_xcpt_if_oh[4] connect fb.io.enq.bits.bp_xcpt_if_oh[5], f4.io.deq.bits.bp_xcpt_if_oh[5] connect fb.io.enq.bits.bp_xcpt_if_oh[6], f4.io.deq.bits.bp_xcpt_if_oh[6] connect fb.io.enq.bits.bp_xcpt_if_oh[7], f4.io.deq.bits.bp_xcpt_if_oh[7] connect fb.io.enq.bits.bp_debug_if_oh[0], f4.io.deq.bits.bp_debug_if_oh[0] connect fb.io.enq.bits.bp_debug_if_oh[1], f4.io.deq.bits.bp_debug_if_oh[1] connect fb.io.enq.bits.bp_debug_if_oh[2], f4.io.deq.bits.bp_debug_if_oh[2] connect fb.io.enq.bits.bp_debug_if_oh[3], f4.io.deq.bits.bp_debug_if_oh[3] connect fb.io.enq.bits.bp_debug_if_oh[4], f4.io.deq.bits.bp_debug_if_oh[4] connect fb.io.enq.bits.bp_debug_if_oh[5], f4.io.deq.bits.bp_debug_if_oh[5] connect fb.io.enq.bits.bp_debug_if_oh[6], f4.io.deq.bits.bp_debug_if_oh[6] connect fb.io.enq.bits.bp_debug_if_oh[7], f4.io.deq.bits.bp_debug_if_oh[7] connect fb.io.enq.bits.xcpt_ae_if, f4.io.deq.bits.xcpt_ae_if connect fb.io.enq.bits.xcpt_pf_if, f4.io.deq.bits.xcpt_pf_if connect fb.io.enq.bits.lhist[0], f4.io.deq.bits.lhist[0] connect fb.io.enq.bits.lhist[1], f4.io.deq.bits.lhist[1] connect fb.io.enq.bits.ghist.ras_idx, f4.io.deq.bits.ghist.ras_idx connect fb.io.enq.bits.ghist.new_saw_branch_taken, f4.io.deq.bits.ghist.new_saw_branch_taken connect fb.io.enq.bits.ghist.new_saw_branch_not_taken, f4.io.deq.bits.ghist.new_saw_branch_not_taken connect fb.io.enq.bits.ghist.current_saw_branch_not_taken, f4.io.deq.bits.ghist.current_saw_branch_not_taken connect fb.io.enq.bits.ghist.old_history, f4.io.deq.bits.ghist.old_history connect fb.io.enq.bits.br_mask, f4.io.deq.bits.br_mask connect fb.io.enq.bits.mask, f4.io.deq.bits.mask connect fb.io.enq.bits.ftq_idx, f4.io.deq.bits.ftq_idx connect fb.io.enq.bits.ras_top, f4.io.deq.bits.ras_top connect fb.io.enq.bits.cfi_npc_plus4, f4.io.deq.bits.cfi_npc_plus4 connect fb.io.enq.bits.cfi_is_ret, f4.io.deq.bits.cfi_is_ret connect fb.io.enq.bits.cfi_is_call, f4.io.deq.bits.cfi_is_call connect fb.io.enq.bits.cfi_type, f4.io.deq.bits.cfi_type connect fb.io.enq.bits.cfi_idx.bits, f4.io.deq.bits.cfi_idx.bits connect fb.io.enq.bits.cfi_idx.valid, f4.io.deq.bits.cfi_idx.valid connect fb.io.enq.bits.shadowed_mask[0], f4.io.deq.bits.shadowed_mask[0] connect fb.io.enq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[1] connect fb.io.enq.bits.shadowed_mask[2], f4.io.deq.bits.shadowed_mask[2] connect fb.io.enq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[3] connect fb.io.enq.bits.shadowed_mask[4], f4.io.deq.bits.shadowed_mask[4] connect fb.io.enq.bits.shadowed_mask[5], f4.io.deq.bits.shadowed_mask[5] connect fb.io.enq.bits.shadowed_mask[6], f4.io.deq.bits.shadowed_mask[6] connect fb.io.enq.bits.shadowed_mask[7], f4.io.deq.bits.shadowed_mask[7] connect fb.io.enq.bits.shadowable_mask[0], f4.io.deq.bits.shadowable_mask[0] connect fb.io.enq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[1] connect fb.io.enq.bits.shadowable_mask[2], f4.io.deq.bits.shadowable_mask[2] connect fb.io.enq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[3] connect fb.io.enq.bits.shadowable_mask[4], f4.io.deq.bits.shadowable_mask[4] connect fb.io.enq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[5] connect fb.io.enq.bits.shadowable_mask[6], f4.io.deq.bits.shadowable_mask[6] connect fb.io.enq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[7] connect fb.io.enq.bits.sfb_dests[0], f4.io.deq.bits.sfb_dests[0] connect fb.io.enq.bits.sfb_dests[1], f4.io.deq.bits.sfb_dests[1] connect fb.io.enq.bits.sfb_dests[2], f4.io.deq.bits.sfb_dests[2] connect fb.io.enq.bits.sfb_dests[3], f4.io.deq.bits.sfb_dests[3] connect fb.io.enq.bits.sfb_dests[4], f4.io.deq.bits.sfb_dests[4] connect fb.io.enq.bits.sfb_dests[5], f4.io.deq.bits.sfb_dests[5] connect fb.io.enq.bits.sfb_dests[6], f4.io.deq.bits.sfb_dests[6] connect fb.io.enq.bits.sfb_dests[7], f4.io.deq.bits.sfb_dests[7] connect fb.io.enq.bits.sfb_masks[0], f4.io.deq.bits.sfb_masks[0] connect fb.io.enq.bits.sfb_masks[1], f4.io.deq.bits.sfb_masks[1] connect fb.io.enq.bits.sfb_masks[2], f4.io.deq.bits.sfb_masks[2] connect fb.io.enq.bits.sfb_masks[3], f4.io.deq.bits.sfb_masks[3] connect fb.io.enq.bits.sfb_masks[4], f4.io.deq.bits.sfb_masks[4] connect fb.io.enq.bits.sfb_masks[5], f4.io.deq.bits.sfb_masks[5] connect fb.io.enq.bits.sfb_masks[6], f4.io.deq.bits.sfb_masks[6] connect fb.io.enq.bits.sfb_masks[7], f4.io.deq.bits.sfb_masks[7] connect fb.io.enq.bits.sfbs[0], f4.io.deq.bits.sfbs[0] connect fb.io.enq.bits.sfbs[1], f4.io.deq.bits.sfbs[1] connect fb.io.enq.bits.sfbs[2], f4.io.deq.bits.sfbs[2] connect fb.io.enq.bits.sfbs[3], f4.io.deq.bits.sfbs[3] connect fb.io.enq.bits.sfbs[4], f4.io.deq.bits.sfbs[4] connect fb.io.enq.bits.sfbs[5], f4.io.deq.bits.sfbs[5] connect fb.io.enq.bits.sfbs[6], f4.io.deq.bits.sfbs[6] connect fb.io.enq.bits.sfbs[7], f4.io.deq.bits.sfbs[7] connect fb.io.enq.bits.exp_insts[0], f4.io.deq.bits.exp_insts[0] connect fb.io.enq.bits.exp_insts[1], f4.io.deq.bits.exp_insts[1] connect fb.io.enq.bits.exp_insts[2], f4.io.deq.bits.exp_insts[2] connect fb.io.enq.bits.exp_insts[3], f4.io.deq.bits.exp_insts[3] connect fb.io.enq.bits.exp_insts[4], f4.io.deq.bits.exp_insts[4] connect fb.io.enq.bits.exp_insts[5], f4.io.deq.bits.exp_insts[5] connect fb.io.enq.bits.exp_insts[6], f4.io.deq.bits.exp_insts[6] connect fb.io.enq.bits.exp_insts[7], f4.io.deq.bits.exp_insts[7] connect fb.io.enq.bits.insts[0], f4.io.deq.bits.insts[0] connect fb.io.enq.bits.insts[1], f4.io.deq.bits.insts[1] connect fb.io.enq.bits.insts[2], f4.io.deq.bits.insts[2] connect fb.io.enq.bits.insts[3], f4.io.deq.bits.insts[3] connect fb.io.enq.bits.insts[4], f4.io.deq.bits.insts[4] connect fb.io.enq.bits.insts[5], f4.io.deq.bits.insts[5] connect fb.io.enq.bits.insts[6], f4.io.deq.bits.insts[6] connect fb.io.enq.bits.insts[7], f4.io.deq.bits.insts[7] connect fb.io.enq.bits.edge_inst[0], f4.io.deq.bits.edge_inst[0] connect fb.io.enq.bits.edge_inst[1], f4.io.deq.bits.edge_inst[1] connect fb.io.enq.bits.next_pc, f4.io.deq.bits.next_pc connect fb.io.enq.bits.pc, f4.io.deq.bits.pc connect fb.io.enq.bits.ftq_idx, ftq.io.enq_idx node _T_115 = dshl(UInt<1>(0h1), f4_sfb_idx) node _T_116 = mux(f4_sfb_valid, _T_115, UInt<8>(0h0)) node _T_117 = bits(_T_116, 0, 0) node _T_118 = bits(_T_116, 1, 1) node _T_119 = bits(_T_116, 2, 2) node _T_120 = bits(_T_116, 3, 3) node _T_121 = bits(_T_116, 4, 4) node _T_122 = bits(_T_116, 5, 5) node _T_123 = bits(_T_116, 6, 6) node _T_124 = bits(_T_116, 7, 7) connect fb.io.enq.bits.sfbs[0], _T_117 connect fb.io.enq.bits.sfbs[1], _T_118 connect fb.io.enq.bits.sfbs[2], _T_119 connect fb.io.enq.bits.sfbs[3], _T_120 connect fb.io.enq.bits.sfbs[4], _T_121 connect fb.io.enq.bits.sfbs[5], _T_122 connect fb.io.enq.bits.sfbs[6], _T_123 connect fb.io.enq.bits.sfbs[7], _T_124 node _T_125 = bits(f4.io.deq.bits.sfb_masks[f4_sfb_idx], 7, 0) node _T_126 = mux(f4_sfb_valid, _T_125, UInt<8>(0h0)) node lo_lo = cat(f4.io.deq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[0]) node lo_hi = cat(f4.io.deq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[2]) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(f4.io.deq.bits.shadowed_mask[5], f4.io.deq.bits.shadowed_mask[4]) node hi_hi = cat(f4.io.deq.bits.shadowed_mask[7], f4.io.deq.bits.shadowed_mask[6]) node hi = cat(hi_hi, hi_lo) node _T_127 = cat(hi, lo) node _T_128 = or(_T_126, _T_127) node _T_129 = bits(_T_128, 0, 0) node _T_130 = bits(_T_128, 1, 1) node _T_131 = bits(_T_128, 2, 2) node _T_132 = bits(_T_128, 3, 3) node _T_133 = bits(_T_128, 4, 4) node _T_134 = bits(_T_128, 5, 5) node _T_135 = bits(_T_128, 6, 6) node _T_136 = bits(_T_128, 7, 7) connect fb.io.enq.bits.shadowed_mask[0], _T_129 connect fb.io.enq.bits.shadowed_mask[1], _T_130 connect fb.io.enq.bits.shadowed_mask[2], _T_131 connect fb.io.enq.bits.shadowed_mask[3], _T_132 connect fb.io.enq.bits.shadowed_mask[4], _T_133 connect fb.io.enq.bits.shadowed_mask[5], _T_134 connect fb.io.enq.bits.shadowed_mask[6], _T_135 connect fb.io.enq.bits.shadowed_mask[7], _T_136 node _ftq_io_enq_valid_T = and(f4.io.deq.valid, fb.io.enq.ready) node _ftq_io_enq_valid_T_1 = eq(f4_delay, UInt<1>(0h0)) node _ftq_io_enq_valid_T_2 = and(_ftq_io_enq_valid_T, _ftq_io_enq_valid_T_1) connect ftq.io.enq.valid, _ftq_io_enq_valid_T_2 connect ftq.io.enq.bits.tsrc, f4.io.deq.bits.tsrc connect ftq.io.enq.bits.fsrc, f4.io.deq.bits.fsrc connect ftq.io.enq.bits.bpd_meta[0], f4.io.deq.bits.bpd_meta[0] connect ftq.io.enq.bits.bpd_meta[1], f4.io.deq.bits.bpd_meta[1] connect ftq.io.enq.bits.end_half.bits, f4.io.deq.bits.end_half.bits connect ftq.io.enq.bits.end_half.valid, f4.io.deq.bits.end_half.valid connect ftq.io.enq.bits.bp_xcpt_if_oh[0], f4.io.deq.bits.bp_xcpt_if_oh[0] connect ftq.io.enq.bits.bp_xcpt_if_oh[1], f4.io.deq.bits.bp_xcpt_if_oh[1] connect ftq.io.enq.bits.bp_xcpt_if_oh[2], f4.io.deq.bits.bp_xcpt_if_oh[2] connect ftq.io.enq.bits.bp_xcpt_if_oh[3], f4.io.deq.bits.bp_xcpt_if_oh[3] connect ftq.io.enq.bits.bp_xcpt_if_oh[4], f4.io.deq.bits.bp_xcpt_if_oh[4] connect ftq.io.enq.bits.bp_xcpt_if_oh[5], f4.io.deq.bits.bp_xcpt_if_oh[5] connect ftq.io.enq.bits.bp_xcpt_if_oh[6], f4.io.deq.bits.bp_xcpt_if_oh[6] connect ftq.io.enq.bits.bp_xcpt_if_oh[7], f4.io.deq.bits.bp_xcpt_if_oh[7] connect ftq.io.enq.bits.bp_debug_if_oh[0], f4.io.deq.bits.bp_debug_if_oh[0] connect ftq.io.enq.bits.bp_debug_if_oh[1], f4.io.deq.bits.bp_debug_if_oh[1] connect ftq.io.enq.bits.bp_debug_if_oh[2], f4.io.deq.bits.bp_debug_if_oh[2] connect ftq.io.enq.bits.bp_debug_if_oh[3], f4.io.deq.bits.bp_debug_if_oh[3] connect ftq.io.enq.bits.bp_debug_if_oh[4], f4.io.deq.bits.bp_debug_if_oh[4] connect ftq.io.enq.bits.bp_debug_if_oh[5], f4.io.deq.bits.bp_debug_if_oh[5] connect ftq.io.enq.bits.bp_debug_if_oh[6], f4.io.deq.bits.bp_debug_if_oh[6] connect ftq.io.enq.bits.bp_debug_if_oh[7], f4.io.deq.bits.bp_debug_if_oh[7] connect ftq.io.enq.bits.xcpt_ae_if, f4.io.deq.bits.xcpt_ae_if connect ftq.io.enq.bits.xcpt_pf_if, f4.io.deq.bits.xcpt_pf_if connect ftq.io.enq.bits.lhist[0], f4.io.deq.bits.lhist[0] connect ftq.io.enq.bits.lhist[1], f4.io.deq.bits.lhist[1] connect ftq.io.enq.bits.ghist.ras_idx, f4.io.deq.bits.ghist.ras_idx connect ftq.io.enq.bits.ghist.new_saw_branch_taken, f4.io.deq.bits.ghist.new_saw_branch_taken connect ftq.io.enq.bits.ghist.new_saw_branch_not_taken, f4.io.deq.bits.ghist.new_saw_branch_not_taken connect ftq.io.enq.bits.ghist.current_saw_branch_not_taken, f4.io.deq.bits.ghist.current_saw_branch_not_taken connect ftq.io.enq.bits.ghist.old_history, f4.io.deq.bits.ghist.old_history connect ftq.io.enq.bits.br_mask, f4.io.deq.bits.br_mask connect ftq.io.enq.bits.mask, f4.io.deq.bits.mask connect ftq.io.enq.bits.ftq_idx, f4.io.deq.bits.ftq_idx connect ftq.io.enq.bits.ras_top, f4.io.deq.bits.ras_top connect ftq.io.enq.bits.cfi_npc_plus4, f4.io.deq.bits.cfi_npc_plus4 connect ftq.io.enq.bits.cfi_is_ret, f4.io.deq.bits.cfi_is_ret connect ftq.io.enq.bits.cfi_is_call, f4.io.deq.bits.cfi_is_call connect ftq.io.enq.bits.cfi_type, f4.io.deq.bits.cfi_type connect ftq.io.enq.bits.cfi_idx.bits, f4.io.deq.bits.cfi_idx.bits connect ftq.io.enq.bits.cfi_idx.valid, f4.io.deq.bits.cfi_idx.valid connect ftq.io.enq.bits.shadowed_mask[0], f4.io.deq.bits.shadowed_mask[0] connect ftq.io.enq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[1] connect ftq.io.enq.bits.shadowed_mask[2], f4.io.deq.bits.shadowed_mask[2] connect ftq.io.enq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[3] connect ftq.io.enq.bits.shadowed_mask[4], f4.io.deq.bits.shadowed_mask[4] connect ftq.io.enq.bits.shadowed_mask[5], f4.io.deq.bits.shadowed_mask[5] connect ftq.io.enq.bits.shadowed_mask[6], f4.io.deq.bits.shadowed_mask[6] connect ftq.io.enq.bits.shadowed_mask[7], f4.io.deq.bits.shadowed_mask[7] connect ftq.io.enq.bits.shadowable_mask[0], f4.io.deq.bits.shadowable_mask[0] connect ftq.io.enq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[1] connect ftq.io.enq.bits.shadowable_mask[2], f4.io.deq.bits.shadowable_mask[2] connect ftq.io.enq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[3] connect ftq.io.enq.bits.shadowable_mask[4], f4.io.deq.bits.shadowable_mask[4] connect ftq.io.enq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[5] connect ftq.io.enq.bits.shadowable_mask[6], f4.io.deq.bits.shadowable_mask[6] connect ftq.io.enq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[7] connect ftq.io.enq.bits.sfb_dests[0], f4.io.deq.bits.sfb_dests[0] connect ftq.io.enq.bits.sfb_dests[1], f4.io.deq.bits.sfb_dests[1] connect ftq.io.enq.bits.sfb_dests[2], f4.io.deq.bits.sfb_dests[2] connect ftq.io.enq.bits.sfb_dests[3], f4.io.deq.bits.sfb_dests[3] connect ftq.io.enq.bits.sfb_dests[4], f4.io.deq.bits.sfb_dests[4] connect ftq.io.enq.bits.sfb_dests[5], f4.io.deq.bits.sfb_dests[5] connect ftq.io.enq.bits.sfb_dests[6], f4.io.deq.bits.sfb_dests[6] connect ftq.io.enq.bits.sfb_dests[7], f4.io.deq.bits.sfb_dests[7] connect ftq.io.enq.bits.sfb_masks[0], f4.io.deq.bits.sfb_masks[0] connect ftq.io.enq.bits.sfb_masks[1], f4.io.deq.bits.sfb_masks[1] connect ftq.io.enq.bits.sfb_masks[2], f4.io.deq.bits.sfb_masks[2] connect ftq.io.enq.bits.sfb_masks[3], f4.io.deq.bits.sfb_masks[3] connect ftq.io.enq.bits.sfb_masks[4], f4.io.deq.bits.sfb_masks[4] connect ftq.io.enq.bits.sfb_masks[5], f4.io.deq.bits.sfb_masks[5] connect ftq.io.enq.bits.sfb_masks[6], f4.io.deq.bits.sfb_masks[6] connect ftq.io.enq.bits.sfb_masks[7], f4.io.deq.bits.sfb_masks[7] connect ftq.io.enq.bits.sfbs[0], f4.io.deq.bits.sfbs[0] connect ftq.io.enq.bits.sfbs[1], f4.io.deq.bits.sfbs[1] connect ftq.io.enq.bits.sfbs[2], f4.io.deq.bits.sfbs[2] connect ftq.io.enq.bits.sfbs[3], f4.io.deq.bits.sfbs[3] connect ftq.io.enq.bits.sfbs[4], f4.io.deq.bits.sfbs[4] connect ftq.io.enq.bits.sfbs[5], f4.io.deq.bits.sfbs[5] connect ftq.io.enq.bits.sfbs[6], f4.io.deq.bits.sfbs[6] connect ftq.io.enq.bits.sfbs[7], f4.io.deq.bits.sfbs[7] connect ftq.io.enq.bits.exp_insts[0], f4.io.deq.bits.exp_insts[0] connect ftq.io.enq.bits.exp_insts[1], f4.io.deq.bits.exp_insts[1] connect ftq.io.enq.bits.exp_insts[2], f4.io.deq.bits.exp_insts[2] connect ftq.io.enq.bits.exp_insts[3], f4.io.deq.bits.exp_insts[3] connect ftq.io.enq.bits.exp_insts[4], f4.io.deq.bits.exp_insts[4] connect ftq.io.enq.bits.exp_insts[5], f4.io.deq.bits.exp_insts[5] connect ftq.io.enq.bits.exp_insts[6], f4.io.deq.bits.exp_insts[6] connect ftq.io.enq.bits.exp_insts[7], f4.io.deq.bits.exp_insts[7] connect ftq.io.enq.bits.insts[0], f4.io.deq.bits.insts[0] connect ftq.io.enq.bits.insts[1], f4.io.deq.bits.insts[1] connect ftq.io.enq.bits.insts[2], f4.io.deq.bits.insts[2] connect ftq.io.enq.bits.insts[3], f4.io.deq.bits.insts[3] connect ftq.io.enq.bits.insts[4], f4.io.deq.bits.insts[4] connect ftq.io.enq.bits.insts[5], f4.io.deq.bits.insts[5] connect ftq.io.enq.bits.insts[6], f4.io.deq.bits.insts[6] connect ftq.io.enq.bits.insts[7], f4.io.deq.bits.insts[7] connect ftq.io.enq.bits.edge_inst[0], f4.io.deq.bits.edge_inst[0] connect ftq.io.enq.bits.edge_inst[1], f4.io.deq.bits.edge_inst[1] connect ftq.io.enq.bits.next_pc, f4.io.deq.bits.next_pc connect ftq.io.enq.bits.pc, f4.io.deq.bits.pc inst bpd_update_arbiter of Arbiter2_BranchPredictionUpdate_1 connect bpd_update_arbiter.clock, clock connect bpd_update_arbiter.reset, reset connect bpd_update_arbiter.io.in[0].valid, ftq.io.bpdupdate.valid connect bpd_update_arbiter.io.in[0].bits.meta[0], ftq.io.bpdupdate.bits.meta[0] connect bpd_update_arbiter.io.in[0].bits.meta[1], ftq.io.bpdupdate.bits.meta[1] connect bpd_update_arbiter.io.in[0].bits.target, ftq.io.bpdupdate.bits.target connect bpd_update_arbiter.io.in[0].bits.lhist[0], ftq.io.bpdupdate.bits.lhist[0] connect bpd_update_arbiter.io.in[0].bits.lhist[1], ftq.io.bpdupdate.bits.lhist[1] connect bpd_update_arbiter.io.in[0].bits.ghist.ras_idx, ftq.io.bpdupdate.bits.ghist.ras_idx connect bpd_update_arbiter.io.in[0].bits.ghist.new_saw_branch_taken, ftq.io.bpdupdate.bits.ghist.new_saw_branch_taken connect bpd_update_arbiter.io.in[0].bits.ghist.new_saw_branch_not_taken, ftq.io.bpdupdate.bits.ghist.new_saw_branch_not_taken connect bpd_update_arbiter.io.in[0].bits.ghist.current_saw_branch_not_taken, ftq.io.bpdupdate.bits.ghist.current_saw_branch_not_taken connect bpd_update_arbiter.io.in[0].bits.ghist.old_history, ftq.io.bpdupdate.bits.ghist.old_history connect bpd_update_arbiter.io.in[0].bits.cfi_is_jalr, ftq.io.bpdupdate.bits.cfi_is_jalr connect bpd_update_arbiter.io.in[0].bits.cfi_is_jal, ftq.io.bpdupdate.bits.cfi_is_jal connect bpd_update_arbiter.io.in[0].bits.cfi_is_br, ftq.io.bpdupdate.bits.cfi_is_br connect bpd_update_arbiter.io.in[0].bits.cfi_mispredicted, ftq.io.bpdupdate.bits.cfi_mispredicted connect bpd_update_arbiter.io.in[0].bits.cfi_taken, ftq.io.bpdupdate.bits.cfi_taken connect bpd_update_arbiter.io.in[0].bits.cfi_idx.bits, ftq.io.bpdupdate.bits.cfi_idx.bits connect bpd_update_arbiter.io.in[0].bits.cfi_idx.valid, ftq.io.bpdupdate.bits.cfi_idx.valid connect bpd_update_arbiter.io.in[0].bits.br_mask, ftq.io.bpdupdate.bits.br_mask connect bpd_update_arbiter.io.in[0].bits.pc, ftq.io.bpdupdate.bits.pc connect bpd_update_arbiter.io.in[0].bits.btb_mispredicts, ftq.io.bpdupdate.bits.btb_mispredicts connect bpd_update_arbiter.io.in[0].bits.is_repair_update, ftq.io.bpdupdate.bits.is_repair_update connect bpd_update_arbiter.io.in[0].bits.is_mispredict_update, ftq.io.bpdupdate.bits.is_mispredict_update node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(bpd_update_arbiter.io.in[0].ready, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed\n at frontend.scala:928 assert(bpd_update_arbiter.io.in(0).ready)\n") : printf_1 assert(clock, bpd_update_arbiter.io.in[0].ready, UInt<1>(0h1), "") : assert_1 connect bpd_update_arbiter.io.in[1], f4_btb_corrections.io.deq connect bpd.io.update.bits.meta[0], bpd_update_arbiter.io.out.bits.meta[0] connect bpd.io.update.bits.meta[1], bpd_update_arbiter.io.out.bits.meta[1] connect bpd.io.update.bits.target, bpd_update_arbiter.io.out.bits.target connect bpd.io.update.bits.lhist[0], bpd_update_arbiter.io.out.bits.lhist[0] connect bpd.io.update.bits.lhist[1], bpd_update_arbiter.io.out.bits.lhist[1] connect bpd.io.update.bits.ghist.ras_idx, bpd_update_arbiter.io.out.bits.ghist.ras_idx connect bpd.io.update.bits.ghist.new_saw_branch_taken, bpd_update_arbiter.io.out.bits.ghist.new_saw_branch_taken connect bpd.io.update.bits.ghist.new_saw_branch_not_taken, bpd_update_arbiter.io.out.bits.ghist.new_saw_branch_not_taken connect bpd.io.update.bits.ghist.current_saw_branch_not_taken, bpd_update_arbiter.io.out.bits.ghist.current_saw_branch_not_taken connect bpd.io.update.bits.ghist.old_history, bpd_update_arbiter.io.out.bits.ghist.old_history connect bpd.io.update.bits.cfi_is_jalr, bpd_update_arbiter.io.out.bits.cfi_is_jalr connect bpd.io.update.bits.cfi_is_jal, bpd_update_arbiter.io.out.bits.cfi_is_jal connect bpd.io.update.bits.cfi_is_br, bpd_update_arbiter.io.out.bits.cfi_is_br connect bpd.io.update.bits.cfi_mispredicted, bpd_update_arbiter.io.out.bits.cfi_mispredicted connect bpd.io.update.bits.cfi_taken, bpd_update_arbiter.io.out.bits.cfi_taken connect bpd.io.update.bits.cfi_idx.bits, bpd_update_arbiter.io.out.bits.cfi_idx.bits connect bpd.io.update.bits.cfi_idx.valid, bpd_update_arbiter.io.out.bits.cfi_idx.valid connect bpd.io.update.bits.br_mask, bpd_update_arbiter.io.out.bits.br_mask connect bpd.io.update.bits.pc, bpd_update_arbiter.io.out.bits.pc connect bpd.io.update.bits.btb_mispredicts, bpd_update_arbiter.io.out.bits.btb_mispredicts connect bpd.io.update.bits.is_repair_update, bpd_update_arbiter.io.out.bits.is_repair_update connect bpd.io.update.bits.is_mispredict_update, bpd_update_arbiter.io.out.bits.is_mispredict_update connect bpd.io.update.valid, bpd_update_arbiter.io.out.valid connect bpd_update_arbiter.io.out.ready, UInt<1>(0h1) node _T_140 = and(ftq.io.ras_update, UInt<1>(0h1)) when _T_140 : connect ras.io.write_valid, UInt<1>(0h1) connect ras.io.write_idx, ftq.io.ras_update_idx connect ras.io.write_addr, ftq.io.ras_update_pc connect io.cpu.fetchpacket.bits, fb.io.deq.bits connect io.cpu.fetchpacket.valid, fb.io.deq.valid connect fb.io.deq.ready, io.cpu.fetchpacket.ready connect io.cpu.get_pc[0].next_pc, ftq.io.get_ftq_pc[0].next_pc connect io.cpu.get_pc[0].next_val, ftq.io.get_ftq_pc[0].next_val connect io.cpu.get_pc[0].com_pc, ftq.io.get_ftq_pc[0].com_pc connect io.cpu.get_pc[0].pc, ftq.io.get_ftq_pc[0].pc connect io.cpu.get_pc[0].ghist, ftq.io.get_ftq_pc[0].ghist connect io.cpu.get_pc[0].entry, ftq.io.get_ftq_pc[0].entry connect ftq.io.get_ftq_pc[0].ftq_idx, io.cpu.get_pc[0].ftq_idx connect io.cpu.get_pc[1].next_pc, ftq.io.get_ftq_pc[1].next_pc connect io.cpu.get_pc[1].next_val, ftq.io.get_ftq_pc[1].next_val connect io.cpu.get_pc[1].com_pc, ftq.io.get_ftq_pc[1].com_pc connect io.cpu.get_pc[1].pc, ftq.io.get_ftq_pc[1].pc connect io.cpu.get_pc[1].ghist, ftq.io.get_ftq_pc[1].ghist connect io.cpu.get_pc[1].entry, ftq.io.get_ftq_pc[1].entry connect ftq.io.get_ftq_pc[1].ftq_idx, io.cpu.get_pc[1].ftq_idx connect ftq.io.deq.bits, io.cpu.commit.bits connect ftq.io.deq.valid, io.cpu.commit.valid connect ftq.io.brupdate.b2.target_offset, io.cpu.brupdate.b2.target_offset connect ftq.io.brupdate.b2.jalr_target, io.cpu.brupdate.b2.jalr_target connect ftq.io.brupdate.b2.pc_sel, io.cpu.brupdate.b2.pc_sel connect ftq.io.brupdate.b2.cfi_type, io.cpu.brupdate.b2.cfi_type connect ftq.io.brupdate.b2.taken, io.cpu.brupdate.b2.taken connect ftq.io.brupdate.b2.mispredict, io.cpu.brupdate.b2.mispredict connect ftq.io.brupdate.b2.valid, io.cpu.brupdate.b2.valid connect ftq.io.brupdate.b2.uop.debug_tsrc, io.cpu.brupdate.b2.uop.debug_tsrc connect ftq.io.brupdate.b2.uop.debug_fsrc, io.cpu.brupdate.b2.uop.debug_fsrc connect ftq.io.brupdate.b2.uop.bp_xcpt_if, io.cpu.brupdate.b2.uop.bp_xcpt_if connect ftq.io.brupdate.b2.uop.bp_debug_if, io.cpu.brupdate.b2.uop.bp_debug_if connect ftq.io.brupdate.b2.uop.xcpt_ma_if, io.cpu.brupdate.b2.uop.xcpt_ma_if connect ftq.io.brupdate.b2.uop.xcpt_ae_if, io.cpu.brupdate.b2.uop.xcpt_ae_if connect ftq.io.brupdate.b2.uop.xcpt_pf_if, io.cpu.brupdate.b2.uop.xcpt_pf_if connect ftq.io.brupdate.b2.uop.fp_single, io.cpu.brupdate.b2.uop.fp_single connect ftq.io.brupdate.b2.uop.fp_val, io.cpu.brupdate.b2.uop.fp_val connect ftq.io.brupdate.b2.uop.frs3_en, io.cpu.brupdate.b2.uop.frs3_en connect ftq.io.brupdate.b2.uop.lrs2_rtype, io.cpu.brupdate.b2.uop.lrs2_rtype connect ftq.io.brupdate.b2.uop.lrs1_rtype, io.cpu.brupdate.b2.uop.lrs1_rtype connect ftq.io.brupdate.b2.uop.dst_rtype, io.cpu.brupdate.b2.uop.dst_rtype connect ftq.io.brupdate.b2.uop.ldst_val, io.cpu.brupdate.b2.uop.ldst_val connect ftq.io.brupdate.b2.uop.lrs3, io.cpu.brupdate.b2.uop.lrs3 connect ftq.io.brupdate.b2.uop.lrs2, io.cpu.brupdate.b2.uop.lrs2 connect ftq.io.brupdate.b2.uop.lrs1, io.cpu.brupdate.b2.uop.lrs1 connect ftq.io.brupdate.b2.uop.ldst, io.cpu.brupdate.b2.uop.ldst connect ftq.io.brupdate.b2.uop.ldst_is_rs1, io.cpu.brupdate.b2.uop.ldst_is_rs1 connect ftq.io.brupdate.b2.uop.flush_on_commit, io.cpu.brupdate.b2.uop.flush_on_commit connect ftq.io.brupdate.b2.uop.is_unique, io.cpu.brupdate.b2.uop.is_unique connect ftq.io.brupdate.b2.uop.is_sys_pc2epc, io.cpu.brupdate.b2.uop.is_sys_pc2epc connect ftq.io.brupdate.b2.uop.uses_stq, io.cpu.brupdate.b2.uop.uses_stq connect ftq.io.brupdate.b2.uop.uses_ldq, io.cpu.brupdate.b2.uop.uses_ldq connect ftq.io.brupdate.b2.uop.is_amo, io.cpu.brupdate.b2.uop.is_amo connect ftq.io.brupdate.b2.uop.is_fencei, io.cpu.brupdate.b2.uop.is_fencei connect ftq.io.brupdate.b2.uop.is_fence, io.cpu.brupdate.b2.uop.is_fence connect ftq.io.brupdate.b2.uop.mem_signed, io.cpu.brupdate.b2.uop.mem_signed connect ftq.io.brupdate.b2.uop.mem_size, io.cpu.brupdate.b2.uop.mem_size connect ftq.io.brupdate.b2.uop.mem_cmd, io.cpu.brupdate.b2.uop.mem_cmd connect ftq.io.brupdate.b2.uop.bypassable, io.cpu.brupdate.b2.uop.bypassable connect ftq.io.brupdate.b2.uop.exc_cause, io.cpu.brupdate.b2.uop.exc_cause connect ftq.io.brupdate.b2.uop.exception, io.cpu.brupdate.b2.uop.exception connect ftq.io.brupdate.b2.uop.stale_pdst, io.cpu.brupdate.b2.uop.stale_pdst connect ftq.io.brupdate.b2.uop.ppred_busy, io.cpu.brupdate.b2.uop.ppred_busy connect ftq.io.brupdate.b2.uop.prs3_busy, io.cpu.brupdate.b2.uop.prs3_busy connect ftq.io.brupdate.b2.uop.prs2_busy, io.cpu.brupdate.b2.uop.prs2_busy connect ftq.io.brupdate.b2.uop.prs1_busy, io.cpu.brupdate.b2.uop.prs1_busy connect ftq.io.brupdate.b2.uop.ppred, io.cpu.brupdate.b2.uop.ppred connect ftq.io.brupdate.b2.uop.prs3, io.cpu.brupdate.b2.uop.prs3 connect ftq.io.brupdate.b2.uop.prs2, io.cpu.brupdate.b2.uop.prs2 connect ftq.io.brupdate.b2.uop.prs1, io.cpu.brupdate.b2.uop.prs1 connect ftq.io.brupdate.b2.uop.pdst, io.cpu.brupdate.b2.uop.pdst connect ftq.io.brupdate.b2.uop.rxq_idx, io.cpu.brupdate.b2.uop.rxq_idx connect ftq.io.brupdate.b2.uop.stq_idx, io.cpu.brupdate.b2.uop.stq_idx connect ftq.io.brupdate.b2.uop.ldq_idx, io.cpu.brupdate.b2.uop.ldq_idx connect ftq.io.brupdate.b2.uop.rob_idx, io.cpu.brupdate.b2.uop.rob_idx connect ftq.io.brupdate.b2.uop.csr_addr, io.cpu.brupdate.b2.uop.csr_addr connect ftq.io.brupdate.b2.uop.imm_packed, io.cpu.brupdate.b2.uop.imm_packed connect ftq.io.brupdate.b2.uop.taken, io.cpu.brupdate.b2.uop.taken connect ftq.io.brupdate.b2.uop.pc_lob, io.cpu.brupdate.b2.uop.pc_lob connect ftq.io.brupdate.b2.uop.edge_inst, io.cpu.brupdate.b2.uop.edge_inst connect ftq.io.brupdate.b2.uop.ftq_idx, io.cpu.brupdate.b2.uop.ftq_idx connect ftq.io.brupdate.b2.uop.br_tag, io.cpu.brupdate.b2.uop.br_tag connect ftq.io.brupdate.b2.uop.br_mask, io.cpu.brupdate.b2.uop.br_mask connect ftq.io.brupdate.b2.uop.is_sfb, io.cpu.brupdate.b2.uop.is_sfb connect ftq.io.brupdate.b2.uop.is_jal, io.cpu.brupdate.b2.uop.is_jal connect ftq.io.brupdate.b2.uop.is_jalr, io.cpu.brupdate.b2.uop.is_jalr connect ftq.io.brupdate.b2.uop.is_br, io.cpu.brupdate.b2.uop.is_br connect ftq.io.brupdate.b2.uop.iw_p2_poisoned, io.cpu.brupdate.b2.uop.iw_p2_poisoned connect ftq.io.brupdate.b2.uop.iw_p1_poisoned, io.cpu.brupdate.b2.uop.iw_p1_poisoned connect ftq.io.brupdate.b2.uop.iw_state, io.cpu.brupdate.b2.uop.iw_state connect ftq.io.brupdate.b2.uop.ctrl.is_std, io.cpu.brupdate.b2.uop.ctrl.is_std connect ftq.io.brupdate.b2.uop.ctrl.is_sta, io.cpu.brupdate.b2.uop.ctrl.is_sta connect ftq.io.brupdate.b2.uop.ctrl.is_load, io.cpu.brupdate.b2.uop.ctrl.is_load connect ftq.io.brupdate.b2.uop.ctrl.csr_cmd, io.cpu.brupdate.b2.uop.ctrl.csr_cmd connect ftq.io.brupdate.b2.uop.ctrl.fcn_dw, io.cpu.brupdate.b2.uop.ctrl.fcn_dw connect ftq.io.brupdate.b2.uop.ctrl.op_fcn, io.cpu.brupdate.b2.uop.ctrl.op_fcn connect ftq.io.brupdate.b2.uop.ctrl.imm_sel, io.cpu.brupdate.b2.uop.ctrl.imm_sel connect ftq.io.brupdate.b2.uop.ctrl.op2_sel, io.cpu.brupdate.b2.uop.ctrl.op2_sel connect ftq.io.brupdate.b2.uop.ctrl.op1_sel, io.cpu.brupdate.b2.uop.ctrl.op1_sel connect ftq.io.brupdate.b2.uop.ctrl.br_type, io.cpu.brupdate.b2.uop.ctrl.br_type connect ftq.io.brupdate.b2.uop.fu_code, io.cpu.brupdate.b2.uop.fu_code connect ftq.io.brupdate.b2.uop.iq_type, io.cpu.brupdate.b2.uop.iq_type connect ftq.io.brupdate.b2.uop.debug_pc, io.cpu.brupdate.b2.uop.debug_pc connect ftq.io.brupdate.b2.uop.is_rvc, io.cpu.brupdate.b2.uop.is_rvc connect ftq.io.brupdate.b2.uop.debug_inst, io.cpu.brupdate.b2.uop.debug_inst connect ftq.io.brupdate.b2.uop.inst, io.cpu.brupdate.b2.uop.inst connect ftq.io.brupdate.b2.uop.uopc, io.cpu.brupdate.b2.uop.uopc connect ftq.io.brupdate.b1.mispredict_mask, io.cpu.brupdate.b1.mispredict_mask connect ftq.io.brupdate.b1.resolve_mask, io.cpu.brupdate.b1.resolve_mask connect ftq.io.redirect.valid, io.cpu.redirect_val connect ftq.io.redirect.bits, io.cpu.redirect_ftq_idx connect fb.io.clear, UInt<1>(0h0) when io.cpu.sfence.valid : connect fb.io.clear, UInt<1>(0h1) connect f4_clear, UInt<1>(0h1) connect f3_clear, UInt<1>(0h1) connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) connect s0_valid, UInt<1>(0h0) connect s0_vpc, io.cpu.sfence.bits.addr connect s0_is_replay, UInt<1>(0h0) connect s0_is_sfence, UInt<1>(0h1) else : when io.cpu.redirect_flush : connect fb.io.clear, UInt<1>(0h1) connect f4_clear, UInt<1>(0h1) connect f3_clear, UInt<1>(0h1) connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) connect f3_prev_is_half, UInt<1>(0h0) connect s0_valid, io.cpu.redirect_val connect s0_vpc, io.cpu.redirect_pc connect s0_ghist, io.cpu.redirect_ghist connect s0_tsrc, UInt<2>(0h3) connect s0_is_replay, UInt<1>(0h0) connect ftq.io.redirect.valid, io.cpu.redirect_val connect ftq.io.redirect.bits, io.cpu.redirect_ftq_idx connect ftq.io.debug_ftq_idx[0], io.cpu.debug_ftq_idx[0] connect ftq.io.debug_ftq_idx[1], io.cpu.debug_ftq_idx[1] connect ftq.io.debug_ftq_idx[2], io.cpu.debug_ftq_idx[2] connect io.cpu.debug_fetch_pc, ftq.io.debug_fetch_pc	module BoomFrontend_1( // @[frontend.scala:322:7] input clock, // @[frontend.scala:322:7] input reset, // @[frontend.scala:322:7] input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_cpu_fetchpacket_ready, // @[frontend.scala:326:14] output io_cpu_fetchpacket_valid, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_valid, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_0_bits_inst, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_inst, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_is_rvc, // @[frontend.scala:326:14] output [39:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_pc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_is_sfb, // @[frontend.scala:326:14] output [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_edge_inst, // @[frontend.scala:326:14] output [5:0] io_cpu_fetchpacket_bits_uops_0_bits_pc_lob, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_taken, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[frontend.scala:326:14] output [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_valid, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_1_bits_inst, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_inst, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_is_rvc, // @[frontend.scala:326:14] output [39:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_pc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_is_sfb, // @[frontend.scala:326:14] output [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_edge_inst, // @[frontend.scala:326:14] output [5:0] io_cpu_fetchpacket_bits_uops_1_bits_pc_lob, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_taken, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if, // @[frontend.scala:326:14] output [1:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_valid, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_2_bits_inst, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_inst, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_is_rvc, // @[frontend.scala:326:14] output [39:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_pc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_is_sfb, // @[frontend.scala:326:14] output [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_edge_inst, // @[frontend.scala:326:14] output [5:0] io_cpu_fetchpacket_bits_uops_2_bits_pc_lob, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_taken, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if, // @[frontend.scala:326:14] output [1:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc, // @[frontend.scala:326:14] input [4:0] io_cpu_get_pc_0_ftq_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_idx_valid, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_0_entry_cfi_idx_bits, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_mispredicted, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_0_entry_cfi_type, // @[frontend.scala:326:14] output [7:0] io_cpu_get_pc_0_entry_br_mask, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_is_call, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_is_ret, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_npc_plus4, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_entry_ras_top, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_0_entry_ras_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_start_bank, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_com_pc, // @[frontend.scala:326:14] output io_cpu_get_pc_0_next_val, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_next_pc, // @[frontend.scala:326:14] input [4:0] io_cpu_get_pc_1_ftq_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_idx_valid, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_1_entry_cfi_idx_bits, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_mispredicted, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_1_entry_cfi_type, // @[frontend.scala:326:14] output [7:0] io_cpu_get_pc_1_entry_br_mask, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_is_call, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_is_ret, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_npc_plus4, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_entry_ras_top, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_1_entry_ras_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_start_bank, // @[frontend.scala:326:14] output [63:0] io_cpu_get_pc_1_ghist_old_history, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_current_saw_branch_not_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_new_saw_branch_not_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_new_saw_branch_taken, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_1_ghist_ras_idx, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_com_pc, // @[frontend.scala:326:14] output io_cpu_get_pc_1_next_val, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_next_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_debug_fetch_pc_0, // @[frontend.scala:326:14] output [39:0] io_cpu_debug_fetch_pc_1, // @[frontend.scala:326:14] output [39:0] io_cpu_debug_fetch_pc_2, // @[frontend.scala:326:14] input io_cpu_status_debug, // @[frontend.scala:326:14] input io_cpu_status_cease, // @[frontend.scala:326:14] input io_cpu_status_wfi, // @[frontend.scala:326:14] input [1:0] io_cpu_status_dprv, // @[frontend.scala:326:14] input io_cpu_status_dv, // @[frontend.scala:326:14] input [1:0] io_cpu_status_prv, // @[frontend.scala:326:14] input io_cpu_status_v, // @[frontend.scala:326:14] input io_cpu_status_sd, // @[frontend.scala:326:14] input io_cpu_status_mpv, // @[frontend.scala:326:14] input io_cpu_status_gva, // @[frontend.scala:326:14] input io_cpu_status_tsr, // @[frontend.scala:326:14] input io_cpu_status_tw, // @[frontend.scala:326:14] input io_cpu_status_tvm, // @[frontend.scala:326:14] input io_cpu_status_mxr, // @[frontend.scala:326:14] input io_cpu_status_sum, // @[frontend.scala:326:14] input io_cpu_status_mprv, // @[frontend.scala:326:14] input [1:0] io_cpu_status_fs, // @[frontend.scala:326:14] input [1:0] io_cpu_status_mpp, // @[frontend.scala:326:14] input io_cpu_status_spp, // @[frontend.scala:326:14] input io_cpu_status_mpie, // @[frontend.scala:326:14] input io_cpu_status_spie, // @[frontend.scala:326:14] input io_cpu_status_mie, // @[frontend.scala:326:14] input io_cpu_status_sie, // @[frontend.scala:326:14] input io_cpu_sfence_valid, // @[frontend.scala:326:14] input io_cpu_sfence_bits_rs1, // @[frontend.scala:326:14] input io_cpu_sfence_bits_rs2, // @[frontend.scala:326:14] input [38:0] io_cpu_sfence_bits_addr, // @[frontend.scala:326:14] input io_cpu_sfence_bits_asid, // @[frontend.scala:326:14] input [15:0] io_cpu_brupdate_b1_resolve_mask, // @[frontend.scala:326:14] input [15:0] io_cpu_brupdate_b1_mispredict_mask, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_uopc, // @[frontend.scala:326:14] input [31:0] io_cpu_brupdate_b2_uop_inst, // @[frontend.scala:326:14] input [31:0] io_cpu_brupdate_b2_uop_debug_inst, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_rvc, // @[frontend.scala:326:14] input [39:0] io_cpu_brupdate_b2_uop_debug_pc, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_iq_type, // @[frontend.scala:326:14] input [9:0] io_cpu_brupdate_b2_uop_fu_code, // @[frontend.scala:326:14] input [3:0] io_cpu_brupdate_b2_uop_ctrl_br_type, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_ctrl_op1_sel, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_op2_sel, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_imm_sel, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ctrl_op_fcn, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_fcn_dw, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_csr_cmd, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_load, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_sta, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_std, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_iw_state, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_iw_p1_poisoned, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_iw_p2_poisoned, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_br, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_jalr, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_jal, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_sfb, // @[frontend.scala:326:14] input [15:0] io_cpu_brupdate_b2_uop_br_mask, // @[frontend.scala:326:14] input [3:0] io_cpu_brupdate_b2_uop_br_tag, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ftq_idx, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_edge_inst, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_pc_lob, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_taken, // @[frontend.scala:326:14] input [19:0] io_cpu_brupdate_b2_uop_imm_packed, // @[frontend.scala:326:14] input [11:0] io_cpu_brupdate_b2_uop_csr_addr, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_rob_idx, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ldq_idx, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_stq_idx, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_rxq_idx, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_pdst, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_prs1, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_prs2, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_prs3, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ppred, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs1_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs2_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs3_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ppred_busy, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_stale_pdst, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_exception, // @[frontend.scala:326:14] input [63:0] io_cpu_brupdate_b2_uop_exc_cause, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bypassable, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_mem_cmd, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_mem_size, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_mem_signed, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_fence, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_fencei, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_amo, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_uses_ldq, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_uses_stq, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_sys_pc2epc, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_unique, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_flush_on_commit, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ldst_is_rs1, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_ldst, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs1, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs2, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs3, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ldst_val, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_dst_rtype, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_lrs1_rtype, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_lrs2_rtype, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_frs3_en, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_fp_val, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_fp_single, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_pf_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_ae_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_ma_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bp_debug_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bp_xcpt_if, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_debug_fsrc, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_debug_tsrc, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_valid, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_mispredict, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_taken, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_cfi_type, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_pc_sel, // @[frontend.scala:326:14] input [39:0] io_cpu_brupdate_b2_jalr_target, // @[frontend.scala:326:14] input [20:0] io_cpu_brupdate_b2_target_offset, // @[frontend.scala:326:14] input io_cpu_redirect_flush, // @[frontend.scala:326:14] input io_cpu_redirect_val, // @[frontend.scala:326:14] input [39:0] io_cpu_redirect_pc, // @[frontend.scala:326:14] input [4:0] io_cpu_redirect_ftq_idx, // @[frontend.scala:326:14] input [63:0] io_cpu_redirect_ghist_old_history, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_current_saw_branch_not_taken, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_new_saw_branch_not_taken, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_new_saw_branch_taken, // @[frontend.scala:326:14] input [4:0] io_cpu_redirect_ghist_ras_idx, // @[frontend.scala:326:14] input io_cpu_commit_valid, // @[frontend.scala:326:14] input [31:0] io_cpu_commit_bits, // @[frontend.scala:326:14] input io_cpu_flush_icache, // @[frontend.scala:326:14] output io_cpu_perf_acquire, // @[frontend.scala:326:14] output io_cpu_perf_tlbMiss, // @[frontend.scala:326:14] input io_ptw_req_ready, // @[frontend.scala:326:14] output io_ptw_req_valid, // @[frontend.scala:326:14] output [26:0] io_ptw_req_bits_bits_addr, // @[frontend.scala:326:14] output io_ptw_req_bits_bits_need_gpa, // @[frontend.scala:326:14] input io_ptw_resp_valid, // @[frontend.scala:326:14] input io_ptw_resp_bits_ae_ptw, // @[frontend.scala:326:14] input io_ptw_resp_bits_ae_final, // @[frontend.scala:326:14] input io_ptw_resp_bits_pf, // @[frontend.scala:326:14] input io_ptw_resp_bits_gf, // @[frontend.scala:326:14] input io_ptw_resp_bits_hr, // @[frontend.scala:326:14] input io_ptw_resp_bits_hw, // @[frontend.scala:326:14] input io_ptw_resp_bits_hx, // @[frontend.scala:326:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[frontend.scala:326:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[frontend.scala:326:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_d, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_a, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_g, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_u, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_x, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_w, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_r, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_v, // @[frontend.scala:326:14] input [1:0] io_ptw_resp_bits_level, // @[frontend.scala:326:14] input io_ptw_resp_bits_homogeneous, // @[frontend.scala:326:14] input io_ptw_resp_bits_gpa_valid, // @[frontend.scala:326:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[frontend.scala:326:14] input io_ptw_resp_bits_gpa_is_pte, // @[frontend.scala:326:14] input [3:0] io_ptw_ptbr_mode, // @[frontend.scala:326:14] input [43:0] io_ptw_ptbr_ppn, // @[frontend.scala:326:14] input io_ptw_status_debug, // @[frontend.scala:326:14] input io_ptw_status_cease, // @[frontend.scala:326:14] input io_ptw_status_wfi, // @[frontend.scala:326:14] input [1:0] io_ptw_status_dprv, // @[frontend.scala:326:14] input io_ptw_status_dv, // @[frontend.scala:326:14] input [1:0] io_ptw_status_prv, // @[frontend.scala:326:14] input io_ptw_status_v, // @[frontend.scala:326:14] input io_ptw_status_sd, // @[frontend.scala:326:14] input io_ptw_status_mpv, // @[frontend.scala:326:14] input io_ptw_status_gva, // @[frontend.scala:326:14] input io_ptw_status_tsr, // @[frontend.scala:326:14] input io_ptw_status_tw, // @[frontend.scala:326:14] input io_ptw_status_tvm, // @[frontend.scala:326:14] input io_ptw_status_mxr, // @[frontend.scala:326:14] input io_ptw_status_sum, // @[frontend.scala:326:14] input io_ptw_status_mprv, // @[frontend.scala:326:14] input [1:0] io_ptw_status_fs, // @[frontend.scala:326:14] input [1:0] io_ptw_status_mpp, // @[frontend.scala:326:14] input io_ptw_status_spp, // @[frontend.scala:326:14] input io_ptw_status_mpie, // @[frontend.scala:326:14] input io_ptw_status_spie, // @[frontend.scala:326:14] input io_ptw_status_mie, // @[frontend.scala:326:14] input io_ptw_status_sie, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_0_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_0_mask, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_1_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_1_mask, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_2_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_2_mask, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_3_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_3_mask, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_4_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_4_mask, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_5_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_5_mask, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_6_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_6_mask, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_7_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_7_mask // @[frontend.scala:326:14] ); wire [4:0] f3_io_enq_bits_ghist_ras_idx; // @[frontend.scala:533:24, :814:38, :821:79, :822:28] wire f3_fetch_bundle_cfi_is_ret; // @[frontend.scala:569:29] wire [2:0] f3_fetch_bundle_cfi_idx_bits; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_idx_valid; // @[frontend.scala:569:29] wire _bpd_update_arbiter_io_in_1_ready; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_valid; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_is_mispredict_update; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_is_repair_update; // @[frontend.scala:925:34] wire [7:0] _bpd_update_arbiter_io_out_bits_btb_mispredicts; // @[frontend.scala:925:34] wire [39:0] _bpd_update_arbiter_io_out_bits_pc; // @[frontend.scala:925:34] wire [7:0] _bpd_update_arbiter_io_out_bits_br_mask; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_idx_valid; // @[frontend.scala:925:34] wire [2:0] _bpd_update_arbiter_io_out_bits_cfi_idx_bits; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_mispredicted; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_br; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_jal; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_jalr; // @[frontend.scala:925:34] wire [63:0] _bpd_update_arbiter_io_out_bits_ghist_old_history; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_new_saw_branch_taken; // @[frontend.scala:925:34] wire [4:0] _bpd_update_arbiter_io_out_bits_ghist_ras_idx; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_lhist_0; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_lhist_1; // @[frontend.scala:925:34] wire [39:0] _bpd_update_arbiter_io_out_bits_target; // @[frontend.scala:925:34] wire [119:0] _bpd_update_arbiter_io_out_bits_meta_0; // @[frontend.scala:925:34] wire [119:0] _bpd_update_arbiter_io_out_bits_meta_1; // @[frontend.scala:925:34] wire _ftq_io_enq_ready; // @[frontend.scala:862:19] wire [4:0] _ftq_io_enq_idx; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_valid; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_is_mispredict_update; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_is_repair_update; // @[frontend.scala:862:19] wire [39:0] _ftq_io_bpdupdate_bits_pc; // @[frontend.scala:862:19] wire [7:0] _ftq_io_bpdupdate_bits_br_mask; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_idx_valid; // @[frontend.scala:862:19] wire [2:0] _ftq_io_bpdupdate_bits_cfi_idx_bits; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_mispredicted; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_is_br; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_is_jal; // @[frontend.scala:862:19] wire [63:0] _ftq_io_bpdupdate_bits_ghist_old_history; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_new_saw_branch_taken; // @[frontend.scala:862:19] wire [4:0] _ftq_io_bpdupdate_bits_ghist_ras_idx; // @[frontend.scala:862:19] wire [39:0] _ftq_io_bpdupdate_bits_target; // @[frontend.scala:862:19] wire [119:0] _ftq_io_bpdupdate_bits_meta_0; // @[frontend.scala:862:19] wire [119:0] _ftq_io_bpdupdate_bits_meta_1; // @[frontend.scala:862:19] wire _ftq_io_ras_update; // @[frontend.scala:862:19] wire [4:0] _ftq_io_ras_update_idx; // @[frontend.scala:862:19] wire [39:0] _ftq_io_ras_update_pc; // @[frontend.scala:862:19] wire _fb_io_enq_ready; // @[frontend.scala:861:19] wire _f4_io_deq_valid; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_pc; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_next_pc; // @[frontend.scala:859:11] wire _f4_io_deq_bits_edge_inst_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_edge_inst_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_0; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_2; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_3; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_4; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_5; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_6; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_7; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_0; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_2; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_3; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_4; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_5; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_6; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_7; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_0; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_1; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_2; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_3; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_4; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_5; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_6; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_7; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_0; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_1; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_2; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_3; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_4; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_5; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_6; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_idx_valid; // @[frontend.scala:859:11] wire [2:0] _f4_io_deq_bits_cfi_idx_bits; // @[frontend.scala:859:11] wire [2:0] _f4_io_deq_bits_cfi_type; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_is_call; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_is_ret; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_npc_plus4; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_ras_top; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_ftq_idx; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_mask; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_br_mask; // @[frontend.scala:859:11] wire [63:0] _f4_io_deq_bits_ghist_old_history; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_new_saw_branch_taken; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_ghist_ras_idx; // @[frontend.scala:859:11] wire _f4_io_deq_bits_lhist_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_lhist_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_xcpt_pf_if; // @[frontend.scala:859:11] wire _f4_io_deq_bits_xcpt_ae_if; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_end_half_valid; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_end_half_bits; // @[frontend.scala:859:11] wire [119:0] _f4_io_deq_bits_bpd_meta_0; // @[frontend.scala:859:11] wire [119:0] _f4_io_deq_bits_bpd_meta_1; // @[frontend.scala:859:11] wire [1:0] _f4_io_deq_bits_fsrc; // @[frontend.scala:859:11] wire [1:0] _f4_io_deq_bits_tsrc; // @[frontend.scala:859:11] wire _f4_btb_corrections_io_deq_valid; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_is_mispredict_update; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_is_repair_update; // @[frontend.scala:842:34] wire [7:0] _f4_btb_corrections_io_deq_bits_btb_mispredicts; // @[frontend.scala:842:34] wire [39:0] _f4_btb_corrections_io_deq_bits_pc; // @[frontend.scala:842:34] wire [7:0] _f4_btb_corrections_io_deq_bits_br_mask; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_idx_valid; // @[frontend.scala:842:34] wire [2:0] _f4_btb_corrections_io_deq_bits_cfi_idx_bits; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_mispredicted; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_br; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_jal; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_jalr; // @[frontend.scala:842:34] wire [63:0] _f4_btb_corrections_io_deq_bits_ghist_old_history; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_new_saw_branch_taken; // @[frontend.scala:842:34] wire [4:0] _f4_btb_corrections_io_deq_bits_ghist_ras_idx; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_lhist_0; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_lhist_1; // @[frontend.scala:842:34] wire [39:0] _f4_btb_corrections_io_deq_bits_target; // @[frontend.scala:842:34] wire [119:0] _f4_btb_corrections_io_deq_bits_meta_0; // @[frontend.scala:842:34] wire [119:0] _f4_btb_corrections_io_deq_bits_meta_1; // @[frontend.scala:842:34] wire [31:0] _exp_inst_rvc_exp_5_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_5_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_4_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_4_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_3_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_3_io_rvc; // @[consts.scala:330:25] wire _bpd_decoder0b_io_out_is_ret; // @[frontend.scala:639:39] wire _bpd_decoder0b_io_out_is_call; // @[frontend.scala:639:39] wire [39:0] _bpd_decoder0b_io_out_target; // @[frontend.scala:639:39] wire [2:0] _bpd_decoder0b_io_out_cfi_type; // @[frontend.scala:639:39] wire _bpd_decoder0b_io_out_sfb_offset_valid; // @[frontend.scala:639:39] wire [5:0] _bpd_decoder0b_io_out_sfb_offset_bits; // @[frontend.scala:639:39] wire _bpd_decoder0b_io_out_shadowable; // @[frontend.scala:639:39] wire [31:0] _exp_inst0b_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst0b_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _bpd_decoder1_1_io_out_is_ret; // @[frontend.scala:625:34] wire _bpd_decoder1_1_io_out_is_call; // @[frontend.scala:625:34] wire [39:0] _bpd_decoder1_1_io_out_target; // @[frontend.scala:625:34] wire [2:0] _bpd_decoder1_1_io_out_cfi_type; // @[frontend.scala:625:34] wire _bpd_decoder1_1_io_out_sfb_offset_valid; // @[frontend.scala:625:34] wire [5:0] _bpd_decoder1_1_io_out_sfb_offset_bits; // @[frontend.scala:625:34] wire _bpd_decoder1_1_io_out_shadowable; // @[frontend.scala:625:34] wire _bpd_decoder0_1_io_out_is_ret; // @[frontend.scala:622:34] wire _bpd_decoder0_1_io_out_is_call; // @[frontend.scala:622:34] wire [39:0] _bpd_decoder0_1_io_out_target; // @[frontend.scala:622:34] wire [2:0] _bpd_decoder0_1_io_out_cfi_type; // @[frontend.scala:622:34] wire _bpd_decoder0_1_io_out_sfb_offset_valid; // @[frontend.scala:622:34] wire [5:0] _bpd_decoder0_1_io_out_sfb_offset_bits; // @[frontend.scala:622:34] wire _bpd_decoder0_1_io_out_shadowable; // @[frontend.scala:622:34] wire [31:0] _exp_inst1_rvc_exp_1_io_out_bits; // @[consts.scala:330:25] wire _exp_inst1_rvc_exp_1_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst0_rvc_exp_1_io_out_bits; // @[consts.scala:330:25] wire _exp_inst0_rvc_exp_1_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_2_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_2_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_1_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_1_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _bpd_decoder1_io_out_is_ret; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_is_call; // @[frontend.scala:625:34] wire [39:0] _bpd_decoder1_io_out_target; // @[frontend.scala:625:34] wire [2:0] _bpd_decoder1_io_out_cfi_type; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_sfb_offset_valid; // @[frontend.scala:625:34] wire [5:0] _bpd_decoder1_io_out_sfb_offset_bits; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_shadowable; // @[frontend.scala:625:34] wire _bpd_decoder0_io_out_is_ret; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_is_call; // @[frontend.scala:622:34] wire [39:0] _bpd_decoder0_io_out_target; // @[frontend.scala:622:34] wire [2:0] _bpd_decoder0_io_out_cfi_type; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_sfb_offset_valid; // @[frontend.scala:622:34] wire [5:0] _bpd_decoder0_io_out_sfb_offset_bits; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_shadowable; // @[frontend.scala:622:34] wire [31:0] _exp_inst1_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst1_rvc_exp_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst0_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst0_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _f3_bpd_resp_io_enq_ready; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_pc; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_0_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_1_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_2_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_3_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_4_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_5_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_6_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_7_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_io_enq_ready; // @[frontend.scala:516:11] wire _f3_io_deq_valid; // @[frontend.scala:516:11] wire [39:0] _f3_io_deq_bits_pc; // @[frontend.scala:516:11] wire [127:0] _f3_io_deq_bits_data; // @[frontend.scala:516:11] wire [7:0] _f3_io_deq_bits_mask; // @[frontend.scala:516:11] wire [1:0] _f3_io_deq_bits_fsrc; // @[frontend.scala:516:11] wire _tlb_io_resp_miss; // @[frontend.scala:337:19] wire [31:0] _tlb_io_resp_paddr; // @[frontend.scala:337:19] wire [39:0] _tlb_io_resp_gpa; // @[frontend.scala:337:19] wire _tlb_io_resp_pf_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_pf_inst; // @[frontend.scala:337:19] wire _tlb_io_resp_ae_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_ae_inst; // @[frontend.scala:337:19] wire _tlb_io_resp_ma_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_cacheable; // @[frontend.scala:337:19] wire _tlb_io_resp_prefetchable; // @[frontend.scala:337:19] wire [39:0] _ras_io_read_addr; // @[frontend.scala:333:19] wire _bpd_io_resp_f1_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_4_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_5_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_6_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_7_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_4_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_5_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_6_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_7_predicted_pc_bits; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_pc; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_4_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_5_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_6_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_7_predicted_pc_bits; // @[frontend.scala:331:19] wire [119:0] _bpd_io_resp_f3_meta_0; // @[frontend.scala:331:19] wire [119:0] _bpd_io_resp_f3_meta_1; // @[frontend.scala:331:19] wire _icache_io_resp_valid; // @[frontend.scala:299:26] wire [127:0] _icache_io_resp_bits_data; // @[frontend.scala:299:26] wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[frontend.scala:322:7] wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[frontend.scala:322:7] wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[frontend.scala:322:7] wire [127:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_ready_0 = io_cpu_fetchpacket_ready; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_ftq_idx_0 = io_cpu_get_pc_0_ftq_idx; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_ftq_idx_0 = io_cpu_get_pc_1_ftq_idx; // @[frontend.scala:322:7] wire io_cpu_status_debug_0 = io_cpu_status_debug; // @[frontend.scala:322:7] wire io_cpu_status_cease_0 = io_cpu_status_cease; // @[frontend.scala:322:7] wire io_cpu_status_wfi_0 = io_cpu_status_wfi; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_dprv_0 = io_cpu_status_dprv; // @[frontend.scala:322:7] wire io_cpu_status_dv_0 = io_cpu_status_dv; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_prv_0 = io_cpu_status_prv; // @[frontend.scala:322:7] wire io_cpu_status_v_0 = io_cpu_status_v; // @[frontend.scala:322:7] wire io_cpu_status_sd_0 = io_cpu_status_sd; // @[frontend.scala:322:7] wire io_cpu_status_mpv_0 = io_cpu_status_mpv; // @[frontend.scala:322:7] wire io_cpu_status_gva_0 = io_cpu_status_gva; // @[frontend.scala:322:7] wire io_cpu_status_tsr_0 = io_cpu_status_tsr; // @[frontend.scala:322:7] wire io_cpu_status_tw_0 = io_cpu_status_tw; // @[frontend.scala:322:7] wire io_cpu_status_tvm_0 = io_cpu_status_tvm; // @[frontend.scala:322:7] wire io_cpu_status_mxr_0 = io_cpu_status_mxr; // @[frontend.scala:322:7] wire io_cpu_status_sum_0 = io_cpu_status_sum; // @[frontend.scala:322:7] wire io_cpu_status_mprv_0 = io_cpu_status_mprv; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_fs_0 = io_cpu_status_fs; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_mpp_0 = io_cpu_status_mpp; // @[frontend.scala:322:7] wire io_cpu_status_spp_0 = io_cpu_status_spp; // @[frontend.scala:322:7] wire io_cpu_status_mpie_0 = io_cpu_status_mpie; // @[frontend.scala:322:7] wire io_cpu_status_spie_0 = io_cpu_status_spie; // @[frontend.scala:322:7] wire io_cpu_status_mie_0 = io_cpu_status_mie; // @[frontend.scala:322:7] wire io_cpu_status_sie_0 = io_cpu_status_sie; // @[frontend.scala:322:7] wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[frontend.scala:322:7] wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[frontend.scala:322:7] wire [15:0] io_cpu_brupdate_b1_resolve_mask_0 = io_cpu_brupdate_b1_resolve_mask; // @[frontend.scala:322:7] wire [15:0] io_cpu_brupdate_b1_mispredict_mask_0 = io_cpu_brupdate_b1_mispredict_mask; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_uopc_0 = io_cpu_brupdate_b2_uop_uopc; // @[frontend.scala:322:7] wire [31:0] io_cpu_brupdate_b2_uop_inst_0 = io_cpu_brupdate_b2_uop_inst; // @[frontend.scala:322:7] wire [31:0] io_cpu_brupdate_b2_uop_debug_inst_0 = io_cpu_brupdate_b2_uop_debug_inst; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_rvc_0 = io_cpu_brupdate_b2_uop_is_rvc; // @[frontend.scala:322:7] wire [39:0] io_cpu_brupdate_b2_uop_debug_pc_0 = io_cpu_brupdate_b2_uop_debug_pc; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_iq_type_0 = io_cpu_brupdate_b2_uop_iq_type; // @[frontend.scala:322:7] wire [9:0] io_cpu_brupdate_b2_uop_fu_code_0 = io_cpu_brupdate_b2_uop_fu_code; // @[frontend.scala:322:7] wire [3:0] io_cpu_brupdate_b2_uop_ctrl_br_type_0 = io_cpu_brupdate_b2_uop_ctrl_br_type; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_ctrl_op1_sel_0 = io_cpu_brupdate_b2_uop_ctrl_op1_sel; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_op2_sel_0 = io_cpu_brupdate_b2_uop_ctrl_op2_sel; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_imm_sel_0 = io_cpu_brupdate_b2_uop_ctrl_imm_sel; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ctrl_op_fcn_0 = io_cpu_brupdate_b2_uop_ctrl_op_fcn; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_fcn_dw_0 = io_cpu_brupdate_b2_uop_ctrl_fcn_dw; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_csr_cmd_0 = io_cpu_brupdate_b2_uop_ctrl_csr_cmd; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_load_0 = io_cpu_brupdate_b2_uop_ctrl_is_load; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_sta_0 = io_cpu_brupdate_b2_uop_ctrl_is_sta; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_std_0 = io_cpu_brupdate_b2_uop_ctrl_is_std; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_iw_state_0 = io_cpu_brupdate_b2_uop_iw_state; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_iw_p1_poisoned_0 = io_cpu_brupdate_b2_uop_iw_p1_poisoned; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_iw_p2_poisoned_0 = io_cpu_brupdate_b2_uop_iw_p2_poisoned; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_br_0 = io_cpu_brupdate_b2_uop_is_br; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_jalr_0 = io_cpu_brupdate_b2_uop_is_jalr; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_jal_0 = io_cpu_brupdate_b2_uop_is_jal; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_sfb_0 = io_cpu_brupdate_b2_uop_is_sfb; // @[frontend.scala:322:7] wire [15:0] io_cpu_brupdate_b2_uop_br_mask_0 = io_cpu_brupdate_b2_uop_br_mask; // @[frontend.scala:322:7] wire [3:0] io_cpu_brupdate_b2_uop_br_tag_0 = io_cpu_brupdate_b2_uop_br_tag; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ftq_idx_0 = io_cpu_brupdate_b2_uop_ftq_idx; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_edge_inst_0 = io_cpu_brupdate_b2_uop_edge_inst; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_pc_lob_0 = io_cpu_brupdate_b2_uop_pc_lob; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_taken_0 = io_cpu_brupdate_b2_uop_taken; // @[frontend.scala:322:7] wire [19:0] io_cpu_brupdate_b2_uop_imm_packed_0 = io_cpu_brupdate_b2_uop_imm_packed; // @[frontend.scala:322:7] wire [11:0] io_cpu_brupdate_b2_uop_csr_addr_0 = io_cpu_brupdate_b2_uop_csr_addr; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_rob_idx_0 = io_cpu_brupdate_b2_uop_rob_idx; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ldq_idx_0 = io_cpu_brupdate_b2_uop_ldq_idx; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_stq_idx_0 = io_cpu_brupdate_b2_uop_stq_idx; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_rxq_idx_0 = io_cpu_brupdate_b2_uop_rxq_idx; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_pdst_0 = io_cpu_brupdate_b2_uop_pdst; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_prs1_0 = io_cpu_brupdate_b2_uop_prs1; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_prs2_0 = io_cpu_brupdate_b2_uop_prs2; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_prs3_0 = io_cpu_brupdate_b2_uop_prs3; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ppred_0 = io_cpu_brupdate_b2_uop_ppred; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs1_busy_0 = io_cpu_brupdate_b2_uop_prs1_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs2_busy_0 = io_cpu_brupdate_b2_uop_prs2_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs3_busy_0 = io_cpu_brupdate_b2_uop_prs3_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ppred_busy_0 = io_cpu_brupdate_b2_uop_ppred_busy; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_stale_pdst_0 = io_cpu_brupdate_b2_uop_stale_pdst; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_exception_0 = io_cpu_brupdate_b2_uop_exception; // @[frontend.scala:322:7] wire [63:0] io_cpu_brupdate_b2_uop_exc_cause_0 = io_cpu_brupdate_b2_uop_exc_cause; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bypassable_0 = io_cpu_brupdate_b2_uop_bypassable; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_mem_cmd_0 = io_cpu_brupdate_b2_uop_mem_cmd; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_mem_size_0 = io_cpu_brupdate_b2_uop_mem_size; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_mem_signed_0 = io_cpu_brupdate_b2_uop_mem_signed; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_fence_0 = io_cpu_brupdate_b2_uop_is_fence; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_fencei_0 = io_cpu_brupdate_b2_uop_is_fencei; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_amo_0 = io_cpu_brupdate_b2_uop_is_amo; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_uses_ldq_0 = io_cpu_brupdate_b2_uop_uses_ldq; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_uses_stq_0 = io_cpu_brupdate_b2_uop_uses_stq; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_sys_pc2epc_0 = io_cpu_brupdate_b2_uop_is_sys_pc2epc; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_unique_0 = io_cpu_brupdate_b2_uop_is_unique; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_flush_on_commit_0 = io_cpu_brupdate_b2_uop_flush_on_commit; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ldst_is_rs1_0 = io_cpu_brupdate_b2_uop_ldst_is_rs1; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_ldst_0 = io_cpu_brupdate_b2_uop_ldst; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs1_0 = io_cpu_brupdate_b2_uop_lrs1; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs2_0 = io_cpu_brupdate_b2_uop_lrs2; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs3_0 = io_cpu_brupdate_b2_uop_lrs3; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ldst_val_0 = io_cpu_brupdate_b2_uop_ldst_val; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_dst_rtype_0 = io_cpu_brupdate_b2_uop_dst_rtype; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_lrs1_rtype_0 = io_cpu_brupdate_b2_uop_lrs1_rtype; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_lrs2_rtype_0 = io_cpu_brupdate_b2_uop_lrs2_rtype; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_frs3_en_0 = io_cpu_brupdate_b2_uop_frs3_en; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_fp_val_0 = io_cpu_brupdate_b2_uop_fp_val; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_fp_single_0 = io_cpu_brupdate_b2_uop_fp_single; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_pf_if_0 = io_cpu_brupdate_b2_uop_xcpt_pf_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_ae_if_0 = io_cpu_brupdate_b2_uop_xcpt_ae_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_ma_if_0 = io_cpu_brupdate_b2_uop_xcpt_ma_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bp_debug_if_0 = io_cpu_brupdate_b2_uop_bp_debug_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bp_xcpt_if_0 = io_cpu_brupdate_b2_uop_bp_xcpt_if; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_debug_fsrc_0 = io_cpu_brupdate_b2_uop_debug_fsrc; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_debug_tsrc_0 = io_cpu_brupdate_b2_uop_debug_tsrc; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_valid_0 = io_cpu_brupdate_b2_valid; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_mispredict_0 = io_cpu_brupdate_b2_mispredict; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_taken_0 = io_cpu_brupdate_b2_taken; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_cfi_type_0 = io_cpu_brupdate_b2_cfi_type; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_pc_sel_0 = io_cpu_brupdate_b2_pc_sel; // @[frontend.scala:322:7] wire [39:0] io_cpu_brupdate_b2_jalr_target_0 = io_cpu_brupdate_b2_jalr_target; // @[frontend.scala:322:7] wire [20:0] io_cpu_brupdate_b2_target_offset_0 = io_cpu_brupdate_b2_target_offset; // @[frontend.scala:322:7] wire io_cpu_redirect_flush_0 = io_cpu_redirect_flush; // @[frontend.scala:322:7] wire io_cpu_redirect_val_0 = io_cpu_redirect_val; // @[frontend.scala:322:7] wire [39:0] io_cpu_redirect_pc_0 = io_cpu_redirect_pc; // @[frontend.scala:322:7] wire [4:0] io_cpu_redirect_ftq_idx_0 = io_cpu_redirect_ftq_idx; // @[frontend.scala:322:7] wire [63:0] io_cpu_redirect_ghist_old_history_0 = io_cpu_redirect_ghist_old_history; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_current_saw_branch_not_taken_0 = io_cpu_redirect_ghist_current_saw_branch_not_taken; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_new_saw_branch_not_taken_0 = io_cpu_redirect_ghist_new_saw_branch_not_taken; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_new_saw_branch_taken_0 = io_cpu_redirect_ghist_new_saw_branch_taken; // @[frontend.scala:322:7] wire [4:0] io_cpu_redirect_ghist_ras_idx_0 = io_cpu_redirect_ghist_ras_idx; // @[frontend.scala:322:7] wire io_cpu_commit_valid_0 = io_cpu_commit_valid; // @[frontend.scala:322:7] wire [31:0] io_cpu_commit_bits_0 = io_cpu_commit_bits; // @[frontend.scala:322:7] wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[frontend.scala:322:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[frontend.scala:322:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[frontend.scala:322:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[frontend.scala:322:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[frontend.scala:322:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[frontend.scala:322:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[frontend.scala:322:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[frontend.scala:322:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[frontend.scala:322:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[frontend.scala:322:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[frontend.scala:322:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[frontend.scala:322:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[frontend.scala:322:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[frontend.scala:322:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[frontend.scala:322:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[frontend.scala:322:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[frontend.scala:322:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[frontend.scala:322:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[frontend.scala:322:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[frontend.scala:322:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[frontend.scala:322:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[frontend.scala:322:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[frontend.scala:322:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[frontend.scala:322:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[frontend.scala:322:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[frontend.scala:322:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[frontend.scala:322:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[frontend.scala:322:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[frontend.scala:322:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[frontend.scala:322:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[frontend.scala:322:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_uopc = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_rob_idx = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_prs1 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_prs2 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_prs3 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_stale_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_uopc = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_rob_idx = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_prs1 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_prs2 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_prs3 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_stale_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_uopc = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_rob_idx = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_prs1 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_prs2 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_prs3 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_stale_pdst = 7'h0; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_iq_type = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_op2_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_imm_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_csr_cmd = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_iq_type = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_op2_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_imm_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_csr_cmd = 3'h0; // @[frontend.scala:322:7] wire [9:0] io_cpu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0; // @[frontend.scala:322:7] wire [9:0] io_cpu_fetchpacket_bits_uops_1_bits_fu_code = 10'h0; // @[frontend.scala:322:7] wire [9:0] io_cpu_fetchpacket_bits_uops_2_bits_fu_code = 10'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_0_bits_br_tag = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_br_type = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_1_bits_br_tag = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_br_type = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_2_bits_br_tag = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_op1_sel = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_iw_state = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_rxq_idx = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_mem_size = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_dst_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_tsrc = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_op1_sel = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_iw_state = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_rxq_idx = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_mem_size = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_dst_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs1_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs2_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_tsrc = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] _offset_from_aligned_pc_T_8 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_13 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_18 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_28 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_33 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_38 = 2'h0; // @[frontend.scala:710:12] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ldq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_stq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ppred = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_op_fcn = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ldq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_stq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ppred = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_mem_cmd = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_op_fcn = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ldq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_stq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ppred = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_mem_cmd = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_ghist_ras_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_debug_ftq_idx_0 = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_debug_ftq_idx_1 = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_debug_ftq_idx_2 = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[frontend.scala:322:7] wire [4:0] _s0_ghist_WIRE_ras_idx = 5'h0; // @[frontend.scala:348:45] wire [4:0] _s0_ghist_WIRE_1_ras_idx = 5'h0; // @[frontend.scala:364:33] wire [4:0] f3_fetch_bundle_ftq_idx = 5'h0; // @[frontend.scala:569:29] wire auto_icache_master_out_a_bits_source = 1'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_source = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_br = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_fcn_dw = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_is_load = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_is_sta = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_is_std = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_iw_p1_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_iw_p2_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_br = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_jalr = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_jal = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_prs1_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_prs2_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_prs3_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ppred_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_exception = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_bypassable = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_mem_signed = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_fence = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_fencei = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_amo = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_uses_ldq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_uses_stq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_unique = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_flush_on_commit = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ldst_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_frs3_en = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_fp_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_fp_single = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_fcn_dw = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_is_load = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_is_sta = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_is_std = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_iw_p1_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_iw_p2_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_br = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_jalr = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_jal = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_prs1_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_prs2_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_prs3_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ppred_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_exception = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_bypassable = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_mem_signed = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_fence = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_fencei = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_amo = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_uses_ldq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_uses_stq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_sys_pc2epc = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_unique = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_flush_on_commit = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ldst_is_rs1 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ldst_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_frs3_en = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_fp_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_fp_single = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ma_if = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_mbe = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_sbe = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_ube = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_upie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_hie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_uie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_hv = 1'h0; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_hg = 1'h0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_mbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_sbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_ube = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_upie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_hie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_uie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtw = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_hu = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_spvp = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_spv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_gva = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_debug = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_cease = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_wfi = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_dv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_v = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sd = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mpv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_gva = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tsr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tw = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tvm = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mxr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sum = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mprv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_spp = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mpie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_ube = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_spie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_upie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_hie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_uie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[frontend.scala:322:7] wire _s0_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:348:45] wire _s0_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:348:45] wire _s0_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[frontend.scala:348:45] wire s0_replay_bpd_resp_lhist_0 = 1'h0; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_lhist_1 = 1'h0; // @[frontend.scala:354:32] wire _s0_ghist_WIRE_1_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:364:33] wire _s0_ghist_WIRE_1_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:364:33] wire _s0_ghist_WIRE_1_new_saw_branch_taken = 1'h0; // @[frontend.scala:364:33] wire f1_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire _f1_predicted_ghist_new_history_ras_idx_T = 1'h0; // @[frontend.scala:123:42] wire _f1_predicted_ghist_new_history_ras_idx_T_4 = 1'h0; // @[frontend.scala:124:42] wire f2_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire _f2_predicted_ghist_new_history_ras_idx_T = 1'h0; // @[frontend.scala:123:42] wire _f2_predicted_ghist_new_history_ras_idx_T_4 = 1'h0; // @[frontend.scala:124:42] wire f3_shadowed_mask_0 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_1 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_2 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_3 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_4 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_5 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_6 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_7 = 1'h0; // @[frontend.scala:568:30] wire f3_fetch_bundle_shadowed_mask_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_4 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_5 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_6 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_7 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_4 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_5 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_6 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_7 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_4 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_5 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_6 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_7 = 1'h0; // @[frontend.scala:569:29] wire _offset_from_aligned_pc_T_7 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_12 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_17 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_27 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_32 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_37 = 1'h0; // @[frontend.scala:710:31] wire f3_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire _f4_sfbs_T_17 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_35 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_53 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_71 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_89 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_107 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_125 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_143 = 1'h0; // @[frontend.scala:876:20] wire f4_sfbs_0 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_1 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_2 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_3 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_4 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_5 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_6 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_7 = 1'h0; // @[frontend.scala:875:24] wire _f4_sfb_valid_T = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_1 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_2 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_3 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_4 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_5 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_6 = 1'h0; // @[frontend.scala:890:38] wire f4_sfb_valid = 1'h0; // @[frontend.scala:890:43] wire [15:0] io_cpu_fetchpacket_bits_uops_0_bits_br_mask = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_cpu_fetchpacket_bits_uops_1_bits_br_mask = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_cpu_fetchpacket_bits_uops_2_bits_br_mask = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_1 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_2 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_3 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_2 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_3 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_3 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_15 = 16'h0; // @[util.scala:373:29] wire [19:0] io_cpu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[frontend.scala:322:7] wire [19:0] io_cpu_fetchpacket_bits_uops_1_bits_imm_packed = 20'h0; // @[frontend.scala:322:7] wire [19:0] io_cpu_fetchpacket_bits_uops_2_bits_imm_packed = 20'h0; // @[frontend.scala:322:7] wire [11:0] io_cpu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0; // @[frontend.scala:322:7] wire [11:0] io_cpu_fetchpacket_bits_uops_1_bits_csr_addr = 12'h0; // @[frontend.scala:322:7] wire [11:0] io_cpu_fetchpacket_bits_uops_2_bits_csr_addr = 12'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_fetchpacket_bits_uops_1_bits_exc_cause = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_fetchpacket_bits_uops_2_bits_exc_cause = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_get_pc_0_ghist_old_history = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] _s0_ghist_WIRE_old_history = 64'h0; // @[frontend.scala:348:45] wire [63:0] _s0_ghist_WIRE_1_old_history = 64'h0; // @[frontend.scala:364:33] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_ldst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_ldst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[frontend.scala:322:7] wire [31:0] io_cpu_status_isa = 32'h14112D; // @[frontend.scala:322:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[frontend.scala:322:7] wire [22:0] io_cpu_status_zero2 = 23'h0; // @[frontend.scala:322:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[frontend.scala:322:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[frontend.scala:322:7] wire [7:0] io_cpu_status_zero1 = 8'h0; // @[frontend.scala:322:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[frontend.scala:322:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[frontend.scala:322:7] wire [15:0] auto_icache_master_out_a_bits_mask = 16'hFFFF; // @[frontend.scala:322:7] wire [127:0] auto_icache_master_out_a_bits_data = 128'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_d_ready = 1'h1; // @[frontend.scala:322:7] wire io_ptw_req_bits_valid = 1'h1; // @[frontend.scala:322:7] wire valid = 1'h1; // @[frontend.scala:605:23] wire _bank_mask_0_T_3 = 1'h1; // @[frontend.scala:689:74] wire _f3_mask_0_T_3 = 1'h1; // @[frontend.scala:690:74] wire valid_4 = 1'h1; // @[frontend.scala:605:23] wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[frontend.scala:322:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [1:0] io_cpu_status_sxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_uxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] _lower_mask_T_1 = 2'h2; // @[OneHot.scala:58:35] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[frontend.scala:322:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[frontend.scala:322:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[frontend.scala:322:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[frontend.scala:322:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[frontend.scala:322:7] wire [2:0] _f4_sfb_idx_T = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_1 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_2 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_3 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_4 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_5 = 3'h7; // @[Mux.scala:50:70] wire [2:0] f4_sfb_idx = 3'h7; // @[Mux.scala:50:70] wire [7:0] _f1_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:180:81] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire [7:0] _f2_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:180:81] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire [7:0] _f3_io_enq_bits_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:180:81] wire [7:0] _f3_predicted_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_31 = 16'hFF00; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_22 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_23 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_24 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_25 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_26 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_27 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_28 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_29 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_30 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_21 = 16'hFE; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_20 = 16'hFC; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_19 = 16'hF8; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_18 = 16'hF0; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_17 = 16'hE0; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_16 = 16'hC0; // @[util.scala:373:45] wire [15:0] lower_mask = 16'h1; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_16 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_17 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_18 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_19 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_20 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_21 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_22 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_23 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_24 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_25 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_26 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_27 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_28 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_29 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_30 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_1 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_2 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_3 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_4 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_5 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_6 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_7 = 16'h1; // @[util.scala:373:29] wire [15:0] lower_mask_1 = 16'h2; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_1 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_2 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_3 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_4 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_5 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_6 = 16'h2; // @[util.scala:373:29] wire [15:0] lower_mask_2 = 16'h4; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_1 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_2 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_3 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_4 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_5 = 16'h4; // @[util.scala:373:29] wire [15:0] lower_mask_3 = 16'h8; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_1 = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_2 = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_3 = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_4 = 16'h8; // @[util.scala:373:29] wire [15:0] lower_mask_4 = 16'h10; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T = 16'h10; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_1 = 16'h10; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_2 = 16'h10; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_3 = 16'h10; // @[util.scala:373:29] wire [15:0] lower_mask_5 = 16'h20; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T = 16'h20; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_1 = 16'h20; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_2 = 16'h20; // @[util.scala:373:29] wire [15:0] lower_mask_6 = 16'h40; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T = 16'h40; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_1 = 16'h40; // @[util.scala:373:29] wire [15:0] lower_mask_7 = 16'h80; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T = 16'h80; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_31 = 16'hFF80; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_21 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_22 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_23 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_24 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_25 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_26 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_27 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_28 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_29 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_30 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_20 = 16'h7E; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_19 = 16'h7C; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_18 = 16'h78; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_17 = 16'h70; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_16 = 16'h60; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_31 = 16'hFFC0; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_20 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_21 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_22 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_23 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_24 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_25 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_26 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_27 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_28 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_29 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_30 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_19 = 16'h3E; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_18 = 16'h3C; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_17 = 16'h38; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_16 = 16'h30; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_31 = 16'hFFE0; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_19 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_20 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_21 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_22 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_23 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_24 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_25 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_26 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_27 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_28 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_29 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_30 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_18 = 16'h1E; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_17 = 16'h1C; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_16 = 16'h18; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_31 = 16'hFFF0; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_18 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_19 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_20 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_21 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_22 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_23 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_24 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_25 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_26 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_27 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_28 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_29 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_30 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_17 = 16'hE; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_16 = 16'hC; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_31 = 16'hFFF8; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_17 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_18 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_19 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_20 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_21 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_22 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_23 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_24 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_25 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_26 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_27 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_28 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_29 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_30 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_16 = 16'h6; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_31 = 16'hFFFC; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_16 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_17 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_18 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_19 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_20 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_21 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_22 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_23 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_24 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_25 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_26 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_27 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_28 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_29 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_30 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_31 = 16'hFFFE; // @[frontend.scala:722:45] wire [119:0] s0_replay_bpd_resp_meta_0 = 120'h0; // @[frontend.scala:354:32] wire [119:0] s0_replay_bpd_resp_meta_1 = 120'h0; // @[frontend.scala:354:32] wire [7:0] _lower_mask_T_7 = 8'h80; // @[OneHot.scala:58:35] wire [7:0] _lower_mask_T_6 = 8'h40; // @[OneHot.scala:58:35] wire [7:0] _lower_mask_T_5 = 8'h20; // @[OneHot.scala:58:35] wire [7:0] _lower_mask_T_4 = 8'h10; // @[OneHot.scala:58:35] wire [3:0] _lower_mask_T_2 = 4'h4; // @[OneHot.scala:58:35] wire [1:0] _lower_mask_T = 2'h1; // @[OneHot.scala:58:35] wire [3:0] _lower_mask_T_3 = 4'h8; // @[OneHot.scala:58:35] wire [3:0] _f1_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:180:56] wire [3:0] _f2_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:180:56] wire [3:0] _f3_io_enq_bits_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:180:56] wire s0_is_sfence = io_cpu_sfence_valid_0; // @[frontend.scala:322:7, :352:30] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire [31:0] auto_icache_master_out_a_bits_address_0; // @[frontend.scala:322:7] wire auto_icache_master_out_a_valid_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_0_bits_inst_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_inst_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_rvc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_pc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_sfb_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_edge_inst_0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_pc_lob_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_taken_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_valid_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_1_bits_inst_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_inst_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_rvc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_pc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_sfb_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_edge_inst_0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_pc_lob_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_taken_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_valid_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_2_bits_inst_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_inst_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_rvc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_pc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_sfb_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_edge_inst_0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_pc_lob_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_taken_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_valid_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_valid_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_idx_valid_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_0_entry_cfi_idx_bits_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_mispredicted_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_0_entry_cfi_type_0; // @[frontend.scala:322:7] wire [7:0] io_cpu_get_pc_0_entry_br_mask_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_is_call_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_is_ret_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_npc_plus4_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_entry_ras_top_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_entry_ras_idx_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_start_bank_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_com_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_next_val_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_next_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_idx_valid_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_1_entry_cfi_idx_bits_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_mispredicted_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_1_entry_cfi_type_0; // @[frontend.scala:322:7] wire [7:0] io_cpu_get_pc_1_entry_br_mask_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_is_call_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_is_ret_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_npc_plus4_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_entry_ras_top_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_entry_ras_idx_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_start_bank_0; // @[frontend.scala:322:7] wire [63:0] io_cpu_get_pc_1_ghist_old_history_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_new_saw_branch_not_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_new_saw_branch_taken_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_ghist_ras_idx_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_com_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_next_val_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_next_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_debug_fetch_pc_0_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_debug_fetch_pc_1_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_debug_fetch_pc_2_0; // @[frontend.scala:322:7] wire io_cpu_perf_acquire_0; // @[frontend.scala:322:7] wire io_cpu_perf_tlbMiss_0; // @[frontend.scala:322:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[frontend.scala:322:7] wire io_ptw_req_valid_0; // @[frontend.scala:322:7] assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_cpu_perf_tlbMiss_0 = _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire [39:0] s0_vpc; // @[frontend.scala:347:30] wire [63:0] s0_ghist_old_history; // @[frontend.scala:348:30] wire s0_ghist_current_saw_branch_not_taken; // @[frontend.scala:348:30] wire s0_ghist_new_saw_branch_not_taken; // @[frontend.scala:348:30] wire s0_ghist_new_saw_branch_taken; // @[frontend.scala:348:30] wire [4:0] s0_ghist_ras_idx; // @[frontend.scala:348:30] wire [1:0] s0_tsrc; // @[frontend.scala:349:30] wire s0_valid; // @[frontend.scala:350:30] wire s0_is_replay; // @[frontend.scala:351:30] wire s0_replay_resp_pf_ld; // @[frontend.scala:353:28] wire s0_replay_resp_pf_st; // @[frontend.scala:353:28] wire s0_replay_resp_pf_inst; // @[frontend.scala:353:28] wire s0_replay_resp_gf_ld; // @[frontend.scala:353:28] wire s0_replay_resp_gf_st; // @[frontend.scala:353:28] wire s0_replay_resp_gf_inst; // @[frontend.scala:353:28] wire s0_replay_resp_ae_ld; // @[frontend.scala:353:28] wire s0_replay_resp_ae_st; // @[frontend.scala:353:28] wire s0_replay_resp_ae_inst; // @[frontend.scala:353:28] wire s0_replay_resp_ma_ld; // @[frontend.scala:353:28] wire s0_replay_resp_ma_st; // @[frontend.scala:353:28] wire s0_replay_resp_ma_inst; // @[frontend.scala:353:28] wire s0_replay_resp_miss; // @[frontend.scala:353:28] wire [31:0] s0_replay_resp_paddr; // @[frontend.scala:353:28] wire [39:0] s0_replay_resp_gpa; // @[frontend.scala:353:28] wire s0_replay_resp_gpa_is_pte; // @[frontend.scala:353:28] wire s0_replay_resp_cacheable; // @[frontend.scala:353:28] wire s0_replay_resp_must_alloc; // @[frontend.scala:353:28] wire s0_replay_resp_prefetchable; // @[frontend.scala:353:28] wire [2:0] s0_replay_resp_size; // @[frontend.scala:353:28] wire [4:0] s0_replay_resp_cmd; // @[frontend.scala:353:28] wire s0_replay_bpd_resp_preds_0_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_0_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_1_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_2_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_3_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_4_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_5_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_6_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_7_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_is_jal; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_pc; // @[frontend.scala:354:32] wire [31:0] s0_replay_ppc; // @[frontend.scala:355:28] wire s0_s1_use_f3_bpd_resp; // @[frontend.scala:356:39] reg REG; // @[frontend.scala:361:16] wire _T_3 = REG & ~reset; // @[frontend.scala:361:{16,31,34}] reg [39:0] s1_vpc; // @[frontend.scala:379:29] reg s1_valid; // @[frontend.scala:380:29] reg [63:0] s1_ghist_old_history; // @[frontend.scala:381:29] reg s1_ghist_current_saw_branch_not_taken; // @[frontend.scala:381:29] reg s1_ghist_new_saw_branch_not_taken; // @[frontend.scala:381:29] reg s1_ghist_new_saw_branch_taken; // @[frontend.scala:381:29] reg [4:0] s1_ghist_ras_idx; // @[frontend.scala:381:29] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_8 = s1_ghist_ras_idx; // @[frontend.scala:124:31, :381:29] reg s1_is_replay; // @[frontend.scala:382:29] reg s1_is_sfence; // @[frontend.scala:383:29] wire f1_clear; // @[frontend.scala:384:30] reg [1:0] s1_tsrc; // @[frontend.scala:385:29] wire _tlb_io_req_valid_T = ~s1_is_replay; // @[frontend.scala:382:29, :386:41] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[frontend.scala:380:29, :386:{38,41}] wire _tlb_io_req_valid_T_2 = ~f1_clear; // @[frontend.scala:384:30, :386:58] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_1 & _tlb_io_req_valid_T_2; // @[frontend.scala:386:{38,55,58}] wire _tlb_io_req_valid_T_4 = _tlb_io_req_valid_T_3 \| s1_is_sfence; // @[frontend.scala:383:29, :386:{55,69}] reg tlb_io_sfence_REG_valid; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_rs1; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_rs2; // @[frontend.scala:393:35] reg [38:0] tlb_io_sfence_REG_bits_addr; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_asid; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_hv; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_hg; // @[frontend.scala:393:35] wire _s1_tlb_miss_T = ~s1_is_replay; // @[frontend.scala:382:29, :386:41, :396:21] wire s1_tlb_miss = _s1_tlb_miss_T & _tlb_io_resp_miss; // @[frontend.scala:337:19, :396:{21,35}] reg s1_tlb_resp_REG_miss; // @[frontend.scala:397:46] reg [31:0] s1_tlb_resp_REG_paddr; // @[frontend.scala:397:46] reg [39:0] s1_tlb_resp_REG_gpa; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gpa_is_pte; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_cacheable; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_must_alloc; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_prefetchable; // @[frontend.scala:397:46] reg [2:0] s1_tlb_resp_REG_size; // @[frontend.scala:397:46] reg [4:0] s1_tlb_resp_REG_cmd; // @[frontend.scala:397:46] wire s1_tlb_resp_miss = s1_is_replay ? s1_tlb_resp_REG_miss : _tlb_io_resp_miss; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [31:0] s1_tlb_resp_paddr = s1_is_replay ? s1_tlb_resp_REG_paddr : _tlb_io_resp_paddr; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [39:0] s1_tlb_resp_gpa = s1_is_replay ? s1_tlb_resp_REG_gpa : _tlb_io_resp_gpa; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_gpa_is_pte = s1_is_replay & s1_tlb_resp_REG_gpa_is_pte; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_pf_ld = s1_is_replay ? s1_tlb_resp_REG_pf_ld : _tlb_io_resp_pf_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_pf_st = s1_is_replay & s1_tlb_resp_REG_pf_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_pf_inst = s1_is_replay ? s1_tlb_resp_REG_pf_inst : _tlb_io_resp_pf_inst; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_gf_ld = s1_is_replay & s1_tlb_resp_REG_gf_ld; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_gf_st = s1_is_replay & s1_tlb_resp_REG_gf_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_gf_inst = s1_is_replay & s1_tlb_resp_REG_gf_inst; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ae_ld = s1_is_replay ? s1_tlb_resp_REG_ae_ld : _tlb_io_resp_ae_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ae_st = s1_is_replay & s1_tlb_resp_REG_ae_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ae_inst = s1_is_replay ? s1_tlb_resp_REG_ae_inst : _tlb_io_resp_ae_inst; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ma_ld = s1_is_replay ? s1_tlb_resp_REG_ma_ld : _tlb_io_resp_ma_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ma_st = s1_is_replay & s1_tlb_resp_REG_ma_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ma_inst = s1_is_replay & s1_tlb_resp_REG_ma_inst; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_cacheable = s1_is_replay ? s1_tlb_resp_REG_cacheable : _tlb_io_resp_cacheable; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_must_alloc = s1_is_replay & s1_tlb_resp_REG_must_alloc; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_prefetchable = s1_is_replay ? s1_tlb_resp_REG_prefetchable : _tlb_io_resp_prefetchable; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [2:0] s1_tlb_resp_size = s1_is_replay ? s1_tlb_resp_REG_size : 3'h4; // @[frontend.scala:382:29, :397:{24,46}] wire [4:0] s1_tlb_resp_cmd = s1_is_replay ? s1_tlb_resp_REG_cmd : 5'h0; // @[frontend.scala:382:29, :397:{24,46}] reg [31:0] s1_ppc_REG; // @[frontend.scala:398:42] wire [31:0] s1_ppc = s1_is_replay ? s1_ppc_REG : _tlb_io_resp_paddr; // @[frontend.scala:337:19, :382:29, :398:{20,42}] wire _icache_io_s1_kill_T = _tlb_io_resp_miss \| f1_clear; // @[frontend.scala:337:19, :384:30, :402:42] wire [2:0] f1_mask_idx = s1_vpc[3:1]; // @[package.scala:163:13] wire [1:0] f1_mask_shamt = f1_mask_idx[1:0]; // @[package.scala:163:13] wire [2:0] _f1_mask_end_mask_T = s1_vpc[5:3]; // @[frontend.scala:152:28, :379:29] wire [2:0] _f1_predicted_target_T_17 = s1_vpc[5:3]; // @[frontend.scala:152:28, :379:29] wire [2:0] _f1_predicted_ghist_ignore_second_bank_T = s1_vpc[5:3]; // @[frontend.scala:152:28, :379:29] wire _f1_mask_end_mask_T_1 = &_f1_mask_end_mask_T; // @[frontend.scala:152:{28,66}] wire _f1_mask_end_mask_T_2 = _f1_mask_end_mask_T_1; // @[frontend.scala:152:{21,66}] wire [7:0] f1_mask_end_mask = _f1_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:152:21, :180:25] wire [10:0] _f1_mask_T = 11'hFF << f1_mask_shamt; // @[package.scala:163:13] wire [10:0] f1_mask = {3'h0, _f1_mask_T[7:0] & f1_mask_end_mask}; // @[frontend.scala:180:25, :181:{31,40}] wire _f1_redirects_T = f1_mask[0]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_1 = s1_valid & _f1_redirects_T; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_2 = _f1_redirects_T_1 & _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_3 = _bpd_io_resp_f1_preds_0_is_br & _bpd_io_resp_f1_preds_0_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_4 = _bpd_io_resp_f1_preds_0_is_jal \| _f1_redirects_T_3; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_0 = _f1_redirects_T_2 & _f1_redirects_T_4; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_5 = f1_mask[1]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_6 = s1_valid & _f1_redirects_T_5; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_7 = _f1_redirects_T_6 & _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_8 = _bpd_io_resp_f1_preds_1_is_br & _bpd_io_resp_f1_preds_1_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_9 = _bpd_io_resp_f1_preds_1_is_jal \| _f1_redirects_T_8; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_1 = _f1_redirects_T_7 & _f1_redirects_T_9; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_10 = f1_mask[2]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_11 = s1_valid & _f1_redirects_T_10; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_12 = _f1_redirects_T_11 & _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_13 = _bpd_io_resp_f1_preds_2_is_br & _bpd_io_resp_f1_preds_2_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_14 = _bpd_io_resp_f1_preds_2_is_jal \| _f1_redirects_T_13; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_2 = _f1_redirects_T_12 & _f1_redirects_T_14; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_15 = f1_mask[3]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_16 = s1_valid & _f1_redirects_T_15; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_17 = _f1_redirects_T_16 & _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_18 = _bpd_io_resp_f1_preds_3_is_br & _bpd_io_resp_f1_preds_3_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_19 = _bpd_io_resp_f1_preds_3_is_jal \| _f1_redirects_T_18; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_3 = _f1_redirects_T_17 & _f1_redirects_T_19; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_20 = f1_mask[4]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_21 = s1_valid & _f1_redirects_T_20; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_22 = _f1_redirects_T_21 & _bpd_io_resp_f1_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_23 = _bpd_io_resp_f1_preds_4_is_br & _bpd_io_resp_f1_preds_4_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_24 = _bpd_io_resp_f1_preds_4_is_jal \| _f1_redirects_T_23; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_4 = _f1_redirects_T_22 & _f1_redirects_T_24; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_25 = f1_mask[5]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_26 = s1_valid & _f1_redirects_T_25; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_27 = _f1_redirects_T_26 & _bpd_io_resp_f1_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_28 = _bpd_io_resp_f1_preds_5_is_br & _bpd_io_resp_f1_preds_5_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_29 = _bpd_io_resp_f1_preds_5_is_jal \| _f1_redirects_T_28; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_5 = _f1_redirects_T_27 & _f1_redirects_T_29; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_30 = f1_mask[6]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_31 = s1_valid & _f1_redirects_T_30; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_32 = _f1_redirects_T_31 & _bpd_io_resp_f1_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_33 = _bpd_io_resp_f1_preds_6_is_br & _bpd_io_resp_f1_preds_6_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_34 = _bpd_io_resp_f1_preds_6_is_jal \| _f1_redirects_T_33; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_6 = _f1_redirects_T_32 & _f1_redirects_T_34; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_35 = f1_mask[7]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_36 = s1_valid & _f1_redirects_T_35; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_37 = _f1_redirects_T_36 & _bpd_io_resp_f1_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_38 = _bpd_io_resp_f1_preds_7_is_br & _bpd_io_resp_f1_preds_7_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_39 = _bpd_io_resp_f1_preds_7_is_jal \| _f1_redirects_T_38; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_7 = _f1_redirects_T_37 & _f1_redirects_T_39; // @[frontend.scala:406:{28,71}, :407:34] wire [2:0] _f1_redirect_idx_T = {2'h3, ~f1_redirects_6}; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_1 = f1_redirects_5 ? 3'h5 : _f1_redirect_idx_T; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_2 = f1_redirects_4 ? 3'h4 : _f1_redirect_idx_T_1; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_3 = f1_redirects_3 ? 3'h3 : _f1_redirect_idx_T_2; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_4 = f1_redirects_2 ? 3'h2 : _f1_redirect_idx_T_3; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_5 = f1_redirects_1 ? 3'h1 : _f1_redirect_idx_T_4; // @[Mux.scala:50:70] wire [2:0] f1_redirect_idx = f1_redirects_0 ? 3'h0 : _f1_redirect_idx_T_5; // @[Mux.scala:50:70] wire [2:0] f1_predicted_ghist_cfi_idx_fixed = f1_redirect_idx; // @[Mux.scala:50:70] wire _f1_do_redirect_T = f1_redirects_0 \| f1_redirects_1; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_1 = _f1_do_redirect_T \| f1_redirects_2; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_2 = _f1_do_redirect_T_1 \| f1_redirects_3; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_3 = _f1_do_redirect_T_2 \| f1_redirects_4; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_4 = _f1_do_redirect_T_3 \| f1_redirects_5; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_5 = _f1_do_redirect_T_4 \| f1_redirects_6; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_6 = _f1_do_redirect_T_5 \| f1_redirects_7; // @[frontend.scala:406:71, :411:45] wire f1_do_redirect = _f1_do_redirect_T_6; // @[frontend.scala:411:{45,50}] wire _f1_predicted_target_T = f1_redirect_idx == 3'h1; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_1 = _f1_predicted_target_T ? _bpd_io_resp_f1_preds_1_predicted_pc_bits : _bpd_io_resp_f1_preds_0_predicted_pc_bits; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_2 = f1_redirect_idx == 3'h2; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_3 = _f1_predicted_target_T_2 ? _bpd_io_resp_f1_preds_2_predicted_pc_bits : _f1_predicted_target_T_1; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_4 = f1_redirect_idx == 3'h3; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_5 = _f1_predicted_target_T_4 ? _bpd_io_resp_f1_preds_3_predicted_pc_bits : _f1_predicted_target_T_3; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_6 = f1_redirect_idx == 3'h4; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_7 = _f1_predicted_target_T_6 ? _bpd_io_resp_f1_preds_4_predicted_pc_bits : _f1_predicted_target_T_5; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_8 = f1_redirect_idx == 3'h5; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_9 = _f1_predicted_target_T_8 ? _bpd_io_resp_f1_preds_5_predicted_pc_bits : _f1_predicted_target_T_7; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_10 = f1_redirect_idx == 3'h6; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_11 = _f1_predicted_target_T_10 ? _bpd_io_resp_f1_preds_6_predicted_pc_bits : _f1_predicted_target_T_9; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_12 = &f1_redirect_idx; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_13 = _f1_predicted_target_T_12 ? _bpd_io_resp_f1_preds_7_predicted_pc_bits : _f1_predicted_target_T_11; // @[package.scala:39:{76,86}] wire [39:0] _f1_predicted_target_T_14 = ~s1_vpc; // @[frontend.scala:160:33, :379:29] wire [39:0] _f1_predicted_target_T_15 = {_f1_predicted_target_T_14[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _f1_predicted_target_T_16 = ~_f1_predicted_target_T_15; // @[frontend.scala:160:{31,39}] wire _f1_predicted_target_T_18 = &_f1_predicted_target_T_17; // @[frontend.scala:152:{28,66}] wire _f1_predicted_target_T_19 = _f1_predicted_target_T_18; // @[frontend.scala:152:{21,66}] wire [4:0] _f1_predicted_target_T_20 = _f1_predicted_target_T_19 ? 5'h8 : 5'h10; // @[frontend.scala:152:21, :170:28] wire [40:0] _f1_predicted_target_T_21 = {1'h0, _f1_predicted_target_T_16} + {36'h0, _f1_predicted_target_T_20}; // @[frontend.scala:160:31, :170:{23,28}] wire [39:0] _f1_predicted_target_T_22 = _f1_predicted_target_T_21[39:0]; // @[frontend.scala:170:23] wire [39:0] f1_predicted_target = f1_do_redirect ? _f1_predicted_target_T_13 : _f1_predicted_target_T_22; // @[package.scala:39:76] wire _f1_predicted_ghist_T = _bpd_io_resp_f1_preds_0_is_br & _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_1 = _bpd_io_resp_f1_preds_1_is_br & _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_2 = _bpd_io_resp_f1_preds_2_is_br & _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_3 = _bpd_io_resp_f1_preds_3_is_br & _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_4 = _bpd_io_resp_f1_preds_4_is_br & _bpd_io_resp_f1_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_5 = _bpd_io_resp_f1_preds_5_is_br & _bpd_io_resp_f1_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_6 = _bpd_io_resp_f1_preds_6_is_br & _bpd_io_resp_f1_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_7 = _bpd_io_resp_f1_preds_7_is_br & _bpd_io_resp_f1_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire [1:0] f1_predicted_ghist_lo_lo = {_f1_predicted_ghist_T_1, _f1_predicted_ghist_T}; // @[package.scala:45:27] wire [1:0] f1_predicted_ghist_lo_hi = {_f1_predicted_ghist_T_3, _f1_predicted_ghist_T_2}; // @[package.scala:45:27] wire [3:0] f1_predicted_ghist_lo = {f1_predicted_ghist_lo_hi, f1_predicted_ghist_lo_lo}; // @[package.scala:45:27] wire [1:0] f1_predicted_ghist_hi_lo = {_f1_predicted_ghist_T_5, _f1_predicted_ghist_T_4}; // @[package.scala:45:27] wire [1:0] f1_predicted_ghist_hi_hi = {_f1_predicted_ghist_T_7, _f1_predicted_ghist_T_6}; // @[package.scala:45:27] wire [3:0] f1_predicted_ghist_hi = {f1_predicted_ghist_hi_hi, f1_predicted_ghist_hi_lo}; // @[package.scala:45:27] wire [7:0] _f1_predicted_ghist_T_8 = {f1_predicted_ghist_hi, f1_predicted_ghist_lo}; // @[package.scala:45:27] wire [10:0] _f1_predicted_ghist_T_9 = {3'h0, f1_mask[7:0] & _f1_predicted_ghist_T_8}; // @[package.scala:45:27] wire [7:0] _GEN = {{_bpd_io_resp_f1_preds_7_taken}, {_bpd_io_resp_f1_preds_6_taken}, {_bpd_io_resp_f1_preds_5_taken}, {_bpd_io_resp_f1_preds_4_taken}, {_bpd_io_resp_f1_preds_3_taken}, {_bpd_io_resp_f1_preds_2_taken}, {_bpd_io_resp_f1_preds_1_taken}, {_bpd_io_resp_f1_preds_0_taken}}; // @[frontend.scala:331:19, :419:46] wire [7:0] _GEN_0 = {{_bpd_io_resp_f1_preds_7_is_br}, {_bpd_io_resp_f1_preds_6_is_br}, {_bpd_io_resp_f1_preds_5_is_br}, {_bpd_io_resp_f1_preds_4_is_br}, {_bpd_io_resp_f1_preds_3_is_br}, {_bpd_io_resp_f1_preds_2_is_br}, {_bpd_io_resp_f1_preds_1_is_br}, {_bpd_io_resp_f1_preds_0_is_br}}; // @[frontend.scala:331:19, :419:46] wire _f1_predicted_ghist_T_10 = _GEN[f1_redirect_idx] & f1_do_redirect; // @[Mux.scala:50:70] wire [7:0] f1_predicted_ghist_cfi_idx_oh = 8'h1 << f1_predicted_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T = f1_predicted_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] f1_predicted_ghist_old_history; // @[frontend.scala:87:27] wire f1_predicted_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire f1_predicted_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] f1_predicted_ghist_ras_idx; // @[frontend.scala:87:27] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_1 = {1'h0, f1_predicted_ghist_cfi_idx_oh[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_2 = {2'h0, f1_predicted_ghist_cfi_idx_oh[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_3 = {3'h0, f1_predicted_ghist_cfi_idx_oh[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_4 = {4'h0, f1_predicted_ghist_cfi_idx_oh[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_5 = {5'h0, f1_predicted_ghist_cfi_idx_oh[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_6 = {6'h0, f1_predicted_ghist_cfi_idx_oh[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_7 = {7'h0, f1_predicted_ghist_cfi_idx_oh[7]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_8 = _f1_predicted_ghist_not_taken_branches_T \| _f1_predicted_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_9 = _f1_predicted_ghist_not_taken_branches_T_8 \| _f1_predicted_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_10 = _f1_predicted_ghist_not_taken_branches_T_9 \| _f1_predicted_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_11 = _f1_predicted_ghist_not_taken_branches_T_10 \| _f1_predicted_ghist_not_taken_branches_T_4; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_12 = _f1_predicted_ghist_not_taken_branches_T_11 \| _f1_predicted_ghist_not_taken_branches_T_5; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_13 = _f1_predicted_ghist_not_taken_branches_T_12 \| _f1_predicted_ghist_not_taken_branches_T_6; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_14 = _f1_predicted_ghist_not_taken_branches_T_13 \| _f1_predicted_ghist_not_taken_branches_T_7; // @[util.scala:373:{29,45}] wire _f1_predicted_ghist_not_taken_branches_T_15 = _GEN_0[f1_redirect_idx] & _f1_predicted_ghist_T_10; // @[Mux.scala:50:70] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_16 = _f1_predicted_ghist_not_taken_branches_T_15 ? f1_predicted_ghist_cfi_idx_oh : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_17 = ~_f1_predicted_ghist_not_taken_branches_T_16; // @[frontend.scala:90:{69,73}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_18 = _f1_predicted_ghist_not_taken_branches_T_14 & _f1_predicted_ghist_not_taken_branches_T_17; // @[util.scala:373:45] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_20 = f1_do_redirect ? _f1_predicted_ghist_not_taken_branches_T_18 : 8'hFF; // @[frontend.scala:89:44, :90:67, :411:50] wire [10:0] f1_predicted_ghist_not_taken_branches = {3'h0, _f1_predicted_ghist_T_9[7:0] & _f1_predicted_ghist_not_taken_branches_T_20}; // @[frontend.scala:89:{39,44}, :418:72] wire [64:0] _GEN_1 = {s1_ghist_old_history, 1'h0}; // @[frontend.scala:67:75, :381:29] wire [64:0] _f1_predicted_ghist_base_T; // @[frontend.scala:67:75] assign _f1_predicted_ghist_base_T = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_base_T_2; // @[frontend.scala:68:75] assign _f1_predicted_ghist_base_T_2 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_2; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_2 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_6; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T_6 = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_8; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_8 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_13; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T_13 = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_15; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_15 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_19; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T_19 = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_21; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_21 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_base_T_1 = {_f1_predicted_ghist_base_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _GEN_2 = {1'h0, s1_ghist_old_history}; // @[frontend.scala:68:12, :381:29] wire [64:0] _f1_predicted_ghist_base_T_3 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_base_T_2 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] f1_predicted_ghist_base = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_base_T_1 : _f1_predicted_ghist_base_T_3; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire _GEN_3 = f1_do_redirect & _f1_predicted_ghist_T_10; // @[frontend.scala:104:37, :411:50, :419:46] wire _f1_predicted_ghist_cfi_in_bank_0_T; // @[frontend.scala:104:37] assign _f1_predicted_ghist_cfi_in_bank_0_T = _GEN_3; // @[frontend.scala:104:37] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1; // @[frontend.scala:119:59] assign _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1 = _GEN_3; // @[frontend.scala:104:37, :119:59] wire _f1_predicted_ghist_cfi_in_bank_0_T_1 = ~(f1_predicted_ghist_cfi_idx_fixed[2]); // @[frontend.scala:85:32, :104:67] wire f1_predicted_ghist_cfi_in_bank_0 = _f1_predicted_ghist_cfi_in_bank_0_T & _f1_predicted_ghist_cfi_in_bank_0_T_1; // @[frontend.scala:104:{37,50,67}] wire _f1_predicted_ghist_ignore_second_bank_T_1 = &_f1_predicted_ghist_ignore_second_bank_T; // @[frontend.scala:152:{28,66}] wire _f1_predicted_ghist_ignore_second_bank_T_2 = _f1_predicted_ghist_ignore_second_bank_T_1; // @[frontend.scala:152:{21,66}] wire f1_predicted_ghist_ignore_second_bank = f1_predicted_ghist_cfi_in_bank_0 \| _f1_predicted_ghist_ignore_second_bank_T_2; // @[frontend.scala:104:50, :105:46, :152:21] wire [3:0] _f1_predicted_ghist_first_bank_saw_not_taken_T = f1_predicted_ghist_not_taken_branches[3:0]; // @[frontend.scala:89:39, :107:56] wire _f1_predicted_ghist_first_bank_saw_not_taken_T_1 = \|_f1_predicted_ghist_first_bank_saw_not_taken_T; // @[frontend.scala:107:{56,72}] wire f1_predicted_ghist_first_bank_saw_not_taken = _f1_predicted_ghist_first_bank_saw_not_taken_T_1 \| s1_ghist_current_saw_branch_not_taken; // @[frontend.scala:107:{72,80}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_1 = {_f1_predicted_ghist_new_history_old_history_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_3 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_2 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_4 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_1 : _f1_predicted_ghist_new_history_old_history_T_3; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire _GEN_4 = _GEN_0[f1_redirect_idx] & f1_predicted_ghist_cfi_in_bank_0; // @[Mux.scala:50:70] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T; // @[frontend.scala:112:59] assign _f1_predicted_ghist_new_history_new_saw_branch_taken_T = _GEN_4; // @[frontend.scala:112:59] wire _f1_predicted_ghist_new_history_old_history_T_5; // @[frontend.scala:114:50] assign _f1_predicted_ghist_new_history_old_history_T_5 = _GEN_4; // @[frontend.scala:112:59, :114:50] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_7 = {_f1_predicted_ghist_new_history_old_history_T_6[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_9 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_8 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_10 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_7 : _f1_predicted_ghist_new_history_old_history_T_9; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_11 = {_f1_predicted_ghist_new_history_old_history_T_10, 1'h0}; // @[frontend.scala:67:12, :114:110] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_12 = {_f1_predicted_ghist_new_history_old_history_T_11[65:1], 1'h1}; // @[frontend.scala:114:{110,115}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_14 = {_f1_predicted_ghist_new_history_old_history_T_13[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_16 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_15 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_17 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_14 : _f1_predicted_ghist_new_history_old_history_T_16; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_18 = {_f1_predicted_ghist_new_history_old_history_T_17, 1'h0}; // @[frontend.scala:67:12, :115:110] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_20 = {_f1_predicted_ghist_new_history_old_history_T_19[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_22 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_21 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_23 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_20 : _f1_predicted_ghist_new_history_old_history_T_22; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_24 = f1_predicted_ghist_first_bank_saw_not_taken ? _f1_predicted_ghist_new_history_old_history_T_18 : {1'h0, _f1_predicted_ghist_new_history_old_history_T_23}; // @[frontend.scala:67:12, :107:80, :115:{39,110}] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_25 = _f1_predicted_ghist_new_history_old_history_T_5 ? _f1_predicted_ghist_new_history_old_history_T_12 : _f1_predicted_ghist_new_history_old_history_T_24; // @[frontend.scala:114:{39,50,115}, :115:39] assign f1_predicted_ghist_old_history = f1_predicted_ghist_ignore_second_bank ? _f1_predicted_ghist_new_history_old_history_T_4[63:0] : _f1_predicted_ghist_new_history_old_history_T_25[63:0]; // @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}] wire [3:0] _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T = f1_predicted_ghist_not_taken_branches[7:4]; // @[frontend.scala:89:39, :118:67] wire _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = \|_f1_predicted_ghist_new_history_new_saw_branch_not_taken_T; // @[frontend.scala:118:{67,92}] assign f1_predicted_ghist_new_saw_branch_not_taken = f1_predicted_ghist_ignore_second_bank ? f1_predicted_ghist_first_bank_saw_not_taken : _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1; // @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_2 = _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1 & _GEN_0[f1_redirect_idx]; // @[Mux.scala:50:70] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3 = ~f1_predicted_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :119:88] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4 = _f1_predicted_ghist_new_history_new_saw_branch_taken_T_2 & _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3; // @[frontend.scala:119:{72,85,88}] assign f1_predicted_ghist_new_saw_branch_taken = f1_predicted_ghist_ignore_second_bank ? _f1_predicted_ghist_new_history_new_saw_branch_taken_T : _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4; // @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}] wire [5:0] _GEN_5 = {1'h0, s1_ghist_ras_idx}; // @[util.scala:203:14] wire [5:0] _f1_predicted_ghist_new_history_ras_idx_T_1 = _GEN_5 + 6'h1; // @[util.scala:203:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_2 = _f1_predicted_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_3 = _f1_predicted_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _f1_predicted_ghist_new_history_ras_idx_T_5 = _GEN_5 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_6 = _f1_predicted_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_7 = _f1_predicted_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] assign _f1_predicted_ghist_new_history_ras_idx_T_9 = _f1_predicted_ghist_new_history_ras_idx_T_8; // @[frontend.scala:123:31, :124:31] assign f1_predicted_ghist_ras_idx = _f1_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire _T_5 = s1_valid & ~s1_tlb_miss; // @[frontend.scala:380:29, :396:35, :427:{18,21}] wire _s0_valid_T = s1_tlb_resp_ae_inst \| s1_tlb_resp_pf_inst; // @[frontend.scala:397:24, :429:43] wire _s0_valid_T_1 = ~_s0_valid_T; // @[frontend.scala:429:{21,43}] wire _s2_valid_T = ~f1_clear; // @[frontend.scala:384:30, :386:58, :440:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[frontend.scala:380:29, :440:{35,38}] reg s2_valid; // @[frontend.scala:440:25] reg [39:0] s2_vpc; // @[frontend.scala:441:25] reg [63:0] s2_ghist_old_history; // @[frontend.scala:442:21] reg s2_ghist_current_saw_branch_not_taken; // @[frontend.scala:442:21] reg s2_ghist_new_saw_branch_not_taken; // @[frontend.scala:442:21] reg s2_ghist_new_saw_branch_taken; // @[frontend.scala:442:21] reg [4:0] s2_ghist_ras_idx; // @[frontend.scala:442:21] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_8 = s2_ghist_ras_idx; // @[frontend.scala:124:31, :442:21] reg [31:0] s2_ppc; // @[frontend.scala:444:24] assign s0_replay_ppc = s2_ppc; // @[frontend.scala:355:28, :444:24] reg [1:0] s2_tsrc; // @[frontend.scala:445:24] wire [1:0] s2_fsrc; // @[frontend.scala:446:25] wire f2_clear; // @[frontend.scala:447:26] reg s2_tlb_resp_miss; // @[frontend.scala:448:28] assign s0_replay_resp_miss = s2_tlb_resp_miss; // @[frontend.scala:353:28, :448:28] reg [31:0] s2_tlb_resp_paddr; // @[frontend.scala:448:28] assign s0_replay_resp_paddr = s2_tlb_resp_paddr; // @[frontend.scala:353:28, :448:28] reg [39:0] s2_tlb_resp_gpa; // @[frontend.scala:448:28] assign s0_replay_resp_gpa = s2_tlb_resp_gpa; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gpa_is_pte; // @[frontend.scala:448:28] assign s0_replay_resp_gpa_is_pte = s2_tlb_resp_gpa_is_pte; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_ld; // @[frontend.scala:448:28] assign s0_replay_resp_pf_ld = s2_tlb_resp_pf_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_st; // @[frontend.scala:448:28] assign s0_replay_resp_pf_st = s2_tlb_resp_pf_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_inst; // @[frontend.scala:448:28] assign s0_replay_resp_pf_inst = s2_tlb_resp_pf_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_ld; // @[frontend.scala:448:28] assign s0_replay_resp_gf_ld = s2_tlb_resp_gf_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_st; // @[frontend.scala:448:28] assign s0_replay_resp_gf_st = s2_tlb_resp_gf_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_inst; // @[frontend.scala:448:28] assign s0_replay_resp_gf_inst = s2_tlb_resp_gf_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_ld; // @[frontend.scala:448:28] assign s0_replay_resp_ae_ld = s2_tlb_resp_ae_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_st; // @[frontend.scala:448:28] assign s0_replay_resp_ae_st = s2_tlb_resp_ae_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_inst; // @[frontend.scala:448:28] assign s0_replay_resp_ae_inst = s2_tlb_resp_ae_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_ld; // @[frontend.scala:448:28] assign s0_replay_resp_ma_ld = s2_tlb_resp_ma_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_st; // @[frontend.scala:448:28] assign s0_replay_resp_ma_st = s2_tlb_resp_ma_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_inst; // @[frontend.scala:448:28] assign s0_replay_resp_ma_inst = s2_tlb_resp_ma_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_cacheable; // @[frontend.scala:448:28] assign s0_replay_resp_cacheable = s2_tlb_resp_cacheable; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_must_alloc; // @[frontend.scala:448:28] assign s0_replay_resp_must_alloc = s2_tlb_resp_must_alloc; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_prefetchable; // @[frontend.scala:448:28] assign s0_replay_resp_prefetchable = s2_tlb_resp_prefetchable; // @[frontend.scala:353:28, :448:28] reg [2:0] s2_tlb_resp_size; // @[frontend.scala:448:28] assign s0_replay_resp_size = s2_tlb_resp_size; // @[frontend.scala:353:28, :448:28] reg [4:0] s2_tlb_resp_cmd; // @[frontend.scala:448:28] assign s0_replay_resp_cmd = s2_tlb_resp_cmd; // @[frontend.scala:353:28, :448:28] reg s2_tlb_miss; // @[frontend.scala:449:28] reg s2_is_replay_REG; // @[frontend.scala:450:29] wire s2_is_replay = s2_is_replay_REG & s2_valid; // @[frontend.scala:440:25, :450:{29,44}] wire _GEN_6 = s2_tlb_resp_ae_inst \| s2_tlb_resp_pf_inst; // @[frontend.scala:448:28, :451:50] wire _s2_xcpt_T; // @[frontend.scala:451:50] assign _s2_xcpt_T = _GEN_6; // @[frontend.scala:451:50] wire _s0_valid_T_7; // @[frontend.scala:499:46] assign _s0_valid_T_7 = _GEN_6; // @[frontend.scala:451:50, :499:46] wire _f3_io_enq_valid_T_2; // @[frontend.scala:529:52] assign _f3_io_enq_valid_T_2 = _GEN_6; // @[frontend.scala:451:50, :529:52] wire _s2_xcpt_T_1 = s2_valid & _s2_xcpt_T; // @[frontend.scala:440:25, :451:{26,50}] wire _s2_xcpt_T_2 = ~s2_is_replay; // @[frontend.scala:450:44, :451:77] wire s2_xcpt = _s2_xcpt_T_1 & _s2_xcpt_T_2; // @[frontend.scala:451:{26,74,77}] wire f3_ready; // @[frontend.scala:452:22] wire [2:0] f2_mask_idx = s2_vpc[3:1]; // @[package.scala:163:13] wire [2:0] f3_io_enq_bits_mask_idx = s2_vpc[3:1]; // @[package.scala:163:13] wire [1:0] f2_mask_shamt = f2_mask_idx[1:0]; // @[package.scala:163:13] wire [2:0] _f2_mask_end_mask_T = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire [2:0] _f2_predicted_target_T_17 = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire [2:0] _f2_predicted_ghist_ignore_second_bank_T = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire [2:0] _f3_io_enq_bits_mask_end_mask_T = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire _f2_mask_end_mask_T_1 = &_f2_mask_end_mask_T; // @[frontend.scala:152:{28,66}] wire _f2_mask_end_mask_T_2 = _f2_mask_end_mask_T_1; // @[frontend.scala:152:{21,66}] wire [7:0] f2_mask_end_mask = _f2_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:152:21, :180:25] wire [10:0] _f2_mask_T = 11'hFF << f2_mask_shamt; // @[package.scala:163:13] wire [10:0] f2_mask = {3'h0, _f2_mask_T[7:0] & f2_mask_end_mask}; // @[frontend.scala:180:25, :181:{31,40}] wire _f2_redirects_T = f2_mask[0]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_1 = s2_valid & _f2_redirects_T; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_2 = _f2_redirects_T_1 & _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_3 = _bpd_io_resp_f2_preds_0_is_br & _bpd_io_resp_f2_preds_0_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_4 = _bpd_io_resp_f2_preds_0_is_jal \| _f2_redirects_T_3; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_0 = _f2_redirects_T_2 & _f2_redirects_T_4; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_5 = f2_mask[1]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_6 = s2_valid & _f2_redirects_T_5; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_7 = _f2_redirects_T_6 & _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_8 = _bpd_io_resp_f2_preds_1_is_br & _bpd_io_resp_f2_preds_1_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_9 = _bpd_io_resp_f2_preds_1_is_jal \| _f2_redirects_T_8; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_1 = _f2_redirects_T_7 & _f2_redirects_T_9; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_10 = f2_mask[2]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_11 = s2_valid & _f2_redirects_T_10; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_12 = _f2_redirects_T_11 & _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_13 = _bpd_io_resp_f2_preds_2_is_br & _bpd_io_resp_f2_preds_2_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_14 = _bpd_io_resp_f2_preds_2_is_jal \| _f2_redirects_T_13; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_2 = _f2_redirects_T_12 & _f2_redirects_T_14; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_15 = f2_mask[3]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_16 = s2_valid & _f2_redirects_T_15; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_17 = _f2_redirects_T_16 & _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_18 = _bpd_io_resp_f2_preds_3_is_br & _bpd_io_resp_f2_preds_3_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_19 = _bpd_io_resp_f2_preds_3_is_jal \| _f2_redirects_T_18; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_3 = _f2_redirects_T_17 & _f2_redirects_T_19; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_20 = f2_mask[4]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_21 = s2_valid & _f2_redirects_T_20; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_22 = _f2_redirects_T_21 & _bpd_io_resp_f2_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_23 = _bpd_io_resp_f2_preds_4_is_br & _bpd_io_resp_f2_preds_4_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_24 = _bpd_io_resp_f2_preds_4_is_jal \| _f2_redirects_T_23; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_4 = _f2_redirects_T_22 & _f2_redirects_T_24; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_25 = f2_mask[5]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_26 = s2_valid & _f2_redirects_T_25; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_27 = _f2_redirects_T_26 & _bpd_io_resp_f2_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_28 = _bpd_io_resp_f2_preds_5_is_br & _bpd_io_resp_f2_preds_5_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_29 = _bpd_io_resp_f2_preds_5_is_jal \| _f2_redirects_T_28; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_5 = _f2_redirects_T_27 & _f2_redirects_T_29; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_30 = f2_mask[6]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_31 = s2_valid & _f2_redirects_T_30; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_32 = _f2_redirects_T_31 & _bpd_io_resp_f2_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_33 = _bpd_io_resp_f2_preds_6_is_br & _bpd_io_resp_f2_preds_6_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_34 = _bpd_io_resp_f2_preds_6_is_jal \| _f2_redirects_T_33; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_6 = _f2_redirects_T_32 & _f2_redirects_T_34; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_35 = f2_mask[7]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_36 = s2_valid & _f2_redirects_T_35; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_37 = _f2_redirects_T_36 & _bpd_io_resp_f2_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_38 = _bpd_io_resp_f2_preds_7_is_br & _bpd_io_resp_f2_preds_7_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_39 = _bpd_io_resp_f2_preds_7_is_jal \| _f2_redirects_T_38; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_7 = _f2_redirects_T_37 & _f2_redirects_T_39; // @[frontend.scala:459:{28,71}, :460:34] wire [2:0] _f2_redirect_idx_T = {2'h3, ~f2_redirects_6}; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_1 = f2_redirects_5 ? 3'h5 : _f2_redirect_idx_T; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_2 = f2_redirects_4 ? 3'h4 : _f2_redirect_idx_T_1; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_3 = f2_redirects_3 ? 3'h3 : _f2_redirect_idx_T_2; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_4 = f2_redirects_2 ? 3'h2 : _f2_redirect_idx_T_3; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_5 = f2_redirects_1 ? 3'h1 : _f2_redirect_idx_T_4; // @[Mux.scala:50:70] wire [2:0] f2_redirect_idx = f2_redirects_0 ? 3'h0 : _f2_redirect_idx_T_5; // @[Mux.scala:50:70] wire [2:0] f2_predicted_ghist_cfi_idx_fixed = f2_redirect_idx; // @[Mux.scala:50:70] wire _f2_do_redirect_T = f2_redirects_0 \| f2_redirects_1; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_1 = _f2_do_redirect_T \| f2_redirects_2; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_2 = _f2_do_redirect_T_1 \| f2_redirects_3; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_3 = _f2_do_redirect_T_2 \| f2_redirects_4; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_4 = _f2_do_redirect_T_3 \| f2_redirects_5; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_5 = _f2_do_redirect_T_4 \| f2_redirects_6; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_6 = _f2_do_redirect_T_5 \| f2_redirects_7; // @[frontend.scala:459:71, :465:45] wire f2_do_redirect = _f2_do_redirect_T_6; // @[frontend.scala:465:{45,50}] wire _f2_predicted_target_T = f2_redirect_idx == 3'h1; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_1 = _f2_predicted_target_T ? _bpd_io_resp_f2_preds_1_predicted_pc_bits : _bpd_io_resp_f2_preds_0_predicted_pc_bits; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_2 = f2_redirect_idx == 3'h2; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_3 = _f2_predicted_target_T_2 ? _bpd_io_resp_f2_preds_2_predicted_pc_bits : _f2_predicted_target_T_1; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_4 = f2_redirect_idx == 3'h3; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_5 = _f2_predicted_target_T_4 ? _bpd_io_resp_f2_preds_3_predicted_pc_bits : _f2_predicted_target_T_3; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_6 = f2_redirect_idx == 3'h4; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_7 = _f2_predicted_target_T_6 ? _bpd_io_resp_f2_preds_4_predicted_pc_bits : _f2_predicted_target_T_5; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_8 = f2_redirect_idx == 3'h5; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_9 = _f2_predicted_target_T_8 ? _bpd_io_resp_f2_preds_5_predicted_pc_bits : _f2_predicted_target_T_7; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_10 = f2_redirect_idx == 3'h6; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_11 = _f2_predicted_target_T_10 ? _bpd_io_resp_f2_preds_6_predicted_pc_bits : _f2_predicted_target_T_9; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_12 = &f2_redirect_idx; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_13 = _f2_predicted_target_T_12 ? _bpd_io_resp_f2_preds_7_predicted_pc_bits : _f2_predicted_target_T_11; // @[package.scala:39:{76,86}] wire [39:0] _f2_predicted_target_T_14 = ~s2_vpc; // @[frontend.scala:160:33, :441:25] wire [39:0] _f2_predicted_target_T_15 = {_f2_predicted_target_T_14[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _f2_predicted_target_T_16 = ~_f2_predicted_target_T_15; // @[frontend.scala:160:{31,39}] wire _f2_predicted_target_T_18 = &_f2_predicted_target_T_17; // @[frontend.scala:152:{28,66}] wire _f2_predicted_target_T_19 = _f2_predicted_target_T_18; // @[frontend.scala:152:{21,66}] wire [4:0] _f2_predicted_target_T_20 = _f2_predicted_target_T_19 ? 5'h8 : 5'h10; // @[frontend.scala:152:21, :170:28] wire [40:0] _f2_predicted_target_T_21 = {1'h0, _f2_predicted_target_T_16} + {36'h0, _f2_predicted_target_T_20}; // @[frontend.scala:160:31, :170:{23,28}] wire [39:0] _f2_predicted_target_T_22 = _f2_predicted_target_T_21[39:0]; // @[frontend.scala:170:23] wire [39:0] f2_predicted_target = f2_do_redirect ? _f2_predicted_target_T_13 : _f2_predicted_target_T_22; // @[package.scala:39:76] wire _f2_predicted_ghist_T = _bpd_io_resp_f2_preds_0_is_br & _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_1 = _bpd_io_resp_f2_preds_1_is_br & _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_2 = _bpd_io_resp_f2_preds_2_is_br & _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_3 = _bpd_io_resp_f2_preds_3_is_br & _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_4 = _bpd_io_resp_f2_preds_4_is_br & _bpd_io_resp_f2_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_5 = _bpd_io_resp_f2_preds_5_is_br & _bpd_io_resp_f2_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_6 = _bpd_io_resp_f2_preds_6_is_br & _bpd_io_resp_f2_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_7 = _bpd_io_resp_f2_preds_7_is_br & _bpd_io_resp_f2_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire [1:0] f2_predicted_ghist_lo_lo = {_f2_predicted_ghist_T_1, _f2_predicted_ghist_T}; // @[package.scala:45:27] wire [1:0] f2_predicted_ghist_lo_hi = {_f2_predicted_ghist_T_3, _f2_predicted_ghist_T_2}; // @[package.scala:45:27] wire [3:0] f2_predicted_ghist_lo = {f2_predicted_ghist_lo_hi, f2_predicted_ghist_lo_lo}; // @[package.scala:45:27] wire [1:0] f2_predicted_ghist_hi_lo = {_f2_predicted_ghist_T_5, _f2_predicted_ghist_T_4}; // @[package.scala:45:27] wire [1:0] f2_predicted_ghist_hi_hi = {_f2_predicted_ghist_T_7, _f2_predicted_ghist_T_6}; // @[package.scala:45:27] wire [3:0] f2_predicted_ghist_hi = {f2_predicted_ghist_hi_hi, f2_predicted_ghist_hi_lo}; // @[package.scala:45:27] wire [7:0] _f2_predicted_ghist_T_8 = {f2_predicted_ghist_hi, f2_predicted_ghist_lo}; // @[package.scala:45:27] wire [10:0] _f2_predicted_ghist_T_9 = {3'h0, f2_mask[7:0] & _f2_predicted_ghist_T_8}; // @[package.scala:45:27] wire [7:0] _GEN_7 = {{_bpd_io_resp_f2_preds_7_taken}, {_bpd_io_resp_f2_preds_6_taken}, {_bpd_io_resp_f2_preds_5_taken}, {_bpd_io_resp_f2_preds_4_taken}, {_bpd_io_resp_f2_preds_3_taken}, {_bpd_io_resp_f2_preds_2_taken}, {_bpd_io_resp_f2_preds_1_taken}, {_bpd_io_resp_f2_preds_0_taken}}; // @[frontend.scala:331:19, :471:46] wire [7:0] _GEN_8 = {{_bpd_io_resp_f2_preds_7_is_br}, {_bpd_io_resp_f2_preds_6_is_br}, {_bpd_io_resp_f2_preds_5_is_br}, {_bpd_io_resp_f2_preds_4_is_br}, {_bpd_io_resp_f2_preds_3_is_br}, {_bpd_io_resp_f2_preds_2_is_br}, {_bpd_io_resp_f2_preds_1_is_br}, {_bpd_io_resp_f2_preds_0_is_br}}; // @[frontend.scala:331:19, :471:46] wire _f2_predicted_ghist_T_10 = _GEN_7[f2_redirect_idx] & f2_do_redirect; // @[Mux.scala:50:70] wire [7:0] f2_predicted_ghist_cfi_idx_oh = 8'h1 << f2_predicted_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T = f2_predicted_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] f2_predicted_ghist_old_history; // @[frontend.scala:87:27] wire f2_predicted_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire f2_predicted_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] f2_predicted_ghist_ras_idx; // @[frontend.scala:87:27] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_1 = {1'h0, f2_predicted_ghist_cfi_idx_oh[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_2 = {2'h0, f2_predicted_ghist_cfi_idx_oh[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_3 = {3'h0, f2_predicted_ghist_cfi_idx_oh[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_4 = {4'h0, f2_predicted_ghist_cfi_idx_oh[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_5 = {5'h0, f2_predicted_ghist_cfi_idx_oh[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_6 = {6'h0, f2_predicted_ghist_cfi_idx_oh[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_7 = {7'h0, f2_predicted_ghist_cfi_idx_oh[7]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_8 = _f2_predicted_ghist_not_taken_branches_T \| _f2_predicted_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_9 = _f2_predicted_ghist_not_taken_branches_T_8 \| _f2_predicted_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_10 = _f2_predicted_ghist_not_taken_branches_T_9 \| _f2_predicted_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_11 = _f2_predicted_ghist_not_taken_branches_T_10 \| _f2_predicted_ghist_not_taken_branches_T_4; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_12 = _f2_predicted_ghist_not_taken_branches_T_11 \| _f2_predicted_ghist_not_taken_branches_T_5; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_13 = _f2_predicted_ghist_not_taken_branches_T_12 \| _f2_predicted_ghist_not_taken_branches_T_6; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_14 = _f2_predicted_ghist_not_taken_branches_T_13 \| _f2_predicted_ghist_not_taken_branches_T_7; // @[util.scala:373:{29,45}] wire _f2_predicted_ghist_not_taken_branches_T_15 = _GEN_8[f2_redirect_idx] & _f2_predicted_ghist_T_10; // @[Mux.scala:50:70] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_16 = _f2_predicted_ghist_not_taken_branches_T_15 ? f2_predicted_ghist_cfi_idx_oh : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_17 = ~_f2_predicted_ghist_not_taken_branches_T_16; // @[frontend.scala:90:{69,73}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_18 = _f2_predicted_ghist_not_taken_branches_T_14 & _f2_predicted_ghist_not_taken_branches_T_17; // @[util.scala:373:45] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_20 = f2_do_redirect ? _f2_predicted_ghist_not_taken_branches_T_18 : 8'hFF; // @[frontend.scala:89:44, :90:67, :465:50] wire [10:0] f2_predicted_ghist_not_taken_branches = {3'h0, _f2_predicted_ghist_T_9[7:0] & _f2_predicted_ghist_not_taken_branches_T_20}; // @[frontend.scala:89:{39,44}, :470:72] wire [64:0] _GEN_9 = {s2_ghist_old_history, 1'h0}; // @[frontend.scala:67:75, :442:21] wire [64:0] _f2_predicted_ghist_base_T; // @[frontend.scala:67:75] assign _f2_predicted_ghist_base_T = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_base_T_2; // @[frontend.scala:68:75] assign _f2_predicted_ghist_base_T_2 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_2; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_2 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_6; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T_6 = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_8; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_8 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_13; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T_13 = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_15; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_15 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_19; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T_19 = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_21; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_21 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_base_T_1 = {_f2_predicted_ghist_base_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _GEN_10 = {1'h0, s2_ghist_old_history}; // @[frontend.scala:68:12, :442:21] wire [64:0] _f2_predicted_ghist_base_T_3 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_base_T_2 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] f2_predicted_ghist_base = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_base_T_1 : _f2_predicted_ghist_base_T_3; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire _GEN_11 = f2_do_redirect & _f2_predicted_ghist_T_10; // @[frontend.scala:104:37, :465:50, :471:46] wire _f2_predicted_ghist_cfi_in_bank_0_T; // @[frontend.scala:104:37] assign _f2_predicted_ghist_cfi_in_bank_0_T = _GEN_11; // @[frontend.scala:104:37] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1; // @[frontend.scala:119:59] assign _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1 = _GEN_11; // @[frontend.scala:104:37, :119:59] wire _f2_predicted_ghist_cfi_in_bank_0_T_1 = ~(f2_predicted_ghist_cfi_idx_fixed[2]); // @[frontend.scala:85:32, :104:67] wire f2_predicted_ghist_cfi_in_bank_0 = _f2_predicted_ghist_cfi_in_bank_0_T & _f2_predicted_ghist_cfi_in_bank_0_T_1; // @[frontend.scala:104:{37,50,67}] wire _f2_predicted_ghist_ignore_second_bank_T_1 = &_f2_predicted_ghist_ignore_second_bank_T; // @[frontend.scala:152:{28,66}] wire _f2_predicted_ghist_ignore_second_bank_T_2 = _f2_predicted_ghist_ignore_second_bank_T_1; // @[frontend.scala:152:{21,66}] wire f2_predicted_ghist_ignore_second_bank = f2_predicted_ghist_cfi_in_bank_0 \| _f2_predicted_ghist_ignore_second_bank_T_2; // @[frontend.scala:104:50, :105:46, :152:21] wire [3:0] _f2_predicted_ghist_first_bank_saw_not_taken_T = f2_predicted_ghist_not_taken_branches[3:0]; // @[frontend.scala:89:39, :107:56] wire _f2_predicted_ghist_first_bank_saw_not_taken_T_1 = \|_f2_predicted_ghist_first_bank_saw_not_taken_T; // @[frontend.scala:107:{56,72}] wire f2_predicted_ghist_first_bank_saw_not_taken = _f2_predicted_ghist_first_bank_saw_not_taken_T_1 \| s2_ghist_current_saw_branch_not_taken; // @[frontend.scala:107:{72,80}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_1 = {_f2_predicted_ghist_new_history_old_history_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_3 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_2 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_4 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_1 : _f2_predicted_ghist_new_history_old_history_T_3; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire _GEN_12 = _GEN_8[f2_redirect_idx] & f2_predicted_ghist_cfi_in_bank_0; // @[Mux.scala:50:70] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T; // @[frontend.scala:112:59] assign _f2_predicted_ghist_new_history_new_saw_branch_taken_T = _GEN_12; // @[frontend.scala:112:59] wire _f2_predicted_ghist_new_history_old_history_T_5; // @[frontend.scala:114:50] assign _f2_predicted_ghist_new_history_old_history_T_5 = _GEN_12; // @[frontend.scala:112:59, :114:50] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_7 = {_f2_predicted_ghist_new_history_old_history_T_6[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_9 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_8 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_10 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_7 : _f2_predicted_ghist_new_history_old_history_T_9; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_11 = {_f2_predicted_ghist_new_history_old_history_T_10, 1'h0}; // @[frontend.scala:67:12, :114:110] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_12 = {_f2_predicted_ghist_new_history_old_history_T_11[65:1], 1'h1}; // @[frontend.scala:114:{110,115}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_14 = {_f2_predicted_ghist_new_history_old_history_T_13[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_16 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_15 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_17 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_14 : _f2_predicted_ghist_new_history_old_history_T_16; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_18 = {_f2_predicted_ghist_new_history_old_history_T_17, 1'h0}; // @[frontend.scala:67:12, :115:110] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_20 = {_f2_predicted_ghist_new_history_old_history_T_19[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_22 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_21 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_23 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_20 : _f2_predicted_ghist_new_history_old_history_T_22; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_24 = f2_predicted_ghist_first_bank_saw_not_taken ? _f2_predicted_ghist_new_history_old_history_T_18 : {1'h0, _f2_predicted_ghist_new_history_old_history_T_23}; // @[frontend.scala:67:12, :107:80, :115:{39,110}] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_25 = _f2_predicted_ghist_new_history_old_history_T_5 ? _f2_predicted_ghist_new_history_old_history_T_12 : _f2_predicted_ghist_new_history_old_history_T_24; // @[frontend.scala:114:{39,50,115}, :115:39] assign f2_predicted_ghist_old_history = f2_predicted_ghist_ignore_second_bank ? _f2_predicted_ghist_new_history_old_history_T_4[63:0] : _f2_predicted_ghist_new_history_old_history_T_25[63:0]; // @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}] wire [3:0] _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T = f2_predicted_ghist_not_taken_branches[7:4]; // @[frontend.scala:89:39, :118:67] wire _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = \|_f2_predicted_ghist_new_history_new_saw_branch_not_taken_T; // @[frontend.scala:118:{67,92}] assign f2_predicted_ghist_new_saw_branch_not_taken = f2_predicted_ghist_ignore_second_bank ? f2_predicted_ghist_first_bank_saw_not_taken : _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1; // @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_2 = _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1 & _GEN_8[f2_redirect_idx]; // @[Mux.scala:50:70] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3 = ~f2_predicted_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :119:88] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4 = _f2_predicted_ghist_new_history_new_saw_branch_taken_T_2 & _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3; // @[frontend.scala:119:{72,85,88}] assign f2_predicted_ghist_new_saw_branch_taken = f2_predicted_ghist_ignore_second_bank ? _f2_predicted_ghist_new_history_new_saw_branch_taken_T : _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4; // @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}] wire [5:0] _GEN_13 = {1'h0, s2_ghist_ras_idx}; // @[util.scala:203:14] wire [5:0] _f2_predicted_ghist_new_history_ras_idx_T_1 = _GEN_13 + 6'h1; // @[util.scala:203:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_2 = _f2_predicted_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_3 = _f2_predicted_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _f2_predicted_ghist_new_history_ras_idx_T_5 = _GEN_13 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_6 = _f2_predicted_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_7 = _f2_predicted_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] assign _f2_predicted_ghist_new_history_ras_idx_T_9 = _f2_predicted_ghist_new_history_ras_idx_T_8; // @[frontend.scala:123:31, :124:31] assign f2_predicted_ghist_ras_idx = _f2_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire _f2_correct_f1_ghist_T = s1_ghist_old_history == f2_predicted_ghist_old_history; // @[frontend.scala:75:19, :87:27, :381:29] wire _f2_correct_f1_ghist_T_1 = s1_ghist_new_saw_branch_not_taken == f2_predicted_ghist_new_saw_branch_not_taken; // @[frontend.scala:76:32, :87:27, :381:29] wire _f2_correct_f1_ghist_T_2 = _f2_correct_f1_ghist_T & _f2_correct_f1_ghist_T_1; // @[frontend.scala:75:{19,42}, :76:32] wire _f2_correct_f1_ghist_T_3 = s1_ghist_new_saw_branch_taken == f2_predicted_ghist_new_saw_branch_taken; // @[frontend.scala:77:28, :87:27, :381:29] wire _f2_correct_f1_ghist_T_4 = _f2_correct_f1_ghist_T_2 & _f2_correct_f1_ghist_T_3; // @[frontend.scala:75:42, :76:68, :77:28] wire _f2_correct_f1_ghist_T_5 = ~_f2_correct_f1_ghist_T_4; // @[frontend.scala:76:68, :80:41] wire f2_correct_f1_ghist = _f2_correct_f1_ghist_T_5; // @[frontend.scala:80:41, :479:61] wire _s0_is_replay_T = s2_valid & _icache_io_resp_valid; // @[frontend.scala:299:26, :440:25, :482:19, :485:30] wire _T_11 = s2_valid & ~_icache_io_resp_valid \| _s0_is_replay_T & ~f3_ready; // @[frontend.scala:299:26, :440:25, :452:22, :481:{19,22,45}, :482:{43,46}, :485:30] wire _s0_valid_T_2 = ~s2_tlb_resp_ae_inst; // @[frontend.scala:448:28, :483:18] wire _s0_valid_T_3 = ~s2_tlb_resp_pf_inst; // @[frontend.scala:448:28, :483:42] wire _s0_valid_T_4 = _s0_valid_T_2 & _s0_valid_T_3; // @[frontend.scala:483:{18,39,42}] wire _s0_valid_T_5 = _s0_valid_T_4 \| s2_is_replay; // @[frontend.scala:450:44, :483:{39,64}] wire _s0_valid_T_6 = _s0_valid_T_5 \| s2_tlb_miss; // @[frontend.scala:449:28, :483:{64,80}] wire _s0_s1_use_f3_bpd_resp_T = ~s2_is_replay; // @[frontend.scala:450:44, :451:77, :487:30] assign s0_s1_use_f3_bpd_resp = _T_11 & _s0_s1_use_f3_bpd_resp_T; // @[frontend.scala:356:39, :481:45, :482:58, :487:{27,30}] wire _T_12 = s2_valid & f3_ready; // @[frontend.scala:440:25, :452:22, :491:25] wire _T_21 = s1_valid & (s1_vpc != f2_predicted_target \| f2_correct_f1_ghist) \| ~s1_valid; // @[frontend.scala:379:29, :380:29, :466:32, :479:61, :496:{21,32,56,81,84}] wire _GEN_14 = _T_12 & _T_21; // @[frontend.scala:384:30, :491:{25,38}, :496:{81,95}] wire _s0_valid_T_8 = ~s2_is_replay; // @[frontend.scala:450:44, :451:77, :499:73] wire _s0_valid_T_9 = _s0_valid_T_7 & _s0_valid_T_8; // @[frontend.scala:499:{46,70,73}] wire _s0_valid_T_10 = ~_s0_valid_T_9; // @[frontend.scala:499:{23,70}] wire _GEN_15 = _T_12 & _T_21; // @[frontend.scala:427:35, :491:{25,38}, :496:{81,95}, :499:20] assign s2_fsrc = _T_11 ? 2'h0 : {1'h0, _GEN_15}; // @[frontend.scala:427:35, :446:25, :481:45, :482:58, :491:38, :496:95, :499:20, :503:20] wire f3_clear; // @[frontend.scala:514:26] wire f4_ready; // @[frontend.scala:526:22] wire _f3_io_enq_valid_T = ~f2_clear; // @[frontend.scala:447:26, :528:37] wire _f3_io_enq_valid_T_1 = s2_valid & _f3_io_enq_valid_T; // @[frontend.scala:440:25, :528:{34,37}] wire _f3_io_enq_valid_T_3 = ~s2_tlb_miss; // @[frontend.scala:449:28, :529:79] wire _f3_io_enq_valid_T_4 = _f3_io_enq_valid_T_2 & _f3_io_enq_valid_T_3; // @[frontend.scala:529:{52,76,79}] wire _f3_io_enq_valid_T_5 = _icache_io_resp_valid \| _f3_io_enq_valid_T_4; // @[frontend.scala:299:26, :529:{27,76}] wire _f3_io_enq_valid_T_6 = _f3_io_enq_valid_T_1 & _f3_io_enq_valid_T_5; // @[frontend.scala:528:{34,47}, :529:27] wire [127:0] _f3_io_enq_bits_data_T = s2_xcpt ? 128'h0 : _icache_io_resp_bits_data; // @[frontend.scala:299:26, :451:74, :532:30] wire [1:0] f3_io_enq_bits_mask_shamt = f3_io_enq_bits_mask_idx[1:0]; // @[package.scala:163:13] wire _f3_io_enq_bits_mask_end_mask_T_1 = &_f3_io_enq_bits_mask_end_mask_T; // @[frontend.scala:152:{28,66}] wire _f3_io_enq_bits_mask_end_mask_T_2 = _f3_io_enq_bits_mask_end_mask_T_1; // @[frontend.scala:152:{21,66}] wire [7:0] f3_io_enq_bits_mask_end_mask = _f3_io_enq_bits_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:152:21, :180:25] wire [10:0] _f3_io_enq_bits_mask_T = 11'hFF << f3_io_enq_bits_mask_shamt; // @[package.scala:163:13] wire [10:0] _f3_io_enq_bits_mask_T_1 = {3'h0, _f3_io_enq_bits_mask_T[7:0] & f3_io_enq_bits_mask_end_mask}; // @[frontend.scala:180:25, :181:{31,40}] reg [4:0] ras_read_idx; // @[frontend.scala:540:29] wire _T_26 = _f3_io_enq_ready & _f3_io_enq_valid_T_6; // @[Decoupled.scala:51:35] reg f3_bpd_resp_io_enq_valid_REG; // @[frontend.scala:549:57] wire _f3_bpd_resp_io_enq_valid_T = _f3_io_deq_valid & f3_bpd_resp_io_enq_valid_REG; // @[frontend.scala:516:11, :549:{47,57}] wire [2:0] f3_bank_mask_idx = _f3_io_deq_bits_pc[3:1]; // @[package.scala:163:13] wire [2:0] _f3_bank_mask_T = _f3_io_deq_bits_pc[5:3]; // @[frontend.scala:152:28, :516:11] wire _f3_bank_mask_T_1 = &_f3_bank_mask_T; // @[frontend.scala:152:{28,66}] wire _f3_bank_mask_T_2 = _f3_bank_mask_T_1; // @[frontend.scala:152:{21,66}] wire [1:0] f3_bank_mask = {~_f3_bank_mask_T_2, 1'h1}; // @[frontend.scala:152:21, :190:10] wire [39:0] _f3_aligned_pc_T = ~_f3_io_deq_bits_pc; // @[frontend.scala:160:33, :516:11] wire [39:0] _f3_aligned_pc_T_1 = {_f3_aligned_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] f3_aligned_pc = ~_f3_aligned_pc_T_1; // @[frontend.scala:160:{31,39}] wire [2:0] _f3_is_last_bank_in_block_T = f3_aligned_pc[5:3]; // @[frontend.scala:152:28, :160:31] wire _f3_is_last_bank_in_block_T_1 = &_f3_is_last_bank_in_block_T; // @[frontend.scala:152:{28,66}] wire f3_is_last_bank_in_block = _f3_is_last_bank_in_block_T_1; // @[frontend.scala:152:{21,66}] wire _f3_is_rvc_0_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_1_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_2_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_3_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_4_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_5_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_6_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_7_T_1; // @[frontend.scala:592:38] wire f3_is_rvc_0; // @[frontend.scala:564:29] wire f3_is_rvc_1; // @[frontend.scala:564:29] wire f3_is_rvc_2; // @[frontend.scala:564:29] wire f3_is_rvc_3; // @[frontend.scala:564:29] wire f3_is_rvc_4; // @[frontend.scala:564:29] wire f3_is_rvc_5; // @[frontend.scala:564:29] wire f3_is_rvc_6; // @[frontend.scala:564:29] wire f3_is_rvc_7; // @[frontend.scala:564:29] wire _f3_redirects_0_T_7; // @[frontend.scala:731:40] wire _f3_redirects_1_T_7; // @[frontend.scala:731:40] wire _f3_redirects_2_T_7; // @[frontend.scala:731:40] wire _f3_redirects_3_T_7; // @[frontend.scala:731:40] wire _f3_redirects_4_T_7; // @[frontend.scala:731:40] wire _f3_redirects_5_T_7; // @[frontend.scala:731:40] wire _f3_redirects_6_T_7; // @[frontend.scala:731:40] wire _f3_redirects_7_T_7; // @[frontend.scala:731:40] wire f3_redirects_0; // @[frontend.scala:565:29] wire f3_redirects_1; // @[frontend.scala:565:29] wire f3_redirects_2; // @[frontend.scala:565:29] wire f3_redirects_3; // @[frontend.scala:565:29] wire f3_redirects_4; // @[frontend.scala:565:29] wire f3_redirects_5; // @[frontend.scala:565:29] wire f3_redirects_6; // @[frontend.scala:565:29] wire f3_redirects_7; // @[frontend.scala:565:29] wire [39:0] _f3_targs_0_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_1_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_2_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_3_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_4_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_5_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_6_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_7_T_1; // @[frontend.scala:691:26] wire [39:0] f3_targs_0; // @[frontend.scala:566:29] wire [39:0] f3_targs_1; // @[frontend.scala:566:29] wire [39:0] f3_targs_2; // @[frontend.scala:566:29] wire [39:0] f3_targs_3; // @[frontend.scala:566:29] wire [39:0] f3_targs_4; // @[frontend.scala:566:29] wire [39:0] f3_targs_5; // @[frontend.scala:566:29] wire [39:0] f3_targs_6; // @[frontend.scala:566:29] wire [39:0] f3_targs_7; // @[frontend.scala:566:29] wire [2:0] brsigs_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_1_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_2_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_3_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_4_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_5_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_6_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_7_cfi_type; // @[frontend.scala:613:24] wire [2:0] f3_cfi_types_0; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_1; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_2; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_3; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_4; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_5; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_6; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_7; // @[frontend.scala:567:29] wire [39:0] f3_predicted_target; // @[frontend.scala:784:32] wire [31:0] inst; // @[frontend.scala:660:24] wire [31:0] inst_1; // @[frontend.scala:660:24] wire [31:0] inst_2; // @[frontend.scala:660:24] wire [31:0] inst_3; // @[frontend.scala:660:24] wire [31:0] inst_4; // @[frontend.scala:660:24] wire [31:0] inst_5; // @[frontend.scala:660:24] wire [31:0] exp_inst; // @[consts.scala:332:8] wire [31:0] exp_inst_1; // @[consts.scala:332:8] wire [31:0] exp_inst_2; // @[consts.scala:332:8] wire [31:0] exp_inst_3; // @[consts.scala:332:8] wire [31:0] exp_inst_4; // @[consts.scala:332:8] wire [31:0] exp_inst_5; // @[consts.scala:332:8] wire _f3_fetch_bundle_sfbs_0_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_1_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_2_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_3_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_4_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_5_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_6_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_7_T_3; // @[frontend.scala:719:33] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_80; // @[frontend.scala:722:68] wire _f3_fetch_bundle_shadowable_mask_0_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_1_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_2_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_3_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_4_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_5_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_6_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_7_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_cfi_idx_valid_T_6; // @[frontend.scala:777:57] wire [2:0] _f3_fetch_bundle_cfi_idx_bits_T_6; // @[Mux.scala:50:70] wire _f3_predicted_ghist_cfi_in_bank_0_T = f3_fetch_bundle_cfi_idx_valid; // @[frontend.scala:104:37, :569:29] wire _f3_predicted_ghist_new_history_new_saw_branch_taken_T_1 = f3_fetch_bundle_cfi_idx_valid; // @[frontend.scala:119:59, :569:29] wire [2:0] f3_predicted_ghist_cfi_idx_fixed = f3_fetch_bundle_cfi_idx_bits; // @[frontend.scala:85:32, :569:29] wire _f3_predicted_target_T_7 = f3_fetch_bundle_cfi_is_ret; // @[frontend.scala:569:29, :785:36] wire [7:0] _f3_fetch_bundle_mask_T; // @[frontend.scala:576:35] wire [7:0] _f3_fetch_bundle_br_mask_T; // @[frontend.scala:577:41] wire f3_fetch_bundle_edge_inst_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_edge_inst_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_0; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_2; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_3; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_4; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_5; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_6; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_7; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_0; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_2; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_3; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_4; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_5; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_6; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_7; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_2; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_3; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_4; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_5; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_6; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_7; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_0; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_1; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_2; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_3; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_4; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_5; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_6; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_7; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_0; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_1; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_2; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_3; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_4; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_5; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_6; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_7; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_2; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_3; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_4; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_5; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_6; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_7; // @[frontend.scala:569:29] wire [63:0] f3_fetch_bundle_ghist_old_history; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_current_saw_branch_not_taken; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_new_saw_branch_not_taken; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_new_saw_branch_taken; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_ghist_ras_idx; // @[frontend.scala:569:29] wire f3_fetch_bundle_lhist_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_lhist_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_end_half_valid; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_end_half_bits; // @[frontend.scala:569:29] wire [119:0] f3_fetch_bundle_bpd_meta_0; // @[frontend.scala:569:29] wire [119:0] f3_fetch_bundle_bpd_meta_1; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_pc; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_next_pc; // @[frontend.scala:569:29] wire [2:0] f3_fetch_bundle_cfi_type; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_is_call; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_npc_plus4; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_ras_top; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_mask; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_br_mask; // @[frontend.scala:569:29] wire f3_fetch_bundle_xcpt_pf_if; // @[frontend.scala:569:29] wire f3_fetch_bundle_xcpt_ae_if; // @[frontend.scala:569:29] wire [1:0] f3_fetch_bundle_fsrc; // @[frontend.scala:569:29] wire [1:0] f3_fetch_bundle_tsrc; // @[frontend.scala:569:29] wire _f3_mask_0_T_4; // @[frontend.scala:690:71] wire _f3_mask_1_T_4; // @[frontend.scala:690:71] wire _f3_mask_2_T_4; // @[frontend.scala:690:71] wire _f3_mask_3_T_4; // @[frontend.scala:690:71] wire _f3_mask_4_T_4; // @[frontend.scala:690:71] wire _f3_mask_5_T_4; // @[frontend.scala:690:71] wire _f3_mask_6_T_4; // @[frontend.scala:690:71] wire _f3_mask_7_T_4; // @[frontend.scala:690:71] wire f3_mask_0; // @[frontend.scala:570:29] wire f3_mask_1; // @[frontend.scala:570:29] wire f3_mask_2; // @[frontend.scala:570:29] wire f3_mask_3; // @[frontend.scala:570:29] wire f3_mask_4; // @[frontend.scala:570:29] wire f3_mask_5; // @[frontend.scala:570:29] wire f3_mask_6; // @[frontend.scala:570:29] wire f3_mask_7; // @[frontend.scala:570:29] wire _f3_br_mask_0_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_1_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_2_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_3_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_4_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_5_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_6_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_7_T_1; // @[frontend.scala:736:37] wire f3_br_mask_0; // @[frontend.scala:571:29] wire f3_br_mask_1; // @[frontend.scala:571:29] wire f3_br_mask_2; // @[frontend.scala:571:29] wire f3_br_mask_3; // @[frontend.scala:571:29] wire f3_br_mask_4; // @[frontend.scala:571:29] wire f3_br_mask_5; // @[frontend.scala:571:29] wire f3_br_mask_6; // @[frontend.scala:571:29] wire f3_br_mask_7; // @[frontend.scala:571:29] wire brsigs_is_call; // @[frontend.scala:613:24] wire brsigs_1_is_call; // @[frontend.scala:613:24] wire brsigs_2_is_call; // @[frontend.scala:613:24] wire brsigs_3_is_call; // @[frontend.scala:613:24] wire brsigs_4_is_call; // @[frontend.scala:613:24] wire brsigs_5_is_call; // @[frontend.scala:613:24] wire brsigs_6_is_call; // @[frontend.scala:613:24] wire brsigs_7_is_call; // @[frontend.scala:613:24] wire f3_call_mask_0; // @[frontend.scala:572:29] wire f3_call_mask_1; // @[frontend.scala:572:29] wire f3_call_mask_2; // @[frontend.scala:572:29] wire f3_call_mask_3; // @[frontend.scala:572:29] wire f3_call_mask_4; // @[frontend.scala:572:29] wire f3_call_mask_5; // @[frontend.scala:572:29] wire f3_call_mask_6; // @[frontend.scala:572:29] wire f3_call_mask_7; // @[frontend.scala:572:29] wire brsigs_is_ret; // @[frontend.scala:613:24] wire brsigs_1_is_ret; // @[frontend.scala:613:24] wire brsigs_2_is_ret; // @[frontend.scala:613:24] wire brsigs_3_is_ret; // @[frontend.scala:613:24] wire brsigs_4_is_ret; // @[frontend.scala:613:24] wire brsigs_5_is_ret; // @[frontend.scala:613:24] wire brsigs_6_is_ret; // @[frontend.scala:613:24] wire brsigs_7_is_ret; // @[frontend.scala:613:24] wire f3_ret_mask_0; // @[frontend.scala:573:29] wire f3_ret_mask_1; // @[frontend.scala:573:29] wire f3_ret_mask_2; // @[frontend.scala:573:29] wire f3_ret_mask_3; // @[frontend.scala:573:29] wire f3_ret_mask_4; // @[frontend.scala:573:29] wire f3_ret_mask_5; // @[frontend.scala:573:29] wire f3_ret_mask_6; // @[frontend.scala:573:29] wire f3_ret_mask_7; // @[frontend.scala:573:29] wire _f3_npc_plus4_mask_0_T_2; // @[frontend.scala:703:23] wire _f3_npc_plus4_mask_1_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_2_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_3_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_4_T_2; // @[frontend.scala:703:23] wire _f3_npc_plus4_mask_5_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_6_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_7_T; // @[frontend.scala:705:9] wire f3_npc_plus4_mask_0; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_1; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_2; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_3; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_4; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_5; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_6; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_7; // @[frontend.scala:574:31] wire _f3_btb_mispredicts_0_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_1_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_2_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_3_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_4_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_5_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_6_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_7_T_4; // @[frontend.scala:697:61] wire f3_btb_mispredicts_0; // @[frontend.scala:575:32] wire f3_btb_mispredicts_1; // @[frontend.scala:575:32] wire f3_btb_mispredicts_2; // @[frontend.scala:575:32] wire f3_btb_mispredicts_3; // @[frontend.scala:575:32] wire f3_btb_mispredicts_4; // @[frontend.scala:575:32] wire f3_btb_mispredicts_5; // @[frontend.scala:575:32] wire f3_btb_mispredicts_6; // @[frontend.scala:575:32] wire f3_btb_mispredicts_7; // @[frontend.scala:575:32] wire [1:0] f3_fetch_bundle_mask_lo_lo = {f3_mask_1, f3_mask_0}; // @[frontend.scala:570:29, :576:35] wire [1:0] f3_fetch_bundle_mask_lo_hi = {f3_mask_3, f3_mask_2}; // @[frontend.scala:570:29, :576:35] wire [3:0] f3_fetch_bundle_mask_lo = {f3_fetch_bundle_mask_lo_hi, f3_fetch_bundle_mask_lo_lo}; // @[frontend.scala:576:35] wire [1:0] f3_fetch_bundle_mask_hi_lo = {f3_mask_5, f3_mask_4}; // @[frontend.scala:570:29, :576:35] wire [1:0] f3_fetch_bundle_mask_hi_hi = {f3_mask_7, f3_mask_6}; // @[frontend.scala:570:29, :576:35] wire [3:0] f3_fetch_bundle_mask_hi = {f3_fetch_bundle_mask_hi_hi, f3_fetch_bundle_mask_hi_lo}; // @[frontend.scala:576:35] assign _f3_fetch_bundle_mask_T = {f3_fetch_bundle_mask_hi, f3_fetch_bundle_mask_lo}; // @[frontend.scala:576:35] assign f3_fetch_bundle_mask = _f3_fetch_bundle_mask_T; // @[frontend.scala:569:29, :576:35] wire [1:0] f3_fetch_bundle_br_mask_lo_lo = {f3_br_mask_1, f3_br_mask_0}; // @[frontend.scala:571:29, :577:41] wire [1:0] f3_fetch_bundle_br_mask_lo_hi = {f3_br_mask_3, f3_br_mask_2}; // @[frontend.scala:571:29, :577:41] wire [3:0] f3_fetch_bundle_br_mask_lo = {f3_fetch_bundle_br_mask_lo_hi, f3_fetch_bundle_br_mask_lo_lo}; // @[frontend.scala:577:41] wire [1:0] f3_fetch_bundle_br_mask_hi_lo = {f3_br_mask_5, f3_br_mask_4}; // @[frontend.scala:571:29, :577:41] wire [1:0] f3_fetch_bundle_br_mask_hi_hi = {f3_br_mask_7, f3_br_mask_6}; // @[frontend.scala:571:29, :577:41] wire [3:0] f3_fetch_bundle_br_mask_hi = {f3_fetch_bundle_br_mask_hi_hi, f3_fetch_bundle_br_mask_hi_lo}; // @[frontend.scala:577:41] assign _f3_fetch_bundle_br_mask_T = {f3_fetch_bundle_br_mask_hi, f3_fetch_bundle_br_mask_lo}; // @[frontend.scala:577:41] assign f3_fetch_bundle_br_mask = _f3_fetch_bundle_br_mask_T; // @[frontend.scala:569:29, :577:41] reg [15:0] f3_prev_half; // @[frontend.scala:587:28] reg f3_prev_is_half; // @[frontend.scala:589:32] assign f3_fetch_bundle_edge_inst_0 = f3_prev_is_half; // @[frontend.scala:569:29, :589:32] wire _offset_from_aligned_pc_T_2 = f3_prev_is_half; // @[frontend.scala:589:32, :710:31] wire [63:0] bank_data = _f3_io_deq_bits_data[63:0]; // @[frontend.scala:516:11, :598:29] wire _bank_mask_0_T_4; // @[frontend.scala:689:71] wire _bank_mask_1_T_4; // @[frontend.scala:689:71] wire _bank_mask_2_T_4; // @[frontend.scala:689:71] wire _bank_mask_3_T_4; // @[frontend.scala:689:71] wire bank_mask_0; // @[frontend.scala:599:26] wire bank_mask_1; // @[frontend.scala:599:26] wire bank_mask_2; // @[frontend.scala:599:26] wire bank_mask_3; // @[frontend.scala:599:26] wire [31:0] bank_insts_0; // @[frontend.scala:600:26] wire [31:0] bank_insts_1; // @[frontend.scala:600:26] wire [31:0] bank_insts_2; // @[frontend.scala:600:26] wire [31:0] bank_insts_3; // @[frontend.scala:600:26] assign f3_ret_mask_0 = brsigs_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_0 = brsigs_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_0 = brsigs_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_target; // @[frontend.scala:613:24] wire brsigs_shadowable; // @[frontend.scala:613:24] wire [15:0] _inst0_T = bank_data[15:0]; // @[frontend.scala:598:29, :615:34] wire [31:0] inst0 = {_inst0_T, f3_prev_half}; // @[frontend.scala:587:28, :615:{24,34}] wire [31:0] inst1 = bank_data[31:0]; // @[frontend.scala:598:29, :616:30] wire [31:0] exp_inst0 = _exp_inst0_rvc_exp_io_rvc ? _exp_inst0_rvc_exp_io_out_bits : inst0; // @[frontend.scala:615:24] wire [31:0] exp_inst1 = _exp_inst1_rvc_exp_io_rvc ? _exp_inst1_rvc_exp_io_out_bits : inst1; // @[frontend.scala:616:30] wire [40:0] _GEN_16 = {1'h0, f3_aligned_pc}; // @[frontend.scala:160:31, :619:34] wire [40:0] _pc0_T; // @[frontend.scala:619:34] assign _pc0_T = _GEN_16; // @[frontend.scala:619:34] wire [40:0] _pc1_T; // @[frontend.scala:620:34] assign _pc1_T = _GEN_16; // @[frontend.scala:619:34, :620:34] wire [39:0] _pc0_T_1 = _pc0_T[39:0]; // @[frontend.scala:619:34] wire [40:0] _pc0_T_2 = {1'h0, _pc0_T_1} - 41'h2; // @[frontend.scala:619:{34,69}] wire [39:0] pc0 = _pc0_T_2[39:0]; // @[frontend.scala:619:69] wire [39:0] pc1 = _pc1_T[39:0]; // @[frontend.scala:620:34] wire [31:0] _GEN_17 = f3_prev_is_half ? inst0 : inst1; // @[frontend.scala:589:32, :615:24, :616:30, :629:34, :630:40, :651:40] assign f3_fetch_bundle_insts_0 = _GEN_17; // @[frontend.scala:569:29, :629:34, :630:40, :651:40] assign bank_insts_0 = _GEN_17; // @[frontend.scala:600:26, :629:34, :630:40, :651:40] assign f3_fetch_bundle_exp_insts_0 = f3_prev_is_half ? exp_inst0 : exp_inst1; // @[frontend.scala:569:29, :589:32, :629:34, :632:40, :653:40] assign brsigs_shadowable = f3_prev_is_half ? _bpd_decoder0_io_out_shadowable : _bpd_decoder1_io_out_shadowable; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_sfb_offset_valid = f3_prev_is_half ? _bpd_decoder0_io_out_sfb_offset_valid : _bpd_decoder1_io_out_sfb_offset_valid; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_sfb_offset_bits = f3_prev_is_half ? _bpd_decoder0_io_out_sfb_offset_bits : _bpd_decoder1_io_out_sfb_offset_bits; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_cfi_type = f3_prev_is_half ? _bpd_decoder0_io_out_cfi_type : _bpd_decoder1_io_out_cfi_type; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_target = f3_prev_is_half ? _bpd_decoder0_io_out_target : _bpd_decoder1_io_out_target; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_is_call = f3_prev_is_half ? _bpd_decoder0_io_out_is_call : _bpd_decoder1_io_out_is_call; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_is_ret = f3_prev_is_half ? _bpd_decoder0_io_out_is_ret : _bpd_decoder1_io_out_is_ret; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] wire [1:0] _f3_is_rvc_0_T = bank_insts_0[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T = bank_insts_0[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_0_T_1 = _f3_is_rvc_0_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_0 = _f3_is_rvc_0_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_0_T = _f3_io_deq_bits_mask[0]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_0_T = _f3_io_deq_bits_mask[0]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_0_T_1 = _f3_io_deq_valid & _bank_mask_0_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_0_T_2 = _bank_mask_0_T_1; // @[frontend.scala:689:{39,62}] assign _bank_mask_0_T_4 = _bank_mask_0_T_2; // @[frontend.scala:689:{62,71}] assign bank_mask_0 = _bank_mask_0_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_0_T_1 = _f3_io_deq_valid & _f3_mask_0_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_0_T_2 = _f3_mask_0_T_1; // @[frontend.scala:690:{39,62}] assign _f3_mask_0_T_4 = _f3_mask_0_T_2; // @[frontend.scala:690:{62,71}] assign f3_mask_0 = _f3_mask_0_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_18 = brsigs_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_0_T; // @[frontend.scala:691:43] assign _f3_targs_0_T = _GEN_18; // @[frontend.scala:691:43] wire _f3_redirects_0_T_1; // @[frontend.scala:732:56] assign _f3_redirects_0_T_1 = _GEN_18; // @[frontend.scala:691:43, :732:56] assign _f3_targs_0_T_1 = _f3_targs_0_T ? _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits : brsigs_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_0 = _f3_targs_0_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_19 = brsigs_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_0_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_0_T = _GEN_19; // @[frontend.scala:696:49] wire _f3_redirects_0_T; // @[frontend.scala:732:25] assign _f3_redirects_0_T = _GEN_19; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_0_T_1 = _f3_btb_mispredicts_0_T; // @[frontend.scala:696:{49,61}] wire _f3_btb_mispredicts_0_T_2 = _f3_btb_mispredicts_0_T_1 & _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_0_T_3 = _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits != brsigs_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_0_T_4 = _f3_btb_mispredicts_0_T_2 & _f3_btb_mispredicts_0_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_0 = _f3_btb_mispredicts_0_T_4; // @[frontend.scala:575:32, :697:61] wire _f3_npc_plus4_mask_0_T = ~f3_is_rvc_0; // @[frontend.scala:564:29, :703:9] wire _f3_npc_plus4_mask_0_T_1 = ~f3_prev_is_half; // @[frontend.scala:589:32, :703:26] assign _f3_npc_plus4_mask_0_T_2 = _f3_npc_plus4_mask_0_T & _f3_npc_plus4_mask_0_T_1; // @[frontend.scala:703:{9,23,26}] assign f3_npc_plus4_mask_0 = _f3_npc_plus4_mask_0_T_2; // @[frontend.scala:574:31, :703:23] wire [7:0] _offset_from_aligned_pc_T = {2'h0, brsigs_sfb_offset_bits}; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_1 = _offset_from_aligned_pc_T[6:0]; // @[frontend.scala:708:50] wire [1:0] _offset_from_aligned_pc_T_3 = {_offset_from_aligned_pc_T_2, 1'h0}; // @[frontend.scala:710:{12,31}] wire [7:0] _offset_from_aligned_pc_T_4 = {1'h0, _offset_from_aligned_pc_T_1} - {6'h0, _offset_from_aligned_pc_T_3}; // @[frontend.scala:708:50, :709:32, :710:12] wire [6:0] offset_from_aligned_pc = _offset_from_aligned_pc_T_4[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T = offset_from_aligned_pc[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_1 = 32'h1 << _upper_mask_T; // @[OneHot.scala:58:35] wire [2:0] _GEN_20 = {f3_is_last_bank_in_block, 2'h0}; // @[frontend.scala:152:21, :715:86] wire [2:0] _upper_mask_T_2; // @[frontend.scala:715:86] assign _upper_mask_T_2 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_6; // @[frontend.scala:715:86] assign _upper_mask_T_6 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_10; // @[frontend.scala:715:86] assign _upper_mask_T_10 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_14; // @[frontend.scala:715:86] assign _upper_mask_T_14 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_18; // @[frontend.scala:715:86] assign _upper_mask_T_18 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_22; // @[frontend.scala:715:86] assign _upper_mask_T_22 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_26; // @[frontend.scala:715:86] assign _upper_mask_T_26 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_30; // @[frontend.scala:715:86] assign _upper_mask_T_30 = _GEN_20; // @[frontend.scala:715:86] wire [38:0] _upper_mask_T_3 = {7'h0, _upper_mask_T_1} << _upper_mask_T_2; // @[OneHot.scala:58:35] assign upper_mask = _upper_mask_T_3[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_0_T = f3_mask_0 & brsigs_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire [5:0] _GEN_21 = f3_is_last_bank_in_block ? 6'h18 : 6'h20; // @[frontend.scala:152:21, :720:39] wire [5:0] _f3_fetch_bundle_sfbs_0_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_0_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_1_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_1_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_2_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_2_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_3_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_3_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_4_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_4_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_5_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_5_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_6_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_6_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_7_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_7_T_1 = _GEN_21; // @[frontend.scala:720:39] wire _f3_fetch_bundle_sfbs_0_T_2 = offset_from_aligned_pc <= {1'h0, _f3_fetch_bundle_sfbs_0_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_0_T_3 = _f3_fetch_bundle_sfbs_0_T & _f3_fetch_bundle_sfbs_0_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_0 = _f3_fetch_bundle_sfbs_0_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_0_T_32 = {1'h0, upper_mask}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_33 = _f3_fetch_bundle_sfb_masks_0_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_0_T_34 = {upper_mask, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_35 = _f3_fetch_bundle_sfb_masks_0_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_0_T_36 = {1'h0, upper_mask, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_37 = _f3_fetch_bundle_sfb_masks_0_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_0_T_38 = {upper_mask, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_39 = _f3_fetch_bundle_sfb_masks_0_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_40 = {3'h0, upper_mask, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_41 = _f3_fetch_bundle_sfb_masks_0_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_42 = {2'h0, upper_mask, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_43 = _f3_fetch_bundle_sfb_masks_0_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_44 = {1'h0, upper_mask, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_45 = _f3_fetch_bundle_sfb_masks_0_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_46 = {upper_mask, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_47 = _f3_fetch_bundle_sfb_masks_0_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_48 = {7'h0, upper_mask, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_49 = _f3_fetch_bundle_sfb_masks_0_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_50 = {6'h0, upper_mask, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_51 = _f3_fetch_bundle_sfb_masks_0_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_52 = {5'h0, upper_mask, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_53 = _f3_fetch_bundle_sfb_masks_0_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_54 = {4'h0, upper_mask, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_55 = _f3_fetch_bundle_sfb_masks_0_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_56 = {3'h0, upper_mask, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_57 = _f3_fetch_bundle_sfb_masks_0_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_58 = {2'h0, upper_mask, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_59 = _f3_fetch_bundle_sfb_masks_0_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_60 = {1'h0, upper_mask, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_61 = _f3_fetch_bundle_sfb_masks_0_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_62 = {upper_mask, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_63 = _f3_fetch_bundle_sfb_masks_0_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_64 = _f3_fetch_bundle_sfb_masks_0_T_33 \| _f3_fetch_bundle_sfb_masks_0_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_65 = _f3_fetch_bundle_sfb_masks_0_T_64 \| _f3_fetch_bundle_sfb_masks_0_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_66 = _f3_fetch_bundle_sfb_masks_0_T_65 \| _f3_fetch_bundle_sfb_masks_0_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_67 = _f3_fetch_bundle_sfb_masks_0_T_66 \| _f3_fetch_bundle_sfb_masks_0_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_68 = _f3_fetch_bundle_sfb_masks_0_T_67 \| _f3_fetch_bundle_sfb_masks_0_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_69 = _f3_fetch_bundle_sfb_masks_0_T_68 \| _f3_fetch_bundle_sfb_masks_0_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_70 = _f3_fetch_bundle_sfb_masks_0_T_69 \| _f3_fetch_bundle_sfb_masks_0_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_71 = _f3_fetch_bundle_sfb_masks_0_T_70 \| _f3_fetch_bundle_sfb_masks_0_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_72 = _f3_fetch_bundle_sfb_masks_0_T_71 \| _f3_fetch_bundle_sfb_masks_0_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_73 = _f3_fetch_bundle_sfb_masks_0_T_72 \| _f3_fetch_bundle_sfb_masks_0_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_74 = _f3_fetch_bundle_sfb_masks_0_T_73 \| _f3_fetch_bundle_sfb_masks_0_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_75 = _f3_fetch_bundle_sfb_masks_0_T_74 \| _f3_fetch_bundle_sfb_masks_0_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_76 = _f3_fetch_bundle_sfb_masks_0_T_75 \| _f3_fetch_bundle_sfb_masks_0_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_77 = _f3_fetch_bundle_sfb_masks_0_T_76 \| _f3_fetch_bundle_sfb_masks_0_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_78 = _f3_fetch_bundle_sfb_masks_0_T_77 \| _f3_fetch_bundle_sfb_masks_0_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_79 = ~_f3_fetch_bundle_sfb_masks_0_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_0_T_80 = _f3_fetch_bundle_sfb_masks_0_T_79 & 16'hFFFE; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_0 = _f3_fetch_bundle_sfb_masks_0_T_80; // @[frontend.scala:569:29, :722:68] wire _GEN_22 = f3_fetch_bundle_xcpt_pf_if \| f3_fetch_bundle_xcpt_ae_if; // @[frontend.scala:569:29, :723:75] wire _f3_fetch_bundle_shadowable_mask_0_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_0_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_1_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_1_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_2_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_2_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_3_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_3_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_4_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_4_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_5_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_5_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_6_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_6_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_7_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_7_T = _GEN_22; // @[frontend.scala:723:75] wire _s0_valid_T_11; // @[frontend.scala:831:52] assign _s0_valid_T_11 = _GEN_22; // @[frontend.scala:723:75, :831:52] wire _f3_fetch_bundle_shadowable_mask_0_T_1 = _f3_fetch_bundle_shadowable_mask_0_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_0_T_2 = _f3_fetch_bundle_shadowable_mask_0_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_0_T_3 = ~_f3_fetch_bundle_shadowable_mask_0_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_0_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_1_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_2_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_3_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_0_T_5 = _f3_fetch_bundle_shadowable_mask_0_T_3 & _f3_fetch_bundle_shadowable_mask_0_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_0_T_6 = ~f3_mask_0; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_0_T_7 = brsigs_shadowable \| _f3_fetch_bundle_shadowable_mask_0_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_0_T_8 = _f3_fetch_bundle_shadowable_mask_0_T_5 & _f3_fetch_bundle_shadowable_mask_0_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_0 = _f3_fetch_bundle_shadowable_mask_0_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_0 = offset_from_aligned_pc[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_0_T_2 = _f3_redirects_0_T \| _f3_redirects_0_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_23 = brsigs_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_0_T_3; // @[frontend.scala:733:26] assign _f3_redirects_0_T_3 = _GEN_23; // @[frontend.scala:733:26] wire _f3_br_mask_0_T; // @[frontend.scala:736:56] assign _f3_br_mask_0_T = _GEN_23; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_0_T_4 = _f3_redirects_0_T_3 & _f3_bpd_resp_io_deq_bits_preds_0_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_0_T_5 = _f3_redirects_0_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_0_T_6 = _f3_redirects_0_T_2 \| _f3_redirects_0_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_0_T_7 = f3_mask_0 & _f3_redirects_0_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_0 = _f3_redirects_0_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_0_T_1 = f3_mask_0 & _f3_br_mask_0_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_0 = _f3_br_mask_0_T_1; // @[frontend.scala:571:29, :736:37] wire _valid_T_5; // @[frontend.scala:675:38] wire valid_1; // @[frontend.scala:605:23] assign f3_ret_mask_1 = brsigs_1_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_1 = brsigs_1_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_1 = brsigs_1_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_1_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_1_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_1_target; // @[frontend.scala:613:24] wire brsigs_1_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T; // @[frontend.scala:674:29] assign f3_fetch_bundle_insts_1 = inst; // @[frontend.scala:569:29, :660:24] assign bank_insts_1 = inst; // @[frontend.scala:600:26, :660:24] assign exp_inst = _exp_inst_rvc_exp_io_rvc ? _exp_inst_rvc_exp_io_out_bits : inst; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_1 = exp_inst; // @[frontend.scala:569:29] wire [40:0] _pc_T = _GEN_16 + 41'h2; // @[frontend.scala:619:34, :662:32] wire [39:0] pc = _pc_T[39:0]; // @[frontend.scala:662:32] assign _inst_T = bank_data[47:16]; // @[frontend.scala:598:29, :674:29] assign inst = _inst_T; // @[frontend.scala:660:24, :674:29] wire _valid_T_1 = _valid_T != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_2 = ~_valid_T_1; // @[frontend.scala:592:38, :675:59] wire _valid_T_3 = bank_mask_0 & _valid_T_2; // @[frontend.scala:599:26, :675:{56,59}] wire _valid_T_4 = ~_valid_T_3; // @[frontend.scala:675:{41,56}] assign _valid_T_5 = f3_prev_is_half \| _valid_T_4; // @[frontend.scala:589:32, :675:{38,41}] assign valid_1 = _valid_T_5; // @[frontend.scala:605:23, :675:38] wire [1:0] _f3_is_rvc_1_T = bank_insts_1[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_6 = bank_insts_1[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_1_T_1 = _f3_is_rvc_1_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_1 = _f3_is_rvc_1_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_1_T = _f3_io_deq_bits_mask[1]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_1_T = _f3_io_deq_bits_mask[1]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_1_T_1 = _f3_io_deq_valid & _bank_mask_1_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_1_T_2 = _bank_mask_1_T_1 & valid_1; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_1_T_3 = ~f3_redirects_0; // @[frontend.scala:565:29, :689:74] assign _bank_mask_1_T_4 = _bank_mask_1_T_2 & _bank_mask_1_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1 = _bank_mask_1_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_1_T_1 = _f3_io_deq_valid & _f3_mask_1_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_1_T_2 = _f3_mask_1_T_1 & valid_1; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_1_T_3 = ~f3_redirects_0; // @[frontend.scala:565:29, :689:74, :690:74] assign _f3_mask_1_T_4 = _f3_mask_1_T_2 & _f3_mask_1_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_1 = _f3_mask_1_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_24 = brsigs_1_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_1_T; // @[frontend.scala:691:43] assign _f3_targs_1_T = _GEN_24; // @[frontend.scala:691:43] wire _f3_redirects_1_T_1; // @[frontend.scala:732:56] assign _f3_redirects_1_T_1 = _GEN_24; // @[frontend.scala:691:43, :732:56] assign _f3_targs_1_T_1 = _f3_targs_1_T ? _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits : brsigs_1_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_1 = _f3_targs_1_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_25 = brsigs_1_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_1_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_1_T = _GEN_25; // @[frontend.scala:696:49] wire _f3_redirects_1_T; // @[frontend.scala:732:25] assign _f3_redirects_1_T = _GEN_25; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_1_T_1 = _f3_btb_mispredicts_1_T & valid_1; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_1_T_2 = _f3_btb_mispredicts_1_T_1 & _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_1_T_3 = _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits != brsigs_1_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_1_T_4 = _f3_btb_mispredicts_1_T_2 & _f3_btb_mispredicts_1_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_1 = _f3_btb_mispredicts_1_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_1_T = ~f3_is_rvc_1; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_1 = _f3_npc_plus4_mask_1_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_5 = {2'h0, brsigs_1_sfb_offset_bits} + 8'h2; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_6 = _offset_from_aligned_pc_T_5[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_9 = {1'h0, _offset_from_aligned_pc_T_6}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_1 = _offset_from_aligned_pc_T_9[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_1; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_4 = offset_from_aligned_pc_1[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_5 = 32'h1 << _upper_mask_T_4; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_7 = {7'h0, _upper_mask_T_5} << _upper_mask_T_6; // @[OneHot.scala:58:35] assign upper_mask_1 = _upper_mask_T_7[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_1_T = f3_mask_1 & brsigs_1_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_1_T_2 = offset_from_aligned_pc_1 <= {1'h0, _f3_fetch_bundle_sfbs_1_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_1_T_3 = _f3_fetch_bundle_sfbs_1_T & _f3_fetch_bundle_sfbs_1_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_1 = _f3_fetch_bundle_sfbs_1_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_1_T_32 = {1'h0, upper_mask_1}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_33 = _f3_fetch_bundle_sfb_masks_1_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_1_T_34 = {upper_mask_1, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_35 = _f3_fetch_bundle_sfb_masks_1_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_1_T_36 = {1'h0, upper_mask_1, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_37 = _f3_fetch_bundle_sfb_masks_1_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_1_T_38 = {upper_mask_1, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_39 = _f3_fetch_bundle_sfb_masks_1_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_40 = {3'h0, upper_mask_1, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_41 = _f3_fetch_bundle_sfb_masks_1_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_42 = {2'h0, upper_mask_1, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_43 = _f3_fetch_bundle_sfb_masks_1_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_44 = {1'h0, upper_mask_1, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_45 = _f3_fetch_bundle_sfb_masks_1_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_46 = {upper_mask_1, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_47 = _f3_fetch_bundle_sfb_masks_1_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_48 = {7'h0, upper_mask_1, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_49 = _f3_fetch_bundle_sfb_masks_1_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_50 = {6'h0, upper_mask_1, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_51 = _f3_fetch_bundle_sfb_masks_1_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_52 = {5'h0, upper_mask_1, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_53 = _f3_fetch_bundle_sfb_masks_1_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_54 = {4'h0, upper_mask_1, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_55 = _f3_fetch_bundle_sfb_masks_1_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_56 = {3'h0, upper_mask_1, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_57 = _f3_fetch_bundle_sfb_masks_1_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_58 = {2'h0, upper_mask_1, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_59 = _f3_fetch_bundle_sfb_masks_1_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_60 = {1'h0, upper_mask_1, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_61 = _f3_fetch_bundle_sfb_masks_1_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_62 = {upper_mask_1, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_63 = _f3_fetch_bundle_sfb_masks_1_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_64 = _f3_fetch_bundle_sfb_masks_1_T_33 \| _f3_fetch_bundle_sfb_masks_1_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_65 = _f3_fetch_bundle_sfb_masks_1_T_64 \| _f3_fetch_bundle_sfb_masks_1_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_66 = _f3_fetch_bundle_sfb_masks_1_T_65 \| _f3_fetch_bundle_sfb_masks_1_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_67 = _f3_fetch_bundle_sfb_masks_1_T_66 \| _f3_fetch_bundle_sfb_masks_1_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_68 = _f3_fetch_bundle_sfb_masks_1_T_67 \| _f3_fetch_bundle_sfb_masks_1_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_69 = _f3_fetch_bundle_sfb_masks_1_T_68 \| _f3_fetch_bundle_sfb_masks_1_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_70 = _f3_fetch_bundle_sfb_masks_1_T_69 \| _f3_fetch_bundle_sfb_masks_1_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_71 = _f3_fetch_bundle_sfb_masks_1_T_70 \| _f3_fetch_bundle_sfb_masks_1_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_72 = _f3_fetch_bundle_sfb_masks_1_T_71 \| _f3_fetch_bundle_sfb_masks_1_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_73 = _f3_fetch_bundle_sfb_masks_1_T_72 \| _f3_fetch_bundle_sfb_masks_1_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_74 = _f3_fetch_bundle_sfb_masks_1_T_73 \| _f3_fetch_bundle_sfb_masks_1_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_75 = _f3_fetch_bundle_sfb_masks_1_T_74 \| _f3_fetch_bundle_sfb_masks_1_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_76 = _f3_fetch_bundle_sfb_masks_1_T_75 \| _f3_fetch_bundle_sfb_masks_1_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_77 = _f3_fetch_bundle_sfb_masks_1_T_76 \| _f3_fetch_bundle_sfb_masks_1_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_78 = _f3_fetch_bundle_sfb_masks_1_T_77 \| _f3_fetch_bundle_sfb_masks_1_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_79 = ~_f3_fetch_bundle_sfb_masks_1_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_1_T_80 = _f3_fetch_bundle_sfb_masks_1_T_79 & 16'hFFFC; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_1 = _f3_fetch_bundle_sfb_masks_1_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_1_T_1 = _f3_fetch_bundle_shadowable_mask_1_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_1_T_2 = _f3_fetch_bundle_shadowable_mask_1_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_1_T_3 = ~_f3_fetch_bundle_shadowable_mask_1_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_1_T_5 = _f3_fetch_bundle_shadowable_mask_1_T_3 & _f3_fetch_bundle_shadowable_mask_1_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_1_T_6 = ~f3_mask_1; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_1_T_7 = brsigs_1_shadowable \| _f3_fetch_bundle_shadowable_mask_1_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_1_T_8 = _f3_fetch_bundle_shadowable_mask_1_T_5 & _f3_fetch_bundle_shadowable_mask_1_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_1 = _f3_fetch_bundle_shadowable_mask_1_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_1 = offset_from_aligned_pc_1[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_1_T_2 = _f3_redirects_1_T \| _f3_redirects_1_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_26 = brsigs_1_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_1_T_3; // @[frontend.scala:733:26] assign _f3_redirects_1_T_3 = _GEN_26; // @[frontend.scala:733:26] wire _f3_br_mask_1_T; // @[frontend.scala:736:56] assign _f3_br_mask_1_T = _GEN_26; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_1_T_4 = _f3_redirects_1_T_3 & _f3_bpd_resp_io_deq_bits_preds_1_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_1_T_5 = _f3_redirects_1_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_1_T_6 = _f3_redirects_1_T_2 \| _f3_redirects_1_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_1_T_7 = f3_mask_1 & _f3_redirects_1_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_1 = _f3_redirects_1_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_1_T_1 = f3_mask_1 & _f3_br_mask_1_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_1 = _f3_br_mask_1_T_1; // @[frontend.scala:571:29, :736:37] wire _T_29 = f3_redirects_0 \| f3_redirects_1; // @[frontend.scala:565:29, :744:39] wire _valid_T_10; // @[frontend.scala:682:20] wire valid_2; // @[frontend.scala:605:23] assign f3_ret_mask_2 = brsigs_2_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_2 = brsigs_2_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_2 = brsigs_2_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_2_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_2_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_2_target; // @[frontend.scala:613:24] wire brsigs_2_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_1; // @[frontend.scala:681:29] assign f3_fetch_bundle_insts_2 = inst_1; // @[frontend.scala:569:29, :660:24] assign bank_insts_2 = inst_1; // @[frontend.scala:600:26, :660:24] assign exp_inst_1 = _exp_inst_rvc_exp_1_io_rvc ? _exp_inst_rvc_exp_1_io_out_bits : inst_1; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_2 = exp_inst_1; // @[frontend.scala:569:29] wire [40:0] _pc_T_1 = _GEN_16 + 41'h4; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_1 = _pc_T_1[39:0]; // @[frontend.scala:662:32] assign _inst_T_1 = bank_data[63:32]; // @[frontend.scala:598:29, :681:29] assign inst_1 = _inst_T_1; // @[frontend.scala:660:24, :681:29] wire _valid_T_7 = _valid_T_6 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_8 = ~_valid_T_7; // @[frontend.scala:592:38, :682:40] wire _valid_T_9 = bank_mask_1 & _valid_T_8; // @[frontend.scala:599:26, :682:{37,40}] assign _valid_T_10 = ~_valid_T_9; // @[frontend.scala:682:{20,37}] assign valid_2 = _valid_T_10; // @[frontend.scala:605:23, :682:20] wire [1:0] _f3_is_rvc_2_T = bank_insts_2[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_11 = bank_insts_2[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_2_T_1 = _f3_is_rvc_2_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_2 = _f3_is_rvc_2_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_2_T = _f3_io_deq_bits_mask[2]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_2_T = _f3_io_deq_bits_mask[2]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_2_T_1 = _f3_io_deq_valid & _bank_mask_2_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_2_T_2 = _bank_mask_2_T_1 & valid_2; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_2_T_3 = ~_T_29; // @[frontend.scala:689:74, :744:39] assign _bank_mask_2_T_4 = _bank_mask_2_T_2 & _bank_mask_2_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_2 = _bank_mask_2_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_2_T_1 = _f3_io_deq_valid & _f3_mask_2_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_2_T_2 = _f3_mask_2_T_1 & valid_2; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_2_T_3 = ~_T_29; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_2_T_4 = _f3_mask_2_T_2 & _f3_mask_2_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_2 = _f3_mask_2_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_27 = brsigs_2_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_2_T; // @[frontend.scala:691:43] assign _f3_targs_2_T = _GEN_27; // @[frontend.scala:691:43] wire _f3_redirects_2_T_1; // @[frontend.scala:732:56] assign _f3_redirects_2_T_1 = _GEN_27; // @[frontend.scala:691:43, :732:56] assign _f3_targs_2_T_1 = _f3_targs_2_T ? _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits : brsigs_2_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_2 = _f3_targs_2_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_28 = brsigs_2_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_2_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_2_T = _GEN_28; // @[frontend.scala:696:49] wire _f3_redirects_2_T; // @[frontend.scala:732:25] assign _f3_redirects_2_T = _GEN_28; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_2_T_1 = _f3_btb_mispredicts_2_T & valid_2; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_2_T_2 = _f3_btb_mispredicts_2_T_1 & _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_2_T_3 = _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits != brsigs_2_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_2_T_4 = _f3_btb_mispredicts_2_T_2 & _f3_btb_mispredicts_2_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_2 = _f3_btb_mispredicts_2_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_2_T = ~f3_is_rvc_2; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_2 = _f3_npc_plus4_mask_2_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_10 = {2'h0, brsigs_2_sfb_offset_bits} + 8'h4; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_11 = _offset_from_aligned_pc_T_10[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_14 = {1'h0, _offset_from_aligned_pc_T_11}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_2 = _offset_from_aligned_pc_T_14[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_2; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_8 = offset_from_aligned_pc_2[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_9 = 32'h1 << _upper_mask_T_8; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_11 = {7'h0, _upper_mask_T_9} << _upper_mask_T_10; // @[OneHot.scala:58:35] assign upper_mask_2 = _upper_mask_T_11[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_2_T = f3_mask_2 & brsigs_2_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_2_T_2 = offset_from_aligned_pc_2 <= {1'h0, _f3_fetch_bundle_sfbs_2_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_2_T_3 = _f3_fetch_bundle_sfbs_2_T & _f3_fetch_bundle_sfbs_2_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_2 = _f3_fetch_bundle_sfbs_2_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_2_T_32 = {1'h0, upper_mask_2}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_33 = _f3_fetch_bundle_sfb_masks_2_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_2_T_34 = {upper_mask_2, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_35 = _f3_fetch_bundle_sfb_masks_2_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_2_T_36 = {1'h0, upper_mask_2, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_37 = _f3_fetch_bundle_sfb_masks_2_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_2_T_38 = {upper_mask_2, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_39 = _f3_fetch_bundle_sfb_masks_2_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_40 = {3'h0, upper_mask_2, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_41 = _f3_fetch_bundle_sfb_masks_2_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_42 = {2'h0, upper_mask_2, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_43 = _f3_fetch_bundle_sfb_masks_2_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_44 = {1'h0, upper_mask_2, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_45 = _f3_fetch_bundle_sfb_masks_2_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_46 = {upper_mask_2, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_47 = _f3_fetch_bundle_sfb_masks_2_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_48 = {7'h0, upper_mask_2, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_49 = _f3_fetch_bundle_sfb_masks_2_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_50 = {6'h0, upper_mask_2, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_51 = _f3_fetch_bundle_sfb_masks_2_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_52 = {5'h0, upper_mask_2, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_53 = _f3_fetch_bundle_sfb_masks_2_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_54 = {4'h0, upper_mask_2, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_55 = _f3_fetch_bundle_sfb_masks_2_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_56 = {3'h0, upper_mask_2, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_57 = _f3_fetch_bundle_sfb_masks_2_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_58 = {2'h0, upper_mask_2, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_59 = _f3_fetch_bundle_sfb_masks_2_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_60 = {1'h0, upper_mask_2, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_61 = _f3_fetch_bundle_sfb_masks_2_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_62 = {upper_mask_2, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_63 = _f3_fetch_bundle_sfb_masks_2_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_64 = _f3_fetch_bundle_sfb_masks_2_T_33 \| _f3_fetch_bundle_sfb_masks_2_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_65 = _f3_fetch_bundle_sfb_masks_2_T_64 \| _f3_fetch_bundle_sfb_masks_2_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_66 = _f3_fetch_bundle_sfb_masks_2_T_65 \| _f3_fetch_bundle_sfb_masks_2_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_67 = _f3_fetch_bundle_sfb_masks_2_T_66 \| _f3_fetch_bundle_sfb_masks_2_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_68 = _f3_fetch_bundle_sfb_masks_2_T_67 \| _f3_fetch_bundle_sfb_masks_2_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_69 = _f3_fetch_bundle_sfb_masks_2_T_68 \| _f3_fetch_bundle_sfb_masks_2_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_70 = _f3_fetch_bundle_sfb_masks_2_T_69 \| _f3_fetch_bundle_sfb_masks_2_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_71 = _f3_fetch_bundle_sfb_masks_2_T_70 \| _f3_fetch_bundle_sfb_masks_2_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_72 = _f3_fetch_bundle_sfb_masks_2_T_71 \| _f3_fetch_bundle_sfb_masks_2_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_73 = _f3_fetch_bundle_sfb_masks_2_T_72 \| _f3_fetch_bundle_sfb_masks_2_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_74 = _f3_fetch_bundle_sfb_masks_2_T_73 \| _f3_fetch_bundle_sfb_masks_2_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_75 = _f3_fetch_bundle_sfb_masks_2_T_74 \| _f3_fetch_bundle_sfb_masks_2_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_76 = _f3_fetch_bundle_sfb_masks_2_T_75 \| _f3_fetch_bundle_sfb_masks_2_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_77 = _f3_fetch_bundle_sfb_masks_2_T_76 \| _f3_fetch_bundle_sfb_masks_2_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_78 = _f3_fetch_bundle_sfb_masks_2_T_77 \| _f3_fetch_bundle_sfb_masks_2_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_79 = ~_f3_fetch_bundle_sfb_masks_2_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_2_T_80 = _f3_fetch_bundle_sfb_masks_2_T_79 & 16'hFFF8; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_2 = _f3_fetch_bundle_sfb_masks_2_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_2_T_1 = _f3_fetch_bundle_shadowable_mask_2_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_2_T_2 = _f3_fetch_bundle_shadowable_mask_2_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_2_T_3 = ~_f3_fetch_bundle_shadowable_mask_2_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_2_T_5 = _f3_fetch_bundle_shadowable_mask_2_T_3 & _f3_fetch_bundle_shadowable_mask_2_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_2_T_6 = ~f3_mask_2; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_2_T_7 = brsigs_2_shadowable \| _f3_fetch_bundle_shadowable_mask_2_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_2_T_8 = _f3_fetch_bundle_shadowable_mask_2_T_5 & _f3_fetch_bundle_shadowable_mask_2_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_2 = _f3_fetch_bundle_shadowable_mask_2_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_2 = offset_from_aligned_pc_2[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_2_T_2 = _f3_redirects_2_T \| _f3_redirects_2_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_29 = brsigs_2_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_2_T_3; // @[frontend.scala:733:26] assign _f3_redirects_2_T_3 = _GEN_29; // @[frontend.scala:733:26] wire _f3_br_mask_2_T; // @[frontend.scala:736:56] assign _f3_br_mask_2_T = _GEN_29; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_2_T_4 = _f3_redirects_2_T_3 & _f3_bpd_resp_io_deq_bits_preds_2_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_2_T_5 = _f3_redirects_2_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_2_T_6 = _f3_redirects_2_T_2 \| _f3_redirects_2_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_2_T_7 = f3_mask_2 & _f3_redirects_2_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_2 = _f3_redirects_2_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_2_T_1 = f3_mask_2 & _f3_br_mask_2_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_2 = _f3_br_mask_2_T_1; // @[frontend.scala:571:29, :736:37] wire _T_30 = _T_29 \| f3_redirects_2; // @[frontend.scala:565:29, :744:39] wire _valid_T_19; // @[frontend.scala:678:20] wire valid_3; // @[frontend.scala:605:23] assign f3_ret_mask_3 = brsigs_3_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_3 = brsigs_3_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_3 = brsigs_3_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_3_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_3_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_3_target; // @[frontend.scala:613:24] wire brsigs_3_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_3; // @[frontend.scala:677:23] assign f3_fetch_bundle_insts_3 = inst_2; // @[frontend.scala:569:29, :660:24] assign bank_insts_3 = inst_2; // @[frontend.scala:600:26, :660:24] assign exp_inst_2 = _exp_inst_rvc_exp_2_io_rvc ? _exp_inst_rvc_exp_2_io_out_bits : inst_2; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_3 = exp_inst_2; // @[frontend.scala:569:29] wire [40:0] _pc_T_2 = _GEN_16 + 41'h6; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_2 = _pc_T_2[39:0]; // @[frontend.scala:662:32] wire [15:0] _inst_T_2 = bank_data[63:48]; // @[frontend.scala:598:29, :677:44] assign _inst_T_3 = {16'h0, _inst_T_2}; // @[frontend.scala:677:{23,44}] assign inst_2 = _inst_T_3; // @[frontend.scala:660:24, :677:23] wire _valid_T_12 = _valid_T_11 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_13 = ~_valid_T_12; // @[frontend.scala:592:38, :678:41] wire _valid_T_14 = bank_mask_2 & _valid_T_13; // @[frontend.scala:599:26, :678:{38,41}] wire [1:0] _valid_T_15 = inst_2[1:0]; // @[frontend.scala:592:32, :660:24] wire _valid_T_16 = _valid_T_15 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_17 = ~_valid_T_16; // @[frontend.scala:592:38, :679:13] wire _valid_T_18 = _valid_T_14 \| _valid_T_17; // @[frontend.scala:678:{38,66}, :679:13] assign _valid_T_19 = ~_valid_T_18; // @[frontend.scala:678:{20,66}] assign valid_3 = _valid_T_19; // @[frontend.scala:605:23, :678:20] wire [1:0] _f3_is_rvc_3_T = bank_insts_3[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_3_T_1 = _f3_is_rvc_3_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_3 = _f3_is_rvc_3_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_3_T = _f3_io_deq_bits_mask[3]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_3_T = _f3_io_deq_bits_mask[3]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_3_T_1 = _f3_io_deq_valid & _bank_mask_3_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_3_T_2 = _bank_mask_3_T_1 & valid_3; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_3_T_3 = ~_T_30; // @[frontend.scala:689:74, :744:39] assign _bank_mask_3_T_4 = _bank_mask_3_T_2 & _bank_mask_3_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_3 = _bank_mask_3_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_3_T_1 = _f3_io_deq_valid & _f3_mask_3_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_3_T_2 = _f3_mask_3_T_1 & valid_3; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_3_T_3 = ~_T_30; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_3_T_4 = _f3_mask_3_T_2 & _f3_mask_3_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_3 = _f3_mask_3_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_30 = brsigs_3_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_3_T; // @[frontend.scala:691:43] assign _f3_targs_3_T = _GEN_30; // @[frontend.scala:691:43] wire _f3_redirects_3_T_1; // @[frontend.scala:732:56] assign _f3_redirects_3_T_1 = _GEN_30; // @[frontend.scala:691:43, :732:56] assign _f3_targs_3_T_1 = _f3_targs_3_T ? _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits : brsigs_3_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_3 = _f3_targs_3_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_31 = brsigs_3_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_3_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_3_T = _GEN_31; // @[frontend.scala:696:49] wire _f3_redirects_3_T; // @[frontend.scala:732:25] assign _f3_redirects_3_T = _GEN_31; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_3_T_1 = _f3_btb_mispredicts_3_T & valid_3; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_3_T_2 = _f3_btb_mispredicts_3_T_1 & _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_3_T_3 = _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits != brsigs_3_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_3_T_4 = _f3_btb_mispredicts_3_T_2 & _f3_btb_mispredicts_3_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_3 = _f3_btb_mispredicts_3_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_3_T = ~f3_is_rvc_3; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_3 = _f3_npc_plus4_mask_3_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_15 = {2'h0, brsigs_3_sfb_offset_bits} + 8'h6; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_16 = _offset_from_aligned_pc_T_15[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_19 = {1'h0, _offset_from_aligned_pc_T_16}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_3 = _offset_from_aligned_pc_T_19[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_3; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_12 = offset_from_aligned_pc_3[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_13 = 32'h1 << _upper_mask_T_12; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_15 = {7'h0, _upper_mask_T_13} << _upper_mask_T_14; // @[OneHot.scala:58:35] assign upper_mask_3 = _upper_mask_T_15[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_3_T = f3_mask_3 & brsigs_3_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_3_T_2 = offset_from_aligned_pc_3 <= {1'h0, _f3_fetch_bundle_sfbs_3_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_3_T_3 = _f3_fetch_bundle_sfbs_3_T & _f3_fetch_bundle_sfbs_3_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_3 = _f3_fetch_bundle_sfbs_3_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_3_T_32 = {1'h0, upper_mask_3}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_33 = _f3_fetch_bundle_sfb_masks_3_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_3_T_34 = {upper_mask_3, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_35 = _f3_fetch_bundle_sfb_masks_3_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_3_T_36 = {1'h0, upper_mask_3, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_37 = _f3_fetch_bundle_sfb_masks_3_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_3_T_38 = {upper_mask_3, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_39 = _f3_fetch_bundle_sfb_masks_3_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_40 = {3'h0, upper_mask_3, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_41 = _f3_fetch_bundle_sfb_masks_3_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_42 = {2'h0, upper_mask_3, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_43 = _f3_fetch_bundle_sfb_masks_3_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_44 = {1'h0, upper_mask_3, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_45 = _f3_fetch_bundle_sfb_masks_3_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_46 = {upper_mask_3, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_47 = _f3_fetch_bundle_sfb_masks_3_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_48 = {7'h0, upper_mask_3, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_49 = _f3_fetch_bundle_sfb_masks_3_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_50 = {6'h0, upper_mask_3, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_51 = _f3_fetch_bundle_sfb_masks_3_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_52 = {5'h0, upper_mask_3, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_53 = _f3_fetch_bundle_sfb_masks_3_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_54 = {4'h0, upper_mask_3, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_55 = _f3_fetch_bundle_sfb_masks_3_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_56 = {3'h0, upper_mask_3, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_57 = _f3_fetch_bundle_sfb_masks_3_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_58 = {2'h0, upper_mask_3, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_59 = _f3_fetch_bundle_sfb_masks_3_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_60 = {1'h0, upper_mask_3, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_61 = _f3_fetch_bundle_sfb_masks_3_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_62 = {upper_mask_3, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_63 = _f3_fetch_bundle_sfb_masks_3_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_64 = _f3_fetch_bundle_sfb_masks_3_T_33 \| _f3_fetch_bundle_sfb_masks_3_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_65 = _f3_fetch_bundle_sfb_masks_3_T_64 \| _f3_fetch_bundle_sfb_masks_3_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_66 = _f3_fetch_bundle_sfb_masks_3_T_65 \| _f3_fetch_bundle_sfb_masks_3_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_67 = _f3_fetch_bundle_sfb_masks_3_T_66 \| _f3_fetch_bundle_sfb_masks_3_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_68 = _f3_fetch_bundle_sfb_masks_3_T_67 \| _f3_fetch_bundle_sfb_masks_3_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_69 = _f3_fetch_bundle_sfb_masks_3_T_68 \| _f3_fetch_bundle_sfb_masks_3_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_70 = _f3_fetch_bundle_sfb_masks_3_T_69 \| _f3_fetch_bundle_sfb_masks_3_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_71 = _f3_fetch_bundle_sfb_masks_3_T_70 \| _f3_fetch_bundle_sfb_masks_3_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_72 = _f3_fetch_bundle_sfb_masks_3_T_71 \| _f3_fetch_bundle_sfb_masks_3_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_73 = _f3_fetch_bundle_sfb_masks_3_T_72 \| _f3_fetch_bundle_sfb_masks_3_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_74 = _f3_fetch_bundle_sfb_masks_3_T_73 \| _f3_fetch_bundle_sfb_masks_3_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_75 = _f3_fetch_bundle_sfb_masks_3_T_74 \| _f3_fetch_bundle_sfb_masks_3_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_76 = _f3_fetch_bundle_sfb_masks_3_T_75 \| _f3_fetch_bundle_sfb_masks_3_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_77 = _f3_fetch_bundle_sfb_masks_3_T_76 \| _f3_fetch_bundle_sfb_masks_3_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_78 = _f3_fetch_bundle_sfb_masks_3_T_77 \| _f3_fetch_bundle_sfb_masks_3_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_79 = ~_f3_fetch_bundle_sfb_masks_3_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_3_T_80 = _f3_fetch_bundle_sfb_masks_3_T_79 & 16'hFFF0; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_3 = _f3_fetch_bundle_sfb_masks_3_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_3_T_1 = _f3_fetch_bundle_shadowable_mask_3_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_3_T_2 = _f3_fetch_bundle_shadowable_mask_3_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_3_T_3 = ~_f3_fetch_bundle_shadowable_mask_3_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_3_T_5 = _f3_fetch_bundle_shadowable_mask_3_T_3 & _f3_fetch_bundle_shadowable_mask_3_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_3_T_6 = ~f3_mask_3; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_3_T_7 = brsigs_3_shadowable \| _f3_fetch_bundle_shadowable_mask_3_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_3_T_8 = _f3_fetch_bundle_shadowable_mask_3_T_5 & _f3_fetch_bundle_shadowable_mask_3_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_3 = _f3_fetch_bundle_shadowable_mask_3_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_3 = offset_from_aligned_pc_3[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_3_T_2 = _f3_redirects_3_T \| _f3_redirects_3_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_32 = brsigs_3_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_3_T_3; // @[frontend.scala:733:26] assign _f3_redirects_3_T_3 = _GEN_32; // @[frontend.scala:733:26] wire _f3_br_mask_3_T; // @[frontend.scala:736:56] assign _f3_br_mask_3_T = _GEN_32; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_3_T_4 = _f3_redirects_3_T_3 & _f3_bpd_resp_io_deq_bits_preds_3_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_3_T_5 = _f3_redirects_3_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_3_T_6 = _f3_redirects_3_T_2 \| _f3_redirects_3_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_3_T_7 = f3_mask_3 & _f3_redirects_3_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_3 = _f3_redirects_3_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_3_T_1 = f3_mask_3 & _f3_br_mask_3_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_3 = _f3_br_mask_3_T_1; // @[frontend.scala:571:29, :736:37] wire _T_31 = _T_30 \| f3_redirects_3; // @[frontend.scala:565:29, :744:39] wire _T_43 = f3_bank_mask[0] ? ~(bank_mask_2 & (&(bank_insts_2[1:0]))) & (&(bank_insts_3[1:0])) : f3_prev_is_half; // @[frontend.scala:190:10, :589:32, :592:{32,38}, :599:26, :600:26, :724:58, :746:40, :747:28, :748:{8,33,69}] assign f3_fetch_bundle_edge_inst_1 = _T_43; // @[frontend.scala:569:29, :747:28] wire _offset_from_aligned_pc_T_22; // @[frontend.scala:710:31] assign _offset_from_aligned_pc_T_22 = _T_43; // @[frontend.scala:710:31, :747:28] wire [63:0] bank_data_1 = _f3_io_deq_bits_data[127:64]; // @[frontend.scala:516:11, :598:29] wire _bank_mask_0_T_9; // @[frontend.scala:689:71] wire _bank_mask_1_T_9; // @[frontend.scala:689:71] wire _bank_mask_2_T_9; // @[frontend.scala:689:71] wire _bank_mask_3_T_9; // @[frontend.scala:689:71] wire bank_mask_1_0; // @[frontend.scala:599:26] wire bank_mask_1_1; // @[frontend.scala:599:26] wire bank_mask_1_2; // @[frontend.scala:599:26] wire bank_mask_1_3; // @[frontend.scala:599:26] wire [31:0] bank_insts_1_0; // @[frontend.scala:600:26] wire [31:0] bank_insts_1_1; // @[frontend.scala:600:26] wire [31:0] bank_insts_1_2; // @[frontend.scala:600:26] wire [31:0] bank_insts_1_3; // @[frontend.scala:600:26] assign f3_ret_mask_4 = brsigs_4_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_4 = brsigs_4_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_4 = brsigs_4_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_4_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_4_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_4_target; // @[frontend.scala:613:24] wire brsigs_4_shadowable; // @[frontend.scala:613:24] wire [15:0] _inst0_T_1 = bank_data_1[15:0]; // @[frontend.scala:598:29, :615:34] wire [15:0] _inst0b_T = bank_data_1[15:0]; // @[frontend.scala:598:29, :615:34, :637:43] wire [31:0] inst0_1 = {_inst0_T_1, f3_prev_half}; // @[frontend.scala:587:28, :615:{24,34}] wire [31:0] inst1_1 = bank_data_1[31:0]; // @[frontend.scala:598:29, :616:30] wire [31:0] exp_inst0_1 = _exp_inst0_rvc_exp_1_io_rvc ? _exp_inst0_rvc_exp_1_io_out_bits : inst0_1; // @[frontend.scala:615:24] wire [31:0] exp_inst1_1 = _exp_inst1_rvc_exp_1_io_rvc ? _exp_inst1_rvc_exp_1_io_out_bits : inst1_1; // @[frontend.scala:616:30] wire [40:0] _GEN_33 = _GEN_16 + 41'h8; // @[frontend.scala:619:34] wire [40:0] _pc0_T_3; // @[frontend.scala:619:34] assign _pc0_T_3 = _GEN_33; // @[frontend.scala:619:34] wire [40:0] _pc1_T_1; // @[frontend.scala:620:34] assign _pc1_T_1 = _GEN_33; // @[frontend.scala:619:34, :620:34] wire [39:0] _pc0_T_4 = _pc0_T_3[39:0]; // @[frontend.scala:619:34] wire [40:0] _pc0_T_5 = {1'h0, _pc0_T_4} - 41'h2; // @[frontend.scala:619:{34,69}] wire [39:0] pc0_1 = _pc0_T_5[39:0]; // @[frontend.scala:619:69] wire [39:0] pc1_1 = _pc1_T_1[39:0]; // @[frontend.scala:620:34] wire [31:0] inst0b = {_inst0b_T, bank_insts_3[15:0]}; // @[frontend.scala:600:26, :637:{33,43}, :746:40] wire [31:0] exp_inst0b = _exp_inst0b_rvc_exp_io_rvc ? _exp_inst0b_rvc_exp_io_out_bits : inst0b; // @[frontend.scala:637:33] wire [31:0] _GEN_34 = _T_43 ? (f3_bank_mask[0] ? inst0b : inst0_1) : inst1_1; // @[frontend.scala:190:10, :615:24, :616:30, :629:34, :630:40, :637:33, :643:38, :644:44, :651:40, :724:58, :747:28] assign f3_fetch_bundle_insts_4 = _GEN_34; // @[frontend.scala:569:29, :629:34, :643:38, :651:40] assign bank_insts_1_0 = _GEN_34; // @[frontend.scala:600:26, :629:34, :643:38, :651:40] assign f3_fetch_bundle_exp_insts_4 = _T_43 ? (f3_bank_mask[0] ? exp_inst0b : exp_inst0_1) : exp_inst1_1; // @[frontend.scala:190:10, :569:29, :629:34, :632:40, :643:38, :646:44, :653:40, :724:58, :747:28] assign brsigs_4_shadowable = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_shadowable : _bpd_decoder0_1_io_out_shadowable) : _bpd_decoder1_1_io_out_shadowable; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_sfb_offset_valid = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_sfb_offset_valid : _bpd_decoder0_1_io_out_sfb_offset_valid) : _bpd_decoder1_1_io_out_sfb_offset_valid; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_sfb_offset_bits = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_sfb_offset_bits : _bpd_decoder0_1_io_out_sfb_offset_bits) : _bpd_decoder1_1_io_out_sfb_offset_bits; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_cfi_type = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_cfi_type : _bpd_decoder0_1_io_out_cfi_type) : _bpd_decoder1_1_io_out_cfi_type; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_target = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_target : _bpd_decoder0_1_io_out_target) : _bpd_decoder1_1_io_out_target; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_is_call = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_is_call : _bpd_decoder0_1_io_out_is_call) : _bpd_decoder1_1_io_out_is_call; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_is_ret = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_is_ret : _bpd_decoder0_1_io_out_is_ret) : _bpd_decoder1_1_io_out_is_ret; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] wire [1:0] _f3_is_rvc_4_T = bank_insts_1_0[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_20 = bank_insts_1_0[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_4_T_1 = _f3_is_rvc_4_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_4 = _f3_is_rvc_4_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_0_T_5 = _f3_io_deq_bits_mask[4]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_4_T = _f3_io_deq_bits_mask[4]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_0_T_6 = _f3_io_deq_valid & _bank_mask_0_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_0_T_7 = _bank_mask_0_T_6; // @[frontend.scala:689:{39,62}] wire _bank_mask_0_T_8 = ~_T_31; // @[frontend.scala:689:74, :744:39] assign _bank_mask_0_T_9 = _bank_mask_0_T_7 & _bank_mask_0_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_0 = _bank_mask_0_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_4_T_1 = _f3_io_deq_valid & _f3_mask_4_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_4_T_2 = _f3_mask_4_T_1; // @[frontend.scala:690:{39,62}] wire _f3_mask_4_T_3 = ~_T_31; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_4_T_4 = _f3_mask_4_T_2 & _f3_mask_4_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_4 = _f3_mask_4_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_35 = brsigs_4_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_4_T; // @[frontend.scala:691:43] assign _f3_targs_4_T = _GEN_35; // @[frontend.scala:691:43] wire _f3_redirects_4_T_1; // @[frontend.scala:732:56] assign _f3_redirects_4_T_1 = _GEN_35; // @[frontend.scala:691:43, :732:56] assign _f3_targs_4_T_1 = _f3_targs_4_T ? _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_bits : brsigs_4_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_4 = _f3_targs_4_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_36 = brsigs_4_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_4_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_4_T = _GEN_36; // @[frontend.scala:696:49] wire _f3_redirects_4_T; // @[frontend.scala:732:25] assign _f3_redirects_4_T = _GEN_36; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_4_T_1 = _f3_btb_mispredicts_4_T; // @[frontend.scala:696:{49,61}] wire _f3_btb_mispredicts_4_T_2 = _f3_btb_mispredicts_4_T_1 & _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_4_T_3 = _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_bits != brsigs_4_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_4_T_4 = _f3_btb_mispredicts_4_T_2 & _f3_btb_mispredicts_4_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_4 = _f3_btb_mispredicts_4_T_4; // @[frontend.scala:575:32, :697:61] wire _f3_npc_plus4_mask_4_T = ~f3_is_rvc_4; // @[frontend.scala:564:29, :703:9] wire _f3_npc_plus4_mask_4_T_1 = ~_T_43; // @[frontend.scala:703:26, :747:28] assign _f3_npc_plus4_mask_4_T_2 = _f3_npc_plus4_mask_4_T & _f3_npc_plus4_mask_4_T_1; // @[frontend.scala:703:{9,23,26}] assign f3_npc_plus4_mask_4 = _f3_npc_plus4_mask_4_T_2; // @[frontend.scala:574:31, :703:23] wire [7:0] _offset_from_aligned_pc_T_20 = {2'h0, brsigs_4_sfb_offset_bits} + 8'h8; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_21 = _offset_from_aligned_pc_T_20[6:0]; // @[frontend.scala:708:50] wire [1:0] _offset_from_aligned_pc_T_23 = {_offset_from_aligned_pc_T_22, 1'h0}; // @[frontend.scala:710:{12,31}] wire [7:0] _offset_from_aligned_pc_T_24 = {1'h0, _offset_from_aligned_pc_T_21} - {6'h0, _offset_from_aligned_pc_T_23}; // @[frontend.scala:708:50, :709:32, :710:12] wire [6:0] offset_from_aligned_pc_4 = _offset_from_aligned_pc_T_24[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_4; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_16 = offset_from_aligned_pc_4[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_17 = 32'h1 << _upper_mask_T_16; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_19 = {7'h0, _upper_mask_T_17} << _upper_mask_T_18; // @[OneHot.scala:58:35] assign upper_mask_4 = _upper_mask_T_19[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_4_T = f3_mask_4 & brsigs_4_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_4_T_2 = offset_from_aligned_pc_4 <= {1'h0, _f3_fetch_bundle_sfbs_4_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_4_T_3 = _f3_fetch_bundle_sfbs_4_T & _f3_fetch_bundle_sfbs_4_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_4 = _f3_fetch_bundle_sfbs_4_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_4_T_32 = {1'h0, upper_mask_4}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_33 = _f3_fetch_bundle_sfb_masks_4_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_4_T_34 = {upper_mask_4, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_35 = _f3_fetch_bundle_sfb_masks_4_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_4_T_36 = {1'h0, upper_mask_4, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_37 = _f3_fetch_bundle_sfb_masks_4_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_4_T_38 = {upper_mask_4, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_39 = _f3_fetch_bundle_sfb_masks_4_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_40 = {3'h0, upper_mask_4, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_41 = _f3_fetch_bundle_sfb_masks_4_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_42 = {2'h0, upper_mask_4, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_43 = _f3_fetch_bundle_sfb_masks_4_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_44 = {1'h0, upper_mask_4, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_45 = _f3_fetch_bundle_sfb_masks_4_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_46 = {upper_mask_4, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_47 = _f3_fetch_bundle_sfb_masks_4_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_48 = {7'h0, upper_mask_4, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_49 = _f3_fetch_bundle_sfb_masks_4_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_50 = {6'h0, upper_mask_4, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_51 = _f3_fetch_bundle_sfb_masks_4_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_52 = {5'h0, upper_mask_4, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_53 = _f3_fetch_bundle_sfb_masks_4_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_54 = {4'h0, upper_mask_4, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_55 = _f3_fetch_bundle_sfb_masks_4_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_56 = {3'h0, upper_mask_4, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_57 = _f3_fetch_bundle_sfb_masks_4_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_58 = {2'h0, upper_mask_4, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_59 = _f3_fetch_bundle_sfb_masks_4_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_60 = {1'h0, upper_mask_4, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_61 = _f3_fetch_bundle_sfb_masks_4_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_62 = {upper_mask_4, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_63 = _f3_fetch_bundle_sfb_masks_4_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_64 = _f3_fetch_bundle_sfb_masks_4_T_33 \| _f3_fetch_bundle_sfb_masks_4_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_65 = _f3_fetch_bundle_sfb_masks_4_T_64 \| _f3_fetch_bundle_sfb_masks_4_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_66 = _f3_fetch_bundle_sfb_masks_4_T_65 \| _f3_fetch_bundle_sfb_masks_4_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_67 = _f3_fetch_bundle_sfb_masks_4_T_66 \| _f3_fetch_bundle_sfb_masks_4_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_68 = _f3_fetch_bundle_sfb_masks_4_T_67 \| _f3_fetch_bundle_sfb_masks_4_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_69 = _f3_fetch_bundle_sfb_masks_4_T_68 \| _f3_fetch_bundle_sfb_masks_4_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_70 = _f3_fetch_bundle_sfb_masks_4_T_69 \| _f3_fetch_bundle_sfb_masks_4_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_71 = _f3_fetch_bundle_sfb_masks_4_T_70 \| _f3_fetch_bundle_sfb_masks_4_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_72 = _f3_fetch_bundle_sfb_masks_4_T_71 \| _f3_fetch_bundle_sfb_masks_4_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_73 = _f3_fetch_bundle_sfb_masks_4_T_72 \| _f3_fetch_bundle_sfb_masks_4_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_74 = _f3_fetch_bundle_sfb_masks_4_T_73 \| _f3_fetch_bundle_sfb_masks_4_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_75 = _f3_fetch_bundle_sfb_masks_4_T_74 \| _f3_fetch_bundle_sfb_masks_4_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_76 = _f3_fetch_bundle_sfb_masks_4_T_75 \| _f3_fetch_bundle_sfb_masks_4_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_77 = _f3_fetch_bundle_sfb_masks_4_T_76 \| _f3_fetch_bundle_sfb_masks_4_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_78 = _f3_fetch_bundle_sfb_masks_4_T_77 \| _f3_fetch_bundle_sfb_masks_4_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_79 = ~_f3_fetch_bundle_sfb_masks_4_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_4_T_80 = _f3_fetch_bundle_sfb_masks_4_T_79 & 16'hFFE0; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_4 = _f3_fetch_bundle_sfb_masks_4_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_4_T_1 = _f3_fetch_bundle_shadowable_mask_4_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_4_T_2 = _f3_fetch_bundle_shadowable_mask_4_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_4_T_3 = ~_f3_fetch_bundle_shadowable_mask_4_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_4_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_5_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_6_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_7_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_4_T_5 = _f3_fetch_bundle_shadowable_mask_4_T_3 & _f3_fetch_bundle_shadowable_mask_4_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_4_T_6 = ~f3_mask_4; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_4_T_7 = brsigs_4_shadowable \| _f3_fetch_bundle_shadowable_mask_4_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_4_T_8 = _f3_fetch_bundle_shadowable_mask_4_T_5 & _f3_fetch_bundle_shadowable_mask_4_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_4 = _f3_fetch_bundle_shadowable_mask_4_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_4 = offset_from_aligned_pc_4[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_4_T_2 = _f3_redirects_4_T \| _f3_redirects_4_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_37 = brsigs_4_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_4_T_3; // @[frontend.scala:733:26] assign _f3_redirects_4_T_3 = _GEN_37; // @[frontend.scala:733:26] wire _f3_br_mask_4_T; // @[frontend.scala:736:56] assign _f3_br_mask_4_T = _GEN_37; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_4_T_4 = _f3_redirects_4_T_3 & _f3_bpd_resp_io_deq_bits_preds_4_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_4_T_5 = _f3_redirects_4_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_4_T_6 = _f3_redirects_4_T_2 \| _f3_redirects_4_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_4_T_7 = f3_mask_4 & _f3_redirects_4_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_4 = _f3_redirects_4_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_4_T_1 = f3_mask_4 & _f3_br_mask_4_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_4 = _f3_br_mask_4_T_1; // @[frontend.scala:571:29, :736:37] wire _T_48 = _T_31 \| f3_redirects_4; // @[frontend.scala:565:29, :744:39] wire _valid_T_25; // @[frontend.scala:675:38] wire valid_5; // @[frontend.scala:605:23] assign f3_ret_mask_5 = brsigs_5_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_5 = brsigs_5_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_5 = brsigs_5_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_5_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_5_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_5_target; // @[frontend.scala:613:24] wire brsigs_5_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_4; // @[frontend.scala:674:29] assign f3_fetch_bundle_insts_5 = inst_3; // @[frontend.scala:569:29, :660:24] assign bank_insts_1_1 = inst_3; // @[frontend.scala:600:26, :660:24] assign exp_inst_3 = _exp_inst_rvc_exp_3_io_rvc ? _exp_inst_rvc_exp_3_io_out_bits : inst_3; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_5 = exp_inst_3; // @[frontend.scala:569:29] wire [40:0] _pc_T_3 = _GEN_16 + 41'hA; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_3 = _pc_T_3[39:0]; // @[frontend.scala:662:32] assign _inst_T_4 = bank_data_1[47:16]; // @[frontend.scala:598:29, :674:29] assign inst_3 = _inst_T_4; // @[frontend.scala:660:24, :674:29] wire _valid_T_21 = _valid_T_20 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_22 = ~_valid_T_21; // @[frontend.scala:592:38, :675:59] wire _valid_T_23 = bank_mask_1_0 & _valid_T_22; // @[frontend.scala:599:26, :675:{56,59}] wire _valid_T_24 = ~_valid_T_23; // @[frontend.scala:675:{41,56}] assign _valid_T_25 = _T_43 \| _valid_T_24; // @[frontend.scala:675:{38,41}, :747:28] assign valid_5 = _valid_T_25; // @[frontend.scala:605:23, :675:38] wire [1:0] _f3_is_rvc_5_T = bank_insts_1_1[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_26 = bank_insts_1_1[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_5_T_1 = _f3_is_rvc_5_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_5 = _f3_is_rvc_5_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_1_T_5 = _f3_io_deq_bits_mask[5]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_5_T = _f3_io_deq_bits_mask[5]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_1_T_6 = _f3_io_deq_valid & _bank_mask_1_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_1_T_7 = _bank_mask_1_T_6 & valid_5; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_1_T_8 = ~_T_48; // @[frontend.scala:689:74, :744:39] assign _bank_mask_1_T_9 = _bank_mask_1_T_7 & _bank_mask_1_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_1 = _bank_mask_1_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_5_T_1 = _f3_io_deq_valid & _f3_mask_5_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_5_T_2 = _f3_mask_5_T_1 & valid_5; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_5_T_3 = ~_T_48; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_5_T_4 = _f3_mask_5_T_2 & _f3_mask_5_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_5 = _f3_mask_5_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_38 = brsigs_5_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_5_T; // @[frontend.scala:691:43] assign _f3_targs_5_T = _GEN_38; // @[frontend.scala:691:43] wire _f3_redirects_5_T_1; // @[frontend.scala:732:56] assign _f3_redirects_5_T_1 = _GEN_38; // @[frontend.scala:691:43, :732:56] assign _f3_targs_5_T_1 = _f3_targs_5_T ? _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_bits : brsigs_5_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_5 = _f3_targs_5_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_39 = brsigs_5_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_5_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_5_T = _GEN_39; // @[frontend.scala:696:49] wire _f3_redirects_5_T; // @[frontend.scala:732:25] assign _f3_redirects_5_T = _GEN_39; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_5_T_1 = _f3_btb_mispredicts_5_T & valid_5; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_5_T_2 = _f3_btb_mispredicts_5_T_1 & _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_5_T_3 = _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_bits != brsigs_5_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_5_T_4 = _f3_btb_mispredicts_5_T_2 & _f3_btb_mispredicts_5_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_5 = _f3_btb_mispredicts_5_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_5_T = ~f3_is_rvc_5; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_5 = _f3_npc_plus4_mask_5_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_25 = {2'h0, brsigs_5_sfb_offset_bits} + 8'hA; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_26 = _offset_from_aligned_pc_T_25[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_29 = {1'h0, _offset_from_aligned_pc_T_26}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_5 = _offset_from_aligned_pc_T_29[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_5; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_20 = offset_from_aligned_pc_5[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_21 = 32'h1 << _upper_mask_T_20; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_23 = {7'h0, _upper_mask_T_21} << _upper_mask_T_22; // @[OneHot.scala:58:35] assign upper_mask_5 = _upper_mask_T_23[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_5_T = f3_mask_5 & brsigs_5_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_5_T_2 = offset_from_aligned_pc_5 <= {1'h0, _f3_fetch_bundle_sfbs_5_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_5_T_3 = _f3_fetch_bundle_sfbs_5_T & _f3_fetch_bundle_sfbs_5_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_5 = _f3_fetch_bundle_sfbs_5_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_5_T_32 = {1'h0, upper_mask_5}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_33 = _f3_fetch_bundle_sfb_masks_5_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_5_T_34 = {upper_mask_5, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_35 = _f3_fetch_bundle_sfb_masks_5_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_5_T_36 = {1'h0, upper_mask_5, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_37 = _f3_fetch_bundle_sfb_masks_5_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_5_T_38 = {upper_mask_5, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_39 = _f3_fetch_bundle_sfb_masks_5_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_40 = {3'h0, upper_mask_5, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_41 = _f3_fetch_bundle_sfb_masks_5_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_42 = {2'h0, upper_mask_5, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_43 = _f3_fetch_bundle_sfb_masks_5_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_44 = {1'h0, upper_mask_5, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_45 = _f3_fetch_bundle_sfb_masks_5_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_46 = {upper_mask_5, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_47 = _f3_fetch_bundle_sfb_masks_5_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_48 = {7'h0, upper_mask_5, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_49 = _f3_fetch_bundle_sfb_masks_5_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_50 = {6'h0, upper_mask_5, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_51 = _f3_fetch_bundle_sfb_masks_5_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_52 = {5'h0, upper_mask_5, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_53 = _f3_fetch_bundle_sfb_masks_5_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_54 = {4'h0, upper_mask_5, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_55 = _f3_fetch_bundle_sfb_masks_5_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_56 = {3'h0, upper_mask_5, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_57 = _f3_fetch_bundle_sfb_masks_5_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_58 = {2'h0, upper_mask_5, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_59 = _f3_fetch_bundle_sfb_masks_5_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_60 = {1'h0, upper_mask_5, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_61 = _f3_fetch_bundle_sfb_masks_5_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_62 = {upper_mask_5, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_63 = _f3_fetch_bundle_sfb_masks_5_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_64 = _f3_fetch_bundle_sfb_masks_5_T_33 \| _f3_fetch_bundle_sfb_masks_5_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_65 = _f3_fetch_bundle_sfb_masks_5_T_64 \| _f3_fetch_bundle_sfb_masks_5_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_66 = _f3_fetch_bundle_sfb_masks_5_T_65 \| _f3_fetch_bundle_sfb_masks_5_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_67 = _f3_fetch_bundle_sfb_masks_5_T_66 \| _f3_fetch_bundle_sfb_masks_5_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_68 = _f3_fetch_bundle_sfb_masks_5_T_67 \| _f3_fetch_bundle_sfb_masks_5_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_69 = _f3_fetch_bundle_sfb_masks_5_T_68 \| _f3_fetch_bundle_sfb_masks_5_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_70 = _f3_fetch_bundle_sfb_masks_5_T_69 \| _f3_fetch_bundle_sfb_masks_5_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_71 = _f3_fetch_bundle_sfb_masks_5_T_70 \| _f3_fetch_bundle_sfb_masks_5_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_72 = _f3_fetch_bundle_sfb_masks_5_T_71 \| _f3_fetch_bundle_sfb_masks_5_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_73 = _f3_fetch_bundle_sfb_masks_5_T_72 \| _f3_fetch_bundle_sfb_masks_5_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_74 = _f3_fetch_bundle_sfb_masks_5_T_73 \| _f3_fetch_bundle_sfb_masks_5_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_75 = _f3_fetch_bundle_sfb_masks_5_T_74 \| _f3_fetch_bundle_sfb_masks_5_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_76 = _f3_fetch_bundle_sfb_masks_5_T_75 \| _f3_fetch_bundle_sfb_masks_5_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_77 = _f3_fetch_bundle_sfb_masks_5_T_76 \| _f3_fetch_bundle_sfb_masks_5_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_78 = _f3_fetch_bundle_sfb_masks_5_T_77 \| _f3_fetch_bundle_sfb_masks_5_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_79 = ~_f3_fetch_bundle_sfb_masks_5_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_5_T_80 = _f3_fetch_bundle_sfb_masks_5_T_79 & 16'hFFC0; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_5 = _f3_fetch_bundle_sfb_masks_5_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_5_T_1 = _f3_fetch_bundle_shadowable_mask_5_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_5_T_2 = _f3_fetch_bundle_shadowable_mask_5_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_5_T_3 = ~_f3_fetch_bundle_shadowable_mask_5_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_5_T_5 = _f3_fetch_bundle_shadowable_mask_5_T_3 & _f3_fetch_bundle_shadowable_mask_5_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_5_T_6 = ~f3_mask_5; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_5_T_7 = brsigs_5_shadowable \| _f3_fetch_bundle_shadowable_mask_5_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_5_T_8 = _f3_fetch_bundle_shadowable_mask_5_T_5 & _f3_fetch_bundle_shadowable_mask_5_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_5 = _f3_fetch_bundle_shadowable_mask_5_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_5 = offset_from_aligned_pc_5[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_5_T_2 = _f3_redirects_5_T \| _f3_redirects_5_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_40 = brsigs_5_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_5_T_3; // @[frontend.scala:733:26] assign _f3_redirects_5_T_3 = _GEN_40; // @[frontend.scala:733:26] wire _f3_br_mask_5_T; // @[frontend.scala:736:56] assign _f3_br_mask_5_T = _GEN_40; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_5_T_4 = _f3_redirects_5_T_3 & _f3_bpd_resp_io_deq_bits_preds_5_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_5_T_5 = _f3_redirects_5_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_5_T_6 = _f3_redirects_5_T_2 \| _f3_redirects_5_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_5_T_7 = f3_mask_5 & _f3_redirects_5_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_5 = _f3_redirects_5_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_5_T_1 = f3_mask_5 & _f3_br_mask_5_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_5 = _f3_br_mask_5_T_1; // @[frontend.scala:571:29, :736:37] wire _T_49 = _T_48 \| f3_redirects_5; // @[frontend.scala:565:29, :744:39] wire _valid_T_30; // @[frontend.scala:682:20] wire valid_6; // @[frontend.scala:605:23] assign f3_ret_mask_6 = brsigs_6_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_6 = brsigs_6_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_6 = brsigs_6_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_6_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_6_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_6_target; // @[frontend.scala:613:24] wire brsigs_6_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_5; // @[frontend.scala:681:29] assign f3_fetch_bundle_insts_6 = inst_4; // @[frontend.scala:569:29, :660:24] assign bank_insts_1_2 = inst_4; // @[frontend.scala:600:26, :660:24] assign exp_inst_4 = _exp_inst_rvc_exp_4_io_rvc ? _exp_inst_rvc_exp_4_io_out_bits : inst_4; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_6 = exp_inst_4; // @[frontend.scala:569:29] wire [40:0] _pc_T_4 = _GEN_16 + 41'hC; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_4 = _pc_T_4[39:0]; // @[frontend.scala:662:32] assign _inst_T_5 = bank_data_1[63:32]; // @[frontend.scala:598:29, :681:29] assign inst_4 = _inst_T_5; // @[frontend.scala:660:24, :681:29] wire _valid_T_27 = _valid_T_26 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_28 = ~_valid_T_27; // @[frontend.scala:592:38, :682:40] wire _valid_T_29 = bank_mask_1_1 & _valid_T_28; // @[frontend.scala:599:26, :682:{37,40}] assign _valid_T_30 = ~_valid_T_29; // @[frontend.scala:682:{20,37}] assign valid_6 = _valid_T_30; // @[frontend.scala:605:23, :682:20] wire [1:0] _f3_is_rvc_6_T = bank_insts_1_2[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_31 = bank_insts_1_2[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_6_T_1 = _f3_is_rvc_6_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_6 = _f3_is_rvc_6_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_2_T_5 = _f3_io_deq_bits_mask[6]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_6_T = _f3_io_deq_bits_mask[6]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_2_T_6 = _f3_io_deq_valid & _bank_mask_2_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_2_T_7 = _bank_mask_2_T_6 & valid_6; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_2_T_8 = ~_T_49; // @[frontend.scala:689:74, :744:39] assign _bank_mask_2_T_9 = _bank_mask_2_T_7 & _bank_mask_2_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_2 = _bank_mask_2_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_6_T_1 = _f3_io_deq_valid & _f3_mask_6_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_6_T_2 = _f3_mask_6_T_1 & valid_6; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_6_T_3 = ~_T_49; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_6_T_4 = _f3_mask_6_T_2 & _f3_mask_6_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_6 = _f3_mask_6_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_41 = brsigs_6_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_6_T; // @[frontend.scala:691:43] assign _f3_targs_6_T = _GEN_41; // @[frontend.scala:691:43] wire _f3_redirects_6_T_1; // @[frontend.scala:732:56] assign _f3_redirects_6_T_1 = _GEN_41; // @[frontend.scala:691:43, :732:56] assign _f3_targs_6_T_1 = _f3_targs_6_T ? _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_bits : brsigs_6_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_6 = _f3_targs_6_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_42 = brsigs_6_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_6_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_6_T = _GEN_42; // @[frontend.scala:696:49] wire _f3_redirects_6_T; // @[frontend.scala:732:25] assign _f3_redirects_6_T = _GEN_42; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_6_T_1 = _f3_btb_mispredicts_6_T & valid_6; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_6_T_2 = _f3_btb_mispredicts_6_T_1 & _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_6_T_3 = _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_bits != brsigs_6_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_6_T_4 = _f3_btb_mispredicts_6_T_2 & _f3_btb_mispredicts_6_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_6 = _f3_btb_mispredicts_6_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_6_T = ~f3_is_rvc_6; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_6 = _f3_npc_plus4_mask_6_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_30 = {2'h0, brsigs_6_sfb_offset_bits} + 8'hC; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_31 = _offset_from_aligned_pc_T_30[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_34 = {1'h0, _offset_from_aligned_pc_T_31}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_6 = _offset_from_aligned_pc_T_34[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_6; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_24 = offset_from_aligned_pc_6[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_25 = 32'h1 << _upper_mask_T_24; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_27 = {7'h0, _upper_mask_T_25} << _upper_mask_T_26; // @[OneHot.scala:58:35] assign upper_mask_6 = _upper_mask_T_27[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_6_T = f3_mask_6 & brsigs_6_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_6_T_2 = offset_from_aligned_pc_6 <= {1'h0, _f3_fetch_bundle_sfbs_6_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_6_T_3 = _f3_fetch_bundle_sfbs_6_T & _f3_fetch_bundle_sfbs_6_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_6 = _f3_fetch_bundle_sfbs_6_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_6_T_32 = {1'h0, upper_mask_6}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_33 = _f3_fetch_bundle_sfb_masks_6_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_6_T_34 = {upper_mask_6, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_35 = _f3_fetch_bundle_sfb_masks_6_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_6_T_36 = {1'h0, upper_mask_6, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_37 = _f3_fetch_bundle_sfb_masks_6_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_6_T_38 = {upper_mask_6, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_39 = _f3_fetch_bundle_sfb_masks_6_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_40 = {3'h0, upper_mask_6, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_41 = _f3_fetch_bundle_sfb_masks_6_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_42 = {2'h0, upper_mask_6, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_43 = _f3_fetch_bundle_sfb_masks_6_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_44 = {1'h0, upper_mask_6, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_45 = _f3_fetch_bundle_sfb_masks_6_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_46 = {upper_mask_6, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_47 = _f3_fetch_bundle_sfb_masks_6_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_48 = {7'h0, upper_mask_6, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_49 = _f3_fetch_bundle_sfb_masks_6_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_50 = {6'h0, upper_mask_6, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_51 = _f3_fetch_bundle_sfb_masks_6_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_52 = {5'h0, upper_mask_6, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_53 = _f3_fetch_bundle_sfb_masks_6_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_54 = {4'h0, upper_mask_6, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_55 = _f3_fetch_bundle_sfb_masks_6_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_56 = {3'h0, upper_mask_6, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_57 = _f3_fetch_bundle_sfb_masks_6_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_58 = {2'h0, upper_mask_6, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_59 = _f3_fetch_bundle_sfb_masks_6_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_60 = {1'h0, upper_mask_6, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_61 = _f3_fetch_bundle_sfb_masks_6_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_62 = {upper_mask_6, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_63 = _f3_fetch_bundle_sfb_masks_6_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_64 = _f3_fetch_bundle_sfb_masks_6_T_33 \| _f3_fetch_bundle_sfb_masks_6_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_65 = _f3_fetch_bundle_sfb_masks_6_T_64 \| _f3_fetch_bundle_sfb_masks_6_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_66 = _f3_fetch_bundle_sfb_masks_6_T_65 \| _f3_fetch_bundle_sfb_masks_6_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_67 = _f3_fetch_bundle_sfb_masks_6_T_66 \| _f3_fetch_bundle_sfb_masks_6_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_68 = _f3_fetch_bundle_sfb_masks_6_T_67 \| _f3_fetch_bundle_sfb_masks_6_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_69 = _f3_fetch_bundle_sfb_masks_6_T_68 \| _f3_fetch_bundle_sfb_masks_6_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_70 = _f3_fetch_bundle_sfb_masks_6_T_69 \| _f3_fetch_bundle_sfb_masks_6_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_71 = _f3_fetch_bundle_sfb_masks_6_T_70 \| _f3_fetch_bundle_sfb_masks_6_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_72 = _f3_fetch_bundle_sfb_masks_6_T_71 \| _f3_fetch_bundle_sfb_masks_6_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_73 = _f3_fetch_bundle_sfb_masks_6_T_72 \| _f3_fetch_bundle_sfb_masks_6_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_74 = _f3_fetch_bundle_sfb_masks_6_T_73 \| _f3_fetch_bundle_sfb_masks_6_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_75 = _f3_fetch_bundle_sfb_masks_6_T_74 \| _f3_fetch_bundle_sfb_masks_6_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_76 = _f3_fetch_bundle_sfb_masks_6_T_75 \| _f3_fetch_bundle_sfb_masks_6_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_77 = _f3_fetch_bundle_sfb_masks_6_T_76 \| _f3_fetch_bundle_sfb_masks_6_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_78 = _f3_fetch_bundle_sfb_masks_6_T_77 \| _f3_fetch_bundle_sfb_masks_6_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_79 = ~_f3_fetch_bundle_sfb_masks_6_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_6_T_80 = _f3_fetch_bundle_sfb_masks_6_T_79 & 16'hFF80; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_6 = _f3_fetch_bundle_sfb_masks_6_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_6_T_1 = _f3_fetch_bundle_shadowable_mask_6_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_6_T_2 = _f3_fetch_bundle_shadowable_mask_6_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_6_T_3 = ~_f3_fetch_bundle_shadowable_mask_6_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_6_T_5 = _f3_fetch_bundle_shadowable_mask_6_T_3 & _f3_fetch_bundle_shadowable_mask_6_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_6_T_6 = ~f3_mask_6; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_6_T_7 = brsigs_6_shadowable \| _f3_fetch_bundle_shadowable_mask_6_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_6_T_8 = _f3_fetch_bundle_shadowable_mask_6_T_5 & _f3_fetch_bundle_shadowable_mask_6_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_6 = _f3_fetch_bundle_shadowable_mask_6_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_6 = offset_from_aligned_pc_6[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_6_T_2 = _f3_redirects_6_T \| _f3_redirects_6_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_43 = brsigs_6_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_6_T_3; // @[frontend.scala:733:26] assign _f3_redirects_6_T_3 = _GEN_43; // @[frontend.scala:733:26] wire _f3_br_mask_6_T; // @[frontend.scala:736:56] assign _f3_br_mask_6_T = _GEN_43; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_6_T_4 = _f3_redirects_6_T_3 & _f3_bpd_resp_io_deq_bits_preds_6_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_6_T_5 = _f3_redirects_6_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_6_T_6 = _f3_redirects_6_T_2 \| _f3_redirects_6_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_6_T_7 = f3_mask_6 & _f3_redirects_6_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_6 = _f3_redirects_6_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_6_T_1 = f3_mask_6 & _f3_br_mask_6_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_6 = _f3_br_mask_6_T_1; // @[frontend.scala:571:29, :736:37] wire _T_50 = _T_49 \| f3_redirects_6; // @[frontend.scala:565:29, :744:39] wire _valid_T_39; // @[frontend.scala:678:20] wire valid_7; // @[frontend.scala:605:23] assign f3_ret_mask_7 = brsigs_7_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_7 = brsigs_7_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_7 = brsigs_7_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_7_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_7_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_7_target; // @[frontend.scala:613:24] wire brsigs_7_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_7; // @[frontend.scala:677:23] assign f3_fetch_bundle_insts_7 = inst_5; // @[frontend.scala:569:29, :660:24] assign bank_insts_1_3 = inst_5; // @[frontend.scala:600:26, :660:24] assign exp_inst_5 = _exp_inst_rvc_exp_5_io_rvc ? _exp_inst_rvc_exp_5_io_out_bits : inst_5; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_7 = exp_inst_5; // @[frontend.scala:569:29] wire [40:0] _pc_T_5 = _GEN_16 + 41'hE; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_5 = _pc_T_5[39:0]; // @[frontend.scala:662:32] wire [15:0] _inst_T_6 = bank_data_1[63:48]; // @[frontend.scala:598:29, :677:44] assign _inst_T_7 = {16'h0, _inst_T_6}; // @[frontend.scala:677:{23,44}] assign inst_5 = _inst_T_7; // @[frontend.scala:660:24, :677:23] wire _valid_T_32 = _valid_T_31 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_33 = ~_valid_T_32; // @[frontend.scala:592:38, :678:41] wire _valid_T_34 = bank_mask_1_2 & _valid_T_33; // @[frontend.scala:599:26, :678:{38,41}] wire [1:0] _valid_T_35 = inst_5[1:0]; // @[frontend.scala:592:32, :660:24] wire _valid_T_36 = _valid_T_35 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_37 = ~_valid_T_36; // @[frontend.scala:592:38, :679:13] wire _valid_T_38 = _valid_T_34 \| _valid_T_37; // @[frontend.scala:678:{38,66}, :679:13] assign _valid_T_39 = ~_valid_T_38; // @[frontend.scala:678:{20,66}] assign valid_7 = _valid_T_39; // @[frontend.scala:605:23, :678:20] wire [1:0] _f3_is_rvc_7_T = bank_insts_1_3[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_7_T_1 = _f3_is_rvc_7_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_7 = _f3_is_rvc_7_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_3_T_5 = _f3_io_deq_bits_mask[7]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_7_T = _f3_io_deq_bits_mask[7]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_3_T_6 = _f3_io_deq_valid & _bank_mask_3_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_3_T_7 = _bank_mask_3_T_6 & valid_7; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_3_T_8 = ~_T_50; // @[frontend.scala:689:74, :744:39] assign _bank_mask_3_T_9 = _bank_mask_3_T_7 & _bank_mask_3_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_3 = _bank_mask_3_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_7_T_1 = _f3_io_deq_valid & _f3_mask_7_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_7_T_2 = _f3_mask_7_T_1 & valid_7; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_7_T_3 = ~_T_50; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_7_T_4 = _f3_mask_7_T_2 & _f3_mask_7_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_7 = _f3_mask_7_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_44 = brsigs_7_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_7_T; // @[frontend.scala:691:43] assign _f3_targs_7_T = _GEN_44; // @[frontend.scala:691:43] wire _f3_redirects_7_T_1; // @[frontend.scala:732:56] assign _f3_redirects_7_T_1 = _GEN_44; // @[frontend.scala:691:43, :732:56] assign _f3_targs_7_T_1 = _f3_targs_7_T ? _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_bits : brsigs_7_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_7 = _f3_targs_7_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_45 = brsigs_7_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_7_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_7_T = _GEN_45; // @[frontend.scala:696:49] wire _f3_redirects_7_T; // @[frontend.scala:732:25] assign _f3_redirects_7_T = _GEN_45; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_7_T_1 = _f3_btb_mispredicts_7_T & valid_7; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_7_T_2 = _f3_btb_mispredicts_7_T_1 & _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_7_T_3 = _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_bits != brsigs_7_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_7_T_4 = _f3_btb_mispredicts_7_T_2 & _f3_btb_mispredicts_7_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_7 = _f3_btb_mispredicts_7_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_7_T = ~f3_is_rvc_7; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_7 = _f3_npc_plus4_mask_7_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_35 = {2'h0, brsigs_7_sfb_offset_bits} + 8'hE; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_36 = _offset_from_aligned_pc_T_35[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_39 = {1'h0, _offset_from_aligned_pc_T_36}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_7 = _offset_from_aligned_pc_T_39[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_7; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_28 = offset_from_aligned_pc_7[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_29 = 32'h1 << _upper_mask_T_28; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_31 = {7'h0, _upper_mask_T_29} << _upper_mask_T_30; // @[OneHot.scala:58:35] assign upper_mask_7 = _upper_mask_T_31[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_7_T = f3_mask_7 & brsigs_7_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_7_T_2 = offset_from_aligned_pc_7 <= {1'h0, _f3_fetch_bundle_sfbs_7_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_7_T_3 = _f3_fetch_bundle_sfbs_7_T & _f3_fetch_bundle_sfbs_7_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_7 = _f3_fetch_bundle_sfbs_7_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_7_T_32 = {1'h0, upper_mask_7}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_33 = _f3_fetch_bundle_sfb_masks_7_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_7_T_34 = {upper_mask_7, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_35 = _f3_fetch_bundle_sfb_masks_7_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_7_T_36 = {1'h0, upper_mask_7, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_37 = _f3_fetch_bundle_sfb_masks_7_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_7_T_38 = {upper_mask_7, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_39 = _f3_fetch_bundle_sfb_masks_7_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_40 = {3'h0, upper_mask_7, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_41 = _f3_fetch_bundle_sfb_masks_7_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_42 = {2'h0, upper_mask_7, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_43 = _f3_fetch_bundle_sfb_masks_7_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_44 = {1'h0, upper_mask_7, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_45 = _f3_fetch_bundle_sfb_masks_7_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_46 = {upper_mask_7, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_47 = _f3_fetch_bundle_sfb_masks_7_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_48 = {7'h0, upper_mask_7, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_49 = _f3_fetch_bundle_sfb_masks_7_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_50 = {6'h0, upper_mask_7, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_51 = _f3_fetch_bundle_sfb_masks_7_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_52 = {5'h0, upper_mask_7, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_53 = _f3_fetch_bundle_sfb_masks_7_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_54 = {4'h0, upper_mask_7, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_55 = _f3_fetch_bundle_sfb_masks_7_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_56 = {3'h0, upper_mask_7, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_57 = _f3_fetch_bundle_sfb_masks_7_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_58 = {2'h0, upper_mask_7, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_59 = _f3_fetch_bundle_sfb_masks_7_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_60 = {1'h0, upper_mask_7, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_61 = _f3_fetch_bundle_sfb_masks_7_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_62 = {upper_mask_7, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_63 = _f3_fetch_bundle_sfb_masks_7_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_64 = _f3_fetch_bundle_sfb_masks_7_T_33 \| _f3_fetch_bundle_sfb_masks_7_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_65 = _f3_fetch_bundle_sfb_masks_7_T_64 \| _f3_fetch_bundle_sfb_masks_7_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_66 = _f3_fetch_bundle_sfb_masks_7_T_65 \| _f3_fetch_bundle_sfb_masks_7_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_67 = _f3_fetch_bundle_sfb_masks_7_T_66 \| _f3_fetch_bundle_sfb_masks_7_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_68 = _f3_fetch_bundle_sfb_masks_7_T_67 \| _f3_fetch_bundle_sfb_masks_7_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_69 = _f3_fetch_bundle_sfb_masks_7_T_68 \| _f3_fetch_bundle_sfb_masks_7_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_70 = _f3_fetch_bundle_sfb_masks_7_T_69 \| _f3_fetch_bundle_sfb_masks_7_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_71 = _f3_fetch_bundle_sfb_masks_7_T_70 \| _f3_fetch_bundle_sfb_masks_7_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_72 = _f3_fetch_bundle_sfb_masks_7_T_71 \| _f3_fetch_bundle_sfb_masks_7_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_73 = _f3_fetch_bundle_sfb_masks_7_T_72 \| _f3_fetch_bundle_sfb_masks_7_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_74 = _f3_fetch_bundle_sfb_masks_7_T_73 \| _f3_fetch_bundle_sfb_masks_7_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_75 = _f3_fetch_bundle_sfb_masks_7_T_74 \| _f3_fetch_bundle_sfb_masks_7_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_76 = _f3_fetch_bundle_sfb_masks_7_T_75 \| _f3_fetch_bundle_sfb_masks_7_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_77 = _f3_fetch_bundle_sfb_masks_7_T_76 \| _f3_fetch_bundle_sfb_masks_7_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_78 = _f3_fetch_bundle_sfb_masks_7_T_77 \| _f3_fetch_bundle_sfb_masks_7_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_79 = ~_f3_fetch_bundle_sfb_masks_7_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_7_T_80 = _f3_fetch_bundle_sfb_masks_7_T_79 & 16'hFF00; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_7 = _f3_fetch_bundle_sfb_masks_7_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_7_T_1 = _f3_fetch_bundle_shadowable_mask_7_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_7_T_2 = _f3_fetch_bundle_shadowable_mask_7_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_7_T_3 = ~_f3_fetch_bundle_shadowable_mask_7_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_7_T_5 = _f3_fetch_bundle_shadowable_mask_7_T_3 & _f3_fetch_bundle_shadowable_mask_7_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_7_T_6 = ~f3_mask_7; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_7_T_7 = brsigs_7_shadowable \| _f3_fetch_bundle_shadowable_mask_7_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_7_T_8 = _f3_fetch_bundle_shadowable_mask_7_T_5 & _f3_fetch_bundle_shadowable_mask_7_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_7 = _f3_fetch_bundle_shadowable_mask_7_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_7 = offset_from_aligned_pc_7[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_7_T_2 = _f3_redirects_7_T \| _f3_redirects_7_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_46 = brsigs_7_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_7_T_3; // @[frontend.scala:733:26] assign _f3_redirects_7_T_3 = _GEN_46; // @[frontend.scala:733:26] wire _f3_br_mask_7_T; // @[frontend.scala:736:56] assign _f3_br_mask_7_T = _GEN_46; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_7_T_4 = _f3_redirects_7_T_3 & _f3_bpd_resp_io_deq_bits_preds_7_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_7_T_5 = _f3_redirects_7_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_7_T_6 = _f3_redirects_7_T_2 \| _f3_redirects_7_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_7_T_7 = f3_mask_7 & _f3_redirects_7_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_7 = _f3_redirects_7_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_7_T_1 = f3_mask_7 & _f3_br_mask_7_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_7 = _f3_br_mask_7_T_1; // @[frontend.scala:571:29, :736:37] assign f3_fetch_bundle_end_half_valid = f3_bank_mask[1] ? ~(bank_mask_1_2 & (&(bank_insts_1_2[1:0]))) & (&(bank_insts_1_3[1:0])) : _T_43; // @[frontend.scala:190:10, :569:29, :592:{32,38}, :599:26, :600:26, :724:58, :746:40, :747:28, :748:{8,33,69}] assign f3_fetch_bundle_end_half_bits = f3_bank_mask[1] ? bank_insts_1_3[15:0] : f3_bank_mask[0] ? bank_insts_3[15:0] : f3_prev_half; // @[frontend.scala:190:10, :569:29, :587:28, :600:26, :724:58, :746:40, :750:28] wire [7:0][2:0] _GEN_47 = {{f3_cfi_types_7}, {f3_cfi_types_6}, {f3_cfi_types_5}, {f3_cfi_types_4}, {f3_cfi_types_3}, {f3_cfi_types_2}, {f3_cfi_types_1}, {f3_cfi_types_0}}; // @[frontend.scala:567:29, :755:33] assign f3_fetch_bundle_cfi_type = _GEN_47[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :755:33] wire [7:0] _GEN_48 = {{f3_call_mask_7}, {f3_call_mask_6}, {f3_call_mask_5}, {f3_call_mask_4}, {f3_call_mask_3}, {f3_call_mask_2}, {f3_call_mask_1}, {f3_call_mask_0}}; // @[frontend.scala:572:29, :756:33] assign f3_fetch_bundle_cfi_is_call = _GEN_48[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :756:33] wire [7:0] _GEN_49 = {{f3_ret_mask_7}, {f3_ret_mask_6}, {f3_ret_mask_5}, {f3_ret_mask_4}, {f3_ret_mask_3}, {f3_ret_mask_2}, {f3_ret_mask_1}, {f3_ret_mask_0}}; // @[frontend.scala:573:29, :757:33] assign f3_fetch_bundle_cfi_is_ret = _GEN_49[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :757:33] wire [7:0] _GEN_50 = {{f3_npc_plus4_mask_7}, {f3_npc_plus4_mask_6}, {f3_npc_plus4_mask_5}, {f3_npc_plus4_mask_4}, {f3_npc_plus4_mask_3}, {f3_npc_plus4_mask_2}, {f3_npc_plus4_mask_1}, {f3_npc_plus4_mask_0}}; // @[frontend.scala:574:31, :758:33] assign f3_fetch_bundle_cfi_npc_plus4 = _GEN_50[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :758:33] wire _f4_btb_corrections_io_enq_valid_T = f4_ready & _f3_io_deq_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s7k4z3c : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_40 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a32d128s7k4z3c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a32d128s7k4z3c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready connect nodeIn.b, nodeOut.b connect nodeOut.c, nodeIn.c connect nodeOut.e, nodeIn.e	module TLBuffer_a32d128s7k4z3c( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [127:0] auto_in_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] nodeIn_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [15:0] auto_in_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] nodeIn_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [6:0] auto_in_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [6:0] auto_out_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [6:0] nodeIn_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [6:0] nodeOut_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_source = nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a32d128s7k4z3c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a32d128s7k4z3c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NBDTLB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}[1], miss_rdy : UInt<1>, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} reg sectored_entries : { level : UInt<2>, tag : UInt<27>, data : UInt<34>[4], valid : UInt<1>[4]}[2], clock reg superpage_entries : { level : UInt<2>, tag : UInt<27>, data : UInt<34>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag : UInt<27>, data : UInt<34>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<1>, clock reg r_sectored_hit_addr : UInt<1>, clock reg r_sectored_hit : UInt<1>, clock node priv_s = bits(io.ptw.status.dprv, 0, 0) node priv_uses_vm = leq(io.ptw.status.dprv, UInt<1>(0h1)) node _vm_enabled_T = bits(io.ptw.ptbr.mode, 3, 3) node _vm_enabled_T_1 = and(UInt<1>(0h1), _vm_enabled_T) node _vm_enabled_T_2 = and(_vm_enabled_T_1, priv_uses_vm) node _vm_enabled_T_3 = eq(io.req[0].bits.passthrough, UInt<1>(0h0)) node _vm_enabled_T_4 = and(_vm_enabled_T_2, _vm_enabled_T_3) wire vm_enabled : UInt<1>[1] connect vm_enabled[0], _vm_enabled_T_4 node _vpn_T = bits(io.req[0].bits.vaddr, 38, 12) wire vpn : UInt<27>[1] connect vpn[0], _vpn_T node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled[0], UInt<1>(0h1)) wire _mpu_ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_data_WIRE_1 : UInt<34> connect _mpu_ppn_data_WIRE_1, special_entry.data[0] node _mpu_ppn_data_T = bits(_mpu_ppn_data_WIRE_1, 0, 0) connect _mpu_ppn_data_WIRE.fragmented_superpage, _mpu_ppn_data_T node _mpu_ppn_data_T_1 = bits(_mpu_ppn_data_WIRE_1, 1, 1) connect _mpu_ppn_data_WIRE.c, _mpu_ppn_data_T_1 node _mpu_ppn_data_T_2 = bits(_mpu_ppn_data_WIRE_1, 2, 2) connect _mpu_ppn_data_WIRE.eff, _mpu_ppn_data_T_2 node _mpu_ppn_data_T_3 = bits(_mpu_ppn_data_WIRE_1, 3, 3) connect _mpu_ppn_data_WIRE.paa, _mpu_ppn_data_T_3 node _mpu_ppn_data_T_4 = bits(_mpu_ppn_data_WIRE_1, 4, 4) connect _mpu_ppn_data_WIRE.pal, _mpu_ppn_data_T_4 node _mpu_ppn_data_T_5 = bits(_mpu_ppn_data_WIRE_1, 5, 5) connect _mpu_ppn_data_WIRE.pr, _mpu_ppn_data_T_5 node _mpu_ppn_data_T_6 = bits(_mpu_ppn_data_WIRE_1, 6, 6) connect _mpu_ppn_data_WIRE.px, _mpu_ppn_data_T_6 node _mpu_ppn_data_T_7 = bits(_mpu_ppn_data_WIRE_1, 7, 7) connect _mpu_ppn_data_WIRE.pw, _mpu_ppn_data_T_7 node _mpu_ppn_data_T_8 = bits(_mpu_ppn_data_WIRE_1, 8, 8) connect _mpu_ppn_data_WIRE.sr, _mpu_ppn_data_T_8 node _mpu_ppn_data_T_9 = bits(_mpu_ppn_data_WIRE_1, 9, 9) connect _mpu_ppn_data_WIRE.sx, _mpu_ppn_data_T_9 node _mpu_ppn_data_T_10 = bits(_mpu_ppn_data_WIRE_1, 10, 10) connect _mpu_ppn_data_WIRE.sw, _mpu_ppn_data_T_10 node _mpu_ppn_data_T_11 = bits(_mpu_ppn_data_WIRE_1, 11, 11) connect _mpu_ppn_data_WIRE.ae, _mpu_ppn_data_T_11 node _mpu_ppn_data_T_12 = bits(_mpu_ppn_data_WIRE_1, 12, 12) connect _mpu_ppn_data_WIRE.g, _mpu_ppn_data_T_12 node _mpu_ppn_data_T_13 = bits(_mpu_ppn_data_WIRE_1, 13, 13) connect _mpu_ppn_data_WIRE.u, _mpu_ppn_data_T_13 node _mpu_ppn_data_T_14 = bits(_mpu_ppn_data_WIRE_1, 33, 14) connect _mpu_ppn_data_WIRE.ppn, _mpu_ppn_data_T_14 inst mpu_ppn_data_barrier of OptimizationBarrier_EntryData connect mpu_ppn_data_barrier.clock, clock connect mpu_ppn_data_barrier.reset, reset connect mpu_ppn_data_barrier.io.x.fragmented_superpage, _mpu_ppn_data_WIRE.fragmented_superpage connect mpu_ppn_data_barrier.io.x.c, _mpu_ppn_data_WIRE.c connect mpu_ppn_data_barrier.io.x.eff, _mpu_ppn_data_WIRE.eff connect mpu_ppn_data_barrier.io.x.paa, _mpu_ppn_data_WIRE.paa connect mpu_ppn_data_barrier.io.x.pal, _mpu_ppn_data_WIRE.pal connect mpu_ppn_data_barrier.io.x.pr, _mpu_ppn_data_WIRE.pr connect mpu_ppn_data_barrier.io.x.px, _mpu_ppn_data_WIRE.px connect mpu_ppn_data_barrier.io.x.pw, _mpu_ppn_data_WIRE.pw connect mpu_ppn_data_barrier.io.x.sr, _mpu_ppn_data_WIRE.sr connect mpu_ppn_data_barrier.io.x.sx, _mpu_ppn_data_WIRE.sx connect mpu_ppn_data_barrier.io.x.sw, _mpu_ppn_data_WIRE.sw connect mpu_ppn_data_barrier.io.x.ae, _mpu_ppn_data_WIRE.ae connect mpu_ppn_data_barrier.io.x.g, _mpu_ppn_data_WIRE.g connect mpu_ppn_data_barrier.io.x.u, _mpu_ppn_data_WIRE.u connect mpu_ppn_data_barrier.io.x.ppn, _mpu_ppn_data_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_data_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_1 = mux(mpu_ppn_ignore, vpn[0], UInt<1>(0h0)) node _mpu_ppn_T_2 = or(_mpu_ppn_T_1, mpu_ppn_data_barrier.io.y.ppn) node _mpu_ppn_T_3 = bits(_mpu_ppn_T_2, 17, 9) node _mpu_ppn_T_4 = cat(mpu_ppn_res, _mpu_ppn_T_3) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_5 = mux(mpu_ppn_ignore_1, vpn[0], UInt<1>(0h0)) node _mpu_ppn_T_6 = or(_mpu_ppn_T_5, mpu_ppn_data_barrier.io.y.ppn) node _mpu_ppn_T_7 = bits(_mpu_ppn_T_6, 8, 0) node _mpu_ppn_T_8 = cat(_mpu_ppn_T_4, _mpu_ppn_T_7) node _mpu_ppn_T_9 = shr(io.req[0].bits.vaddr, 12) node _mpu_ppn_T_10 = mux(_mpu_ppn_T, _mpu_ppn_T_8, _mpu_ppn_T_9) node _mpu_ppn_T_11 = mux(do_refill, refill_ppn, _mpu_ppn_T_10) wire mpu_ppn : UInt<28>[1] connect mpu_ppn[0], _mpu_ppn_T_11 node _mpu_physaddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _mpu_physaddr_T_1 = cat(mpu_ppn[0], _mpu_physaddr_T) wire mpu_physaddr : UInt<40>[1] connect mpu_physaddr[0], _mpu_physaddr_T_1 inst pmp_0 of PMPChecker_s3_1 connect pmp_0.clock, clock connect pmp_0.reset, reset connect pmp_0.io.addr, mpu_physaddr[0] connect pmp_0.io.size, io.req[0].bits.size connect pmp_0.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp_0.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp_0.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp_0.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp_0.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp_0.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp_0.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp_0.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp_0.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp_0.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp_0.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp_0.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp_0.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp_0.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp_0.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp_0.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp_0.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp_0.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp_0.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp_0.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp_0.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp_0.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp_0.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp_0.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp_0.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp_0.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp_0.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp_0.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp_0.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp_0.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp_0.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp_0.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp_0.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp_0.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp_0.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp_0.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp_0.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp_0.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp_0.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp_0.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp_0.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp_0.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp_0.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp_0.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp_0.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp_0.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp_0.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp_0.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp_0.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp_0.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp_0.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp_0.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp_0.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp_0.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp_0.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp_0.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp_0.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp_0.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp_0.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp_0.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp_0.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp_0.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp_0.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp_0.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l node _pmp_0_io_prv_T = or(do_refill, io.req[0].bits.passthrough) node _pmp_0_io_prv_T_1 = and(UInt<1>(0h1), _pmp_0_io_prv_T) node _pmp_0_io_prv_T_2 = mux(_pmp_0_io_prv_T_1, UInt<1>(0h1), io.ptw.status.dprv) connect pmp_0.io.prv, _pmp_0_io_prv_T_2 node _legal_address_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(mpu_physaddr[0], UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(mpu_physaddr[0], UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(mpu_physaddr[0], UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node _legal_address_T_70 = or(_legal_address_T_69, _legal_address_WIRE[11]) wire legal_address : UInt<1>[1] connect legal_address[0], _legal_address_T_70 node _cacheable_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _cacheable_T_1 = cvt(_cacheable_T) node _cacheable_T_2 = and(_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_3 = asSInt(_cacheable_T_2) node _cacheable_T_4 = eq(_cacheable_T_3, asSInt(UInt<1>(0h0))) node _cacheable_T_5 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _cacheable_T_6 = cvt(_cacheable_T_5) node _cacheable_T_7 = and(_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _cacheable_T_8 = asSInt(_cacheable_T_7) node _cacheable_T_9 = eq(_cacheable_T_8, asSInt(UInt<1>(0h0))) node _cacheable_T_10 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _cacheable_T_11 = cvt(_cacheable_T_10) node _cacheable_T_12 = and(_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_13 = asSInt(_cacheable_T_12) node _cacheable_T_14 = eq(_cacheable_T_13, asSInt(UInt<1>(0h0))) node _cacheable_T_15 = or(_cacheable_T_4, _cacheable_T_9) node _cacheable_T_16 = or(_cacheable_T_15, _cacheable_T_14) node _cacheable_T_17 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _cacheable_T_18 = cvt(_cacheable_T_17) node _cacheable_T_19 = and(_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _cacheable_T_20 = asSInt(_cacheable_T_19) node _cacheable_T_21 = eq(_cacheable_T_20, asSInt(UInt<1>(0h0))) node _cacheable_T_22 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _cacheable_T_23 = cvt(_cacheable_T_22) node _cacheable_T_24 = and(_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _cacheable_T_25 = asSInt(_cacheable_T_24) node _cacheable_T_26 = eq(_cacheable_T_25, asSInt(UInt<1>(0h0))) node _cacheable_T_27 = or(_cacheable_T_21, _cacheable_T_26) node _cacheable_T_28 = mux(_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _cacheable_T_29 = mux(_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _cacheable_T_30 = or(_cacheable_T_28, _cacheable_T_29) wire _cacheable_WIRE : UInt<1> connect _cacheable_WIRE, _cacheable_T_30 node _cacheable_T_31 = and(legal_address[0], _cacheable_WIRE) node _cacheable_T_32 = and(_cacheable_T_31, UInt<1>(0h1)) wire cacheable : UInt<1>[1] connect cacheable[0], _cacheable_T_32 node _homogeneous_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr[0], UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node _homogeneous_T_59 = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_60 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_61 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_62 = cvt(_homogeneous_T_61) node _homogeneous_T_63 = and(_homogeneous_T_62, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_64 = asSInt(_homogeneous_T_63) node _homogeneous_T_65 = eq(_homogeneous_T_64, asSInt(UInt<1>(0h0))) node _homogeneous_T_66 = or(UInt<1>(0h0), _homogeneous_T_65) node _homogeneous_T_67 = eq(_homogeneous_T_66, UInt<1>(0h0)) node _homogeneous_T_68 = xor(mpu_physaddr[0], UInt<1>(0h0)) node _homogeneous_T_69 = cvt(_homogeneous_T_68) node _homogeneous_T_70 = and(_homogeneous_T_69, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_71 = asSInt(_homogeneous_T_70) node _homogeneous_T_72 = eq(_homogeneous_T_71, asSInt(UInt<1>(0h0))) node _homogeneous_T_73 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _homogeneous_T_74 = cvt(_homogeneous_T_73) node _homogeneous_T_75 = and(_homogeneous_T_74, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_76 = asSInt(_homogeneous_T_75) node _homogeneous_T_77 = eq(_homogeneous_T_76, asSInt(UInt<1>(0h0))) node _homogeneous_T_78 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_79 = cvt(_homogeneous_T_78) node _homogeneous_T_80 = and(_homogeneous_T_79, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_81 = asSInt(_homogeneous_T_80) node _homogeneous_T_82 = eq(_homogeneous_T_81, asSInt(UInt<1>(0h0))) node _homogeneous_T_83 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _homogeneous_T_84 = cvt(_homogeneous_T_83) node _homogeneous_T_85 = and(_homogeneous_T_84, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_86 = asSInt(_homogeneous_T_85) node _homogeneous_T_87 = eq(_homogeneous_T_86, asSInt(UInt<1>(0h0))) node _homogeneous_T_88 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_89 = cvt(_homogeneous_T_88) node _homogeneous_T_90 = and(_homogeneous_T_89, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_91 = asSInt(_homogeneous_T_90) node _homogeneous_T_92 = eq(_homogeneous_T_91, asSInt(UInt<1>(0h0))) node _homogeneous_T_93 = or(UInt<1>(0h0), _homogeneous_T_72) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_77) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_82) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_87) node _homogeneous_T_97 = or(_homogeneous_T_96, _homogeneous_T_92) node _homogeneous_T_98 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _homogeneous_T_99 = cvt(_homogeneous_T_98) node _homogeneous_T_100 = and(_homogeneous_T_99, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_101 = asSInt(_homogeneous_T_100) node _homogeneous_T_102 = eq(_homogeneous_T_101, asSInt(UInt<1>(0h0))) node _homogeneous_T_103 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_104 = cvt(_homogeneous_T_103) node _homogeneous_T_105 = and(_homogeneous_T_104, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_106 = asSInt(_homogeneous_T_105) node _homogeneous_T_107 = eq(_homogeneous_T_106, asSInt(UInt<1>(0h0))) node _homogeneous_T_108 = or(UInt<1>(0h0), _homogeneous_T_102) node _homogeneous_T_109 = or(_homogeneous_T_108, _homogeneous_T_107) node _homogeneous_T_110 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_111 = cvt(_homogeneous_T_110) node _homogeneous_T_112 = and(_homogeneous_T_111, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_113 = asSInt(_homogeneous_T_112) node _homogeneous_T_114 = eq(_homogeneous_T_113, asSInt(UInt<1>(0h0))) node _homogeneous_T_115 = or(UInt<1>(0h0), _homogeneous_T_114) node _homogeneous_T_116 = eq(_homogeneous_T_115, UInt<1>(0h0)) node _homogeneous_T_117 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_118 = cvt(_homogeneous_T_117) node _homogeneous_T_119 = and(_homogeneous_T_118, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_120 = asSInt(_homogeneous_T_119) node _homogeneous_T_121 = eq(_homogeneous_T_120, asSInt(UInt<1>(0h0))) node _homogeneous_T_122 = or(UInt<1>(0h0), _homogeneous_T_121) node _homogeneous_T_123 = eq(_homogeneous_T_122, UInt<1>(0h0)) wire homogeneous : UInt<1>[1] connect homogeneous[0], _homogeneous_T_59 node _prot_r_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_r_T_1 = cvt(_prot_r_T) node _prot_r_T_2 = and(_prot_r_T_1, asSInt(UInt<1>(0h0))) node _prot_r_T_3 = asSInt(_prot_r_T_2) node _prot_r_T_4 = eq(_prot_r_T_3, asSInt(UInt<1>(0h0))) node _prot_r_T_5 = and(legal_address[0], UInt<1>(0h1)) node _prot_r_T_6 = and(_prot_r_T_5, pmp_0.io.r) wire prot_r : UInt<1>[1] connect prot_r[0], _prot_r_T_6 node _prot_w_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_w_T_1 = cvt(_prot_w_T) node _prot_w_T_2 = and(_prot_w_T_1, asSInt(UInt<33>(0h98110000))) node _prot_w_T_3 = asSInt(_prot_w_T_2) node _prot_w_T_4 = eq(_prot_w_T_3, asSInt(UInt<1>(0h0))) node _prot_w_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_w_T_6 = cvt(_prot_w_T_5) node _prot_w_T_7 = and(_prot_w_T_6, asSInt(UInt<33>(0h9a101000))) node _prot_w_T_8 = asSInt(_prot_w_T_7) node _prot_w_T_9 = eq(_prot_w_T_8, asSInt(UInt<1>(0h0))) node _prot_w_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_w_T_11 = cvt(_prot_w_T_10) node _prot_w_T_12 = and(_prot_w_T_11, asSInt(UInt<33>(0h9a111000))) node _prot_w_T_13 = asSInt(_prot_w_T_12) node _prot_w_T_14 = eq(_prot_w_T_13, asSInt(UInt<1>(0h0))) node _prot_w_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_w_T_16 = cvt(_prot_w_T_15) node _prot_w_T_17 = and(_prot_w_T_16, asSInt(UInt<33>(0h98000000))) node _prot_w_T_18 = asSInt(_prot_w_T_17) node _prot_w_T_19 = eq(_prot_w_T_18, asSInt(UInt<1>(0h0))) node _prot_w_T_20 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_w_T_21 = cvt(_prot_w_T_20) node _prot_w_T_22 = and(_prot_w_T_21, asSInt(UInt<33>(0h9a110000))) node _prot_w_T_23 = asSInt(_prot_w_T_22) node _prot_w_T_24 = eq(_prot_w_T_23, asSInt(UInt<1>(0h0))) node _prot_w_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_w_T_26 = cvt(_prot_w_T_25) node _prot_w_T_27 = and(_prot_w_T_26, asSInt(UInt<33>(0h9a111000))) node _prot_w_T_28 = asSInt(_prot_w_T_27) node _prot_w_T_29 = eq(_prot_w_T_28, asSInt(UInt<1>(0h0))) node _prot_w_T_30 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_w_T_31 = cvt(_prot_w_T_30) node _prot_w_T_32 = and(_prot_w_T_31, asSInt(UInt<33>(0h90000000))) node _prot_w_T_33 = asSInt(_prot_w_T_32) node _prot_w_T_34 = eq(_prot_w_T_33, asSInt(UInt<1>(0h0))) node _prot_w_T_35 = or(_prot_w_T_4, _prot_w_T_9) node _prot_w_T_36 = or(_prot_w_T_35, _prot_w_T_14) node _prot_w_T_37 = or(_prot_w_T_36, _prot_w_T_19) node _prot_w_T_38 = or(_prot_w_T_37, _prot_w_T_24) node _prot_w_T_39 = or(_prot_w_T_38, _prot_w_T_29) node _prot_w_T_40 = or(_prot_w_T_39, _prot_w_T_34) node _prot_w_T_41 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_w_T_42 = cvt(_prot_w_T_41) node _prot_w_T_43 = and(_prot_w_T_42, asSInt(UInt<33>(0h9a110000))) node _prot_w_T_44 = asSInt(_prot_w_T_43) node _prot_w_T_45 = eq(_prot_w_T_44, asSInt(UInt<1>(0h0))) node _prot_w_T_46 = mux(_prot_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _prot_w_T_47 = mux(_prot_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _prot_w_T_48 = or(_prot_w_T_46, _prot_w_T_47) wire _prot_w_WIRE : UInt<1> connect _prot_w_WIRE, _prot_w_T_48 node _prot_w_T_49 = and(legal_address[0], _prot_w_WIRE) node _prot_w_T_50 = and(_prot_w_T_49, pmp_0.io.w) wire prot_w : UInt<1>[1] connect prot_w[0], _prot_w_T_50 node _prot_al_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_al_T_1 = cvt(_prot_al_T) node _prot_al_T_2 = and(_prot_al_T_1, asSInt(UInt<33>(0h98110000))) node _prot_al_T_3 = asSInt(_prot_al_T_2) node _prot_al_T_4 = eq(_prot_al_T_3, asSInt(UInt<1>(0h0))) node _prot_al_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_al_T_6 = cvt(_prot_al_T_5) node _prot_al_T_7 = and(_prot_al_T_6, asSInt(UInt<33>(0h9a101000))) node _prot_al_T_8 = asSInt(_prot_al_T_7) node _prot_al_T_9 = eq(_prot_al_T_8, asSInt(UInt<1>(0h0))) node _prot_al_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_al_T_11 = cvt(_prot_al_T_10) node _prot_al_T_12 = and(_prot_al_T_11, asSInt(UInt<33>(0h9a111000))) node _prot_al_T_13 = asSInt(_prot_al_T_12) node _prot_al_T_14 = eq(_prot_al_T_13, asSInt(UInt<1>(0h0))) node _prot_al_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_al_T_16 = cvt(_prot_al_T_15) node _prot_al_T_17 = and(_prot_al_T_16, asSInt(UInt<33>(0h98000000))) node _prot_al_T_18 = asSInt(_prot_al_T_17) node _prot_al_T_19 = eq(_prot_al_T_18, asSInt(UInt<1>(0h0))) node _prot_al_T_20 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_al_T_21 = cvt(_prot_al_T_20) node _prot_al_T_22 = and(_prot_al_T_21, asSInt(UInt<33>(0h9a110000))) node _prot_al_T_23 = asSInt(_prot_al_T_22) node _prot_al_T_24 = eq(_prot_al_T_23, asSInt(UInt<1>(0h0))) node _prot_al_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_al_T_26 = cvt(_prot_al_T_25) node _prot_al_T_27 = and(_prot_al_T_26, asSInt(UInt<33>(0h9a111000))) node _prot_al_T_28 = asSInt(_prot_al_T_27) node _prot_al_T_29 = eq(_prot_al_T_28, asSInt(UInt<1>(0h0))) node _prot_al_T_30 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_al_T_31 = cvt(_prot_al_T_30) node _prot_al_T_32 = and(_prot_al_T_31, asSInt(UInt<33>(0h90000000))) node _prot_al_T_33 = asSInt(_prot_al_T_32) node _prot_al_T_34 = eq(_prot_al_T_33, asSInt(UInt<1>(0h0))) node _prot_al_T_35 = or(_prot_al_T_4, _prot_al_T_9) node _prot_al_T_36 = or(_prot_al_T_35, _prot_al_T_14) node _prot_al_T_37 = or(_prot_al_T_36, _prot_al_T_19) node _prot_al_T_38 = or(_prot_al_T_37, _prot_al_T_24) node _prot_al_T_39 = or(_prot_al_T_38, _prot_al_T_29) node _prot_al_T_40 = or(_prot_al_T_39, _prot_al_T_34) node _prot_al_T_41 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_al_T_42 = cvt(_prot_al_T_41) node _prot_al_T_43 = and(_prot_al_T_42, asSInt(UInt<33>(0h9a110000))) node _prot_al_T_44 = asSInt(_prot_al_T_43) node _prot_al_T_45 = eq(_prot_al_T_44, asSInt(UInt<1>(0h0))) node _prot_al_T_46 = mux(_prot_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _prot_al_T_47 = mux(_prot_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _prot_al_T_48 = or(_prot_al_T_46, _prot_al_T_47) wire _prot_al_WIRE : UInt<1> connect _prot_al_WIRE, _prot_al_T_48 node _prot_al_T_49 = and(legal_address[0], _prot_al_WIRE) wire prot_al : UInt<1>[1] connect prot_al[0], _prot_al_T_49 node _prot_aa_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_aa_T_1 = cvt(_prot_aa_T) node _prot_aa_T_2 = and(_prot_aa_T_1, asSInt(UInt<33>(0h98110000))) node _prot_aa_T_3 = asSInt(_prot_aa_T_2) node _prot_aa_T_4 = eq(_prot_aa_T_3, asSInt(UInt<1>(0h0))) node _prot_aa_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_aa_T_6 = cvt(_prot_aa_T_5) node _prot_aa_T_7 = and(_prot_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _prot_aa_T_8 = asSInt(_prot_aa_T_7) node _prot_aa_T_9 = eq(_prot_aa_T_8, asSInt(UInt<1>(0h0))) node _prot_aa_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_aa_T_11 = cvt(_prot_aa_T_10) node _prot_aa_T_12 = and(_prot_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _prot_aa_T_13 = asSInt(_prot_aa_T_12) node _prot_aa_T_14 = eq(_prot_aa_T_13, asSInt(UInt<1>(0h0))) node _prot_aa_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_aa_T_16 = cvt(_prot_aa_T_15) node _prot_aa_T_17 = and(_prot_aa_T_16, asSInt(UInt<33>(0h98000000))) node _prot_aa_T_18 = asSInt(_prot_aa_T_17) node _prot_aa_T_19 = eq(_prot_aa_T_18, asSInt(UInt<1>(0h0))) node _prot_aa_T_20 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_aa_T_21 = cvt(_prot_aa_T_20) node _prot_aa_T_22 = and(_prot_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _prot_aa_T_23 = asSInt(_prot_aa_T_22) node _prot_aa_T_24 = eq(_prot_aa_T_23, asSInt(UInt<1>(0h0))) node _prot_aa_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_aa_T_26 = cvt(_prot_aa_T_25) node _prot_aa_T_27 = and(_prot_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _prot_aa_T_28 = asSInt(_prot_aa_T_27) node _prot_aa_T_29 = eq(_prot_aa_T_28, asSInt(UInt<1>(0h0))) node _prot_aa_T_30 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_aa_T_31 = cvt(_prot_aa_T_30) node _prot_aa_T_32 = and(_prot_aa_T_31, asSInt(UInt<33>(0h90000000))) node _prot_aa_T_33 = asSInt(_prot_aa_T_32) node _prot_aa_T_34 = eq(_prot_aa_T_33, asSInt(UInt<1>(0h0))) node _prot_aa_T_35 = or(_prot_aa_T_4, _prot_aa_T_9) node _prot_aa_T_36 = or(_prot_aa_T_35, _prot_aa_T_14) node _prot_aa_T_37 = or(_prot_aa_T_36, _prot_aa_T_19) node _prot_aa_T_38 = or(_prot_aa_T_37, _prot_aa_T_24) node _prot_aa_T_39 = or(_prot_aa_T_38, _prot_aa_T_29) node _prot_aa_T_40 = or(_prot_aa_T_39, _prot_aa_T_34) node _prot_aa_T_41 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_aa_T_42 = cvt(_prot_aa_T_41) node _prot_aa_T_43 = and(_prot_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _prot_aa_T_44 = asSInt(_prot_aa_T_43) node _prot_aa_T_45 = eq(_prot_aa_T_44, asSInt(UInt<1>(0h0))) node _prot_aa_T_46 = mux(_prot_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _prot_aa_T_47 = mux(_prot_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _prot_aa_T_48 = or(_prot_aa_T_46, _prot_aa_T_47) wire _prot_aa_WIRE : UInt<1> connect _prot_aa_WIRE, _prot_aa_T_48 node _prot_aa_T_49 = and(legal_address[0], _prot_aa_WIRE) wire prot_aa : UInt<1>[1] connect prot_aa[0], _prot_aa_T_49 node _prot_x_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_x_T_1 = cvt(_prot_x_T) node _prot_x_T_2 = and(_prot_x_T_1, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_3 = asSInt(_prot_x_T_2) node _prot_x_T_4 = eq(_prot_x_T_3, asSInt(UInt<1>(0h0))) node _prot_x_T_5 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _prot_x_T_6 = cvt(_prot_x_T_5) node _prot_x_T_7 = and(_prot_x_T_6, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_8 = asSInt(_prot_x_T_7) node _prot_x_T_9 = eq(_prot_x_T_8, asSInt(UInt<1>(0h0))) node _prot_x_T_10 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_x_T_11 = cvt(_prot_x_T_10) node _prot_x_T_12 = and(_prot_x_T_11, asSInt(UInt<33>(0h9e110000))) node _prot_x_T_13 = asSInt(_prot_x_T_12) node _prot_x_T_14 = eq(_prot_x_T_13, asSInt(UInt<1>(0h0))) node _prot_x_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_x_T_16 = cvt(_prot_x_T_15) node _prot_x_T_17 = and(_prot_x_T_16, asSInt(UInt<33>(0h9e110000))) node _prot_x_T_18 = asSInt(_prot_x_T_17) node _prot_x_T_19 = eq(_prot_x_T_18, asSInt(UInt<1>(0h0))) node _prot_x_T_20 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_x_T_21 = cvt(_prot_x_T_20) node _prot_x_T_22 = and(_prot_x_T_21, asSInt(UInt<33>(0h90000000))) node _prot_x_T_23 = asSInt(_prot_x_T_22) node _prot_x_T_24 = eq(_prot_x_T_23, asSInt(UInt<1>(0h0))) node _prot_x_T_25 = or(_prot_x_T_4, _prot_x_T_9) node _prot_x_T_26 = or(_prot_x_T_25, _prot_x_T_14) node _prot_x_T_27 = or(_prot_x_T_26, _prot_x_T_19) node _prot_x_T_28 = or(_prot_x_T_27, _prot_x_T_24) node _prot_x_T_29 = xor(mpu_physaddr[0], UInt<13>(0h1000)) node _prot_x_T_30 = cvt(_prot_x_T_29) node _prot_x_T_31 = and(_prot_x_T_30, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_32 = asSInt(_prot_x_T_31) node _prot_x_T_33 = eq(_prot_x_T_32, asSInt(UInt<1>(0h0))) node _prot_x_T_34 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_x_T_35 = cvt(_prot_x_T_34) node _prot_x_T_36 = and(_prot_x_T_35, asSInt(UInt<33>(0h9e103000))) node _prot_x_T_37 = asSInt(_prot_x_T_36) node _prot_x_T_38 = eq(_prot_x_T_37, asSInt(UInt<1>(0h0))) node _prot_x_T_39 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _prot_x_T_40 = cvt(_prot_x_T_39) node _prot_x_T_41 = and(_prot_x_T_40, asSInt(UInt<33>(0h9e110000))) node _prot_x_T_42 = asSInt(_prot_x_T_41) node _prot_x_T_43 = eq(_prot_x_T_42, asSInt(UInt<1>(0h0))) node _prot_x_T_44 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_x_T_45 = cvt(_prot_x_T_44) node _prot_x_T_46 = and(_prot_x_T_45, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_47 = asSInt(_prot_x_T_46) node _prot_x_T_48 = eq(_prot_x_T_47, asSInt(UInt<1>(0h0))) node _prot_x_T_49 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _prot_x_T_50 = cvt(_prot_x_T_49) node _prot_x_T_51 = and(_prot_x_T_50, asSInt(UInt<33>(0h9c000000))) node _prot_x_T_52 = asSInt(_prot_x_T_51) node _prot_x_T_53 = eq(_prot_x_T_52, asSInt(UInt<1>(0h0))) node _prot_x_T_54 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_x_T_55 = cvt(_prot_x_T_54) node _prot_x_T_56 = and(_prot_x_T_55, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_57 = asSInt(_prot_x_T_56) node _prot_x_T_58 = eq(_prot_x_T_57, asSInt(UInt<1>(0h0))) node _prot_x_T_59 = or(_prot_x_T_33, _prot_x_T_38) node _prot_x_T_60 = or(_prot_x_T_59, _prot_x_T_43) node _prot_x_T_61 = or(_prot_x_T_60, _prot_x_T_48) node _prot_x_T_62 = or(_prot_x_T_61, _prot_x_T_53) node _prot_x_T_63 = or(_prot_x_T_62, _prot_x_T_58) node _prot_x_T_64 = mux(_prot_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _prot_x_T_65 = mux(_prot_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _prot_x_T_66 = or(_prot_x_T_64, _prot_x_T_65) wire _prot_x_WIRE : UInt<1> connect _prot_x_WIRE, _prot_x_T_66 node _prot_x_T_67 = and(legal_address[0], _prot_x_WIRE) node _prot_x_T_68 = and(_prot_x_T_67, pmp_0.io.x) wire prot_x : UInt<1>[1] connect prot_x[0], _prot_x_T_68 node _prot_eff_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_eff_T_1 = cvt(_prot_eff_T) node _prot_eff_T_2 = and(_prot_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _prot_eff_T_3 = asSInt(_prot_eff_T_2) node _prot_eff_T_4 = eq(_prot_eff_T_3, asSInt(UInt<1>(0h0))) node _prot_eff_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_eff_T_6 = cvt(_prot_eff_T_5) node _prot_eff_T_7 = and(_prot_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _prot_eff_T_8 = asSInt(_prot_eff_T_7) node _prot_eff_T_9 = eq(_prot_eff_T_8, asSInt(UInt<1>(0h0))) node _prot_eff_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _prot_eff_T_11 = cvt(_prot_eff_T_10) node _prot_eff_T_12 = and(_prot_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _prot_eff_T_13 = asSInt(_prot_eff_T_12) node _prot_eff_T_14 = eq(_prot_eff_T_13, asSInt(UInt<1>(0h0))) node _prot_eff_T_15 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_eff_T_16 = cvt(_prot_eff_T_15) node _prot_eff_T_17 = and(_prot_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _prot_eff_T_18 = asSInt(_prot_eff_T_17) node _prot_eff_T_19 = eq(_prot_eff_T_18, asSInt(UInt<1>(0h0))) node _prot_eff_T_20 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _prot_eff_T_21 = cvt(_prot_eff_T_20) node _prot_eff_T_22 = and(_prot_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _prot_eff_T_23 = asSInt(_prot_eff_T_22) node _prot_eff_T_24 = eq(_prot_eff_T_23, asSInt(UInt<1>(0h0))) node _prot_eff_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_eff_T_26 = cvt(_prot_eff_T_25) node _prot_eff_T_27 = and(_prot_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _prot_eff_T_28 = asSInt(_prot_eff_T_27) node _prot_eff_T_29 = eq(_prot_eff_T_28, asSInt(UInt<1>(0h0))) node _prot_eff_T_30 = or(_prot_eff_T_4, _prot_eff_T_9) node _prot_eff_T_31 = or(_prot_eff_T_30, _prot_eff_T_14) node _prot_eff_T_32 = or(_prot_eff_T_31, _prot_eff_T_19) node _prot_eff_T_33 = or(_prot_eff_T_32, _prot_eff_T_24) node _prot_eff_T_34 = or(_prot_eff_T_33, _prot_eff_T_29) node _prot_eff_T_35 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _prot_eff_T_36 = cvt(_prot_eff_T_35) node _prot_eff_T_37 = and(_prot_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _prot_eff_T_38 = asSInt(_prot_eff_T_37) node _prot_eff_T_39 = eq(_prot_eff_T_38, asSInt(UInt<1>(0h0))) node _prot_eff_T_40 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_eff_T_41 = cvt(_prot_eff_T_40) node _prot_eff_T_42 = and(_prot_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _prot_eff_T_43 = asSInt(_prot_eff_T_42) node _prot_eff_T_44 = eq(_prot_eff_T_43, asSInt(UInt<1>(0h0))) node _prot_eff_T_45 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_eff_T_46 = cvt(_prot_eff_T_45) node _prot_eff_T_47 = and(_prot_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _prot_eff_T_48 = asSInt(_prot_eff_T_47) node _prot_eff_T_49 = eq(_prot_eff_T_48, asSInt(UInt<1>(0h0))) node _prot_eff_T_50 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_eff_T_51 = cvt(_prot_eff_T_50) node _prot_eff_T_52 = and(_prot_eff_T_51, asSInt(UInt<33>(0h90000000))) node _prot_eff_T_53 = asSInt(_prot_eff_T_52) node _prot_eff_T_54 = eq(_prot_eff_T_53, asSInt(UInt<1>(0h0))) node _prot_eff_T_55 = or(_prot_eff_T_39, _prot_eff_T_44) node _prot_eff_T_56 = or(_prot_eff_T_55, _prot_eff_T_49) node _prot_eff_T_57 = or(_prot_eff_T_56, _prot_eff_T_54) node _prot_eff_T_58 = mux(_prot_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _prot_eff_T_59 = mux(_prot_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _prot_eff_T_60 = or(_prot_eff_T_58, _prot_eff_T_59) wire _prot_eff_WIRE : UInt<1> connect _prot_eff_WIRE, _prot_eff_T_60 node _prot_eff_T_61 = and(legal_address[0], _prot_eff_WIRE) wire prot_eff : UInt<1>[1] connect prot_eff[0], _prot_eff_T_61 node _sector_hits_T = or(sectored_entries[0].valid[0], sectored_entries[0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0].tag, vpn[0]) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = and(_sector_hits_T_2, _sector_hits_T_5) node _sector_hits_T_7 = or(sectored_entries[1].valid[0], sectored_entries[1].valid[1]) node _sector_hits_T_8 = or(_sector_hits_T_7, sectored_entries[1].valid[2]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[1].valid[3]) node _sector_hits_T_10 = xor(sectored_entries[1].tag, vpn[0]) node _sector_hits_T_11 = shr(_sector_hits_T_10, 2) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = and(_sector_hits_T_9, _sector_hits_T_12) wire _sector_hits_WIRE : UInt<1>[2] connect _sector_hits_WIRE[0], _sector_hits_T_6 connect _sector_hits_WIRE[1], _sector_hits_T_13 wire sector_hits : UInt<1>[2][1] connect sector_hits[0], _sector_hits_WIRE node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = bits(superpage_entries[0].tag, 26, 18) node _superpage_hits_T_1 = bits(vpn[0], 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T, _superpage_hits_T_1) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_entries[0].valid[0], _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = bits(superpage_entries[0].tag, 17, 9) node _superpage_hits_T_6 = bits(vpn[0], 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_5, _superpage_hits_T_6) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = bits(superpage_entries[0].tag, 8, 0) node _superpage_hits_T_11 = bits(vpn[0], 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_10, _superpage_hits_T_11) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node _superpage_hits_T_14 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_15 = bits(superpage_entries[1].tag, 26, 18) node _superpage_hits_T_16 = bits(vpn[0], 26, 18) node _superpage_hits_T_17 = eq(_superpage_hits_T_15, _superpage_hits_T_16) node _superpage_hits_T_18 = or(superpage_hits_ignore_3, _superpage_hits_T_17) node _superpage_hits_T_19 = and(superpage_entries[1].valid[0], _superpage_hits_T_18) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_20 = bits(superpage_entries[1].tag, 17, 9) node _superpage_hits_T_21 = bits(vpn[0], 17, 9) node _superpage_hits_T_22 = eq(_superpage_hits_T_20, _superpage_hits_T_21) node _superpage_hits_T_23 = or(superpage_hits_ignore_4, _superpage_hits_T_22) node _superpage_hits_T_24 = and(_superpage_hits_T_19, _superpage_hits_T_23) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_25 = bits(superpage_entries[1].tag, 8, 0) node _superpage_hits_T_26 = bits(vpn[0], 8, 0) node _superpage_hits_T_27 = eq(_superpage_hits_T_25, _superpage_hits_T_26) node _superpage_hits_T_28 = or(superpage_hits_ignore_5, _superpage_hits_T_27) node _superpage_hits_T_29 = and(_superpage_hits_T_24, _superpage_hits_T_28) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_30 = bits(superpage_entries[2].tag, 26, 18) node _superpage_hits_T_31 = bits(vpn[0], 26, 18) node _superpage_hits_T_32 = eq(_superpage_hits_T_30, _superpage_hits_T_31) node _superpage_hits_T_33 = or(superpage_hits_ignore_6, _superpage_hits_T_32) node _superpage_hits_T_34 = and(superpage_entries[2].valid[0], _superpage_hits_T_33) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_35 = bits(superpage_entries[2].tag, 17, 9) node _superpage_hits_T_36 = bits(vpn[0], 17, 9) node _superpage_hits_T_37 = eq(_superpage_hits_T_35, _superpage_hits_T_36) node _superpage_hits_T_38 = or(superpage_hits_ignore_7, _superpage_hits_T_37) node _superpage_hits_T_39 = and(_superpage_hits_T_34, _superpage_hits_T_38) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_40 = bits(superpage_entries[2].tag, 8, 0) node _superpage_hits_T_41 = bits(vpn[0], 8, 0) node _superpage_hits_T_42 = eq(_superpage_hits_T_40, _superpage_hits_T_41) node _superpage_hits_T_43 = or(superpage_hits_ignore_8, _superpage_hits_T_42) node _superpage_hits_T_44 = and(_superpage_hits_T_39, _superpage_hits_T_43) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_45 = bits(superpage_entries[3].tag, 26, 18) node _superpage_hits_T_46 = bits(vpn[0], 26, 18) node _superpage_hits_T_47 = eq(_superpage_hits_T_45, _superpage_hits_T_46) node _superpage_hits_T_48 = or(superpage_hits_ignore_9, _superpage_hits_T_47) node _superpage_hits_T_49 = and(superpage_entries[3].valid[0], _superpage_hits_T_48) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_50 = bits(superpage_entries[3].tag, 17, 9) node _superpage_hits_T_51 = bits(vpn[0], 17, 9) node _superpage_hits_T_52 = eq(_superpage_hits_T_50, _superpage_hits_T_51) node _superpage_hits_T_53 = or(superpage_hits_ignore_10, _superpage_hits_T_52) node _superpage_hits_T_54 = and(_superpage_hits_T_49, _superpage_hits_T_53) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_55 = bits(superpage_entries[3].tag, 8, 0) node _superpage_hits_T_56 = bits(vpn[0], 8, 0) node _superpage_hits_T_57 = eq(_superpage_hits_T_55, _superpage_hits_T_56) node _superpage_hits_T_58 = or(superpage_hits_ignore_11, _superpage_hits_T_57) node _superpage_hits_T_59 = and(_superpage_hits_T_54, _superpage_hits_T_58) wire _superpage_hits_WIRE : UInt<1>[4] connect _superpage_hits_WIRE[0], _superpage_hits_T_14 connect _superpage_hits_WIRE[1], _superpage_hits_T_29 connect _superpage_hits_WIRE[2], _superpage_hits_T_44 connect _superpage_hits_WIRE[3], _superpage_hits_T_59 wire superpage_hits : UInt<1>[4][1] connect superpage_hits[0], _superpage_hits_WIRE node hitsVec_idx = bits(vpn[0], 1, 0) node _hitsVec_T = xor(sectored_entries[0].tag, vpn[0]) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = and(sectored_entries[0].valid[hitsVec_idx], _hitsVec_T_2) node _hitsVec_T_4 = and(vm_enabled[0], _hitsVec_T_3) node hitsVec_idx_1 = bits(vpn[0], 1, 0) node _hitsVec_T_5 = xor(sectored_entries[1].tag, vpn[0]) node _hitsVec_T_6 = shr(_hitsVec_T_5, 2) node _hitsVec_T_7 = eq(_hitsVec_T_6, UInt<1>(0h0)) node _hitsVec_T_8 = and(sectored_entries[1].valid[hitsVec_idx_1], _hitsVec_T_7) node _hitsVec_T_9 = and(vm_enabled[0], _hitsVec_T_8) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_10 = bits(superpage_entries[0].tag, 26, 18) node _hitsVec_T_11 = bits(vpn[0], 26, 18) node _hitsVec_T_12 = eq(_hitsVec_T_10, _hitsVec_T_11) node _hitsVec_T_13 = or(hitsVec_ignore, _hitsVec_T_12) node _hitsVec_T_14 = and(superpage_entries[0].valid[0], _hitsVec_T_13) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_15 = bits(superpage_entries[0].tag, 17, 9) node _hitsVec_T_16 = bits(vpn[0], 17, 9) node _hitsVec_T_17 = eq(_hitsVec_T_15, _hitsVec_T_16) node _hitsVec_T_18 = or(hitsVec_ignore_1, _hitsVec_T_17) node _hitsVec_T_19 = and(_hitsVec_T_14, _hitsVec_T_18) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_20 = bits(superpage_entries[0].tag, 8, 0) node _hitsVec_T_21 = bits(vpn[0], 8, 0) node _hitsVec_T_22 = eq(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = or(hitsVec_ignore_2, _hitsVec_T_22) node _hitsVec_T_24 = and(_hitsVec_T_19, _hitsVec_T_23) node _hitsVec_T_25 = and(vm_enabled[0], _hitsVec_T_24) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_26 = bits(superpage_entries[1].tag, 26, 18) node _hitsVec_T_27 = bits(vpn[0], 26, 18) node _hitsVec_T_28 = eq(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = or(hitsVec_ignore_3, _hitsVec_T_28) node _hitsVec_T_30 = and(superpage_entries[1].valid[0], _hitsVec_T_29) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_31 = bits(superpage_entries[1].tag, 17, 9) node _hitsVec_T_32 = bits(vpn[0], 17, 9) node _hitsVec_T_33 = eq(_hitsVec_T_31, _hitsVec_T_32) node _hitsVec_T_34 = or(hitsVec_ignore_4, _hitsVec_T_33) node _hitsVec_T_35 = and(_hitsVec_T_30, _hitsVec_T_34) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_36 = bits(superpage_entries[1].tag, 8, 0) node _hitsVec_T_37 = bits(vpn[0], 8, 0) node _hitsVec_T_38 = eq(_hitsVec_T_36, _hitsVec_T_37) node _hitsVec_T_39 = or(hitsVec_ignore_5, _hitsVec_T_38) node _hitsVec_T_40 = and(_hitsVec_T_35, _hitsVec_T_39) node _hitsVec_T_41 = and(vm_enabled[0], _hitsVec_T_40) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_42 = bits(superpage_entries[2].tag, 26, 18) node _hitsVec_T_43 = bits(vpn[0], 26, 18) node _hitsVec_T_44 = eq(_hitsVec_T_42, _hitsVec_T_43) node _hitsVec_T_45 = or(hitsVec_ignore_6, _hitsVec_T_44) node _hitsVec_T_46 = and(superpage_entries[2].valid[0], _hitsVec_T_45) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_47 = bits(superpage_entries[2].tag, 17, 9) node _hitsVec_T_48 = bits(vpn[0], 17, 9) node _hitsVec_T_49 = eq(_hitsVec_T_47, _hitsVec_T_48) node _hitsVec_T_50 = or(hitsVec_ignore_7, _hitsVec_T_49) node _hitsVec_T_51 = and(_hitsVec_T_46, _hitsVec_T_50) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_52 = bits(superpage_entries[2].tag, 8, 0) node _hitsVec_T_53 = bits(vpn[0], 8, 0) node _hitsVec_T_54 = eq(_hitsVec_T_52, _hitsVec_T_53) node _hitsVec_T_55 = or(hitsVec_ignore_8, _hitsVec_T_54) node _hitsVec_T_56 = and(_hitsVec_T_51, _hitsVec_T_55) node _hitsVec_T_57 = and(vm_enabled[0], _hitsVec_T_56) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_58 = bits(superpage_entries[3].tag, 26, 18) node _hitsVec_T_59 = bits(vpn[0], 26, 18) node _hitsVec_T_60 = eq(_hitsVec_T_58, _hitsVec_T_59) node _hitsVec_T_61 = or(hitsVec_ignore_9, _hitsVec_T_60) node _hitsVec_T_62 = and(superpage_entries[3].valid[0], _hitsVec_T_61) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_63 = bits(superpage_entries[3].tag, 17, 9) node _hitsVec_T_64 = bits(vpn[0], 17, 9) node _hitsVec_T_65 = eq(_hitsVec_T_63, _hitsVec_T_64) node _hitsVec_T_66 = or(hitsVec_ignore_10, _hitsVec_T_65) node _hitsVec_T_67 = and(_hitsVec_T_62, _hitsVec_T_66) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_68 = bits(superpage_entries[3].tag, 8, 0) node _hitsVec_T_69 = bits(vpn[0], 8, 0) node _hitsVec_T_70 = eq(_hitsVec_T_68, _hitsVec_T_69) node _hitsVec_T_71 = or(hitsVec_ignore_11, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_T_73 = and(vm_enabled[0], _hitsVec_T_72) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_74 = bits(special_entry.tag, 26, 18) node _hitsVec_T_75 = bits(vpn[0], 26, 18) node _hitsVec_T_76 = eq(_hitsVec_T_74, _hitsVec_T_75) node _hitsVec_T_77 = or(hitsVec_ignore_12, _hitsVec_T_76) node _hitsVec_T_78 = and(special_entry.valid[0], _hitsVec_T_77) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_79 = bits(special_entry.tag, 17, 9) node _hitsVec_T_80 = bits(vpn[0], 17, 9) node _hitsVec_T_81 = eq(_hitsVec_T_79, _hitsVec_T_80) node _hitsVec_T_82 = or(hitsVec_ignore_13, _hitsVec_T_81) node _hitsVec_T_83 = and(_hitsVec_T_78, _hitsVec_T_82) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_84 = bits(special_entry.tag, 8, 0) node _hitsVec_T_85 = bits(vpn[0], 8, 0) node _hitsVec_T_86 = eq(_hitsVec_T_84, _hitsVec_T_85) node _hitsVec_T_87 = or(hitsVec_ignore_14, _hitsVec_T_86) node _hitsVec_T_88 = and(_hitsVec_T_83, _hitsVec_T_87) node _hitsVec_T_89 = and(vm_enabled[0], _hitsVec_T_88) wire _hitsVec_WIRE : UInt<1>[7] connect _hitsVec_WIRE[0], _hitsVec_T_4 connect _hitsVec_WIRE[1], _hitsVec_T_9 connect _hitsVec_WIRE[2], _hitsVec_T_25 connect _hitsVec_WIRE[3], _hitsVec_T_41 connect _hitsVec_WIRE[4], _hitsVec_T_57 connect _hitsVec_WIRE[5], _hitsVec_T_73 connect _hitsVec_WIRE[6], _hitsVec_T_89 wire hitsVec : UInt<1>[7][1] connect hitsVec[0], _hitsVec_WIRE node real_hits_lo_hi = cat(hitsVec[0][2], hitsVec[0][1]) node real_hits_lo = cat(real_hits_lo_hi, hitsVec[0][0]) node real_hits_hi_lo = cat(hitsVec[0][4], hitsVec[0][3]) node real_hits_hi_hi = cat(hitsVec[0][6], hitsVec[0][5]) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node _real_hits_T = cat(real_hits_hi, real_hits_lo) wire real_hits : UInt<7>[1] connect real_hits[0], _real_hits_T node _hits_T = eq(vm_enabled[0], UInt<1>(0h0)) node _hits_T_1 = cat(_hits_T, real_hits[0]) wire hits : UInt<8>[1] connect hits[0], _hits_T_1 node _ppn_T = eq(vm_enabled[0], UInt<1>(0h0)) node _ppn_data_T = bits(vpn[0], 1, 0) wire _ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_1 : UInt<34> connect _ppn_data_WIRE_1, sectored_entries[0].data[_ppn_data_T] node _ppn_data_T_1 = bits(_ppn_data_WIRE_1, 0, 0) connect _ppn_data_WIRE.fragmented_superpage, _ppn_data_T_1 node _ppn_data_T_2 = bits(_ppn_data_WIRE_1, 1, 1) connect _ppn_data_WIRE.c, _ppn_data_T_2 node _ppn_data_T_3 = bits(_ppn_data_WIRE_1, 2, 2) connect _ppn_data_WIRE.eff, _ppn_data_T_3 node _ppn_data_T_4 = bits(_ppn_data_WIRE_1, 3, 3) connect _ppn_data_WIRE.paa, _ppn_data_T_4 node _ppn_data_T_5 = bits(_ppn_data_WIRE_1, 4, 4) connect _ppn_data_WIRE.pal, _ppn_data_T_5 node _ppn_data_T_6 = bits(_ppn_data_WIRE_1, 5, 5) connect _ppn_data_WIRE.pr, _ppn_data_T_6 node _ppn_data_T_7 = bits(_ppn_data_WIRE_1, 6, 6) connect _ppn_data_WIRE.px, _ppn_data_T_7 node _ppn_data_T_8 = bits(_ppn_data_WIRE_1, 7, 7) connect _ppn_data_WIRE.pw, _ppn_data_T_8 node _ppn_data_T_9 = bits(_ppn_data_WIRE_1, 8, 8) connect _ppn_data_WIRE.sr, _ppn_data_T_9 node _ppn_data_T_10 = bits(_ppn_data_WIRE_1, 9, 9) connect _ppn_data_WIRE.sx, _ppn_data_T_10 node _ppn_data_T_11 = bits(_ppn_data_WIRE_1, 10, 10) connect _ppn_data_WIRE.sw, _ppn_data_T_11 node _ppn_data_T_12 = bits(_ppn_data_WIRE_1, 11, 11) connect _ppn_data_WIRE.ae, _ppn_data_T_12 node _ppn_data_T_13 = bits(_ppn_data_WIRE_1, 12, 12) connect _ppn_data_WIRE.g, _ppn_data_T_13 node _ppn_data_T_14 = bits(_ppn_data_WIRE_1, 13, 13) connect _ppn_data_WIRE.u, _ppn_data_T_14 node _ppn_data_T_15 = bits(_ppn_data_WIRE_1, 33, 14) connect _ppn_data_WIRE.ppn, _ppn_data_T_15 inst ppn_data_barrier of OptimizationBarrier_EntryData_1 connect ppn_data_barrier.clock, clock connect ppn_data_barrier.reset, reset connect ppn_data_barrier.io.x.fragmented_superpage, _ppn_data_WIRE.fragmented_superpage connect ppn_data_barrier.io.x.c, _ppn_data_WIRE.c connect ppn_data_barrier.io.x.eff, _ppn_data_WIRE.eff connect ppn_data_barrier.io.x.paa, _ppn_data_WIRE.paa connect ppn_data_barrier.io.x.pal, _ppn_data_WIRE.pal connect ppn_data_barrier.io.x.pr, _ppn_data_WIRE.pr connect ppn_data_barrier.io.x.px, _ppn_data_WIRE.px connect ppn_data_barrier.io.x.pw, _ppn_data_WIRE.pw connect ppn_data_barrier.io.x.sr, _ppn_data_WIRE.sr connect ppn_data_barrier.io.x.sx, _ppn_data_WIRE.sx connect ppn_data_barrier.io.x.sw, _ppn_data_WIRE.sw connect ppn_data_barrier.io.x.ae, _ppn_data_WIRE.ae connect ppn_data_barrier.io.x.g, _ppn_data_WIRE.g connect ppn_data_barrier.io.x.u, _ppn_data_WIRE.u connect ppn_data_barrier.io.x.ppn, _ppn_data_WIRE.ppn node _ppn_data_T_16 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_3 : UInt<34> connect _ppn_data_WIRE_3, sectored_entries[1].data[_ppn_data_T_16] node _ppn_data_T_17 = bits(_ppn_data_WIRE_3, 0, 0) connect _ppn_data_WIRE_2.fragmented_superpage, _ppn_data_T_17 node _ppn_data_T_18 = bits(_ppn_data_WIRE_3, 1, 1) connect _ppn_data_WIRE_2.c, _ppn_data_T_18 node _ppn_data_T_19 = bits(_ppn_data_WIRE_3, 2, 2) connect _ppn_data_WIRE_2.eff, _ppn_data_T_19 node _ppn_data_T_20 = bits(_ppn_data_WIRE_3, 3, 3) connect _ppn_data_WIRE_2.paa, _ppn_data_T_20 node _ppn_data_T_21 = bits(_ppn_data_WIRE_3, 4, 4) connect _ppn_data_WIRE_2.pal, _ppn_data_T_21 node _ppn_data_T_22 = bits(_ppn_data_WIRE_3, 5, 5) connect _ppn_data_WIRE_2.pr, _ppn_data_T_22 node _ppn_data_T_23 = bits(_ppn_data_WIRE_3, 6, 6) connect _ppn_data_WIRE_2.px, _ppn_data_T_23 node _ppn_data_T_24 = bits(_ppn_data_WIRE_3, 7, 7) connect _ppn_data_WIRE_2.pw, _ppn_data_T_24 node _ppn_data_T_25 = bits(_ppn_data_WIRE_3, 8, 8) connect _ppn_data_WIRE_2.sr, _ppn_data_T_25 node _ppn_data_T_26 = bits(_ppn_data_WIRE_3, 9, 9) connect _ppn_data_WIRE_2.sx, _ppn_data_T_26 node _ppn_data_T_27 = bits(_ppn_data_WIRE_3, 10, 10) connect _ppn_data_WIRE_2.sw, _ppn_data_T_27 node _ppn_data_T_28 = bits(_ppn_data_WIRE_3, 11, 11) connect _ppn_data_WIRE_2.ae, _ppn_data_T_28 node _ppn_data_T_29 = bits(_ppn_data_WIRE_3, 12, 12) connect _ppn_data_WIRE_2.g, _ppn_data_T_29 node _ppn_data_T_30 = bits(_ppn_data_WIRE_3, 13, 13) connect _ppn_data_WIRE_2.u, _ppn_data_T_30 node _ppn_data_T_31 = bits(_ppn_data_WIRE_3, 33, 14) connect _ppn_data_WIRE_2.ppn, _ppn_data_T_31 inst ppn_data_barrier_1 of OptimizationBarrier_EntryData_2 connect ppn_data_barrier_1.clock, clock connect ppn_data_barrier_1.reset, reset connect ppn_data_barrier_1.io.x.fragmented_superpage, _ppn_data_WIRE_2.fragmented_superpage connect ppn_data_barrier_1.io.x.c, _ppn_data_WIRE_2.c connect ppn_data_barrier_1.io.x.eff, _ppn_data_WIRE_2.eff connect ppn_data_barrier_1.io.x.paa, _ppn_data_WIRE_2.paa connect ppn_data_barrier_1.io.x.pal, _ppn_data_WIRE_2.pal connect ppn_data_barrier_1.io.x.pr, _ppn_data_WIRE_2.pr connect ppn_data_barrier_1.io.x.px, _ppn_data_WIRE_2.px connect ppn_data_barrier_1.io.x.pw, _ppn_data_WIRE_2.pw connect ppn_data_barrier_1.io.x.sr, _ppn_data_WIRE_2.sr connect ppn_data_barrier_1.io.x.sx, _ppn_data_WIRE_2.sx connect ppn_data_barrier_1.io.x.sw, _ppn_data_WIRE_2.sw connect ppn_data_barrier_1.io.x.ae, _ppn_data_WIRE_2.ae connect ppn_data_barrier_1.io.x.g, _ppn_data_WIRE_2.g connect ppn_data_barrier_1.io.x.u, _ppn_data_WIRE_2.u connect ppn_data_barrier_1.io.x.ppn, _ppn_data_WIRE_2.ppn wire _ppn_data_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_5 : UInt<34> connect _ppn_data_WIRE_5, superpage_entries[0].data[0] node _ppn_data_T_32 = bits(_ppn_data_WIRE_5, 0, 0) connect _ppn_data_WIRE_4.fragmented_superpage, _ppn_data_T_32 node _ppn_data_T_33 = bits(_ppn_data_WIRE_5, 1, 1) connect _ppn_data_WIRE_4.c, _ppn_data_T_33 node _ppn_data_T_34 = bits(_ppn_data_WIRE_5, 2, 2) connect _ppn_data_WIRE_4.eff, _ppn_data_T_34 node _ppn_data_T_35 = bits(_ppn_data_WIRE_5, 3, 3) connect _ppn_data_WIRE_4.paa, _ppn_data_T_35 node _ppn_data_T_36 = bits(_ppn_data_WIRE_5, 4, 4) connect _ppn_data_WIRE_4.pal, _ppn_data_T_36 node _ppn_data_T_37 = bits(_ppn_data_WIRE_5, 5, 5) connect _ppn_data_WIRE_4.pr, _ppn_data_T_37 node _ppn_data_T_38 = bits(_ppn_data_WIRE_5, 6, 6) connect _ppn_data_WIRE_4.px, _ppn_data_T_38 node _ppn_data_T_39 = bits(_ppn_data_WIRE_5, 7, 7) connect _ppn_data_WIRE_4.pw, _ppn_data_T_39 node _ppn_data_T_40 = bits(_ppn_data_WIRE_5, 8, 8) connect _ppn_data_WIRE_4.sr, _ppn_data_T_40 node _ppn_data_T_41 = bits(_ppn_data_WIRE_5, 9, 9) connect _ppn_data_WIRE_4.sx, _ppn_data_T_41 node _ppn_data_T_42 = bits(_ppn_data_WIRE_5, 10, 10) connect _ppn_data_WIRE_4.sw, _ppn_data_T_42 node _ppn_data_T_43 = bits(_ppn_data_WIRE_5, 11, 11) connect _ppn_data_WIRE_4.ae, _ppn_data_T_43 node _ppn_data_T_44 = bits(_ppn_data_WIRE_5, 12, 12) connect _ppn_data_WIRE_4.g, _ppn_data_T_44 node _ppn_data_T_45 = bits(_ppn_data_WIRE_5, 13, 13) connect _ppn_data_WIRE_4.u, _ppn_data_T_45 node _ppn_data_T_46 = bits(_ppn_data_WIRE_5, 33, 14) connect _ppn_data_WIRE_4.ppn, _ppn_data_T_46 inst ppn_data_barrier_2 of OptimizationBarrier_EntryData_3 connect ppn_data_barrier_2.clock, clock connect ppn_data_barrier_2.reset, reset connect ppn_data_barrier_2.io.x.fragmented_superpage, _ppn_data_WIRE_4.fragmented_superpage connect ppn_data_barrier_2.io.x.c, _ppn_data_WIRE_4.c connect ppn_data_barrier_2.io.x.eff, _ppn_data_WIRE_4.eff connect ppn_data_barrier_2.io.x.paa, _ppn_data_WIRE_4.paa connect ppn_data_barrier_2.io.x.pal, _ppn_data_WIRE_4.pal connect ppn_data_barrier_2.io.x.pr, _ppn_data_WIRE_4.pr connect ppn_data_barrier_2.io.x.px, _ppn_data_WIRE_4.px connect ppn_data_barrier_2.io.x.pw, _ppn_data_WIRE_4.pw connect ppn_data_barrier_2.io.x.sr, _ppn_data_WIRE_4.sr connect ppn_data_barrier_2.io.x.sx, _ppn_data_WIRE_4.sx connect ppn_data_barrier_2.io.x.sw, _ppn_data_WIRE_4.sw connect ppn_data_barrier_2.io.x.ae, _ppn_data_WIRE_4.ae connect ppn_data_barrier_2.io.x.g, _ppn_data_WIRE_4.g connect ppn_data_barrier_2.io.x.u, _ppn_data_WIRE_4.u connect ppn_data_barrier_2.io.x.ppn, _ppn_data_WIRE_4.ppn node ppn_res = shr(ppn_data_barrier_2.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn[0], UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, ppn_data_barrier_2.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn[0], UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, ppn_data_barrier_2.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) wire _ppn_data_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_7 : UInt<34> connect _ppn_data_WIRE_7, superpage_entries[1].data[0] node _ppn_data_T_47 = bits(_ppn_data_WIRE_7, 0, 0) connect _ppn_data_WIRE_6.fragmented_superpage, _ppn_data_T_47 node _ppn_data_T_48 = bits(_ppn_data_WIRE_7, 1, 1) connect _ppn_data_WIRE_6.c, _ppn_data_T_48 node _ppn_data_T_49 = bits(_ppn_data_WIRE_7, 2, 2) connect _ppn_data_WIRE_6.eff, _ppn_data_T_49 node _ppn_data_T_50 = bits(_ppn_data_WIRE_7, 3, 3) connect _ppn_data_WIRE_6.paa, _ppn_data_T_50 node _ppn_data_T_51 = bits(_ppn_data_WIRE_7, 4, 4) connect _ppn_data_WIRE_6.pal, _ppn_data_T_51 node _ppn_data_T_52 = bits(_ppn_data_WIRE_7, 5, 5) connect _ppn_data_WIRE_6.pr, _ppn_data_T_52 node _ppn_data_T_53 = bits(_ppn_data_WIRE_7, 6, 6) connect _ppn_data_WIRE_6.px, _ppn_data_T_53 node _ppn_data_T_54 = bits(_ppn_data_WIRE_7, 7, 7) connect _ppn_data_WIRE_6.pw, _ppn_data_T_54 node _ppn_data_T_55 = bits(_ppn_data_WIRE_7, 8, 8) connect _ppn_data_WIRE_6.sr, _ppn_data_T_55 node _ppn_data_T_56 = bits(_ppn_data_WIRE_7, 9, 9) connect _ppn_data_WIRE_6.sx, _ppn_data_T_56 node _ppn_data_T_57 = bits(_ppn_data_WIRE_7, 10, 10) connect _ppn_data_WIRE_6.sw, _ppn_data_T_57 node _ppn_data_T_58 = bits(_ppn_data_WIRE_7, 11, 11) connect _ppn_data_WIRE_6.ae, _ppn_data_T_58 node _ppn_data_T_59 = bits(_ppn_data_WIRE_7, 12, 12) connect _ppn_data_WIRE_6.g, _ppn_data_T_59 node _ppn_data_T_60 = bits(_ppn_data_WIRE_7, 13, 13) connect _ppn_data_WIRE_6.u, _ppn_data_T_60 node _ppn_data_T_61 = bits(_ppn_data_WIRE_7, 33, 14) connect _ppn_data_WIRE_6.ppn, _ppn_data_T_61 inst ppn_data_barrier_3 of OptimizationBarrier_EntryData_4 connect ppn_data_barrier_3.clock, clock connect ppn_data_barrier_3.reset, reset connect ppn_data_barrier_3.io.x.fragmented_superpage, _ppn_data_WIRE_6.fragmented_superpage connect ppn_data_barrier_3.io.x.c, _ppn_data_WIRE_6.c connect ppn_data_barrier_3.io.x.eff, _ppn_data_WIRE_6.eff connect ppn_data_barrier_3.io.x.paa, _ppn_data_WIRE_6.paa connect ppn_data_barrier_3.io.x.pal, _ppn_data_WIRE_6.pal connect ppn_data_barrier_3.io.x.pr, _ppn_data_WIRE_6.pr connect ppn_data_barrier_3.io.x.px, _ppn_data_WIRE_6.px connect ppn_data_barrier_3.io.x.pw, _ppn_data_WIRE_6.pw connect ppn_data_barrier_3.io.x.sr, _ppn_data_WIRE_6.sr connect ppn_data_barrier_3.io.x.sx, _ppn_data_WIRE_6.sx connect ppn_data_barrier_3.io.x.sw, _ppn_data_WIRE_6.sw connect ppn_data_barrier_3.io.x.ae, _ppn_data_WIRE_6.ae connect ppn_data_barrier_3.io.x.g, _ppn_data_WIRE_6.g connect ppn_data_barrier_3.io.x.u, _ppn_data_WIRE_6.u connect ppn_data_barrier_3.io.x.ppn, _ppn_data_WIRE_6.ppn node ppn_res_1 = shr(ppn_data_barrier_3.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn[0], UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, ppn_data_barrier_3.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn[0], UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, ppn_data_barrier_3.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) wire _ppn_data_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_9 : UInt<34> connect _ppn_data_WIRE_9, superpage_entries[2].data[0] node _ppn_data_T_62 = bits(_ppn_data_WIRE_9, 0, 0) connect _ppn_data_WIRE_8.fragmented_superpage, _ppn_data_T_62 node _ppn_data_T_63 = bits(_ppn_data_WIRE_9, 1, 1) connect _ppn_data_WIRE_8.c, _ppn_data_T_63 node _ppn_data_T_64 = bits(_ppn_data_WIRE_9, 2, 2) connect _ppn_data_WIRE_8.eff, _ppn_data_T_64 node _ppn_data_T_65 = bits(_ppn_data_WIRE_9, 3, 3) connect _ppn_data_WIRE_8.paa, _ppn_data_T_65 node _ppn_data_T_66 = bits(_ppn_data_WIRE_9, 4, 4) connect _ppn_data_WIRE_8.pal, _ppn_data_T_66 node _ppn_data_T_67 = bits(_ppn_data_WIRE_9, 5, 5) connect _ppn_data_WIRE_8.pr, _ppn_data_T_67 node _ppn_data_T_68 = bits(_ppn_data_WIRE_9, 6, 6) connect _ppn_data_WIRE_8.px, _ppn_data_T_68 node _ppn_data_T_69 = bits(_ppn_data_WIRE_9, 7, 7) connect _ppn_data_WIRE_8.pw, _ppn_data_T_69 node _ppn_data_T_70 = bits(_ppn_data_WIRE_9, 8, 8) connect _ppn_data_WIRE_8.sr, _ppn_data_T_70 node _ppn_data_T_71 = bits(_ppn_data_WIRE_9, 9, 9) connect _ppn_data_WIRE_8.sx, _ppn_data_T_71 node _ppn_data_T_72 = bits(_ppn_data_WIRE_9, 10, 10) connect _ppn_data_WIRE_8.sw, _ppn_data_T_72 node _ppn_data_T_73 = bits(_ppn_data_WIRE_9, 11, 11) connect _ppn_data_WIRE_8.ae, _ppn_data_T_73 node _ppn_data_T_74 = bits(_ppn_data_WIRE_9, 12, 12) connect _ppn_data_WIRE_8.g, _ppn_data_T_74 node _ppn_data_T_75 = bits(_ppn_data_WIRE_9, 13, 13) connect _ppn_data_WIRE_8.u, _ppn_data_T_75 node _ppn_data_T_76 = bits(_ppn_data_WIRE_9, 33, 14) connect _ppn_data_WIRE_8.ppn, _ppn_data_T_76 inst ppn_data_barrier_4 of OptimizationBarrier_EntryData_5 connect ppn_data_barrier_4.clock, clock connect ppn_data_barrier_4.reset, reset connect ppn_data_barrier_4.io.x.fragmented_superpage, _ppn_data_WIRE_8.fragmented_superpage connect ppn_data_barrier_4.io.x.c, _ppn_data_WIRE_8.c connect ppn_data_barrier_4.io.x.eff, _ppn_data_WIRE_8.eff connect ppn_data_barrier_4.io.x.paa, _ppn_data_WIRE_8.paa connect ppn_data_barrier_4.io.x.pal, _ppn_data_WIRE_8.pal connect ppn_data_barrier_4.io.x.pr, _ppn_data_WIRE_8.pr connect ppn_data_barrier_4.io.x.px, _ppn_data_WIRE_8.px connect ppn_data_barrier_4.io.x.pw, _ppn_data_WIRE_8.pw connect ppn_data_barrier_4.io.x.sr, _ppn_data_WIRE_8.sr connect ppn_data_barrier_4.io.x.sx, _ppn_data_WIRE_8.sx connect ppn_data_barrier_4.io.x.sw, _ppn_data_WIRE_8.sw connect ppn_data_barrier_4.io.x.ae, _ppn_data_WIRE_8.ae connect ppn_data_barrier_4.io.x.g, _ppn_data_WIRE_8.g connect ppn_data_barrier_4.io.x.u, _ppn_data_WIRE_8.u connect ppn_data_barrier_4.io.x.ppn, _ppn_data_WIRE_8.ppn node ppn_res_2 = shr(ppn_data_barrier_4.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn[0], UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, ppn_data_barrier_4.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn[0], UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, ppn_data_barrier_4.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) wire _ppn_data_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_11 : UInt<34> connect _ppn_data_WIRE_11, superpage_entries[3].data[0] node _ppn_data_T_77 = bits(_ppn_data_WIRE_11, 0, 0) connect _ppn_data_WIRE_10.fragmented_superpage, _ppn_data_T_77 node _ppn_data_T_78 = bits(_ppn_data_WIRE_11, 1, 1) connect _ppn_data_WIRE_10.c, _ppn_data_T_78 node _ppn_data_T_79 = bits(_ppn_data_WIRE_11, 2, 2) connect _ppn_data_WIRE_10.eff, _ppn_data_T_79 node _ppn_data_T_80 = bits(_ppn_data_WIRE_11, 3, 3) connect _ppn_data_WIRE_10.paa, _ppn_data_T_80 node _ppn_data_T_81 = bits(_ppn_data_WIRE_11, 4, 4) connect _ppn_data_WIRE_10.pal, _ppn_data_T_81 node _ppn_data_T_82 = bits(_ppn_data_WIRE_11, 5, 5) connect _ppn_data_WIRE_10.pr, _ppn_data_T_82 node _ppn_data_T_83 = bits(_ppn_data_WIRE_11, 6, 6) connect _ppn_data_WIRE_10.px, _ppn_data_T_83 node _ppn_data_T_84 = bits(_ppn_data_WIRE_11, 7, 7) connect _ppn_data_WIRE_10.pw, _ppn_data_T_84 node _ppn_data_T_85 = bits(_ppn_data_WIRE_11, 8, 8) connect _ppn_data_WIRE_10.sr, _ppn_data_T_85 node _ppn_data_T_86 = bits(_ppn_data_WIRE_11, 9, 9) connect _ppn_data_WIRE_10.sx, _ppn_data_T_86 node _ppn_data_T_87 = bits(_ppn_data_WIRE_11, 10, 10) connect _ppn_data_WIRE_10.sw, _ppn_data_T_87 node _ppn_data_T_88 = bits(_ppn_data_WIRE_11, 11, 11) connect _ppn_data_WIRE_10.ae, _ppn_data_T_88 node _ppn_data_T_89 = bits(_ppn_data_WIRE_11, 12, 12) connect _ppn_data_WIRE_10.g, _ppn_data_T_89 node _ppn_data_T_90 = bits(_ppn_data_WIRE_11, 13, 13) connect _ppn_data_WIRE_10.u, _ppn_data_T_90 node _ppn_data_T_91 = bits(_ppn_data_WIRE_11, 33, 14) connect _ppn_data_WIRE_10.ppn, _ppn_data_T_91 inst ppn_data_barrier_5 of OptimizationBarrier_EntryData_6 connect ppn_data_barrier_5.clock, clock connect ppn_data_barrier_5.reset, reset connect ppn_data_barrier_5.io.x.fragmented_superpage, _ppn_data_WIRE_10.fragmented_superpage connect ppn_data_barrier_5.io.x.c, _ppn_data_WIRE_10.c connect ppn_data_barrier_5.io.x.eff, _ppn_data_WIRE_10.eff connect ppn_data_barrier_5.io.x.paa, _ppn_data_WIRE_10.paa connect ppn_data_barrier_5.io.x.pal, _ppn_data_WIRE_10.pal connect ppn_data_barrier_5.io.x.pr, _ppn_data_WIRE_10.pr connect ppn_data_barrier_5.io.x.px, _ppn_data_WIRE_10.px connect ppn_data_barrier_5.io.x.pw, _ppn_data_WIRE_10.pw connect ppn_data_barrier_5.io.x.sr, _ppn_data_WIRE_10.sr connect ppn_data_barrier_5.io.x.sx, _ppn_data_WIRE_10.sx connect ppn_data_barrier_5.io.x.sw, _ppn_data_WIRE_10.sw connect ppn_data_barrier_5.io.x.ae, _ppn_data_WIRE_10.ae connect ppn_data_barrier_5.io.x.g, _ppn_data_WIRE_10.g connect ppn_data_barrier_5.io.x.u, _ppn_data_WIRE_10.u connect ppn_data_barrier_5.io.x.ppn, _ppn_data_WIRE_10.ppn node ppn_res_3 = shr(ppn_data_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn[0], UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, ppn_data_barrier_5.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn[0], UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, ppn_data_barrier_5.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) wire _ppn_data_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_13 : UInt<34> connect _ppn_data_WIRE_13, special_entry.data[0] node _ppn_data_T_92 = bits(_ppn_data_WIRE_13, 0, 0) connect _ppn_data_WIRE_12.fragmented_superpage, _ppn_data_T_92 node _ppn_data_T_93 = bits(_ppn_data_WIRE_13, 1, 1) connect _ppn_data_WIRE_12.c, _ppn_data_T_93 node _ppn_data_T_94 = bits(_ppn_data_WIRE_13, 2, 2) connect _ppn_data_WIRE_12.eff, _ppn_data_T_94 node _ppn_data_T_95 = bits(_ppn_data_WIRE_13, 3, 3) connect _ppn_data_WIRE_12.paa, _ppn_data_T_95 node _ppn_data_T_96 = bits(_ppn_data_WIRE_13, 4, 4) connect _ppn_data_WIRE_12.pal, _ppn_data_T_96 node _ppn_data_T_97 = bits(_ppn_data_WIRE_13, 5, 5) connect _ppn_data_WIRE_12.pr, _ppn_data_T_97 node _ppn_data_T_98 = bits(_ppn_data_WIRE_13, 6, 6) connect _ppn_data_WIRE_12.px, _ppn_data_T_98 node _ppn_data_T_99 = bits(_ppn_data_WIRE_13, 7, 7) connect _ppn_data_WIRE_12.pw, _ppn_data_T_99 node _ppn_data_T_100 = bits(_ppn_data_WIRE_13, 8, 8) connect _ppn_data_WIRE_12.sr, _ppn_data_T_100 node _ppn_data_T_101 = bits(_ppn_data_WIRE_13, 9, 9) connect _ppn_data_WIRE_12.sx, _ppn_data_T_101 node _ppn_data_T_102 = bits(_ppn_data_WIRE_13, 10, 10) connect _ppn_data_WIRE_12.sw, _ppn_data_T_102 node _ppn_data_T_103 = bits(_ppn_data_WIRE_13, 11, 11) connect _ppn_data_WIRE_12.ae, _ppn_data_T_103 node _ppn_data_T_104 = bits(_ppn_data_WIRE_13, 12, 12) connect _ppn_data_WIRE_12.g, _ppn_data_T_104 node _ppn_data_T_105 = bits(_ppn_data_WIRE_13, 13, 13) connect _ppn_data_WIRE_12.u, _ppn_data_T_105 node _ppn_data_T_106 = bits(_ppn_data_WIRE_13, 33, 14) connect _ppn_data_WIRE_12.ppn, _ppn_data_T_106 inst ppn_data_barrier_6 of OptimizationBarrier_EntryData_7 connect ppn_data_barrier_6.clock, clock connect ppn_data_barrier_6.reset, reset connect ppn_data_barrier_6.io.x.fragmented_superpage, _ppn_data_WIRE_12.fragmented_superpage connect ppn_data_barrier_6.io.x.c, _ppn_data_WIRE_12.c connect ppn_data_barrier_6.io.x.eff, _ppn_data_WIRE_12.eff connect ppn_data_barrier_6.io.x.paa, _ppn_data_WIRE_12.paa connect ppn_data_barrier_6.io.x.pal, _ppn_data_WIRE_12.pal connect ppn_data_barrier_6.io.x.pr, _ppn_data_WIRE_12.pr connect ppn_data_barrier_6.io.x.px, _ppn_data_WIRE_12.px connect ppn_data_barrier_6.io.x.pw, _ppn_data_WIRE_12.pw connect ppn_data_barrier_6.io.x.sr, _ppn_data_WIRE_12.sr connect ppn_data_barrier_6.io.x.sx, _ppn_data_WIRE_12.sx connect ppn_data_barrier_6.io.x.sw, _ppn_data_WIRE_12.sw connect ppn_data_barrier_6.io.x.ae, _ppn_data_WIRE_12.ae connect ppn_data_barrier_6.io.x.g, _ppn_data_WIRE_12.g connect ppn_data_barrier_6.io.x.u, _ppn_data_WIRE_12.u connect ppn_data_barrier_6.io.x.ppn, _ppn_data_WIRE_12.ppn node ppn_res_4 = shr(ppn_data_barrier_6.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn[0], UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, ppn_data_barrier_6.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn[0], UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, ppn_data_barrier_6.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn[0], 19, 0) node _ppn_T_42 = mux(hitsVec[0][0], ppn_data_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec[0][1], ppn_data_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec[0][2], _ppn_T_8, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec[0][3], _ppn_T_16, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec[0][4], _ppn_T_24, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec[0][5], _ppn_T_32, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec[0][6], _ppn_T_40, UInt<1>(0h0)) node _ppn_T_49 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_50 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_51 = or(_ppn_T_50, _ppn_T_44) node _ppn_T_52 = or(_ppn_T_51, _ppn_T_45) node _ppn_T_53 = or(_ppn_T_52, _ppn_T_46) node _ppn_T_54 = or(_ppn_T_53, _ppn_T_47) node _ppn_T_55 = or(_ppn_T_54, _ppn_T_48) node _ppn_T_56 = or(_ppn_T_55, _ppn_T_49) wire _ppn_WIRE : UInt<20> connect _ppn_WIRE, _ppn_T_56 wire ppn : UInt<20>[1] connect ppn[0], _ppn_WIRE when do_refill : wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable[0] connect newEntry.u, io.ptw.resp.bits.pte.u connect newEntry.g, io.ptw.resp.bits.pte.g connect newEntry.ae, io.ptw.resp.bits.ae_final node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r[0] connect newEntry.pw, prot_w[0] connect newEntry.px, prot_x[0] connect newEntry.pal, prot_al[0] connect newEntry.paa, prot_aa[0] connect newEntry.eff, prot_eff[0] connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag, r_refill_tag node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, newEntry.fragmented_superpage) node special_entry_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node special_entry_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node special_entry_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag, r_refill_tag node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_0_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_0_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag, r_refill_tag node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_1_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_1_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag, r_refill_tag node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_2_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_2_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag, r_refill_tag node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_3_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_3_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T else : node waddr = mux(r_sectored_hit, r_sectored_hit_addr, r_sectored_repl_addr) node _T_7 = eq(waddr, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) connect sectored_entries[0].tag, r_refill_tag connect sectored_entries[0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0].valid[idx], UInt<1>(0h1) node sectored_entries_0_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_0_data_lo_lo = cat(sectored_entries_0_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_0_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_lo_hi = cat(sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo) node sectored_entries_0_data_lo = cat(sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo) node sectored_entries_0_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_0_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_0_data_hi_lo = cat(sectored_entries_0_data_hi_lo_hi, sectored_entries_0_data_hi_lo_lo) node sectored_entries_0_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_0_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_hi_hi = cat(sectored_entries_0_data_hi_hi_hi, sectored_entries_0_data_hi_hi_lo) node sectored_entries_0_data_hi = cat(sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo) node _sectored_entries_0_data_T = cat(sectored_entries_0_data_hi, sectored_entries_0_data_lo) connect sectored_entries[0].data[idx], _sectored_entries_0_data_T node _T_9 = eq(waddr, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_10 : connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) connect sectored_entries[1].tag, r_refill_tag connect sectored_entries[1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[1].valid[idx_1], UInt<1>(0h1) node sectored_entries_1_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_1_data_lo_lo = cat(sectored_entries_1_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_1_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_lo_hi = cat(sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo) node sectored_entries_1_data_lo = cat(sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo) node sectored_entries_1_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_1_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_1_data_hi_lo = cat(sectored_entries_1_data_hi_lo_hi, sectored_entries_1_data_hi_lo_lo) node sectored_entries_1_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_1_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_hi_hi = cat(sectored_entries_1_data_hi_hi_hi, sectored_entries_1_data_hi_hi_lo) node sectored_entries_1_data_hi = cat(sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo) node _sectored_entries_1_data_T = cat(sectored_entries_1_data_hi, sectored_entries_1_data_lo) connect sectored_entries[1].data[idx_1], _sectored_entries_1_data_T node _entries_T = bits(vpn[0], 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<34> connect _entries_WIRE_1, sectored_entries[0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.sr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.sx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.sw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.ae, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.g, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.u, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 33, 14) connect _entries_WIRE.ppn, _entries_T_15 inst entries_barrier of OptimizationBarrier_EntryData_8 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.ae, _entries_WIRE.ae connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_16 = bits(vpn[0], 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<34> connect _entries_WIRE_3, sectored_entries[1].data[_entries_T_16] node _entries_T_17 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.pr, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.px, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.pw, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.sr, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.sx, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.sw, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.ae, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.g, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.u, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 33, 14) connect _entries_WIRE_2.ppn, _entries_T_31 inst entries_barrier_1 of OptimizationBarrier_EntryData_9 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.ae, _entries_WIRE_2.ae connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<34> connect _entries_WIRE_5, superpage_entries[0].data[0] node _entries_T_32 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.pr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.px, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.pw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.sr, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.sx, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.sw, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.ae, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.g, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.u, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_5, 33, 14) connect _entries_WIRE_4.ppn, _entries_T_46 inst entries_barrier_2 of OptimizationBarrier_EntryData_10 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.ae, _entries_WIRE_4.ae connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<34> connect _entries_WIRE_7, superpage_entries[1].data[0] node _entries_T_47 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.pr, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.px, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.pw, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.sr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.sx, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.sw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.ae, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.g, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.u, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_7, 33, 14) connect _entries_WIRE_6.ppn, _entries_T_61 inst entries_barrier_3 of OptimizationBarrier_EntryData_11 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.ae, _entries_WIRE_6.ae connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<34> connect _entries_WIRE_9, superpage_entries[2].data[0] node _entries_T_62 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.pr, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.px, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.pw, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.sr, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.sx, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.sw, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.ae, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.g, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.u, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_9, 33, 14) connect _entries_WIRE_8.ppn, _entries_T_76 inst entries_barrier_4 of OptimizationBarrier_EntryData_12 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.ae, _entries_WIRE_8.ae connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<34> connect _entries_WIRE_11, superpage_entries[3].data[0] node _entries_T_77 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.pr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.px, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.pw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.ae, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.g, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.u, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_11, 33, 14) connect _entries_WIRE_10.ppn, _entries_T_91 inst entries_barrier_5 of OptimizationBarrier_EntryData_13 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.ae, _entries_WIRE_10.ae connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<34> connect _entries_WIRE_13, special_entry.data[0] node _entries_T_92 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.pr, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.px, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.pw, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.sr, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.sx, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.sw, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.ae, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.g, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.u, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_13, 33, 14) connect _entries_WIRE_12.ppn, _entries_T_106 inst entries_barrier_6 of OptimizationBarrier_EntryData_14 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.ae, _entries_WIRE_12.ae connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[7] connect _entries_WIRE_14[0], entries_barrier.io.y connect _entries_WIRE_14[1], entries_barrier_1.io.y connect _entries_WIRE_14[2], entries_barrier_2.io.y connect _entries_WIRE_14[3], entries_barrier_3.io.y connect _entries_WIRE_14[4], entries_barrier_4.io.y connect _entries_WIRE_14[5], entries_barrier_5.io.y connect _entries_WIRE_14[6], entries_barrier_6.io.y wire entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[7][1] connect entries[0], _entries_WIRE_14 node _normal_entries_T = bits(vpn[0], 1, 0) wire _normal_entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_1 : UInt<34> connect _normal_entries_WIRE_1, sectored_entries[0].data[_normal_entries_T] node _normal_entries_T_1 = bits(_normal_entries_WIRE_1, 0, 0) connect _normal_entries_WIRE.fragmented_superpage, _normal_entries_T_1 node _normal_entries_T_2 = bits(_normal_entries_WIRE_1, 1, 1) connect _normal_entries_WIRE.c, _normal_entries_T_2 node _normal_entries_T_3 = bits(_normal_entries_WIRE_1, 2, 2) connect _normal_entries_WIRE.eff, _normal_entries_T_3 node _normal_entries_T_4 = bits(_normal_entries_WIRE_1, 3, 3) connect _normal_entries_WIRE.paa, _normal_entries_T_4 node _normal_entries_T_5 = bits(_normal_entries_WIRE_1, 4, 4) connect _normal_entries_WIRE.pal, _normal_entries_T_5 node _normal_entries_T_6 = bits(_normal_entries_WIRE_1, 5, 5) connect _normal_entries_WIRE.pr, _normal_entries_T_6 node _normal_entries_T_7 = bits(_normal_entries_WIRE_1, 6, 6) connect _normal_entries_WIRE.px, _normal_entries_T_7 node _normal_entries_T_8 = bits(_normal_entries_WIRE_1, 7, 7) connect _normal_entries_WIRE.pw, _normal_entries_T_8 node _normal_entries_T_9 = bits(_normal_entries_WIRE_1, 8, 8) connect _normal_entries_WIRE.sr, _normal_entries_T_9 node _normal_entries_T_10 = bits(_normal_entries_WIRE_1, 9, 9) connect _normal_entries_WIRE.sx, _normal_entries_T_10 node _normal_entries_T_11 = bits(_normal_entries_WIRE_1, 10, 10) connect _normal_entries_WIRE.sw, _normal_entries_T_11 node _normal_entries_T_12 = bits(_normal_entries_WIRE_1, 11, 11) connect _normal_entries_WIRE.ae, _normal_entries_T_12 node _normal_entries_T_13 = bits(_normal_entries_WIRE_1, 12, 12) connect _normal_entries_WIRE.g, _normal_entries_T_13 node _normal_entries_T_14 = bits(_normal_entries_WIRE_1, 13, 13) connect _normal_entries_WIRE.u, _normal_entries_T_14 node _normal_entries_T_15 = bits(_normal_entries_WIRE_1, 33, 14) connect _normal_entries_WIRE.ppn, _normal_entries_T_15 inst normal_entries_barrier of OptimizationBarrier_EntryData_15 connect normal_entries_barrier.clock, clock connect normal_entries_barrier.reset, reset connect normal_entries_barrier.io.x.fragmented_superpage, _normal_entries_WIRE.fragmented_superpage connect normal_entries_barrier.io.x.c, _normal_entries_WIRE.c connect normal_entries_barrier.io.x.eff, _normal_entries_WIRE.eff connect normal_entries_barrier.io.x.paa, _normal_entries_WIRE.paa connect normal_entries_barrier.io.x.pal, _normal_entries_WIRE.pal connect normal_entries_barrier.io.x.pr, _normal_entries_WIRE.pr connect normal_entries_barrier.io.x.px, _normal_entries_WIRE.px connect normal_entries_barrier.io.x.pw, _normal_entries_WIRE.pw connect normal_entries_barrier.io.x.sr, _normal_entries_WIRE.sr connect normal_entries_barrier.io.x.sx, _normal_entries_WIRE.sx connect normal_entries_barrier.io.x.sw, _normal_entries_WIRE.sw connect normal_entries_barrier.io.x.ae, _normal_entries_WIRE.ae connect normal_entries_barrier.io.x.g, _normal_entries_WIRE.g connect normal_entries_barrier.io.x.u, _normal_entries_WIRE.u connect normal_entries_barrier.io.x.ppn, _normal_entries_WIRE.ppn node _normal_entries_T_16 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_3 : UInt<34> connect _normal_entries_WIRE_3, sectored_entries[1].data[_normal_entries_T_16] node _normal_entries_T_17 = bits(_normal_entries_WIRE_3, 0, 0) connect _normal_entries_WIRE_2.fragmented_superpage, _normal_entries_T_17 node _normal_entries_T_18 = bits(_normal_entries_WIRE_3, 1, 1) connect _normal_entries_WIRE_2.c, _normal_entries_T_18 node _normal_entries_T_19 = bits(_normal_entries_WIRE_3, 2, 2) connect _normal_entries_WIRE_2.eff, _normal_entries_T_19 node _normal_entries_T_20 = bits(_normal_entries_WIRE_3, 3, 3) connect _normal_entries_WIRE_2.paa, _normal_entries_T_20 node _normal_entries_T_21 = bits(_normal_entries_WIRE_3, 4, 4) connect _normal_entries_WIRE_2.pal, _normal_entries_T_21 node _normal_entries_T_22 = bits(_normal_entries_WIRE_3, 5, 5) connect _normal_entries_WIRE_2.pr, _normal_entries_T_22 node _normal_entries_T_23 = bits(_normal_entries_WIRE_3, 6, 6) connect _normal_entries_WIRE_2.px, _normal_entries_T_23 node _normal_entries_T_24 = bits(_normal_entries_WIRE_3, 7, 7) connect _normal_entries_WIRE_2.pw, _normal_entries_T_24 node _normal_entries_T_25 = bits(_normal_entries_WIRE_3, 8, 8) connect _normal_entries_WIRE_2.sr, _normal_entries_T_25 node _normal_entries_T_26 = bits(_normal_entries_WIRE_3, 9, 9) connect _normal_entries_WIRE_2.sx, _normal_entries_T_26 node _normal_entries_T_27 = bits(_normal_entries_WIRE_3, 10, 10) connect _normal_entries_WIRE_2.sw, _normal_entries_T_27 node _normal_entries_T_28 = bits(_normal_entries_WIRE_3, 11, 11) connect _normal_entries_WIRE_2.ae, _normal_entries_T_28 node _normal_entries_T_29 = bits(_normal_entries_WIRE_3, 12, 12) connect _normal_entries_WIRE_2.g, _normal_entries_T_29 node _normal_entries_T_30 = bits(_normal_entries_WIRE_3, 13, 13) connect _normal_entries_WIRE_2.u, _normal_entries_T_30 node _normal_entries_T_31 = bits(_normal_entries_WIRE_3, 33, 14) connect _normal_entries_WIRE_2.ppn, _normal_entries_T_31 inst normal_entries_barrier_1 of OptimizationBarrier_EntryData_16 connect normal_entries_barrier_1.clock, clock connect normal_entries_barrier_1.reset, reset connect normal_entries_barrier_1.io.x.fragmented_superpage, _normal_entries_WIRE_2.fragmented_superpage connect normal_entries_barrier_1.io.x.c, _normal_entries_WIRE_2.c connect normal_entries_barrier_1.io.x.eff, _normal_entries_WIRE_2.eff connect normal_entries_barrier_1.io.x.paa, _normal_entries_WIRE_2.paa connect normal_entries_barrier_1.io.x.pal, _normal_entries_WIRE_2.pal connect normal_entries_barrier_1.io.x.pr, _normal_entries_WIRE_2.pr connect normal_entries_barrier_1.io.x.px, _normal_entries_WIRE_2.px connect normal_entries_barrier_1.io.x.pw, _normal_entries_WIRE_2.pw connect normal_entries_barrier_1.io.x.sr, _normal_entries_WIRE_2.sr connect normal_entries_barrier_1.io.x.sx, _normal_entries_WIRE_2.sx connect normal_entries_barrier_1.io.x.sw, _normal_entries_WIRE_2.sw connect normal_entries_barrier_1.io.x.ae, _normal_entries_WIRE_2.ae connect normal_entries_barrier_1.io.x.g, _normal_entries_WIRE_2.g connect normal_entries_barrier_1.io.x.u, _normal_entries_WIRE_2.u connect normal_entries_barrier_1.io.x.ppn, _normal_entries_WIRE_2.ppn wire _normal_entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_5 : UInt<34> connect _normal_entries_WIRE_5, superpage_entries[0].data[0] node _normal_entries_T_32 = bits(_normal_entries_WIRE_5, 0, 0) connect _normal_entries_WIRE_4.fragmented_superpage, _normal_entries_T_32 node _normal_entries_T_33 = bits(_normal_entries_WIRE_5, 1, 1) connect _normal_entries_WIRE_4.c, _normal_entries_T_33 node _normal_entries_T_34 = bits(_normal_entries_WIRE_5, 2, 2) connect _normal_entries_WIRE_4.eff, _normal_entries_T_34 node _normal_entries_T_35 = bits(_normal_entries_WIRE_5, 3, 3) connect _normal_entries_WIRE_4.paa, _normal_entries_T_35 node _normal_entries_T_36 = bits(_normal_entries_WIRE_5, 4, 4) connect _normal_entries_WIRE_4.pal, _normal_entries_T_36 node _normal_entries_T_37 = bits(_normal_entries_WIRE_5, 5, 5) connect _normal_entries_WIRE_4.pr, _normal_entries_T_37 node _normal_entries_T_38 = bits(_normal_entries_WIRE_5, 6, 6) connect _normal_entries_WIRE_4.px, _normal_entries_T_38 node _normal_entries_T_39 = bits(_normal_entries_WIRE_5, 7, 7) connect _normal_entries_WIRE_4.pw, _normal_entries_T_39 node _normal_entries_T_40 = bits(_normal_entries_WIRE_5, 8, 8) connect _normal_entries_WIRE_4.sr, _normal_entries_T_40 node _normal_entries_T_41 = bits(_normal_entries_WIRE_5, 9, 9) connect _normal_entries_WIRE_4.sx, _normal_entries_T_41 node _normal_entries_T_42 = bits(_normal_entries_WIRE_5, 10, 10) connect _normal_entries_WIRE_4.sw, _normal_entries_T_42 node _normal_entries_T_43 = bits(_normal_entries_WIRE_5, 11, 11) connect _normal_entries_WIRE_4.ae, _normal_entries_T_43 node _normal_entries_T_44 = bits(_normal_entries_WIRE_5, 12, 12) connect _normal_entries_WIRE_4.g, _normal_entries_T_44 node _normal_entries_T_45 = bits(_normal_entries_WIRE_5, 13, 13) connect _normal_entries_WIRE_4.u, _normal_entries_T_45 node _normal_entries_T_46 = bits(_normal_entries_WIRE_5, 33, 14) connect _normal_entries_WIRE_4.ppn, _normal_entries_T_46 inst normal_entries_barrier_2 of OptimizationBarrier_EntryData_17 connect normal_entries_barrier_2.clock, clock connect normal_entries_barrier_2.reset, reset connect normal_entries_barrier_2.io.x.fragmented_superpage, _normal_entries_WIRE_4.fragmented_superpage connect normal_entries_barrier_2.io.x.c, _normal_entries_WIRE_4.c connect normal_entries_barrier_2.io.x.eff, _normal_entries_WIRE_4.eff connect normal_entries_barrier_2.io.x.paa, _normal_entries_WIRE_4.paa connect normal_entries_barrier_2.io.x.pal, _normal_entries_WIRE_4.pal connect normal_entries_barrier_2.io.x.pr, _normal_entries_WIRE_4.pr connect normal_entries_barrier_2.io.x.px, _normal_entries_WIRE_4.px connect normal_entries_barrier_2.io.x.pw, _normal_entries_WIRE_4.pw connect normal_entries_barrier_2.io.x.sr, _normal_entries_WIRE_4.sr connect normal_entries_barrier_2.io.x.sx, _normal_entries_WIRE_4.sx connect normal_entries_barrier_2.io.x.sw, _normal_entries_WIRE_4.sw connect normal_entries_barrier_2.io.x.ae, _normal_entries_WIRE_4.ae connect normal_entries_barrier_2.io.x.g, _normal_entries_WIRE_4.g connect normal_entries_barrier_2.io.x.u, _normal_entries_WIRE_4.u connect normal_entries_barrier_2.io.x.ppn, _normal_entries_WIRE_4.ppn wire _normal_entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_7 : UInt<34> connect _normal_entries_WIRE_7, superpage_entries[1].data[0] node _normal_entries_T_47 = bits(_normal_entries_WIRE_7, 0, 0) connect _normal_entries_WIRE_6.fragmented_superpage, _normal_entries_T_47 node _normal_entries_T_48 = bits(_normal_entries_WIRE_7, 1, 1) connect _normal_entries_WIRE_6.c, _normal_entries_T_48 node _normal_entries_T_49 = bits(_normal_entries_WIRE_7, 2, 2) connect _normal_entries_WIRE_6.eff, _normal_entries_T_49 node _normal_entries_T_50 = bits(_normal_entries_WIRE_7, 3, 3) connect _normal_entries_WIRE_6.paa, _normal_entries_T_50 node _normal_entries_T_51 = bits(_normal_entries_WIRE_7, 4, 4) connect _normal_entries_WIRE_6.pal, _normal_entries_T_51 node _normal_entries_T_52 = bits(_normal_entries_WIRE_7, 5, 5) connect _normal_entries_WIRE_6.pr, _normal_entries_T_52 node _normal_entries_T_53 = bits(_normal_entries_WIRE_7, 6, 6) connect _normal_entries_WIRE_6.px, _normal_entries_T_53 node _normal_entries_T_54 = bits(_normal_entries_WIRE_7, 7, 7) connect _normal_entries_WIRE_6.pw, _normal_entries_T_54 node _normal_entries_T_55 = bits(_normal_entries_WIRE_7, 8, 8) connect _normal_entries_WIRE_6.sr, _normal_entries_T_55 node _normal_entries_T_56 = bits(_normal_entries_WIRE_7, 9, 9) connect _normal_entries_WIRE_6.sx, _normal_entries_T_56 node _normal_entries_T_57 = bits(_normal_entries_WIRE_7, 10, 10) connect _normal_entries_WIRE_6.sw, _normal_entries_T_57 node _normal_entries_T_58 = bits(_normal_entries_WIRE_7, 11, 11) connect _normal_entries_WIRE_6.ae, _normal_entries_T_58 node _normal_entries_T_59 = bits(_normal_entries_WIRE_7, 12, 12) connect _normal_entries_WIRE_6.g, _normal_entries_T_59 node _normal_entries_T_60 = bits(_normal_entries_WIRE_7, 13, 13) connect _normal_entries_WIRE_6.u, _normal_entries_T_60 node _normal_entries_T_61 = bits(_normal_entries_WIRE_7, 33, 14) connect _normal_entries_WIRE_6.ppn, _normal_entries_T_61 inst normal_entries_barrier_3 of OptimizationBarrier_EntryData_18 connect normal_entries_barrier_3.clock, clock connect normal_entries_barrier_3.reset, reset connect normal_entries_barrier_3.io.x.fragmented_superpage, _normal_entries_WIRE_6.fragmented_superpage connect normal_entries_barrier_3.io.x.c, _normal_entries_WIRE_6.c connect normal_entries_barrier_3.io.x.eff, _normal_entries_WIRE_6.eff connect normal_entries_barrier_3.io.x.paa, _normal_entries_WIRE_6.paa connect normal_entries_barrier_3.io.x.pal, _normal_entries_WIRE_6.pal connect normal_entries_barrier_3.io.x.pr, _normal_entries_WIRE_6.pr connect normal_entries_barrier_3.io.x.px, _normal_entries_WIRE_6.px connect normal_entries_barrier_3.io.x.pw, _normal_entries_WIRE_6.pw connect normal_entries_barrier_3.io.x.sr, _normal_entries_WIRE_6.sr connect normal_entries_barrier_3.io.x.sx, _normal_entries_WIRE_6.sx connect normal_entries_barrier_3.io.x.sw, _normal_entries_WIRE_6.sw connect normal_entries_barrier_3.io.x.ae, _normal_entries_WIRE_6.ae connect normal_entries_barrier_3.io.x.g, _normal_entries_WIRE_6.g connect normal_entries_barrier_3.io.x.u, _normal_entries_WIRE_6.u connect normal_entries_barrier_3.io.x.ppn, _normal_entries_WIRE_6.ppn wire _normal_entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_9 : UInt<34> connect _normal_entries_WIRE_9, superpage_entries[2].data[0] node _normal_entries_T_62 = bits(_normal_entries_WIRE_9, 0, 0) connect _normal_entries_WIRE_8.fragmented_superpage, _normal_entries_T_62 node _normal_entries_T_63 = bits(_normal_entries_WIRE_9, 1, 1) connect _normal_entries_WIRE_8.c, _normal_entries_T_63 node _normal_entries_T_64 = bits(_normal_entries_WIRE_9, 2, 2) connect _normal_entries_WIRE_8.eff, _normal_entries_T_64 node _normal_entries_T_65 = bits(_normal_entries_WIRE_9, 3, 3) connect _normal_entries_WIRE_8.paa, _normal_entries_T_65 node _normal_entries_T_66 = bits(_normal_entries_WIRE_9, 4, 4) connect _normal_entries_WIRE_8.pal, _normal_entries_T_66 node _normal_entries_T_67 = bits(_normal_entries_WIRE_9, 5, 5) connect _normal_entries_WIRE_8.pr, _normal_entries_T_67 node _normal_entries_T_68 = bits(_normal_entries_WIRE_9, 6, 6) connect _normal_entries_WIRE_8.px, _normal_entries_T_68 node _normal_entries_T_69 = bits(_normal_entries_WIRE_9, 7, 7) connect _normal_entries_WIRE_8.pw, _normal_entries_T_69 node _normal_entries_T_70 = bits(_normal_entries_WIRE_9, 8, 8) connect _normal_entries_WIRE_8.sr, _normal_entries_T_70 node _normal_entries_T_71 = bits(_normal_entries_WIRE_9, 9, 9) connect _normal_entries_WIRE_8.sx, _normal_entries_T_71 node _normal_entries_T_72 = bits(_normal_entries_WIRE_9, 10, 10) connect _normal_entries_WIRE_8.sw, _normal_entries_T_72 node _normal_entries_T_73 = bits(_normal_entries_WIRE_9, 11, 11) connect _normal_entries_WIRE_8.ae, _normal_entries_T_73 node _normal_entries_T_74 = bits(_normal_entries_WIRE_9, 12, 12) connect _normal_entries_WIRE_8.g, _normal_entries_T_74 node _normal_entries_T_75 = bits(_normal_entries_WIRE_9, 13, 13) connect _normal_entries_WIRE_8.u, _normal_entries_T_75 node _normal_entries_T_76 = bits(_normal_entries_WIRE_9, 33, 14) connect _normal_entries_WIRE_8.ppn, _normal_entries_T_76 inst normal_entries_barrier_4 of OptimizationBarrier_EntryData_19 connect normal_entries_barrier_4.clock, clock connect normal_entries_barrier_4.reset, reset connect normal_entries_barrier_4.io.x.fragmented_superpage, _normal_entries_WIRE_8.fragmented_superpage connect normal_entries_barrier_4.io.x.c, _normal_entries_WIRE_8.c connect normal_entries_barrier_4.io.x.eff, _normal_entries_WIRE_8.eff connect normal_entries_barrier_4.io.x.paa, _normal_entries_WIRE_8.paa connect normal_entries_barrier_4.io.x.pal, _normal_entries_WIRE_8.pal connect normal_entries_barrier_4.io.x.pr, _normal_entries_WIRE_8.pr connect normal_entries_barrier_4.io.x.px, _normal_entries_WIRE_8.px connect normal_entries_barrier_4.io.x.pw, _normal_entries_WIRE_8.pw connect normal_entries_barrier_4.io.x.sr, _normal_entries_WIRE_8.sr connect normal_entries_barrier_4.io.x.sx, _normal_entries_WIRE_8.sx connect normal_entries_barrier_4.io.x.sw, _normal_entries_WIRE_8.sw connect normal_entries_barrier_4.io.x.ae, _normal_entries_WIRE_8.ae connect normal_entries_barrier_4.io.x.g, _normal_entries_WIRE_8.g connect normal_entries_barrier_4.io.x.u, _normal_entries_WIRE_8.u connect normal_entries_barrier_4.io.x.ppn, _normal_entries_WIRE_8.ppn wire _normal_entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_11 : UInt<34> connect _normal_entries_WIRE_11, superpage_entries[3].data[0] node _normal_entries_T_77 = bits(_normal_entries_WIRE_11, 0, 0) connect _normal_entries_WIRE_10.fragmented_superpage, _normal_entries_T_77 node _normal_entries_T_78 = bits(_normal_entries_WIRE_11, 1, 1) connect _normal_entries_WIRE_10.c, _normal_entries_T_78 node _normal_entries_T_79 = bits(_normal_entries_WIRE_11, 2, 2) connect _normal_entries_WIRE_10.eff, _normal_entries_T_79 node _normal_entries_T_80 = bits(_normal_entries_WIRE_11, 3, 3) connect _normal_entries_WIRE_10.paa, _normal_entries_T_80 node _normal_entries_T_81 = bits(_normal_entries_WIRE_11, 4, 4) connect _normal_entries_WIRE_10.pal, _normal_entries_T_81 node _normal_entries_T_82 = bits(_normal_entries_WIRE_11, 5, 5) connect _normal_entries_WIRE_10.pr, _normal_entries_T_82 node _normal_entries_T_83 = bits(_normal_entries_WIRE_11, 6, 6) connect _normal_entries_WIRE_10.px, _normal_entries_T_83 node _normal_entries_T_84 = bits(_normal_entries_WIRE_11, 7, 7) connect _normal_entries_WIRE_10.pw, _normal_entries_T_84 node _normal_entries_T_85 = bits(_normal_entries_WIRE_11, 8, 8) connect _normal_entries_WIRE_10.sr, _normal_entries_T_85 node _normal_entries_T_86 = bits(_normal_entries_WIRE_11, 9, 9) connect _normal_entries_WIRE_10.sx, _normal_entries_T_86 node _normal_entries_T_87 = bits(_normal_entries_WIRE_11, 10, 10) connect _normal_entries_WIRE_10.sw, _normal_entries_T_87 node _normal_entries_T_88 = bits(_normal_entries_WIRE_11, 11, 11) connect _normal_entries_WIRE_10.ae, _normal_entries_T_88 node _normal_entries_T_89 = bits(_normal_entries_WIRE_11, 12, 12) connect _normal_entries_WIRE_10.g, _normal_entries_T_89 node _normal_entries_T_90 = bits(_normal_entries_WIRE_11, 13, 13) connect _normal_entries_WIRE_10.u, _normal_entries_T_90 node _normal_entries_T_91 = bits(_normal_entries_WIRE_11, 33, 14) connect _normal_entries_WIRE_10.ppn, _normal_entries_T_91 inst normal_entries_barrier_5 of OptimizationBarrier_EntryData_20 connect normal_entries_barrier_5.clock, clock connect normal_entries_barrier_5.reset, reset connect normal_entries_barrier_5.io.x.fragmented_superpage, _normal_entries_WIRE_10.fragmented_superpage connect normal_entries_barrier_5.io.x.c, _normal_entries_WIRE_10.c connect normal_entries_barrier_5.io.x.eff, _normal_entries_WIRE_10.eff connect normal_entries_barrier_5.io.x.paa, _normal_entries_WIRE_10.paa connect normal_entries_barrier_5.io.x.pal, _normal_entries_WIRE_10.pal connect normal_entries_barrier_5.io.x.pr, _normal_entries_WIRE_10.pr connect normal_entries_barrier_5.io.x.px, _normal_entries_WIRE_10.px connect normal_entries_barrier_5.io.x.pw, _normal_entries_WIRE_10.pw connect normal_entries_barrier_5.io.x.sr, _normal_entries_WIRE_10.sr connect normal_entries_barrier_5.io.x.sx, _normal_entries_WIRE_10.sx connect normal_entries_barrier_5.io.x.sw, _normal_entries_WIRE_10.sw connect normal_entries_barrier_5.io.x.ae, _normal_entries_WIRE_10.ae connect normal_entries_barrier_5.io.x.g, _normal_entries_WIRE_10.g connect normal_entries_barrier_5.io.x.u, _normal_entries_WIRE_10.u connect normal_entries_barrier_5.io.x.ppn, _normal_entries_WIRE_10.ppn wire _normal_entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[6] connect _normal_entries_WIRE_12[0], normal_entries_barrier.io.y connect _normal_entries_WIRE_12[1], normal_entries_barrier_1.io.y connect _normal_entries_WIRE_12[2], normal_entries_barrier_2.io.y connect _normal_entries_WIRE_12[3], normal_entries_barrier_3.io.y connect _normal_entries_WIRE_12[4], normal_entries_barrier_4.io.y connect _normal_entries_WIRE_12[5], normal_entries_barrier_5.io.y wire normal_entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[6][1] connect normal_entries[0], _normal_entries_WIRE_12 node ptw_ae_array_lo_hi = cat(entries[0][2].ae, entries[0][1].ae) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries[0][0].ae) node ptw_ae_array_hi_lo = cat(entries[0][4].ae, entries[0][3].ae) node ptw_ae_array_hi_hi = cat(entries[0][6].ae, entries[0][5].ae) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node _ptw_ae_array_T_1 = cat(UInt<1>(0h0), _ptw_ae_array_T) wire ptw_ae_array : UInt<8>[1] connect ptw_ae_array[0], _ptw_ae_array_T_1 node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, io.ptw.status.sum) node priv_rw_ok_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries[0][0].u) node priv_rw_ok_hi_lo = cat(entries[0][4].u, entries[0][3].u) node priv_rw_ok_hi_hi = cat(entries[0][6].u, entries[0][5].u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries[0][0].u) node priv_rw_ok_hi_lo_1 = cat(entries[0][4].u, entries[0][3].u) node priv_rw_ok_hi_hi_1 = cat(entries[0][6].u, entries[0][5].u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node _priv_rw_ok_T_7 = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) wire priv_rw_ok : UInt<7>[1] connect priv_rw_ok[0], _priv_rw_ok_T_7 node priv_x_ok_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries[0][0].u) node priv_x_ok_hi_lo = cat(entries[0][4].u, entries[0][3].u) node priv_x_ok_hi_hi = cat(entries[0][6].u, entries[0][5].u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries[0][0].u) node priv_x_ok_hi_lo_1 = cat(entries[0][4].u, entries[0][3].u) node priv_x_ok_hi_hi_1 = cat(entries[0][6].u, entries[0][5].u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node _priv_x_ok_T_3 = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) wire priv_x_ok : UInt<7>[1] connect priv_x_ok[0], _priv_x_ok_T_3 node r_array_lo_hi = cat(entries[0][2].sr, entries[0][1].sr) node r_array_lo = cat(r_array_lo_hi, entries[0][0].sr) node r_array_hi_lo = cat(entries[0][4].sr, entries[0][3].sr) node r_array_hi_hi = cat(entries[0][6].sr, entries[0][5].sr) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries[0][2].sx, entries[0][1].sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries[0][0].sx) node r_array_hi_lo_1 = cat(entries[0][4].sx, entries[0][3].sx) node r_array_hi_hi_1 = cat(entries[0][6].sx, entries[0][5].sx) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(io.ptw.status.mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok[0], _r_array_T_3) node _r_array_T_5 = cat(UInt<1>(0h1), _r_array_T_4) wire r_array : UInt<8>[1] connect r_array[0], _r_array_T_5 node w_array_lo_hi = cat(entries[0][2].sw, entries[0][1].sw) node w_array_lo = cat(w_array_lo_hi, entries[0][0].sw) node w_array_hi_lo = cat(entries[0][4].sw, entries[0][3].sw) node w_array_hi_hi = cat(entries[0][6].sw, entries[0][5].sw) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok[0], _w_array_T) node _w_array_T_2 = cat(UInt<1>(0h1), _w_array_T_1) wire w_array : UInt<8>[1] connect w_array[0], _w_array_T_2 node x_array_lo_hi = cat(entries[0][2].sx, entries[0][1].sx) node x_array_lo = cat(x_array_lo_hi, entries[0][0].sx) node x_array_hi_lo = cat(entries[0][4].sx, entries[0][3].sx) node x_array_hi_hi = cat(entries[0][6].sx, entries[0][5].sx) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok[0], _x_array_T) node _x_array_T_2 = cat(UInt<1>(0h1), _x_array_T_1) wire x_array : UInt<8>[1] connect x_array[0], _x_array_T_2 node _pr_array_T = mux(prot_r[0], UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_hi = cat(normal_entries[0][2].pr, normal_entries[0][1].pr) node pr_array_lo = cat(pr_array_lo_hi, normal_entries[0][0].pr) node pr_array_hi_hi = cat(normal_entries[0][5].pr, normal_entries[0][4].pr) node pr_array_hi = cat(pr_array_hi_hi, normal_entries[0][3].pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = not(ptw_ae_array[0]) node _pr_array_T_4 = and(_pr_array_T_2, _pr_array_T_3) wire pr_array : UInt<8>[1] connect pr_array[0], _pr_array_T_4 node _pw_array_T = mux(prot_w[0], UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_hi = cat(normal_entries[0][2].pw, normal_entries[0][1].pw) node pw_array_lo = cat(pw_array_lo_hi, normal_entries[0][0].pw) node pw_array_hi_hi = cat(normal_entries[0][5].pw, normal_entries[0][4].pw) node pw_array_hi = cat(pw_array_hi_hi, normal_entries[0][3].pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = not(ptw_ae_array[0]) node _pw_array_T_4 = and(_pw_array_T_2, _pw_array_T_3) wire pw_array : UInt<8>[1] connect pw_array[0], _pw_array_T_4 node _px_array_T = mux(prot_x[0], UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_hi = cat(normal_entries[0][2].px, normal_entries[0][1].px) node px_array_lo = cat(px_array_lo_hi, normal_entries[0][0].px) node px_array_hi_hi = cat(normal_entries[0][5].px, normal_entries[0][4].px) node px_array_hi = cat(px_array_hi_hi, normal_entries[0][3].px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = not(ptw_ae_array[0]) node _px_array_T_4 = and(_px_array_T_2, _px_array_T_3) wire px_array : UInt<8>[1] connect px_array[0], _px_array_T_4 node _eff_array_T = mux(prot_eff[0], UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_hi = cat(normal_entries[0][2].eff, normal_entries[0][1].eff) node eff_array_lo = cat(eff_array_lo_hi, normal_entries[0][0].eff) node eff_array_hi_hi = cat(normal_entries[0][5].eff, normal_entries[0][4].eff) node eff_array_hi = cat(eff_array_hi_hi, normal_entries[0][3].eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node _eff_array_T_2 = cat(_eff_array_T, _eff_array_T_1) wire eff_array : UInt<8>[1] connect eff_array[0], _eff_array_T_2 node _c_array_T = mux(cacheable[0], UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node c_array_lo = cat(c_array_lo_hi, normal_entries[0][0].c) node c_array_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node c_array_hi = cat(c_array_hi_hi, normal_entries[0][3].c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node _c_array_T_2 = cat(_c_array_T, _c_array_T_1) wire c_array : UInt<8>[1] connect c_array[0], _c_array_T_2 node _paa_array_T = mux(prot_aa[0], UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_hi = cat(normal_entries[0][2].paa, normal_entries[0][1].paa) node paa_array_lo = cat(paa_array_lo_hi, normal_entries[0][0].paa) node paa_array_hi_hi = cat(normal_entries[0][5].paa, normal_entries[0][4].paa) node paa_array_hi = cat(paa_array_hi_hi, normal_entries[0][3].paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node _paa_array_T_2 = cat(_paa_array_T, _paa_array_T_1) wire paa_array : UInt<8>[1] connect paa_array[0], _paa_array_T_2 node _pal_array_T = mux(prot_al[0], UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_hi = cat(normal_entries[0][2].pal, normal_entries[0][1].pal) node pal_array_lo = cat(pal_array_lo_hi, normal_entries[0][0].pal) node pal_array_hi_hi = cat(normal_entries[0][5].pal, normal_entries[0][4].pal) node pal_array_hi = cat(pal_array_hi_hi, normal_entries[0][3].pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node _pal_array_T_2 = cat(_pal_array_T, _pal_array_T_1) wire pal_array : UInt<8>[1] connect pal_array[0], _pal_array_T_2 node _paa_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _paa_array_if_cached_T_1 = or(paa_array[0], _paa_array_if_cached_T) wire paa_array_if_cached : UInt<8>[1] connect paa_array_if_cached[0], _paa_array_if_cached_T_1 node _pal_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _pal_array_if_cached_T_1 = or(pal_array[0], _pal_array_if_cached_T) wire pal_array_if_cached : UInt<8>[1] connect pal_array_if_cached[0], _pal_array_if_cached_T_1 node _prefetchable_array_T = and(cacheable[0], homogeneous[0]) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, normal_entries[0][0].c) node prefetchable_array_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, normal_entries[0][3].c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node _prefetchable_array_T_3 = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) wire prefetchable_array : UInt<8>[1] connect prefetchable_array[0], _prefetchable_array_T_3 node _misaligned_T = dshl(UInt<1>(0h1), io.req[0].bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req[0].bits.vaddr, _misaligned_T_2) node _misaligned_T_4 = orr(_misaligned_T_3) wire misaligned : UInt<1>[1] connect misaligned[0], _misaligned_T_4 node bad_va_maskedVAddr = and(io.req[0].bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_1 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_3 = or(_bad_va_T_1, _bad_va_T_2) node _bad_va_T_4 = eq(_bad_va_T_3, UInt<1>(0h0)) node _bad_va_T_5 = and(_bad_va_T, _bad_va_T_4) node _bad_va_T_6 = and(vm_enabled[0], _bad_va_T_5) wire bad_va : UInt<1>[1] connect bad_va[0], _bad_va_T_6 node _cmd_lrsc_T = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node _cmd_lrsc_T_3 = and(UInt<1>(0h1), _cmd_lrsc_T_2) wire cmd_lrsc : UInt<1>[1] connect cmd_lrsc[0], _cmd_lrsc_T_3 node _cmd_amo_logical_T = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node _cmd_amo_logical_T_7 = and(UInt<1>(0h1), _cmd_amo_logical_T_6) wire cmd_amo_logical : UInt<1>[1] connect cmd_amo_logical[0], _cmd_amo_logical_T_7 node _cmd_amo_arithmetic_T = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node _cmd_amo_arithmetic_T_9 = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) wire cmd_amo_arithmetic : UInt<1>[1] connect cmd_amo_arithmetic[0], _cmd_amo_arithmetic_T_9 node _cmd_read_T = eq(io.req[0].bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node _cmd_read_T_24 = or(_cmd_read_T_6, _cmd_read_T_23) wire cmd_read : UInt<1>[1] connect cmd_read[0], _cmd_read_T_24 node _cmd_write_T = eq(io.req[0].bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node _cmd_write_T_22 = or(_cmd_write_T_4, _cmd_write_T_21) wire cmd_write : UInt<1>[1] connect cmd_write[0], _cmd_write_T_22 node _cmd_write_perms_T = eq(io.req[0].bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = and(UInt<1>(0h0), _cmd_write_perms_T) node _cmd_write_perms_T_2 = or(cmd_write[0], _cmd_write_perms_T_1) wire cmd_write_perms : UInt<1>[1] connect cmd_write_perms[0], _cmd_write_perms_T_2 node _lrscAllowed_T = mux(UInt<1>(0h0), UInt<1>(0h0), c_array[0]) wire lrscAllowed : UInt<8>[1] connect lrscAllowed[0], _lrscAllowed_T node _ae_array_T = mux(misaligned[0], eff_array[0], UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed[0]) node _ae_array_T_2 = mux(cmd_lrsc[0], _ae_array_T_1, UInt<1>(0h0)) node _ae_array_T_3 = or(_ae_array_T, _ae_array_T_2) wire ae_array : UInt<8>[1] connect ae_array[0], _ae_array_T_3 node _ae_valid_array_T = eq(do_refill, UInt<1>(0h0)) node _ae_valid_array_T_1 = cat(UInt<1>(0h1), _ae_valid_array_T) node _ae_valid_array_T_2 = mux(UInt<1>(0h1), UInt<6>(0h3f), UInt<6>(0h0)) node _ae_valid_array_T_3 = cat(_ae_valid_array_T_1, _ae_valid_array_T_2) wire ae_valid_array : UInt<8>[1] connect ae_valid_array[0], _ae_valid_array_T_3 node _ae_ld_array_T = not(pr_array[0]) node _ae_ld_array_T_1 = or(ae_array[0], _ae_ld_array_T) node _ae_ld_array_T_2 = mux(cmd_read[0], _ae_ld_array_T_1, UInt<1>(0h0)) wire ae_ld_array : UInt<8>[1] connect ae_ld_array[0], _ae_ld_array_T_2 node _ae_st_array_T = not(pw_array[0]) node _ae_st_array_T_1 = or(ae_array[0], _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms[0], _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(pal_array_if_cached[0]) node _ae_st_array_T_4 = mux(cmd_amo_logical[0], _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(paa_array_if_cached[0]) node _ae_st_array_T_7 = mux(cmd_amo_arithmetic[0], _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) wire ae_st_array : UInt<8>[1] connect ae_st_array[0], _ae_st_array_T_8 node _must_alloc_array_T = not(paa_array[0]) node _must_alloc_array_T_1 = mux(cmd_amo_logical[0], _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array[0]) node _must_alloc_array_T_3 = mux(cmd_amo_arithmetic[0], _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(UInt<8>(0h0)) node _must_alloc_array_T_6 = mux(cmd_lrsc[0], _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) wire must_alloc_array : UInt<8>[1] connect must_alloc_array[0], _must_alloc_array_T_7 node _ma_ld_array_T = and(misaligned[0], cmd_read[0]) node _ma_ld_array_T_1 = not(eff_array[0]) node _ma_ld_array_T_2 = mux(_ma_ld_array_T, _ma_ld_array_T_1, UInt<1>(0h0)) wire ma_ld_array : UInt<8>[1] connect ma_ld_array[0], _ma_ld_array_T_2 node _ma_st_array_T = and(misaligned[0], cmd_write[0]) node _ma_st_array_T_1 = not(eff_array[0]) node _ma_st_array_T_2 = mux(_ma_st_array_T, _ma_st_array_T_1, UInt<1>(0h0)) wire ma_st_array : UInt<8>[1] connect ma_st_array[0], _ma_st_array_T_2 node _pf_ld_array_T = or(r_array[0], ptw_ae_array[0]) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = mux(cmd_read[0], _pf_ld_array_T_1, UInt<1>(0h0)) wire pf_ld_array : UInt<8>[1] connect pf_ld_array[0], _pf_ld_array_T_2 node _pf_st_array_T = or(w_array[0], ptw_ae_array[0]) node _pf_st_array_T_1 = not(_pf_st_array_T) node _pf_st_array_T_2 = mux(cmd_write_perms[0], _pf_st_array_T_1, UInt<1>(0h0)) wire pf_st_array : UInt<8>[1] connect pf_st_array[0], _pf_st_array_T_2 node _pf_inst_array_T = or(x_array[0], ptw_ae_array[0]) node _pf_inst_array_T_1 = not(_pf_inst_array_T) wire pf_inst_array : UInt<8>[1] connect pf_inst_array[0], _pf_inst_array_T_1 node _tlb_hit_T = orr(real_hits[0]) wire tlb_hit : UInt<1>[1] connect tlb_hit[0], _tlb_hit_T node _tlb_miss_T = eq(bad_va[0], UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled[0], _tlb_miss_T) node _tlb_miss_T_2 = eq(tlb_hit[0], UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) wire tlb_miss : UInt<1>[1] connect tlb_miss[0], _tlb_miss_T_3 regreset state_reg : UInt<1>, clock, reset, UInt<1>(0h0) regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_11 = and(io.req[0].valid, vm_enabled[0]) when _T_11 : node _T_12 = or(sector_hits[0][0], sector_hits[0][1]) when _T_12 : node _T_13 = cat(sector_hits[0][1], sector_hits[0][0]) node _T_14 = bits(_T_13, 1, 1) node state_reg_touch_way_sized = bits(_T_14, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = eq(_state_reg_T, UInt<1>(0h0)) connect state_reg, _state_reg_T_1 node _T_15 = or(superpage_hits[0][0], superpage_hits[0][1]) node _T_16 = or(_T_15, superpage_hits[0][2]) node _T_17 = or(_T_16, superpage_hits[0][3]) when _T_17 : node lo = cat(superpage_hits[0][1], superpage_hits[0][0]) node hi = cat(superpage_hits[0][3], superpage_hits[0][2]) node _T_18 = cat(hi, lo) node hi_1 = bits(_T_18, 3, 2) node lo_1 = bits(_T_18, 1, 0) node _T_19 = orr(hi_1) node _T_20 = or(hi_1, lo_1) node _T_21 = bits(_T_20, 1, 1) node _T_22 = cat(_T_19, _T_21) node state_reg_touch_way_sized_1 = bits(_T_22, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized_1, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T_2 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_3 = bits(_state_reg_T_2, 0, 0) node _state_reg_T_4 = eq(_state_reg_T_3, UInt<1>(0h0)) node _state_reg_T_5 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_4) node _state_reg_T_6 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_7 = bits(_state_reg_T_6, 0, 0) node _state_reg_T_8 = eq(_state_reg_T_7, UInt<1>(0h0)) node _state_reg_T_9 = mux(state_reg_set_left_older, _state_reg_T_8, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_5) node _state_reg_T_10 = cat(state_reg_hi, _state_reg_T_9) connect state_reg_1, _state_reg_T_10 node _multipleHits_T = bits(real_hits[0], 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits[0], 6, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 1, 0) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_2) node _multipleHits_T_13 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_14 = and(multipleHits_leftOne_3, multipleHits_rightOne_2) node multipleHits_leftTwo_1 = or(_multipleHits_T_13, _multipleHits_T_14) node _multipleHits_T_15 = bits(_multipleHits_T_9, 3, 2) node _multipleHits_T_16 = bits(_multipleHits_T_15, 0, 0) node multipleHits_leftOne_5 = bits(_multipleHits_T_16, 0, 0) node _multipleHits_T_17 = bits(_multipleHits_T_15, 1, 1) node multipleHits_rightOne_3 = bits(_multipleHits_T_17, 0, 0) node multipleHits_rightOne_4 = or(multipleHits_leftOne_5, multipleHits_rightOne_3) node _multipleHits_T_18 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_19 = and(multipleHits_leftOne_5, multipleHits_rightOne_3) node multipleHits_rightTwo_1 = or(_multipleHits_T_18, _multipleHits_T_19) node multipleHits_rightOne_5 = or(multipleHits_leftOne_4, multipleHits_rightOne_4) node _multipleHits_T_20 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_1) node _multipleHits_T_21 = and(multipleHits_leftOne_4, multipleHits_rightOne_4) node multipleHits_rightTwo_2 = or(_multipleHits_T_20, _multipleHits_T_21) node _multipleHits_T_22 = or(multipleHits_leftOne_2, multipleHits_rightOne_5) node _multipleHits_T_23 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_24 = and(multipleHits_leftOne_2, multipleHits_rightOne_5) node _multipleHits_T_25 = or(_multipleHits_T_23, _multipleHits_T_24) wire multipleHits : UInt<1>[1] connect multipleHits[0], _multipleHits_T_25 node _io_miss_rdy_T = eq(state, UInt<2>(0h0)) connect io.miss_rdy, _io_miss_rdy_T connect io.req[0].ready, UInt<1>(0h1) invalidate io.resp[0].gpa invalidate io.resp[0].gpa_is_pte connect io.resp[0].gf.ld, UInt<1>(0h0) connect io.resp[0].gf.st, UInt<1>(0h0) connect io.resp[0].gf.inst, UInt<1>(0h0) node _io_resp_0_pf_ld_T = and(bad_va[0], cmd_read[0]) node _io_resp_0_pf_ld_T_1 = and(pf_ld_array[0], hits[0]) node _io_resp_0_pf_ld_T_2 = orr(_io_resp_0_pf_ld_T_1) node _io_resp_0_pf_ld_T_3 = or(_io_resp_0_pf_ld_T, _io_resp_0_pf_ld_T_2) connect io.resp[0].pf.ld, _io_resp_0_pf_ld_T_3 node _io_resp_0_pf_st_T = and(bad_va[0], cmd_write_perms[0]) node _io_resp_0_pf_st_T_1 = and(pf_st_array[0], hits[0]) node _io_resp_0_pf_st_T_2 = orr(_io_resp_0_pf_st_T_1) node _io_resp_0_pf_st_T_3 = or(_io_resp_0_pf_st_T, _io_resp_0_pf_st_T_2) connect io.resp[0].pf.st, _io_resp_0_pf_st_T_3 node _io_resp_0_pf_inst_T = and(pf_inst_array[0], hits[0]) node _io_resp_0_pf_inst_T_1 = orr(_io_resp_0_pf_inst_T) node _io_resp_0_pf_inst_T_2 = or(bad_va[0], _io_resp_0_pf_inst_T_1) connect io.resp[0].pf.inst, _io_resp_0_pf_inst_T_2 node _io_resp_0_ae_ld_T = and(ae_valid_array[0], ae_ld_array[0]) node _io_resp_0_ae_ld_T_1 = and(_io_resp_0_ae_ld_T, hits[0]) node _io_resp_0_ae_ld_T_2 = orr(_io_resp_0_ae_ld_T_1) connect io.resp[0].ae.ld, _io_resp_0_ae_ld_T_2 node _io_resp_0_ae_st_T = and(ae_valid_array[0], ae_st_array[0]) node _io_resp_0_ae_st_T_1 = and(_io_resp_0_ae_st_T, hits[0]) node _io_resp_0_ae_st_T_2 = orr(_io_resp_0_ae_st_T_1) connect io.resp[0].ae.st, _io_resp_0_ae_st_T_2 node _io_resp_0_ae_inst_T = not(px_array[0]) node _io_resp_0_ae_inst_T_1 = and(ae_valid_array[0], _io_resp_0_ae_inst_T) node _io_resp_0_ae_inst_T_2 = and(_io_resp_0_ae_inst_T_1, hits[0]) node _io_resp_0_ae_inst_T_3 = orr(_io_resp_0_ae_inst_T_2) connect io.resp[0].ae.inst, _io_resp_0_ae_inst_T_3 node _io_resp_0_ma_ld_T = and(ma_ld_array[0], hits[0]) node _io_resp_0_ma_ld_T_1 = orr(_io_resp_0_ma_ld_T) connect io.resp[0].ma.ld, _io_resp_0_ma_ld_T_1 node _io_resp_0_ma_st_T = and(ma_st_array[0], hits[0]) node _io_resp_0_ma_st_T_1 = orr(_io_resp_0_ma_st_T) connect io.resp[0].ma.st, _io_resp_0_ma_st_T_1 connect io.resp[0].ma.inst, UInt<1>(0h0) node _io_resp_0_cacheable_T = and(c_array[0], hits[0]) node _io_resp_0_cacheable_T_1 = orr(_io_resp_0_cacheable_T) connect io.resp[0].cacheable, _io_resp_0_cacheable_T_1 node _io_resp_0_must_alloc_T = and(must_alloc_array[0], hits[0]) node _io_resp_0_must_alloc_T_1 = orr(_io_resp_0_must_alloc_T) connect io.resp[0].must_alloc, _io_resp_0_must_alloc_T_1 node _io_resp_0_prefetchable_T = and(prefetchable_array[0], hits[0]) node _io_resp_0_prefetchable_T_1 = orr(_io_resp_0_prefetchable_T) node _io_resp_0_prefetchable_T_2 = and(_io_resp_0_prefetchable_T_1, UInt<1>(0h1)) connect io.resp[0].prefetchable, _io_resp_0_prefetchable_T_2 node _io_resp_0_miss_T = or(do_refill, tlb_miss[0]) node _io_resp_0_miss_T_1 = or(_io_resp_0_miss_T, multipleHits[0]) connect io.resp[0].miss, _io_resp_0_miss_T_1 node _io_resp_0_paddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _io_resp_0_paddr_T_1 = cat(ppn[0], _io_resp_0_paddr_T) connect io.resp[0].paddr, _io_resp_0_paddr_T_1 connect io.resp[0].size, io.req[0].bits.size connect io.resp[0].cmd, io.req[0].bits.cmd invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T invalidate io.ptw.req.bits.bits.stage2 invalidate io.ptw.req.bits.bits.vstage1 invalidate io.ptw.req.bits.bits.need_gpa invalidate io.ptw.req.bits.bits.addr invalidate io.ptw.req.bits.valid node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag node _T_23 = and(io.req[0].ready, io.req[0].valid) node _T_24 = and(_T_23, tlb_miss[0]) node _T_25 = eq(state, UInt<2>(0h0)) node _T_26 = and(_T_24, _T_25) when _T_26 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn[0] node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node _r_sectored_repl_addr_T = bits(state_reg, 0, 0) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0].valid[0], sectored_entries[0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[1].valid[0], sectored_entries[1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[1].valid[3]) node r_sectored_repl_addr_valids = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node _r_sectored_repl_addr_T_1 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_2 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_3 = bits(_r_sectored_repl_addr_T_2, 0, 0) node _r_sectored_repl_addr_T_4 = bits(_r_sectored_repl_addr_T_2, 1, 1) node _r_sectored_repl_addr_T_5 = mux(_r_sectored_repl_addr_T_3, UInt<1>(0h0), UInt<1>(0h1)) node _r_sectored_repl_addr_T_6 = mux(_r_sectored_repl_addr_T_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_5) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_6 node _r_sectored_hit_addr_T = cat(sector_hits[0][1], sector_hits[0][0]) node _r_sectored_hit_addr_T_1 = bits(_r_sectored_hit_addr_T, 1, 1) connect r_sectored_hit_addr, _r_sectored_hit_addr_T_1 node _r_sectored_hit_T = or(sector_hits[0][0], sector_hits[0][1]) connect r_sectored_hit, _r_sectored_hit_T node _T_27 = eq(state, UInt<2>(0h1)) when _T_27 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_28 = eq(state, UInt<2>(0h2)) node _T_29 = and(_T_28, io.sfence.valid) when _T_29 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_30 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_31 = shr(io.sfence.bits.addr, 12) node _T_32 = eq(_T_31, vpn[0]) node _T_33 = or(_T_30, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at tlb.scala:349 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn(w))\n") : printf assert(clock, _T_33, UInt<1>(0h1), "") : assert when io.sfence.bits.rs1 : node _T_37 = xor(sectored_entries[0].tag, vpn[0]) node _T_38 = shr(_T_37, 2) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = bits(vpn[0], 1, 0) connect sectored_entries[0].valid[_T_40], UInt<1>(0h0) node _T_41 = xor(sectored_entries[0].tag, vpn[0]) node _T_42 = shr(_T_41, 18) node _T_43 = eq(_T_42, UInt<1>(0h0)) when _T_43 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<34> connect _WIRE_1, sectored_entries[0].data[0] node _T_44 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_44 node _T_45 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_45 node _T_46 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_46 node _T_47 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_47 node _T_48 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_48 node _T_49 = bits(_WIRE_1, 5, 5) connect _WIRE.pr, _T_49 node _T_50 = bits(_WIRE_1, 6, 6) connect _WIRE.px, _T_50 node _T_51 = bits(_WIRE_1, 7, 7) connect _WIRE.pw, _T_51 node _T_52 = bits(_WIRE_1, 8, 8) connect _WIRE.sr, _T_52 node _T_53 = bits(_WIRE_1, 9, 9) connect _WIRE.sx, _T_53 node _T_54 = bits(_WIRE_1, 10, 10) connect _WIRE.sw, _T_54 node _T_55 = bits(_WIRE_1, 11, 11) connect _WIRE.ae, _T_55 node _T_56 = bits(_WIRE_1, 12, 12) connect _WIRE.g, _T_56 node _T_57 = bits(_WIRE_1, 13, 13) connect _WIRE.u, _T_57 node _T_58 = bits(_WIRE_1, 33, 14) connect _WIRE.ppn, _T_58 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<34> connect _WIRE_3, sectored_entries[0].data[1] node _T_59 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_59 node _T_60 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_60 node _T_61 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_61 node _T_62 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_62 node _T_63 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_63 node _T_64 = bits(_WIRE_3, 5, 5) connect _WIRE_2.pr, _T_64 node _T_65 = bits(_WIRE_3, 6, 6) connect _WIRE_2.px, _T_65 node _T_66 = bits(_WIRE_3, 7, 7) connect _WIRE_2.pw, _T_66 node _T_67 = bits(_WIRE_3, 8, 8) connect _WIRE_2.sr, _T_67 node _T_68 = bits(_WIRE_3, 9, 9) connect _WIRE_2.sx, _T_68 node _T_69 = bits(_WIRE_3, 10, 10) connect _WIRE_2.sw, _T_69 node _T_70 = bits(_WIRE_3, 11, 11) connect _WIRE_2.ae, _T_70 node _T_71 = bits(_WIRE_3, 12, 12) connect _WIRE_2.g, _T_71 node _T_72 = bits(_WIRE_3, 13, 13) connect _WIRE_2.u, _T_72 node _T_73 = bits(_WIRE_3, 33, 14) connect _WIRE_2.ppn, _T_73 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<34> connect _WIRE_5, sectored_entries[0].data[2] node _T_74 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_74 node _T_75 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_75 node _T_76 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_76 node _T_77 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_77 node _T_78 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_78 node _T_79 = bits(_WIRE_5, 5, 5) connect _WIRE_4.pr, _T_79 node _T_80 = bits(_WIRE_5, 6, 6) connect _WIRE_4.px, _T_80 node _T_81 = bits(_WIRE_5, 7, 7) connect _WIRE_4.pw, _T_81 node _T_82 = bits(_WIRE_5, 8, 8) connect _WIRE_4.sr, _T_82 node _T_83 = bits(_WIRE_5, 9, 9) connect _WIRE_4.sx, _T_83 node _T_84 = bits(_WIRE_5, 10, 10) connect _WIRE_4.sw, _T_84 node _T_85 = bits(_WIRE_5, 11, 11) connect _WIRE_4.ae, _T_85 node _T_86 = bits(_WIRE_5, 12, 12) connect _WIRE_4.g, _T_86 node _T_87 = bits(_WIRE_5, 13, 13) connect _WIRE_4.u, _T_87 node _T_88 = bits(_WIRE_5, 33, 14) connect _WIRE_4.ppn, _T_88 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<34> connect _WIRE_7, sectored_entries[0].data[3] node _T_89 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_89 node _T_90 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_90 node _T_91 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_91 node _T_92 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_92 node _T_93 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_93 node _T_94 = bits(_WIRE_7, 5, 5) connect _WIRE_6.pr, _T_94 node _T_95 = bits(_WIRE_7, 6, 6) connect _WIRE_6.px, _T_95 node _T_96 = bits(_WIRE_7, 7, 7) connect _WIRE_6.pw, _T_96 node _T_97 = bits(_WIRE_7, 8, 8) connect _WIRE_6.sr, _T_97 node _T_98 = bits(_WIRE_7, 9, 9) connect _WIRE_6.sx, _T_98 node _T_99 = bits(_WIRE_7, 10, 10) connect _WIRE_6.sw, _T_99 node _T_100 = bits(_WIRE_7, 11, 11) connect _WIRE_6.ae, _T_100 node _T_101 = bits(_WIRE_7, 12, 12) connect _WIRE_6.g, _T_101 node _T_102 = bits(_WIRE_7, 13, 13) connect _WIRE_6.u, _T_102 node _T_103 = bits(_WIRE_7, 33, 14) connect _WIRE_6.ppn, _T_103 when _WIRE.fragmented_superpage : connect sectored_entries[0].valid[0], UInt<1>(0h0) when _WIRE_2.fragmented_superpage : connect sectored_entries[0].valid[1], UInt<1>(0h0) when _WIRE_4.fragmented_superpage : connect sectored_entries[0].valid[2], UInt<1>(0h0) when _WIRE_6.fragmented_superpage : connect sectored_entries[0].valid[3], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<34> connect _WIRE_9, sectored_entries[0].data[0] node _T_104 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_104 node _T_105 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_105 node _T_106 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_106 node _T_107 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_107 node _T_108 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_108 node _T_109 = bits(_WIRE_9, 5, 5) connect _WIRE_8.pr, _T_109 node _T_110 = bits(_WIRE_9, 6, 6) connect _WIRE_8.px, _T_110 node _T_111 = bits(_WIRE_9, 7, 7) connect _WIRE_8.pw, _T_111 node _T_112 = bits(_WIRE_9, 8, 8) connect _WIRE_8.sr, _T_112 node _T_113 = bits(_WIRE_9, 9, 9) connect _WIRE_8.sx, _T_113 node _T_114 = bits(_WIRE_9, 10, 10) connect _WIRE_8.sw, _T_114 node _T_115 = bits(_WIRE_9, 11, 11) connect _WIRE_8.ae, _T_115 node _T_116 = bits(_WIRE_9, 12, 12) connect _WIRE_8.g, _T_116 node _T_117 = bits(_WIRE_9, 13, 13) connect _WIRE_8.u, _T_117 node _T_118 = bits(_WIRE_9, 33, 14) connect _WIRE_8.ppn, _T_118 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<34> connect _WIRE_11, sectored_entries[0].data[1] node _T_119 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_119 node _T_120 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_120 node _T_121 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_121 node _T_122 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_122 node _T_123 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_123 node _T_124 = bits(_WIRE_11, 5, 5) connect _WIRE_10.pr, _T_124 node _T_125 = bits(_WIRE_11, 6, 6) connect _WIRE_10.px, _T_125 node _T_126 = bits(_WIRE_11, 7, 7) connect _WIRE_10.pw, _T_126 node _T_127 = bits(_WIRE_11, 8, 8) connect _WIRE_10.sr, _T_127 node _T_128 = bits(_WIRE_11, 9, 9) connect _WIRE_10.sx, _T_128 node _T_129 = bits(_WIRE_11, 10, 10) connect _WIRE_10.sw, _T_129 node _T_130 = bits(_WIRE_11, 11, 11) connect _WIRE_10.ae, _T_130 node _T_131 = bits(_WIRE_11, 12, 12) connect _WIRE_10.g, _T_131 node _T_132 = bits(_WIRE_11, 13, 13) connect _WIRE_10.u, _T_132 node _T_133 = bits(_WIRE_11, 33, 14) connect _WIRE_10.ppn, _T_133 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<34> connect _WIRE_13, sectored_entries[0].data[2] node _T_134 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_134 node _T_135 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_135 node _T_136 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_136 node _T_137 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_137 node _T_138 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_138 node _T_139 = bits(_WIRE_13, 5, 5) connect _WIRE_12.pr, _T_139 node _T_140 = bits(_WIRE_13, 6, 6) connect _WIRE_12.px, _T_140 node _T_141 = bits(_WIRE_13, 7, 7) connect _WIRE_12.pw, _T_141 node _T_142 = bits(_WIRE_13, 8, 8) connect _WIRE_12.sr, _T_142 node _T_143 = bits(_WIRE_13, 9, 9) connect _WIRE_12.sx, _T_143 node _T_144 = bits(_WIRE_13, 10, 10) connect _WIRE_12.sw, _T_144 node _T_145 = bits(_WIRE_13, 11, 11) connect _WIRE_12.ae, _T_145 node _T_146 = bits(_WIRE_13, 12, 12) connect _WIRE_12.g, _T_146 node _T_147 = bits(_WIRE_13, 13, 13) connect _WIRE_12.u, _T_147 node _T_148 = bits(_WIRE_13, 33, 14) connect _WIRE_12.ppn, _T_148 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<34> connect _WIRE_15, sectored_entries[0].data[3] node _T_149 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_149 node _T_150 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_150 node _T_151 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_151 node _T_152 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_152 node _T_153 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_153 node _T_154 = bits(_WIRE_15, 5, 5) connect _WIRE_14.pr, _T_154 node _T_155 = bits(_WIRE_15, 6, 6) connect _WIRE_14.px, _T_155 node _T_156 = bits(_WIRE_15, 7, 7) connect _WIRE_14.pw, _T_156 node _T_157 = bits(_WIRE_15, 8, 8) connect _WIRE_14.sr, _T_157 node _T_158 = bits(_WIRE_15, 9, 9) connect _WIRE_14.sx, _T_158 node _T_159 = bits(_WIRE_15, 10, 10) connect _WIRE_14.sw, _T_159 node _T_160 = bits(_WIRE_15, 11, 11) connect _WIRE_14.ae, _T_160 node _T_161 = bits(_WIRE_15, 12, 12) connect _WIRE_14.g, _T_161 node _T_162 = bits(_WIRE_15, 13, 13) connect _WIRE_14.u, _T_162 node _T_163 = bits(_WIRE_15, 33, 14) connect _WIRE_14.ppn, _T_163 node _T_164 = eq(_WIRE_8.g, UInt<1>(0h0)) when _T_164 : connect sectored_entries[0].valid[0], UInt<1>(0h0) node _T_165 = eq(_WIRE_10.g, UInt<1>(0h0)) when _T_165 : connect sectored_entries[0].valid[1], UInt<1>(0h0) node _T_166 = eq(_WIRE_12.g, UInt<1>(0h0)) when _T_166 : connect sectored_entries[0].valid[2], UInt<1>(0h0) node _T_167 = eq(_WIRE_14.g, UInt<1>(0h0)) when _T_167 : connect sectored_entries[0].valid[3], UInt<1>(0h0) else : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) when io.sfence.bits.rs1 : node _T_168 = xor(sectored_entries[1].tag, vpn[0]) node _T_169 = shr(_T_168, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = bits(vpn[0], 1, 0) connect sectored_entries[1].valid[_T_171], UInt<1>(0h0) node _T_172 = xor(sectored_entries[1].tag, vpn[0]) node _T_173 = shr(_T_172, 18) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<34> connect _WIRE_17, sectored_entries[1].data[0] node _T_175 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_175 node _T_176 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_176 node _T_177 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_177 node _T_178 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_178 node _T_179 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_179 node _T_180 = bits(_WIRE_17, 5, 5) connect _WIRE_16.pr, _T_180 node _T_181 = bits(_WIRE_17, 6, 6) connect _WIRE_16.px, _T_181 node _T_182 = bits(_WIRE_17, 7, 7) connect _WIRE_16.pw, _T_182 node _T_183 = bits(_WIRE_17, 8, 8) connect _WIRE_16.sr, _T_183 node _T_184 = bits(_WIRE_17, 9, 9) connect _WIRE_16.sx, _T_184 node _T_185 = bits(_WIRE_17, 10, 10) connect _WIRE_16.sw, _T_185 node _T_186 = bits(_WIRE_17, 11, 11) connect _WIRE_16.ae, _T_186 node _T_187 = bits(_WIRE_17, 12, 12) connect _WIRE_16.g, _T_187 node _T_188 = bits(_WIRE_17, 13, 13) connect _WIRE_16.u, _T_188 node _T_189 = bits(_WIRE_17, 33, 14) connect _WIRE_16.ppn, _T_189 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<34> connect _WIRE_19, sectored_entries[1].data[1] node _T_190 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_190 node _T_191 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_191 node _T_192 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_192 node _T_193 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_193 node _T_194 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_194 node _T_195 = bits(_WIRE_19, 5, 5) connect _WIRE_18.pr, _T_195 node _T_196 = bits(_WIRE_19, 6, 6) connect _WIRE_18.px, _T_196 node _T_197 = bits(_WIRE_19, 7, 7) connect _WIRE_18.pw, _T_197 node _T_198 = bits(_WIRE_19, 8, 8) connect _WIRE_18.sr, _T_198 node _T_199 = bits(_WIRE_19, 9, 9) connect _WIRE_18.sx, _T_199 node _T_200 = bits(_WIRE_19, 10, 10) connect _WIRE_18.sw, _T_200 node _T_201 = bits(_WIRE_19, 11, 11) connect _WIRE_18.ae, _T_201 node _T_202 = bits(_WIRE_19, 12, 12) connect _WIRE_18.g, _T_202 node _T_203 = bits(_WIRE_19, 13, 13) connect _WIRE_18.u, _T_203 node _T_204 = bits(_WIRE_19, 33, 14) connect _WIRE_18.ppn, _T_204 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<34> connect _WIRE_21, sectored_entries[1].data[2] node _T_205 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_205 node _T_206 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_206 node _T_207 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_207 node _T_208 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_208 node _T_209 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_209 node _T_210 = bits(_WIRE_21, 5, 5) connect _WIRE_20.pr, _T_210 node _T_211 = bits(_WIRE_21, 6, 6) connect _WIRE_20.px, _T_211 node _T_212 = bits(_WIRE_21, 7, 7) connect _WIRE_20.pw, _T_212 node _T_213 = bits(_WIRE_21, 8, 8) connect _WIRE_20.sr, _T_213 node _T_214 = bits(_WIRE_21, 9, 9) connect _WIRE_20.sx, _T_214 node _T_215 = bits(_WIRE_21, 10, 10) connect _WIRE_20.sw, _T_215 node _T_216 = bits(_WIRE_21, 11, 11) connect _WIRE_20.ae, _T_216 node _T_217 = bits(_WIRE_21, 12, 12) connect _WIRE_20.g, _T_217 node _T_218 = bits(_WIRE_21, 13, 13) connect _WIRE_20.u, _T_218 node _T_219 = bits(_WIRE_21, 33, 14) connect _WIRE_20.ppn, _T_219 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<34> connect _WIRE_23, sectored_entries[1].data[3] node _T_220 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_220 node _T_221 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_221 node _T_222 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_222 node _T_223 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_223 node _T_224 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_224 node _T_225 = bits(_WIRE_23, 5, 5) connect _WIRE_22.pr, _T_225 node _T_226 = bits(_WIRE_23, 6, 6) connect _WIRE_22.px, _T_226 node _T_227 = bits(_WIRE_23, 7, 7) connect _WIRE_22.pw, _T_227 node _T_228 = bits(_WIRE_23, 8, 8) connect _WIRE_22.sr, _T_228 node _T_229 = bits(_WIRE_23, 9, 9) connect _WIRE_22.sx, _T_229 node _T_230 = bits(_WIRE_23, 10, 10) connect _WIRE_22.sw, _T_230 node _T_231 = bits(_WIRE_23, 11, 11) connect _WIRE_22.ae, _T_231 node _T_232 = bits(_WIRE_23, 12, 12) connect _WIRE_22.g, _T_232 node _T_233 = bits(_WIRE_23, 13, 13) connect _WIRE_22.u, _T_233 node _T_234 = bits(_WIRE_23, 33, 14) connect _WIRE_22.ppn, _T_234 when _WIRE_16.fragmented_superpage : connect sectored_entries[1].valid[0], UInt<1>(0h0) when _WIRE_18.fragmented_superpage : connect sectored_entries[1].valid[1], UInt<1>(0h0) when _WIRE_20.fragmented_superpage : connect sectored_entries[1].valid[2], UInt<1>(0h0) when _WIRE_22.fragmented_superpage : connect sectored_entries[1].valid[3], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<34> connect _WIRE_25, sectored_entries[1].data[0] node _T_235 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_235 node _T_236 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_236 node _T_237 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_237 node _T_238 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_238 node _T_239 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_239 node _T_240 = bits(_WIRE_25, 5, 5) connect _WIRE_24.pr, _T_240 node _T_241 = bits(_WIRE_25, 6, 6) connect _WIRE_24.px, _T_241 node _T_242 = bits(_WIRE_25, 7, 7) connect _WIRE_24.pw, _T_242 node _T_243 = bits(_WIRE_25, 8, 8) connect _WIRE_24.sr, _T_243 node _T_244 = bits(_WIRE_25, 9, 9) connect _WIRE_24.sx, _T_244 node _T_245 = bits(_WIRE_25, 10, 10) connect _WIRE_24.sw, _T_245 node _T_246 = bits(_WIRE_25, 11, 11) connect _WIRE_24.ae, _T_246 node _T_247 = bits(_WIRE_25, 12, 12) connect _WIRE_24.g, _T_247 node _T_248 = bits(_WIRE_25, 13, 13) connect _WIRE_24.u, _T_248 node _T_249 = bits(_WIRE_25, 33, 14) connect _WIRE_24.ppn, _T_249 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<34> connect _WIRE_27, sectored_entries[1].data[1] node _T_250 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_250 node _T_251 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_251 node _T_252 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_252 node _T_253 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_253 node _T_254 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_254 node _T_255 = bits(_WIRE_27, 5, 5) connect _WIRE_26.pr, _T_255 node _T_256 = bits(_WIRE_27, 6, 6) connect _WIRE_26.px, _T_256 node _T_257 = bits(_WIRE_27, 7, 7) connect _WIRE_26.pw, _T_257 node _T_258 = bits(_WIRE_27, 8, 8) connect _WIRE_26.sr, _T_258 node _T_259 = bits(_WIRE_27, 9, 9) connect _WIRE_26.sx, _T_259 node _T_260 = bits(_WIRE_27, 10, 10) connect _WIRE_26.sw, _T_260 node _T_261 = bits(_WIRE_27, 11, 11) connect _WIRE_26.ae, _T_261 node _T_262 = bits(_WIRE_27, 12, 12) connect _WIRE_26.g, _T_262 node _T_263 = bits(_WIRE_27, 13, 13) connect _WIRE_26.u, _T_263 node _T_264 = bits(_WIRE_27, 33, 14) connect _WIRE_26.ppn, _T_264 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<34> connect _WIRE_29, sectored_entries[1].data[2] node _T_265 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_265 node _T_266 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_266 node _T_267 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_267 node _T_268 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_268 node _T_269 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_269 node _T_270 = bits(_WIRE_29, 5, 5) connect _WIRE_28.pr, _T_270 node _T_271 = bits(_WIRE_29, 6, 6) connect _WIRE_28.px, _T_271 node _T_272 = bits(_WIRE_29, 7, 7) connect _WIRE_28.pw, _T_272 node _T_273 = bits(_WIRE_29, 8, 8) connect _WIRE_28.sr, _T_273 node _T_274 = bits(_WIRE_29, 9, 9) connect _WIRE_28.sx, _T_274 node _T_275 = bits(_WIRE_29, 10, 10) connect _WIRE_28.sw, _T_275 node _T_276 = bits(_WIRE_29, 11, 11) connect _WIRE_28.ae, _T_276 node _T_277 = bits(_WIRE_29, 12, 12) connect _WIRE_28.g, _T_277 node _T_278 = bits(_WIRE_29, 13, 13) connect _WIRE_28.u, _T_278 node _T_279 = bits(_WIRE_29, 33, 14) connect _WIRE_28.ppn, _T_279 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<34> connect _WIRE_31, sectored_entries[1].data[3] node _T_280 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_280 node _T_281 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_281 node _T_282 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_282 node _T_283 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_283 node _T_284 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_284 node _T_285 = bits(_WIRE_31, 5, 5) connect _WIRE_30.pr, _T_285 node _T_286 = bits(_WIRE_31, 6, 6) connect _WIRE_30.px, _T_286 node _T_287 = bits(_WIRE_31, 7, 7) connect _WIRE_30.pw, _T_287 node _T_288 = bits(_WIRE_31, 8, 8) connect _WIRE_30.sr, _T_288 node _T_289 = bits(_WIRE_31, 9, 9) connect _WIRE_30.sx, _T_289 node _T_290 = bits(_WIRE_31, 10, 10) connect _WIRE_30.sw, _T_290 node _T_291 = bits(_WIRE_31, 11, 11) connect _WIRE_30.ae, _T_291 node _T_292 = bits(_WIRE_31, 12, 12) connect _WIRE_30.g, _T_292 node _T_293 = bits(_WIRE_31, 13, 13) connect _WIRE_30.u, _T_293 node _T_294 = bits(_WIRE_31, 33, 14) connect _WIRE_30.ppn, _T_294 node _T_295 = eq(_WIRE_24.g, UInt<1>(0h0)) when _T_295 : connect sectored_entries[1].valid[0], UInt<1>(0h0) node _T_296 = eq(_WIRE_26.g, UInt<1>(0h0)) when _T_296 : connect sectored_entries[1].valid[1], UInt<1>(0h0) node _T_297 = eq(_WIRE_28.g, UInt<1>(0h0)) when _T_297 : connect sectored_entries[1].valid[2], UInt<1>(0h0) node _T_298 = eq(_WIRE_30.g, UInt<1>(0h0)) when _T_298 : connect sectored_entries[1].valid[3], UInt<1>(0h0) else : connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_299 = bits(superpage_entries[0].tag, 26, 18) node _T_300 = bits(vpn[0], 26, 18) node _T_301 = eq(_T_299, _T_300) node _T_302 = or(ignore, _T_301) node _T_303 = and(superpage_entries[0].valid[0], _T_302) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_304 = bits(superpage_entries[0].tag, 17, 9) node _T_305 = bits(vpn[0], 17, 9) node _T_306 = eq(_T_304, _T_305) node _T_307 = or(ignore_1, _T_306) node _T_308 = and(_T_303, _T_307) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_309 = bits(superpage_entries[0].tag, 8, 0) node _T_310 = bits(vpn[0], 8, 0) node _T_311 = eq(_T_309, _T_310) node _T_312 = or(ignore_2, _T_311) node _T_313 = and(_T_308, _T_312) when _T_313 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<34> connect _WIRE_33, superpage_entries[0].data[0] node _T_314 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_314 node _T_315 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_315 node _T_316 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_316 node _T_317 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_317 node _T_318 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_318 node _T_319 = bits(_WIRE_33, 5, 5) connect _WIRE_32.pr, _T_319 node _T_320 = bits(_WIRE_33, 6, 6) connect _WIRE_32.px, _T_320 node _T_321 = bits(_WIRE_33, 7, 7) connect _WIRE_32.pw, _T_321 node _T_322 = bits(_WIRE_33, 8, 8) connect _WIRE_32.sr, _T_322 node _T_323 = bits(_WIRE_33, 9, 9) connect _WIRE_32.sx, _T_323 node _T_324 = bits(_WIRE_33, 10, 10) connect _WIRE_32.sw, _T_324 node _T_325 = bits(_WIRE_33, 11, 11) connect _WIRE_32.ae, _T_325 node _T_326 = bits(_WIRE_33, 12, 12) connect _WIRE_32.g, _T_326 node _T_327 = bits(_WIRE_33, 13, 13) connect _WIRE_32.u, _T_327 node _T_328 = bits(_WIRE_33, 33, 14) connect _WIRE_32.ppn, _T_328 node _T_329 = eq(_WIRE_32.g, UInt<1>(0h0)) when _T_329 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : connect superpage_entries[0].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_330 = bits(superpage_entries[1].tag, 26, 18) node _T_331 = bits(vpn[0], 26, 18) node _T_332 = eq(_T_330, _T_331) node _T_333 = or(ignore_3, _T_332) node _T_334 = and(superpage_entries[1].valid[0], _T_333) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_335 = bits(superpage_entries[1].tag, 17, 9) node _T_336 = bits(vpn[0], 17, 9) node _T_337 = eq(_T_335, _T_336) node _T_338 = or(ignore_4, _T_337) node _T_339 = and(_T_334, _T_338) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_340 = bits(superpage_entries[1].tag, 8, 0) node _T_341 = bits(vpn[0], 8, 0) node _T_342 = eq(_T_340, _T_341) node _T_343 = or(ignore_5, _T_342) node _T_344 = and(_T_339, _T_343) when _T_344 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<34> connect _WIRE_35, superpage_entries[1].data[0] node _T_345 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_345 node _T_346 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_346 node _T_347 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_347 node _T_348 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_348 node _T_349 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_349 node _T_350 = bits(_WIRE_35, 5, 5) connect _WIRE_34.pr, _T_350 node _T_351 = bits(_WIRE_35, 6, 6) connect _WIRE_34.px, _T_351 node _T_352 = bits(_WIRE_35, 7, 7) connect _WIRE_34.pw, _T_352 node _T_353 = bits(_WIRE_35, 8, 8) connect _WIRE_34.sr, _T_353 node _T_354 = bits(_WIRE_35, 9, 9) connect _WIRE_34.sx, _T_354 node _T_355 = bits(_WIRE_35, 10, 10) connect _WIRE_34.sw, _T_355 node _T_356 = bits(_WIRE_35, 11, 11) connect _WIRE_34.ae, _T_356 node _T_357 = bits(_WIRE_35, 12, 12) connect _WIRE_34.g, _T_357 node _T_358 = bits(_WIRE_35, 13, 13) connect _WIRE_34.u, _T_358 node _T_359 = bits(_WIRE_35, 33, 14) connect _WIRE_34.ppn, _T_359 node _T_360 = eq(_WIRE_34.g, UInt<1>(0h0)) when _T_360 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : connect superpage_entries[1].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_361 = bits(superpage_entries[2].tag, 26, 18) node _T_362 = bits(vpn[0], 26, 18) node _T_363 = eq(_T_361, _T_362) node _T_364 = or(ignore_6, _T_363) node _T_365 = and(superpage_entries[2].valid[0], _T_364) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_366 = bits(superpage_entries[2].tag, 17, 9) node _T_367 = bits(vpn[0], 17, 9) node _T_368 = eq(_T_366, _T_367) node _T_369 = or(ignore_7, _T_368) node _T_370 = and(_T_365, _T_369) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_371 = bits(superpage_entries[2].tag, 8, 0) node _T_372 = bits(vpn[0], 8, 0) node _T_373 = eq(_T_371, _T_372) node _T_374 = or(ignore_8, _T_373) node _T_375 = and(_T_370, _T_374) when _T_375 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<34> connect _WIRE_37, superpage_entries[2].data[0] node _T_376 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_376 node _T_377 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_377 node _T_378 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_378 node _T_379 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_379 node _T_380 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_380 node _T_381 = bits(_WIRE_37, 5, 5) connect _WIRE_36.pr, _T_381 node _T_382 = bits(_WIRE_37, 6, 6) connect _WIRE_36.px, _T_382 node _T_383 = bits(_WIRE_37, 7, 7) connect _WIRE_36.pw, _T_383 node _T_384 = bits(_WIRE_37, 8, 8) connect _WIRE_36.sr, _T_384 node _T_385 = bits(_WIRE_37, 9, 9) connect _WIRE_36.sx, _T_385 node _T_386 = bits(_WIRE_37, 10, 10) connect _WIRE_36.sw, _T_386 node _T_387 = bits(_WIRE_37, 11, 11) connect _WIRE_36.ae, _T_387 node _T_388 = bits(_WIRE_37, 12, 12) connect _WIRE_36.g, _T_388 node _T_389 = bits(_WIRE_37, 13, 13) connect _WIRE_36.u, _T_389 node _T_390 = bits(_WIRE_37, 33, 14) connect _WIRE_36.ppn, _T_390 node _T_391 = eq(_WIRE_36.g, UInt<1>(0h0)) when _T_391 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : connect superpage_entries[2].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_392 = bits(superpage_entries[3].tag, 26, 18) node _T_393 = bits(vpn[0], 26, 18) node _T_394 = eq(_T_392, _T_393) node _T_395 = or(ignore_9, _T_394) node _T_396 = and(superpage_entries[3].valid[0], _T_395) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_397 = bits(superpage_entries[3].tag, 17, 9) node _T_398 = bits(vpn[0], 17, 9) node _T_399 = eq(_T_397, _T_398) node _T_400 = or(ignore_10, _T_399) node _T_401 = and(_T_396, _T_400) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_402 = bits(superpage_entries[3].tag, 8, 0) node _T_403 = bits(vpn[0], 8, 0) node _T_404 = eq(_T_402, _T_403) node _T_405 = or(ignore_11, _T_404) node _T_406 = and(_T_401, _T_405) when _T_406 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<34> connect _WIRE_39, superpage_entries[3].data[0] node _T_407 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_407 node _T_408 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_408 node _T_409 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_409 node _T_410 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_410 node _T_411 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_411 node _T_412 = bits(_WIRE_39, 5, 5) connect _WIRE_38.pr, _T_412 node _T_413 = bits(_WIRE_39, 6, 6) connect _WIRE_38.px, _T_413 node _T_414 = bits(_WIRE_39, 7, 7) connect _WIRE_38.pw, _T_414 node _T_415 = bits(_WIRE_39, 8, 8) connect _WIRE_38.sr, _T_415 node _T_416 = bits(_WIRE_39, 9, 9) connect _WIRE_38.sx, _T_416 node _T_417 = bits(_WIRE_39, 10, 10) connect _WIRE_38.sw, _T_417 node _T_418 = bits(_WIRE_39, 11, 11) connect _WIRE_38.ae, _T_418 node _T_419 = bits(_WIRE_39, 12, 12) connect _WIRE_38.g, _T_419 node _T_420 = bits(_WIRE_39, 13, 13) connect _WIRE_38.u, _T_420 node _T_421 = bits(_WIRE_39, 33, 14) connect _WIRE_38.ppn, _T_421 node _T_422 = eq(_WIRE_38.g, UInt<1>(0h0)) when _T_422 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : connect superpage_entries[3].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_423 = bits(special_entry.tag, 26, 18) node _T_424 = bits(vpn[0], 26, 18) node _T_425 = eq(_T_423, _T_424) node _T_426 = or(ignore_12, _T_425) node _T_427 = and(special_entry.valid[0], _T_426) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_428 = bits(special_entry.tag, 17, 9) node _T_429 = bits(vpn[0], 17, 9) node _T_430 = eq(_T_428, _T_429) node _T_431 = or(ignore_13, _T_430) node _T_432 = and(_T_427, _T_431) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_433 = bits(special_entry.tag, 8, 0) node _T_434 = bits(vpn[0], 8, 0) node _T_435 = eq(_T_433, _T_434) node _T_436 = or(ignore_14, _T_435) node _T_437 = and(_T_432, _T_436) when _T_437 : connect special_entry.valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<34> connect _WIRE_41, special_entry.data[0] node _T_438 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_438 node _T_439 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_439 node _T_440 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_440 node _T_441 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_441 node _T_442 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_442 node _T_443 = bits(_WIRE_41, 5, 5) connect _WIRE_40.pr, _T_443 node _T_444 = bits(_WIRE_41, 6, 6) connect _WIRE_40.px, _T_444 node _T_445 = bits(_WIRE_41, 7, 7) connect _WIRE_40.pw, _T_445 node _T_446 = bits(_WIRE_41, 8, 8) connect _WIRE_40.sr, _T_446 node _T_447 = bits(_WIRE_41, 9, 9) connect _WIRE_40.sx, _T_447 node _T_448 = bits(_WIRE_41, 10, 10) connect _WIRE_40.sw, _T_448 node _T_449 = bits(_WIRE_41, 11, 11) connect _WIRE_40.ae, _T_449 node _T_450 = bits(_WIRE_41, 12, 12) connect _WIRE_40.g, _T_450 node _T_451 = bits(_WIRE_41, 13, 13) connect _WIRE_40.u, _T_451 node _T_452 = bits(_WIRE_41, 33, 14) connect _WIRE_40.ppn, _T_452 node _T_453 = eq(_WIRE_40.g, UInt<1>(0h0)) when _T_453 : connect special_entry.valid[0], UInt<1>(0h0) else : connect special_entry.valid[0], UInt<1>(0h0) node _T_454 = asUInt(reset) node _T_455 = or(multipleHits[0], _T_454) when _T_455 : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0)	module NBDTLB( // @[tlb.scala:17:7] input clock, // @[tlb.scala:17:7] input reset, // @[tlb.scala:17:7] input io_req_0_valid, // @[tlb.scala:19:14] input [39:0] io_req_0_bits_vaddr, // @[tlb.scala:19:14] input io_req_0_bits_passthrough, // @[tlb.scala:19:14] input [1:0] io_req_0_bits_size, // @[tlb.scala:19:14] input [4:0] io_req_0_bits_cmd, // @[tlb.scala:19:14] input [1:0] io_req_0_bits_prv, // @[tlb.scala:19:14] input io_req_0_bits_v, // @[tlb.scala:19:14] output io_resp_0_miss, // @[tlb.scala:19:14] output [31:0] io_resp_0_paddr, // @[tlb.scala:19:14] output io_resp_0_pf_ld, // @[tlb.scala:19:14] output io_resp_0_pf_st, // @[tlb.scala:19:14] output io_resp_0_ae_ld, // @[tlb.scala:19:14] output io_resp_0_ae_st, // @[tlb.scala:19:14] output io_resp_0_ma_ld, // @[tlb.scala:19:14] output io_resp_0_ma_st, // @[tlb.scala:19:14] output io_resp_0_cacheable, // @[tlb.scala:19:14] input io_sfence_valid, // @[tlb.scala:19:14] input io_sfence_bits_rs1, // @[tlb.scala:19:14] input io_sfence_bits_rs2, // @[tlb.scala:19:14] input [38:0] io_sfence_bits_addr, // @[tlb.scala:19:14] input io_sfence_bits_asid, // @[tlb.scala:19:14] input io_sfence_bits_hv, // @[tlb.scala:19:14] input io_sfence_bits_hg, // @[tlb.scala:19:14] input io_ptw_req_ready, // @[tlb.scala:19:14] output io_ptw_req_valid, // @[tlb.scala:19:14] output io_ptw_req_bits_valid, // @[tlb.scala:19:14] output [26:0] io_ptw_req_bits_bits_addr, // @[tlb.scala:19:14] input io_ptw_resp_valid, // @[tlb.scala:19:14] input io_ptw_resp_bits_ae_ptw, // @[tlb.scala:19:14] input io_ptw_resp_bits_ae_final, // @[tlb.scala:19:14] input io_ptw_resp_bits_pf, // @[tlb.scala:19:14] input io_ptw_resp_bits_gf, // @[tlb.scala:19:14] input io_ptw_resp_bits_hr, // @[tlb.scala:19:14] input io_ptw_resp_bits_hw, // @[tlb.scala:19:14] input io_ptw_resp_bits_hx, // @[tlb.scala:19:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[tlb.scala:19:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[tlb.scala:19:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_d, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_a, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_g, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_u, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_x, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_w, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_r, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_v, // @[tlb.scala:19:14] input [1:0] io_ptw_resp_bits_level, // @[tlb.scala:19:14] input io_ptw_resp_bits_homogeneous, // @[tlb.scala:19:14] input io_ptw_resp_bits_gpa_valid, // @[tlb.scala:19:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[tlb.scala:19:14] input io_ptw_resp_bits_gpa_is_pte, // @[tlb.scala:19:14] input [3:0] io_ptw_ptbr_mode, // @[tlb.scala:19:14] input [43:0] io_ptw_ptbr_ppn, // @[tlb.scala:19:14] input io_ptw_status_debug, // @[tlb.scala:19:14] input io_ptw_status_cease, // @[tlb.scala:19:14] input io_ptw_status_wfi, // @[tlb.scala:19:14] input [1:0] io_ptw_status_dprv, // @[tlb.scala:19:14] input io_ptw_status_dv, // @[tlb.scala:19:14] input [1:0] io_ptw_status_prv, // @[tlb.scala:19:14] input io_ptw_status_v, // @[tlb.scala:19:14] input io_ptw_status_sd, // @[tlb.scala:19:14] input io_ptw_status_mpv, // @[tlb.scala:19:14] input io_ptw_status_gva, // @[tlb.scala:19:14] input io_ptw_status_tsr, // @[tlb.scala:19:14] input io_ptw_status_tw, // @[tlb.scala:19:14] input io_ptw_status_tvm, // @[tlb.scala:19:14] input io_ptw_status_mxr, // @[tlb.scala:19:14] input io_ptw_status_sum, // @[tlb.scala:19:14] input io_ptw_status_mprv, // @[tlb.scala:19:14] input [1:0] io_ptw_status_fs, // @[tlb.scala:19:14] input [1:0] io_ptw_status_mpp, // @[tlb.scala:19:14] input io_ptw_status_spp, // @[tlb.scala:19:14] input io_ptw_status_mpie, // @[tlb.scala:19:14] input io_ptw_status_spie, // @[tlb.scala:19:14] input io_ptw_status_mie, // @[tlb.scala:19:14] input io_ptw_status_sie, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_0_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_0_mask, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_1_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_1_mask, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_2_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_2_mask, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_3_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_3_mask, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_4_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_4_mask, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_5_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_5_mask, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_6_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_6_mask, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_7_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_7_mask, // @[tlb.scala:19:14] input io_kill // @[tlb.scala:19:14] ); wire _normal_entries_WIRE_12_5_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_5_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_4_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_3_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_2_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_1_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_0_ppn; // @[tlb.scala:212:45] wire _entries_WIRE_14_6_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_6_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_5_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_4_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_3_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_2_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_1_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_0_ppn; // @[tlb.scala:211:38] wire [19:0] _ppn_data_barrier_6_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_5_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_4_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_3_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_2_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_1_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_io_y_ppn; // @[package.scala:267:25] wire _pmp_0_io_r; // @[tlb.scala:150:40] wire _pmp_0_io_w; // @[tlb.scala:150:40] wire _pmp_0_io_x; // @[tlb.scala:150:40] wire [19:0] _mpu_ppn_data_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_0_valid_0 = io_req_0_valid; // @[tlb.scala:17:7] wire [39:0] io_req_0_bits_vaddr_0 = io_req_0_bits_vaddr; // @[tlb.scala:17:7] wire io_req_0_bits_passthrough_0 = io_req_0_bits_passthrough; // @[tlb.scala:17:7] wire [1:0] io_req_0_bits_size_0 = io_req_0_bits_size; // @[tlb.scala:17:7] wire [4:0] io_req_0_bits_cmd_0 = io_req_0_bits_cmd; // @[tlb.scala:17:7] wire [1:0] io_req_0_bits_prv_0 = io_req_0_bits_prv; // @[tlb.scala:17:7] wire io_req_0_bits_v_0 = io_req_0_bits_v; // @[tlb.scala:17:7] wire io_sfence_valid_0 = io_sfence_valid; // @[tlb.scala:17:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[tlb.scala:17:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[tlb.scala:17:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[tlb.scala:17:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[tlb.scala:17:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[tlb.scala:17:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[tlb.scala:17:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[tlb.scala:17:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[tlb.scala:17:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[tlb.scala:17:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[tlb.scala:17:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[tlb.scala:17:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[tlb.scala:17:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[tlb.scala:17:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[tlb.scala:17:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[tlb.scala:17:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[tlb.scala:17:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[tlb.scala:17:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[tlb.scala:17:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[tlb.scala:17:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[tlb.scala:17:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[tlb.scala:17:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[tlb.scala:17:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[tlb.scala:17:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[tlb.scala:17:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[tlb.scala:17:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[tlb.scala:17:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[tlb.scala:17:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[tlb.scala:17:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[tlb.scala:17:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[tlb.scala:17:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[tlb.scala:17:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[tlb.scala:17:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[tlb.scala:17:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[tlb.scala:17:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[tlb.scala:17:7] wire io_kill_0 = io_kill; // @[tlb.scala:17:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[tlb.scala:17:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[tlb.scala:17:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[tlb.scala:17:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[tlb.scala:17:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[tlb.scala:17:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[tlb.scala:17:7] wire io_resp_0_gpa_is_pte = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_ld = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_st = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_inst = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_ma_inst = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_hu = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spvp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_debug = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_cease = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_wfi = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_dv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_v = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mxr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sum = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mprv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[tlb.scala:17:7] wire _cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _prot_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _prot_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _prot_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _prot_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _prot_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire _superpage_hits_ignore_T = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore = 1'h0; // @[tlb.scala:66:36] wire _superpage_hits_ignore_T_3 = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore_3 = 1'h0; // @[tlb.scala:66:36] wire _superpage_hits_ignore_T_6 = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore_6 = 1'h0; // @[tlb.scala:66:36] wire _superpage_hits_ignore_T_9 = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore_9 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_3 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_3 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_6 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_6 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_9 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_9 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_12 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_12 = 1'h0; // @[tlb.scala:66:36] wire newEntry_fragmented_superpage = 1'h0; // @[tlb.scala:179:24] wire _cmd_write_perms_T_1 = 1'h0; // @[tlb.scala:248:29] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:37] wire _ignore_T = 1'h0; // @[tlb.scala:66:30] wire ignore = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_3 = 1'h0; // @[tlb.scala:66:30] wire ignore_3 = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_6 = 1'h0; // @[tlb.scala:66:30] wire ignore_6 = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_9 = 1'h0; // @[tlb.scala:66:30] wire ignore_9 = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_12 = 1'h0; // @[tlb.scala:66:30] wire ignore_12 = 1'h0; // @[tlb.scala:66:36] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[tlb.scala:17:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[tlb.scala:17:7] wire io_req_0_ready = 1'h1; // @[tlb.scala:17:7] wire _homogeneous_T_60 = 1'h1; // @[TLBPermissions.scala:87:22] wire _prot_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire superpage_hits_ignore_2 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_13 = 1'h1; // @[tlb.scala:67:42] wire superpage_hits_ignore_5 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_28 = 1'h1; // @[tlb.scala:67:42] wire superpage_hits_ignore_8 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_43 = 1'h1; // @[tlb.scala:67:42] wire superpage_hits_ignore_11 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_58 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_2 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_23 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_5 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_39 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_8 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_55 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_11 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_71 = 1'h1; // @[tlb.scala:67:42] wire ppn_ignore_1 = 1'h1; // @[tlb.scala:80:38] wire ppn_ignore_3 = 1'h1; // @[tlb.scala:80:38] wire ppn_ignore_5 = 1'h1; // @[tlb.scala:80:38] wire ppn_ignore_7 = 1'h1; // @[tlb.scala:80:38] wire _bad_va_T = 1'h1; // @[tlb.scala:238:38] wire ignore_2 = 1'h1; // @[tlb.scala:66:36] wire ignore_5 = 1'h1; // @[tlb.scala:66:36] wire ignore_8 = 1'h1; // @[tlb.scala:66:36] wire ignore_11 = 1'h1; // @[tlb.scala:66:36] wire [39:0] io_resp_0_gpa = 40'h0; // @[tlb.scala:17:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[tlb.scala:17:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[tlb.scala:17:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[tlb.scala:17:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[tlb.scala:17:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[tlb.scala:17:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[tlb.scala:17:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[tlb.scala:17:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[tlb.scala:17:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[tlb.scala:17:7] wire [7:0] _must_alloc_array_T_5 = 8'hFF; // @[tlb.scala:264:32] wire [5:0] _ae_valid_array_T_2 = 6'h3F; // @[tlb.scala:255:9] wire [40:0] _prot_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _prot_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire [1:0] io_resp_0_size = io_req_0_bits_size_0; // @[tlb.scala:17:7] wire [4:0] io_resp_0_cmd = io_req_0_bits_cmd_0; // @[tlb.scala:17:7] wire _io_miss_rdy_T; // @[tlb.scala:290:24] wire _io_resp_0_miss_T_1; // @[tlb.scala:310:50] wire [31:0] _io_resp_0_paddr_T_1; // @[tlb.scala:311:28] wire _io_resp_0_pf_ld_T_3; // @[tlb.scala:298:54] wire _io_resp_0_pf_st_T_3; // @[tlb.scala:299:61] wire _io_resp_0_pf_inst_T_2; // @[tlb.scala:300:37] wire _io_resp_0_ae_ld_T_2; // @[tlb.scala:301:74] wire _io_resp_0_ae_st_T_2; // @[tlb.scala:302:74] wire _io_resp_0_ae_inst_T_3; // @[tlb.scala:303:74] wire _io_resp_0_ma_ld_T_1; // @[tlb.scala:304:54] wire _io_resp_0_ma_st_T_1; // @[tlb.scala:305:54] wire _io_resp_0_cacheable_T_1; // @[tlb.scala:307:55] wire _io_resp_0_must_alloc_T_1; // @[tlb.scala:308:64] wire _io_resp_0_prefetchable_T_2; // @[tlb.scala:309:70] wire _io_ptw_req_valid_T; // @[tlb.scala:317:29] wire _io_ptw_req_bits_valid_T; // @[tlb.scala:319:28] wire do_refill = io_ptw_resp_valid_0; // @[tlb.scala:17:7, :144:29] wire newEntry_ae = io_ptw_resp_bits_ae_final_0; // @[tlb.scala:17:7, :179:24] wire newEntry_g = io_ptw_resp_bits_pte_g_0; // @[tlb.scala:17:7, :179:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[tlb.scala:17:7, :179:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire io_resp_0_pf_ld_0; // @[tlb.scala:17:7] wire io_resp_0_pf_st_0; // @[tlb.scala:17:7] wire io_resp_0_pf_inst; // @[tlb.scala:17:7] wire io_resp_0_ae_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ae_st_0; // @[tlb.scala:17:7] wire io_resp_0_ae_inst; // @[tlb.scala:17:7] wire io_resp_0_ma_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ma_st_0; // @[tlb.scala:17:7] wire io_resp_0_miss_0; // @[tlb.scala:17:7] wire [31:0] io_resp_0_paddr_0; // @[tlb.scala:17:7] wire io_resp_0_cacheable_0; // @[tlb.scala:17:7] wire io_resp_0_must_alloc; // @[tlb.scala:17:7] wire io_resp_0_prefetchable; // @[tlb.scala:17:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[tlb.scala:17:7] wire io_ptw_req_bits_valid_0; // @[tlb.scala:17:7] wire io_ptw_req_valid_0; // @[tlb.scala:17:7] wire io_miss_rdy; // @[tlb.scala:17:7] reg [1:0] sectored_entries_0_level; // @[tlb.scala:122:29] reg [26:0] sectored_entries_0_tag; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_0; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_1; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_2; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_3; // @[tlb.scala:122:29] reg sectored_entries_0_valid_0; // @[tlb.scala:122:29] reg sectored_entries_0_valid_1; // @[tlb.scala:122:29] reg sectored_entries_0_valid_2; // @[tlb.scala:122:29] reg sectored_entries_0_valid_3; // @[tlb.scala:122:29] reg [1:0] sectored_entries_1_level; // @[tlb.scala:122:29] reg [26:0] sectored_entries_1_tag; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_0; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_1; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_2; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_3; // @[tlb.scala:122:29] reg sectored_entries_1_valid_0; // @[tlb.scala:122:29] reg sectored_entries_1_valid_1; // @[tlb.scala:122:29] reg sectored_entries_1_valid_2; // @[tlb.scala:122:29] reg sectored_entries_1_valid_3; // @[tlb.scala:122:29] reg [1:0] superpage_entries_0_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_0_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_0_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_5 = superpage_entries_0_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_5 = superpage_entries_0_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_5 = superpage_entries_0_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_0_valid_0; // @[tlb.scala:123:30] reg [1:0] superpage_entries_1_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_1_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_1_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_7 = superpage_entries_1_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_7 = superpage_entries_1_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_7 = superpage_entries_1_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_1_valid_0; // @[tlb.scala:123:30] reg [1:0] superpage_entries_2_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_2_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_2_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_9 = superpage_entries_2_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_9 = superpage_entries_2_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_9 = superpage_entries_2_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_2_valid_0; // @[tlb.scala:123:30] reg [1:0] superpage_entries_3_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_3_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_3_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_11 = superpage_entries_3_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_11 = superpage_entries_3_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_11 = superpage_entries_3_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_3_valid_0; // @[tlb.scala:123:30] reg [1:0] special_entry_level; // @[tlb.scala:124:56] reg [26:0] special_entry_tag; // @[tlb.scala:124:56] reg [33:0] special_entry_data_0; // @[tlb.scala:124:56] wire [33:0] _mpu_ppn_data_WIRE_1 = special_entry_data_0; // @[tlb.scala:58:79, :124:56] wire [33:0] _ppn_data_WIRE_13 = special_entry_data_0; // @[tlb.scala:58:79, :124:56] wire [33:0] _entries_WIRE_13 = special_entry_data_0; // @[tlb.scala:58:79, :124:56] reg special_entry_valid_0; // @[tlb.scala:124:56] reg [1:0] state; // @[tlb.scala:129:22] reg [26:0] r_refill_tag; // @[tlb.scala:130:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[tlb.scala:17:7, :130:25] reg [1:0] r_superpage_repl_addr; // @[tlb.scala:131:34] reg r_sectored_repl_addr; // @[tlb.scala:132:33] reg r_sectored_hit_addr; // @[tlb.scala:133:32] reg r_sectored_hit; // @[tlb.scala:134:27] wire priv_s = io_ptw_status_dprv_0[0]; // @[tlb.scala:17:7, :137:20] wire priv_uses_vm = ~(io_ptw_status_dprv_0[1]); // @[tlb.scala:17:7, :138:27] wire _vm_enabled_T = io_ptw_ptbr_mode_0[3]; // @[tlb.scala:17:7, :139:63] wire _vm_enabled_T_1 = _vm_enabled_T; // @[tlb.scala:139:{44,63}] wire _vm_enabled_T_2 = _vm_enabled_T_1 & priv_uses_vm; // @[tlb.scala:138:27, :139:{44,93}] wire _vm_enabled_T_3 = ~io_req_0_bits_passthrough_0; // @[tlb.scala:17:7, :139:112] wire _vm_enabled_T_4 = _vm_enabled_T_2 & _vm_enabled_T_3; // @[tlb.scala:139:{93,109,112}] wire vm_enabled_0 = _vm_enabled_T_4; // @[tlb.scala:119:49, :139:109] wire _mpu_ppn_T = vm_enabled_0; // @[tlb.scala:119:49, :148:35] wire [26:0] _vpn_T = io_req_0_bits_vaddr_0[38:12]; // @[tlb.scala:17:7, :142:47] wire [26:0] vpn_0 = _vpn_T; // @[tlb.scala:119:49, :142:47] wire [26:0] _ppn_T_5 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [26:0] _ppn_T_13 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [26:0] _ppn_T_21 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [26:0] _ppn_T_29 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44, :179:24] wire _T_27 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_27; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_27; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_data_T_14; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_13; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_12; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_11; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_10; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_9; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_8; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_7; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_6; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_5; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_4; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_3; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_2; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_1; // @[tlb.scala:58:79] wire _mpu_ppn_data_T; // @[tlb.scala:58:79] assign _mpu_ppn_data_T = _mpu_ppn_data_WIRE_1[0]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_fragmented_superpage = _mpu_ppn_data_T; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_1 = _mpu_ppn_data_WIRE_1[1]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_c = _mpu_ppn_data_T_1; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_2 = _mpu_ppn_data_WIRE_1[2]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_eff = _mpu_ppn_data_T_2; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_3 = _mpu_ppn_data_WIRE_1[3]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_paa = _mpu_ppn_data_T_3; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_4 = _mpu_ppn_data_WIRE_1[4]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pal = _mpu_ppn_data_T_4; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_5 = _mpu_ppn_data_WIRE_1[5]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pr = _mpu_ppn_data_T_5; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_6 = _mpu_ppn_data_WIRE_1[6]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_px = _mpu_ppn_data_T_6; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_7 = _mpu_ppn_data_WIRE_1[7]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pw = _mpu_ppn_data_T_7; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_8 = _mpu_ppn_data_WIRE_1[8]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sr = _mpu_ppn_data_T_8; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_9 = _mpu_ppn_data_WIRE_1[9]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sx = _mpu_ppn_data_T_9; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_10 = _mpu_ppn_data_WIRE_1[10]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sw = _mpu_ppn_data_T_10; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_11 = _mpu_ppn_data_WIRE_1[11]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_ae = _mpu_ppn_data_T_11; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_12 = _mpu_ppn_data_WIRE_1[12]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_g = _mpu_ppn_data_T_12; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_13 = _mpu_ppn_data_WIRE_1[13]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_u = _mpu_ppn_data_T_13; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_14 = _mpu_ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _mpu_ppn_data_WIRE_ppn = _mpu_ppn_data_T_14; // @[tlb.scala:58:79] wire [1:0] mpu_ppn_res = _mpu_ppn_data_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[tlb.scala:80:31, :124:56] wire _mpu_ppn_ignore_T; // @[tlb.scala:80:31] assign _mpu_ppn_ignore_T = _GEN; // @[tlb.scala:80:31] wire _hitsVec_ignore_T_13; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_13 = _GEN; // @[tlb.scala:66:30, :80:31] wire _ppn_ignore_T_8; // @[tlb.scala:80:31] assign _ppn_ignore_T_8 = _GEN; // @[tlb.scala:80:31] wire _ignore_T_13; // @[tlb.scala:66:30] assign _ignore_T_13 = _GEN; // @[tlb.scala:66:30, :80:31] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[tlb.scala:80:{31,38}] wire [26:0] _mpu_ppn_T_1 = mpu_ppn_ignore ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _mpu_ppn_T_2 = {_mpu_ppn_T_1[26:20], _mpu_ppn_T_1[19:0] \| _mpu_ppn_data_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_3 = _mpu_ppn_T_2[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _mpu_ppn_T_4 = {mpu_ppn_res, _mpu_ppn_T_3}; // @[tlb.scala:78:28, :81:{20,60}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[tlb.scala:80:31, :124:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[tlb.scala:80:{31,38}] wire [26:0] _mpu_ppn_T_5 = mpu_ppn_ignore_1 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _mpu_ppn_T_6 = {_mpu_ppn_T_5[26:20], _mpu_ppn_T_5[19:0] \| _mpu_ppn_data_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_7 = _mpu_ppn_T_6[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _mpu_ppn_T_8 = {_mpu_ppn_T_4, _mpu_ppn_T_7}; // @[tlb.scala:81:{20,60}] wire [27:0] _mpu_ppn_T_9 = io_req_0_bits_vaddr_0[39:12]; // @[tlb.scala:17:7, :148:134] wire [27:0] _mpu_ppn_T_10 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_8} : _mpu_ppn_T_9; // @[tlb.scala:81:20, :148:{20,35,134}] wire [27:0] _mpu_ppn_T_11 = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_10; // @[tlb.scala:143:44, :144:29, :147:20, :148:20] wire [27:0] mpu_ppn_0 = _mpu_ppn_T_11; // @[tlb.scala:119:49, :147:20] wire [11:0] _mpu_physaddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72] wire [11:0] _io_resp_0_paddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72, :311:57] wire [39:0] _mpu_physaddr_T_1 = {mpu_ppn_0, _mpu_physaddr_T}; // @[tlb.scala:119:49, :149:{39,72}] wire [39:0] mpu_physaddr_0 = _mpu_physaddr_T_1; // @[tlb.scala:119:49, :149:39] wire [39:0] _legal_address_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_68 = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_r_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire _pmp_0_io_prv_T = do_refill \| io_req_0_bits_passthrough_0; // @[tlb.scala:17:7, :144:29, :155:50] wire _pmp_0_io_prv_T_1 = _pmp_0_io_prv_T; // @[tlb.scala:155:{36,50}] wire [1:0] _pmp_0_io_prv_T_2 = _pmp_0_io_prv_T_1 ? 2'h1 : io_ptw_status_dprv_0; // @[tlb.scala:17:7, :155:{25,36}] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {mpu_physaddr_0[39:13], mpu_physaddr_0[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_29; // @[Parameters.scala:137:31] assign _prot_x_T_29 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {mpu_physaddr_0[39:14], mpu_physaddr_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_73; // @[Parameters.scala:137:31] assign _homogeneous_T_73 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_5; // @[Parameters.scala:137:31] assign _prot_x_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_35; // @[Parameters.scala:137:31] assign _prot_eff_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {mpu_physaddr_0[39:17], mpu_physaddr_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_5; // @[Parameters.scala:137:31] assign _cacheable_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_61; // @[Parameters.scala:137:31] assign _homogeneous_T_61 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_78; // @[Parameters.scala:137:31] assign _homogeneous_T_78 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_110; // @[Parameters.scala:137:31] assign _homogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_117; // @[Parameters.scala:137:31] assign _homogeneous_T_117 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_41; // @[Parameters.scala:137:31] assign _prot_w_T_41 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_41; // @[Parameters.scala:137:31] assign _prot_al_T_41 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_41; // @[Parameters.scala:137:31] assign _prot_aa_T_41 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_10; // @[Parameters.scala:137:31] assign _prot_x_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_40; // @[Parameters.scala:137:31] assign _prot_eff_T_40 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {mpu_physaddr_0[39:21], mpu_physaddr_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_15; // @[Parameters.scala:137:31] assign _homogeneous_T_15 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_5; // @[Parameters.scala:137:31] assign _prot_w_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_5; // @[Parameters.scala:137:31] assign _prot_al_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_5; // @[Parameters.scala:137:31] assign _prot_aa_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_34; // @[Parameters.scala:137:31] assign _prot_x_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_5; // @[Parameters.scala:137:31] assign _prot_eff_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {mpu_physaddr_0[39:21], mpu_physaddr_0[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {mpu_physaddr_0[39:26], mpu_physaddr_0[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_20; // @[Parameters.scala:137:31] assign _homogeneous_T_20 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_39; // @[Parameters.scala:137:31] assign _prot_x_T_39 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_10; // @[Parameters.scala:137:31] assign _prot_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {mpu_physaddr_0[39:26], mpu_physaddr_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_25; // @[Parameters.scala:137:31] assign _homogeneous_T_25 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_10; // @[Parameters.scala:137:31] assign _prot_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_10; // @[Parameters.scala:137:31] assign _prot_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_10; // @[Parameters.scala:137:31] assign _prot_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_44; // @[Parameters.scala:137:31] assign _prot_x_T_44 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_15; // @[Parameters.scala:137:31] assign _prot_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {mpu_physaddr_0[39:28], mpu_physaddr_0[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_17; // @[Parameters.scala:137:31] assign _cacheable_T_17 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_83; // @[Parameters.scala:137:31] assign _homogeneous_T_83 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_98; // @[Parameters.scala:137:31] assign _homogeneous_T_98 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_15; // @[Parameters.scala:137:31] assign _prot_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_20; // @[Parameters.scala:137:31] assign _prot_w_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_15; // @[Parameters.scala:137:31] assign _prot_al_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_20; // @[Parameters.scala:137:31] assign _prot_al_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_15; // @[Parameters.scala:137:31] assign _prot_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_20; // @[Parameters.scala:137:31] assign _prot_aa_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_15; // @[Parameters.scala:137:31] assign _prot_x_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_45; // @[Parameters.scala:137:31] assign _prot_eff_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {mpu_physaddr_0[39:28], mpu_physaddr_0[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_10; // @[Parameters.scala:137:31] assign _cacheable_T_10 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_35; // @[Parameters.scala:137:31] assign _homogeneous_T_35 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_49; // @[Parameters.scala:137:31] assign _prot_x_T_49 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_20; // @[Parameters.scala:137:31] assign _prot_eff_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _GEN_8 = {mpu_physaddr_0[39:29], mpu_physaddr_0[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_50; // @[Parameters.scala:137:31] assign _legal_address_T_50 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_40; // @[Parameters.scala:137:31] assign _homogeneous_T_40 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_9 = {mpu_physaddr_0[39:32], mpu_physaddr_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_22; // @[Parameters.scala:137:31] assign _cacheable_T_22 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_88; // @[Parameters.scala:137:31] assign _homogeneous_T_88 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_103; // @[Parameters.scala:137:31] assign _homogeneous_T_103 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_30; // @[Parameters.scala:137:31] assign _prot_w_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_30; // @[Parameters.scala:137:31] assign _prot_al_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_30; // @[Parameters.scala:137:31] assign _prot_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_20; // @[Parameters.scala:137:31] assign _prot_x_T_20 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_50; // @[Parameters.scala:137:31] assign _prot_eff_T_50 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 \| _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 \| _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 \| _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 \| _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 \| _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 \| _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 \| _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 \| _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 \| _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 \| _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire _legal_address_T_70 = _legal_address_T_69 \| _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire legal_address_0 = _legal_address_T_70; // @[tlb.scala:119:49, :157:84] wire _prot_r_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22] wire [40:0] _cacheable_T_1 = {1'h0, _cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_2 = _cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_3 = _cacheable_T_2; // @[Parameters.scala:137:46] wire _cacheable_T_4 = _cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _cacheable_T_6 = {1'h0, _cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_7 = _cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_8 = _cacheable_T_7; // @[Parameters.scala:137:46] wire _cacheable_T_9 = _cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _cacheable_T_11 = {1'h0, _cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_12 = _cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_13 = _cacheable_T_12; // @[Parameters.scala:137:46] wire _cacheable_T_14 = _cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_15 = _cacheable_T_4 \| _cacheable_T_9; // @[Parameters.scala:629:89] wire _cacheable_T_16 = _cacheable_T_15 \| _cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _cacheable_T_18 = {1'h0, _cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_19 = _cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_20 = _cacheable_T_19; // @[Parameters.scala:137:46] wire _cacheable_T_21 = _cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _cacheable_T_23 = {1'h0, _cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_24 = _cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_25 = _cacheable_T_24; // @[Parameters.scala:137:46] wire _cacheable_T_26 = _cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_27 = _cacheable_T_21 \| _cacheable_T_26; // @[Parameters.scala:629:89] wire _cacheable_T_29 = _cacheable_T_27; // @[Mux.scala:30:73] wire _cacheable_T_30 = _cacheable_T_29; // @[Mux.scala:30:73] wire _cacheable_WIRE = _cacheable_T_30; // @[Mux.scala:30:73] wire _cacheable_T_31 = legal_address_0 & _cacheable_WIRE; // @[Mux.scala:30:73] wire _cacheable_T_32 = _cacheable_T_31; // @[tlb.scala:159:22, :160:66] wire cacheable_0 = _cacheable_T_32; // @[tlb.scala:119:49, :160:66] wire newEntry_c = cacheable_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_59 = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire homogeneous_0 = _homogeneous_T_59; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_62 = {1'h0, _homogeneous_T_61}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_64 = _homogeneous_T_63; // @[Parameters.scala:137:46] wire _homogeneous_T_65 = _homogeneous_T_64 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_66 = _homogeneous_T_65; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_67 = ~_homogeneous_T_66; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_69 = {1'h0, _homogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_71 = _homogeneous_T_70; // @[Parameters.scala:137:46] wire _homogeneous_T_72 = _homogeneous_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_72; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_74 = {1'h0, _homogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_76 = _homogeneous_T_75; // @[Parameters.scala:137:46] wire _homogeneous_T_77 = _homogeneous_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_79 = {1'h0, _homogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_81 = _homogeneous_T_80; // @[Parameters.scala:137:46] wire _homogeneous_T_82 = _homogeneous_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_84 = {1'h0, _homogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_86 = _homogeneous_T_85; // @[Parameters.scala:137:46] wire _homogeneous_T_87 = _homogeneous_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_89 = {1'h0, _homogeneous_T_88}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_91 = _homogeneous_T_90; // @[Parameters.scala:137:46] wire _homogeneous_T_92 = _homogeneous_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_77; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_82; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_87; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_97 = _homogeneous_T_96 \| _homogeneous_T_92; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_99 = {1'h0, _homogeneous_T_98}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_101 = _homogeneous_T_100; // @[Parameters.scala:137:46] wire _homogeneous_T_102 = _homogeneous_T_101 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_102; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_104 = {1'h0, _homogeneous_T_103}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_106 = _homogeneous_T_105; // @[Parameters.scala:137:46] wire _homogeneous_T_107 = _homogeneous_T_106 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_109 = _homogeneous_T_108 \| _homogeneous_T_107; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_111 = {1'h0, _homogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_113 = _homogeneous_T_112; // @[Parameters.scala:137:46] wire _homogeneous_T_114 = _homogeneous_T_113 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_115 = _homogeneous_T_114; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_116 = ~_homogeneous_T_115; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_118 = {1'h0, _homogeneous_T_117}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_120 = _homogeneous_T_119; // @[Parameters.scala:137:46] wire _homogeneous_T_121 = _homogeneous_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_122 = _homogeneous_T_121; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_123 = ~_homogeneous_T_122; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _prot_r_T_1 = {1'h0, _prot_r_T}; // @[Parameters.scala:137:{31,41}] wire _prot_r_T_6 = _prot_r_T_5 & _pmp_0_io_r; // @[tlb.scala:150:40, :159:22, :162:60] wire prot_r_0 = _prot_r_T_6; // @[tlb.scala:119:49, :162:60] wire newEntry_pr = prot_r_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_w_T_1 = {1'h0, _prot_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_2 = _prot_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_3 = _prot_w_T_2; // @[Parameters.scala:137:46] wire _prot_w_T_4 = _prot_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_6 = {1'h0, _prot_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_7 = _prot_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_8 = _prot_w_T_7; // @[Parameters.scala:137:46] wire _prot_w_T_9 = _prot_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_11 = {1'h0, _prot_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_12 = _prot_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_13 = _prot_w_T_12; // @[Parameters.scala:137:46] wire _prot_w_T_14 = _prot_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_16 = {1'h0, _prot_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_17 = _prot_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_18 = _prot_w_T_17; // @[Parameters.scala:137:46] wire _prot_w_T_19 = _prot_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_21 = {1'h0, _prot_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_22 = _prot_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_23 = _prot_w_T_22; // @[Parameters.scala:137:46] wire _prot_w_T_24 = _prot_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_10 = {mpu_physaddr_0[39:29], mpu_physaddr_0[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_25; // @[Parameters.scala:137:31] assign _prot_w_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_25; // @[Parameters.scala:137:31] assign _prot_al_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_25; // @[Parameters.scala:137:31] assign _prot_aa_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_54; // @[Parameters.scala:137:31] assign _prot_x_T_54 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_25; // @[Parameters.scala:137:31] assign _prot_eff_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [40:0] _prot_w_T_26 = {1'h0, _prot_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_27 = _prot_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_28 = _prot_w_T_27; // @[Parameters.scala:137:46] wire _prot_w_T_29 = _prot_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_31 = {1'h0, _prot_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_32 = _prot_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_33 = _prot_w_T_32; // @[Parameters.scala:137:46] wire _prot_w_T_34 = _prot_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_w_T_35 = _prot_w_T_4 \| _prot_w_T_9; // @[Parameters.scala:629:89] wire _prot_w_T_36 = _prot_w_T_35 \| _prot_w_T_14; // @[Parameters.scala:629:89] wire _prot_w_T_37 = _prot_w_T_36 \| _prot_w_T_19; // @[Parameters.scala:629:89] wire _prot_w_T_38 = _prot_w_T_37 \| _prot_w_T_24; // @[Parameters.scala:629:89] wire _prot_w_T_39 = _prot_w_T_38 \| _prot_w_T_29; // @[Parameters.scala:629:89] wire _prot_w_T_40 = _prot_w_T_39 \| _prot_w_T_34; // @[Parameters.scala:629:89] wire _prot_w_T_46 = _prot_w_T_40; // @[Mux.scala:30:73] wire [40:0] _prot_w_T_42 = {1'h0, _prot_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_43 = _prot_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_44 = _prot_w_T_43; // @[Parameters.scala:137:46] wire _prot_w_T_45 = _prot_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_w_T_48 = _prot_w_T_46; // @[Mux.scala:30:73] wire _prot_w_WIRE = _prot_w_T_48; // @[Mux.scala:30:73] wire _prot_w_T_49 = legal_address_0 & _prot_w_WIRE; // @[Mux.scala:30:73] wire _prot_w_T_50 = _prot_w_T_49 & _pmp_0_io_w; // @[tlb.scala:150:40, :159:22, :163:64] wire prot_w_0 = _prot_w_T_50; // @[tlb.scala:119:49, :163:64] wire newEntry_pw = prot_w_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_al_T_1 = {1'h0, _prot_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_2 = _prot_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_3 = _prot_al_T_2; // @[Parameters.scala:137:46] wire _prot_al_T_4 = _prot_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_6 = {1'h0, _prot_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_7 = _prot_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_8 = _prot_al_T_7; // @[Parameters.scala:137:46] wire _prot_al_T_9 = _prot_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_11 = {1'h0, _prot_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_12 = _prot_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_13 = _prot_al_T_12; // @[Parameters.scala:137:46] wire _prot_al_T_14 = _prot_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_16 = {1'h0, _prot_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_17 = _prot_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_18 = _prot_al_T_17; // @[Parameters.scala:137:46] wire _prot_al_T_19 = _prot_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_21 = {1'h0, _prot_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_22 = _prot_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_23 = _prot_al_T_22; // @[Parameters.scala:137:46] wire _prot_al_T_24 = _prot_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_26 = {1'h0, _prot_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_27 = _prot_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_28 = _prot_al_T_27; // @[Parameters.scala:137:46] wire _prot_al_T_29 = _prot_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_31 = {1'h0, _prot_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_32 = _prot_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_33 = _prot_al_T_32; // @[Parameters.scala:137:46] wire _prot_al_T_34 = _prot_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_al_T_35 = _prot_al_T_4 \| _prot_al_T_9; // @[Parameters.scala:629:89] wire _prot_al_T_36 = _prot_al_T_35 \| _prot_al_T_14; // @[Parameters.scala:629:89] wire _prot_al_T_37 = _prot_al_T_36 \| _prot_al_T_19; // @[Parameters.scala:629:89] wire _prot_al_T_38 = _prot_al_T_37 \| _prot_al_T_24; // @[Parameters.scala:629:89] wire _prot_al_T_39 = _prot_al_T_38 \| _prot_al_T_29; // @[Parameters.scala:629:89] wire _prot_al_T_40 = _prot_al_T_39 \| _prot_al_T_34; // @[Parameters.scala:629:89] wire _prot_al_T_46 = _prot_al_T_40; // @[Mux.scala:30:73] wire [40:0] _prot_al_T_42 = {1'h0, _prot_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_43 = _prot_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_44 = _prot_al_T_43; // @[Parameters.scala:137:46] wire _prot_al_T_45 = _prot_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_al_T_48 = _prot_al_T_46; // @[Mux.scala:30:73] wire _prot_al_WIRE = _prot_al_T_48; // @[Mux.scala:30:73] wire _prot_al_T_49 = legal_address_0 & _prot_al_WIRE; // @[Mux.scala:30:73] wire prot_al_0 = _prot_al_T_49; // @[tlb.scala:119:49, :159:22] wire newEntry_pal = prot_al_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_aa_T_1 = {1'h0, _prot_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_2 = _prot_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_3 = _prot_aa_T_2; // @[Parameters.scala:137:46] wire _prot_aa_T_4 = _prot_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_6 = {1'h0, _prot_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_7 = _prot_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_8 = _prot_aa_T_7; // @[Parameters.scala:137:46] wire _prot_aa_T_9 = _prot_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_11 = {1'h0, _prot_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_12 = _prot_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_13 = _prot_aa_T_12; // @[Parameters.scala:137:46] wire _prot_aa_T_14 = _prot_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_16 = {1'h0, _prot_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_17 = _prot_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_18 = _prot_aa_T_17; // @[Parameters.scala:137:46] wire _prot_aa_T_19 = _prot_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_21 = {1'h0, _prot_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_22 = _prot_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_23 = _prot_aa_T_22; // @[Parameters.scala:137:46] wire _prot_aa_T_24 = _prot_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_26 = {1'h0, _prot_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_27 = _prot_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_28 = _prot_aa_T_27; // @[Parameters.scala:137:46] wire _prot_aa_T_29 = _prot_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_31 = {1'h0, _prot_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_32 = _prot_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_33 = _prot_aa_T_32; // @[Parameters.scala:137:46] wire _prot_aa_T_34 = _prot_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_aa_T_35 = _prot_aa_T_4 \| _prot_aa_T_9; // @[Parameters.scala:629:89] wire _prot_aa_T_36 = _prot_aa_T_35 \| _prot_aa_T_14; // @[Parameters.scala:629:89] wire _prot_aa_T_37 = _prot_aa_T_36 \| _prot_aa_T_19; // @[Parameters.scala:629:89] wire _prot_aa_T_38 = _prot_aa_T_37 \| _prot_aa_T_24; // @[Parameters.scala:629:89] wire _prot_aa_T_39 = _prot_aa_T_38 \| _prot_aa_T_29; // @[Parameters.scala:629:89] wire _prot_aa_T_40 = _prot_aa_T_39 \| _prot_aa_T_34; // @[Parameters.scala:629:89] wire _prot_aa_T_46 = _prot_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _prot_aa_T_42 = {1'h0, _prot_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_43 = _prot_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_44 = _prot_aa_T_43; // @[Parameters.scala:137:46] wire _prot_aa_T_45 = _prot_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_aa_T_48 = _prot_aa_T_46; // @[Mux.scala:30:73] wire _prot_aa_WIRE = _prot_aa_T_48; // @[Mux.scala:30:73] wire _prot_aa_T_49 = legal_address_0 & _prot_aa_WIRE; // @[Mux.scala:30:73] wire prot_aa_0 = _prot_aa_T_49; // @[tlb.scala:119:49, :159:22] wire newEntry_paa = prot_aa_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_x_T_1 = {1'h0, _prot_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_2 = _prot_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_3 = _prot_x_T_2; // @[Parameters.scala:137:46] wire _prot_x_T_4 = _prot_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_6 = {1'h0, _prot_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_7 = _prot_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_8 = _prot_x_T_7; // @[Parameters.scala:137:46] wire _prot_x_T_9 = _prot_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_11 = {1'h0, _prot_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_12 = _prot_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_13 = _prot_x_T_12; // @[Parameters.scala:137:46] wire _prot_x_T_14 = _prot_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_16 = {1'h0, _prot_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_17 = _prot_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_18 = _prot_x_T_17; // @[Parameters.scala:137:46] wire _prot_x_T_19 = _prot_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_21 = {1'h0, _prot_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_22 = _prot_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_23 = _prot_x_T_22; // @[Parameters.scala:137:46] wire _prot_x_T_24 = _prot_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_25 = _prot_x_T_4 \| _prot_x_T_9; // @[Parameters.scala:629:89] wire _prot_x_T_26 = _prot_x_T_25 \| _prot_x_T_14; // @[Parameters.scala:629:89] wire _prot_x_T_27 = _prot_x_T_26 \| _prot_x_T_19; // @[Parameters.scala:629:89] wire _prot_x_T_28 = _prot_x_T_27 \| _prot_x_T_24; // @[Parameters.scala:629:89] wire _prot_x_T_64 = _prot_x_T_28; // @[Mux.scala:30:73] wire [40:0] _prot_x_T_30 = {1'h0, _prot_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_31 = _prot_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_32 = _prot_x_T_31; // @[Parameters.scala:137:46] wire _prot_x_T_33 = _prot_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_35 = {1'h0, _prot_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_36 = _prot_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_37 = _prot_x_T_36; // @[Parameters.scala:137:46] wire _prot_x_T_38 = _prot_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_40 = {1'h0, _prot_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_41 = _prot_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_42 = _prot_x_T_41; // @[Parameters.scala:137:46] wire _prot_x_T_43 = _prot_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_45 = {1'h0, _prot_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_46 = _prot_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_47 = _prot_x_T_46; // @[Parameters.scala:137:46] wire _prot_x_T_48 = _prot_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_50 = {1'h0, _prot_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_51 = _prot_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_52 = _prot_x_T_51; // @[Parameters.scala:137:46] wire _prot_x_T_53 = _prot_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_55 = {1'h0, _prot_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_56 = _prot_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_57 = _prot_x_T_56; // @[Parameters.scala:137:46] wire _prot_x_T_58 = _prot_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_59 = _prot_x_T_33 \| _prot_x_T_38; // @[Parameters.scala:629:89] wire _prot_x_T_60 = _prot_x_T_59 \| _prot_x_T_43; // @[Parameters.scala:629:89] wire _prot_x_T_61 = _prot_x_T_60 \| _prot_x_T_48; // @[Parameters.scala:629:89] wire _prot_x_T_62 = _prot_x_T_61 \| _prot_x_T_53; // @[Parameters.scala:629:89] wire _prot_x_T_63 = _prot_x_T_62 \| _prot_x_T_58; // @[Parameters.scala:629:89] wire _prot_x_T_66 = _prot_x_T_64; // @[Mux.scala:30:73] wire _prot_x_WIRE = _prot_x_T_66; // @[Mux.scala:30:73] wire _prot_x_T_67 = legal_address_0 & _prot_x_WIRE; // @[Mux.scala:30:73] wire _prot_x_T_68 = _prot_x_T_67 & _pmp_0_io_x; // @[tlb.scala:150:40, :159:22, :166:59] wire prot_x_0 = _prot_x_T_68; // @[tlb.scala:119:49, :166:59] wire newEntry_px = prot_x_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_eff_T_1 = {1'h0, _prot_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_2 = _prot_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_3 = _prot_eff_T_2; // @[Parameters.scala:137:46] wire _prot_eff_T_4 = _prot_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_6 = {1'h0, _prot_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_7 = _prot_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_8 = _prot_eff_T_7; // @[Parameters.scala:137:46] wire _prot_eff_T_9 = _prot_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_11 = {1'h0, _prot_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_12 = _prot_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_13 = _prot_eff_T_12; // @[Parameters.scala:137:46] wire _prot_eff_T_14 = _prot_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_16 = {1'h0, _prot_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_17 = _prot_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_18 = _prot_eff_T_17; // @[Parameters.scala:137:46] wire _prot_eff_T_19 = _prot_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_21 = {1'h0, _prot_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_22 = _prot_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_23 = _prot_eff_T_22; // @[Parameters.scala:137:46] wire _prot_eff_T_24 = _prot_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_26 = {1'h0, _prot_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_27 = _prot_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_28 = _prot_eff_T_27; // @[Parameters.scala:137:46] wire _prot_eff_T_29 = _prot_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_30 = _prot_eff_T_4 \| _prot_eff_T_9; // @[Parameters.scala:629:89] wire _prot_eff_T_31 = _prot_eff_T_30 \| _prot_eff_T_14; // @[Parameters.scala:629:89] wire _prot_eff_T_32 = _prot_eff_T_31 \| _prot_eff_T_19; // @[Parameters.scala:629:89] wire _prot_eff_T_33 = _prot_eff_T_32 \| _prot_eff_T_24; // @[Parameters.scala:629:89] wire _prot_eff_T_34 = _prot_eff_T_33 \| _prot_eff_T_29; // @[Parameters.scala:629:89] wire _prot_eff_T_58 = _prot_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _prot_eff_T_36 = {1'h0, _prot_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_37 = _prot_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_38 = _prot_eff_T_37; // @[Parameters.scala:137:46] wire _prot_eff_T_39 = _prot_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_41 = {1'h0, _prot_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_42 = _prot_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_43 = _prot_eff_T_42; // @[Parameters.scala:137:46] wire _prot_eff_T_44 = _prot_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_46 = {1'h0, _prot_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_47 = _prot_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_48 = _prot_eff_T_47; // @[Parameters.scala:137:46] wire _prot_eff_T_49 = _prot_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_51 = {1'h0, _prot_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_52 = _prot_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_53 = _prot_eff_T_52; // @[Parameters.scala:137:46] wire _prot_eff_T_54 = _prot_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_55 = _prot_eff_T_39 \| _prot_eff_T_44; // @[Parameters.scala:629:89] wire _prot_eff_T_56 = _prot_eff_T_55 \| _prot_eff_T_49; // @[Parameters.scala:629:89] wire _prot_eff_T_57 = _prot_eff_T_56 \| _prot_eff_T_54; // @[Parameters.scala:629:89] wire _prot_eff_T_60 = _prot_eff_T_58; // @[Mux.scala:30:73] wire _prot_eff_WIRE = _prot_eff_T_60; // @[Mux.scala:30:73] wire _prot_eff_T_61 = legal_address_0 & _prot_eff_WIRE; // @[Mux.scala:30:73] wire prot_eff_0 = _prot_eff_T_61; // @[tlb.scala:119:49, :159:22] wire newEntry_eff = prot_eff_0; // @[tlb.scala:119:49, :179:24] wire _GEN_11 = sectored_entries_0_valid_0 \| sectored_entries_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T \| sectored_entries_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 \| sectored_entries_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_41 = sectored_entries_0_tag ^ vpn_0; // @[tlb.scala:60:43, :119:49, :122:29] wire [26:0] _sector_hits_T_3; // @[tlb.scala:60:43] assign _sector_hits_T_3 = _T_41; // @[tlb.scala:60:43] wire [26:0] _hitsVec_T; // @[tlb.scala:60:43] assign _hitsVec_T = _T_41; // @[tlb.scala:60:43] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_6 = _sector_hits_T_2 & _sector_hits_T_5; // @[package.scala:81:59] wire _sector_hits_WIRE_0 = _sector_hits_T_6; // @[tlb.scala:59:42, :169:42] wire _GEN_12 = sectored_entries_1_valid_0 \| sectored_entries_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_7; // @[package.scala:81:59] assign _sector_hits_T_7 = _GEN_12; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_12; // @[package.scala:81:59] wire _sector_hits_T_8 = _sector_hits_T_7 \| sectored_entries_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 \| sectored_entries_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_172 = sectored_entries_1_tag ^ vpn_0; // @[tlb.scala:60:43, :119:49, :122:29] wire [26:0] _sector_hits_T_10; // @[tlb.scala:60:43] assign _sector_hits_T_10 = _T_172; // @[tlb.scala:60:43] wire [26:0] _hitsVec_T_5; // @[tlb.scala:60:43] assign _hitsVec_T_5 = _T_172; // @[tlb.scala:60:43] wire [24:0] _sector_hits_T_11 = _sector_hits_T_10[26:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_12 = _sector_hits_T_11 == 25'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_13 = _sector_hits_T_9 & _sector_hits_T_12; // @[package.scala:81:59] wire _sector_hits_WIRE_1 = _sector_hits_T_13; // @[tlb.scala:59:42, :169:42] wire sector_hits_0_0 = _sector_hits_WIRE_0; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_1 = _sector_hits_WIRE_1; // @[tlb.scala:119:49, :169:42] wire state_reg_touch_way_sized = sector_hits_0_1; // @[package.scala:163:13] wire [8:0] _superpage_hits_T = superpage_entries_0_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_10 = superpage_entries_0_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _superpage_hits_T_1 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_16 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_31 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_46 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_11 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_27 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_43 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_59 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_75 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire _superpage_hits_T_2 = _superpage_hits_T == _superpage_hits_T_1; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_4 = superpage_entries_0_valid_0 & _superpage_hits_T_3; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_13 = superpage_entries_0_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_1; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_1 = _GEN_13; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_1; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_1 = _GEN_13; // @[tlb.scala:66:30] wire _ppn_ignore_T; // @[tlb.scala:80:31] assign _ppn_ignore_T = _GEN_13; // @[tlb.scala:66:30, :80:31] wire _ignore_T_1; // @[tlb.scala:66:30] assign _ignore_T_1 = _GEN_13; // @[tlb.scala:66:30] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_5 = superpage_entries_0_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_15 = superpage_entries_0_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _superpage_hits_T_6 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_21 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_36 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_51 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_16 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_32 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_48 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_64 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_80 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire _superpage_hits_T_7 = _superpage_hits_T_5 == _superpage_hits_T_6; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_14 = _superpage_hits_T_9; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_10 = superpage_entries_0_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_20 = superpage_entries_0_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _superpage_hits_T_11 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_26 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_41 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_56 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_21 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_37 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_53 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_69 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_85 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire _superpage_hits_T_12 = _superpage_hits_T_10 == _superpage_hits_T_11; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_0 = _superpage_hits_T_14; // @[tlb.scala:67:31, :170:45] wire [8:0] _superpage_hits_T_15 = superpage_entries_1_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_26 = superpage_entries_1_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_17 = _superpage_hits_T_15 == _superpage_hits_T_16; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_18 = _superpage_hits_T_17; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_19 = superpage_entries_1_valid_0 & _superpage_hits_T_18; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_14 = superpage_entries_1_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_4; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_4 = _GEN_14; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_4; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_4 = _GEN_14; // @[tlb.scala:66:30] wire _ppn_ignore_T_2; // @[tlb.scala:80:31] assign _ppn_ignore_T_2 = _GEN_14; // @[tlb.scala:66:30, :80:31] wire _ignore_T_4; // @[tlb.scala:66:30] assign _ignore_T_4 = _GEN_14; // @[tlb.scala:66:30] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_20 = superpage_entries_1_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_31 = superpage_entries_1_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_22 = _superpage_hits_T_20 == _superpage_hits_T_21; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_23 = superpage_hits_ignore_4 \| _superpage_hits_T_22; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_24 = _superpage_hits_T_19 & _superpage_hits_T_23; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_29 = _superpage_hits_T_24; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_25 = superpage_entries_1_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_36 = superpage_entries_1_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_27 = _superpage_hits_T_25 == _superpage_hits_T_26; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_1 = _superpage_hits_T_29; // @[tlb.scala:67:31, :170:45] wire [8:0] _superpage_hits_T_30 = superpage_entries_2_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_42 = superpage_entries_2_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_32 = _superpage_hits_T_30 == _superpage_hits_T_31; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_33 = _superpage_hits_T_32; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_34 = superpage_entries_2_valid_0 & _superpage_hits_T_33; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_15 = superpage_entries_2_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_7; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_7 = _GEN_15; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_7; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_7 = _GEN_15; // @[tlb.scala:66:30] wire _ppn_ignore_T_4; // @[tlb.scala:80:31] assign _ppn_ignore_T_4 = _GEN_15; // @[tlb.scala:66:30, :80:31] wire _ignore_T_7; // @[tlb.scala:66:30] assign _ignore_T_7 = _GEN_15; // @[tlb.scala:66:30] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_35 = superpage_entries_2_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_47 = superpage_entries_2_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_37 = _superpage_hits_T_35 == _superpage_hits_T_36; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_38 = superpage_hits_ignore_7 \| _superpage_hits_T_37; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_39 = _superpage_hits_T_34 & _superpage_hits_T_38; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_44 = _superpage_hits_T_39; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_40 = superpage_entries_2_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_52 = superpage_entries_2_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_42 = _superpage_hits_T_40 == _superpage_hits_T_41; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_2 = _superpage_hits_T_44; // @[tlb.scala:67:31, :170:45] wire [8:0] _superpage_hits_T_45 = superpage_entries_3_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_58 = superpage_entries_3_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_47 = _superpage_hits_T_45 == _superpage_hits_T_46; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_48 = _superpage_hits_T_47; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_49 = superpage_entries_3_valid_0 & _superpage_hits_T_48; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_16 = superpage_entries_3_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_10; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_10 = _GEN_16; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_10; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_10 = _GEN_16; // @[tlb.scala:66:30] wire _ppn_ignore_T_6; // @[tlb.scala:80:31] assign _ppn_ignore_T_6 = _GEN_16; // @[tlb.scala:66:30, :80:31] wire _ignore_T_10; // @[tlb.scala:66:30] assign _ignore_T_10 = _GEN_16; // @[tlb.scala:66:30] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_50 = superpage_entries_3_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_63 = superpage_entries_3_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_52 = _superpage_hits_T_50 == _superpage_hits_T_51; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_53 = superpage_hits_ignore_10 \| _superpage_hits_T_52; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_54 = _superpage_hits_T_49 & _superpage_hits_T_53; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_59 = _superpage_hits_T_54; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_55 = superpage_entries_3_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_68 = superpage_entries_3_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_57 = _superpage_hits_T_55 == _superpage_hits_T_56; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_3 = _superpage_hits_T_59; // @[tlb.scala:67:31, :170:45] wire superpage_hits_0_0 = _superpage_hits_WIRE_0; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_1 = _superpage_hits_WIRE_1; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_2 = _superpage_hits_WIRE_2; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_3 = _superpage_hits_WIRE_3; // @[tlb.scala:119:49, :170:45] wire [1:0] hitsVec_idx = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[tlb.scala:60:{50,73}] wire [3:0] _GEN_17 = {{sectored_entries_0_valid_3}, {sectored_entries_0_valid_2}, {sectored_entries_0_valid_1}, {sectored_entries_0_valid_0}}; // @[tlb.scala:72:20, :122:29] wire _hitsVec_T_3 = _GEN_17[hitsVec_idx] & _hitsVec_T_2; // @[package.scala:163:13] wire _hitsVec_T_4 = vm_enabled_0 & _hitsVec_T_3; // @[tlb.scala:72:20, :119:49, :171:69] wire _hitsVec_WIRE_0 = _hitsVec_T_4; // @[tlb.scala:171:{38,69}] wire [24:0] _hitsVec_T_6 = _hitsVec_T_5[26:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_7 = _hitsVec_T_6 == 25'h0; // @[tlb.scala:60:{50,73}] wire [3:0] _GEN_18 = {{sectored_entries_1_valid_3}, {sectored_entries_1_valid_2}, {sectored_entries_1_valid_1}, {sectored_entries_1_valid_0}}; // @[tlb.scala:72:20, :122:29] wire _hitsVec_T_8 = _GEN_18[hitsVec_idx_1] & _hitsVec_T_7; // @[package.scala:163:13] wire _hitsVec_T_9 = vm_enabled_0 & _hitsVec_T_8; // @[tlb.scala:72:20, :119:49, :171:69] wire _hitsVec_WIRE_1 = _hitsVec_T_9; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_12 = _hitsVec_T_10 == _hitsVec_T_11; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_13 = _hitsVec_T_12; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_14 = superpage_entries_0_valid_0 & _hitsVec_T_13; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_17 = _hitsVec_T_15 == _hitsVec_T_16; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_18 = hitsVec_ignore_1 \| _hitsVec_T_17; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_19 = _hitsVec_T_14 & _hitsVec_T_18; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_24 = _hitsVec_T_19; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_22 = _hitsVec_T_20 == _hitsVec_T_21; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_25 = vm_enabled_0 & _hitsVec_T_24; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_2 = _hitsVec_T_25; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_28 = _hitsVec_T_26 == _hitsVec_T_27; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_29 = _hitsVec_T_28; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_30 = superpage_entries_1_valid_0 & _hitsVec_T_29; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_33 = _hitsVec_T_31 == _hitsVec_T_32; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_34 = hitsVec_ignore_4 \| _hitsVec_T_33; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_35 = _hitsVec_T_30 & _hitsVec_T_34; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_40 = _hitsVec_T_35; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_38 = _hitsVec_T_36 == _hitsVec_T_37; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_41 = vm_enabled_0 & _hitsVec_T_40; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_3 = _hitsVec_T_41; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_44 = _hitsVec_T_42 == _hitsVec_T_43; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_45 = _hitsVec_T_44; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_46 = superpage_entries_2_valid_0 & _hitsVec_T_45; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_49 = _hitsVec_T_47 == _hitsVec_T_48; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_50 = hitsVec_ignore_7 \| _hitsVec_T_49; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_51 = _hitsVec_T_46 & _hitsVec_T_50; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_56 = _hitsVec_T_51; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_54 = _hitsVec_T_52 == _hitsVec_T_53; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_57 = vm_enabled_0 & _hitsVec_T_56; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_4 = _hitsVec_T_57; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_60 = _hitsVec_T_58 == _hitsVec_T_59; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_61 = _hitsVec_T_60; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_62 = superpage_entries_3_valid_0 & _hitsVec_T_61; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_65 = _hitsVec_T_63 == _hitsVec_T_64; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_66 = hitsVec_ignore_10 \| _hitsVec_T_65; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_67 = _hitsVec_T_62 & _hitsVec_T_66; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_72 = _hitsVec_T_67; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_70 = _hitsVec_T_68 == _hitsVec_T_69; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_73 = vm_enabled_0 & _hitsVec_T_72; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_5 = _hitsVec_T_73; // @[tlb.scala:171:{38,69}] wire [8:0] _hitsVec_T_74 = special_entry_tag[26:18]; // @[tlb.scala:67:48, :124:56] wire _hitsVec_T_76 = _hitsVec_T_74 == _hitsVec_T_75; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_77 = _hitsVec_T_76; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_78 = special_entry_valid_0 & _hitsVec_T_77; // @[tlb.scala:67:{31,42}, :124:56] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[tlb.scala:66:{30,36}] wire [8:0] _hitsVec_T_79 = special_entry_tag[17:9]; // @[tlb.scala:67:48, :124:56] wire _hitsVec_T_81 = _hitsVec_T_79 == _hitsVec_T_80; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_82 = hitsVec_ignore_13 \| _hitsVec_T_81; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_83 = _hitsVec_T_78 & _hitsVec_T_82; // @[tlb.scala:67:{31,42}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[tlb.scala:66:30, :80:31, :124:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[tlb.scala:66:{30,36}] wire [8:0] _hitsVec_T_84 = special_entry_tag[8:0]; // @[tlb.scala:67:48, :124:56] wire _hitsVec_T_86 = _hitsVec_T_84 == _hitsVec_T_85; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_87 = hitsVec_ignore_14 \| _hitsVec_T_86; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_88 = _hitsVec_T_83 & _hitsVec_T_87; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_89 = vm_enabled_0 & _hitsVec_T_88; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_6 = _hitsVec_T_89; // @[tlb.scala:171:{38,69}] wire hitsVec_0_0 = _hitsVec_WIRE_0; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_1 = _hitsVec_WIRE_1; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_2 = _hitsVec_WIRE_2; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_3 = _hitsVec_WIRE_3; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_4 = _hitsVec_WIRE_4; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_5 = _hitsVec_WIRE_5; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_6 = _hitsVec_WIRE_6; // @[tlb.scala:119:49, :171:38] wire [1:0] real_hits_lo_hi = {hitsVec_0_2, hitsVec_0_1}; // @[tlb.scala:119:49, :172:44] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0_0}; // @[tlb.scala:119:49, :172:44] wire [1:0] real_hits_hi_lo = {hitsVec_0_4, hitsVec_0_3}; // @[tlb.scala:119:49, :172:44] wire [1:0] real_hits_hi_hi = {hitsVec_0_6, hitsVec_0_5}; // @[tlb.scala:119:49, :172:44] wire [3:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[tlb.scala:172:44] wire [6:0] _real_hits_T = {real_hits_hi, real_hits_lo}; // @[tlb.scala:172:44] wire [6:0] real_hits_0 = _real_hits_T; // @[tlb.scala:119:49, :172:44] wire _hits_T = ~vm_enabled_0; // @[tlb.scala:119:49, :173:32] wire [7:0] _hits_T_1 = {_hits_T, real_hits_0}; // @[tlb.scala:119:49, :173:{31,32}] wire [7:0] hits_0 = _hits_T_1; // @[tlb.scala:119:49, :173:31] wire _ppn_T = ~vm_enabled_0; // @[tlb.scala:119:49, :173:32, :174:47] wire [19:0] _ppn_data_T_15; // @[tlb.scala:58:79] wire _ppn_data_T_14; // @[tlb.scala:58:79] wire _ppn_data_T_13; // @[tlb.scala:58:79] wire _ppn_data_T_12; // @[tlb.scala:58:79] wire _ppn_data_T_11; // @[tlb.scala:58:79] wire _ppn_data_T_10; // @[tlb.scala:58:79] wire _ppn_data_T_9; // @[tlb.scala:58:79] wire _ppn_data_T_8; // @[tlb.scala:58:79] wire _ppn_data_T_7; // @[tlb.scala:58:79] wire _ppn_data_T_6; // @[tlb.scala:58:79] wire _ppn_data_T_5; // @[tlb.scala:58:79] wire _ppn_data_T_4; // @[tlb.scala:58:79] wire _ppn_data_T_3; // @[tlb.scala:58:79] wire _ppn_data_T_2; // @[tlb.scala:58:79] wire _ppn_data_T_1; // @[tlb.scala:58:79] wire [3:0][33:0] _GEN_19 = {{sectored_entries_0_data_3}, {sectored_entries_0_data_2}, {sectored_entries_0_data_1}, {sectored_entries_0_data_0}}; // @[tlb.scala:58:79, :122:29] wire [33:0] _ppn_data_WIRE_1 = _GEN_19[_ppn_data_T]; // @[package.scala:163:13] assign _ppn_data_T_1 = _ppn_data_WIRE_1[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_fragmented_superpage = _ppn_data_T_1; // @[tlb.scala:58:79] assign _ppn_data_T_2 = _ppn_data_WIRE_1[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_c = _ppn_data_T_2; // @[tlb.scala:58:79] assign _ppn_data_T_3 = _ppn_data_WIRE_1[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_eff = _ppn_data_T_3; // @[tlb.scala:58:79] assign _ppn_data_T_4 = _ppn_data_WIRE_1[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_paa = _ppn_data_T_4; // @[tlb.scala:58:79] assign _ppn_data_T_5 = _ppn_data_WIRE_1[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pal = _ppn_data_T_5; // @[tlb.scala:58:79] assign _ppn_data_T_6 = _ppn_data_WIRE_1[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pr = _ppn_data_T_6; // @[tlb.scala:58:79] assign _ppn_data_T_7 = _ppn_data_WIRE_1[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_px = _ppn_data_T_7; // @[tlb.scala:58:79] assign _ppn_data_T_8 = _ppn_data_WIRE_1[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pw = _ppn_data_T_8; // @[tlb.scala:58:79] assign _ppn_data_T_9 = _ppn_data_WIRE_1[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sr = _ppn_data_T_9; // @[tlb.scala:58:79] assign _ppn_data_T_10 = _ppn_data_WIRE_1[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sx = _ppn_data_T_10; // @[tlb.scala:58:79] assign _ppn_data_T_11 = _ppn_data_WIRE_1[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sw = _ppn_data_T_11; // @[tlb.scala:58:79] assign _ppn_data_T_12 = _ppn_data_WIRE_1[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_ae = _ppn_data_T_12; // @[tlb.scala:58:79] assign _ppn_data_T_13 = _ppn_data_WIRE_1[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_g = _ppn_data_T_13; // @[tlb.scala:58:79] assign _ppn_data_T_14 = _ppn_data_WIRE_1[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_u = _ppn_data_T_14; // @[tlb.scala:58:79] assign _ppn_data_T_15 = _ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_ppn = _ppn_data_T_15; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_31; // @[tlb.scala:58:79] wire _ppn_data_T_30; // @[tlb.scala:58:79] wire _ppn_data_T_29; // @[tlb.scala:58:79] wire _ppn_data_T_28; // @[tlb.scala:58:79] wire _ppn_data_T_27; // @[tlb.scala:58:79] wire _ppn_data_T_26; // @[tlb.scala:58:79] wire _ppn_data_T_25; // @[tlb.scala:58:79] wire _ppn_data_T_24; // @[tlb.scala:58:79] wire _ppn_data_T_23; // @[tlb.scala:58:79] wire _ppn_data_T_22; // @[tlb.scala:58:79] wire _ppn_data_T_21; // @[tlb.scala:58:79] wire _ppn_data_T_20; // @[tlb.scala:58:79] wire _ppn_data_T_19; // @[tlb.scala:58:79] wire _ppn_data_T_18; // @[tlb.scala:58:79] wire _ppn_data_T_17; // @[tlb.scala:58:79] wire [3:0][33:0] _GEN_20 = {{sectored_entries_1_data_3}, {sectored_entries_1_data_2}, {sectored_entries_1_data_1}, {sectored_entries_1_data_0}}; // @[tlb.scala:58:79, :122:29] wire [33:0] _ppn_data_WIRE_3 = _GEN_20[_ppn_data_T_16]; // @[package.scala:163:13] assign _ppn_data_T_17 = _ppn_data_WIRE_3[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_fragmented_superpage = _ppn_data_T_17; // @[tlb.scala:58:79] assign _ppn_data_T_18 = _ppn_data_WIRE_3[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_c = _ppn_data_T_18; // @[tlb.scala:58:79] assign _ppn_data_T_19 = _ppn_data_WIRE_3[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_eff = _ppn_data_T_19; // @[tlb.scala:58:79] assign _ppn_data_T_20 = _ppn_data_WIRE_3[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_paa = _ppn_data_T_20; // @[tlb.scala:58:79] assign _ppn_data_T_21 = _ppn_data_WIRE_3[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pal = _ppn_data_T_21; // @[tlb.scala:58:79] assign _ppn_data_T_22 = _ppn_data_WIRE_3[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pr = _ppn_data_T_22; // @[tlb.scala:58:79] assign _ppn_data_T_23 = _ppn_data_WIRE_3[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_px = _ppn_data_T_23; // @[tlb.scala:58:79] assign _ppn_data_T_24 = _ppn_data_WIRE_3[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pw = _ppn_data_T_24; // @[tlb.scala:58:79] assign _ppn_data_T_25 = _ppn_data_WIRE_3[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sr = _ppn_data_T_25; // @[tlb.scala:58:79] assign _ppn_data_T_26 = _ppn_data_WIRE_3[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sx = _ppn_data_T_26; // @[tlb.scala:58:79] assign _ppn_data_T_27 = _ppn_data_WIRE_3[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sw = _ppn_data_T_27; // @[tlb.scala:58:79] assign _ppn_data_T_28 = _ppn_data_WIRE_3[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_ae = _ppn_data_T_28; // @[tlb.scala:58:79] assign _ppn_data_T_29 = _ppn_data_WIRE_3[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_g = _ppn_data_T_29; // @[tlb.scala:58:79] assign _ppn_data_T_30 = _ppn_data_WIRE_3[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_u = _ppn_data_T_30; // @[tlb.scala:58:79] assign _ppn_data_T_31 = _ppn_data_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_2_ppn = _ppn_data_T_31; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_46; // @[tlb.scala:58:79] wire _ppn_data_T_45; // @[tlb.scala:58:79] wire _ppn_data_T_44; // @[tlb.scala:58:79] wire _ppn_data_T_43; // @[tlb.scala:58:79] wire _ppn_data_T_42; // @[tlb.scala:58:79] wire _ppn_data_T_41; // @[tlb.scala:58:79] wire _ppn_data_T_40; // @[tlb.scala:58:79] wire _ppn_data_T_39; // @[tlb.scala:58:79] wire _ppn_data_T_38; // @[tlb.scala:58:79] wire _ppn_data_T_37; // @[tlb.scala:58:79] wire _ppn_data_T_36; // @[tlb.scala:58:79] wire _ppn_data_T_35; // @[tlb.scala:58:79] wire _ppn_data_T_34; // @[tlb.scala:58:79] wire _ppn_data_T_33; // @[tlb.scala:58:79] wire _ppn_data_T_32; // @[tlb.scala:58:79] assign _ppn_data_T_32 = _ppn_data_WIRE_5[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_fragmented_superpage = _ppn_data_T_32; // @[tlb.scala:58:79] assign _ppn_data_T_33 = _ppn_data_WIRE_5[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_c = _ppn_data_T_33; // @[tlb.scala:58:79] assign _ppn_data_T_34 = _ppn_data_WIRE_5[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_eff = _ppn_data_T_34; // @[tlb.scala:58:79] assign _ppn_data_T_35 = _ppn_data_WIRE_5[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_paa = _ppn_data_T_35; // @[tlb.scala:58:79] assign _ppn_data_T_36 = _ppn_data_WIRE_5[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pal = _ppn_data_T_36; // @[tlb.scala:58:79] assign _ppn_data_T_37 = _ppn_data_WIRE_5[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pr = _ppn_data_T_37; // @[tlb.scala:58:79] assign _ppn_data_T_38 = _ppn_data_WIRE_5[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_px = _ppn_data_T_38; // @[tlb.scala:58:79] assign _ppn_data_T_39 = _ppn_data_WIRE_5[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pw = _ppn_data_T_39; // @[tlb.scala:58:79] assign _ppn_data_T_40 = _ppn_data_WIRE_5[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sr = _ppn_data_T_40; // @[tlb.scala:58:79] assign _ppn_data_T_41 = _ppn_data_WIRE_5[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sx = _ppn_data_T_41; // @[tlb.scala:58:79] assign _ppn_data_T_42 = _ppn_data_WIRE_5[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sw = _ppn_data_T_42; // @[tlb.scala:58:79] assign _ppn_data_T_43 = _ppn_data_WIRE_5[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_ae = _ppn_data_T_43; // @[tlb.scala:58:79] assign _ppn_data_T_44 = _ppn_data_WIRE_5[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_g = _ppn_data_T_44; // @[tlb.scala:58:79] assign _ppn_data_T_45 = _ppn_data_WIRE_5[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_u = _ppn_data_T_45; // @[tlb.scala:58:79] assign _ppn_data_T_46 = _ppn_data_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_4_ppn = _ppn_data_T_46; // @[tlb.scala:58:79] wire [1:0] ppn_res = _ppn_data_barrier_2_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _ppn_data_barrier_2_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _ppn_data_barrier_2_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_61; // @[tlb.scala:58:79] wire _ppn_data_T_60; // @[tlb.scala:58:79] wire _ppn_data_T_59; // @[tlb.scala:58:79] wire _ppn_data_T_58; // @[tlb.scala:58:79] wire _ppn_data_T_57; // @[tlb.scala:58:79] wire _ppn_data_T_56; // @[tlb.scala:58:79] wire _ppn_data_T_55; // @[tlb.scala:58:79] wire _ppn_data_T_54; // @[tlb.scala:58:79] wire _ppn_data_T_53; // @[tlb.scala:58:79] wire _ppn_data_T_52; // @[tlb.scala:58:79] wire _ppn_data_T_51; // @[tlb.scala:58:79] wire _ppn_data_T_50; // @[tlb.scala:58:79] wire _ppn_data_T_49; // @[tlb.scala:58:79] wire _ppn_data_T_48; // @[tlb.scala:58:79] wire _ppn_data_T_47; // @[tlb.scala:58:79] assign _ppn_data_T_47 = _ppn_data_WIRE_7[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_fragmented_superpage = _ppn_data_T_47; // @[tlb.scala:58:79] assign _ppn_data_T_48 = _ppn_data_WIRE_7[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_c = _ppn_data_T_48; // @[tlb.scala:58:79] assign _ppn_data_T_49 = _ppn_data_WIRE_7[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_eff = _ppn_data_T_49; // @[tlb.scala:58:79] assign _ppn_data_T_50 = _ppn_data_WIRE_7[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_paa = _ppn_data_T_50; // @[tlb.scala:58:79] assign _ppn_data_T_51 = _ppn_data_WIRE_7[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pal = _ppn_data_T_51; // @[tlb.scala:58:79] assign _ppn_data_T_52 = _ppn_data_WIRE_7[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pr = _ppn_data_T_52; // @[tlb.scala:58:79] assign _ppn_data_T_53 = _ppn_data_WIRE_7[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_px = _ppn_data_T_53; // @[tlb.scala:58:79] assign _ppn_data_T_54 = _ppn_data_WIRE_7[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pw = _ppn_data_T_54; // @[tlb.scala:58:79] assign _ppn_data_T_55 = _ppn_data_WIRE_7[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sr = _ppn_data_T_55; // @[tlb.scala:58:79] assign _ppn_data_T_56 = _ppn_data_WIRE_7[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sx = _ppn_data_T_56; // @[tlb.scala:58:79] assign _ppn_data_T_57 = _ppn_data_WIRE_7[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sw = _ppn_data_T_57; // @[tlb.scala:58:79] assign _ppn_data_T_58 = _ppn_data_WIRE_7[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_ae = _ppn_data_T_58; // @[tlb.scala:58:79] assign _ppn_data_T_59 = _ppn_data_WIRE_7[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_g = _ppn_data_T_59; // @[tlb.scala:58:79] assign _ppn_data_T_60 = _ppn_data_WIRE_7[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_u = _ppn_data_T_60; // @[tlb.scala:58:79] assign _ppn_data_T_61 = _ppn_data_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_6_ppn = _ppn_data_T_61; // @[tlb.scala:58:79] wire [1:0] ppn_res_1 = _ppn_data_barrier_3_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _ppn_data_barrier_3_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _ppn_data_barrier_3_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_76; // @[tlb.scala:58:79] wire _ppn_data_T_75; // @[tlb.scala:58:79] wire _ppn_data_T_74; // @[tlb.scala:58:79] wire _ppn_data_T_73; // @[tlb.scala:58:79] wire _ppn_data_T_72; // @[tlb.scala:58:79] wire _ppn_data_T_71; // @[tlb.scala:58:79] wire _ppn_data_T_70; // @[tlb.scala:58:79] wire _ppn_data_T_69; // @[tlb.scala:58:79] wire _ppn_data_T_68; // @[tlb.scala:58:79] wire _ppn_data_T_67; // @[tlb.scala:58:79] wire _ppn_data_T_66; // @[tlb.scala:58:79] wire _ppn_data_T_65; // @[tlb.scala:58:79] wire _ppn_data_T_64; // @[tlb.scala:58:79] wire _ppn_data_T_63; // @[tlb.scala:58:79] wire _ppn_data_T_62; // @[tlb.scala:58:79] assign _ppn_data_T_62 = _ppn_data_WIRE_9[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_fragmented_superpage = _ppn_data_T_62; // @[tlb.scala:58:79] assign _ppn_data_T_63 = _ppn_data_WIRE_9[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_c = _ppn_data_T_63; // @[tlb.scala:58:79] assign _ppn_data_T_64 = _ppn_data_WIRE_9[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_eff = _ppn_data_T_64; // @[tlb.scala:58:79] assign _ppn_data_T_65 = _ppn_data_WIRE_9[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_paa = _ppn_data_T_65; // @[tlb.scala:58:79] assign _ppn_data_T_66 = _ppn_data_WIRE_9[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pal = _ppn_data_T_66; // @[tlb.scala:58:79] assign _ppn_data_T_67 = _ppn_data_WIRE_9[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pr = _ppn_data_T_67; // @[tlb.scala:58:79] assign _ppn_data_T_68 = _ppn_data_WIRE_9[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_px = _ppn_data_T_68; // @[tlb.scala:58:79] assign _ppn_data_T_69 = _ppn_data_WIRE_9[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pw = _ppn_data_T_69; // @[tlb.scala:58:79] assign _ppn_data_T_70 = _ppn_data_WIRE_9[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sr = _ppn_data_T_70; // @[tlb.scala:58:79] assign _ppn_data_T_71 = _ppn_data_WIRE_9[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sx = _ppn_data_T_71; // @[tlb.scala:58:79] assign _ppn_data_T_72 = _ppn_data_WIRE_9[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sw = _ppn_data_T_72; // @[tlb.scala:58:79] assign _ppn_data_T_73 = _ppn_data_WIRE_9[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_ae = _ppn_data_T_73; // @[tlb.scala:58:79] assign _ppn_data_T_74 = _ppn_data_WIRE_9[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_g = _ppn_data_T_74; // @[tlb.scala:58:79] assign _ppn_data_T_75 = _ppn_data_WIRE_9[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_u = _ppn_data_T_75; // @[tlb.scala:58:79] assign _ppn_data_T_76 = _ppn_data_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_8_ppn = _ppn_data_T_76; // @[tlb.scala:58:79] wire [1:0] ppn_res_2 = _ppn_data_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] \| _ppn_data_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] \| _ppn_data_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_91; // @[tlb.scala:58:79] wire _ppn_data_T_90; // @[tlb.scala:58:79] wire _ppn_data_T_89; // @[tlb.scala:58:79] wire _ppn_data_T_88; // @[tlb.scala:58:79] wire _ppn_data_T_87; // @[tlb.scala:58:79] wire _ppn_data_T_86; // @[tlb.scala:58:79] wire _ppn_data_T_85; // @[tlb.scala:58:79] wire _ppn_data_T_84; // @[tlb.scala:58:79] wire _ppn_data_T_83; // @[tlb.scala:58:79] wire _ppn_data_T_82; // @[tlb.scala:58:79] wire _ppn_data_T_81; // @[tlb.scala:58:79] wire _ppn_data_T_80; // @[tlb.scala:58:79] wire _ppn_data_T_79; // @[tlb.scala:58:79] wire _ppn_data_T_78; // @[tlb.scala:58:79] wire _ppn_data_T_77; // @[tlb.scala:58:79] assign _ppn_data_T_77 = _ppn_data_WIRE_11[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_fragmented_superpage = _ppn_data_T_77; // @[tlb.scala:58:79] assign _ppn_data_T_78 = _ppn_data_WIRE_11[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_c = _ppn_data_T_78; // @[tlb.scala:58:79] assign _ppn_data_T_79 = _ppn_data_WIRE_11[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_eff = _ppn_data_T_79; // @[tlb.scala:58:79] assign _ppn_data_T_80 = _ppn_data_WIRE_11[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_paa = _ppn_data_T_80; // @[tlb.scala:58:79] assign _ppn_data_T_81 = _ppn_data_WIRE_11[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pal = _ppn_data_T_81; // @[tlb.scala:58:79] assign _ppn_data_T_82 = _ppn_data_WIRE_11[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pr = _ppn_data_T_82; // @[tlb.scala:58:79] assign _ppn_data_T_83 = _ppn_data_WIRE_11[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_px = _ppn_data_T_83; // @[tlb.scala:58:79] assign _ppn_data_T_84 = _ppn_data_WIRE_11[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pw = _ppn_data_T_84; // @[tlb.scala:58:79] assign _ppn_data_T_85 = _ppn_data_WIRE_11[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sr = _ppn_data_T_85; // @[tlb.scala:58:79] assign _ppn_data_T_86 = _ppn_data_WIRE_11[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sx = _ppn_data_T_86; // @[tlb.scala:58:79] assign _ppn_data_T_87 = _ppn_data_WIRE_11[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sw = _ppn_data_T_87; // @[tlb.scala:58:79] assign _ppn_data_T_88 = _ppn_data_WIRE_11[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_ae = _ppn_data_T_88; // @[tlb.scala:58:79] assign _ppn_data_T_89 = _ppn_data_WIRE_11[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_g = _ppn_data_T_89; // @[tlb.scala:58:79] assign _ppn_data_T_90 = _ppn_data_WIRE_11[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_u = _ppn_data_T_90; // @[tlb.scala:58:79] assign _ppn_data_T_91 = _ppn_data_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_10_ppn = _ppn_data_T_91; // @[tlb.scala:58:79] wire [1:0] ppn_res_3 = _ppn_data_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] \| _ppn_data_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] \| _ppn_data_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_106; // @[tlb.scala:58:79] wire _ppn_data_T_105; // @[tlb.scala:58:79] wire _ppn_data_T_104; // @[tlb.scala:58:79] wire _ppn_data_T_103; // @[tlb.scala:58:79] wire _ppn_data_T_102; // @[tlb.scala:58:79] wire _ppn_data_T_101; // @[tlb.scala:58:79] wire _ppn_data_T_100; // @[tlb.scala:58:79] wire _ppn_data_T_99; // @[tlb.scala:58:79] wire _ppn_data_T_98; // @[tlb.scala:58:79] wire _ppn_data_T_97; // @[tlb.scala:58:79] wire _ppn_data_T_96; // @[tlb.scala:58:79] wire _ppn_data_T_95; // @[tlb.scala:58:79] wire _ppn_data_T_94; // @[tlb.scala:58:79] wire _ppn_data_T_93; // @[tlb.scala:58:79] wire _ppn_data_T_92; // @[tlb.scala:58:79] assign _ppn_data_T_92 = _ppn_data_WIRE_13[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_fragmented_superpage = _ppn_data_T_92; // @[tlb.scala:58:79] assign _ppn_data_T_93 = _ppn_data_WIRE_13[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_c = _ppn_data_T_93; // @[tlb.scala:58:79] assign _ppn_data_T_94 = _ppn_data_WIRE_13[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_eff = _ppn_data_T_94; // @[tlb.scala:58:79] assign _ppn_data_T_95 = _ppn_data_WIRE_13[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_paa = _ppn_data_T_95; // @[tlb.scala:58:79] assign _ppn_data_T_96 = _ppn_data_WIRE_13[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pal = _ppn_data_T_96; // @[tlb.scala:58:79] assign _ppn_data_T_97 = _ppn_data_WIRE_13[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pr = _ppn_data_T_97; // @[tlb.scala:58:79] assign _ppn_data_T_98 = _ppn_data_WIRE_13[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_px = _ppn_data_T_98; // @[tlb.scala:58:79] assign _ppn_data_T_99 = _ppn_data_WIRE_13[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pw = _ppn_data_T_99; // @[tlb.scala:58:79] assign _ppn_data_T_100 = _ppn_data_WIRE_13[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sr = _ppn_data_T_100; // @[tlb.scala:58:79] assign _ppn_data_T_101 = _ppn_data_WIRE_13[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sx = _ppn_data_T_101; // @[tlb.scala:58:79] assign _ppn_data_T_102 = _ppn_data_WIRE_13[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sw = _ppn_data_T_102; // @[tlb.scala:58:79] assign _ppn_data_T_103 = _ppn_data_WIRE_13[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_ae = _ppn_data_T_103; // @[tlb.scala:58:79] assign _ppn_data_T_104 = _ppn_data_WIRE_13[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_g = _ppn_data_T_104; // @[tlb.scala:58:79] assign _ppn_data_T_105 = _ppn_data_WIRE_13[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_u = _ppn_data_T_105; // @[tlb.scala:58:79] assign _ppn_data_T_106 = _ppn_data_WIRE_13[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_12_ppn = _ppn_data_T_106; // @[tlb.scala:58:79] wire [1:0] ppn_res_4 = _ppn_data_barrier_6_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] \| _ppn_data_barrier_6_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[tlb.scala:80:31, :124:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] \| _ppn_data_barrier_6_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_T_41 = vpn_0[19:0]; // @[tlb.scala:119:49, :174:103] wire [19:0] _ppn_T_42 = hitsVec_0_0 ? _ppn_data_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_0_1 ? _ppn_data_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_0_2 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_0_3 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_0_4 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_0_5 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_0_6 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = _ppn_T_42 \| _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = _ppn_T_50 \| _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = _ppn_T_51 \| _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = _ppn_T_52 \| _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = _ppn_T_53 \| _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T_54 \| _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_55 \| _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_WIRE = _ppn_T_56; // @[Mux.scala:30:73] wire [19:0] ppn_0 = _ppn_WIRE; // @[Mux.scala:30:73] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_sw; // @[tlb.scala:179:24] wire newEntry_sx; // @[tlb.scala:179:24] wire newEntry_sr; // @[tlb.scala:179:24] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:47] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[PTW.scala:141:{44,47}] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[PTW.scala:141:{38,44}] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[PTW.scala:141:{32,38}] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[PTW.scala:141:{32,52}] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[PTW.scala:141:52, :149:35] assign newEntry_sr = _newEntry_sr_T_5; // @[PTW.scala:149:35] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:47] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[PTW.scala:141:{44,47}] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[PTW.scala:141:{38,44}] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[PTW.scala:141:{32,38}] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[PTW.scala:141:{32,52}] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:52, :151:35] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[PTW.scala:151:{35,40}] assign newEntry_sw = _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:47] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[PTW.scala:141:{44,47}] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[PTW.scala:141:{38,44}] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[PTW.scala:141:{32,38}] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[PTW.scala:141:{32,52}] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[PTW.scala:141:52, :153:35] assign newEntry_sx = _newEntry_sx_T_5; // @[PTW.scala:153:35] wire [1:0] _GEN_21 = {newEntry_eff, newEntry_c}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign special_entry_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [2:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [1:0] _GEN_22 = {newEntry_pal, newEntry_paa}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign special_entry_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] _GEN_23 = {newEntry_px, newEntry_pr}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign special_entry_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [3:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[tlb.scala:95:26] wire [1:0] _GEN_24 = {newEntry_sr, newEntry_pw}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign special_entry_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] _GEN_25 = {newEntry_sw, newEntry_sx}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign special_entry_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [3:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [1:0] _GEN_26 = {newEntry_g, newEntry_ae}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign special_entry_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [20:0] _GEN_27 = {newEntry_ppn, newEntry_u}; // @[tlb.scala:95:26, :179:24] wire [20:0] special_entry_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign special_entry_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_0_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_1_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_2_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_3_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] sectored_entries_0_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] sectored_entries_1_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [22:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[tlb.scala:95:26] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[tlb.scala:95:26] wire waddr = r_sectored_hit ? r_sectored_hit_addr : r_sectored_repl_addr; // @[tlb.scala:132:33, :133:32, :134:27, :203:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_data_lo_lo = {sectored_entries_0_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_0_data_lo_hi = {sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_0_data_lo = {sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_0_data_hi_lo = {sectored_entries_0_data_hi_lo_hi, sectored_entries_0_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_0_data_hi_hi = {sectored_entries_0_data_hi_hi_hi, sectored_entries_0_data_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_0_data_hi = {sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_0_data_T = {sectored_entries_0_data_hi, sectored_entries_0_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_1_data_lo_lo = {sectored_entries_1_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_1_data_lo_hi = {sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_1_data_lo = {sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_1_data_hi_lo = {sectored_entries_1_data_hi_lo_hi, sectored_entries_1_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_1_data_hi_hi = {sectored_entries_1_data_hi_hi_hi, sectored_entries_1_data_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_1_data_hi = {sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_1_data_T = {sectored_entries_1_data_hi, sectored_entries_1_data_lo}; // @[tlb.scala:95:26] wire [19:0] _entries_T_15; // @[tlb.scala:58:79] wire _entries_T_14; // @[tlb.scala:58:79] wire _entries_T_13; // @[tlb.scala:58:79] wire _entries_T_12; // @[tlb.scala:58:79] wire _entries_T_11; // @[tlb.scala:58:79] wire _entries_T_10; // @[tlb.scala:58:79] wire _entries_T_9; // @[tlb.scala:58:79] wire _entries_T_8; // @[tlb.scala:58:79] wire _entries_T_7; // @[tlb.scala:58:79] wire _entries_T_6; // @[tlb.scala:58:79] wire _entries_T_5; // @[tlb.scala:58:79] wire _entries_T_4; // @[tlb.scala:58:79] wire _entries_T_3; // @[tlb.scala:58:79] wire _entries_T_2; // @[tlb.scala:58:79] wire _entries_T_1; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_1 = _GEN_19[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[tlb.scala:58:79] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[tlb.scala:58:79] assign _entries_T_2 = _entries_WIRE_1[1]; // @[tlb.scala:58:79] wire _entries_WIRE_c = _entries_T_2; // @[tlb.scala:58:79] assign _entries_T_3 = _entries_WIRE_1[2]; // @[tlb.scala:58:79] wire _entries_WIRE_eff = _entries_T_3; // @[tlb.scala:58:79] assign _entries_T_4 = _entries_WIRE_1[3]; // @[tlb.scala:58:79] wire _entries_WIRE_paa = _entries_T_4; // @[tlb.scala:58:79] assign _entries_T_5 = _entries_WIRE_1[4]; // @[tlb.scala:58:79] wire _entries_WIRE_pal = _entries_T_5; // @[tlb.scala:58:79] assign _entries_T_6 = _entries_WIRE_1[5]; // @[tlb.scala:58:79] wire _entries_WIRE_pr = _entries_T_6; // @[tlb.scala:58:79] assign _entries_T_7 = _entries_WIRE_1[6]; // @[tlb.scala:58:79] wire _entries_WIRE_px = _entries_T_7; // @[tlb.scala:58:79] assign _entries_T_8 = _entries_WIRE_1[7]; // @[tlb.scala:58:79] wire _entries_WIRE_pw = _entries_T_8; // @[tlb.scala:58:79] assign _entries_T_9 = _entries_WIRE_1[8]; // @[tlb.scala:58:79] wire _entries_WIRE_sr = _entries_T_9; // @[tlb.scala:58:79] assign _entries_T_10 = _entries_WIRE_1[9]; // @[tlb.scala:58:79] wire _entries_WIRE_sx = _entries_T_10; // @[tlb.scala:58:79] assign _entries_T_11 = _entries_WIRE_1[10]; // @[tlb.scala:58:79] wire _entries_WIRE_sw = _entries_T_11; // @[tlb.scala:58:79] assign _entries_T_12 = _entries_WIRE_1[11]; // @[tlb.scala:58:79] wire _entries_WIRE_ae = _entries_T_12; // @[tlb.scala:58:79] assign _entries_T_13 = _entries_WIRE_1[12]; // @[tlb.scala:58:79] wire _entries_WIRE_g = _entries_T_13; // @[tlb.scala:58:79] assign _entries_T_14 = _entries_WIRE_1[13]; // @[tlb.scala:58:79] wire _entries_WIRE_u = _entries_T_14; // @[tlb.scala:58:79] assign _entries_T_15 = _entries_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_ppn = _entries_T_15; // @[tlb.scala:58:79] wire [19:0] _entries_T_31; // @[tlb.scala:58:79] wire _entries_T_30; // @[tlb.scala:58:79] wire _entries_T_29; // @[tlb.scala:58:79] wire _entries_T_28; // @[tlb.scala:58:79] wire _entries_T_27; // @[tlb.scala:58:79] wire _entries_T_26; // @[tlb.scala:58:79] wire _entries_T_25; // @[tlb.scala:58:79] wire _entries_T_24; // @[tlb.scala:58:79] wire _entries_T_23; // @[tlb.scala:58:79] wire _entries_T_22; // @[tlb.scala:58:79] wire _entries_T_21; // @[tlb.scala:58:79] wire _entries_T_20; // @[tlb.scala:58:79] wire _entries_T_19; // @[tlb.scala:58:79] wire _entries_T_18; // @[tlb.scala:58:79] wire _entries_T_17; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_3 = _GEN_20[_entries_T_16]; // @[package.scala:163:13] assign _entries_T_17 = _entries_WIRE_3[0]; // @[tlb.scala:58:79] wire _entries_WIRE_2_fragmented_superpage = _entries_T_17; // @[tlb.scala:58:79] assign _entries_T_18 = _entries_WIRE_3[1]; // @[tlb.scala:58:79] wire _entries_WIRE_2_c = _entries_T_18; // @[tlb.scala:58:79] assign _entries_T_19 = _entries_WIRE_3[2]; // @[tlb.scala:58:79] wire _entries_WIRE_2_eff = _entries_T_19; // @[tlb.scala:58:79] assign _entries_T_20 = _entries_WIRE_3[3]; // @[tlb.scala:58:79] wire _entries_WIRE_2_paa = _entries_T_20; // @[tlb.scala:58:79] assign _entries_T_21 = _entries_WIRE_3[4]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pal = _entries_T_21; // @[tlb.scala:58:79] assign _entries_T_22 = _entries_WIRE_3[5]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pr = _entries_T_22; // @[tlb.scala:58:79] assign _entries_T_23 = _entries_WIRE_3[6]; // @[tlb.scala:58:79] wire _entries_WIRE_2_px = _entries_T_23; // @[tlb.scala:58:79] assign _entries_T_24 = _entries_WIRE_3[7]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pw = _entries_T_24; // @[tlb.scala:58:79] assign _entries_T_25 = _entries_WIRE_3[8]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sr = _entries_T_25; // @[tlb.scala:58:79] assign _entries_T_26 = _entries_WIRE_3[9]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sx = _entries_T_26; // @[tlb.scala:58:79] assign _entries_T_27 = _entries_WIRE_3[10]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sw = _entries_T_27; // @[tlb.scala:58:79] assign _entries_T_28 = _entries_WIRE_3[11]; // @[tlb.scala:58:79] wire _entries_WIRE_2_ae = _entries_T_28; // @[tlb.scala:58:79] assign _entries_T_29 = _entries_WIRE_3[12]; // @[tlb.scala:58:79] wire _entries_WIRE_2_g = _entries_T_29; // @[tlb.scala:58:79] assign _entries_T_30 = _entries_WIRE_3[13]; // @[tlb.scala:58:79] wire _entries_WIRE_2_u = _entries_T_30; // @[tlb.scala:58:79] assign _entries_T_31 = _entries_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_2_ppn = _entries_T_31; // @[tlb.scala:58:79] wire [19:0] _entries_T_46; // @[tlb.scala:58:79] wire _entries_T_45; // @[tlb.scala:58:79] wire _entries_T_44; // @[tlb.scala:58:79] wire _entries_T_43; // @[tlb.scala:58:79] wire _entries_T_42; // @[tlb.scala:58:79] wire _entries_T_41; // @[tlb.scala:58:79] wire _entries_T_40; // @[tlb.scala:58:79] wire _entries_T_39; // @[tlb.scala:58:79] wire _entries_T_38; // @[tlb.scala:58:79] wire _entries_T_37; // @[tlb.scala:58:79] wire _entries_T_36; // @[tlb.scala:58:79] wire _entries_T_35; // @[tlb.scala:58:79] wire _entries_T_34; // @[tlb.scala:58:79] wire _entries_T_33; // @[tlb.scala:58:79] wire _entries_T_32; // @[tlb.scala:58:79] assign _entries_T_32 = _entries_WIRE_5[0]; // @[tlb.scala:58:79] wire _entries_WIRE_4_fragmented_superpage = _entries_T_32; // @[tlb.scala:58:79] assign _entries_T_33 = _entries_WIRE_5[1]; // @[tlb.scala:58:79] wire _entries_WIRE_4_c = _entries_T_33; // @[tlb.scala:58:79] assign _entries_T_34 = _entries_WIRE_5[2]; // @[tlb.scala:58:79] wire _entries_WIRE_4_eff = _entries_T_34; // @[tlb.scala:58:79] assign _entries_T_35 = _entries_WIRE_5[3]; // @[tlb.scala:58:79] wire _entries_WIRE_4_paa = _entries_T_35; // @[tlb.scala:58:79] assign _entries_T_36 = _entries_WIRE_5[4]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pal = _entries_T_36; // @[tlb.scala:58:79] assign _entries_T_37 = _entries_WIRE_5[5]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pr = _entries_T_37; // @[tlb.scala:58:79] assign _entries_T_38 = _entries_WIRE_5[6]; // @[tlb.scala:58:79] wire _entries_WIRE_4_px = _entries_T_38; // @[tlb.scala:58:79] assign _entries_T_39 = _entries_WIRE_5[7]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pw = _entries_T_39; // @[tlb.scala:58:79] assign _entries_T_40 = _entries_WIRE_5[8]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sr = _entries_T_40; // @[tlb.scala:58:79] assign _entries_T_41 = _entries_WIRE_5[9]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sx = _entries_T_41; // @[tlb.scala:58:79] assign _entries_T_42 = _entries_WIRE_5[10]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sw = _entries_T_42; // @[tlb.scala:58:79] assign _entries_T_43 = _entries_WIRE_5[11]; // @[tlb.scala:58:79] wire _entries_WIRE_4_ae = _entries_T_43; // @[tlb.scala:58:79] assign _entries_T_44 = _entries_WIRE_5[12]; // @[tlb.scala:58:79] wire _entries_WIRE_4_g = _entries_T_44; // @[tlb.scala:58:79] assign _entries_T_45 = _entries_WIRE_5[13]; // @[tlb.scala:58:79] wire _entries_WIRE_4_u = _entries_T_45; // @[tlb.scala:58:79] assign _entries_T_46 = _entries_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_4_ppn = _entries_T_46; // @[tlb.scala:58:79] wire [19:0] _entries_T_61; // @[tlb.scala:58:79] wire _entries_T_60; // @[tlb.scala:58:79] wire _entries_T_59; // @[tlb.scala:58:79] wire _entries_T_58; // @[tlb.scala:58:79] wire _entries_T_57; // @[tlb.scala:58:79] wire _entries_T_56; // @[tlb.scala:58:79] wire _entries_T_55; // @[tlb.scala:58:79] wire _entries_T_54; // @[tlb.scala:58:79] wire _entries_T_53; // @[tlb.scala:58:79] wire _entries_T_52; // @[tlb.scala:58:79] wire _entries_T_51; // @[tlb.scala:58:79] wire _entries_T_50; // @[tlb.scala:58:79] wire _entries_T_49; // @[tlb.scala:58:79] wire _entries_T_48; // @[tlb.scala:58:79] wire _entries_T_47; // @[tlb.scala:58:79] assign _entries_T_47 = _entries_WIRE_7[0]; // @[tlb.scala:58:79] wire _entries_WIRE_6_fragmented_superpage = _entries_T_47; // @[tlb.scala:58:79] assign _entries_T_48 = _entries_WIRE_7[1]; // @[tlb.scala:58:79] wire _entries_WIRE_6_c = _entries_T_48; // @[tlb.scala:58:79] assign _entries_T_49 = _entries_WIRE_7[2]; // @[tlb.scala:58:79] wire _entries_WIRE_6_eff = _entries_T_49; // @[tlb.scala:58:79] assign _entries_T_50 = _entries_WIRE_7[3]; // @[tlb.scala:58:79] wire _entries_WIRE_6_paa = _entries_T_50; // @[tlb.scala:58:79] assign _entries_T_51 = _entries_WIRE_7[4]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pal = _entries_T_51; // @[tlb.scala:58:79] assign _entries_T_52 = _entries_WIRE_7[5]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pr = _entries_T_52; // @[tlb.scala:58:79] assign _entries_T_53 = _entries_WIRE_7[6]; // @[tlb.scala:58:79] wire _entries_WIRE_6_px = _entries_T_53; // @[tlb.scala:58:79] assign _entries_T_54 = _entries_WIRE_7[7]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pw = _entries_T_54; // @[tlb.scala:58:79] assign _entries_T_55 = _entries_WIRE_7[8]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sr = _entries_T_55; // @[tlb.scala:58:79] assign _entries_T_56 = _entries_WIRE_7[9]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sx = _entries_T_56; // @[tlb.scala:58:79] assign _entries_T_57 = _entries_WIRE_7[10]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sw = _entries_T_57; // @[tlb.scala:58:79] assign _entries_T_58 = _entries_WIRE_7[11]; // @[tlb.scala:58:79] wire _entries_WIRE_6_ae = _entries_T_58; // @[tlb.scala:58:79] assign _entries_T_59 = _entries_WIRE_7[12]; // @[tlb.scala:58:79] wire _entries_WIRE_6_g = _entries_T_59; // @[tlb.scala:58:79] assign _entries_T_60 = _entries_WIRE_7[13]; // @[tlb.scala:58:79] wire _entries_WIRE_6_u = _entries_T_60; // @[tlb.scala:58:79] assign _entries_T_61 = _entries_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_6_ppn = _entries_T_61; // @[tlb.scala:58:79] wire [19:0] _entries_T_76; // @[tlb.scala:58:79] wire _entries_T_75; // @[tlb.scala:58:79] wire _entries_T_74; // @[tlb.scala:58:79] wire _entries_T_73; // @[tlb.scala:58:79] wire _entries_T_72; // @[tlb.scala:58:79] wire _entries_T_71; // @[tlb.scala:58:79] wire _entries_T_70; // @[tlb.scala:58:79] wire _entries_T_69; // @[tlb.scala:58:79] wire _entries_T_68; // @[tlb.scala:58:79] wire _entries_T_67; // @[tlb.scala:58:79] wire _entries_T_66; // @[tlb.scala:58:79] wire _entries_T_65; // @[tlb.scala:58:79] wire _entries_T_64; // @[tlb.scala:58:79] wire _entries_T_63; // @[tlb.scala:58:79] wire _entries_T_62; // @[tlb.scala:58:79] assign _entries_T_62 = _entries_WIRE_9[0]; // @[tlb.scala:58:79] wire _entries_WIRE_8_fragmented_superpage = _entries_T_62; // @[tlb.scala:58:79] assign _entries_T_63 = _entries_WIRE_9[1]; // @[tlb.scala:58:79] wire _entries_WIRE_8_c = _entries_T_63; // @[tlb.scala:58:79] assign _entries_T_64 = _entries_WIRE_9[2]; // @[tlb.scala:58:79] wire _entries_WIRE_8_eff = _entries_T_64; // @[tlb.scala:58:79] assign _entries_T_65 = _entries_WIRE_9[3]; // @[tlb.scala:58:79] wire _entries_WIRE_8_paa = _entries_T_65; // @[tlb.scala:58:79] assign _entries_T_66 = _entries_WIRE_9[4]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pal = _entries_T_66; // @[tlb.scala:58:79] assign _entries_T_67 = _entries_WIRE_9[5]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pr = _entries_T_67; // @[tlb.scala:58:79] assign _entries_T_68 = _entries_WIRE_9[6]; // @[tlb.scala:58:79] wire _entries_WIRE_8_px = _entries_T_68; // @[tlb.scala:58:79] assign _entries_T_69 = _entries_WIRE_9[7]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pw = _entries_T_69; // @[tlb.scala:58:79] assign _entries_T_70 = _entries_WIRE_9[8]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sr = _entries_T_70; // @[tlb.scala:58:79] assign _entries_T_71 = _entries_WIRE_9[9]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sx = _entries_T_71; // @[tlb.scala:58:79] assign _entries_T_72 = _entries_WIRE_9[10]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sw = _entries_T_72; // @[tlb.scala:58:79] assign _entries_T_73 = _entries_WIRE_9[11]; // @[tlb.scala:58:79] wire _entries_WIRE_8_ae = _entries_T_73; // @[tlb.scala:58:79] assign _entries_T_74 = _entries_WIRE_9[12]; // @[tlb.scala:58:79] wire _entries_WIRE_8_g = _entries_T_74; // @[tlb.scala:58:79] assign _entries_T_75 = _entries_WIRE_9[13]; // @[tlb.scala:58:79] wire _entries_WIRE_8_u = _entries_T_75; // @[tlb.scala:58:79] assign _entries_T_76 = _entries_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_8_ppn = _entries_T_76; // @[tlb.scala:58:79] wire [19:0] _entries_T_91; // @[tlb.scala:58:79] wire _entries_T_90; // @[tlb.scala:58:79] wire _entries_T_89; // @[tlb.scala:58:79] wire _entries_T_88; // @[tlb.scala:58:79] wire _entries_T_87; // @[tlb.scala:58:79] wire _entries_T_86; // @[tlb.scala:58:79] wire _entries_T_85; // @[tlb.scala:58:79] wire _entries_T_84; // @[tlb.scala:58:79] wire _entries_T_83; // @[tlb.scala:58:79] wire _entries_T_82; // @[tlb.scala:58:79] wire _entries_T_81; // @[tlb.scala:58:79] wire _entries_T_80; // @[tlb.scala:58:79] wire _entries_T_79; // @[tlb.scala:58:79] wire _entries_T_78; // @[tlb.scala:58:79] wire _entries_T_77; // @[tlb.scala:58:79] assign _entries_T_77 = _entries_WIRE_11[0]; // @[tlb.scala:58:79] wire _entries_WIRE_10_fragmented_superpage = _entries_T_77; // @[tlb.scala:58:79] assign _entries_T_78 = _entries_WIRE_11[1]; // @[tlb.scala:58:79] wire _entries_WIRE_10_c = _entries_T_78; // @[tlb.scala:58:79] assign _entries_T_79 = _entries_WIRE_11[2]; // @[tlb.scala:58:79] wire _entries_WIRE_10_eff = _entries_T_79; // @[tlb.scala:58:79] assign _entries_T_80 = _entries_WIRE_11[3]; // @[tlb.scala:58:79] wire _entries_WIRE_10_paa = _entries_T_80; // @[tlb.scala:58:79] assign _entries_T_81 = _entries_WIRE_11[4]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pal = _entries_T_81; // @[tlb.scala:58:79] assign _entries_T_82 = _entries_WIRE_11[5]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pr = _entries_T_82; // @[tlb.scala:58:79] assign _entries_T_83 = _entries_WIRE_11[6]; // @[tlb.scala:58:79] wire _entries_WIRE_10_px = _entries_T_83; // @[tlb.scala:58:79] assign _entries_T_84 = _entries_WIRE_11[7]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pw = _entries_T_84; // @[tlb.scala:58:79] assign _entries_T_85 = _entries_WIRE_11[8]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sr = _entries_T_85; // @[tlb.scala:58:79] assign _entries_T_86 = _entries_WIRE_11[9]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sx = _entries_T_86; // @[tlb.scala:58:79] assign _entries_T_87 = _entries_WIRE_11[10]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sw = _entries_T_87; // @[tlb.scala:58:79] assign _entries_T_88 = _entries_WIRE_11[11]; // @[tlb.scala:58:79] wire _entries_WIRE_10_ae = _entries_T_88; // @[tlb.scala:58:79] assign _entries_T_89 = _entries_WIRE_11[12]; // @[tlb.scala:58:79] wire _entries_WIRE_10_g = _entries_T_89; // @[tlb.scala:58:79] assign _entries_T_90 = _entries_WIRE_11[13]; // @[tlb.scala:58:79] wire _entries_WIRE_10_u = _entries_T_90; // @[tlb.scala:58:79] assign _entries_T_91 = _entries_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_10_ppn = _entries_T_91; // @[tlb.scala:58:79] wire [19:0] _entries_T_106; // @[tlb.scala:58:79] wire _entries_T_105; // @[tlb.scala:58:79] wire _entries_T_104; // @[tlb.scala:58:79] wire _entries_T_103; // @[tlb.scala:58:79] wire _entries_T_102; // @[tlb.scala:58:79] wire _entries_T_101; // @[tlb.scala:58:79] wire _entries_T_100; // @[tlb.scala:58:79] wire _entries_T_99; // @[tlb.scala:58:79] wire _entries_T_98; // @[tlb.scala:58:79] wire _entries_T_97; // @[tlb.scala:58:79] wire _entries_T_96; // @[tlb.scala:58:79] wire _entries_T_95; // @[tlb.scala:58:79] wire _entries_T_94; // @[tlb.scala:58:79] wire _entries_T_93; // @[tlb.scala:58:79] wire _entries_T_92; // @[tlb.scala:58:79] assign _entries_T_92 = _entries_WIRE_13[0]; // @[tlb.scala:58:79] wire _entries_WIRE_12_fragmented_superpage = _entries_T_92; // @[tlb.scala:58:79] assign _entries_T_93 = _entries_WIRE_13[1]; // @[tlb.scala:58:79] wire _entries_WIRE_12_c = _entries_T_93; // @[tlb.scala:58:79] assign _entries_T_94 = _entries_WIRE_13[2]; // @[tlb.scala:58:79] wire _entries_WIRE_12_eff = _entries_T_94; // @[tlb.scala:58:79] assign _entries_T_95 = _entries_WIRE_13[3]; // @[tlb.scala:58:79] wire _entries_WIRE_12_paa = _entries_T_95; // @[tlb.scala:58:79] assign _entries_T_96 = _entries_WIRE_13[4]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pal = _entries_T_96; // @[tlb.scala:58:79] assign _entries_T_97 = _entries_WIRE_13[5]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pr = _entries_T_97; // @[tlb.scala:58:79] assign _entries_T_98 = _entries_WIRE_13[6]; // @[tlb.scala:58:79] wire _entries_WIRE_12_px = _entries_T_98; // @[tlb.scala:58:79] assign _entries_T_99 = _entries_WIRE_13[7]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pw = _entries_T_99; // @[tlb.scala:58:79] assign _entries_T_100 = _entries_WIRE_13[8]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sr = _entries_T_100; // @[tlb.scala:58:79] assign _entries_T_101 = _entries_WIRE_13[9]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sx = _entries_T_101; // @[tlb.scala:58:79] assign _entries_T_102 = _entries_WIRE_13[10]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sw = _entries_T_102; // @[tlb.scala:58:79] assign _entries_T_103 = _entries_WIRE_13[11]; // @[tlb.scala:58:79] wire _entries_WIRE_12_ae = _entries_T_103; // @[tlb.scala:58:79] assign _entries_T_104 = _entries_WIRE_13[12]; // @[tlb.scala:58:79] wire _entries_WIRE_12_g = _entries_T_104; // @[tlb.scala:58:79] assign _entries_T_105 = _entries_WIRE_13[13]; // @[tlb.scala:58:79] wire _entries_WIRE_12_u = _entries_T_105; // @[tlb.scala:58:79] assign _entries_T_106 = _entries_WIRE_13[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_12_ppn = _entries_T_106; // @[tlb.scala:58:79] wire [19:0] entries_0_0_ppn = _entries_WIRE_14_0_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_0_u = _entries_WIRE_14_0_u; // @[tlb.scala:119:49, :211:38] wire entries_0_0_g = _entries_WIRE_14_0_g; // @[tlb.scala:119:49, :211:38] wire entries_0_0_ae = _entries_WIRE_14_0_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sw = _entries_WIRE_14_0_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sx = _entries_WIRE_14_0_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sr = _entries_WIRE_14_0_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pw = _entries_WIRE_14_0_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_0_px = _entries_WIRE_14_0_px; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pr = _entries_WIRE_14_0_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pal = _entries_WIRE_14_0_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_0_paa = _entries_WIRE_14_0_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_0_eff = _entries_WIRE_14_0_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_0_c = _entries_WIRE_14_0_c; // @[tlb.scala:119:49, :211:38] wire entries_0_0_fragmented_superpage = _entries_WIRE_14_0_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_1_ppn = _entries_WIRE_14_1_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_1_u = _entries_WIRE_14_1_u; // @[tlb.scala:119:49, :211:38] wire entries_0_1_g = _entries_WIRE_14_1_g; // @[tlb.scala:119:49, :211:38] wire entries_0_1_ae = _entries_WIRE_14_1_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sw = _entries_WIRE_14_1_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sx = _entries_WIRE_14_1_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sr = _entries_WIRE_14_1_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pw = _entries_WIRE_14_1_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_1_px = _entries_WIRE_14_1_px; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pr = _entries_WIRE_14_1_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pal = _entries_WIRE_14_1_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_1_paa = _entries_WIRE_14_1_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_1_eff = _entries_WIRE_14_1_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_1_c = _entries_WIRE_14_1_c; // @[tlb.scala:119:49, :211:38] wire entries_0_1_fragmented_superpage = _entries_WIRE_14_1_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_2_ppn = _entries_WIRE_14_2_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_2_u = _entries_WIRE_14_2_u; // @[tlb.scala:119:49, :211:38] wire entries_0_2_g = _entries_WIRE_14_2_g; // @[tlb.scala:119:49, :211:38] wire entries_0_2_ae = _entries_WIRE_14_2_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sw = _entries_WIRE_14_2_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sx = _entries_WIRE_14_2_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sr = _entries_WIRE_14_2_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pw = _entries_WIRE_14_2_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_2_px = _entries_WIRE_14_2_px; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pr = _entries_WIRE_14_2_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pal = _entries_WIRE_14_2_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_2_paa = _entries_WIRE_14_2_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_2_eff = _entries_WIRE_14_2_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_2_c = _entries_WIRE_14_2_c; // @[tlb.scala:119:49, :211:38] wire entries_0_2_fragmented_superpage = _entries_WIRE_14_2_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_3_ppn = _entries_WIRE_14_3_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_3_u = _entries_WIRE_14_3_u; // @[tlb.scala:119:49, :211:38] wire entries_0_3_g = _entries_WIRE_14_3_g; // @[tlb.scala:119:49, :211:38] wire entries_0_3_ae = _entries_WIRE_14_3_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sw = _entries_WIRE_14_3_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sx = _entries_WIRE_14_3_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sr = _entries_WIRE_14_3_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pw = _entries_WIRE_14_3_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_3_px = _entries_WIRE_14_3_px; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pr = _entries_WIRE_14_3_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pal = _entries_WIRE_14_3_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_3_paa = _entries_WIRE_14_3_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_3_eff = _entries_WIRE_14_3_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_3_c = _entries_WIRE_14_3_c; // @[tlb.scala:119:49, :211:38] wire entries_0_3_fragmented_superpage = _entries_WIRE_14_3_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_4_ppn = _entries_WIRE_14_4_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_4_u = _entries_WIRE_14_4_u; // @[tlb.scala:119:49, :211:38] wire entries_0_4_g = _entries_WIRE_14_4_g; // @[tlb.scala:119:49, :211:38] wire entries_0_4_ae = _entries_WIRE_14_4_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sw = _entries_WIRE_14_4_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sx = _entries_WIRE_14_4_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sr = _entries_WIRE_14_4_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pw = _entries_WIRE_14_4_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_4_px = _entries_WIRE_14_4_px; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pr = _entries_WIRE_14_4_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pal = _entries_WIRE_14_4_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_4_paa = _entries_WIRE_14_4_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_4_eff = _entries_WIRE_14_4_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_4_c = _entries_WIRE_14_4_c; // @[tlb.scala:119:49, :211:38] wire entries_0_4_fragmented_superpage = _entries_WIRE_14_4_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_5_ppn = _entries_WIRE_14_5_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_5_u = _entries_WIRE_14_5_u; // @[tlb.scala:119:49, :211:38] wire entries_0_5_g = _entries_WIRE_14_5_g; // @[tlb.scala:119:49, :211:38] wire entries_0_5_ae = _entries_WIRE_14_5_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sw = _entries_WIRE_14_5_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sx = _entries_WIRE_14_5_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sr = _entries_WIRE_14_5_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pw = _entries_WIRE_14_5_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_5_px = _entries_WIRE_14_5_px; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pr = _entries_WIRE_14_5_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pal = _entries_WIRE_14_5_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_5_paa = _entries_WIRE_14_5_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_5_eff = _entries_WIRE_14_5_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_5_c = _entries_WIRE_14_5_c; // @[tlb.scala:119:49, :211:38] wire entries_0_5_fragmented_superpage = _entries_WIRE_14_5_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_6_ppn = _entries_WIRE_14_6_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_6_u = _entries_WIRE_14_6_u; // @[tlb.scala:119:49, :211:38] wire entries_0_6_g = _entries_WIRE_14_6_g; // @[tlb.scala:119:49, :211:38] wire entries_0_6_ae = _entries_WIRE_14_6_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sw = _entries_WIRE_14_6_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sx = _entries_WIRE_14_6_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sr = _entries_WIRE_14_6_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pw = _entries_WIRE_14_6_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_6_px = _entries_WIRE_14_6_px; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pr = _entries_WIRE_14_6_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pal = _entries_WIRE_14_6_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_6_paa = _entries_WIRE_14_6_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_6_eff = _entries_WIRE_14_6_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_6_c = _entries_WIRE_14_6_c; // @[tlb.scala:119:49, :211:38] wire entries_0_6_fragmented_superpage = _entries_WIRE_14_6_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] _normal_entries_T_15; // @[tlb.scala:58:79] wire _normal_entries_T_14; // @[tlb.scala:58:79] wire _normal_entries_T_13; // @[tlb.scala:58:79] wire _normal_entries_T_12; // @[tlb.scala:58:79] wire _normal_entries_T_11; // @[tlb.scala:58:79] wire _normal_entries_T_10; // @[tlb.scala:58:79] wire _normal_entries_T_9; // @[tlb.scala:58:79] wire _normal_entries_T_8; // @[tlb.scala:58:79] wire _normal_entries_T_7; // @[tlb.scala:58:79] wire _normal_entries_T_6; // @[tlb.scala:58:79] wire _normal_entries_T_5; // @[tlb.scala:58:79] wire _normal_entries_T_4; // @[tlb.scala:58:79] wire _normal_entries_T_3; // @[tlb.scala:58:79] wire _normal_entries_T_2; // @[tlb.scala:58:79] wire _normal_entries_T_1; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_1 = _GEN_19[_normal_entries_T]; // @[package.scala:163:13] assign _normal_entries_T_1 = _normal_entries_WIRE_1[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_fragmented_superpage = _normal_entries_T_1; // @[tlb.scala:58:79] assign _normal_entries_T_2 = _normal_entries_WIRE_1[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_c = _normal_entries_T_2; // @[tlb.scala:58:79] assign _normal_entries_T_3 = _normal_entries_WIRE_1[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_eff = _normal_entries_T_3; // @[tlb.scala:58:79] assign _normal_entries_T_4 = _normal_entries_WIRE_1[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_paa = _normal_entries_T_4; // @[tlb.scala:58:79] assign _normal_entries_T_5 = _normal_entries_WIRE_1[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pal = _normal_entries_T_5; // @[tlb.scala:58:79] assign _normal_entries_T_6 = _normal_entries_WIRE_1[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pr = _normal_entries_T_6; // @[tlb.scala:58:79] assign _normal_entries_T_7 = _normal_entries_WIRE_1[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_px = _normal_entries_T_7; // @[tlb.scala:58:79] assign _normal_entries_T_8 = _normal_entries_WIRE_1[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pw = _normal_entries_T_8; // @[tlb.scala:58:79] assign _normal_entries_T_9 = _normal_entries_WIRE_1[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sr = _normal_entries_T_9; // @[tlb.scala:58:79] assign _normal_entries_T_10 = _normal_entries_WIRE_1[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sx = _normal_entries_T_10; // @[tlb.scala:58:79] assign _normal_entries_T_11 = _normal_entries_WIRE_1[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sw = _normal_entries_T_11; // @[tlb.scala:58:79] assign _normal_entries_T_12 = _normal_entries_WIRE_1[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_ae = _normal_entries_T_12; // @[tlb.scala:58:79] assign _normal_entries_T_13 = _normal_entries_WIRE_1[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_g = _normal_entries_T_13; // @[tlb.scala:58:79] assign _normal_entries_T_14 = _normal_entries_WIRE_1[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_u = _normal_entries_T_14; // @[tlb.scala:58:79] assign _normal_entries_T_15 = _normal_entries_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_ppn = _normal_entries_T_15; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_31; // @[tlb.scala:58:79] wire _normal_entries_T_30; // @[tlb.scala:58:79] wire _normal_entries_T_29; // @[tlb.scala:58:79] wire _normal_entries_T_28; // @[tlb.scala:58:79] wire _normal_entries_T_27; // @[tlb.scala:58:79] wire _normal_entries_T_26; // @[tlb.scala:58:79] wire _normal_entries_T_25; // @[tlb.scala:58:79] wire _normal_entries_T_24; // @[tlb.scala:58:79] wire _normal_entries_T_23; // @[tlb.scala:58:79] wire _normal_entries_T_22; // @[tlb.scala:58:79] wire _normal_entries_T_21; // @[tlb.scala:58:79] wire _normal_entries_T_20; // @[tlb.scala:58:79] wire _normal_entries_T_19; // @[tlb.scala:58:79] wire _normal_entries_T_18; // @[tlb.scala:58:79] wire _normal_entries_T_17; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_3 = _GEN_20[_normal_entries_T_16]; // @[package.scala:163:13] assign _normal_entries_T_17 = _normal_entries_WIRE_3[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_fragmented_superpage = _normal_entries_T_17; // @[tlb.scala:58:79] assign _normal_entries_T_18 = _normal_entries_WIRE_3[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_c = _normal_entries_T_18; // @[tlb.scala:58:79] assign _normal_entries_T_19 = _normal_entries_WIRE_3[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_eff = _normal_entries_T_19; // @[tlb.scala:58:79] assign _normal_entries_T_20 = _normal_entries_WIRE_3[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_paa = _normal_entries_T_20; // @[tlb.scala:58:79] assign _normal_entries_T_21 = _normal_entries_WIRE_3[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pal = _normal_entries_T_21; // @[tlb.scala:58:79] assign _normal_entries_T_22 = _normal_entries_WIRE_3[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pr = _normal_entries_T_22; // @[tlb.scala:58:79] assign _normal_entries_T_23 = _normal_entries_WIRE_3[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_px = _normal_entries_T_23; // @[tlb.scala:58:79] assign _normal_entries_T_24 = _normal_entries_WIRE_3[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pw = _normal_entries_T_24; // @[tlb.scala:58:79] assign _normal_entries_T_25 = _normal_entries_WIRE_3[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sr = _normal_entries_T_25; // @[tlb.scala:58:79] assign _normal_entries_T_26 = _normal_entries_WIRE_3[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sx = _normal_entries_T_26; // @[tlb.scala:58:79] assign _normal_entries_T_27 = _normal_entries_WIRE_3[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sw = _normal_entries_T_27; // @[tlb.scala:58:79] assign _normal_entries_T_28 = _normal_entries_WIRE_3[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_ae = _normal_entries_T_28; // @[tlb.scala:58:79] assign _normal_entries_T_29 = _normal_entries_WIRE_3[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_g = _normal_entries_T_29; // @[tlb.scala:58:79] assign _normal_entries_T_30 = _normal_entries_WIRE_3[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_u = _normal_entries_T_30; // @[tlb.scala:58:79] assign _normal_entries_T_31 = _normal_entries_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_2_ppn = _normal_entries_T_31; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_46; // @[tlb.scala:58:79] wire _normal_entries_T_45; // @[tlb.scala:58:79] wire _normal_entries_T_44; // @[tlb.scala:58:79] wire _normal_entries_T_43; // @[tlb.scala:58:79] wire _normal_entries_T_42; // @[tlb.scala:58:79] wire _normal_entries_T_41; // @[tlb.scala:58:79] wire _normal_entries_T_40; // @[tlb.scala:58:79] wire _normal_entries_T_39; // @[tlb.scala:58:79] wire _normal_entries_T_38; // @[tlb.scala:58:79] wire _normal_entries_T_37; // @[tlb.scala:58:79] wire _normal_entries_T_36; // @[tlb.scala:58:79] wire _normal_entries_T_35; // @[tlb.scala:58:79] wire _normal_entries_T_34; // @[tlb.scala:58:79] wire _normal_entries_T_33; // @[tlb.scala:58:79] wire _normal_entries_T_32; // @[tlb.scala:58:79] assign _normal_entries_T_32 = _normal_entries_WIRE_5[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_fragmented_superpage = _normal_entries_T_32; // @[tlb.scala:58:79] assign _normal_entries_T_33 = _normal_entries_WIRE_5[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_c = _normal_entries_T_33; // @[tlb.scala:58:79] assign _normal_entries_T_34 = _normal_entries_WIRE_5[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_eff = _normal_entries_T_34; // @[tlb.scala:58:79] assign _normal_entries_T_35 = _normal_entries_WIRE_5[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_paa = _normal_entries_T_35; // @[tlb.scala:58:79] assign _normal_entries_T_36 = _normal_entries_WIRE_5[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pal = _normal_entries_T_36; // @[tlb.scala:58:79] assign _normal_entries_T_37 = _normal_entries_WIRE_5[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pr = _normal_entries_T_37; // @[tlb.scala:58:79] assign _normal_entries_T_38 = _normal_entries_WIRE_5[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_px = _normal_entries_T_38; // @[tlb.scala:58:79] assign _normal_entries_T_39 = _normal_entries_WIRE_5[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pw = _normal_entries_T_39; // @[tlb.scala:58:79] assign _normal_entries_T_40 = _normal_entries_WIRE_5[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sr = _normal_entries_T_40; // @[tlb.scala:58:79] assign _normal_entries_T_41 = _normal_entries_WIRE_5[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sx = _normal_entries_T_41; // @[tlb.scala:58:79] assign _normal_entries_T_42 = _normal_entries_WIRE_5[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sw = _normal_entries_T_42; // @[tlb.scala:58:79] assign _normal_entries_T_43 = _normal_entries_WIRE_5[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_ae = _normal_entries_T_43; // @[tlb.scala:58:79] assign _normal_entries_T_44 = _normal_entries_WIRE_5[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_g = _normal_entries_T_44; // @[tlb.scala:58:79] assign _normal_entries_T_45 = _normal_entries_WIRE_5[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_u = _normal_entries_T_45; // @[tlb.scala:58:79] assign _normal_entries_T_46 = _normal_entries_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_4_ppn = _normal_entries_T_46; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_61; // @[tlb.scala:58:79] wire _normal_entries_T_60; // @[tlb.scala:58:79] wire _normal_entries_T_59; // @[tlb.scala:58:79] wire _normal_entries_T_58; // @[tlb.scala:58:79] wire _normal_entries_T_57; // @[tlb.scala:58:79] wire _normal_entries_T_56; // @[tlb.scala:58:79] wire _normal_entries_T_55; // @[tlb.scala:58:79] wire _normal_entries_T_54; // @[tlb.scala:58:79] wire _normal_entries_T_53; // @[tlb.scala:58:79] wire _normal_entries_T_52; // @[tlb.scala:58:79] wire _normal_entries_T_51; // @[tlb.scala:58:79] wire _normal_entries_T_50; // @[tlb.scala:58:79] wire _normal_entries_T_49; // @[tlb.scala:58:79] wire _normal_entries_T_48; // @[tlb.scala:58:79] wire _normal_entries_T_47; // @[tlb.scala:58:79] assign _normal_entries_T_47 = _normal_entries_WIRE_7[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_fragmented_superpage = _normal_entries_T_47; // @[tlb.scala:58:79] assign _normal_entries_T_48 = _normal_entries_WIRE_7[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_c = _normal_entries_T_48; // @[tlb.scala:58:79] assign _normal_entries_T_49 = _normal_entries_WIRE_7[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_eff = _normal_entries_T_49; // @[tlb.scala:58:79] assign _normal_entries_T_50 = _normal_entries_WIRE_7[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_paa = _normal_entries_T_50; // @[tlb.scala:58:79] assign _normal_entries_T_51 = _normal_entries_WIRE_7[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pal = _normal_entries_T_51; // @[tlb.scala:58:79] assign _normal_entries_T_52 = _normal_entries_WIRE_7[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pr = _normal_entries_T_52; // @[tlb.scala:58:79] assign _normal_entries_T_53 = _normal_entries_WIRE_7[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_px = _normal_entries_T_53; // @[tlb.scala:58:79] assign _normal_entries_T_54 = _normal_entries_WIRE_7[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pw = _normal_entries_T_54; // @[tlb.scala:58:79] assign _normal_entries_T_55 = _normal_entries_WIRE_7[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sr = _normal_entries_T_55; // @[tlb.scala:58:79] assign _normal_entries_T_56 = _normal_entries_WIRE_7[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sx = _normal_entries_T_56; // @[tlb.scala:58:79] assign _normal_entries_T_57 = _normal_entries_WIRE_7[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sw = _normal_entries_T_57; // @[tlb.scala:58:79] assign _normal_entries_T_58 = _normal_entries_WIRE_7[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_ae = _normal_entries_T_58; // @[tlb.scala:58:79] assign _normal_entries_T_59 = _normal_entries_WIRE_7[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_g = _normal_entries_T_59; // @[tlb.scala:58:79] assign _normal_entries_T_60 = _normal_entries_WIRE_7[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_u = _normal_entries_T_60; // @[tlb.scala:58:79] assign _normal_entries_T_61 = _normal_entries_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_6_ppn = _normal_entries_T_61; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_76; // @[tlb.scala:58:79] wire _normal_entries_T_75; // @[tlb.scala:58:79] wire _normal_entries_T_74; // @[tlb.scala:58:79] wire _normal_entries_T_73; // @[tlb.scala:58:79] wire _normal_entries_T_72; // @[tlb.scala:58:79] wire _normal_entries_T_71; // @[tlb.scala:58:79] wire _normal_entries_T_70; // @[tlb.scala:58:79] wire _normal_entries_T_69; // @[tlb.scala:58:79] wire _normal_entries_T_68; // @[tlb.scala:58:79] wire _normal_entries_T_67; // @[tlb.scala:58:79] wire _normal_entries_T_66; // @[tlb.scala:58:79] wire _normal_entries_T_65; // @[tlb.scala:58:79] wire _normal_entries_T_64; // @[tlb.scala:58:79] wire _normal_entries_T_63; // @[tlb.scala:58:79] wire _normal_entries_T_62; // @[tlb.scala:58:79] assign _normal_entries_T_62 = _normal_entries_WIRE_9[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_fragmented_superpage = _normal_entries_T_62; // @[tlb.scala:58:79] assign _normal_entries_T_63 = _normal_entries_WIRE_9[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_c = _normal_entries_T_63; // @[tlb.scala:58:79] assign _normal_entries_T_64 = _normal_entries_WIRE_9[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_eff = _normal_entries_T_64; // @[tlb.scala:58:79] assign _normal_entries_T_65 = _normal_entries_WIRE_9[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_paa = _normal_entries_T_65; // @[tlb.scala:58:79] assign _normal_entries_T_66 = _normal_entries_WIRE_9[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pal = _normal_entries_T_66; // @[tlb.scala:58:79] assign _normal_entries_T_67 = _normal_entries_WIRE_9[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pr = _normal_entries_T_67; // @[tlb.scala:58:79] assign _normal_entries_T_68 = _normal_entries_WIRE_9[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_px = _normal_entries_T_68; // @[tlb.scala:58:79] assign _normal_entries_T_69 = _normal_entries_WIRE_9[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pw = _normal_entries_T_69; // @[tlb.scala:58:79] assign _normal_entries_T_70 = _normal_entries_WIRE_9[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sr = _normal_entries_T_70; // @[tlb.scala:58:79] assign _normal_entries_T_71 = _normal_entries_WIRE_9[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sx = _normal_entries_T_71; // @[tlb.scala:58:79] assign _normal_entries_T_72 = _normal_entries_WIRE_9[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sw = _normal_entries_T_72; // @[tlb.scala:58:79] assign _normal_entries_T_73 = _normal_entries_WIRE_9[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_ae = _normal_entries_T_73; // @[tlb.scala:58:79] assign _normal_entries_T_74 = _normal_entries_WIRE_9[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_g = _normal_entries_T_74; // @[tlb.scala:58:79] assign _normal_entries_T_75 = _normal_entries_WIRE_9[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_u = _normal_entries_T_75; // @[tlb.scala:58:79] assign _normal_entries_T_76 = _normal_entries_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_8_ppn = _normal_entries_T_76; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_91; // @[tlb.scala:58:79] wire _normal_entries_T_90; // @[tlb.scala:58:79] wire _normal_entries_T_89; // @[tlb.scala:58:79] wire _normal_entries_T_88; // @[tlb.scala:58:79] wire _normal_entries_T_87; // @[tlb.scala:58:79] wire _normal_entries_T_86; // @[tlb.scala:58:79] wire _normal_entries_T_85; // @[tlb.scala:58:79] wire _normal_entries_T_84; // @[tlb.scala:58:79] wire _normal_entries_T_83; // @[tlb.scala:58:79] wire _normal_entries_T_82; // @[tlb.scala:58:79] wire _normal_entries_T_81; // @[tlb.scala:58:79] wire _normal_entries_T_80; // @[tlb.scala:58:79] wire _normal_entries_T_79; // @[tlb.scala:58:79] wire _normal_entries_T_78; // @[tlb.scala:58:79] wire _normal_entries_T_77; // @[tlb.scala:58:79] assign _normal_entries_T_77 = _normal_entries_WIRE_11[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_fragmented_superpage = _normal_entries_T_77; // @[tlb.scala:58:79] assign _normal_entries_T_78 = _normal_entries_WIRE_11[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_c = _normal_entries_T_78; // @[tlb.scala:58:79] assign _normal_entries_T_79 = _normal_entries_WIRE_11[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_eff = _normal_entries_T_79; // @[tlb.scala:58:79] assign _normal_entries_T_80 = _normal_entries_WIRE_11[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_paa = _normal_entries_T_80; // @[tlb.scala:58:79] assign _normal_entries_T_81 = _normal_entries_WIRE_11[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pal = _normal_entries_T_81; // @[tlb.scala:58:79] assign _normal_entries_T_82 = _normal_entries_WIRE_11[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pr = _normal_entries_T_82; // @[tlb.scala:58:79] assign _normal_entries_T_83 = _normal_entries_WIRE_11[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_px = _normal_entries_T_83; // @[tlb.scala:58:79] assign _normal_entries_T_84 = _normal_entries_WIRE_11[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pw = _normal_entries_T_84; // @[tlb.scala:58:79] assign _normal_entries_T_85 = _normal_entries_WIRE_11[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sr = _normal_entries_T_85; // @[tlb.scala:58:79] assign _normal_entries_T_86 = _normal_entries_WIRE_11[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sx = _normal_entries_T_86; // @[tlb.scala:58:79] assign _normal_entries_T_87 = _normal_entries_WIRE_11[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sw = _normal_entries_T_87; // @[tlb.scala:58:79] assign _normal_entries_T_88 = _normal_entries_WIRE_11[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_ae = _normal_entries_T_88; // @[tlb.scala:58:79] assign _normal_entries_T_89 = _normal_entries_WIRE_11[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_g = _normal_entries_T_89; // @[tlb.scala:58:79] assign _normal_entries_T_90 = _normal_entries_WIRE_11[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_u = _normal_entries_T_90; // @[tlb.scala:58:79] assign _normal_entries_T_91 = _normal_entries_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_10_ppn = _normal_entries_T_91; // @[tlb.scala:58:79] wire [19:0] normal_entries_0_0_ppn = _normal_entries_WIRE_12_0_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_u = _normal_entries_WIRE_12_0_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_g = _normal_entries_WIRE_12_0_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_ae = _normal_entries_WIRE_12_0_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sw = _normal_entries_WIRE_12_0_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sx = _normal_entries_WIRE_12_0_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sr = _normal_entries_WIRE_12_0_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pw = _normal_entries_WIRE_12_0_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_px = _normal_entries_WIRE_12_0_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pr = _normal_entries_WIRE_12_0_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pal = _normal_entries_WIRE_12_0_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_paa = _normal_entries_WIRE_12_0_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_eff = _normal_entries_WIRE_12_0_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_c = _normal_entries_WIRE_12_0_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_fragmented_superpage = _normal_entries_WIRE_12_0_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_1_ppn = _normal_entries_WIRE_12_1_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_u = _normal_entries_WIRE_12_1_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_g = _normal_entries_WIRE_12_1_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_ae = _normal_entries_WIRE_12_1_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sw = _normal_entries_WIRE_12_1_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sx = _normal_entries_WIRE_12_1_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sr = _normal_entries_WIRE_12_1_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pw = _normal_entries_WIRE_12_1_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_px = _normal_entries_WIRE_12_1_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pr = _normal_entries_WIRE_12_1_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pal = _normal_entries_WIRE_12_1_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_paa = _normal_entries_WIRE_12_1_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_eff = _normal_entries_WIRE_12_1_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_c = _normal_entries_WIRE_12_1_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_fragmented_superpage = _normal_entries_WIRE_12_1_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_2_ppn = _normal_entries_WIRE_12_2_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_u = _normal_entries_WIRE_12_2_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_g = _normal_entries_WIRE_12_2_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_ae = _normal_entries_WIRE_12_2_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sw = _normal_entries_WIRE_12_2_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sx = _normal_entries_WIRE_12_2_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sr = _normal_entries_WIRE_12_2_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pw = _normal_entries_WIRE_12_2_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_px = _normal_entries_WIRE_12_2_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pr = _normal_entries_WIRE_12_2_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pal = _normal_entries_WIRE_12_2_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_paa = _normal_entries_WIRE_12_2_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_eff = _normal_entries_WIRE_12_2_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_c = _normal_entries_WIRE_12_2_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_fragmented_superpage = _normal_entries_WIRE_12_2_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_3_ppn = _normal_entries_WIRE_12_3_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_u = _normal_entries_WIRE_12_3_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_g = _normal_entries_WIRE_12_3_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_ae = _normal_entries_WIRE_12_3_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sw = _normal_entries_WIRE_12_3_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sx = _normal_entries_WIRE_12_3_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sr = _normal_entries_WIRE_12_3_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pw = _normal_entries_WIRE_12_3_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_px = _normal_entries_WIRE_12_3_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pr = _normal_entries_WIRE_12_3_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pal = _normal_entries_WIRE_12_3_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_paa = _normal_entries_WIRE_12_3_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_eff = _normal_entries_WIRE_12_3_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_c = _normal_entries_WIRE_12_3_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_fragmented_superpage = _normal_entries_WIRE_12_3_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_4_ppn = _normal_entries_WIRE_12_4_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_u = _normal_entries_WIRE_12_4_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_g = _normal_entries_WIRE_12_4_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_ae = _normal_entries_WIRE_12_4_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sw = _normal_entries_WIRE_12_4_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sx = _normal_entries_WIRE_12_4_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sr = _normal_entries_WIRE_12_4_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pw = _normal_entries_WIRE_12_4_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_px = _normal_entries_WIRE_12_4_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pr = _normal_entries_WIRE_12_4_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pal = _normal_entries_WIRE_12_4_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_paa = _normal_entries_WIRE_12_4_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_eff = _normal_entries_WIRE_12_4_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_c = _normal_entries_WIRE_12_4_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_fragmented_superpage = _normal_entries_WIRE_12_4_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_5_ppn = _normal_entries_WIRE_12_5_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_u = _normal_entries_WIRE_12_5_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_g = _normal_entries_WIRE_12_5_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_ae = _normal_entries_WIRE_12_5_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sw = _normal_entries_WIRE_12_5_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sx = _normal_entries_WIRE_12_5_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sr = _normal_entries_WIRE_12_5_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pw = _normal_entries_WIRE_12_5_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_px = _normal_entries_WIRE_12_5_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pr = _normal_entries_WIRE_12_5_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pal = _normal_entries_WIRE_12_5_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_paa = _normal_entries_WIRE_12_5_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_eff = _normal_entries_WIRE_12_5_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_c = _normal_entries_WIRE_12_5_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_fragmented_superpage = _normal_entries_WIRE_12_5_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [1:0] ptw_ae_array_lo_hi = {entries_0_2_ae, entries_0_1_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, entries_0_0_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo = {entries_0_4_ae, entries_0_3_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_hi = {entries_0_6_ae, entries_0_5_ae}; // @[package.scala:45:27] wire [3:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [7:0] _ptw_ae_array_T_1 = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [7:0] ptw_ae_array_0 = _ptw_ae_array_T_1; // @[tlb.scala:119:49, :214:39] wire _priv_rw_ok_T = ~priv_s; // @[tlb.scala:137:20, :215:40] wire _priv_rw_ok_T_1 = _priv_rw_ok_T \| io_ptw_status_sum_0; // @[tlb.scala:17:7, :215:{40,48}] wire [1:0] _GEN_28 = {entries_0_2_u, entries_0_1_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_28; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_28; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_28; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_28; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [1:0] _GEN_29 = {entries_0_4_u, entries_0_3_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_lo = _GEN_29; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_1 = _GEN_29; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_lo = _GEN_29; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_1 = _GEN_29; // @[package.scala:45:27] wire [1:0] _GEN_30 = {entries_0_6_u, entries_0_5_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_30; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_30; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_30; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_30; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 7'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 7'h0; // @[tlb.scala:137:20, :215:{108,117}] wire [6:0] _priv_rw_ok_T_7 = _priv_rw_ok_T_3 \| _priv_rw_ok_T_6; // @[tlb.scala:215:{39,103,108}] wire [6:0] priv_rw_ok_0 = _priv_rw_ok_T_7; // @[tlb.scala:119:49, :215:103] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T_3 = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire [6:0] priv_x_ok_0 = _priv_x_ok_T_3; // @[tlb.scala:119:49, :216:39] wire [1:0] r_array_lo_hi = {entries_0_2_sr, entries_0_1_sr}; // @[package.scala:45:27] wire [2:0] r_array_lo = {r_array_lo_hi, entries_0_0_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo = {entries_0_4_sr, entries_0_3_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi = {entries_0_6_sr, entries_0_5_sr}; // @[package.scala:45:27] wire [3:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_31 = {entries_0_2_sx, entries_0_1_sx}; // @[package.scala:45:27] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_31; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_31; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, entries_0_0_sx}; // @[package.scala:45:27] wire [1:0] _GEN_32 = {entries_0_4_sx, entries_0_3_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_lo_1 = _GEN_32; // @[package.scala:45:27] wire [1:0] x_array_hi_lo; // @[package.scala:45:27] assign x_array_hi_lo = _GEN_32; // @[package.scala:45:27] wire [1:0] _GEN_33 = {entries_0_6_sx, entries_0_5_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_33; // @[package.scala:45:27] wire [3:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [6:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [6:0] _r_array_T_2 = io_ptw_status_mxr_0 ? _r_array_T_1 : 7'h0; // @[package.scala:45:27] wire [6:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [6:0] _r_array_T_4 = priv_rw_ok_0 & _r_array_T_3; // @[tlb.scala:119:49, :217:{62,93}] wire [7:0] _r_array_T_5 = {1'h1, _r_array_T_4}; // @[tlb.scala:217:{39,62}] wire [7:0] r_array_0 = _r_array_T_5; // @[tlb.scala:119:49, :217:39] wire [1:0] w_array_lo_hi = {entries_0_2_sw, entries_0_1_sw}; // @[package.scala:45:27] wire [2:0] w_array_lo = {w_array_lo_hi, entries_0_0_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo = {entries_0_4_sw, entries_0_3_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_hi = {entries_0_6_sw, entries_0_5_sw}; // @[package.scala:45:27] wire [3:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [6:0] _w_array_T_1 = priv_rw_ok_0 & _w_array_T; // @[package.scala:45:27] wire [7:0] _w_array_T_2 = {1'h1, _w_array_T_1}; // @[tlb.scala:218:{39,62}] wire [7:0] w_array_0 = _w_array_T_2; // @[tlb.scala:119:49, :218:39] wire [2:0] x_array_lo = {x_array_lo_hi, entries_0_0_sx}; // @[package.scala:45:27] wire [3:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [6:0] _x_array_T_1 = priv_x_ok_0 & _x_array_T; // @[package.scala:45:27] wire [7:0] _x_array_T_2 = {1'h1, _x_array_T_1}; // @[tlb.scala:219:{39,62}] wire [7:0] x_array_0 = _x_array_T_2; // @[tlb.scala:119:49, :219:39] wire [1:0] _pr_array_T = {2{prot_r_0}}; // @[tlb.scala:119:49, :220:44] wire [1:0] pr_array_lo_hi = {normal_entries_0_2_pr, normal_entries_0_1_pr}; // @[package.scala:45:27] wire [2:0] pr_array_lo = {pr_array_lo_hi, normal_entries_0_0_pr}; // @[package.scala:45:27] wire [1:0] pr_array_hi_hi = {normal_entries_0_5_pr, normal_entries_0_4_pr}; // @[package.scala:45:27] wire [2:0] pr_array_hi = {pr_array_hi_hi, normal_entries_0_3_pr}; // @[package.scala:45:27] wire [5:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [7:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [7:0] _pr_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116] wire [7:0] _pr_array_T_4 = _pr_array_T_2 & _pr_array_T_3; // @[tlb.scala:220:{39,114,116}] wire [7:0] pr_array_0 = _pr_array_T_4; // @[tlb.scala:119:49, :220:114] wire [1:0] _pw_array_T = {2{prot_w_0}}; // @[tlb.scala:119:49, :221:44] wire [1:0] pw_array_lo_hi = {normal_entries_0_2_pw, normal_entries_0_1_pw}; // @[package.scala:45:27] wire [2:0] pw_array_lo = {pw_array_lo_hi, normal_entries_0_0_pw}; // @[package.scala:45:27] wire [1:0] pw_array_hi_hi = {normal_entries_0_5_pw, normal_entries_0_4_pw}; // @[package.scala:45:27] wire [2:0] pw_array_hi = {pw_array_hi_hi, normal_entries_0_3_pw}; // @[package.scala:45:27] wire [5:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [7:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [7:0] _pw_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :221:116] wire [7:0] _pw_array_T_4 = _pw_array_T_2 & _pw_array_T_3; // @[tlb.scala:221:{39,114,116}] wire [7:0] pw_array_0 = _pw_array_T_4; // @[tlb.scala:119:49, :221:114] wire [1:0] _px_array_T = {2{prot_x_0}}; // @[tlb.scala:119:49, :222:44] wire [1:0] px_array_lo_hi = {normal_entries_0_2_px, normal_entries_0_1_px}; // @[package.scala:45:27] wire [2:0] px_array_lo = {px_array_lo_hi, normal_entries_0_0_px}; // @[package.scala:45:27] wire [1:0] px_array_hi_hi = {normal_entries_0_5_px, normal_entries_0_4_px}; // @[package.scala:45:27] wire [2:0] px_array_hi = {px_array_hi_hi, normal_entries_0_3_px}; // @[package.scala:45:27] wire [5:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [7:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [7:0] _px_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :222:116] wire [7:0] _px_array_T_4 = _px_array_T_2 & _px_array_T_3; // @[tlb.scala:222:{39,114,116}] wire [7:0] px_array_0 = _px_array_T_4; // @[tlb.scala:119:49, :222:114] wire [1:0] _eff_array_T = {2{prot_eff_0}}; // @[tlb.scala:119:49, :223:44] wire [1:0] eff_array_lo_hi = {normal_entries_0_2_eff, normal_entries_0_1_eff}; // @[package.scala:45:27] wire [2:0] eff_array_lo = {eff_array_lo_hi, normal_entries_0_0_eff}; // @[package.scala:45:27] wire [1:0] eff_array_hi_hi = {normal_entries_0_5_eff, normal_entries_0_4_eff}; // @[package.scala:45:27] wire [2:0] eff_array_hi = {eff_array_hi_hi, normal_entries_0_3_eff}; // @[package.scala:45:27] wire [5:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [7:0] _eff_array_T_2 = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [7:0] eff_array_0 = _eff_array_T_2; // @[tlb.scala:119:49, :223:39] wire [1:0] _c_array_T = {2{cacheable_0}}; // @[tlb.scala:119:49, :224:44] wire [1:0] _GEN_34 = {normal_entries_0_2_c, normal_entries_0_1_c}; // @[package.scala:45:27] wire [1:0] c_array_lo_hi; // @[package.scala:45:27] assign c_array_lo_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi = _GEN_34; // @[package.scala:45:27] wire [2:0] c_array_lo = {c_array_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {normal_entries_0_5_c, normal_entries_0_4_c}; // @[package.scala:45:27] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_35; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [7:0] _c_array_T_2 = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [7:0] c_array_0 = _c_array_T_2; // @[tlb.scala:119:49, :224:39] wire [7:0] _paa_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :227:61] wire [7:0] _pal_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :228:61] wire [7:0] _lrscAllowed_T = c_array_0; // @[tlb.scala:119:49, :250:38] wire [1:0] _paa_array_T = {2{prot_aa_0}}; // @[tlb.scala:119:49, :225:44] wire [1:0] paa_array_lo_hi = {normal_entries_0_2_paa, normal_entries_0_1_paa}; // @[package.scala:45:27] wire [2:0] paa_array_lo = {paa_array_lo_hi, normal_entries_0_0_paa}; // @[package.scala:45:27] wire [1:0] paa_array_hi_hi = {normal_entries_0_5_paa, normal_entries_0_4_paa}; // @[package.scala:45:27] wire [2:0] paa_array_hi = {paa_array_hi_hi, normal_entries_0_3_paa}; // @[package.scala:45:27] wire [5:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [7:0] _paa_array_T_2 = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [7:0] paa_array_0 = _paa_array_T_2; // @[tlb.scala:119:49, :225:39] wire [1:0] _pal_array_T = {2{prot_al_0}}; // @[tlb.scala:119:49, :226:44] wire [1:0] pal_array_lo_hi = {normal_entries_0_2_pal, normal_entries_0_1_pal}; // @[package.scala:45:27] wire [2:0] pal_array_lo = {pal_array_lo_hi, normal_entries_0_0_pal}; // @[package.scala:45:27] wire [1:0] pal_array_hi_hi = {normal_entries_0_5_pal, normal_entries_0_4_pal}; // @[package.scala:45:27] wire [2:0] pal_array_hi = {pal_array_hi_hi, normal_entries_0_3_pal}; // @[package.scala:45:27] wire [5:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [7:0] _pal_array_T_2 = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [7:0] pal_array_0 = _pal_array_T_2; // @[tlb.scala:119:49, :226:39] wire [7:0] _paa_array_if_cached_T_1 = paa_array_0 \| _paa_array_if_cached_T; // @[tlb.scala:119:49, :227:{56,61}] wire [7:0] paa_array_if_cached_0 = _paa_array_if_cached_T_1; // @[tlb.scala:119:49, :227:56] wire [7:0] _pal_array_if_cached_T_1 = pal_array_0 \| _pal_array_if_cached_T; // @[tlb.scala:119:49, :228:{56,61}] wire [7:0] pal_array_if_cached_0 = _pal_array_if_cached_T_1; // @[tlb.scala:119:49, :228:56] wire _prefetchable_array_T = cacheable_0 & homogeneous_0; // @[tlb.scala:119:49, :229:61] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[tlb.scala:229:{61,80}] wire [2:0] prefetchable_array_lo = {prefetchable_array_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [7:0] _prefetchable_array_T_3 = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [7:0] prefetchable_array_0 = _prefetchable_array_T_3; // @[tlb.scala:119:49, :229:46] wire [3:0] _misaligned_T = 4'h1 << io_req_0_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[tlb.scala:231:89] wire [39:0] _misaligned_T_3 = {36'h0, io_req_0_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[tlb.scala:17:7, :231:{56,89}] wire _misaligned_T_4 = \|_misaligned_T_3; // @[tlb.scala:231:{56,97}] wire misaligned_0 = _misaligned_T_4; // @[tlb.scala:119:49, :231:97] wire [39:0] bad_va_maskedVAddr = io_req_0_bits_vaddr_0 & 40'hC000000000; // @[tlb.scala:17:7, :237:46] wire _bad_va_T_1 = bad_va_maskedVAddr == 40'h0; // @[tlb.scala:237:46, :238:63] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'hC000000000; // @[tlb.scala:237:46, :238:86] wire _bad_va_T_3 = _bad_va_T_1 \| _bad_va_T_2; // @[tlb.scala:238:{63,71,86}] wire _bad_va_T_4 = ~_bad_va_T_3; // @[tlb.scala:238:{49,71}] wire _bad_va_T_5 = _bad_va_T_4; // @[tlb.scala:238:{46,49}] wire _bad_va_T_6 = vm_enabled_0 & _bad_va_T_5; // @[tlb.scala:119:49, :232:134, :238:46] wire bad_va_0 = _bad_va_T_6; // @[tlb.scala:119:49, :232:134] wire _GEN_36 = io_req_0_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_36; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = io_req_0_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_37; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_37; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_37; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire _cmd_lrsc_T_3 = _cmd_lrsc_T_2; // @[package.scala:81:59] wire cmd_lrsc_0 = _cmd_lrsc_T_3; // @[tlb.scala:119:49, :242:57] wire _GEN_38 = io_req_0_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_38; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_38; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = io_req_0_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_39; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_39; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = io_req_0_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_40; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_40; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = io_req_0_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_41; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_41; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_41; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_7 = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire cmd_amo_logical_0 = _cmd_amo_logical_T_7; // @[tlb.scala:119:49, :243:57] wire _GEN_42 = io_req_0_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_42; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_0_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_43; // @[package.scala:16:47] wire _GEN_44 = io_req_0_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_0_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_0_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_46; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_9 = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire cmd_amo_arithmetic_0 = _cmd_amo_arithmetic_T_9; // @[tlb.scala:119:49, :244:57] wire _cmd_read_T = io_req_0_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _cmd_read_T_1 = io_req_0_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire _cmd_read_T_24 = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire cmd_read_0 = _cmd_read_T_24; // @[Consts.scala:89:68] wire _cmd_write_T = io_req_0_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _cmd_write_T_1 = io_req_0_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire _cmd_write_T_22 = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire cmd_write_0 = _cmd_write_T_22; // @[Consts.scala:90:76] wire _cmd_write_perms_T_2 = cmd_write_0; // @[tlb.scala:119:49, :247:55] wire _cmd_write_perms_T = io_req_0_bits_cmd_0 == 5'h5; // @[tlb.scala:17:7, :248:51] wire cmd_write_perms_0 = _cmd_write_perms_T_2; // @[tlb.scala:119:49, :247:55] wire [7:0] lrscAllowed_0 = _lrscAllowed_T; // @[tlb.scala:119:49, :250:38] wire [7:0] _ae_array_T = misaligned_0 ? eff_array_0 : 8'h0; // @[tlb.scala:119:49, :252:8] wire [7:0] _ae_array_T_1 = ~lrscAllowed_0; // @[tlb.scala:119:49, :253:24] wire [7:0] _ae_array_T_2 = cmd_lrsc_0 ? _ae_array_T_1 : 8'h0; // @[tlb.scala:119:49, :253:{8,24}] wire [7:0] _ae_array_T_3 = _ae_array_T \| _ae_array_T_2; // @[tlb.scala:252:{8,43}, :253:8] wire [7:0] ae_array_0 = _ae_array_T_3; // @[tlb.scala:119:49, :252:43] wire _ae_valid_array_T = ~do_refill; // @[tlb.scala:144:29, :254:118] wire [1:0] _ae_valid_array_T_1 = {1'h1, _ae_valid_array_T}; // @[tlb.scala:254:{84,118}] wire [7:0] _ae_valid_array_T_3 = {_ae_valid_array_T_1, 6'h3F}; // @[tlb.scala:254:{41,84}] wire [7:0] ae_valid_array_0 = _ae_valid_array_T_3; // @[tlb.scala:119:49, :254:41] wire [7:0] _ae_ld_array_T = ~pr_array_0; // @[tlb.scala:119:49, :256:66] wire [7:0] _ae_ld_array_T_1 = ae_array_0 \| _ae_ld_array_T; // @[tlb.scala:119:49, :256:{64,66}] wire [7:0] _ae_ld_array_T_2 = cmd_read_0 ? _ae_ld_array_T_1 : 8'h0; // @[tlb.scala:119:49, :256:{38,64}] wire [7:0] ae_ld_array_0 = _ae_ld_array_T_2; // @[tlb.scala:119:49, :256:38] wire [7:0] _ae_st_array_T = ~pw_array_0; // @[tlb.scala:119:49, :258:46] wire [7:0] _ae_st_array_T_1 = ae_array_0 \| _ae_st_array_T; // @[tlb.scala:119:49, :258:{44,46}] wire [7:0] _ae_st_array_T_2 = cmd_write_perms_0 ? _ae_st_array_T_1 : 8'h0; // @[tlb.scala:119:49, :258:{8,44}] wire [7:0] _ae_st_array_T_3 = ~pal_array_if_cached_0; // @[tlb.scala:119:49, :259:32] wire [7:0] _ae_st_array_T_4 = cmd_amo_logical_0 ? _ae_st_array_T_3 : 8'h0; // @[tlb.scala:119:49, :259:{8,32}] wire [7:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[tlb.scala:258:{8,65}, :259:8] wire [7:0] _ae_st_array_T_6 = ~paa_array_if_cached_0; // @[tlb.scala:119:49, :260:32] wire [7:0] _ae_st_array_T_7 = cmd_amo_arithmetic_0 ? _ae_st_array_T_6 : 8'h0; // @[tlb.scala:119:49, :260:{8,32}] wire [7:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[tlb.scala:258:65, :259:62, :260:8] wire [7:0] ae_st_array_0 = _ae_st_array_T_8; // @[tlb.scala:119:49, :259:62] wire [7:0] _must_alloc_array_T = ~paa_array_0; // @[tlb.scala:119:49, :262:32] wire [7:0] _must_alloc_array_T_1 = cmd_amo_logical_0 ? _must_alloc_array_T : 8'h0; // @[tlb.scala:119:49, :262:{8,32}] wire [7:0] _must_alloc_array_T_2 = ~pal_array_0; // @[tlb.scala:119:49, :263:32] wire [7:0] _must_alloc_array_T_3 = cmd_amo_arithmetic_0 ? _must_alloc_array_T_2 : 8'h0; // @[tlb.scala:119:49, :263:{8,32}] wire [7:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[tlb.scala:262:{8,52}, :263:8] wire [7:0] _must_alloc_array_T_6 = {8{cmd_lrsc_0}}; // @[tlb.scala:119:49, :264:8] wire [7:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[tlb.scala:262:52, :263:52, :264:8] wire [7:0] must_alloc_array_0 = _must_alloc_array_T_7; // @[tlb.scala:119:49, :263:52] wire _ma_ld_array_T = misaligned_0 & cmd_read_0; // @[tlb.scala:119:49, :265:53] wire [7:0] _ma_ld_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70] wire [7:0] _ma_ld_array_T_2 = _ma_ld_array_T ? _ma_ld_array_T_1 : 8'h0; // @[tlb.scala:265:{38,53,70}] wire [7:0] ma_ld_array_0 = _ma_ld_array_T_2; // @[tlb.scala:119:49, :265:38] wire _ma_st_array_T = misaligned_0 & cmd_write_0; // @[tlb.scala:119:49, :266:53] wire [7:0] _ma_st_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70, :266:70] wire [7:0] _ma_st_array_T_2 = _ma_st_array_T ? _ma_st_array_T_1 : 8'h0; // @[tlb.scala:266:{38,53,70}] wire [7:0] ma_st_array_0 = _ma_st_array_T_2; // @[tlb.scala:119:49, :266:38] wire [7:0] _pf_ld_array_T = r_array_0 \| ptw_ae_array_0; // @[tlb.scala:119:49, :267:72] wire [7:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[tlb.scala:267:{59,72}] wire [7:0] _pf_ld_array_T_2 = cmd_read_0 ? _pf_ld_array_T_1 : 8'h0; // @[tlb.scala:119:49, :267:{38,59}] wire [7:0] pf_ld_array_0 = _pf_ld_array_T_2; // @[tlb.scala:119:49, :267:38] wire [7:0] _pf_st_array_T = w_array_0 \| ptw_ae_array_0; // @[tlb.scala:119:49, :268:72] wire [7:0] _pf_st_array_T_1 = ~_pf_st_array_T; // @[tlb.scala:268:{59,72}] wire [7:0] _pf_st_array_T_2 = cmd_write_perms_0 ? _pf_st_array_T_1 : 8'h0; // @[tlb.scala:119:49, :268:{38,59}] wire [7:0] pf_st_array_0 = _pf_st_array_T_2; // @[tlb.scala:119:49, :268:38] wire [7:0] _pf_inst_array_T = x_array_0 \| ptw_ae_array_0; // @[tlb.scala:119:49, :269:50] wire [7:0] _pf_inst_array_T_1 = ~_pf_inst_array_T; // @[tlb.scala:269:{37,50}] wire [7:0] pf_inst_array_0 = _pf_inst_array_T_1; // @[tlb.scala:119:49, :269:37] wire _tlb_hit_T = \|real_hits_0; // @[tlb.scala:119:49, :271:44] wire tlb_hit_0 = _tlb_hit_T; // @[tlb.scala:119:49, :271:44] wire _tlb_miss_T = ~bad_va_0; // @[tlb.scala:119:49, :272:49] wire _tlb_miss_T_1 = vm_enabled_0 & _tlb_miss_T; // @[tlb.scala:119:49, :272:{46,49}] wire _tlb_miss_T_2 = ~tlb_hit_0; // @[tlb.scala:119:49, :272:63] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[tlb.scala:272:{46,60,63}] wire tlb_miss_0 = _tlb_miss_T_3; // @[tlb.scala:119:49, :272:60] reg state_reg; // @[Replacement.scala:168:70] wire _r_sectored_repl_addr_T = state_reg; // @[Replacement.scala:168:70, :262:12] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire _state_reg_T = state_reg_touch_way_sized; // @[package.scala:163:13] wire _state_reg_T_1 = ~_state_reg_T; // @[Replacement.scala:218:{7,17}] wire [1:0] lo = {superpage_hits_0_1, superpage_hits_0_0}; // @[OneHot.scala:22:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:22:45, :31:18] wire [1:0] hi = {superpage_hits_0_3, superpage_hits_0_2}; // @[OneHot.scala:22:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:22:45, :30:18] wire [1:0] state_reg_touch_way_sized_1 = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T_2 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_6 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_3 = _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_4 = ~_state_reg_T_3; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_5 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_4; // @[package.scala:163:13] wire _state_reg_T_7 = _state_reg_T_6; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_8 = ~_state_reg_T_7; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_9 = state_reg_set_left_older ? _state_reg_T_8 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_5}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_10 = {state_reg_hi, _state_reg_T_9}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits_0[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_9 = real_hits_0[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_10 = _multipleHits_T_9[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_12 = _multipleHits_T_10[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_2 = _multipleHits_T_12; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_14 = multipleHits_leftOne_3 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_1 = _multipleHits_T_14; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_15 = _multipleHits_T_9[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_16 = _multipleHits_T_15[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_5 = _multipleHits_T_16; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_17 = _multipleHits_T_15[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_3 = _multipleHits_T_17; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_4 = multipleHits_leftOne_5 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_19 = multipleHits_leftOne_5 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_19; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_5 = multipleHits_leftOne_4 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_20 = multipleHits_leftTwo_1 \| multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_21 = multipleHits_leftOne_4 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_20 \| _multipleHits_T_21; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_22 = multipleHits_leftOne_2 \| multipleHits_rightOne_5; // @[Misc.scala:183:16] wire _multipleHits_T_23 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_24 = multipleHits_leftOne_2 & multipleHits_rightOne_5; // @[Misc.scala:183:{16,61}] wire _multipleHits_T_25 = _multipleHits_T_23 \| _multipleHits_T_24; // @[Misc.scala:183:{37,49,61}] wire multipleHits_0 = _multipleHits_T_25; // @[Misc.scala:183:49] assign _io_miss_rdy_T = state == 2'h0; // @[tlb.scala:129:22, :290:24] assign io_miss_rdy = _io_miss_rdy_T; // @[tlb.scala:17:7, :290:24] wire _io_resp_0_pf_ld_T = bad_va_0 & cmd_read_0; // @[tlb.scala:119:49, :298:38] wire [7:0] _io_resp_0_pf_ld_T_1 = pf_ld_array_0 & hits_0; // @[tlb.scala:119:49, :298:73] wire _io_resp_0_pf_ld_T_2 = \|_io_resp_0_pf_ld_T_1; // @[tlb.scala:298:{73,84}] assign _io_resp_0_pf_ld_T_3 = _io_resp_0_pf_ld_T \| _io_resp_0_pf_ld_T_2; // @[tlb.scala:298:{38,54,84}] assign io_resp_0_pf_ld_0 = _io_resp_0_pf_ld_T_3; // @[tlb.scala:17:7, :298:54] wire _io_resp_0_pf_st_T = bad_va_0 & cmd_write_perms_0; // @[tlb.scala:119:49, :299:38] wire [7:0] _io_resp_0_pf_st_T_1 = pf_st_array_0 & hits_0; // @[tlb.scala:119:49, :299:80] wire _io_resp_0_pf_st_T_2 = \|_io_resp_0_pf_st_T_1; // @[tlb.scala:299:{80,91}] assign _io_resp_0_pf_st_T_3 = _io_resp_0_pf_st_T \| _io_resp_0_pf_st_T_2; // @[tlb.scala:299:{38,61,91}] assign io_resp_0_pf_st_0 = _io_resp_0_pf_st_T_3; // @[tlb.scala:17:7, :299:61] wire [7:0] _io_resp_0_pf_inst_T = pf_inst_array_0 & hits_0; // @[tlb.scala:119:49, :300:58] wire _io_resp_0_pf_inst_T_1 = \|_io_resp_0_pf_inst_T; // @[tlb.scala:300:{58,69}] assign _io_resp_0_pf_inst_T_2 = bad_va_0 \| _io_resp_0_pf_inst_T_1; // @[tlb.scala:119:49, :300:{37,69}] assign io_resp_0_pf_inst = _io_resp_0_pf_inst_T_2; // @[tlb.scala:17:7, :300:37] wire [7:0] _io_resp_0_ae_ld_T = ae_valid_array_0 & ae_ld_array_0; // @[tlb.scala:119:49, :301:46] wire [7:0] _io_resp_0_ae_ld_T_1 = _io_resp_0_ae_ld_T & hits_0; // @[tlb.scala:119:49, :301:{46,63}] assign _io_resp_0_ae_ld_T_2 = \|_io_resp_0_ae_ld_T_1; // @[tlb.scala:301:{63,74}] assign io_resp_0_ae_ld_0 = _io_resp_0_ae_ld_T_2; // @[tlb.scala:17:7, :301:74] wire [7:0] _io_resp_0_ae_st_T = ae_valid_array_0 & ae_st_array_0; // @[tlb.scala:119:49, :302:46] wire [7:0] _io_resp_0_ae_st_T_1 = _io_resp_0_ae_st_T & hits_0; // @[tlb.scala:119:49, :302:{46,63}] assign _io_resp_0_ae_st_T_2 = \|_io_resp_0_ae_st_T_1; // @[tlb.scala:302:{63,74}] assign io_resp_0_ae_st_0 = _io_resp_0_ae_st_T_2; // @[tlb.scala:17:7, :302:74] wire [7:0] _io_resp_0_ae_inst_T = ~px_array_0; // @[tlb.scala:119:49, :303:48] wire [7:0] _io_resp_0_ae_inst_T_1 = ae_valid_array_0 & _io_resp_0_ae_inst_T; // @[tlb.scala:119:49, :303:{46,48}] wire [7:0] _io_resp_0_ae_inst_T_2 = _io_resp_0_ae_inst_T_1 & hits_0; // @[tlb.scala:119:49, :303:{46,63}] assign _io_resp_0_ae_inst_T_3 = \|_io_resp_0_ae_inst_T_2; // @[tlb.scala:303:{63,74}] assign io_resp_0_ae_inst = _io_resp_0_ae_inst_T_3; // @[tlb.scala:17:7, :303:74] wire [7:0] _io_resp_0_ma_ld_T = ma_ld_array_0 & hits_0; // @[tlb.scala:119:49, :304:43] assign _io_resp_0_ma_ld_T_1 = \|_io_resp_0_ma_ld_T; // @[tlb.scala:304:{43,54}] assign io_resp_0_ma_ld_0 = _io_resp_0_ma_ld_T_1; // @[tlb.scala:17:7, :304:54] wire [7:0] _io_resp_0_ma_st_T = ma_st_array_0 & hits_0; // @[tlb.scala:119:49, :305:43] assign _io_resp_0_ma_st_T_1 = \|_io_resp_0_ma_st_T; // @[tlb.scala:305:{43,54}] assign io_resp_0_ma_st_0 = _io_resp_0_ma_st_T_1; // @[tlb.scala:17:7, :305:54] wire [7:0] _io_resp_0_cacheable_T = c_array_0 & hits_0; // @[tlb.scala:119:49, :307:44] assign _io_resp_0_cacheable_T_1 = \|_io_resp_0_cacheable_T; // @[tlb.scala:307:{44,55}] assign io_resp_0_cacheable_0 = _io_resp_0_cacheable_T_1; // @[tlb.scala:17:7, :307:55] wire [7:0] _io_resp_0_must_alloc_T = must_alloc_array_0 & hits_0; // @[tlb.scala:119:49, :308:53] assign _io_resp_0_must_alloc_T_1 = \|_io_resp_0_must_alloc_T; // @[tlb.scala:308:{53,64}] assign io_resp_0_must_alloc = _io_resp_0_must_alloc_T_1; // @[tlb.scala:17:7, :308:64] wire [7:0] _io_resp_0_prefetchable_T = prefetchable_array_0 & hits_0; // @[tlb.scala:119:49, :309:55] wire _io_resp_0_prefetchable_T_1 = \|_io_resp_0_prefetchable_T; // @[tlb.scala:309:{55,66}] assign _io_resp_0_prefetchable_T_2 = _io_resp_0_prefetchable_T_1; // @[tlb.scala:309:{66,70}] assign io_resp_0_prefetchable = _io_resp_0_prefetchable_T_2; // @[tlb.scala:17:7, :309:70] wire _io_resp_0_miss_T = do_refill \| tlb_miss_0; // @[tlb.scala:119:49, :144:29, :310:35] assign _io_resp_0_miss_T_1 = _io_resp_0_miss_T \| multipleHits_0; // @[tlb.scala:119:49, :310:{35,50}] assign io_resp_0_miss_0 = _io_resp_0_miss_T_1; // @[tlb.scala:17:7, :310:50] assign _io_resp_0_paddr_T_1 = {ppn_0, _io_resp_0_paddr_T}; // @[tlb.scala:119:49, :311:{28,57}] assign io_resp_0_paddr_0 = _io_resp_0_paddr_T_1; // @[tlb.scala:17:7, :311:28] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[tlb.scala:17:7, :317:29] assign _io_ptw_req_bits_valid_T = ~io_kill_0; // @[tlb.scala:17:7, :319:28] assign io_ptw_req_bits_valid_0 = _io_ptw_req_bits_valid_T; // @[tlb.scala:17:7, :319:28] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T \| sectored_entries_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 \| sectored_entries_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 \| sectored_entries_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 \| sectored_entries_1_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire _r_sectored_repl_addr_T_1 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [1:0] _r_sectored_repl_addr_T_2 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_3 = _r_sectored_repl_addr_T_2[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_4 = _r_sectored_repl_addr_T_2[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_5 = ~_r_sectored_repl_addr_T_3; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_5; // @[Mux.scala:50:70] wire [1:0] _r_sectored_hit_addr_T = {sector_hits_0_1, sector_hits_0_0}; // @[OneHot.scala:22:45] wire _r_sectored_hit_addr_T_1 = _r_sectored_hit_addr_T[1]; // @[OneHot.scala:22:45] wire _r_sectored_hit_T = sector_hits_0_0 \| sector_hits_0_1; // @[package.scala:81:59] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[tlb.scala:17:7, :337:45]
Generate the Verilog code corresponding to this FIRRTL code module SourceX_6 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}, x : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}} wire x : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}} inst io_x_q of Queue1_SourceXRequest_6 connect io_x_q.clock, clock connect io_x_q.reset, reset connect io_x_q.io.enq.valid, x.valid connect io_x_q.io.enq.bits.fail, x.bits.fail connect x.ready, io_x_q.io.enq.ready connect io.x.bits, io_x_q.io.deq.bits connect io.x.valid, io_x_q.io.deq.valid connect io_x_q.io.deq.ready, io.x.ready connect io.req.ready, x.ready connect x.valid, io.req.valid node _T = eq(x.ready, UInt<1>(0h0)) node _T_1 = and(x.valid, _T) connect x.bits, io.req.bits	module SourceX_6( // @[SourceX.scala:29:7] input clock, // @[SourceX.scala:29:7] input reset, // @[SourceX.scala:29:7] output io_req_ready, // @[SourceX.scala:31:14] input io_req_valid, // @[SourceX.scala:31:14] output io_x_valid // @[SourceX.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceX.scala:29:7] wire io_x_ready = 1'h1; // @[Decoupled.scala:362:21] wire io_req_bits_fail = 1'h0; // @[SourceX.scala:29:7] wire io_x_bits_fail = 1'h0; // @[SourceX.scala:29:7] wire x_ready; // @[SourceX.scala:36:15] wire x_bits_fail = 1'h0; // @[SourceX.scala:36:15] wire x_valid = io_req_valid_0; // @[SourceX.scala:29:7, :36:15] wire io_req_ready_0; // @[SourceX.scala:29:7] wire io_x_valid_0; // @[SourceX.scala:29:7] assign io_req_ready_0 = x_ready; // @[SourceX.scala:29:7, :36:15] Queue1_SourceXRequest_6 io_x_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x_ready), .io_enq_valid (x_valid), // @[SourceX.scala:36:15] .io_deq_valid (io_x_valid_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceX.scala:29:7] assign io_x_valid = io_x_valid_0; // @[SourceX.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = and(_T_207, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_206, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_215, UInt<1>(0h1), "") : assert_26 node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(is_aligned, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(io.in.a.bits.mask, mask) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_229, UInt<1>(0h1), "") : assert_30 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_237 = shr(io.in.a.bits.source, 11) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(_T_244, _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_253, UInt<1>(0h1), "") : assert_31 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_263, UInt<1>(0h1), "") : assert_34 node _T_267 = not(mask) node _T_268 = and(io.in.a.bits.mask, _T_267) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_269, UInt<1>(0h1), "") : assert_35 node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_277 = shr(io.in.a.bits.source, 11) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) node _T_280 = and(_T_278, _T_279) node _T_281 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_282 = and(_T_280, _T_281) node _T_283 = and(_T_276, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_T_284, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_293, UInt<1>(0h1), "") : assert_36 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(is_aligned, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_303, UInt<1>(0h1), "") : assert_39 node _T_307 = eq(io.in.a.bits.mask, mask) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_307, UInt<1>(0h1), "") : assert_40 node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_311 : node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_315 = shr(io.in.a.bits.source, 11) node _T_316 = eq(_T_315, UInt<1>(0h0)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_320 = and(_T_318, _T_319) node _T_321 = and(_T_314, _T_320) node _T_322 = or(UInt<1>(0h0), _T_321) node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = and(_T_323, _T_328) node _T_330 = or(UInt<1>(0h0), _T_329) node _T_331 = and(_T_322, _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_331, UInt<1>(0h1), "") : assert_41 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(is_aligned, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_341, UInt<1>(0h1), "") : assert_44 node _T_345 = eq(io.in.a.bits.mask, mask) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_345, UInt<1>(0h1), "") : assert_45 node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_349 : node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_353 = shr(io.in.a.bits.source, 11) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_358 = and(_T_356, _T_357) node _T_359 = and(_T_352, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = and(_T_361, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(_T_360, _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_369, UInt<1>(0h1), "") : assert_46 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(is_aligned, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_379, UInt<1>(0h1), "") : assert_49 node _T_383 = eq(io.in.a.bits.mask, mask) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_383, UInt<1>(0h1), "") : assert_50 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_387, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_391, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_399, UInt<1>(0h1), "") : assert_54 node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_403, UInt<1>(0h1), "") : assert_55 node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_407, UInt<1>(0h1), "") : assert_56 node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_411, UInt<1>(0h1), "") : assert_57 node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(sink_ok, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_422, UInt<1>(0h1), "") : assert_60 node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_426, UInt<1>(0h1), "") : assert_61 node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_430, UInt<1>(0h1), "") : assert_62 node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_434, UInt<1>(0h1), "") : assert_63 node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_439, UInt<1>(0h1), "") : assert_64 node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_443 : node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(sink_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_450, UInt<1>(0h1), "") : assert_67 node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_454, UInt<1>(0h1), "") : assert_68 node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_458, UInt<1>(0h1), "") : assert_69 node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_463 = or(_T_462, io.in.d.bits.corrupt) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_463, UInt<1>(0h1), "") : assert_70 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_468, UInt<1>(0h1), "") : assert_71 node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_472 : node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_476, UInt<1>(0h1), "") : assert_73 node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_480, UInt<1>(0h1), "") : assert_74 node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_485, UInt<1>(0h1), "") : assert_75 node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_493, UInt<1>(0h1), "") : assert_77 node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_498 = or(_T_497, io.in.d.bits.corrupt) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_498, UInt<1>(0h1), "") : assert_78 node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_503, UInt<1>(0h1), "") : assert_79 node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_507 : node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_511, UInt<1>(0h1), "") : assert_81 node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_515, UInt<1>(0h1), "") : assert_82 node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_520, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_524, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_528, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_532, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_536 = eq(a_first, UInt<1>(0h0)) node _T_537 = and(io.in.a.valid, _T_536) when _T_537 : node _T_538 = eq(io.in.a.bits.opcode, opcode) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_538, UInt<1>(0h1), "") : assert_87 node _T_542 = eq(io.in.a.bits.param, param) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_542, UInt<1>(0h1), "") : assert_88 node _T_546 = eq(io.in.a.bits.size, size) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_546, UInt<1>(0h1), "") : assert_89 node _T_550 = eq(io.in.a.bits.source, source) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_550, UInt<1>(0h1), "") : assert_90 node _T_554 = eq(io.in.a.bits.address, address) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_554, UInt<1>(0h1), "") : assert_91 node _T_558 = and(io.in.a.ready, io.in.a.valid) node _T_559 = and(_T_558, a_first) when _T_559 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_560 = eq(d_first, UInt<1>(0h0)) node _T_561 = and(io.in.d.valid, _T_560) when _T_561 : node _T_562 = eq(io.in.d.bits.opcode, opcode_1) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_562, UInt<1>(0h1), "") : assert_92 node _T_566 = eq(io.in.d.bits.param, param_1) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_566, UInt<1>(0h1), "") : assert_93 node _T_570 = eq(io.in.d.bits.size, size_1) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_570, UInt<1>(0h1), "") : assert_94 node _T_574 = eq(io.in.d.bits.source, source_1) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_574, UInt<1>(0h1), "") : assert_95 node _T_578 = eq(io.in.d.bits.sink, sink) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_578, UInt<1>(0h1), "") : assert_96 node _T_582 = eq(io.in.d.bits.denied, denied) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_582, UInt<1>(0h1), "") : assert_97 node _T_586 = and(io.in.d.ready, io.in.d.valid) node _T_587 = and(_T_586, d_first) when _T_587 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_588 = and(io.in.a.valid, a_first_1) node _T_589 = and(_T_588, UInt<1>(0h1)) when _T_589 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_590 = and(io.in.a.ready, io.in.a.valid) node _T_591 = and(_T_590, a_first_1) node _T_592 = and(_T_591, UInt<1>(0h1)) when _T_592 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_593 = dshr(inflight, io.in.a.bits.source) node _T_594 = bits(_T_593, 0, 0) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_595, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_599 = and(io.in.d.valid, d_first_1) node _T_600 = and(_T_599, UInt<1>(0h1)) node _T_601 = eq(d_release_ack, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) when _T_602 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_603 = and(io.in.d.ready, io.in.d.valid) node _T_604 = and(_T_603, d_first_1) node _T_605 = and(_T_604, UInt<1>(0h1)) node _T_606 = eq(d_release_ack, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_608 = and(io.in.d.valid, d_first_1) node _T_609 = and(_T_608, UInt<1>(0h1)) node _T_610 = eq(d_release_ack, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) when _T_611 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_612 = dshr(inflight, io.in.d.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = or(_T_613, same_cycle_resp) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_614, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_620 = or(_T_618, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_620, UInt<1>(0h1), "") : assert_100 node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_624, UInt<1>(0h1), "") : assert_101 else : node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_630 = or(_T_628, _T_629) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_630, UInt<1>(0h1), "") : assert_102 node _T_634 = eq(io.in.d.bits.size, a_size_lookup) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_634, UInt<1>(0h1), "") : assert_103 node _T_638 = and(io.in.d.valid, d_first_1) node _T_639 = and(_T_638, a_first_1) node _T_640 = and(_T_639, io.in.a.valid) node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_642 = and(_T_640, _T_641) node _T_643 = eq(d_release_ack, UInt<1>(0h0)) node _T_644 = and(_T_642, _T_643) when _T_644 : node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_646 = or(_T_645, io.in.a.ready) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_646, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_131 node _T_650 = orr(inflight) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_653 = or(_T_651, _T_652) node _T_654 = lt(watchdog, plusarg_reader.out) node _T_655 = or(_T_653, _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_655, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_659 = and(io.in.a.ready, io.in.a.valid) node _T_660 = and(io.in.d.ready, io.in.d.valid) node _T_661 = or(_T_659, _T_660) when _T_661 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_662 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_665 = and(_T_663, _T_664) node _T_666 = and(_T_662, _T_665) when _T_666 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_668 = and(_T_667, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) node _T_674 = bits(_T_673, 0, 0) node _T_675 = eq(_T_674, UInt<1>(0h0)) node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(_T_675, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_675, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_679 = and(io.in.d.valid, d_first_2) node _T_680 = and(_T_679, UInt<1>(0h1)) node _T_681 = and(_T_680, d_release_ack_1) when _T_681 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_682 = and(io.in.d.ready, io.in.d.valid) node _T_683 = and(_T_682, d_first_2) node _T_684 = and(_T_683, UInt<1>(0h1)) node _T_685 = and(_T_684, d_release_ack_1) when _T_685 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_686 = and(io.in.d.valid, d_first_2) node _T_687 = and(_T_686, UInt<1>(0h1)) node _T_688 = and(_T_687, d_release_ack_1) when _T_688 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_689 = dshr(inflight_1, io.in.d.bits.source) node _T_690 = bits(_T_689, 0, 0) node _T_691 = or(_T_690, same_cycle_resp_1) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_691, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_695, UInt<1>(0h1), "") : assert_108 else : node _T_699 = eq(io.in.d.bits.size, c_size_lookup) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_699, UInt<1>(0h1), "") : assert_109 node _T_703 = and(io.in.d.valid, d_first_2) node _T_704 = and(_T_703, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_705 = and(_T_704, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_707 = and(_T_705, _T_706) node _T_708 = and(_T_707, d_release_ack_1) node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_712 = or(_T_711, _WIRE_23.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_132 node _T_716 = orr(inflight_1) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_719 = or(_T_717, _T_718) node _T_720 = lt(watchdog_1, plusarg_reader_1.out) node _T_721 = or(_T_719, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_721, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_726 = and(io.in.d.ready, io.in.d.valid) node _T_727 = or(_T_725, _T_726) when _T_727 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<13>(0h1000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = and(_T_381, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = and(_T_380, _T_388) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_389, UInt<1>(0h1), "") : assert_2 node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<1>(0h0)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_8) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h1)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_9) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<2>(0h2)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_10) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h3)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_11) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_393 connect _WIRE[1], _T_399 connect _WIRE[2], _T_405 connect _WIRE[3], _T_411 connect _WIRE[4], _T_417 connect _WIRE[5], _T_418 connect _WIRE[6], _T_419 connect _WIRE[7], _T_420 connect _WIRE[8], _T_421 connect _WIRE[9], _T_422 connect _WIRE[10], _T_423 connect _WIRE[11], _T_424 connect _WIRE[12], _T_425 connect _WIRE[13], _T_426 connect _WIRE[14], _T_427 connect _WIRE[15], _T_428 connect _WIRE[16], _T_429 connect _WIRE[17], _T_430 connect _WIRE[18], _T_431 connect _WIRE[19], _T_432 connect _WIRE[20], _T_433 connect _WIRE[21], _T_434 connect _WIRE[22], _T_435 connect _WIRE[23], _T_436 connect _WIRE[24], _T_437 connect _WIRE[25], _T_438 connect _WIRE[26], _T_439 connect _WIRE[27], _T_440 connect _WIRE[28], _T_441 connect _WIRE[29], _T_442 node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0)) node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0)) node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0)) node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0)) node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0)) node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0)) node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0)) node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0)) node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_481 = or(_T_451, _T_452) node _T_482 = or(_T_481, _T_453) node _T_483 = or(_T_482, _T_454) node _T_484 = or(_T_483, _T_455) node _T_485 = or(_T_484, _T_456) node _T_486 = or(_T_485, _T_457) node _T_487 = or(_T_486, _T_458) node _T_488 = or(_T_487, _T_459) node _T_489 = or(_T_488, _T_460) node _T_490 = or(_T_489, _T_461) node _T_491 = or(_T_490, _T_462) node _T_492 = or(_T_491, _T_463) node _T_493 = or(_T_492, _T_464) node _T_494 = or(_T_493, _T_465) node _T_495 = or(_T_494, _T_466) node _T_496 = or(_T_495, _T_467) node _T_497 = or(_T_496, _T_468) node _T_498 = or(_T_497, _T_469) node _T_499 = or(_T_498, _T_470) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_472) node _T_502 = or(_T_501, _T_473) node _T_503 = or(_T_502, _T_474) node _T_504 = or(_T_503, _T_475) node _T_505 = or(_T_504, _T_476) node _T_506 = or(_T_505, _T_477) node _T_507 = or(_T_506, _T_478) node _T_508 = or(_T_507, _T_479) node _T_509 = or(_T_508, _T_480) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_509 node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(UInt<1>(0h0), _T_512) node _T_514 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_WIRE_1, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_521, UInt<1>(0h1), "") : assert_3 node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(source_ok, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_528, UInt<1>(0h1), "") : assert_5 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(is_aligned, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_535, UInt<1>(0h1), "") : assert_7 node _T_539 = not(io.in.a.bits.mask) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_540, UInt<1>(0h1), "") : assert_8 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_544, UInt<1>(0h1), "") : assert_9 node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<1>(0h0)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_12) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<1>(0h1)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_13) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<2>(0h2)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_14) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<2>(0h3)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_15) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_602 = or(_T_552, _T_558) node _T_603 = or(_T_602, _T_564) node _T_604 = or(_T_603, _T_570) node _T_605 = or(_T_604, _T_576) node _T_606 = or(_T_605, _T_577) node _T_607 = or(_T_606, _T_578) node _T_608 = or(_T_607, _T_579) node _T_609 = or(_T_608, _T_580) node _T_610 = or(_T_609, _T_581) node _T_611 = or(_T_610, _T_582) node _T_612 = or(_T_611, _T_583) node _T_613 = or(_T_612, _T_584) node _T_614 = or(_T_613, _T_585) node _T_615 = or(_T_614, _T_586) node _T_616 = or(_T_615, _T_587) node _T_617 = or(_T_616, _T_588) node _T_618 = or(_T_617, _T_589) node _T_619 = or(_T_618, _T_590) node _T_620 = or(_T_619, _T_591) node _T_621 = or(_T_620, _T_592) node _T_622 = or(_T_621, _T_593) node _T_623 = or(_T_622, _T_594) node _T_624 = or(_T_623, _T_595) node _T_625 = or(_T_624, _T_596) node _T_626 = or(_T_625, _T_597) node _T_627 = or(_T_626, _T_598) node _T_628 = or(_T_627, _T_599) node _T_629 = or(_T_628, _T_600) node _T_630 = or(_T_629, _T_601) node _T_631 = and(_T_551, _T_630) node _T_632 = or(UInt<1>(0h0), _T_631) node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = and(_T_633, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = and(_T_632, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_641, UInt<1>(0h1), "") : assert_10 node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_646 = shr(io.in.a.bits.source, 2) node _T_647 = eq(_T_646, UInt<1>(0h0)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_16) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_652 = shr(io.in.a.bits.source, 2) node _T_653 = eq(_T_652, UInt<1>(0h1)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_17) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_658 = shr(io.in.a.bits.source, 2) node _T_659 = eq(_T_658, UInt<2>(0h2)) node _T_660 = leq(UInt<1>(0h0), uncommonBits_18) node _T_661 = and(_T_659, _T_660) node _T_662 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<2>(0h3)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_19) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_645 connect _WIRE_2[1], _T_651 connect _WIRE_2[2], _T_657 connect _WIRE_2[3], _T_663 connect _WIRE_2[4], _T_669 connect _WIRE_2[5], _T_670 connect _WIRE_2[6], _T_671 connect _WIRE_2[7], _T_672 connect _WIRE_2[8], _T_673 connect _WIRE_2[9], _T_674 connect _WIRE_2[10], _T_675 connect _WIRE_2[11], _T_676 connect _WIRE_2[12], _T_677 connect _WIRE_2[13], _T_678 connect _WIRE_2[14], _T_679 connect _WIRE_2[15], _T_680 connect _WIRE_2[16], _T_681 connect _WIRE_2[17], _T_682 connect _WIRE_2[18], _T_683 connect _WIRE_2[19], _T_684 connect _WIRE_2[20], _T_685 connect _WIRE_2[21], _T_686 connect _WIRE_2[22], _T_687 connect _WIRE_2[23], _T_688 connect _WIRE_2[24], _T_689 connect _WIRE_2[25], _T_690 connect _WIRE_2[26], _T_691 connect _WIRE_2[27], _T_692 connect _WIRE_2[28], _T_693 connect _WIRE_2[29], _T_694 node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0)) node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0)) node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0)) node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0)) node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0)) node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0)) node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0)) node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0)) node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_733 = or(_T_703, _T_704) node _T_734 = or(_T_733, _T_705) node _T_735 = or(_T_734, _T_706) node _T_736 = or(_T_735, _T_707) node _T_737 = or(_T_736, _T_708) node _T_738 = or(_T_737, _T_709) node _T_739 = or(_T_738, _T_710) node _T_740 = or(_T_739, _T_711) node _T_741 = or(_T_740, _T_712) node _T_742 = or(_T_741, _T_713) node _T_743 = or(_T_742, _T_714) node _T_744 = or(_T_743, _T_715) node _T_745 = or(_T_744, _T_716) node _T_746 = or(_T_745, _T_717) node _T_747 = or(_T_746, _T_718) node _T_748 = or(_T_747, _T_719) node _T_749 = or(_T_748, _T_720) node _T_750 = or(_T_749, _T_721) node _T_751 = or(_T_750, _T_722) node _T_752 = or(_T_751, _T_723) node _T_753 = or(_T_752, _T_724) node _T_754 = or(_T_753, _T_725) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_727) node _T_757 = or(_T_756, _T_728) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_730) node _T_760 = or(_T_759, _T_731) node _T_761 = or(_T_760, _T_732) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_761 node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_764 = and(_T_762, _T_763) node _T_765 = or(UInt<1>(0h0), _T_764) node _T_766 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_771) node _T_773 = and(_WIRE_3, _T_772) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_773, UInt<1>(0h1), "") : assert_11 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(source_ok, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_780, UInt<1>(0h1), "") : assert_13 node _T_784 = asUInt(reset) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(is_aligned, UInt<1>(0h0)) when _T_786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_787, UInt<1>(0h1), "") : assert_15 node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_791, UInt<1>(0h1), "") : assert_16 node _T_795 = not(io.in.a.bits.mask) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_796, UInt<1>(0h1), "") : assert_17 node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_800, UInt<1>(0h1), "") : assert_18 node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_20) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_21) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_22) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_23) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_858 = or(_T_808, _T_814) node _T_859 = or(_T_858, _T_820) node _T_860 = or(_T_859, _T_826) node _T_861 = or(_T_860, _T_832) node _T_862 = or(_T_861, _T_833) node _T_863 = or(_T_862, _T_834) node _T_864 = or(_T_863, _T_835) node _T_865 = or(_T_864, _T_836) node _T_866 = or(_T_865, _T_837) node _T_867 = or(_T_866, _T_838) node _T_868 = or(_T_867, _T_839) node _T_869 = or(_T_868, _T_840) node _T_870 = or(_T_869, _T_841) node _T_871 = or(_T_870, _T_842) node _T_872 = or(_T_871, _T_843) node _T_873 = or(_T_872, _T_844) node _T_874 = or(_T_873, _T_845) node _T_875 = or(_T_874, _T_846) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_848) node _T_878 = or(_T_877, _T_849) node _T_879 = or(_T_878, _T_850) node _T_880 = or(_T_879, _T_851) node _T_881 = or(_T_880, _T_852) node _T_882 = or(_T_881, _T_853) node _T_883 = or(_T_882, _T_854) node _T_884 = or(_T_883, _T_855) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = and(_T_807, _T_886) node _T_888 = or(UInt<1>(0h0), _T_887) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_888, UInt<1>(0h1), "") : assert_19 node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_893 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_894 = and(_T_892, _T_893) node _T_895 = or(UInt<1>(0h0), _T_894) node _T_896 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = and(_T_895, _T_900) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_902, UInt<1>(0h1), "") : assert_20 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(is_aligned, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_912, UInt<1>(0h1), "") : assert_23 node _T_916 = eq(io.in.a.bits.mask, mask) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_916, UInt<1>(0h1), "") : assert_24 node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_920, UInt<1>(0h1), "") : assert_25 node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_924 : node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_927 = and(_T_925, _T_926) node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_929 = shr(io.in.a.bits.source, 2) node _T_930 = eq(_T_929, UInt<1>(0h0)) node _T_931 = leq(UInt<1>(0h0), uncommonBits_24) node _T_932 = and(_T_930, _T_931) node _T_933 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_934 = and(_T_932, _T_933) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_935 = shr(io.in.a.bits.source, 2) node _T_936 = eq(_T_935, UInt<1>(0h1)) node _T_937 = leq(UInt<1>(0h0), uncommonBits_25) node _T_938 = and(_T_936, _T_937) node _T_939 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_940 = and(_T_938, _T_939) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_941 = shr(io.in.a.bits.source, 2) node _T_942 = eq(_T_941, UInt<2>(0h2)) node _T_943 = leq(UInt<1>(0h0), uncommonBits_26) node _T_944 = and(_T_942, _T_943) node _T_945 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_946 = and(_T_944, _T_945) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_947 = shr(io.in.a.bits.source, 2) node _T_948 = eq(_T_947, UInt<2>(0h3)) node _T_949 = leq(UInt<1>(0h0), uncommonBits_27) node _T_950 = and(_T_948, _T_949) node _T_951 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_952 = and(_T_950, _T_951) node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_978 = or(_T_928, _T_934) node _T_979 = or(_T_978, _T_940) node _T_980 = or(_T_979, _T_946) node _T_981 = or(_T_980, _T_952) node _T_982 = or(_T_981, _T_953) node _T_983 = or(_T_982, _T_954) node _T_984 = or(_T_983, _T_955) node _T_985 = or(_T_984, _T_956) node _T_986 = or(_T_985, _T_957) node _T_987 = or(_T_986, _T_958) node _T_988 = or(_T_987, _T_959) node _T_989 = or(_T_988, _T_960) node _T_990 = or(_T_989, _T_961) node _T_991 = or(_T_990, _T_962) node _T_992 = or(_T_991, _T_963) node _T_993 = or(_T_992, _T_964) node _T_994 = or(_T_993, _T_965) node _T_995 = or(_T_994, _T_966) node _T_996 = or(_T_995, _T_967) node _T_997 = or(_T_996, _T_968) node _T_998 = or(_T_997, _T_969) node _T_999 = or(_T_998, _T_970) node _T_1000 = or(_T_999, _T_971) node _T_1001 = or(_T_1000, _T_972) node _T_1002 = or(_T_1001, _T_973) node _T_1003 = or(_T_1002, _T_974) node _T_1004 = or(_T_1003, _T_975) node _T_1005 = or(_T_1004, _T_976) node _T_1006 = or(_T_1005, _T_977) node _T_1007 = and(_T_927, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1010 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = and(_T_1012, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = and(_T_1008, _T_1019) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_26 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(source_ok, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(is_aligned, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1030 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_29 node _T_1034 = eq(io.in.a.bits.mask, mask) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_30 node _T_1038 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1038 : node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1040 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1043 = shr(io.in.a.bits.source, 2) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1048 = and(_T_1046, _T_1047) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1049 = shr(io.in.a.bits.source, 2) node _T_1050 = eq(_T_1049, UInt<1>(0h1)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1055 = shr(io.in.a.bits.source, 2) node _T_1056 = eq(_T_1055, UInt<2>(0h2)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1061 = shr(io.in.a.bits.source, 2) node _T_1062 = eq(_T_1061, UInt<2>(0h3)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1092 = or(_T_1042, _T_1048) node _T_1093 = or(_T_1092, _T_1054) node _T_1094 = or(_T_1093, _T_1060) node _T_1095 = or(_T_1094, _T_1066) node _T_1096 = or(_T_1095, _T_1067) node _T_1097 = or(_T_1096, _T_1068) node _T_1098 = or(_T_1097, _T_1069) node _T_1099 = or(_T_1098, _T_1070) node _T_1100 = or(_T_1099, _T_1071) node _T_1101 = or(_T_1100, _T_1072) node _T_1102 = or(_T_1101, _T_1073) node _T_1103 = or(_T_1102, _T_1074) node _T_1104 = or(_T_1103, _T_1075) node _T_1105 = or(_T_1104, _T_1076) node _T_1106 = or(_T_1105, _T_1077) node _T_1107 = or(_T_1106, _T_1078) node _T_1108 = or(_T_1107, _T_1079) node _T_1109 = or(_T_1108, _T_1080) node _T_1110 = or(_T_1109, _T_1081) node _T_1111 = or(_T_1110, _T_1082) node _T_1112 = or(_T_1111, _T_1083) node _T_1113 = or(_T_1112, _T_1084) node _T_1114 = or(_T_1113, _T_1085) node _T_1115 = or(_T_1114, _T_1086) node _T_1116 = or(_T_1115, _T_1087) node _T_1117 = or(_T_1116, _T_1088) node _T_1118 = or(_T_1117, _T_1089) node _T_1119 = or(_T_1118, _T_1090) node _T_1120 = or(_T_1119, _T_1091) node _T_1121 = and(_T_1041, _T_1120) node _T_1122 = or(UInt<1>(0h0), _T_1121) node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = or(UInt<1>(0h0), _T_1125) node _T_1127 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = and(_T_1126, _T_1131) node _T_1133 = or(UInt<1>(0h0), _T_1132) node _T_1134 = and(_T_1122, _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_31 node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(source_ok, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(is_aligned, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1144 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_34 node _T_1148 = not(mask) node _T_1149 = and(io.in.a.bits.mask, _T_1148) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_35 node _T_1154 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1154 : node _T_1155 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1156 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1159 = shr(io.in.a.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1165 = shr(io.in.a.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1171 = shr(io.in.a.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1177 = shr(io.in.a.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1201 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1202 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1203 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1204 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1205 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1207 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1208 = or(_T_1158, _T_1164) node _T_1209 = or(_T_1208, _T_1170) node _T_1210 = or(_T_1209, _T_1176) node _T_1211 = or(_T_1210, _T_1182) node _T_1212 = or(_T_1211, _T_1183) node _T_1213 = or(_T_1212, _T_1184) node _T_1214 = or(_T_1213, _T_1185) node _T_1215 = or(_T_1214, _T_1186) node _T_1216 = or(_T_1215, _T_1187) node _T_1217 = or(_T_1216, _T_1188) node _T_1218 = or(_T_1217, _T_1189) node _T_1219 = or(_T_1218, _T_1190) node _T_1220 = or(_T_1219, _T_1191) node _T_1221 = or(_T_1220, _T_1192) node _T_1222 = or(_T_1221, _T_1193) node _T_1223 = or(_T_1222, _T_1194) node _T_1224 = or(_T_1223, _T_1195) node _T_1225 = or(_T_1224, _T_1196) node _T_1226 = or(_T_1225, _T_1197) node _T_1227 = or(_T_1226, _T_1198) node _T_1228 = or(_T_1227, _T_1199) node _T_1229 = or(_T_1228, _T_1200) node _T_1230 = or(_T_1229, _T_1201) node _T_1231 = or(_T_1230, _T_1202) node _T_1232 = or(_T_1231, _T_1203) node _T_1233 = or(_T_1232, _T_1204) node _T_1234 = or(_T_1233, _T_1205) node _T_1235 = or(_T_1234, _T_1206) node _T_1236 = or(_T_1235, _T_1207) node _T_1237 = and(_T_1157, _T_1236) node _T_1238 = or(UInt<1>(0h0), _T_1237) node _T_1239 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1240 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1241 = and(_T_1239, _T_1240) node _T_1242 = or(UInt<1>(0h0), _T_1241) node _T_1243 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<13>(0h1000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = and(_T_1242, _T_1247) node _T_1249 = or(UInt<1>(0h0), _T_1248) node _T_1250 = and(_T_1238, _T_1249) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_36 node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(source_ok, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(is_aligned, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1260 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_39 node _T_1264 = eq(io.in.a.bits.mask, mask) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_40 node _T_1268 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1268 : node _T_1269 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1270 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1271 = and(_T_1269, _T_1270) node _T_1272 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1273 = shr(io.in.a.bits.source, 2) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) node _T_1275 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1276 = and(_T_1274, _T_1275) node _T_1277 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1278 = and(_T_1276, _T_1277) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1279 = shr(io.in.a.bits.source, 2) node _T_1280 = eq(_T_1279, UInt<1>(0h1)) node _T_1281 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1284 = and(_T_1282, _T_1283) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1285 = shr(io.in.a.bits.source, 2) node _T_1286 = eq(_T_1285, UInt<2>(0h2)) node _T_1287 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1288 = and(_T_1286, _T_1287) node _T_1289 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1290 = and(_T_1288, _T_1289) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1291 = shr(io.in.a.bits.source, 2) node _T_1292 = eq(_T_1291, UInt<2>(0h3)) node _T_1293 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1294 = and(_T_1292, _T_1293) node _T_1295 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1312 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1313 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1315 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1316 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1317 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1318 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1319 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1320 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1321 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1322 = or(_T_1272, _T_1278) node _T_1323 = or(_T_1322, _T_1284) node _T_1324 = or(_T_1323, _T_1290) node _T_1325 = or(_T_1324, _T_1296) node _T_1326 = or(_T_1325, _T_1297) node _T_1327 = or(_T_1326, _T_1298) node _T_1328 = or(_T_1327, _T_1299) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1301) node _T_1331 = or(_T_1330, _T_1302) node _T_1332 = or(_T_1331, _T_1303) node _T_1333 = or(_T_1332, _T_1304) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1306) node _T_1336 = or(_T_1335, _T_1307) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1309) node _T_1339 = or(_T_1338, _T_1310) node _T_1340 = or(_T_1339, _T_1311) node _T_1341 = or(_T_1340, _T_1312) node _T_1342 = or(_T_1341, _T_1313) node _T_1343 = or(_T_1342, _T_1314) node _T_1344 = or(_T_1343, _T_1315) node _T_1345 = or(_T_1344, _T_1316) node _T_1346 = or(_T_1345, _T_1317) node _T_1347 = or(_T_1346, _T_1318) node _T_1348 = or(_T_1347, _T_1319) node _T_1349 = or(_T_1348, _T_1320) node _T_1350 = or(_T_1349, _T_1321) node _T_1351 = and(_T_1271, _T_1350) node _T_1352 = or(UInt<1>(0h0), _T_1351) node _T_1353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1354 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1355 = and(_T_1353, _T_1354) node _T_1356 = or(UInt<1>(0h0), _T_1355) node _T_1357 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1358 = cvt(_T_1357) node _T_1359 = and(_T_1358, asSInt(UInt<13>(0h1000))) node _T_1360 = asSInt(_T_1359) node _T_1361 = eq(_T_1360, asSInt(UInt<1>(0h0))) node _T_1362 = and(_T_1356, _T_1361) node _T_1363 = or(UInt<1>(0h0), _T_1362) node _T_1364 = and(_T_1352, _T_1363) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_41 node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(source_ok, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(is_aligned, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1374 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_44 node _T_1378 = eq(io.in.a.bits.mask, mask) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_45 node _T_1382 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1382 : node _T_1383 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1384 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1385 = and(_T_1383, _T_1384) node _T_1386 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1387 = shr(io.in.a.bits.source, 2) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1393 = shr(io.in.a.bits.source, 2) node _T_1394 = eq(_T_1393, UInt<1>(0h1)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1399 = shr(io.in.a.bits.source, 2) node _T_1400 = eq(_T_1399, UInt<2>(0h2)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1405 = shr(io.in.a.bits.source, 2) node _T_1406 = eq(_T_1405, UInt<2>(0h3)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1410 = and(_T_1408, _T_1409) node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1429 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1430 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1431 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1434 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1435 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1436 = or(_T_1386, _T_1392) node _T_1437 = or(_T_1436, _T_1398) node _T_1438 = or(_T_1437, _T_1404) node _T_1439 = or(_T_1438, _T_1410) node _T_1440 = or(_T_1439, _T_1411) node _T_1441 = or(_T_1440, _T_1412) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1414) node _T_1444 = or(_T_1443, _T_1415) node _T_1445 = or(_T_1444, _T_1416) node _T_1446 = or(_T_1445, _T_1417) node _T_1447 = or(_T_1446, _T_1418) node _T_1448 = or(_T_1447, _T_1419) node _T_1449 = or(_T_1448, _T_1420) node _T_1450 = or(_T_1449, _T_1421) node _T_1451 = or(_T_1450, _T_1422) node _T_1452 = or(_T_1451, _T_1423) node _T_1453 = or(_T_1452, _T_1424) node _T_1454 = or(_T_1453, _T_1425) node _T_1455 = or(_T_1454, _T_1426) node _T_1456 = or(_T_1455, _T_1427) node _T_1457 = or(_T_1456, _T_1428) node _T_1458 = or(_T_1457, _T_1429) node _T_1459 = or(_T_1458, _T_1430) node _T_1460 = or(_T_1459, _T_1431) node _T_1461 = or(_T_1460, _T_1432) node _T_1462 = or(_T_1461, _T_1433) node _T_1463 = or(_T_1462, _T_1434) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = and(_T_1385, _T_1464) node _T_1466 = or(UInt<1>(0h0), _T_1465) node _T_1467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = or(UInt<1>(0h0), _T_1469) node _T_1471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = and(_T_1470, _T_1475) node _T_1477 = or(UInt<1>(0h0), _T_1476) node _T_1478 = and(_T_1466, _T_1477) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_46 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(source_ok, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(is_aligned, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1488 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_49 node _T_1492 = eq(io.in.a.bits.mask, mask) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_50 node _T_1496 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(_T_1496, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1496, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1500 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1504 : node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok_1, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1508 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_54 node _T_1512 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_55 node _T_1516 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_56 node _T_1520 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_57 node _T_1524 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1524 : node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(source_ok_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(sink_ok, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1531 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(_T_1531, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1531, UInt<1>(0h1), "") : assert_60 node _T_1535 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_61 node _T_1539 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_62 node _T_1543 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_63 node _T_1547 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1548 = or(UInt<1>(0h1), _T_1547) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_64 node _T_1552 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1552 : node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(source_ok_1, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(sink_ok, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1559 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_67 node _T_1563 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_68 node _T_1567 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_69 node _T_1571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1572 = or(_T_1571, io.in.d.bits.corrupt) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_70 node _T_1576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1577 = or(UInt<1>(0h1), _T_1576) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_71 node _T_1581 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1581 : node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(source_ok_1, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_73 node _T_1589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_74 node _T_1593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1594 = or(UInt<1>(0h1), _T_1593) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_75 node _T_1598 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1598 : node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(source_ok_1, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1602 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(_T_1602, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1602, UInt<1>(0h1), "") : assert_77 node _T_1606 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1607 = or(_T_1606, io.in.d.bits.corrupt) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_78 node _T_1611 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1612 = or(UInt<1>(0h1), _T_1611) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_79 node _T_1616 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1616 : node _T_1617 = asUInt(reset) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) when _T_1618 : node _T_1619 = eq(source_ok_1, UInt<1>(0h0)) when _T_1619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1620 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(_T_1620, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1620, UInt<1>(0h1), "") : assert_81 node _T_1624 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(_T_1624, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1624, UInt<1>(0h1), "") : assert_82 node _T_1628 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1629 = or(UInt<1>(0h1), _T_1628) node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(_T_1629, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1629, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1633 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(_T_1633, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1633, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1637 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1641 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1642 = asUInt(reset) node _T_1643 = eq(_T_1642, UInt<1>(0h0)) when _T_1643 : node _T_1644 = eq(_T_1641, UInt<1>(0h0)) when _T_1644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1641, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1645 = eq(a_first, UInt<1>(0h0)) node _T_1646 = and(io.in.a.valid, _T_1645) when _T_1646 : node _T_1647 = eq(io.in.a.bits.opcode, opcode) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_87 node _T_1651 = eq(io.in.a.bits.param, param) node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(_T_1651, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1651, UInt<1>(0h1), "") : assert_88 node _T_1655 = eq(io.in.a.bits.size, size) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_89 node _T_1659 = eq(io.in.a.bits.source, source) node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(_T_1659, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1659, UInt<1>(0h1), "") : assert_90 node _T_1663 = eq(io.in.a.bits.address, address) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_91 node _T_1667 = and(io.in.a.ready, io.in.a.valid) node _T_1668 = and(_T_1667, a_first) when _T_1668 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1669 = eq(d_first, UInt<1>(0h0)) node _T_1670 = and(io.in.d.valid, _T_1669) when _T_1670 : node _T_1671 = eq(io.in.d.bits.opcode, opcode_1) node _T_1672 = asUInt(reset) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(_T_1671, UInt<1>(0h0)) when _T_1674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1671, UInt<1>(0h1), "") : assert_92 node _T_1675 = eq(io.in.d.bits.param, param_1) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_93 node _T_1679 = eq(io.in.d.bits.size, size_1) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_94 node _T_1683 = eq(io.in.d.bits.source, source_1) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_95 node _T_1687 = eq(io.in.d.bits.sink, sink) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_96 node _T_1691 = eq(io.in.d.bits.denied, denied) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_97 node _T_1695 = and(io.in.d.ready, io.in.d.valid) node _T_1696 = and(_T_1695, d_first) when _T_1696 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1697 = and(io.in.a.valid, a_first_1) node _T_1698 = and(_T_1697, UInt<1>(0h1)) when _T_1698 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first_1) node _T_1701 = and(_T_1700, UInt<1>(0h1)) when _T_1701 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1702 = dshr(inflight, io.in.a.bits.source) node _T_1703 = bits(_T_1702, 0, 0) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1708 = and(io.in.d.valid, d_first_1) node _T_1709 = and(_T_1708, UInt<1>(0h1)) node _T_1710 = eq(d_release_ack, UInt<1>(0h0)) node _T_1711 = and(_T_1709, _T_1710) when _T_1711 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1712 = and(io.in.d.ready, io.in.d.valid) node _T_1713 = and(_T_1712, d_first_1) node _T_1714 = and(_T_1713, UInt<1>(0h1)) node _T_1715 = eq(d_release_ack, UInt<1>(0h0)) node _T_1716 = and(_T_1714, _T_1715) when _T_1716 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1717 = and(io.in.d.valid, d_first_1) node _T_1718 = and(_T_1717, UInt<1>(0h1)) node _T_1719 = eq(d_release_ack, UInt<1>(0h0)) node _T_1720 = and(_T_1718, _T_1719) when _T_1720 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1721 = dshr(inflight, io.in.d.bits.source) node _T_1722 = bits(_T_1721, 0, 0) node _T_1723 = or(_T_1722, same_cycle_resp) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1727 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1728 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1729 = or(_T_1727, _T_1728) node _T_1730 = asUInt(reset) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) when _T_1731 : node _T_1732 = eq(_T_1729, UInt<1>(0h0)) when _T_1732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1729, UInt<1>(0h1), "") : assert_100 node _T_1733 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1734 = asUInt(reset) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) when _T_1735 : node _T_1736 = eq(_T_1733, UInt<1>(0h0)) when _T_1736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1733, UInt<1>(0h1), "") : assert_101 else : node _T_1737 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1738 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1739 = or(_T_1737, _T_1738) node _T_1740 = asUInt(reset) node _T_1741 = eq(_T_1740, UInt<1>(0h0)) when _T_1741 : node _T_1742 = eq(_T_1739, UInt<1>(0h0)) when _T_1742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1739, UInt<1>(0h1), "") : assert_102 node _T_1743 = eq(io.in.d.bits.size, a_size_lookup) node _T_1744 = asUInt(reset) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) when _T_1745 : node _T_1746 = eq(_T_1743, UInt<1>(0h0)) when _T_1746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1743, UInt<1>(0h1), "") : assert_103 node _T_1747 = and(io.in.d.valid, d_first_1) node _T_1748 = and(_T_1747, a_first_1) node _T_1749 = and(_T_1748, io.in.a.valid) node _T_1750 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1751 = and(_T_1749, _T_1750) node _T_1752 = eq(d_release_ack, UInt<1>(0h0)) node _T_1753 = and(_T_1751, _T_1752) when _T_1753 : node _T_1754 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1755 = or(_T_1754, io.in.a.ready) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_104 node _T_1759 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1760 = orr(a_set_wo_ready) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = or(_T_1759, _T_1761) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_78 node _T_1766 = orr(inflight) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) node _T_1768 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1769 = or(_T_1767, _T_1768) node _T_1770 = lt(watchdog, plusarg_reader.out) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1775 = and(io.in.a.ready, io.in.a.valid) node _T_1776 = and(io.in.d.ready, io.in.d.valid) node _T_1777 = or(_T_1775, _T_1776) when _T_1777 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1778 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1779 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1780 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1781 = and(_T_1779, _T_1780) node _T_1782 = and(_T_1778, _T_1781) when _T_1782 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1783 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1784 = and(_T_1783, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1785 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1786 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = and(_T_1784, _T_1787) when _T_1788 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1789 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1790 = bits(_T_1789, 0, 0) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1795 = and(io.in.d.valid, d_first_2) node _T_1796 = and(_T_1795, UInt<1>(0h1)) node _T_1797 = and(_T_1796, d_release_ack_1) when _T_1797 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1798 = and(io.in.d.ready, io.in.d.valid) node _T_1799 = and(_T_1798, d_first_2) node _T_1800 = and(_T_1799, UInt<1>(0h1)) node _T_1801 = and(_T_1800, d_release_ack_1) when _T_1801 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1802 = and(io.in.d.valid, d_first_2) node _T_1803 = and(_T_1802, UInt<1>(0h1)) node _T_1804 = and(_T_1803, d_release_ack_1) when _T_1804 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1805 = dshr(inflight_1, io.in.d.bits.source) node _T_1806 = bits(_T_1805, 0, 0) node _T_1807 = or(_T_1806, same_cycle_resp_1) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1811 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1812 = asUInt(reset) node _T_1813 = eq(_T_1812, UInt<1>(0h0)) when _T_1813 : node _T_1814 = eq(_T_1811, UInt<1>(0h0)) when _T_1814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1811, UInt<1>(0h1), "") : assert_109 else : node _T_1815 = eq(io.in.d.bits.size, c_size_lookup) node _T_1816 = asUInt(reset) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) when _T_1817 : node _T_1818 = eq(_T_1815, UInt<1>(0h0)) when _T_1818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1815, UInt<1>(0h1), "") : assert_110 node _T_1819 = and(io.in.d.valid, d_first_2) node _T_1820 = and(_T_1819, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1821 = and(_T_1820, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1822 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = and(_T_1823, d_release_ack_1) node _T_1825 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1826 = and(_T_1824, _T_1825) when _T_1826 : node _T_1827 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1828 = or(_T_1827, _WIRE_27.ready) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_111 node _T_1832 = orr(c_set_wo_ready) when _T_1832 : node _T_1833 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1834 = asUInt(reset) node _T_1835 = eq(_T_1834, UInt<1>(0h0)) when _T_1835 : node _T_1836 = eq(_T_1833, UInt<1>(0h0)) when _T_1836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1833, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_79 node _T_1837 = orr(inflight_1) node _T_1838 = eq(_T_1837, UInt<1>(0h0)) node _T_1839 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1840 = or(_T_1838, _T_1839) node _T_1841 = lt(watchdog_1, plusarg_reader_1.out) node _T_1842 = or(_T_1840, _T_1841) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1846 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1847 = and(io.in.d.ready, io.in.d.valid) node _T_1848 = or(_T_1846, _T_1847) when _T_1848 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module BranchPredictor : input clock : Clock input reset : Reset output io : { flip f0_req : { valid : UInt<1>, bits : { pc : UInt<40>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}}}, resp : { f1 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]}, f2 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]}, f3 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]}}, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<8>, pc : UInt<40>, br_mask : UInt<8>, cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[2], target : UInt<40>, meta : UInt<120>[2]}}} inst banked_predictors_0 of ComposedBranchPredictorBank connect banked_predictors_0.clock, clock connect banked_predictors_0.reset, reset inst banked_predictors_1 of ComposedBranchPredictorBank_1 connect banked_predictors_1.clock, clock connect banked_predictors_1.reset, reset inst banked_lhist_providers_0 of NullLocalBranchPredictorBank connect banked_lhist_providers_0.clock, clock connect banked_lhist_providers_0.reset, reset inst banked_lhist_providers_1 of NullLocalBranchPredictorBank_1 connect banked_lhist_providers_1.clock, clock connect banked_lhist_providers_1.reset, reset wire _banked_predictors_0_io_resp_in_0_WIRE : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]} connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken, UInt<1>(0h0) connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal connect banked_predictors_0.io.resp_in[0].f3[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br connect banked_predictors_0.io.resp_in[0].f3[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal connect banked_predictors_0.io.resp_in[0].f3[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br connect banked_predictors_0.io.resp_in[0].f3[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal connect banked_predictors_0.io.resp_in[0].f3[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br connect banked_predictors_0.io.resp_in[0].f3[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal connect banked_predictors_0.io.resp_in[0].f3[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br connect banked_predictors_0.io.resp_in[0].f3[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal connect banked_predictors_0.io.resp_in[0].f2[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br connect banked_predictors_0.io.resp_in[0].f2[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal connect banked_predictors_0.io.resp_in[0].f2[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br connect banked_predictors_0.io.resp_in[0].f2[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal connect banked_predictors_0.io.resp_in[0].f2[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br connect banked_predictors_0.io.resp_in[0].f2[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal connect banked_predictors_0.io.resp_in[0].f2[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br connect banked_predictors_0.io.resp_in[0].f2[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal connect banked_predictors_0.io.resp_in[0].f1[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br connect banked_predictors_0.io.resp_in[0].f1[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal connect banked_predictors_0.io.resp_in[0].f1[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br connect banked_predictors_0.io.resp_in[0].f1[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal connect banked_predictors_0.io.resp_in[0].f1[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br connect banked_predictors_0.io.resp_in[0].f1[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal connect banked_predictors_0.io.resp_in[0].f1[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br connect banked_predictors_0.io.resp_in[0].f1[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken wire _banked_predictors_1_io_resp_in_0_WIRE : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]} connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].taken, UInt<1>(0h0) connect banked_predictors_1.io.resp_in[0].f3[0].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[0].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[0].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_jal connect banked_predictors_1.io.resp_in[0].f3[0].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_br connect banked_predictors_1.io.resp_in[0].f3[0].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].taken connect banked_predictors_1.io.resp_in[0].f3[1].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[1].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[1].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_jal connect banked_predictors_1.io.resp_in[0].f3[1].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_br connect banked_predictors_1.io.resp_in[0].f3[1].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].taken connect banked_predictors_1.io.resp_in[0].f3[2].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[2].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[2].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_jal connect banked_predictors_1.io.resp_in[0].f3[2].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_br connect banked_predictors_1.io.resp_in[0].f3[2].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].taken connect banked_predictors_1.io.resp_in[0].f3[3].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[3].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[3].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_jal connect banked_predictors_1.io.resp_in[0].f3[3].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_br connect banked_predictors_1.io.resp_in[0].f3[3].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].taken connect banked_predictors_1.io.resp_in[0].f2[0].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[0].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[0].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_jal connect banked_predictors_1.io.resp_in[0].f2[0].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_br connect banked_predictors_1.io.resp_in[0].f2[0].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].taken connect banked_predictors_1.io.resp_in[0].f2[1].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[1].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[1].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_jal connect banked_predictors_1.io.resp_in[0].f2[1].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_br connect banked_predictors_1.io.resp_in[0].f2[1].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].taken connect banked_predictors_1.io.resp_in[0].f2[2].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[2].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[2].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_jal connect banked_predictors_1.io.resp_in[0].f2[2].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_br connect banked_predictors_1.io.resp_in[0].f2[2].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].taken connect banked_predictors_1.io.resp_in[0].f2[3].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[3].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[3].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_jal connect banked_predictors_1.io.resp_in[0].f2[3].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_br connect banked_predictors_1.io.resp_in[0].f2[3].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].taken connect banked_predictors_1.io.resp_in[0].f1[0].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[0].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[0].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_jal connect banked_predictors_1.io.resp_in[0].f1[0].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_br connect banked_predictors_1.io.resp_in[0].f1[0].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].taken connect banked_predictors_1.io.resp_in[0].f1[1].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[1].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[1].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_jal connect banked_predictors_1.io.resp_in[0].f1[1].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_br connect banked_predictors_1.io.resp_in[0].f1[1].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].taken connect banked_predictors_1.io.resp_in[0].f1[2].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[2].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[2].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_jal connect banked_predictors_1.io.resp_in[0].f1[2].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_br connect banked_predictors_1.io.resp_in[0].f1[2].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].taken connect banked_predictors_1.io.resp_in[0].f1[3].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[3].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[3].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_jal connect banked_predictors_1.io.resp_in[0].f1[3].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_br connect banked_predictors_1.io.resp_in[0].f1[3].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].taken connect banked_predictors_0.io.f1_lhist, banked_lhist_providers_0.io.f1_lhist connect banked_predictors_1.io.f1_lhist, banked_lhist_providers_1.io.f1_lhist node _T = bits(io.f0_req.bits.pc, 3, 3) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : connect banked_lhist_providers_0.io.f0_valid, io.f0_req.valid node _banked_lhist_providers_0_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_lhist_providers_0_io_f0_pc_T_1 = or(_banked_lhist_providers_0_io_f0_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_0_io_f0_pc_T_2 = not(_banked_lhist_providers_0_io_f0_pc_T_1) connect banked_lhist_providers_0.io.f0_pc, _banked_lhist_providers_0_io_f0_pc_T_2 connect banked_lhist_providers_1.io.f0_valid, io.f0_req.valid node _banked_lhist_providers_1_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_lhist_providers_1_io_f0_pc_T_1 = or(_banked_lhist_providers_1_io_f0_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_1_io_f0_pc_T_2 = not(_banked_lhist_providers_1_io_f0_pc_T_1) node _banked_lhist_providers_1_io_f0_pc_T_3 = add(_banked_lhist_providers_1_io_f0_pc_T_2, UInt<4>(0h8)) node _banked_lhist_providers_1_io_f0_pc_T_4 = tail(_banked_lhist_providers_1_io_f0_pc_T_3, 1) connect banked_lhist_providers_1.io.f0_pc, _banked_lhist_providers_1_io_f0_pc_T_4 connect banked_predictors_0.io.f0_valid, io.f0_req.valid connect banked_predictors_0.io.f0_pc, io.f0_req.bits.pc node banked_predictors_0_io_f0_mask_idx = bits(io.f0_req.bits.pc, 3, 1) node banked_predictors_0_io_f0_mask_shamt = bits(banked_predictors_0_io_f0_mask_idx, 1, 0) node _banked_predictors_0_io_f0_mask_end_mask_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_predictors_0_io_f0_mask_end_mask_T_1 = eq(_banked_predictors_0_io_f0_mask_end_mask_T, UInt<3>(0h7)) node _banked_predictors_0_io_f0_mask_end_mask_T_2 = and(UInt<1>(0h1), _banked_predictors_0_io_f0_mask_end_mask_T_1) node _banked_predictors_0_io_f0_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _banked_predictors_0_io_f0_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node banked_predictors_0_io_f0_mask_end_mask = mux(_banked_predictors_0_io_f0_mask_end_mask_T_2, _banked_predictors_0_io_f0_mask_end_mask_T_3, _banked_predictors_0_io_f0_mask_end_mask_T_4) node _banked_predictors_0_io_f0_mask_T = dshl(UInt<8>(0hff), banked_predictors_0_io_f0_mask_shamt) node _banked_predictors_0_io_f0_mask_T_1 = and(_banked_predictors_0_io_f0_mask_T, banked_predictors_0_io_f0_mask_end_mask) connect banked_predictors_0.io.f0_mask, _banked_predictors_0_io_f0_mask_T_1 connect banked_predictors_1.io.f0_valid, io.f0_req.valid node _banked_predictors_1_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_predictors_1_io_f0_pc_T_1 = or(_banked_predictors_1_io_f0_pc_T, UInt<3>(0h7)) node _banked_predictors_1_io_f0_pc_T_2 = not(_banked_predictors_1_io_f0_pc_T_1) node _banked_predictors_1_io_f0_pc_T_3 = add(_banked_predictors_1_io_f0_pc_T_2, UInt<4>(0h8)) node _banked_predictors_1_io_f0_pc_T_4 = tail(_banked_predictors_1_io_f0_pc_T_3, 1) connect banked_predictors_1.io.f0_pc, _banked_predictors_1_io_f0_pc_T_4 node _banked_predictors_1_io_f0_mask_T = not(UInt<4>(0h0)) connect banked_predictors_1.io.f0_mask, _banked_predictors_1_io_f0_mask_T else : node _banked_lhist_providers_0_io_f0_valid_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_lhist_providers_0_io_f0_valid_T_1 = eq(_banked_lhist_providers_0_io_f0_valid_T, UInt<3>(0h7)) node _banked_lhist_providers_0_io_f0_valid_T_2 = and(UInt<1>(0h1), _banked_lhist_providers_0_io_f0_valid_T_1) node _banked_lhist_providers_0_io_f0_valid_T_3 = eq(_banked_lhist_providers_0_io_f0_valid_T_2, UInt<1>(0h0)) node _banked_lhist_providers_0_io_f0_valid_T_4 = and(io.f0_req.valid, _banked_lhist_providers_0_io_f0_valid_T_3) connect banked_lhist_providers_0.io.f0_valid, _banked_lhist_providers_0_io_f0_valid_T_4 node _banked_lhist_providers_0_io_f0_pc_T_3 = not(io.f0_req.bits.pc) node _banked_lhist_providers_0_io_f0_pc_T_4 = or(_banked_lhist_providers_0_io_f0_pc_T_3, UInt<3>(0h7)) node _banked_lhist_providers_0_io_f0_pc_T_5 = not(_banked_lhist_providers_0_io_f0_pc_T_4) node _banked_lhist_providers_0_io_f0_pc_T_6 = add(_banked_lhist_providers_0_io_f0_pc_T_5, UInt<4>(0h8)) node _banked_lhist_providers_0_io_f0_pc_T_7 = tail(_banked_lhist_providers_0_io_f0_pc_T_6, 1) connect banked_lhist_providers_0.io.f0_pc, _banked_lhist_providers_0_io_f0_pc_T_7 connect banked_lhist_providers_1.io.f0_valid, io.f0_req.valid node _banked_lhist_providers_1_io_f0_pc_T_5 = not(io.f0_req.bits.pc) node _banked_lhist_providers_1_io_f0_pc_T_6 = or(_banked_lhist_providers_1_io_f0_pc_T_5, UInt<3>(0h7)) node _banked_lhist_providers_1_io_f0_pc_T_7 = not(_banked_lhist_providers_1_io_f0_pc_T_6) connect banked_lhist_providers_1.io.f0_pc, _banked_lhist_providers_1_io_f0_pc_T_7 node _banked_predictors_0_io_f0_valid_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_predictors_0_io_f0_valid_T_1 = eq(_banked_predictors_0_io_f0_valid_T, UInt<3>(0h7)) node _banked_predictors_0_io_f0_valid_T_2 = and(UInt<1>(0h1), _banked_predictors_0_io_f0_valid_T_1) node _banked_predictors_0_io_f0_valid_T_3 = eq(_banked_predictors_0_io_f0_valid_T_2, UInt<1>(0h0)) node _banked_predictors_0_io_f0_valid_T_4 = and(io.f0_req.valid, _banked_predictors_0_io_f0_valid_T_3) connect banked_predictors_0.io.f0_valid, _banked_predictors_0_io_f0_valid_T_4 node _banked_predictors_0_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_predictors_0_io_f0_pc_T_1 = or(_banked_predictors_0_io_f0_pc_T, UInt<3>(0h7)) node _banked_predictors_0_io_f0_pc_T_2 = not(_banked_predictors_0_io_f0_pc_T_1) node _banked_predictors_0_io_f0_pc_T_3 = add(_banked_predictors_0_io_f0_pc_T_2, UInt<4>(0h8)) node _banked_predictors_0_io_f0_pc_T_4 = tail(_banked_predictors_0_io_f0_pc_T_3, 1) connect banked_predictors_0.io.f0_pc, _banked_predictors_0_io_f0_pc_T_4 node _banked_predictors_0_io_f0_mask_T_2 = not(UInt<4>(0h0)) connect banked_predictors_0.io.f0_mask, _banked_predictors_0_io_f0_mask_T_2 connect banked_predictors_1.io.f0_valid, io.f0_req.valid connect banked_predictors_1.io.f0_pc, io.f0_req.bits.pc node banked_predictors_1_io_f0_mask_idx = bits(io.f0_req.bits.pc, 3, 1) node banked_predictors_1_io_f0_mask_shamt = bits(banked_predictors_1_io_f0_mask_idx, 1, 0) node _banked_predictors_1_io_f0_mask_end_mask_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_predictors_1_io_f0_mask_end_mask_T_1 = eq(_banked_predictors_1_io_f0_mask_end_mask_T, UInt<3>(0h7)) node _banked_predictors_1_io_f0_mask_end_mask_T_2 = and(UInt<1>(0h1), _banked_predictors_1_io_f0_mask_end_mask_T_1) node _banked_predictors_1_io_f0_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _banked_predictors_1_io_f0_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node banked_predictors_1_io_f0_mask_end_mask = mux(_banked_predictors_1_io_f0_mask_end_mask_T_2, _banked_predictors_1_io_f0_mask_end_mask_T_3, _banked_predictors_1_io_f0_mask_end_mask_T_4) node _banked_predictors_1_io_f0_mask_T_1 = dshl(UInt<8>(0hff), banked_predictors_1_io_f0_mask_shamt) node _banked_predictors_1_io_f0_mask_T_2 = and(_banked_predictors_1_io_f0_mask_T_1, banked_predictors_1_io_f0_mask_end_mask) connect banked_predictors_1.io.f0_mask, _banked_predictors_1_io_f0_mask_T_2 node _T_2 = bits(io.f0_req.bits.pc, 3, 3) node _T_3 = eq(_T_2, UInt<1>(0h0)) reg REG : UInt<1>, clock connect REG, _T_3 when REG : reg banked_predictors_0_io_f1_ghist_REG : UInt, clock connect banked_predictors_0_io_f1_ghist_REG, io.f0_req.bits.ghist.old_history connect banked_predictors_0.io.f1_ghist, banked_predictors_0_io_f1_ghist_REG node _banked_predictors_1_io_f1_ghist_T = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_1_io_f1_ghist_T_1 = or(_banked_predictors_1_io_f1_ghist_T, UInt<1>(0h1)) node _banked_predictors_1_io_f1_ghist_T_2 = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_1_io_f1_ghist_T_3 = mux(io.f0_req.bits.ghist.new_saw_branch_not_taken, _banked_predictors_1_io_f1_ghist_T_2, io.f0_req.bits.ghist.old_history) node _banked_predictors_1_io_f1_ghist_T_4 = mux(io.f0_req.bits.ghist.new_saw_branch_taken, _banked_predictors_1_io_f1_ghist_T_1, _banked_predictors_1_io_f1_ghist_T_3) reg banked_predictors_1_io_f1_ghist_REG : UInt, clock connect banked_predictors_1_io_f1_ghist_REG, _banked_predictors_1_io_f1_ghist_T_4 connect banked_predictors_1.io.f1_ghist, banked_predictors_1_io_f1_ghist_REG else : node _banked_predictors_0_io_f1_ghist_T = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_0_io_f1_ghist_T_1 = or(_banked_predictors_0_io_f1_ghist_T, UInt<1>(0h1)) node _banked_predictors_0_io_f1_ghist_T_2 = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_0_io_f1_ghist_T_3 = mux(io.f0_req.bits.ghist.new_saw_branch_not_taken, _banked_predictors_0_io_f1_ghist_T_2, io.f0_req.bits.ghist.old_history) node _banked_predictors_0_io_f1_ghist_T_4 = mux(io.f0_req.bits.ghist.new_saw_branch_taken, _banked_predictors_0_io_f1_ghist_T_1, _banked_predictors_0_io_f1_ghist_T_3) reg banked_predictors_0_io_f1_ghist_REG_1 : UInt, clock connect banked_predictors_0_io_f1_ghist_REG_1, _banked_predictors_0_io_f1_ghist_T_4 connect banked_predictors_0.io.f1_ghist, banked_predictors_0_io_f1_ghist_REG_1 reg banked_predictors_1_io_f1_ghist_REG_1 : UInt, clock connect banked_predictors_1_io_f1_ghist_REG_1, io.f0_req.bits.ghist.old_history connect banked_predictors_1.io.f1_ghist, banked_predictors_1_io_f1_ghist_REG_1 node _banked_lhist_providers_0_io_f3_taken_br_T = and(banked_predictors_0.io.resp.f3[0].is_br, banked_predictors_0.io.resp.f3[0].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_1 = and(_banked_lhist_providers_0_io_f3_taken_br_T, banked_predictors_0.io.resp.f3[0].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_2 = and(banked_predictors_0.io.resp.f3[1].is_br, banked_predictors_0.io.resp.f3[1].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_3 = and(_banked_lhist_providers_0_io_f3_taken_br_T_2, banked_predictors_0.io.resp.f3[1].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_4 = and(banked_predictors_0.io.resp.f3[2].is_br, banked_predictors_0.io.resp.f3[2].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_5 = and(_banked_lhist_providers_0_io_f3_taken_br_T_4, banked_predictors_0.io.resp.f3[2].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_6 = and(banked_predictors_0.io.resp.f3[3].is_br, banked_predictors_0.io.resp.f3[3].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_7 = and(_banked_lhist_providers_0_io_f3_taken_br_T_6, banked_predictors_0.io.resp.f3[3].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_8 = or(_banked_lhist_providers_0_io_f3_taken_br_T_1, _banked_lhist_providers_0_io_f3_taken_br_T_3) node _banked_lhist_providers_0_io_f3_taken_br_T_9 = or(_banked_lhist_providers_0_io_f3_taken_br_T_8, _banked_lhist_providers_0_io_f3_taken_br_T_5) node _banked_lhist_providers_0_io_f3_taken_br_T_10 = or(_banked_lhist_providers_0_io_f3_taken_br_T_9, _banked_lhist_providers_0_io_f3_taken_br_T_7) connect banked_lhist_providers_0.io.f3_taken_br, _banked_lhist_providers_0_io_f3_taken_br_T_10 node _banked_lhist_providers_1_io_f3_taken_br_T = and(banked_predictors_1.io.resp.f3[0].is_br, banked_predictors_1.io.resp.f3[0].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_1 = and(_banked_lhist_providers_1_io_f3_taken_br_T, banked_predictors_1.io.resp.f3[0].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_2 = and(banked_predictors_1.io.resp.f3[1].is_br, banked_predictors_1.io.resp.f3[1].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_3 = and(_banked_lhist_providers_1_io_f3_taken_br_T_2, banked_predictors_1.io.resp.f3[1].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_4 = and(banked_predictors_1.io.resp.f3[2].is_br, banked_predictors_1.io.resp.f3[2].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_5 = and(_banked_lhist_providers_1_io_f3_taken_br_T_4, banked_predictors_1.io.resp.f3[2].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_6 = and(banked_predictors_1.io.resp.f3[3].is_br, banked_predictors_1.io.resp.f3[3].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_7 = and(_banked_lhist_providers_1_io_f3_taken_br_T_6, banked_predictors_1.io.resp.f3[3].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_8 = or(_banked_lhist_providers_1_io_f3_taken_br_T_1, _banked_lhist_providers_1_io_f3_taken_br_T_3) node _banked_lhist_providers_1_io_f3_taken_br_T_9 = or(_banked_lhist_providers_1_io_f3_taken_br_T_8, _banked_lhist_providers_1_io_f3_taken_br_T_5) node _banked_lhist_providers_1_io_f3_taken_br_T_10 = or(_banked_lhist_providers_1_io_f3_taken_br_T_9, _banked_lhist_providers_1_io_f3_taken_br_T_7) connect banked_lhist_providers_1.io.f3_taken_br, _banked_lhist_providers_1_io_f3_taken_br_T_10 reg b0_fire_REG : UInt<1>, clock connect b0_fire_REG, banked_predictors_0.io.f0_valid reg b0_fire_REG_1 : UInt<1>, clock connect b0_fire_REG_1, b0_fire_REG reg b0_fire_REG_2 : UInt<1>, clock connect b0_fire_REG_2, b0_fire_REG_1 node b0_fire = and(io.f3_fire, b0_fire_REG_2) reg b1_fire_REG : UInt<1>, clock connect b1_fire_REG, banked_predictors_1.io.f0_valid reg b1_fire_REG_1 : UInt<1>, clock connect b1_fire_REG_1, b1_fire_REG reg b1_fire_REG_2 : UInt<1>, clock connect b1_fire_REG_2, b1_fire_REG_1 node b1_fire = and(io.f3_fire, b1_fire_REG_2) connect banked_predictors_0.io.f3_fire, b0_fire connect banked_predictors_1.io.f3_fire, b1_fire connect banked_lhist_providers_0.io.f3_fire, b0_fire connect banked_lhist_providers_1.io.f3_fire, b1_fire connect io.resp.f3.meta[0], banked_predictors_0.io.f3_meta connect io.resp.f3.meta[1], banked_predictors_1.io.f3_meta connect io.resp.f3.lhist[0], banked_lhist_providers_0.io.f3_lhist connect io.resp.f3.lhist[1], banked_lhist_providers_1.io.f3_lhist node _T_4 = bits(io.resp.f1.pc, 3, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : connect io.resp.f1.preds[0], banked_predictors_0.io.resp.f1[0] connect io.resp.f1.preds[4], banked_predictors_1.io.resp.f1[0] connect io.resp.f1.preds[1], banked_predictors_0.io.resp.f1[1] connect io.resp.f1.preds[5], banked_predictors_1.io.resp.f1[1] connect io.resp.f1.preds[2], banked_predictors_0.io.resp.f1[2] connect io.resp.f1.preds[6], banked_predictors_1.io.resp.f1[2] connect io.resp.f1.preds[3], banked_predictors_0.io.resp.f1[3] connect io.resp.f1.preds[7], banked_predictors_1.io.resp.f1[3] else : connect io.resp.f1.preds[0], banked_predictors_1.io.resp.f1[0] connect io.resp.f1.preds[4], banked_predictors_0.io.resp.f1[0] connect io.resp.f1.preds[1], banked_predictors_1.io.resp.f1[1] connect io.resp.f1.preds[5], banked_predictors_0.io.resp.f1[1] connect io.resp.f1.preds[2], banked_predictors_1.io.resp.f1[2] connect io.resp.f1.preds[6], banked_predictors_0.io.resp.f1[2] connect io.resp.f1.preds[3], banked_predictors_1.io.resp.f1[3] connect io.resp.f1.preds[7], banked_predictors_0.io.resp.f1[3] node _T_6 = bits(io.resp.f2.pc, 3, 3) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : connect io.resp.f2.preds[0], banked_predictors_0.io.resp.f2[0] connect io.resp.f2.preds[4], banked_predictors_1.io.resp.f2[0] connect io.resp.f2.preds[1], banked_predictors_0.io.resp.f2[1] connect io.resp.f2.preds[5], banked_predictors_1.io.resp.f2[1] connect io.resp.f2.preds[2], banked_predictors_0.io.resp.f2[2] connect io.resp.f2.preds[6], banked_predictors_1.io.resp.f2[2] connect io.resp.f2.preds[3], banked_predictors_0.io.resp.f2[3] connect io.resp.f2.preds[7], banked_predictors_1.io.resp.f2[3] else : connect io.resp.f2.preds[0], banked_predictors_1.io.resp.f2[0] connect io.resp.f2.preds[4], banked_predictors_0.io.resp.f2[0] connect io.resp.f2.preds[1], banked_predictors_1.io.resp.f2[1] connect io.resp.f2.preds[5], banked_predictors_0.io.resp.f2[1] connect io.resp.f2.preds[2], banked_predictors_1.io.resp.f2[2] connect io.resp.f2.preds[6], banked_predictors_0.io.resp.f2[2] connect io.resp.f2.preds[3], banked_predictors_1.io.resp.f2[3] connect io.resp.f2.preds[7], banked_predictors_0.io.resp.f2[3] node _T_8 = bits(io.resp.f3.pc, 3, 3) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : connect io.resp.f3.preds[0], banked_predictors_0.io.resp.f3[0] connect io.resp.f3.preds[4], banked_predictors_1.io.resp.f3[0] connect io.resp.f3.preds[1], banked_predictors_0.io.resp.f3[1] connect io.resp.f3.preds[5], banked_predictors_1.io.resp.f3[1] connect io.resp.f3.preds[2], banked_predictors_0.io.resp.f3[2] connect io.resp.f3.preds[6], banked_predictors_1.io.resp.f3[2] connect io.resp.f3.preds[3], banked_predictors_0.io.resp.f3[3] connect io.resp.f3.preds[7], banked_predictors_1.io.resp.f3[3] else : connect io.resp.f3.preds[0], banked_predictors_1.io.resp.f3[0] connect io.resp.f3.preds[4], banked_predictors_0.io.resp.f3[0] connect io.resp.f3.preds[1], banked_predictors_1.io.resp.f3[1] connect io.resp.f3.preds[5], banked_predictors_0.io.resp.f3[1] connect io.resp.f3.preds[2], banked_predictors_1.io.resp.f3[2] connect io.resp.f3.preds[6], banked_predictors_0.io.resp.f3[2] connect io.resp.f3.preds[3], banked_predictors_1.io.resp.f3[3] connect io.resp.f3.preds[7], banked_predictors_0.io.resp.f3[3] reg io_resp_f1_pc_REG : UInt, clock connect io_resp_f1_pc_REG, io.f0_req.bits.pc connect io.resp.f1.pc, io_resp_f1_pc_REG reg io_resp_f2_pc_REG : UInt, clock connect io_resp_f2_pc_REG, io.resp.f1.pc connect io.resp.f2.pc, io_resp_f2_pc_REG reg io_resp_f3_pc_REG : UInt, clock connect io_resp_f3_pc_REG, io.resp.f2.pc connect io.resp.f3.pc, io_resp_f3_pc_REG invalidate io.resp.f1.meta[0] invalidate io.resp.f1.meta[1] invalidate io.resp.f2.meta[0] invalidate io.resp.f2.meta[1] invalidate io.resp.f1.lhist[0] invalidate io.resp.f1.lhist[1] invalidate io.resp.f2.lhist[0] invalidate io.resp.f2.lhist[1] connect banked_predictors_0.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect banked_predictors_0.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect banked_predictors_0.io.update.bits.meta, io.update.bits.meta[0] connect banked_predictors_0.io.update.bits.lhist, io.update.bits.lhist[0] connect banked_predictors_0.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect banked_predictors_0.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect banked_predictors_0.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect banked_predictors_0.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect banked_predictors_0.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect banked_predictors_0.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect banked_predictors_0.io.update.bits.target, io.update.bits.target connect banked_lhist_providers_0.io.update.mispredict, io.update.bits.is_mispredict_update connect banked_lhist_providers_0.io.update.repair, io.update.bits.is_repair_update connect banked_lhist_providers_0.io.update.lhist, io.update.bits.lhist[0] connect banked_predictors_1.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect banked_predictors_1.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect banked_predictors_1.io.update.bits.meta, io.update.bits.meta[1] connect banked_predictors_1.io.update.bits.lhist, io.update.bits.lhist[1] connect banked_predictors_1.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect banked_predictors_1.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect banked_predictors_1.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect banked_predictors_1.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect banked_predictors_1.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect banked_predictors_1.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect banked_predictors_1.io.update.bits.target, io.update.bits.target connect banked_lhist_providers_1.io.update.mispredict, io.update.bits.is_mispredict_update connect banked_lhist_providers_1.io.update.repair, io.update.bits.is_repair_update connect banked_lhist_providers_1.io.update.lhist, io.update.bits.lhist[1] node _T_10 = bits(io.update.bits.pc, 3, 3) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _b1_update_valid_T = eq(io.update.bits.cfi_idx.valid, UInt<1>(0h0)) node _b1_update_valid_T_1 = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _b1_update_valid_T_2 = or(_b1_update_valid_T, _b1_update_valid_T_1) node b1_update_valid = and(io.update.valid, _b1_update_valid_T_2) node _banked_lhist_providers_0_io_update_valid_T = bits(io.update.bits.br_mask, 3, 0) node _banked_lhist_providers_0_io_update_valid_T_1 = neq(_banked_lhist_providers_0_io_update_valid_T, UInt<1>(0h0)) node _banked_lhist_providers_0_io_update_valid_T_2 = and(io.update.valid, _banked_lhist_providers_0_io_update_valid_T_1) connect banked_lhist_providers_0.io.update.valid, _banked_lhist_providers_0_io_update_valid_T_2 node _banked_lhist_providers_1_io_update_valid_T = bits(io.update.bits.br_mask, 7, 4) node _banked_lhist_providers_1_io_update_valid_T_1 = neq(_banked_lhist_providers_1_io_update_valid_T, UInt<1>(0h0)) node _banked_lhist_providers_1_io_update_valid_T_2 = and(b1_update_valid, _banked_lhist_providers_1_io_update_valid_T_1) connect banked_lhist_providers_1.io.update.valid, _banked_lhist_providers_1_io_update_valid_T_2 node _banked_lhist_providers_0_io_update_pc_T = not(io.update.bits.pc) node _banked_lhist_providers_0_io_update_pc_T_1 = or(_banked_lhist_providers_0_io_update_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_0_io_update_pc_T_2 = not(_banked_lhist_providers_0_io_update_pc_T_1) connect banked_lhist_providers_0.io.update.pc, _banked_lhist_providers_0_io_update_pc_T_2 node _banked_lhist_providers_1_io_update_pc_T = not(io.update.bits.pc) node _banked_lhist_providers_1_io_update_pc_T_1 = or(_banked_lhist_providers_1_io_update_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_1_io_update_pc_T_2 = not(_banked_lhist_providers_1_io_update_pc_T_1) node _banked_lhist_providers_1_io_update_pc_T_3 = add(_banked_lhist_providers_1_io_update_pc_T_2, UInt<4>(0h8)) node _banked_lhist_providers_1_io_update_pc_T_4 = tail(_banked_lhist_providers_1_io_update_pc_T_3, 1) connect banked_lhist_providers_1.io.update.pc, _banked_lhist_providers_1_io_update_pc_T_4 connect banked_predictors_0.io.update.valid, io.update.valid connect banked_predictors_1.io.update.valid, b1_update_valid connect banked_predictors_0.io.update.bits.pc, io.update.bits.pc node _banked_predictors_1_io_update_bits_pc_T = not(io.update.bits.pc) node _banked_predictors_1_io_update_bits_pc_T_1 = or(_banked_predictors_1_io_update_bits_pc_T, UInt<3>(0h7)) node _banked_predictors_1_io_update_bits_pc_T_2 = not(_banked_predictors_1_io_update_bits_pc_T_1) node _banked_predictors_1_io_update_bits_pc_T_3 = add(_banked_predictors_1_io_update_bits_pc_T_2, UInt<4>(0h8)) node _banked_predictors_1_io_update_bits_pc_T_4 = tail(_banked_predictors_1_io_update_bits_pc_T_3, 1) connect banked_predictors_1.io.update.bits.pc, _banked_predictors_1_io_update_bits_pc_T_4 connect banked_predictors_0.io.update.bits.br_mask, io.update.bits.br_mask node _banked_predictors_1_io_update_bits_br_mask_T = shr(io.update.bits.br_mask, 4) connect banked_predictors_1.io.update.bits.br_mask, _banked_predictors_1_io_update_bits_br_mask_T connect banked_predictors_0.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts node _banked_predictors_1_io_update_bits_btb_mispredicts_T = shr(io.update.bits.btb_mispredicts, 4) connect banked_predictors_1.io.update.bits.btb_mispredicts, _banked_predictors_1_io_update_bits_btb_mispredicts_T node _banked_predictors_0_io_update_bits_cfi_idx_valid_T = lt(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_0_io_update_bits_cfi_idx_valid_T_1 = and(io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T) connect banked_predictors_0.io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T_1 node _banked_predictors_1_io_update_bits_cfi_idx_valid_T = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_1_io_update_bits_cfi_idx_valid_T_1 = and(io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T) connect banked_predictors_1.io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T_1 connect banked_predictors_0.io.update.bits.ghist, io.update.bits.ghist.old_history node _banked_predictors_1_io_update_bits_ghist_T = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_1_io_update_bits_ghist_T_1 = or(_banked_predictors_1_io_update_bits_ghist_T, UInt<1>(0h1)) node _banked_predictors_1_io_update_bits_ghist_T_2 = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_1_io_update_bits_ghist_T_3 = mux(io.update.bits.ghist.new_saw_branch_not_taken, _banked_predictors_1_io_update_bits_ghist_T_2, io.update.bits.ghist.old_history) node _banked_predictors_1_io_update_bits_ghist_T_4 = mux(io.update.bits.ghist.new_saw_branch_taken, _banked_predictors_1_io_update_bits_ghist_T_1, _banked_predictors_1_io_update_bits_ghist_T_3) connect banked_predictors_1.io.update.bits.ghist, _banked_predictors_1_io_update_bits_ghist_T_4 else : node _b0_update_valid_T = bits(io.update.bits.pc, 5, 3) node _b0_update_valid_T_1 = eq(_b0_update_valid_T, UInt<3>(0h7)) node _b0_update_valid_T_2 = and(UInt<1>(0h1), _b0_update_valid_T_1) node _b0_update_valid_T_3 = eq(_b0_update_valid_T_2, UInt<1>(0h0)) node _b0_update_valid_T_4 = and(io.update.valid, _b0_update_valid_T_3) node _b0_update_valid_T_5 = eq(io.update.bits.cfi_idx.valid, UInt<1>(0h0)) node _b0_update_valid_T_6 = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _b0_update_valid_T_7 = or(_b0_update_valid_T_5, _b0_update_valid_T_6) node b0_update_valid = and(_b0_update_valid_T_4, _b0_update_valid_T_7) node _banked_lhist_providers_1_io_update_valid_T_3 = bits(io.update.bits.br_mask, 3, 0) node _banked_lhist_providers_1_io_update_valid_T_4 = neq(_banked_lhist_providers_1_io_update_valid_T_3, UInt<1>(0h0)) node _banked_lhist_providers_1_io_update_valid_T_5 = and(io.update.valid, _banked_lhist_providers_1_io_update_valid_T_4) connect banked_lhist_providers_1.io.update.valid, _banked_lhist_providers_1_io_update_valid_T_5 node _banked_lhist_providers_0_io_update_valid_T_3 = bits(io.update.bits.br_mask, 7, 4) node _banked_lhist_providers_0_io_update_valid_T_4 = neq(_banked_lhist_providers_0_io_update_valid_T_3, UInt<1>(0h0)) node _banked_lhist_providers_0_io_update_valid_T_5 = and(b0_update_valid, _banked_lhist_providers_0_io_update_valid_T_4) connect banked_lhist_providers_0.io.update.valid, _banked_lhist_providers_0_io_update_valid_T_5 node _banked_lhist_providers_1_io_update_pc_T_5 = not(io.update.bits.pc) node _banked_lhist_providers_1_io_update_pc_T_6 = or(_banked_lhist_providers_1_io_update_pc_T_5, UInt<3>(0h7)) node _banked_lhist_providers_1_io_update_pc_T_7 = not(_banked_lhist_providers_1_io_update_pc_T_6) connect banked_lhist_providers_1.io.update.pc, _banked_lhist_providers_1_io_update_pc_T_7 node _banked_lhist_providers_0_io_update_pc_T_3 = not(io.update.bits.pc) node _banked_lhist_providers_0_io_update_pc_T_4 = or(_banked_lhist_providers_0_io_update_pc_T_3, UInt<3>(0h7)) node _banked_lhist_providers_0_io_update_pc_T_5 = not(_banked_lhist_providers_0_io_update_pc_T_4) node _banked_lhist_providers_0_io_update_pc_T_6 = add(_banked_lhist_providers_0_io_update_pc_T_5, UInt<4>(0h8)) node _banked_lhist_providers_0_io_update_pc_T_7 = tail(_banked_lhist_providers_0_io_update_pc_T_6, 1) connect banked_lhist_providers_0.io.update.pc, _banked_lhist_providers_0_io_update_pc_T_7 connect banked_predictors_1.io.update.valid, io.update.valid connect banked_predictors_0.io.update.valid, b0_update_valid connect banked_predictors_1.io.update.bits.pc, io.update.bits.pc node _banked_predictors_0_io_update_bits_pc_T = not(io.update.bits.pc) node _banked_predictors_0_io_update_bits_pc_T_1 = or(_banked_predictors_0_io_update_bits_pc_T, UInt<3>(0h7)) node _banked_predictors_0_io_update_bits_pc_T_2 = not(_banked_predictors_0_io_update_bits_pc_T_1) node _banked_predictors_0_io_update_bits_pc_T_3 = add(_banked_predictors_0_io_update_bits_pc_T_2, UInt<4>(0h8)) node _banked_predictors_0_io_update_bits_pc_T_4 = tail(_banked_predictors_0_io_update_bits_pc_T_3, 1) connect banked_predictors_0.io.update.bits.pc, _banked_predictors_0_io_update_bits_pc_T_4 connect banked_predictors_1.io.update.bits.br_mask, io.update.bits.br_mask node _banked_predictors_0_io_update_bits_br_mask_T = shr(io.update.bits.br_mask, 4) connect banked_predictors_0.io.update.bits.br_mask, _banked_predictors_0_io_update_bits_br_mask_T connect banked_predictors_1.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts node _banked_predictors_0_io_update_bits_btb_mispredicts_T = shr(io.update.bits.btb_mispredicts, 4) connect banked_predictors_0.io.update.bits.btb_mispredicts, _banked_predictors_0_io_update_bits_btb_mispredicts_T node _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2 = lt(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_1_io_update_bits_cfi_idx_valid_T_3 = and(io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2) connect banked_predictors_1.io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T_3 node _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2 = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_0_io_update_bits_cfi_idx_valid_T_3 = and(io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2) connect banked_predictors_0.io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T_3 connect banked_predictors_1.io.update.bits.ghist, io.update.bits.ghist.old_history node _banked_predictors_0_io_update_bits_ghist_T = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_0_io_update_bits_ghist_T_1 = or(_banked_predictors_0_io_update_bits_ghist_T, UInt<1>(0h1)) node _banked_predictors_0_io_update_bits_ghist_T_2 = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_0_io_update_bits_ghist_T_3 = mux(io.update.bits.ghist.new_saw_branch_not_taken, _banked_predictors_0_io_update_bits_ghist_T_2, io.update.bits.ghist.old_history) node _banked_predictors_0_io_update_bits_ghist_T_4 = mux(io.update.bits.ghist.new_saw_branch_taken, _banked_predictors_0_io_update_bits_ghist_T_1, _banked_predictors_0_io_update_bits_ghist_T_3) connect banked_predictors_0.io.update.bits.ghist, _banked_predictors_0_io_update_bits_ghist_T_4 when io.update.valid : node _T_12 = and(io.update.bits.cfi_is_br, io.update.bits.cfi_idx.valid) when _T_12 : node _T_13 = dshr(io.update.bits.br_mask, io.update.bits.cfi_idx.bits) node _T_14 = bits(_T_13, 0, 0) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at predictor.scala:470 assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits))\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert	module BranchPredictor( // @[predictor.scala:196:7] input clock, // @[predictor.scala:196:7] input reset, // @[predictor.scala:196:7] input io_f0_req_valid, // @[predictor.scala:199:14] input [39:0] io_f0_req_bits_pc, // @[predictor.scala:199:14] input [63:0] io_f0_req_bits_ghist_old_history, // @[predictor.scala:199:14] input io_f0_req_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:199:14] input io_f0_req_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:199:14] input io_f0_req_bits_ghist_new_saw_branch_taken, // @[predictor.scala:199:14] input [4:0] io_f0_req_bits_ghist_ras_idx, // @[predictor.scala:199:14] output io_resp_f1_preds_0_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_0_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_0_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_0_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_0_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_1_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_1_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_1_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_1_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_1_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_2_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_2_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_2_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_2_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_2_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_3_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_3_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_3_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_3_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_3_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_4_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_4_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_4_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_4_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_4_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_5_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_5_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_5_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_5_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_5_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_6_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_6_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_6_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_6_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_6_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_7_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_7_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_7_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_7_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_7_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_0_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_0_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_0_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_0_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_0_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_1_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_1_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_1_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_1_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_1_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_2_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_2_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_2_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_2_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_2_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_3_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_3_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_3_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_3_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_3_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_4_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_4_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_4_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_4_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_4_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_5_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_5_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_5_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_5_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_5_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_6_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_6_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_6_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_6_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_6_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_7_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_7_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_7_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_7_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_7_predicted_pc_bits, // @[predictor.scala:199:14] output [39:0] io_resp_f3_pc, // @[predictor.scala:199:14] output io_resp_f3_preds_0_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_0_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_0_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_0_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_0_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_1_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_1_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_1_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_1_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_1_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_2_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_2_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_2_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_2_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_2_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_3_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_3_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_3_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_3_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_3_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_4_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_4_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_4_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_4_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_4_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_5_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_5_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_5_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_5_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_5_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_6_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_6_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_6_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_6_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_6_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_7_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_7_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_7_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_7_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_7_predicted_pc_bits, // @[predictor.scala:199:14] output [119:0] io_resp_f3_meta_0, // @[predictor.scala:199:14] output [119:0] io_resp_f3_meta_1, // @[predictor.scala:199:14] input io_f3_fire, // @[predictor.scala:199:14] input io_update_valid, // @[predictor.scala:199:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:199:14] input io_update_bits_is_repair_update, // @[predictor.scala:199:14] input [7:0] io_update_bits_btb_mispredicts, // @[predictor.scala:199:14] input [39:0] io_update_bits_pc, // @[predictor.scala:199:14] input [7:0] io_update_bits_br_mask, // @[predictor.scala:199:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:199:14] input [2:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:199:14] input io_update_bits_cfi_taken, // @[predictor.scala:199:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:199:14] input io_update_bits_cfi_is_br, // @[predictor.scala:199:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:199:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:199:14] input [63:0] io_update_bits_ghist_old_history, // @[predictor.scala:199:14] input io_update_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:199:14] input io_update_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:199:14] input io_update_bits_ghist_new_saw_branch_taken, // @[predictor.scala:199:14] input [4:0] io_update_bits_ghist_ras_idx, // @[predictor.scala:199:14] input io_update_bits_lhist_0, // @[predictor.scala:199:14] input io_update_bits_lhist_1, // @[predictor.scala:199:14] input [39:0] io_update_bits_target, // @[predictor.scala:199:14] input [119:0] io_update_bits_meta_0, // @[predictor.scala:199:14] input [119:0] io_update_bits_meta_1 // @[predictor.scala:199:14] ); wire _banked_predictors_1_io_resp_f1_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_3_predicted_pc_bits; // @[predictor.scala:221:19] wire io_f0_req_valid_0 = io_f0_req_valid; // @[predictor.scala:196:7] wire [39:0] io_f0_req_bits_pc_0 = io_f0_req_bits_pc; // @[predictor.scala:196:7] wire [63:0] io_f0_req_bits_ghist_old_history_0 = io_f0_req_bits_ghist_old_history; // @[predictor.scala:196:7] wire io_f0_req_bits_ghist_current_saw_branch_not_taken_0 = io_f0_req_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_f0_req_bits_ghist_new_saw_branch_not_taken_0 = io_f0_req_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_f0_req_bits_ghist_new_saw_branch_taken_0 = io_f0_req_bits_ghist_new_saw_branch_taken; // @[predictor.scala:196:7] wire [4:0] io_f0_req_bits_ghist_ras_idx_0 = io_f0_req_bits_ghist_ras_idx; // @[predictor.scala:196:7] wire io_f3_fire_0 = io_f3_fire; // @[predictor.scala:196:7] wire io_update_valid_0 = io_update_valid; // @[predictor.scala:196:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[predictor.scala:196:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[predictor.scala:196:7] wire [7:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[predictor.scala:196:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[predictor.scala:196:7] wire [7:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[predictor.scala:196:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[predictor.scala:196:7] wire [2:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[predictor.scala:196:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[predictor.scala:196:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[predictor.scala:196:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[predictor.scala:196:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[predictor.scala:196:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[predictor.scala:196:7] wire [63:0] io_update_bits_ghist_old_history_0 = io_update_bits_ghist_old_history; // @[predictor.scala:196:7] wire io_update_bits_ghist_current_saw_branch_not_taken_0 = io_update_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_update_bits_ghist_new_saw_branch_not_taken_0 = io_update_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_update_bits_ghist_new_saw_branch_taken_0 = io_update_bits_ghist_new_saw_branch_taken; // @[predictor.scala:196:7] wire [4:0] io_update_bits_ghist_ras_idx_0 = io_update_bits_ghist_ras_idx; // @[predictor.scala:196:7] wire io_update_bits_lhist_0_0 = io_update_bits_lhist_0; // @[predictor.scala:196:7] wire io_update_bits_lhist_1_0 = io_update_bits_lhist_1; // @[predictor.scala:196:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[predictor.scala:196:7] wire [119:0] io_update_bits_meta_0_0 = io_update_bits_meta_0; // @[predictor.scala:196:7] wire [119:0] io_update_bits_meta_1_0 = io_update_bits_meta_1; // @[predictor.scala:196:7] wire [119:0] io_resp_f1_meta_0 = 120'h0; // @[predictor.scala:196:7] wire [119:0] io_resp_f1_meta_1 = 120'h0; // @[predictor.scala:196:7] wire [119:0] io_resp_f2_meta_0 = 120'h0; // @[predictor.scala:196:7] wire [119:0] io_resp_f2_meta_1 = 120'h0; // @[predictor.scala:196:7] wire io_resp_f1_lhist_0 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f1_lhist_1 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f2_lhist_0 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f2_lhist_1 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f3_lhist_0 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f3_lhist_1 = 1'h0; // @[predictor.scala:196:7] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire [7:0] _banked_predictors_0_io_f0_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:167:81] wire [7:0] _banked_predictors_1_io_f0_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:167:81] wire [3:0] _banked_predictors_0_io_f0_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:167:56] wire [3:0] _banked_predictors_1_io_f0_mask_T = 4'hF; // @[predictor.scala:268:43] wire [3:0] _banked_predictors_0_io_f0_mask_T_2 = 4'hF; // @[predictor.scala:278:43] wire [3:0] _banked_predictors_1_io_f0_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:167:56] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire io_resp_f1_preds_0_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_0_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_0_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_0_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_0_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_1_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_2_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_3_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_4_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_5_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_6_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_7_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_is_jal_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_pc; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_0_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_1_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_2_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_3_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_4_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_5_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_6_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_7_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_is_jal_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_pc; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_0_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_1_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_2_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_3_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_4_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_5_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_6_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_7_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_is_jal_0; // @[predictor.scala:196:7] wire [119:0] io_resp_f3_meta_0_0; // @[predictor.scala:196:7] wire [119:0] io_resp_f3_meta_1_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_pc_0; // @[predictor.scala:196:7] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_1 = {_banked_lhist_providers_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_2 = ~_banked_lhist_providers_0_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_1 = {_banked_lhist_providers_1_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_2 = ~_banked_lhist_providers_1_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_1_io_f0_pc_T_3 = {1'h0, _banked_lhist_providers_1_io_f0_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_4 = _banked_lhist_providers_1_io_f0_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [2:0] banked_predictors_0_io_f0_mask_idx = io_f0_req_bits_pc_0[3:1]; // @[package.scala:163:13] wire [2:0] banked_predictors_1_io_f0_mask_idx = io_f0_req_bits_pc_0[3:1]; // @[package.scala:163:13] wire [1:0] banked_predictors_0_io_f0_mask_shamt = banked_predictors_0_io_f0_mask_idx[1:0]; // @[package.scala:163:13] wire [2:0] _banked_predictors_0_io_f0_mask_end_mask_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire [2:0] _banked_lhist_providers_0_io_f0_valid_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire [2:0] _banked_predictors_0_io_f0_valid_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire [2:0] _banked_predictors_1_io_f0_mask_end_mask_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire _banked_predictors_0_io_f0_mask_end_mask_T_1 = &_banked_predictors_0_io_f0_mask_end_mask_T; // @[frontend.scala:139:{28,66}] wire _banked_predictors_0_io_f0_mask_end_mask_T_2 = _banked_predictors_0_io_f0_mask_end_mask_T_1; // @[frontend.scala:139:{21,66}] wire [7:0] banked_predictors_0_io_f0_mask_end_mask = _banked_predictors_0_io_f0_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:139:21, :167:25] wire [10:0] _banked_predictors_0_io_f0_mask_T = 11'hFF << banked_predictors_0_io_f0_mask_shamt; // @[package.scala:163:13] wire [10:0] _banked_predictors_0_io_f0_mask_T_1 = {3'h0, _banked_predictors_0_io_f0_mask_T[7:0] & banked_predictors_0_io_f0_mask_end_mask}; // @[frontend.scala:167:25, :168:{31,40}] wire [39:0] _banked_predictors_1_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_1_io_f0_pc_T_1 = {_banked_predictors_1_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_1_io_f0_pc_T_2 = ~_banked_predictors_1_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_1_io_f0_pc_T_3 = {1'h0, _banked_predictors_1_io_f0_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_1_io_f0_pc_T_4 = _banked_predictors_1_io_f0_pc_T_3[39:0]; // @[frontend.scala:151:46] wire _banked_lhist_providers_0_io_f0_valid_T_1 = &_banked_lhist_providers_0_io_f0_valid_T; // @[frontend.scala:139:{28,66}] wire _banked_lhist_providers_0_io_f0_valid_T_2 = _banked_lhist_providers_0_io_f0_valid_T_1; // @[frontend.scala:139:{21,66}] wire _banked_lhist_providers_0_io_f0_valid_T_3 = ~_banked_lhist_providers_0_io_f0_valid_T_2; // @[frontend.scala:139:21] wire _banked_lhist_providers_0_io_f0_valid_T_4 = io_f0_req_valid_0 & _banked_lhist_providers_0_io_f0_valid_T_3; // @[predictor.scala:196:7, :270:{64,67}] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_3 = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_4 = {_banked_lhist_providers_0_io_f0_pc_T_3[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_5 = ~_banked_lhist_providers_0_io_f0_pc_T_4; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_0_io_f0_pc_T_6 = {1'h0, _banked_lhist_providers_0_io_f0_pc_T_5} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_7 = _banked_lhist_providers_0_io_f0_pc_T_6[39:0]; // @[frontend.scala:151:46] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_5 = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_6 = {_banked_lhist_providers_1_io_f0_pc_T_5[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_7 = ~_banked_lhist_providers_1_io_f0_pc_T_6; // @[frontend.scala:147:{31,39}] wire _banked_predictors_0_io_f0_valid_T_1 = &_banked_predictors_0_io_f0_valid_T; // @[frontend.scala:139:{28,66}] wire _banked_predictors_0_io_f0_valid_T_2 = _banked_predictors_0_io_f0_valid_T_1; // @[frontend.scala:139:{21,66}] wire _banked_predictors_0_io_f0_valid_T_3 = ~_banked_predictors_0_io_f0_valid_T_2; // @[frontend.scala:139:21] wire _banked_predictors_0_io_f0_valid_T_4 = io_f0_req_valid_0 & _banked_predictors_0_io_f0_valid_T_3; // @[predictor.scala:196:7, :276:{59,62}] wire banked_predictors_0_io_f0_valid = io_f0_req_bits_pc_0[3] ? _banked_predictors_0_io_f0_valid_T_4 : io_f0_req_valid_0; // @[frontend.scala:137:47] wire [39:0] _banked_predictors_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_0_io_f0_pc_T_1 = {_banked_predictors_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_0_io_f0_pc_T_2 = ~_banked_predictors_0_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_0_io_f0_pc_T_3 = {1'h0, _banked_predictors_0_io_f0_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_0_io_f0_pc_T_4 = _banked_predictors_0_io_f0_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [1:0] banked_predictors_1_io_f0_mask_shamt = banked_predictors_1_io_f0_mask_idx[1:0]; // @[package.scala:163:13] wire _banked_predictors_1_io_f0_mask_end_mask_T_1 = &_banked_predictors_1_io_f0_mask_end_mask_T; // @[frontend.scala:139:{28,66}] wire _banked_predictors_1_io_f0_mask_end_mask_T_2 = _banked_predictors_1_io_f0_mask_end_mask_T_1; // @[frontend.scala:139:{21,66}] wire [7:0] banked_predictors_1_io_f0_mask_end_mask = _banked_predictors_1_io_f0_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:139:21, :167:25] wire [10:0] _banked_predictors_1_io_f0_mask_T_1 = 11'hFF << banked_predictors_1_io_f0_mask_shamt; // @[package.scala:163:13] wire [10:0] _banked_predictors_1_io_f0_mask_T_2 = {3'h0, _banked_predictors_1_io_f0_mask_T_1[7:0] & banked_predictors_1_io_f0_mask_end_mask}; // @[frontend.scala:167:25, :168:{31,40}] reg REG; // @[predictor.scala:284:18] reg [63:0] banked_predictors_0_io_f1_ghist_REG; // @[predictor.scala:285:51] wire [64:0] _GEN = {io_f0_req_bits_ghist_old_history_0, 1'h0}; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_f1_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_1_io_f1_ghist_T = _GEN; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_f1_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_1_io_f1_ghist_T_2 = _GEN; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_0_io_f1_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_0_io_f1_ghist_T = _GEN; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_0_io_f1_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_0_io_f1_ghist_T_2 = _GEN; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_1_io_f1_ghist_T_1 = {_banked_predictors_1_io_f1_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _GEN_0 = {1'h0, io_f0_req_bits_ghist_old_history_0}; // @[frontend.scala:54:12] wire [64:0] _banked_predictors_1_io_f1_ghist_T_3 = io_f0_req_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_1_io_f1_ghist_T_2 : _GEN_0; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_1_io_f1_ghist_T_4 = io_f0_req_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_1_io_f1_ghist_T_1 : _banked_predictors_1_io_f1_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12] reg [64:0] banked_predictors_1_io_f1_ghist_REG; // @[predictor.scala:286:51] wire [64:0] _banked_predictors_0_io_f1_ghist_T_1 = {_banked_predictors_0_io_f1_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _banked_predictors_0_io_f1_ghist_T_3 = io_f0_req_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_0_io_f1_ghist_T_2 : _GEN_0; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_0_io_f1_ghist_T_4 = io_f0_req_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_0_io_f1_ghist_T_1 : _banked_predictors_0_io_f1_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12] reg [64:0] banked_predictors_0_io_f1_ghist_REG_1; // @[predictor.scala:288:51] reg [63:0] banked_predictors_1_io_f1_ghist_REG_1; // @[predictor.scala:289:51] wire _banked_lhist_providers_0_io_f3_taken_br_T = _banked_predictors_0_io_resp_f3_0_is_br & _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_1 = _banked_lhist_providers_0_io_f3_taken_br_T & _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_2 = _banked_predictors_0_io_resp_f3_1_is_br & _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_3 = _banked_lhist_providers_0_io_f3_taken_br_T_2 & _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_4 = _banked_predictors_0_io_resp_f3_2_is_br & _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_5 = _banked_lhist_providers_0_io_f3_taken_br_T_4 & _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_6 = _banked_predictors_0_io_resp_f3_3_is_br & _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_7 = _banked_lhist_providers_0_io_f3_taken_br_T_6 & _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_8 = _banked_lhist_providers_0_io_f3_taken_br_T_1 \| _banked_lhist_providers_0_io_f3_taken_br_T_3; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_9 = _banked_lhist_providers_0_io_f3_taken_br_T_8 \| _banked_lhist_providers_0_io_f3_taken_br_T_5; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_10 = _banked_lhist_providers_0_io_f3_taken_br_T_9 \| _banked_lhist_providers_0_io_f3_taken_br_T_7; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_1_io_f3_taken_br_T = _banked_predictors_1_io_resp_f3_0_is_br & _banked_predictors_1_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_1 = _banked_lhist_providers_1_io_f3_taken_br_T & _banked_predictors_1_io_resp_f3_0_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_2 = _banked_predictors_1_io_resp_f3_1_is_br & _banked_predictors_1_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_3 = _banked_lhist_providers_1_io_f3_taken_br_T_2 & _banked_predictors_1_io_resp_f3_1_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_4 = _banked_predictors_1_io_resp_f3_2_is_br & _banked_predictors_1_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_5 = _banked_lhist_providers_1_io_f3_taken_br_T_4 & _banked_predictors_1_io_resp_f3_2_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_6 = _banked_predictors_1_io_resp_f3_3_is_br & _banked_predictors_1_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_7 = _banked_lhist_providers_1_io_f3_taken_br_T_6 & _banked_predictors_1_io_resp_f3_3_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_8 = _banked_lhist_providers_1_io_f3_taken_br_T_1 \| _banked_lhist_providers_1_io_f3_taken_br_T_3; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_9 = _banked_lhist_providers_1_io_f3_taken_br_T_8 \| _banked_lhist_providers_1_io_f3_taken_br_T_5; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_10 = _banked_lhist_providers_1_io_f3_taken_br_T_9 \| _banked_lhist_providers_1_io_f3_taken_br_T_7; // @[predictor.scala:296:39, :297:15] reg b0_fire_REG; // @[predictor.scala:311:56] reg b0_fire_REG_1; // @[predictor.scala:311:48] reg b0_fire_REG_2; // @[predictor.scala:311:40] wire b0_fire = io_f3_fire_0 & b0_fire_REG_2; // @[predictor.scala:196:7, :311:{30,40}] reg b1_fire_REG; // @[predictor.scala:312:56] reg b1_fire_REG_1; // @[predictor.scala:312:48] reg b1_fire_REG_2; // @[predictor.scala:312:40] wire b1_fire = io_f3_fire_0 & b1_fire_REG_2; // @[predictor.scala:196:7, :312:{30,40}] assign io_resp_f1_preds_0_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_taken : _banked_predictors_0_io_resp_f1_0_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_is_br : _banked_predictors_0_io_resp_f1_0_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_is_jal : _banked_predictors_0_io_resp_f1_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_predicted_pc_valid : _banked_predictors_0_io_resp_f1_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_predicted_pc_bits : _banked_predictors_0_io_resp_f1_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_taken : _banked_predictors_1_io_resp_f1_0_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_is_br : _banked_predictors_1_io_resp_f1_0_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_is_jal : _banked_predictors_1_io_resp_f1_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_predicted_pc_valid : _banked_predictors_1_io_resp_f1_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_predicted_pc_bits : _banked_predictors_1_io_resp_f1_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_taken : _banked_predictors_0_io_resp_f1_1_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_is_br : _banked_predictors_0_io_resp_f1_1_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_is_jal : _banked_predictors_0_io_resp_f1_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_predicted_pc_valid : _banked_predictors_0_io_resp_f1_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_predicted_pc_bits : _banked_predictors_0_io_resp_f1_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_taken : _banked_predictors_1_io_resp_f1_1_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_is_br : _banked_predictors_1_io_resp_f1_1_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_is_jal : _banked_predictors_1_io_resp_f1_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_predicted_pc_valid : _banked_predictors_1_io_resp_f1_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_predicted_pc_bits : _banked_predictors_1_io_resp_f1_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_taken : _banked_predictors_0_io_resp_f1_2_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_is_br : _banked_predictors_0_io_resp_f1_2_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_is_jal : _banked_predictors_0_io_resp_f1_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_predicted_pc_valid : _banked_predictors_0_io_resp_f1_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_predicted_pc_bits : _banked_predictors_0_io_resp_f1_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_taken : _banked_predictors_1_io_resp_f1_2_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_is_br : _banked_predictors_1_io_resp_f1_2_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_is_jal : _banked_predictors_1_io_resp_f1_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_predicted_pc_valid : _banked_predictors_1_io_resp_f1_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_predicted_pc_bits : _banked_predictors_1_io_resp_f1_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_taken : _banked_predictors_0_io_resp_f1_3_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_is_br : _banked_predictors_0_io_resp_f1_3_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_is_jal : _banked_predictors_0_io_resp_f1_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_predicted_pc_valid : _banked_predictors_0_io_resp_f1_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_predicted_pc_bits : _banked_predictors_0_io_resp_f1_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_taken : _banked_predictors_1_io_resp_f1_3_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_is_br : _banked_predictors_1_io_resp_f1_3_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_is_jal : _banked_predictors_1_io_resp_f1_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_predicted_pc_valid : _banked_predictors_1_io_resp_f1_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_predicted_pc_bits : _banked_predictors_1_io_resp_f1_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_taken : _banked_predictors_0_io_resp_f2_0_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_is_br : _banked_predictors_0_io_resp_f2_0_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_is_jal : _banked_predictors_0_io_resp_f2_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_predicted_pc_valid : _banked_predictors_0_io_resp_f2_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_predicted_pc_bits : _banked_predictors_0_io_resp_f2_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_taken : _banked_predictors_1_io_resp_f2_0_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_is_br : _banked_predictors_1_io_resp_f2_0_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_is_jal : _banked_predictors_1_io_resp_f2_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_predicted_pc_valid : _banked_predictors_1_io_resp_f2_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_predicted_pc_bits : _banked_predictors_1_io_resp_f2_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_taken : _banked_predictors_0_io_resp_f2_1_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_is_br : _banked_predictors_0_io_resp_f2_1_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_is_jal : _banked_predictors_0_io_resp_f2_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_predicted_pc_valid : _banked_predictors_0_io_resp_f2_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_predicted_pc_bits : _banked_predictors_0_io_resp_f2_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_taken : _banked_predictors_1_io_resp_f2_1_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_is_br : _banked_predictors_1_io_resp_f2_1_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_is_jal : _banked_predictors_1_io_resp_f2_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_predicted_pc_valid : _banked_predictors_1_io_resp_f2_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_predicted_pc_bits : _banked_predictors_1_io_resp_f2_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_taken : _banked_predictors_0_io_resp_f2_2_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_is_br : _banked_predictors_0_io_resp_f2_2_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_is_jal : _banked_predictors_0_io_resp_f2_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_predicted_pc_valid : _banked_predictors_0_io_resp_f2_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_predicted_pc_bits : _banked_predictors_0_io_resp_f2_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_taken : _banked_predictors_1_io_resp_f2_2_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_is_br : _banked_predictors_1_io_resp_f2_2_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_is_jal : _banked_predictors_1_io_resp_f2_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_predicted_pc_valid : _banked_predictors_1_io_resp_f2_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_predicted_pc_bits : _banked_predictors_1_io_resp_f2_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_taken : _banked_predictors_0_io_resp_f2_3_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_is_br : _banked_predictors_0_io_resp_f2_3_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_is_jal : _banked_predictors_0_io_resp_f2_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_predicted_pc_valid : _banked_predictors_0_io_resp_f2_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_predicted_pc_bits : _banked_predictors_0_io_resp_f2_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_taken : _banked_predictors_1_io_resp_f2_3_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_is_br : _banked_predictors_1_io_resp_f2_3_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_is_jal : _banked_predictors_1_io_resp_f2_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_predicted_pc_valid : _banked_predictors_1_io_resp_f2_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_predicted_pc_bits : _banked_predictors_1_io_resp_f2_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_taken : _banked_predictors_0_io_resp_f3_0_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_is_br : _banked_predictors_0_io_resp_f3_0_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_is_jal : _banked_predictors_0_io_resp_f3_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_predicted_pc_valid : _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_predicted_pc_bits : _banked_predictors_0_io_resp_f3_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_taken : _banked_predictors_1_io_resp_f3_0_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_is_br : _banked_predictors_1_io_resp_f3_0_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_is_jal : _banked_predictors_1_io_resp_f3_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_predicted_pc_valid : _banked_predictors_1_io_resp_f3_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_predicted_pc_bits : _banked_predictors_1_io_resp_f3_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_taken : _banked_predictors_0_io_resp_f3_1_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_is_br : _banked_predictors_0_io_resp_f3_1_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_is_jal : _banked_predictors_0_io_resp_f3_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_predicted_pc_valid : _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_predicted_pc_bits : _banked_predictors_0_io_resp_f3_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_taken : _banked_predictors_1_io_resp_f3_1_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_is_br : _banked_predictors_1_io_resp_f3_1_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_is_jal : _banked_predictors_1_io_resp_f3_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_predicted_pc_valid : _banked_predictors_1_io_resp_f3_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_predicted_pc_bits : _banked_predictors_1_io_resp_f3_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_taken : _banked_predictors_0_io_resp_f3_2_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_is_br : _banked_predictors_0_io_resp_f3_2_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_is_jal : _banked_predictors_0_io_resp_f3_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_predicted_pc_valid : _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_predicted_pc_bits : _banked_predictors_0_io_resp_f3_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_taken : _banked_predictors_1_io_resp_f3_2_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_is_br : _banked_predictors_1_io_resp_f3_2_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_is_jal : _banked_predictors_1_io_resp_f3_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_predicted_pc_valid : _banked_predictors_1_io_resp_f3_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_predicted_pc_bits : _banked_predictors_1_io_resp_f3_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_taken : _banked_predictors_0_io_resp_f3_3_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_is_br : _banked_predictors_0_io_resp_f3_3_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_is_jal : _banked_predictors_0_io_resp_f3_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_predicted_pc_valid : _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_predicted_pc_bits : _banked_predictors_0_io_resp_f3_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_taken : _banked_predictors_1_io_resp_f3_3_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_is_br : _banked_predictors_1_io_resp_f3_3_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_is_jal : _banked_predictors_1_io_resp_f3_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_predicted_pc_valid : _banked_predictors_1_io_resp_f3_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_predicted_pc_bits : _banked_predictors_1_io_resp_f3_3_predicted_pc_bits; // @[frontend.scala:137:47] reg [39:0] io_resp_f1_pc_REG; // @[predictor.scala:365:27] assign io_resp_f1_pc = io_resp_f1_pc_REG; // @[predictor.scala:196:7, :365:27] reg [39:0] io_resp_f2_pc_REG; // @[predictor.scala:366:27] assign io_resp_f2_pc = io_resp_f2_pc_REG; // @[predictor.scala:196:7, :366:27] reg [39:0] io_resp_f3_pc_REG; // @[predictor.scala:367:27] assign io_resp_f3_pc_0 = io_resp_f3_pc_REG; // @[predictor.scala:196:7, :367:27] wire _b1_update_valid_T = ~io_update_bits_cfi_idx_valid_0; // @[predictor.scala:196:7, :413:10] wire _b1_update_valid_T_1 = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71, :434:120] wire _b0_update_valid_T_6 = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71, :440:71] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2 = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71, :461:120] wire _b1_update_valid_T_2 = _b1_update_valid_T \| _b1_update_valid_T_1; // @[predictor.scala:413:{10,40,71}] wire b1_update_valid = io_update_valid_0 & _b1_update_valid_T_2; // @[predictor.scala:196:7, :412:45, :413:40] wire [3:0] _banked_lhist_providers_0_io_update_valid_T = io_update_bits_br_mask_0[3:0]; // @[predictor.scala:196:7, :415:93] wire [3:0] _banked_lhist_providers_1_io_update_valid_T_3 = io_update_bits_br_mask_0[3:0]; // @[predictor.scala:196:7, :415:93, :442:93] wire _banked_lhist_providers_0_io_update_valid_T_1 = \|_banked_lhist_providers_0_io_update_valid_T; // @[predictor.scala:415:{93,109}] wire _banked_lhist_providers_0_io_update_valid_T_2 = io_update_valid_0 & _banked_lhist_providers_0_io_update_valid_T_1; // @[predictor.scala:196:7, :415:{68,109}] wire [3:0] _banked_lhist_providers_1_io_update_valid_T = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93] wire [3:0] _banked_predictors_1_io_update_bits_br_mask_T = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93, :428:77] wire [3:0] _banked_lhist_providers_0_io_update_valid_T_3 = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93, :443:93] wire [3:0] _banked_predictors_0_io_update_bits_br_mask_T = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93, :455:77] wire _banked_lhist_providers_1_io_update_valid_T_1 = \|_banked_lhist_providers_1_io_update_valid_T; // @[predictor.scala:416:{93,118}] wire _banked_lhist_providers_1_io_update_valid_T_2 = b1_update_valid & _banked_lhist_providers_1_io_update_valid_T_1; // @[predictor.scala:412:45, :416:{68,118}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_1 = {_banked_lhist_providers_0_io_update_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_2 = ~_banked_lhist_providers_0_io_update_pc_T_1; // @[frontend.scala:147:{31,39}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_1 = {_banked_lhist_providers_1_io_update_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_2 = ~_banked_lhist_providers_1_io_update_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_1_io_update_pc_T_3 = {1'h0, _banked_lhist_providers_1_io_update_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_4 = _banked_lhist_providers_1_io_update_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [39:0] _banked_predictors_1_io_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_1_io_update_bits_pc_T_1 = {_banked_predictors_1_io_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_1_io_update_bits_pc_T_2 = ~_banked_predictors_1_io_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_1_io_update_bits_pc_T_3 = {1'h0, _banked_predictors_1_io_update_bits_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_1_io_update_bits_pc_T_4 = _banked_predictors_1_io_update_bits_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [3:0] _banked_predictors_1_io_update_bits_btb_mispredicts_T = io_update_bits_btb_mispredicts_0[7:4]; // @[predictor.scala:196:7, :431:94] wire [3:0] _banked_predictors_0_io_update_bits_btb_mispredicts_T = io_update_bits_btb_mispredicts_0[7:4]; // @[predictor.scala:196:7, :431:94, :458:94] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T = ~(io_update_bits_cfi_idx_bits_0[2]); // @[predictor.scala:196:7, :413:71, :433:120] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T_1 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_0_io_update_bits_cfi_idx_valid_T; // @[predictor.scala:196:7, :433:{89,120}] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T_1 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_1_io_update_bits_cfi_idx_valid_T; // @[predictor.scala:196:7, :434:{89,120}] wire [64:0] _GEN_1 = {io_update_bits_ghist_old_history_0, 1'h0}; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_1_io_update_bits_ghist_T = _GEN_1; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_1_io_update_bits_ghist_T_2 = _GEN_1; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_0_io_update_bits_ghist_T = _GEN_1; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_0_io_update_bits_ghist_T_2 = _GEN_1; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_1 = {_banked_predictors_1_io_update_bits_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _GEN_2 = {1'h0, io_update_bits_ghist_old_history_0}; // @[frontend.scala:54:12] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_3 = io_update_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_1_io_update_bits_ghist_T_2 : _GEN_2; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_4 = io_update_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_1_io_update_bits_ghist_T_1 : _banked_predictors_1_io_update_bits_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12] wire [2:0] _b0_update_valid_T = io_update_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire _b0_update_valid_T_1 = &_b0_update_valid_T; // @[frontend.scala:139:{28,66}] wire _b0_update_valid_T_2 = _b0_update_valid_T_1; // @[frontend.scala:139:{21,66}] wire _b0_update_valid_T_3 = ~_b0_update_valid_T_2; // @[frontend.scala:139:21] wire _b0_update_valid_T_4 = io_update_valid_0 & _b0_update_valid_T_3; // @[predictor.scala:196:7, :439:{45,48}] wire _b0_update_valid_T_5 = ~io_update_bits_cfi_idx_valid_0; // @[predictor.scala:196:7, :413:10, :440:10] wire _b0_update_valid_T_7 = _b0_update_valid_T_5 \| _b0_update_valid_T_6; // @[predictor.scala:440:{10,40,71}] wire b0_update_valid = _b0_update_valid_T_4 & _b0_update_valid_T_7; // @[predictor.scala:439:{45,87}, :440:40] wire _banked_lhist_providers_1_io_update_valid_T_4 = \|_banked_lhist_providers_1_io_update_valid_T_3; // @[predictor.scala:442:{93,109}] wire _banked_lhist_providers_1_io_update_valid_T_5 = io_update_valid_0 & _banked_lhist_providers_1_io_update_valid_T_4; // @[predictor.scala:196:7, :442:{68,109}] wire _banked_lhist_providers_0_io_update_valid_T_4 = \|_banked_lhist_providers_0_io_update_valid_T_3; // @[predictor.scala:443:{93,118}] wire _banked_lhist_providers_0_io_update_valid_T_5 = b0_update_valid & _banked_lhist_providers_0_io_update_valid_T_4; // @[predictor.scala:439:87, :443:{68,118}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_5 = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_6 = {_banked_lhist_providers_1_io_update_pc_T_5[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_7 = ~_banked_lhist_providers_1_io_update_pc_T_6; // @[frontend.scala:147:{31,39}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_3 = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_4 = {_banked_lhist_providers_0_io_update_pc_T_3[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_5 = ~_banked_lhist_providers_0_io_update_pc_T_4; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_0_io_update_pc_T_6 = {1'h0, _banked_lhist_providers_0_io_update_pc_T_5} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_7 = _banked_lhist_providers_0_io_update_pc_T_6[39:0]; // @[frontend.scala:151:46] wire [39:0] _banked_predictors_0_io_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_0_io_update_bits_pc_T_1 = {_banked_predictors_0_io_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_0_io_update_bits_pc_T_2 = ~_banked_predictors_0_io_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_0_io_update_bits_pc_T_3 = {1'h0, _banked_predictors_0_io_update_bits_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_0_io_update_bits_pc_T_4 = _banked_predictors_0_io_update_bits_pc_T_3[39:0]; // @[frontend.scala:151:46] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2 = ~(io_update_bits_cfi_idx_bits_0[2]); // @[predictor.scala:196:7, :413:71, :433:120, :460:120] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T_3 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2; // @[predictor.scala:196:7, :460:{89,120}] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T_3 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2; // @[predictor.scala:196:7, :461:{89,120}] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_1 = {_banked_predictors_0_io_update_bits_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_3 = io_update_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_0_io_update_bits_ghist_T_2 : _GEN_2; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_4 = io_update_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_0_io_update_bits_ghist_T_1 : _banked_predictors_0_io_update_bits_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_4.bits.sink, UInt<5>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_58 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_59 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_60 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_61 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_100 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_101 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [4095:0] _GEN = {4084'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [4095:0] _GEN_2 = {4084'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_99 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_57 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_114 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_115 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_66 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(_T_12, _T_19) node _T_35 = or(_T_34, _T_26) node _T_36 = or(_T_35, _T_33) node _T_37 = or(_T_5, _T_36) node _T_38 = asUInt(reset) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = eq(_T_37, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_37, UInt<1>(0h1), "") : assert_1 node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_43 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_50 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_57 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_64 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = or(_T_48, _T_55) node _T_71 = or(_T_70, _T_62) node _T_72 = or(_T_71, _T_69) node _T_73 = or(_T_41, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2 node _T_77 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_84 = and(_T_82, _T_83) node _T_85 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_89 = and(_T_87, _T_88) node _T_90 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_91 = and(_T_89, _T_90) node _T_92 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_105 = and(_T_103, _T_104) node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = or(_T_84, _T_91) node _T_135 = or(_T_134, _T_98) node _T_136 = or(_T_135, _T_105) node _T_137 = or(_T_136, _T_112) node _T_138 = or(_T_137, _T_119) node _T_139 = or(_T_138, _T_126) node _T_140 = or(_T_139, _T_133) node _T_141 = or(_T_77, _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_141, UInt<1>(0h1), "") : assert_3 node _T_145 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_194 = and(_T_192, _T_193) node _T_195 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_196 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_201 = and(_T_199, _T_200) node _T_202 = or(_T_152, _T_159) node _T_203 = or(_T_202, _T_166) node _T_204 = or(_T_203, _T_173) node _T_205 = or(_T_204, _T_180) node _T_206 = or(_T_205, _T_187) node _T_207 = or(_T_206, _T_194) node _T_208 = or(_T_207, _T_201) node _T_209 = or(_T_145, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_209, UInt<1>(0h1), "") : assert_4 node _T_213 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_243 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_250 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_257 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_258 = and(_T_256, _T_257) node _T_259 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_264 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_271 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_272 = and(_T_270, _T_271) node _T_273 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_278 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_285 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_292 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_299 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_304 = and(_T_302, _T_303) node _T_305 = or(_T_220, _T_227) node _T_306 = or(_T_305, _T_234) node _T_307 = or(_T_306, _T_241) node _T_308 = or(_T_307, _T_248) node _T_309 = or(_T_308, _T_255) node _T_310 = or(_T_309, _T_262) node _T_311 = or(_T_310, _T_269) node _T_312 = or(_T_311, _T_276) node _T_313 = or(_T_312, _T_283) node _T_314 = or(_T_313, _T_290) node _T_315 = or(_T_314, _T_297) node _T_316 = or(_T_315, _T_304) node _T_317 = or(_T_213, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_317, UInt<1>(0h1), "") : assert_5 node _T_321 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_322 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_323 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_328 = and(_T_326, _T_327) node _T_329 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_330 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_335 = and(_T_333, _T_334) node _T_336 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_337 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_344 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_345 = and(_T_343, _T_344) node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_351 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_358 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_365 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_370 = and(_T_368, _T_369) node _T_371 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_372 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_373 = and(_T_371, _T_372) node _T_374 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_377 = and(_T_375, _T_376) node _T_378 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_379 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_386 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_387 = and(_T_385, _T_386) node _T_388 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_389 = and(_T_387, _T_388) node _T_390 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_391 = and(_T_389, _T_390) node _T_392 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_393 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_400 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_401 = and(_T_399, _T_400) node _T_402 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_407 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_408 = and(_T_406, _T_407) node _T_409 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_412 = and(_T_410, _T_411) node _T_413 = or(_T_328, _T_335) node _T_414 = or(_T_413, _T_342) node _T_415 = or(_T_414, _T_349) node _T_416 = or(_T_415, _T_356) node _T_417 = or(_T_416, _T_363) node _T_418 = or(_T_417, _T_370) node _T_419 = or(_T_418, _T_377) node _T_420 = or(_T_419, _T_384) node _T_421 = or(_T_420, _T_391) node _T_422 = or(_T_421, _T_398) node _T_423 = or(_T_422, _T_405) node _T_424 = or(_T_423, _T_412) node _T_425 = or(_T_321, _T_424) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_425, UInt<1>(0h1), "") : assert_6 node _T_429 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_431 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_436 = and(_T_434, _T_435) node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_438 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_443 = and(_T_441, _T_442) node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_445 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_446 = and(_T_444, _T_445) node _T_447 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_448 = and(_T_446, _T_447) node _T_449 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_452 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_459 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_462 = and(_T_460, _T_461) node _T_463 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_464 = and(_T_462, _T_463) node _T_465 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_466 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_473 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_476 = and(_T_474, _T_475) node _T_477 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_480 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_481 = and(_T_479, _T_480) node _T_482 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_483 = and(_T_481, _T_482) node _T_484 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_485 = and(_T_483, _T_484) node _T_486 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_487 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_488 = and(_T_486, _T_487) node _T_489 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_490 = and(_T_488, _T_489) node _T_491 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_492 = and(_T_490, _T_491) node _T_493 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_494 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_495 = and(_T_493, _T_494) node _T_496 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_499 = and(_T_497, _T_498) node _T_500 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_501 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_504 = and(_T_502, _T_503) node _T_505 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_508 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_509 = and(_T_507, _T_508) node _T_510 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_511 = and(_T_509, _T_510) node _T_512 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_515 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_516 = and(_T_514, _T_515) node _T_517 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_520 = and(_T_518, _T_519) node _T_521 = or(_T_436, _T_443) node _T_522 = or(_T_521, _T_450) node _T_523 = or(_T_522, _T_457) node _T_524 = or(_T_523, _T_464) node _T_525 = or(_T_524, _T_471) node _T_526 = or(_T_525, _T_478) node _T_527 = or(_T_526, _T_485) node _T_528 = or(_T_527, _T_492) node _T_529 = or(_T_528, _T_499) node _T_530 = or(_T_529, _T_506) node _T_531 = or(_T_530, _T_513) node _T_532 = or(_T_531, _T_520) node _T_533 = or(_T_429, _T_532) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_533, UInt<1>(0h1), "") : assert_7 node _T_537 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_539 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_540 = and(_T_538, _T_539) node _T_541 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_542 = and(_T_540, _T_541) node _T_543 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_546 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_547 = and(_T_545, _T_546) node _T_548 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_553 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_560 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_561 = and(_T_559, _T_560) node _T_562 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_567 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_568 = and(_T_566, _T_567) node _T_569 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_570 = and(_T_568, _T_569) node _T_571 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_574 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_575 = and(_T_573, _T_574) node _T_576 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_577 = and(_T_575, _T_576) node _T_578 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_581 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_582 = and(_T_580, _T_581) node _T_583 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_584 = and(_T_582, _T_583) node _T_585 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_586 = and(_T_584, _T_585) node _T_587 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_588 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_589 = and(_T_587, _T_588) node _T_590 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_591 = and(_T_589, _T_590) node _T_592 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_593 = and(_T_591, _T_592) node _T_594 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_595 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_596 = and(_T_594, _T_595) node _T_597 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_600 = and(_T_598, _T_599) node _T_601 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_602 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_605 = and(_T_603, _T_604) node _T_606 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_609 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_612 = and(_T_610, _T_611) node _T_613 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_614 = and(_T_612, _T_613) node _T_615 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_616 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_617 = and(_T_615, _T_616) node _T_618 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_619 = and(_T_617, _T_618) node _T_620 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_621 = and(_T_619, _T_620) node _T_622 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_623 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_624 = and(_T_622, _T_623) node _T_625 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(_T_544, _T_551) node _T_630 = or(_T_629, _T_558) node _T_631 = or(_T_630, _T_565) node _T_632 = or(_T_631, _T_572) node _T_633 = or(_T_632, _T_579) node _T_634 = or(_T_633, _T_586) node _T_635 = or(_T_634, _T_593) node _T_636 = or(_T_635, _T_600) node _T_637 = or(_T_636, _T_607) node _T_638 = or(_T_637, _T_614) node _T_639 = or(_T_638, _T_621) node _T_640 = or(_T_639, _T_628) node _T_641 = or(_T_537, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_641, UInt<1>(0h1), "") : assert_8	module NoCMonitor_66( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_46 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_92 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_46 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = and(io.in.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail invalidate route_buffer.io.enq.bits.flow.egress_node_id invalidate route_buffer.io.enq.bits.flow.egress_node invalidate route_buffer.io.enq.bits.flow.ingress_node_id invalidate route_buffer.io.enq.bits.flow.ingress_node invalidate route_buffer.io.enq.bits.flow.vnet_id connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h4)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_6 = and(io.in.ready, io.in.valid) node _T_7 = and(_T_6, io.in.bits.head) node _T_8 = and(_T_7, at_dest) when _T_8 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<4>(0he), io.in.bits.egress_id) when _T_9 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<4>(0hf), io.in.bits.egress_id) when _T_10 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<5>(0h10), io.in.bits.egress_id) when _T_11 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_12 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_13 = and(route_q.io.enq.valid, _T_12) node _T_14 = eq(_T_13, UInt<1>(0h0)) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_14, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_93 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_46 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_18 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(vcalloc_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2]) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1 connect io.in.ready, UInt<1>(0h0) connect io.router_req.valid, UInt<1>(0h0) invalidate io.router_req.bits.flow.egress_node_id invalidate io.router_req.bits.flow.egress_node invalidate io.router_req.bits.flow.ingress_node_id invalidate io.router_req.bits.flow.ingress_node invalidate io.router_req.bits.flow.vnet_id invalidate io.router_req.bits.src_virt_id connect io.vcalloc_req.valid, UInt<1>(0h0) invalidate io.vcalloc_req.bits.vc_sel.`0`[0] invalidate io.vcalloc_req.bits.vc_sel.`0`[1] invalidate io.vcalloc_req.bits.vc_sel.`0`[2] invalidate io.vcalloc_req.bits.vc_sel.`0`[3] invalidate io.vcalloc_req.bits.vc_sel.`0`[4] invalidate io.vcalloc_req.bits.vc_sel.`1`[0] invalidate io.vcalloc_req.bits.vc_sel.`2`[0] invalidate io.vcalloc_req.bits.vc_sel.`3`[0] invalidate io.vcalloc_req.bits.in_vc invalidate io.vcalloc_req.bits.flow.egress_node_id invalidate io.vcalloc_req.bits.flow.egress_node invalidate io.vcalloc_req.bits.flow.ingress_node_id invalidate io.vcalloc_req.bits.flow.ingress_node invalidate io.vcalloc_req.bits.flow.vnet_id connect io.salloc_req[0].valid, UInt<1>(0h0) invalidate io.salloc_req[0].bits.tail invalidate io.salloc_req[0].bits.vc_sel.`0`[0] invalidate io.salloc_req[0].bits.vc_sel.`0`[1] invalidate io.salloc_req[0].bits.vc_sel.`0`[2] invalidate io.salloc_req[0].bits.vc_sel.`0`[3] invalidate io.salloc_req[0].bits.vc_sel.`0`[4] invalidate io.salloc_req[0].bits.vc_sel.`1`[0] invalidate io.salloc_req[0].bits.vc_sel.`2`[0] invalidate io.salloc_req[0].bits.vc_sel.`3`[0] connect io.out[0].valid, UInt<1>(0h0) invalidate io.out[0].bits.out_virt_channel invalidate io.out[0].bits.flit.virt_channel_id invalidate io.out[0].bits.flit.flow.egress_node_id invalidate io.out[0].bits.flit.flow.egress_node invalidate io.out[0].bits.flit.flow.ingress_node_id invalidate io.out[0].bits.flit.flow.ingress_node invalidate io.out[0].bits.flit.flow.vnet_id invalidate io.out[0].bits.flit.payload invalidate io.out[0].bits.flit.tail invalidate io.out[0].bits.flit.head	module IngressUnit_46( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_28 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_28( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_473 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_473( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_13 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0)) node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0)) node ordered = and(_ordered_T, _ordered_T_1) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) node _common_ltMags_T = lt(rawA.sExp, rawB.sExp) node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig) node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1) node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2) node _common_eqMags_T = eq(rawA.sig, rawB.sig) node common_eqMags = and(eqExps, _common_eqMags_T) node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0)) node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1) node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0)) node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0)) node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4) node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0)) node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6) node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags) node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9) node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10) node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11) node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12) node _ordered_eq_T = eq(rawA.sign, rawB.sign) node _ordered_eq_T_1 = or(bothInfs, common_eqMags) node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1) node ordered_eq = or(bothZeros, _ordered_eq_T_2) node _invalid_T = bits(rawA.sig, 22, 22) node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0)) node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1) node _invalid_T_3 = bits(rawB.sig, 22, 22) node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0)) node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4) node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5) node _invalid_T_7 = eq(ordered, UInt<1>(0h0)) node _invalid_T_8 = and(io.signaling, _invalid_T_7) node invalid = or(_invalid_T_6, _invalid_T_8) node _io_lt_T = and(ordered, ordered_lt) connect io.lt, _io_lt_T node _io_eq_T = and(ordered, ordered_eq) connect io.eq, _io_eq_T node _io_gt_T = eq(ordered_lt, UInt<1>(0h0)) node _io_gt_T_1 = and(ordered, _io_gt_T) node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0)) node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2) connect io.gt, _io_gt_T_3 node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T	module CompareRecFN_13( // @[CompareRecFN.scala:42:7] input [32:0] io_b, // @[CompareRecFN.scala:44:16] output io_gt // @[CompareRecFN.scala:44:16] ); wire [32:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7] wire [8:0] rawA_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [9:0] rawA_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawA_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawA_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawA_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawA_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawA_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rawA_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawA_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _ordered_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _ordered_lt_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _invalid_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_signaling = 1'h0; // @[CompareRecFN.scala:42:7] wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawA_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire bothInfs = 1'h0; // @[CompareRecFN.scala:58:33] wire _ordered_lt_T_2 = 1'h0; // @[CompareRecFN.scala:67:25] wire _ordered_lt_T_5 = 1'h0; // @[CompareRecFN.scala:69:35] wire _ordered_lt_T_7 = 1'h0; // @[CompareRecFN.scala:69:54] wire _invalid_T = 1'h0; // @[common.scala:82:56] wire _invalid_T_2 = 1'h0; // @[common.scala:82:46] wire _invalid_T_8 = 1'h0; // @[CompareRecFN.scala:76:27] wire [32:0] io_a = 33'h15800000; // @[CompareRecFN.scala:42:7, :44:16] wire _io_lt_T; // @[CompareRecFN.scala:78:22] wire _io_eq_T; // @[CompareRecFN.scala:79:22] wire _io_gt_T_3; // @[CompareRecFN.scala:80:38] wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34] wire io_lt; // @[CompareRecFN.scala:42:7] wire io_eq; // @[CompareRecFN.scala:42:7] wire io_gt_0; // @[CompareRecFN.scala:42:7] wire [4:0] io_exceptionFlags; // @[CompareRecFN.scala:42:7] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire bothZeros = rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire ordered = _ordered_T_1; // @[CompareRecFN.scala:57:{32,35}] wire eqExps = rawB_sExp == 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _common_ltMags_T = $signed(rawB_sExp) > 10'sh2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _common_ltMags_T_1 = \|rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}] wire common_ltMags = _common_ltMags_T \| _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}] wire _common_eqMags_T = rawB_sig == 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}] wire _ordered_eq_T_1 = common_eqMags; // @[CompareRecFN.scala:63:32, :72:62] wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9] wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38] wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57] wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}] wire _ordered_lt_T_10 = _ordered_lt_T_9; // @[CompareRecFN.scala:69:74, :70:41] wire _ordered_lt_T_11 = _ordered_lt_T_10; // @[CompareRecFN.scala:68:30, :69:74] wire _ordered_lt_T_12 = _ordered_lt_T_11; // @[CompareRecFN.scala:67:41, :68:30] wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41] wire _ordered_eq_T = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}] wire ordered_eq = bothZeros \| _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}] wire _invalid_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}] wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_6 = _invalid_T_5; // @[common.scala:82:46] wire invalid = _invalid_T_6; // @[CompareRecFN.scala:75:{32,58}] wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30] assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22] assign io_lt = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22] assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22] assign io_eq = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22] wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25] wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}] wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41] assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}] assign io_gt_0 = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38] assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34] assign io_exceptionFlags = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34] assign io_gt = io_gt_0; // @[CompareRecFN.scala:42:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_1 : input clock : Clock input reset : Reset output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[1], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, flip get_ftq_pc : { flip ftq_idx : UInt<5>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} connect io.req.ready, UInt<1>(0h0) connect io.iresp.valid, UInt<1>(0h0) invalidate io.iresp.bits.fflags.bits.flags invalidate io.iresp.bits.fflags.bits.uop.debug_tsrc invalidate io.iresp.bits.fflags.bits.uop.debug_fsrc invalidate io.iresp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.iresp.bits.fflags.bits.uop.bp_debug_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.iresp.bits.fflags.bits.uop.fp_single invalidate io.iresp.bits.fflags.bits.uop.fp_val invalidate io.iresp.bits.fflags.bits.uop.frs3_en invalidate io.iresp.bits.fflags.bits.uop.lrs2_rtype invalidate io.iresp.bits.fflags.bits.uop.lrs1_rtype invalidate io.iresp.bits.fflags.bits.uop.dst_rtype invalidate io.iresp.bits.fflags.bits.uop.ldst_val invalidate io.iresp.bits.fflags.bits.uop.lrs3 invalidate io.iresp.bits.fflags.bits.uop.lrs2 invalidate io.iresp.bits.fflags.bits.uop.lrs1 invalidate io.iresp.bits.fflags.bits.uop.ldst invalidate io.iresp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.iresp.bits.fflags.bits.uop.flush_on_commit invalidate io.iresp.bits.fflags.bits.uop.is_unique invalidate io.iresp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.iresp.bits.fflags.bits.uop.uses_stq invalidate io.iresp.bits.fflags.bits.uop.uses_ldq invalidate io.iresp.bits.fflags.bits.uop.is_amo invalidate io.iresp.bits.fflags.bits.uop.is_fencei invalidate io.iresp.bits.fflags.bits.uop.is_fence invalidate io.iresp.bits.fflags.bits.uop.mem_signed invalidate io.iresp.bits.fflags.bits.uop.mem_size invalidate io.iresp.bits.fflags.bits.uop.mem_cmd invalidate io.iresp.bits.fflags.bits.uop.bypassable invalidate io.iresp.bits.fflags.bits.uop.exc_cause invalidate io.iresp.bits.fflags.bits.uop.exception invalidate io.iresp.bits.fflags.bits.uop.stale_pdst invalidate io.iresp.bits.fflags.bits.uop.ppred_busy invalidate io.iresp.bits.fflags.bits.uop.prs3_busy invalidate io.iresp.bits.fflags.bits.uop.prs2_busy invalidate io.iresp.bits.fflags.bits.uop.prs1_busy invalidate io.iresp.bits.fflags.bits.uop.ppred invalidate io.iresp.bits.fflags.bits.uop.prs3 invalidate io.iresp.bits.fflags.bits.uop.prs2 invalidate io.iresp.bits.fflags.bits.uop.prs1 invalidate io.iresp.bits.fflags.bits.uop.pdst invalidate io.iresp.bits.fflags.bits.uop.rxq_idx invalidate io.iresp.bits.fflags.bits.uop.stq_idx invalidate io.iresp.bits.fflags.bits.uop.ldq_idx invalidate io.iresp.bits.fflags.bits.uop.rob_idx invalidate io.iresp.bits.fflags.bits.uop.csr_addr invalidate io.iresp.bits.fflags.bits.uop.imm_packed invalidate io.iresp.bits.fflags.bits.uop.taken invalidate io.iresp.bits.fflags.bits.uop.pc_lob invalidate io.iresp.bits.fflags.bits.uop.edge_inst invalidate io.iresp.bits.fflags.bits.uop.ftq_idx invalidate io.iresp.bits.fflags.bits.uop.br_tag invalidate io.iresp.bits.fflags.bits.uop.br_mask invalidate io.iresp.bits.fflags.bits.uop.is_sfb invalidate io.iresp.bits.fflags.bits.uop.is_jal invalidate io.iresp.bits.fflags.bits.uop.is_jalr invalidate io.iresp.bits.fflags.bits.uop.is_br invalidate io.iresp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.iresp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.iresp.bits.fflags.bits.uop.iw_state invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_std invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_load invalidate io.iresp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.iresp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.iresp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.iresp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.br_type invalidate io.iresp.bits.fflags.bits.uop.fu_code invalidate io.iresp.bits.fflags.bits.uop.iq_type invalidate io.iresp.bits.fflags.bits.uop.debug_pc invalidate io.iresp.bits.fflags.bits.uop.is_rvc invalidate io.iresp.bits.fflags.bits.uop.debug_inst invalidate io.iresp.bits.fflags.bits.uop.inst invalidate io.iresp.bits.fflags.bits.uop.uopc invalidate io.iresp.bits.fflags.valid invalidate io.iresp.bits.predicated invalidate io.iresp.bits.data invalidate io.iresp.bits.uop.debug_tsrc invalidate io.iresp.bits.uop.debug_fsrc invalidate io.iresp.bits.uop.bp_xcpt_if invalidate io.iresp.bits.uop.bp_debug_if invalidate io.iresp.bits.uop.xcpt_ma_if invalidate io.iresp.bits.uop.xcpt_ae_if invalidate io.iresp.bits.uop.xcpt_pf_if invalidate io.iresp.bits.uop.fp_single invalidate io.iresp.bits.uop.fp_val invalidate io.iresp.bits.uop.frs3_en invalidate io.iresp.bits.uop.lrs2_rtype invalidate io.iresp.bits.uop.lrs1_rtype invalidate io.iresp.bits.uop.dst_rtype invalidate io.iresp.bits.uop.ldst_val invalidate io.iresp.bits.uop.lrs3 invalidate io.iresp.bits.uop.lrs2 invalidate io.iresp.bits.uop.lrs1 invalidate io.iresp.bits.uop.ldst invalidate io.iresp.bits.uop.ldst_is_rs1 invalidate io.iresp.bits.uop.flush_on_commit invalidate io.iresp.bits.uop.is_unique invalidate io.iresp.bits.uop.is_sys_pc2epc invalidate io.iresp.bits.uop.uses_stq invalidate io.iresp.bits.uop.uses_ldq invalidate io.iresp.bits.uop.is_amo invalidate io.iresp.bits.uop.is_fencei invalidate io.iresp.bits.uop.is_fence invalidate io.iresp.bits.uop.mem_signed invalidate io.iresp.bits.uop.mem_size invalidate io.iresp.bits.uop.mem_cmd invalidate io.iresp.bits.uop.bypassable invalidate io.iresp.bits.uop.exc_cause invalidate io.iresp.bits.uop.exception invalidate io.iresp.bits.uop.stale_pdst invalidate io.iresp.bits.uop.ppred_busy invalidate io.iresp.bits.uop.prs3_busy invalidate io.iresp.bits.uop.prs2_busy invalidate io.iresp.bits.uop.prs1_busy invalidate io.iresp.bits.uop.ppred invalidate io.iresp.bits.uop.prs3 invalidate io.iresp.bits.uop.prs2 invalidate io.iresp.bits.uop.prs1 invalidate io.iresp.bits.uop.pdst invalidate io.iresp.bits.uop.rxq_idx invalidate io.iresp.bits.uop.stq_idx invalidate io.iresp.bits.uop.ldq_idx invalidate io.iresp.bits.uop.rob_idx invalidate io.iresp.bits.uop.csr_addr invalidate io.iresp.bits.uop.imm_packed invalidate io.iresp.bits.uop.taken invalidate io.iresp.bits.uop.pc_lob invalidate io.iresp.bits.uop.edge_inst invalidate io.iresp.bits.uop.ftq_idx invalidate io.iresp.bits.uop.br_tag invalidate io.iresp.bits.uop.br_mask invalidate io.iresp.bits.uop.is_sfb invalidate io.iresp.bits.uop.is_jal invalidate io.iresp.bits.uop.is_jalr invalidate io.iresp.bits.uop.is_br invalidate io.iresp.bits.uop.iw_p2_poisoned invalidate io.iresp.bits.uop.iw_p1_poisoned invalidate io.iresp.bits.uop.iw_state invalidate io.iresp.bits.uop.ctrl.is_std invalidate io.iresp.bits.uop.ctrl.is_sta invalidate io.iresp.bits.uop.ctrl.is_load invalidate io.iresp.bits.uop.ctrl.csr_cmd invalidate io.iresp.bits.uop.ctrl.fcn_dw invalidate io.iresp.bits.uop.ctrl.op_fcn invalidate io.iresp.bits.uop.ctrl.imm_sel invalidate io.iresp.bits.uop.ctrl.op2_sel invalidate io.iresp.bits.uop.ctrl.op1_sel invalidate io.iresp.bits.uop.ctrl.br_type invalidate io.iresp.bits.uop.fu_code invalidate io.iresp.bits.uop.iq_type invalidate io.iresp.bits.uop.debug_pc invalidate io.iresp.bits.uop.is_rvc invalidate io.iresp.bits.uop.debug_inst invalidate io.iresp.bits.uop.inst invalidate io.iresp.bits.uop.uopc connect io.iresp.bits.fflags.valid, UInt<1>(0h0) connect io.iresp.bits.predicated, UInt<1>(0h0) node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : node _T_2 = eq(io.iresp.ready, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:147 assert(io.iresp.ready)\n") : printf assert(clock, io.iresp.ready, UInt<1>(0h1), "") : assert wire div_busy : UInt<1> connect div_busy, UInt<1>(0h0) wire ifpu_busy : UInt<1> connect ifpu_busy, UInt<1>(0h0) node _io_fu_types_T = mux(UInt<1>(0h1), UInt<10>(0h1), UInt<1>(0h0)) node _io_fu_types_T_1 = mux(UInt<1>(0h0), UInt<10>(0h8), UInt<1>(0h0)) node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1) node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0)) node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h1)) node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0)) node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5) node _io_fu_types_T_7 = mux(UInt<1>(0h0), UInt<10>(0h20), UInt<1>(0h0)) node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7) node _io_fu_types_T_9 = mux(UInt<1>(0h1), UInt<10>(0h2), UInt<1>(0h0)) node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9) node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0)) node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h0)) node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0)) node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13) node _io_fu_types_T_15 = mux(UInt<1>(0h0), UInt<10>(0h4), UInt<1>(0h0)) node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15) connect io.fu_types, _io_fu_types_T_16 inst ALUUnit of ALUUnit connect ALUUnit.clock, clock connect ALUUnit.reset, reset node _T_3 = eq(io.req.bits.uop.fu_code, UInt<10>(0h1)) node _T_4 = eq(io.req.bits.uop.fu_code, UInt<10>(0h2)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(io.req.bits.uop.fu_code, UInt<10>(0h20)) node _T_7 = neq(io.req.bits.uop.uopc, UInt<7>(0h6c)) node _T_8 = and(_T_6, _T_7) node _T_9 = or(_T_5, _T_8) node _T_10 = and(io.req.valid, _T_9) connect ALUUnit.io.req.valid, _T_10 connect ALUUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect ALUUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect ALUUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect ALUUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect ALUUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect ALUUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect ALUUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect ALUUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect ALUUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect ALUUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect ALUUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect ALUUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect ALUUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect ALUUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect ALUUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect ALUUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect ALUUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect ALUUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect ALUUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect ALUUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect ALUUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect ALUUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect ALUUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect ALUUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect ALUUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect ALUUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect ALUUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect ALUUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect ALUUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect ALUUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect ALUUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect ALUUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect ALUUnit.io.req.bits.uop.exception, io.req.bits.uop.exception connect ALUUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect ALUUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect ALUUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect ALUUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect ALUUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect ALUUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect ALUUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect ALUUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect ALUUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect ALUUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect ALUUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect ALUUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect ALUUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect ALUUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect ALUUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect ALUUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect ALUUnit.io.req.bits.uop.taken, io.req.bits.uop.taken connect ALUUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect ALUUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect ALUUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect ALUUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect ALUUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect ALUUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect ALUUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect ALUUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect ALUUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect ALUUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect ALUUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect ALUUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect ALUUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect ALUUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect ALUUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect ALUUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect ALUUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect ALUUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect ALUUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect ALUUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect ALUUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect ALUUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect ALUUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect ALUUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect ALUUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect ALUUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect ALUUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect ALUUnit.io.req.bits.uop.inst, io.req.bits.uop.inst connect ALUUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect ALUUnit.io.req.bits.kill, io.req.bits.kill connect ALUUnit.io.req.bits.rs1_data, io.req.bits.rs1_data connect ALUUnit.io.req.bits.rs2_data, io.req.bits.rs2_data invalidate ALUUnit.io.req.bits.rs3_data connect ALUUnit.io.req.bits.pred_data, io.req.bits.pred_data invalidate ALUUnit.io.resp.ready connect ALUUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect ALUUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect ALUUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect ALUUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect ALUUnit.io.brupdate.b2.taken, io.brupdate.b2.taken connect ALUUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect ALUUnit.io.brupdate.b2.valid, io.brupdate.b2.valid connect ALUUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect ALUUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect ALUUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect ALUUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect ALUUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect ALUUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect ALUUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect ALUUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect ALUUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect ALUUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect ALUUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect ALUUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect ALUUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect ALUUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect ALUUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect ALUUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect ALUUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect ALUUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect ALUUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect ALUUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect ALUUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect ALUUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect ALUUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect ALUUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect ALUUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect ALUUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect ALUUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect ALUUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect ALUUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect ALUUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect ALUUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect ALUUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect ALUUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect ALUUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect ALUUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect ALUUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect ALUUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect ALUUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect ALUUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect ALUUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect ALUUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect ALUUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect ALUUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect ALUUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect ALUUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect ALUUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect ALUUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect ALUUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect ALUUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect ALUUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect ALUUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect ALUUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect ALUUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect ALUUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect ALUUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect ALUUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect ALUUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect ALUUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect ALUUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect ALUUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect ALUUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect ALUUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect ALUUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect ALUUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect ALUUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect ALUUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect ALUUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect ALUUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect ALUUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect ALUUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect ALUUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect ALUUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect ALUUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect ALUUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect ALUUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect ALUUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect ALUUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect ALUUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect io.bypass, ALUUnit.io.bypass connect io.brinfo, ALUUnit.io.brinfo connect ALUUnit.io.get_ftq_pc, io.get_ftq_pc wire div_resp_val : UInt<1> connect div_resp_val, UInt<1>(0h0) inst DivUnit of DivUnit connect DivUnit.clock, clock connect DivUnit.reset, reset invalidate DivUnit.io.brupdate.b2.target_offset invalidate DivUnit.io.brupdate.b2.jalr_target invalidate DivUnit.io.brupdate.b2.pc_sel invalidate DivUnit.io.brupdate.b2.cfi_type invalidate DivUnit.io.brupdate.b2.taken invalidate DivUnit.io.brupdate.b2.mispredict invalidate DivUnit.io.brupdate.b2.valid invalidate DivUnit.io.brupdate.b2.uop.debug_tsrc invalidate DivUnit.io.brupdate.b2.uop.debug_fsrc invalidate DivUnit.io.brupdate.b2.uop.bp_xcpt_if invalidate DivUnit.io.brupdate.b2.uop.bp_debug_if invalidate DivUnit.io.brupdate.b2.uop.xcpt_ma_if invalidate DivUnit.io.brupdate.b2.uop.xcpt_ae_if invalidate DivUnit.io.brupdate.b2.uop.xcpt_pf_if invalidate DivUnit.io.brupdate.b2.uop.fp_single invalidate DivUnit.io.brupdate.b2.uop.fp_val invalidate DivUnit.io.brupdate.b2.uop.frs3_en invalidate DivUnit.io.brupdate.b2.uop.lrs2_rtype invalidate DivUnit.io.brupdate.b2.uop.lrs1_rtype invalidate DivUnit.io.brupdate.b2.uop.dst_rtype invalidate DivUnit.io.brupdate.b2.uop.ldst_val invalidate DivUnit.io.brupdate.b2.uop.lrs3 invalidate DivUnit.io.brupdate.b2.uop.lrs2 invalidate DivUnit.io.brupdate.b2.uop.lrs1 invalidate DivUnit.io.brupdate.b2.uop.ldst invalidate DivUnit.io.brupdate.b2.uop.ldst_is_rs1 invalidate DivUnit.io.brupdate.b2.uop.flush_on_commit invalidate DivUnit.io.brupdate.b2.uop.is_unique invalidate DivUnit.io.brupdate.b2.uop.is_sys_pc2epc invalidate DivUnit.io.brupdate.b2.uop.uses_stq invalidate DivUnit.io.brupdate.b2.uop.uses_ldq invalidate DivUnit.io.brupdate.b2.uop.is_amo invalidate DivUnit.io.brupdate.b2.uop.is_fencei invalidate DivUnit.io.brupdate.b2.uop.is_fence invalidate DivUnit.io.brupdate.b2.uop.mem_signed invalidate DivUnit.io.brupdate.b2.uop.mem_size invalidate DivUnit.io.brupdate.b2.uop.mem_cmd invalidate DivUnit.io.brupdate.b2.uop.bypassable invalidate DivUnit.io.brupdate.b2.uop.exc_cause invalidate DivUnit.io.brupdate.b2.uop.exception invalidate DivUnit.io.brupdate.b2.uop.stale_pdst invalidate DivUnit.io.brupdate.b2.uop.ppred_busy invalidate DivUnit.io.brupdate.b2.uop.prs3_busy invalidate DivUnit.io.brupdate.b2.uop.prs2_busy invalidate DivUnit.io.brupdate.b2.uop.prs1_busy invalidate DivUnit.io.brupdate.b2.uop.ppred invalidate DivUnit.io.brupdate.b2.uop.prs3 invalidate DivUnit.io.brupdate.b2.uop.prs2 invalidate DivUnit.io.brupdate.b2.uop.prs1 invalidate DivUnit.io.brupdate.b2.uop.pdst invalidate DivUnit.io.brupdate.b2.uop.rxq_idx invalidate DivUnit.io.brupdate.b2.uop.stq_idx invalidate DivUnit.io.brupdate.b2.uop.ldq_idx invalidate DivUnit.io.brupdate.b2.uop.rob_idx invalidate DivUnit.io.brupdate.b2.uop.csr_addr invalidate DivUnit.io.brupdate.b2.uop.imm_packed invalidate DivUnit.io.brupdate.b2.uop.taken invalidate DivUnit.io.brupdate.b2.uop.pc_lob invalidate DivUnit.io.brupdate.b2.uop.edge_inst invalidate DivUnit.io.brupdate.b2.uop.ftq_idx invalidate DivUnit.io.brupdate.b2.uop.br_tag invalidate DivUnit.io.brupdate.b2.uop.br_mask invalidate DivUnit.io.brupdate.b2.uop.is_sfb invalidate DivUnit.io.brupdate.b2.uop.is_jal invalidate DivUnit.io.brupdate.b2.uop.is_jalr invalidate DivUnit.io.brupdate.b2.uop.is_br invalidate DivUnit.io.brupdate.b2.uop.iw_p2_poisoned invalidate DivUnit.io.brupdate.b2.uop.iw_p1_poisoned invalidate DivUnit.io.brupdate.b2.uop.iw_state invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_std invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_sta invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_load invalidate DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd invalidate DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw invalidate DivUnit.io.brupdate.b2.uop.ctrl.op_fcn invalidate DivUnit.io.brupdate.b2.uop.ctrl.imm_sel invalidate DivUnit.io.brupdate.b2.uop.ctrl.op2_sel invalidate DivUnit.io.brupdate.b2.uop.ctrl.op1_sel invalidate DivUnit.io.brupdate.b2.uop.ctrl.br_type invalidate DivUnit.io.brupdate.b2.uop.fu_code invalidate DivUnit.io.brupdate.b2.uop.iq_type invalidate DivUnit.io.brupdate.b2.uop.debug_pc invalidate DivUnit.io.brupdate.b2.uop.is_rvc invalidate DivUnit.io.brupdate.b2.uop.debug_inst invalidate DivUnit.io.brupdate.b2.uop.inst invalidate DivUnit.io.brupdate.b2.uop.uopc invalidate DivUnit.io.brupdate.b1.mispredict_mask invalidate DivUnit.io.brupdate.b1.resolve_mask invalidate DivUnit.io.resp.bits.sfence.bits.hg invalidate DivUnit.io.resp.bits.sfence.bits.hv invalidate DivUnit.io.resp.bits.sfence.bits.asid invalidate DivUnit.io.resp.bits.sfence.bits.addr invalidate DivUnit.io.resp.bits.sfence.bits.rs2 invalidate DivUnit.io.resp.bits.sfence.bits.rs1 invalidate DivUnit.io.resp.bits.sfence.valid invalidate DivUnit.io.resp.bits.mxcpt.bits invalidate DivUnit.io.resp.bits.mxcpt.valid invalidate DivUnit.io.resp.bits.addr invalidate DivUnit.io.resp.bits.fflags.bits.flags invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_tsrc invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_fsrc invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_debug_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_single invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_val invalidate DivUnit.io.resp.bits.fflags.bits.uop.frs3_en invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate DivUnit.io.resp.bits.fflags.bits.uop.dst_rtype invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_val invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs3 invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2 invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1 invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate DivUnit.io.resp.bits.fflags.bits.uop.flush_on_commit invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_unique invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_stq invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_ldq invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_amo invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fencei invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fence invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_signed invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_size invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_cmd invalidate DivUnit.io.resp.bits.fflags.bits.uop.bypassable invalidate DivUnit.io.resp.bits.fflags.bits.uop.exc_cause invalidate DivUnit.io.resp.bits.fflags.bits.uop.exception invalidate DivUnit.io.resp.bits.fflags.bits.uop.stale_pdst invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3 invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2 invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1 invalidate DivUnit.io.resp.bits.fflags.bits.uop.pdst invalidate DivUnit.io.resp.bits.fflags.bits.uop.rxq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.stq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.rob_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.csr_addr invalidate DivUnit.io.resp.bits.fflags.bits.uop.imm_packed invalidate DivUnit.io.resp.bits.fflags.bits.uop.taken invalidate DivUnit.io.resp.bits.fflags.bits.uop.pc_lob invalidate DivUnit.io.resp.bits.fflags.bits.uop.edge_inst invalidate DivUnit.io.resp.bits.fflags.bits.uop.ftq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_tag invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_mask invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sfb invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jal invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jalr invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_br invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_state invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate DivUnit.io.resp.bits.fflags.bits.uop.fu_code invalidate DivUnit.io.resp.bits.fflags.bits.uop.iq_type invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_pc invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_rvc invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_inst invalidate DivUnit.io.resp.bits.fflags.bits.uop.inst invalidate DivUnit.io.resp.bits.fflags.bits.uop.uopc invalidate DivUnit.io.resp.bits.fflags.valid invalidate DivUnit.io.resp.bits.data invalidate DivUnit.io.resp.bits.predicated invalidate DivUnit.io.resp.bits.uop.debug_tsrc invalidate DivUnit.io.resp.bits.uop.debug_fsrc invalidate DivUnit.io.resp.bits.uop.bp_xcpt_if invalidate DivUnit.io.resp.bits.uop.bp_debug_if invalidate DivUnit.io.resp.bits.uop.xcpt_ma_if invalidate DivUnit.io.resp.bits.uop.xcpt_ae_if invalidate DivUnit.io.resp.bits.uop.xcpt_pf_if invalidate DivUnit.io.resp.bits.uop.fp_single invalidate DivUnit.io.resp.bits.uop.fp_val invalidate DivUnit.io.resp.bits.uop.frs3_en invalidate DivUnit.io.resp.bits.uop.lrs2_rtype invalidate DivUnit.io.resp.bits.uop.lrs1_rtype invalidate DivUnit.io.resp.bits.uop.dst_rtype invalidate DivUnit.io.resp.bits.uop.ldst_val invalidate DivUnit.io.resp.bits.uop.lrs3 invalidate DivUnit.io.resp.bits.uop.lrs2 invalidate DivUnit.io.resp.bits.uop.lrs1 invalidate DivUnit.io.resp.bits.uop.ldst invalidate DivUnit.io.resp.bits.uop.ldst_is_rs1 invalidate DivUnit.io.resp.bits.uop.flush_on_commit invalidate DivUnit.io.resp.bits.uop.is_unique invalidate DivUnit.io.resp.bits.uop.is_sys_pc2epc invalidate DivUnit.io.resp.bits.uop.uses_stq invalidate DivUnit.io.resp.bits.uop.uses_ldq invalidate DivUnit.io.resp.bits.uop.is_amo invalidate DivUnit.io.resp.bits.uop.is_fencei invalidate DivUnit.io.resp.bits.uop.is_fence invalidate DivUnit.io.resp.bits.uop.mem_signed invalidate DivUnit.io.resp.bits.uop.mem_size invalidate DivUnit.io.resp.bits.uop.mem_cmd invalidate DivUnit.io.resp.bits.uop.bypassable invalidate DivUnit.io.resp.bits.uop.exc_cause invalidate DivUnit.io.resp.bits.uop.exception invalidate DivUnit.io.resp.bits.uop.stale_pdst invalidate DivUnit.io.resp.bits.uop.ppred_busy invalidate DivUnit.io.resp.bits.uop.prs3_busy invalidate DivUnit.io.resp.bits.uop.prs2_busy invalidate DivUnit.io.resp.bits.uop.prs1_busy invalidate DivUnit.io.resp.bits.uop.ppred invalidate DivUnit.io.resp.bits.uop.prs3 invalidate DivUnit.io.resp.bits.uop.prs2 invalidate DivUnit.io.resp.bits.uop.prs1 invalidate DivUnit.io.resp.bits.uop.pdst invalidate DivUnit.io.resp.bits.uop.rxq_idx invalidate DivUnit.io.resp.bits.uop.stq_idx invalidate DivUnit.io.resp.bits.uop.ldq_idx invalidate DivUnit.io.resp.bits.uop.rob_idx invalidate DivUnit.io.resp.bits.uop.csr_addr invalidate DivUnit.io.resp.bits.uop.imm_packed invalidate DivUnit.io.resp.bits.uop.taken invalidate DivUnit.io.resp.bits.uop.pc_lob invalidate DivUnit.io.resp.bits.uop.edge_inst invalidate DivUnit.io.resp.bits.uop.ftq_idx invalidate DivUnit.io.resp.bits.uop.br_tag invalidate DivUnit.io.resp.bits.uop.br_mask invalidate DivUnit.io.resp.bits.uop.is_sfb invalidate DivUnit.io.resp.bits.uop.is_jal invalidate DivUnit.io.resp.bits.uop.is_jalr invalidate DivUnit.io.resp.bits.uop.is_br invalidate DivUnit.io.resp.bits.uop.iw_p2_poisoned invalidate DivUnit.io.resp.bits.uop.iw_p1_poisoned invalidate DivUnit.io.resp.bits.uop.iw_state invalidate DivUnit.io.resp.bits.uop.ctrl.is_std invalidate DivUnit.io.resp.bits.uop.ctrl.is_sta invalidate DivUnit.io.resp.bits.uop.ctrl.is_load invalidate DivUnit.io.resp.bits.uop.ctrl.csr_cmd invalidate DivUnit.io.resp.bits.uop.ctrl.fcn_dw invalidate DivUnit.io.resp.bits.uop.ctrl.op_fcn invalidate DivUnit.io.resp.bits.uop.ctrl.imm_sel invalidate DivUnit.io.resp.bits.uop.ctrl.op2_sel invalidate DivUnit.io.resp.bits.uop.ctrl.op1_sel invalidate DivUnit.io.resp.bits.uop.ctrl.br_type invalidate DivUnit.io.resp.bits.uop.fu_code invalidate DivUnit.io.resp.bits.uop.iq_type invalidate DivUnit.io.resp.bits.uop.debug_pc invalidate DivUnit.io.resp.bits.uop.is_rvc invalidate DivUnit.io.resp.bits.uop.debug_inst invalidate DivUnit.io.resp.bits.uop.inst invalidate DivUnit.io.resp.bits.uop.uopc invalidate DivUnit.io.resp.valid invalidate DivUnit.io.resp.ready invalidate DivUnit.io.req.bits.kill invalidate DivUnit.io.req.bits.pred_data invalidate DivUnit.io.req.bits.rs3_data invalidate DivUnit.io.req.bits.rs2_data invalidate DivUnit.io.req.bits.rs1_data invalidate DivUnit.io.req.bits.uop.debug_tsrc invalidate DivUnit.io.req.bits.uop.debug_fsrc invalidate DivUnit.io.req.bits.uop.bp_xcpt_if invalidate DivUnit.io.req.bits.uop.bp_debug_if invalidate DivUnit.io.req.bits.uop.xcpt_ma_if invalidate DivUnit.io.req.bits.uop.xcpt_ae_if invalidate DivUnit.io.req.bits.uop.xcpt_pf_if invalidate DivUnit.io.req.bits.uop.fp_single invalidate DivUnit.io.req.bits.uop.fp_val invalidate DivUnit.io.req.bits.uop.frs3_en invalidate DivUnit.io.req.bits.uop.lrs2_rtype invalidate DivUnit.io.req.bits.uop.lrs1_rtype invalidate DivUnit.io.req.bits.uop.dst_rtype invalidate DivUnit.io.req.bits.uop.ldst_val invalidate DivUnit.io.req.bits.uop.lrs3 invalidate DivUnit.io.req.bits.uop.lrs2 invalidate DivUnit.io.req.bits.uop.lrs1 invalidate DivUnit.io.req.bits.uop.ldst invalidate DivUnit.io.req.bits.uop.ldst_is_rs1 invalidate DivUnit.io.req.bits.uop.flush_on_commit invalidate DivUnit.io.req.bits.uop.is_unique invalidate DivUnit.io.req.bits.uop.is_sys_pc2epc invalidate DivUnit.io.req.bits.uop.uses_stq invalidate DivUnit.io.req.bits.uop.uses_ldq invalidate DivUnit.io.req.bits.uop.is_amo invalidate DivUnit.io.req.bits.uop.is_fencei invalidate DivUnit.io.req.bits.uop.is_fence invalidate DivUnit.io.req.bits.uop.mem_signed invalidate DivUnit.io.req.bits.uop.mem_size invalidate DivUnit.io.req.bits.uop.mem_cmd invalidate DivUnit.io.req.bits.uop.bypassable invalidate DivUnit.io.req.bits.uop.exc_cause invalidate DivUnit.io.req.bits.uop.exception invalidate DivUnit.io.req.bits.uop.stale_pdst invalidate DivUnit.io.req.bits.uop.ppred_busy invalidate DivUnit.io.req.bits.uop.prs3_busy invalidate DivUnit.io.req.bits.uop.prs2_busy invalidate DivUnit.io.req.bits.uop.prs1_busy invalidate DivUnit.io.req.bits.uop.ppred invalidate DivUnit.io.req.bits.uop.prs3 invalidate DivUnit.io.req.bits.uop.prs2 invalidate DivUnit.io.req.bits.uop.prs1 invalidate DivUnit.io.req.bits.uop.pdst invalidate DivUnit.io.req.bits.uop.rxq_idx invalidate DivUnit.io.req.bits.uop.stq_idx invalidate DivUnit.io.req.bits.uop.ldq_idx invalidate DivUnit.io.req.bits.uop.rob_idx invalidate DivUnit.io.req.bits.uop.csr_addr invalidate DivUnit.io.req.bits.uop.imm_packed invalidate DivUnit.io.req.bits.uop.taken invalidate DivUnit.io.req.bits.uop.pc_lob invalidate DivUnit.io.req.bits.uop.edge_inst invalidate DivUnit.io.req.bits.uop.ftq_idx invalidate DivUnit.io.req.bits.uop.br_tag invalidate DivUnit.io.req.bits.uop.br_mask invalidate DivUnit.io.req.bits.uop.is_sfb invalidate DivUnit.io.req.bits.uop.is_jal invalidate DivUnit.io.req.bits.uop.is_jalr invalidate DivUnit.io.req.bits.uop.is_br invalidate DivUnit.io.req.bits.uop.iw_p2_poisoned invalidate DivUnit.io.req.bits.uop.iw_p1_poisoned invalidate DivUnit.io.req.bits.uop.iw_state invalidate DivUnit.io.req.bits.uop.ctrl.is_std invalidate DivUnit.io.req.bits.uop.ctrl.is_sta invalidate DivUnit.io.req.bits.uop.ctrl.is_load invalidate DivUnit.io.req.bits.uop.ctrl.csr_cmd invalidate DivUnit.io.req.bits.uop.ctrl.fcn_dw invalidate DivUnit.io.req.bits.uop.ctrl.op_fcn invalidate DivUnit.io.req.bits.uop.ctrl.imm_sel invalidate DivUnit.io.req.bits.uop.ctrl.op2_sel invalidate DivUnit.io.req.bits.uop.ctrl.op1_sel invalidate DivUnit.io.req.bits.uop.ctrl.br_type invalidate DivUnit.io.req.bits.uop.fu_code invalidate DivUnit.io.req.bits.uop.iq_type invalidate DivUnit.io.req.bits.uop.debug_pc invalidate DivUnit.io.req.bits.uop.is_rvc invalidate DivUnit.io.req.bits.uop.debug_inst invalidate DivUnit.io.req.bits.uop.inst invalidate DivUnit.io.req.bits.uop.uopc invalidate DivUnit.io.req.valid invalidate DivUnit.io.req.ready node _T_11 = and(io.req.bits.uop.fu_code, UInt<10>(0h10)) node _T_12 = neq(_T_11, UInt<1>(0h0)) node _T_13 = and(io.req.valid, _T_12) node _T_14 = and(_T_13, UInt<1>(0h1)) connect DivUnit.io.req.valid, _T_14 connect DivUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect DivUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect DivUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect DivUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect DivUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect DivUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect DivUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect DivUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect DivUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect DivUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect DivUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect DivUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect DivUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect DivUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect DivUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect DivUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect DivUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect DivUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect DivUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect DivUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect DivUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect DivUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect DivUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect DivUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect DivUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect DivUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect DivUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect DivUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect DivUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect DivUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect DivUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect DivUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect DivUnit.io.req.bits.uop.exception, io.req.bits.uop.exception connect DivUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect DivUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect DivUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect DivUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect DivUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect DivUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect DivUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect DivUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect DivUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect DivUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect DivUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect DivUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect DivUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect DivUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect DivUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect DivUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect DivUnit.io.req.bits.uop.taken, io.req.bits.uop.taken connect DivUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect DivUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect DivUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect DivUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect DivUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect DivUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect DivUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect DivUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect DivUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect DivUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect DivUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect DivUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect DivUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect DivUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect DivUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect DivUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect DivUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect DivUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect DivUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect DivUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect DivUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect DivUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect DivUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect DivUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect DivUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect DivUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect DivUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect DivUnit.io.req.bits.uop.inst, io.req.bits.uop.inst connect DivUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect DivUnit.io.req.bits.rs1_data, io.req.bits.rs1_data connect DivUnit.io.req.bits.rs2_data, io.req.bits.rs2_data connect DivUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect DivUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect DivUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect DivUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect DivUnit.io.brupdate.b2.taken, io.brupdate.b2.taken connect DivUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect DivUnit.io.brupdate.b2.valid, io.brupdate.b2.valid connect DivUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect DivUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect DivUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect DivUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect DivUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect DivUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect DivUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect DivUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect DivUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect DivUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect DivUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect DivUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect DivUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect DivUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect DivUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect DivUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect DivUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect DivUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect DivUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect DivUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect DivUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect DivUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect DivUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect DivUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect DivUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect DivUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect DivUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect DivUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect DivUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect DivUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect DivUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect DivUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect DivUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect DivUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect DivUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect DivUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect DivUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect DivUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect DivUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect DivUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect DivUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect DivUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect DivUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect DivUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect DivUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect DivUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect DivUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect DivUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect DivUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect DivUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect DivUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect DivUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect DivUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect DivUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect DivUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect DivUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect DivUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect DivUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect DivUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect DivUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect DivUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect DivUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect DivUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect DivUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect DivUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect DivUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect DivUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect DivUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect DivUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect DivUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect DivUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect DivUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect DivUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect DivUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect DivUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect DivUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect DivUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect DivUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect DivUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect DivUnit.io.req.bits.kill, io.req.bits.kill node _T_15 = eq(ALUUnit.io.resp.valid, UInt<1>(0h0)) connect DivUnit.io.resp.ready, _T_15 connect div_resp_val, DivUnit.io.resp.valid node _div_busy_T = eq(DivUnit.io.req.ready, UInt<1>(0h0)) node _div_busy_T_1 = and(io.req.bits.uop.fu_code, UInt<10>(0h10)) node _div_busy_T_2 = neq(_div_busy_T_1, UInt<1>(0h0)) node _div_busy_T_3 = and(io.req.valid, _div_busy_T_2) node _div_busy_T_4 = or(_div_busy_T, _div_busy_T_3) connect div_busy, _div_busy_T_4 node _io_iresp_valid_T = or(ALUUnit.io.resp.valid, DivUnit.io.resp.valid) connect io.iresp.valid, _io_iresp_valid_T node _io_iresp_bits_uop_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.uop, DivUnit.io.resp.bits.uop) connect io.iresp.bits.uop, _io_iresp_bits_uop_T node _io_iresp_bits_data_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.data, DivUnit.io.resp.bits.data) connect io.iresp.bits.data, _io_iresp_bits_data_T node _io_iresp_bits_predicated_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.predicated, DivUnit.io.resp.bits.predicated) connect io.iresp.bits.predicated, _io_iresp_bits_predicated_T node _io_iresp_bits_uop_csr_addr_sign_T = bits(ALUUnit.io.resp.bits.uop.imm_packed, 19, 19) node io_iresp_bits_uop_csr_addr_sign = asSInt(_io_iresp_bits_uop_csr_addr_sign_T) node _io_iresp_bits_uop_csr_addr_i30_20_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i30_20_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 8) node _io_iresp_bits_uop_csr_addr_i30_20_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i30_20_T_1) node io_iresp_bits_uop_csr_addr_i30_20 = mux(_io_iresp_bits_uop_csr_addr_i30_20_T, _io_iresp_bits_uop_csr_addr_i30_20_T_2, io_iresp_bits_uop_csr_addr_sign) node _io_iresp_bits_uop_csr_addr_i19_12_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i19_12_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4)) node _io_iresp_bits_uop_csr_addr_i19_12_T_2 = or(_io_iresp_bits_uop_csr_addr_i19_12_T, _io_iresp_bits_uop_csr_addr_i19_12_T_1) node _io_iresp_bits_uop_csr_addr_i19_12_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 7, 0) node _io_iresp_bits_uop_csr_addr_i19_12_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i19_12_T_3) node io_iresp_bits_uop_csr_addr_i19_12 = mux(_io_iresp_bits_uop_csr_addr_i19_12_T_2, _io_iresp_bits_uop_csr_addr_i19_12_T_4, io_iresp_bits_uop_csr_addr_sign) node _io_iresp_bits_uop_csr_addr_i11_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i11_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4)) node _io_iresp_bits_uop_csr_addr_i11_T_2 = eq(UInt<3>(0h0), UInt<3>(0h2)) node _io_iresp_bits_uop_csr_addr_i11_T_3 = or(_io_iresp_bits_uop_csr_addr_i11_T_1, _io_iresp_bits_uop_csr_addr_i11_T_2) node _io_iresp_bits_uop_csr_addr_i11_T_4 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8) node _io_iresp_bits_uop_csr_addr_i11_T_5 = asSInt(_io_iresp_bits_uop_csr_addr_i11_T_4) node _io_iresp_bits_uop_csr_addr_i11_T_6 = mux(_io_iresp_bits_uop_csr_addr_i11_T_3, _io_iresp_bits_uop_csr_addr_i11_T_5, io_iresp_bits_uop_csr_addr_sign) node io_iresp_bits_uop_csr_addr_i11 = mux(_io_iresp_bits_uop_csr_addr_i11_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i11_T_6) node _io_iresp_bits_uop_csr_addr_i10_5_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i10_5_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 14) node _io_iresp_bits_uop_csr_addr_i10_5_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i10_5_T_1) node io_iresp_bits_uop_csr_addr_i10_5 = mux(_io_iresp_bits_uop_csr_addr_i10_5_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i10_5_T_2) node _io_iresp_bits_uop_csr_addr_i4_1_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i4_1_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 13, 9) node _io_iresp_bits_uop_csr_addr_i4_1_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i4_1_T_1) node io_iresp_bits_uop_csr_addr_i4_1 = mux(_io_iresp_bits_uop_csr_addr_i4_1_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i4_1_T_2) node _io_iresp_bits_uop_csr_addr_i0_T = eq(UInt<3>(0h0), UInt<3>(0h1)) node _io_iresp_bits_uop_csr_addr_i0_T_1 = eq(UInt<3>(0h0), UInt<3>(0h0)) node _io_iresp_bits_uop_csr_addr_i0_T_2 = or(_io_iresp_bits_uop_csr_addr_i0_T, _io_iresp_bits_uop_csr_addr_i0_T_1) node _io_iresp_bits_uop_csr_addr_i0_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8) node _io_iresp_bits_uop_csr_addr_i0_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i0_T_3) node io_iresp_bits_uop_csr_addr_i0 = mux(_io_iresp_bits_uop_csr_addr_i0_T_2, _io_iresp_bits_uop_csr_addr_i0_T_4, asSInt(UInt<1>(0h0))) node io_iresp_bits_uop_csr_addr_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i0) node io_iresp_bits_uop_csr_addr_lo_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i4_1) node io_iresp_bits_uop_csr_addr_lo_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_i10_5) node io_iresp_bits_uop_csr_addr_lo_hi = cat(io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo) node io_iresp_bits_uop_csr_addr_lo = cat(io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo) node io_iresp_bits_uop_csr_addr_hi_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i11) node io_iresp_bits_uop_csr_addr_hi_lo_hi = asUInt(io_iresp_bits_uop_csr_addr_i19_12) node io_iresp_bits_uop_csr_addr_hi_lo = cat(io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo) node io_iresp_bits_uop_csr_addr_hi_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i30_20) node io_iresp_bits_uop_csr_addr_hi_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_sign) node io_iresp_bits_uop_csr_addr_hi_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo) node io_iresp_bits_uop_csr_addr_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo) node _io_iresp_bits_uop_csr_addr_T = cat(io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo) node _io_iresp_bits_uop_csr_addr_T_1 = asSInt(_io_iresp_bits_uop_csr_addr_T) node _io_iresp_bits_uop_csr_addr_T_2 = asUInt(_io_iresp_bits_uop_csr_addr_T_1) connect io.iresp.bits.uop.csr_addr, _io_iresp_bits_uop_csr_addr_T_2 connect io.iresp.bits.uop.ctrl.csr_cmd, ALUUnit.io.resp.bits.uop.ctrl.csr_cmd node _T_16 = add(ALUUnit.io.resp.valid, DivUnit.io.resp.valid) node _T_17 = bits(_T_16, 1, 0) node _T_18 = leq(_T_17, UInt<1>(0h1)) node _T_19 = eq(div_resp_val, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = add(ALUUnit.io.resp.valid, DivUnit.io.resp.valid) node _T_22 = bits(_T_21, 1, 0) node _T_23 = leq(_T_22, UInt<2>(0h2)) node _T_24 = and(_T_23, div_resp_val) node _T_25 = or(_T_20, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: Multiple functional units are fighting over the write port.\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) \|\|\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1	module ALUExeUnit_1( // @[execution-unit.scala:204:7] input clock, // @[execution-unit.scala:204:7] input reset, // @[execution-unit.scala:204:7] output [9:0] io_fu_types, // @[execution-unit.scala:104:14] input io_req_valid, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14] input [15:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14] input io_req_bits_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_req_bits_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14] input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14] input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14] input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14] input io_req_bits_kill, // @[execution-unit.scala:104:14] output io_iresp_valid, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_iresp_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_iresp_bits_data, // @[execution-unit.scala:104:14] output io_bypass_0_valid, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_bypass_0_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_bypass_0_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_bypass_0_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_bypass_0_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_bypass_0_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_bypass_0_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_bypass_0_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_bypass_0_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_bypass_0_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_bypass_0_bits_data, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14] input io_brupdate_b2_valid, // @[execution-unit.scala:104:14] input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14] input io_brupdate_b2_taken, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14] input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_brinfo_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_brinfo_uop_debug_inst, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_brinfo_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_brinfo_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_brinfo_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_iw_state, // @[execution-unit.scala:104:14] output io_brinfo_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_brinfo_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_br, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_jalr, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_jal, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_brinfo_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_brinfo_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_brinfo_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_pc_lob, // @[execution-unit.scala:104:14] output io_brinfo_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_brinfo_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_brinfo_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ppred, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_brinfo_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_brinfo_uop_exc_cause, // @[execution-unit.scala:104:14] output io_brinfo_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_mem_size, // @[execution-unit.scala:104:14] output io_brinfo_uop_mem_signed, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_fence, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_fencei, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_amo, // @[execution-unit.scala:104:14] output io_brinfo_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_brinfo_uop_uses_stq, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_unique, // @[execution-unit.scala:104:14] output io_brinfo_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_brinfo_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs3, // @[execution-unit.scala:104:14] output io_brinfo_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_brinfo_uop_frs3_en, // @[execution-unit.scala:104:14] output io_brinfo_uop_fp_val, // @[execution-unit.scala:104:14] output io_brinfo_uop_fp_single, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_debug_tsrc, // @[execution-unit.scala:104:14] output io_brinfo_valid, // @[execution-unit.scala:104:14] output io_brinfo_mispredict, // @[execution-unit.scala:104:14] output io_brinfo_taken, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_cfi_type, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_pc_sel, // @[execution-unit.scala:104:14] output [39:0] io_brinfo_jalr_target, // @[execution-unit.scala:104:14] output [20:0] io_brinfo_target_offset, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_idx_valid, // @[execution-unit.scala:104:14] input [2:0] io_get_ftq_pc_entry_cfi_idx_bits, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_taken, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_mispredicted, // @[execution-unit.scala:104:14] input [2:0] io_get_ftq_pc_entry_cfi_type, // @[execution-unit.scala:104:14] input [7:0] io_get_ftq_pc_entry_br_mask, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_is_call, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_is_ret, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_npc_plus4, // @[execution-unit.scala:104:14] input [39:0] io_get_ftq_pc_entry_ras_top, // @[execution-unit.scala:104:14] input [4:0] io_get_ftq_pc_entry_ras_idx, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_start_bank, // @[execution-unit.scala:104:14] input [39:0] io_get_ftq_pc_pc, // @[execution-unit.scala:104:14] input io_get_ftq_pc_next_val, // @[execution-unit.scala:104:14] input [39:0] io_get_ftq_pc_next_pc, // @[execution-unit.scala:104:14] input io_status_debug, // @[execution-unit.scala:104:14] input io_status_cease, // @[execution-unit.scala:104:14] input io_status_wfi, // @[execution-unit.scala:104:14] input [1:0] io_status_dprv, // @[execution-unit.scala:104:14] input io_status_dv, // @[execution-unit.scala:104:14] input [1:0] io_status_prv, // @[execution-unit.scala:104:14] input io_status_v, // @[execution-unit.scala:104:14] input io_status_sd, // @[execution-unit.scala:104:14] input io_status_mpv, // @[execution-unit.scala:104:14] input io_status_gva, // @[execution-unit.scala:104:14] input io_status_tsr, // @[execution-unit.scala:104:14] input io_status_tw, // @[execution-unit.scala:104:14] input io_status_tvm, // @[execution-unit.scala:104:14] input io_status_mxr, // @[execution-unit.scala:104:14] input io_status_sum, // @[execution-unit.scala:104:14] input io_status_mprv, // @[execution-unit.scala:104:14] input [1:0] io_status_fs, // @[execution-unit.scala:104:14] input [1:0] io_status_mpp, // @[execution-unit.scala:104:14] input io_status_spp, // @[execution-unit.scala:104:14] input io_status_mpie, // @[execution-unit.scala:104:14] input io_status_spie, // @[execution-unit.scala:104:14] input io_status_mie, // @[execution-unit.scala:104:14] input io_status_sie // @[execution-unit.scala:104:14] ); wire _DivUnit_io_req_ready; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_valid; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:366:17] wire [31:0] _DivUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:366:17] wire [31:0] _DivUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:366:17] wire [39:0] _DivUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:366:17] wire [9:0] _DivUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:366:17] wire [3:0] _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:366:17] wire [15:0] _DivUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:366:17] wire [3:0] _DivUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:366:17] wire [19:0] _DivUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:366:17] wire [11:0] _DivUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:366:17] wire [63:0] _DivUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:366:17] wire [63:0] _DivUnit_io_resp_bits_data; // @[execution-unit.scala:366:17] wire _ALUUnit_io_resp_valid; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:271:17] wire [31:0] _ALUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:271:17] wire [31:0] _ALUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:271:17] wire [39:0] _ALUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:271:17] wire [9:0] _ALUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:271:17] wire [3:0] _ALUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:271:17] wire [15:0] _ALUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:271:17] wire [3:0] _ALUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:271:17] wire [19:0] _ALUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:271:17] wire [11:0] _ALUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_resp_bits_data; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_bypass_0_bits_data; // @[execution-unit.scala:271:17] wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:204:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:204:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:204:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:204:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:204:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:204:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:204:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:204:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:204:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:204:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:204:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:204:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:204:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:204:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:204:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:204:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:204:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:204:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:204:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:204:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:204:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:204:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:204:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:204:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:204:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:204:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:204:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:204:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:204:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:204:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:204:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:204:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:204:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:204:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:204:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_idx_valid_0 = io_get_ftq_pc_entry_cfi_idx_valid; // @[execution-unit.scala:204:7] wire [2:0] io_get_ftq_pc_entry_cfi_idx_bits_0 = io_get_ftq_pc_entry_cfi_idx_bits; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_taken_0 = io_get_ftq_pc_entry_cfi_taken; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_mispredicted_0 = io_get_ftq_pc_entry_cfi_mispredicted; // @[execution-unit.scala:204:7] wire [2:0] io_get_ftq_pc_entry_cfi_type_0 = io_get_ftq_pc_entry_cfi_type; // @[execution-unit.scala:204:7] wire [7:0] io_get_ftq_pc_entry_br_mask_0 = io_get_ftq_pc_entry_br_mask; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_is_call_0 = io_get_ftq_pc_entry_cfi_is_call; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_is_ret_0 = io_get_ftq_pc_entry_cfi_is_ret; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_npc_plus4_0 = io_get_ftq_pc_entry_cfi_npc_plus4; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_entry_ras_top_0 = io_get_ftq_pc_entry_ras_top; // @[execution-unit.scala:204:7] wire [4:0] io_get_ftq_pc_entry_ras_idx_0 = io_get_ftq_pc_entry_ras_idx; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_start_bank_0 = io_get_ftq_pc_entry_start_bank; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_pc_0 = io_get_ftq_pc_pc; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_next_val_0 = io_get_ftq_pc_next_val; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_next_pc_0 = io_get_ftq_pc_next_pc; // @[execution-unit.scala:204:7] wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:204:7] wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:204:7] wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:204:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:204:7] wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:204:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:204:7] wire io_status_v_0 = io_status_v; // @[execution-unit.scala:204:7] wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:204:7] wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:204:7] wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:204:7] wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:204:7] wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:204:7] wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:204:7] wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:204:7] wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:204:7] wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:204:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:204:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:204:7] wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:204:7] wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:204:7] wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:204:7] wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:204:7] wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:204:7] wire io_req_ready = 1'h0; // @[execution-unit.scala:204:7] wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_status_mbe = 1'h0; // @[execution-unit.scala:204:7] wire io_status_sbe = 1'h0; // @[execution-unit.scala:204:7] wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:204:7] wire io_status_ube = 1'h0; // @[execution-unit.scala:204:7] wire io_status_upie = 1'h0; // @[execution-unit.scala:204:7] wire io_status_hie = 1'h0; // @[execution-unit.scala:204:7] wire io_status_uie = 1'h0; // @[execution-unit.scala:204:7] wire ifpu_busy = 1'h0; // @[execution-unit.scala:254:27] wire _io_fu_types_T_12 = 1'h0; // @[execution-unit.scala:265:33] wire _io_iresp_bits_predicated_T = 1'h0; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_csr_addr_i30_20_T = 1'h0; // @[util.scala:274:27] wire _io_iresp_bits_uop_csr_addr_i19_12_T = 1'h0; // @[util.scala:275:27] wire _io_iresp_bits_uop_csr_addr_i19_12_T_1 = 1'h0; // @[util.scala:275:44] wire _io_iresp_bits_uop_csr_addr_i19_12_T_2 = 1'h0; // @[util.scala:275:36] wire _io_iresp_bits_uop_csr_addr_i11_T = 1'h0; // @[util.scala:276:27] wire _io_iresp_bits_uop_csr_addr_i11_T_1 = 1'h0; // @[util.scala:277:27] wire _io_iresp_bits_uop_csr_addr_i11_T_2 = 1'h0; // @[util.scala:277:44] wire _io_iresp_bits_uop_csr_addr_i11_T_3 = 1'h0; // @[util.scala:277:36] wire _io_iresp_bits_uop_csr_addr_i10_5_T = 1'h0; // @[util.scala:278:27] wire _io_iresp_bits_uop_csr_addr_i4_1_T = 1'h0; // @[util.scala:279:27] wire _io_iresp_bits_uop_csr_addr_i0_T = 1'h0; // @[util.scala:280:27] wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:204:7] wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:204:7] wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[execution-unit.scala:204:7] wire io_iresp_ready = 1'h1; // @[execution-unit.scala:204:7] wire _io_fu_types_T_11 = 1'h1; // @[execution-unit.scala:265:22] wire _io_iresp_bits_uop_csr_addr_i0_T_1 = 1'h1; // @[util.scala:280:44] wire _io_iresp_bits_uop_csr_addr_i0_T_2 = 1'h1; // @[util.scala:280:36] wire [6:0] io_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [39:0] io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_com_pc = 40'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [9:0] io_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] _io_fu_types_T_1 = 10'h0; // @[execution-unit.scala:261:21] wire [9:0] _io_fu_types_T_7 = 10'h0; // @[execution-unit.scala:263:21] wire [9:0] _io_fu_types_T_13 = 10'h0; // @[execution-unit.scala:265:21] wire [9:0] _io_fu_types_T_15 = 10'h0; // @[execution-unit.scala:266:21] wire [3:0] io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_get_ftq_pc_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_get_ftq_pc_ghist_ras_idx = 5'h0; // @[execution-unit.scala:204:7] wire [15:0] io_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [19:0] io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [11:0] io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [63:0] io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [63:0] io_get_ftq_pc_ghist_old_history = 64'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:204:7] wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:204:7] wire [9:0] _io_fu_types_T_9 = 10'h2; // @[execution-unit.scala:264:21] wire [9:0] _io_fu_types_T = 10'h1; // @[execution-unit.scala:260:21] wire [9:0] _io_fu_types_T_2 = 10'h1; // @[execution-unit.scala:260:45] wire [9:0] _io_fu_types_T_16; // @[execution-unit.scala:265:60] wire _io_iresp_valid_T; // @[execution-unit.scala:409:71] wire [6:0] _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70] wire [31:0] _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70] wire [31:0] _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] wire [39:0] _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] wire [9:0] _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] wire [3:0] _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] wire [15:0] _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] wire [3:0] _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70] wire [19:0] _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70] wire [63:0] _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [3:0] io_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_iresp_bits_data_0; // @[execution-unit.scala:204:7] wire io_iresp_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_0_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_0_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_0_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_0_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_0_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_0_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_bypass_0_bits_data_0; // @[execution-unit.scala:204:7] wire io_bypass_0_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_brinfo_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_brinfo_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_brinfo_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_brinfo_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_brinfo_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_brinfo_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_brinfo_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_brinfo_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_brinfo_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire io_brinfo_valid_0; // @[execution-unit.scala:204:7] wire io_brinfo_mispredict_0; // @[execution-unit.scala:204:7] wire io_brinfo_taken_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_cfi_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_pc_sel_0; // @[execution-unit.scala:204:7] wire [39:0] io_brinfo_jalr_target_0; // @[execution-unit.scala:204:7] wire [20:0] io_brinfo_target_offset_0; // @[execution-unit.scala:204:7] wire [9:0] io_fu_types_0; // @[execution-unit.scala:204:7] wire _div_busy_T_4; // @[execution-unit.scala:379:39] wire div_busy; // @[execution-unit.scala:253:27] wire _io_fu_types_T_3 = ~div_busy; // @[execution-unit.scala:253:27, :262:22] wire _io_fu_types_T_4 = _io_fu_types_T_3; // @[execution-unit.scala:262:{22,32}] wire [9:0] _io_fu_types_T_5 = {5'h0, _io_fu_types_T_4, 4'h0}; // @[execution-unit.scala:262:{21,32}] wire [9:0] _io_fu_types_T_6 = _io_fu_types_T_5 \| 10'h1; // @[execution-unit.scala:261:45, :262:21] wire [9:0] _io_fu_types_T_8 = _io_fu_types_T_6; // @[execution-unit.scala:261:45, :262:58] wire [9:0] _io_fu_types_T_10 = _io_fu_types_T_8 \| 10'h2; // @[execution-unit.scala:262:58, :263:45] wire [9:0] _io_fu_types_T_14 = _io_fu_types_T_10; // @[execution-unit.scala:263:45, :264:49] assign _io_fu_types_T_16 = _io_fu_types_T_14; // @[execution-unit.scala:264:49, :265:60] assign io_fu_types_0 = _io_fu_types_T_16; // @[execution-unit.scala:204:7, :265:60] assign io_bypass_0_bits_data_0 = {1'h0, _ALUUnit_io_bypass_0_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15] wire div_resp_val; // @[execution-unit.scala:364:30] wire [9:0] _div_busy_T_1 = io_req_bits_uop_fu_code_0 & 10'h10; // @[execution-unit.scala:204:7] wire _div_busy_T = ~_DivUnit_io_req_ready; // @[execution-unit.scala:366:17, :379:21] wire _div_busy_T_2 = \|_div_busy_T_1; // @[micro-op.scala:154:{40,47}] wire _div_busy_T_3 = io_req_valid_0 & _div_busy_T_2; // @[execution-unit.scala:204:7, :380:35] assign _div_busy_T_4 = _div_busy_T \| _div_busy_T_3; // @[execution-unit.scala:379:{21,39}, :380:35] assign div_busy = _div_busy_T_4; // @[execution-unit.scala:253:27, :379:39] assign _io_iresp_valid_T = _ALUUnit_io_resp_valid \| _DivUnit_io_resp_valid; // @[execution-unit.scala:271:17, :366:17, :409:71] assign io_iresp_valid_0 = _io_iresp_valid_T; // @[execution-unit.scala:204:7, :409:71] assign _io_iresp_bits_uop_T_uopc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uopc : _DivUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_inst : _DivUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_inst : _DivUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_rvc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_rvc : _DivUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_pc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_pc : _DivUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iq_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iq_type : _DivUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fu_code = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fu_code : _DivUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_br_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_br_type : _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op1_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op1_sel : _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op2_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op2_sel : _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_imm_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_imm_sel : _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op_fcn = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op_fcn : _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_fcn_dw = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw : _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_csr_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd : _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_load = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_load : _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_sta = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_sta : _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_std = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_std : _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_state = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_state : _DivUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_p1_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p1_poisoned : _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_p2_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p2_poisoned : _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_br = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_br : _DivUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_jalr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jalr : _DivUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_jal = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jal : _DivUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_sfb = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sfb : _DivUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_br_mask = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_mask : _DivUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_br_tag = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_tag : _DivUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ftq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ftq_idx : _DivUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_edge_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_edge_inst : _DivUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_pc_lob = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pc_lob : _DivUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_taken = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_taken : _DivUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_imm_packed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_imm_packed : _DivUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70] wire [11:0] _io_iresp_bits_uop_T_csr_addr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_csr_addr : _DivUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_rob_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rob_idx : _DivUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldq_idx : _DivUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_stq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stq_idx : _DivUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_rxq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rxq_idx : _DivUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pdst : _DivUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1 : _DivUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2 : _DivUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3 : _DivUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ppred = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred : _DivUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs1_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1_busy : _DivUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs2_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2_busy : _DivUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs3_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3_busy : _DivUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ppred_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred_busy : _DivUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_stale_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stale_pdst : _DivUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_exception = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exception : _DivUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_exc_cause = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exc_cause : _DivUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bypassable = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bypassable : _DivUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_cmd : _DivUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_size = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_size : _DivUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_signed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_signed : _DivUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_fence = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fence : _DivUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_fencei = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fencei : _DivUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_amo = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_amo : _DivUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_uses_ldq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_ldq : _DivUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_uses_stq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_stq : _DivUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_sys_pc2epc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sys_pc2epc : _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_unique = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_unique : _DivUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_flush_on_commit = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_flush_on_commit : _DivUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst_is_rs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_is_rs1 : _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst : _DivUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1 : _DivUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2 : _DivUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs3 : _DivUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_val : _DivUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_dst_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_dst_rtype : _DivUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs1_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1_rtype : _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs2_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2_rtype : _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_frs3_en = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_frs3_en : _DivUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fp_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_val : _DivUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fp_single = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_single : _DivUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_pf_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_pf_if : _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_ae_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ae_if : _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_ma_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ma_if : _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bp_debug_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_debug_if : _DivUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bp_xcpt_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_xcpt_if : _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_fsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_fsrc : _DivUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_tsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_tsrc : _DivUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uopc_0 = _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_inst_0 = _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_inst_0 = _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_rvc_0 = _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_pc_0 = _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iq_type_0 = _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fu_code_0 = _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_br_type_0 = _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op1_sel_0 = _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op2_sel_0 = _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_imm_sel_0 = _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op_fcn_0 = _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_fcn_dw_0 = _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_load_0 = _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_sta_0 = _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_std_0 = _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_state_0 = _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_p1_poisoned_0 = _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_p2_poisoned_0 = _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_br_0 = _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_jalr_0 = _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_jal_0 = _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_sfb_0 = _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] assign io_iresp_bits_uop_br_mask_0 = _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] assign io_iresp_bits_uop_br_tag_0 = _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ftq_idx_0 = _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_edge_inst_0 = _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_pc_lob_0 = _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] assign io_iresp_bits_uop_taken_0 = _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70] assign io_iresp_bits_uop_imm_packed_0 = _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] assign io_iresp_bits_uop_rob_idx_0 = _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldq_idx_0 = _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_stq_idx_0 = _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_rxq_idx_0 = _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_pdst_0 = _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs1_0 = _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs2_0 = _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs3_0 = _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ppred_0 = _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs1_busy_0 = _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs2_busy_0 = _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs3_busy_0 = _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ppred_busy_0 = _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_stale_pdst_0 = _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_exception_0 = _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70] assign io_iresp_bits_uop_exc_cause_0 = _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bypassable_0 = _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_cmd_0 = _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_size_0 = _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_signed_0 = _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_fence_0 = _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_fencei_0 = _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_amo_0 = _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uses_ldq_0 = _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uses_stq_0 = _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_sys_pc2epc_0 = _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_unique_0 = _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] assign io_iresp_bits_uop_flush_on_commit_0 = _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_is_rs1_0 = _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_0 = _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs1_0 = _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs2_0 = _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs3_0 = _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_val_0 = _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] assign io_iresp_bits_uop_dst_rtype_0 = _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs1_rtype_0 = _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs2_rtype_0 = _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_frs3_en_0 = _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fp_val_0 = _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fp_single_0 = _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_pf_if_0 = _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_ae_if_0 = _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_ma_if_0 = _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bp_debug_if_0 = _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bp_xcpt_if_0 = _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_fsrc_0 = _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_tsrc_0 = _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [63:0] _io_iresp_bits_data_T = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_data : _DivUnit_io_resp_bits_data; // @[Mux.scala:50:70] assign io_iresp_bits_data_0 = {1'h0, _io_iresp_bits_data_T}; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_csr_addr_sign_T = _ALUUnit_io_resp_bits_uop_imm_packed[19]; // @[util.scala:273:18] wire io_iresp_bits_uop_csr_addr_sign = _io_iresp_bits_uop_csr_addr_sign_T; // @[util.scala:273:{18,37}] wire _io_iresp_bits_uop_csr_addr_i11_T_6 = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :277:21] wire io_iresp_bits_uop_csr_addr_hi_hi_hi = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :282:15] wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:8]; // @[util.scala:274:39] wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_2 = _io_iresp_bits_uop_csr_addr_i30_20_T_1; // @[util.scala:274:{39,46}] wire [10:0] io_iresp_bits_uop_csr_addr_i30_20 = {11{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :274:21] wire [10:0] io_iresp_bits_uop_csr_addr_hi_hi_lo = io_iresp_bits_uop_csr_addr_i30_20; // @[util.scala:274:21, :282:15] wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[7:0]; // @[util.scala:275:56] wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_4 = _io_iresp_bits_uop_csr_addr_i19_12_T_3; // @[util.scala:275:{56,62}] wire [7:0] io_iresp_bits_uop_csr_addr_i19_12 = {8{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :275:21] wire [7:0] io_iresp_bits_uop_csr_addr_hi_lo_hi = io_iresp_bits_uop_csr_addr_i19_12; // @[util.scala:275:21, :282:15] wire _io_iresp_bits_uop_csr_addr_i11_T_4 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56] wire _io_iresp_bits_uop_csr_addr_i0_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56, :280:56] wire _io_iresp_bits_uop_csr_addr_i11_T_5 = _io_iresp_bits_uop_csr_addr_i11_T_4; // @[util.scala:277:{56,60}] wire io_iresp_bits_uop_csr_addr_i11 = _io_iresp_bits_uop_csr_addr_i11_T_6; // @[util.scala:276:21, :277:21] wire io_iresp_bits_uop_csr_addr_hi_lo_lo = io_iresp_bits_uop_csr_addr_i11; // @[util.scala:276:21, :282:15] wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:14]; // @[util.scala:278:44] wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_2 = _io_iresp_bits_uop_csr_addr_i10_5_T_1; // @[util.scala:278:{44,52}] wire [4:0] io_iresp_bits_uop_csr_addr_i10_5 = _io_iresp_bits_uop_csr_addr_i10_5_T_2; // @[util.scala:278:{21,52}] wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_hi = io_iresp_bits_uop_csr_addr_i10_5; // @[util.scala:278:21, :282:15] wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[13:9]; // @[util.scala:279:44] wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_2 = _io_iresp_bits_uop_csr_addr_i4_1_T_1; // @[util.scala:279:{44,51}] wire [4:0] io_iresp_bits_uop_csr_addr_i4_1 = _io_iresp_bits_uop_csr_addr_i4_1_T_2; // @[util.scala:279:{21,51}] wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_lo = io_iresp_bits_uop_csr_addr_i4_1; // @[util.scala:279:21, :282:15] wire _io_iresp_bits_uop_csr_addr_i0_T_4 = _io_iresp_bits_uop_csr_addr_i0_T_3; // @[util.scala:280:{56,60}] wire io_iresp_bits_uop_csr_addr_i0 = _io_iresp_bits_uop_csr_addr_i0_T_4; // @[util.scala:280:{21,60}] wire io_iresp_bits_uop_csr_addr_lo_lo = io_iresp_bits_uop_csr_addr_i0; // @[util.scala:280:21, :282:15] wire [9:0] io_iresp_bits_uop_csr_addr_lo_hi = {io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo}; // @[util.scala:282:15] wire [10:0] io_iresp_bits_uop_csr_addr_lo = {io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo}; // @[util.scala:282:15] wire [8:0] io_iresp_bits_uop_csr_addr_hi_lo = {io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo}; // @[util.scala:282:15] wire [11:0] io_iresp_bits_uop_csr_addr_hi_hi = {io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo}; // @[util.scala:282:15] wire [20:0] io_iresp_bits_uop_csr_addr_hi = {io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo}; // @[util.scala:282:15] wire [31:0] _io_iresp_bits_uop_csr_addr_T = {io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo}; // @[util.scala:282:15] wire [31:0] _io_iresp_bits_uop_csr_addr_T_1 = _io_iresp_bits_uop_csr_addr_T; // @[util.scala:282:{15,60}] wire [31:0] _io_iresp_bits_uop_csr_addr_T_2 = _io_iresp_bits_uop_csr_addr_T_1; // @[util.scala:282:60] assign io_iresp_bits_uop_csr_addr_0 = _io_iresp_bits_uop_csr_addr_T_2[11:0]; // @[execution-unit.scala:204:7, :420:{34,83}]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_51 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_51( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_55 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_55( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<13>(0h1000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_27, _T_32) node _T_69 = or(_T_68, _T_37) node _T_70 = or(_T_69, _T_42) node _T_71 = or(_T_70, _T_47) node _T_72 = or(_T_71, _T_52) node _T_73 = or(_T_72, _T_57) node _T_74 = or(_T_73, _T_62) node _T_75 = or(_T_74, _T_67) node _T_76 = and(_T_22, _T_75) node _T_77 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_78 = or(UInt<1>(0h0), _T_77) node _T_79 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<17>(0h10000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<29>(0h10000000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = and(_T_78, _T_89) node _T_91 = or(UInt<1>(0h0), _T_76) node _T_92 = or(_T_91, _T_90) node _T_93 = and(_T_21, _T_92) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_93, UInt<1>(0h1), "") : assert_2 node _T_97 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_98 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(UInt<1>(0h0), _T_99) node _T_101 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<14>(0h2000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<13>(0h1000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<18>(0h2f000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<17>(0h10000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<17>(0h10000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_105, _T_110) node _T_157 = or(_T_156, _T_115) node _T_158 = or(_T_157, _T_120) node _T_159 = or(_T_158, _T_125) node _T_160 = or(_T_159, _T_130) node _T_161 = or(_T_160, _T_135) node _T_162 = or(_T_161, _T_140) node _T_163 = or(_T_162, _T_145) node _T_164 = or(_T_163, _T_150) node _T_165 = or(_T_164, _T_155) node _T_166 = and(_T_100, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(UInt<1>(0h0), _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_168, UInt<1>(0h1), "") : assert_3 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_175 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_175, UInt<1>(0h1), "") : assert_5 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(is_aligned, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_182 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_183 = asUInt(reset) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : node _T_185 = eq(_T_182, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_182, UInt<1>(0h1), "") : assert_7 node _T_186 = not(io.in.a.bits.mask) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_187, UInt<1>(0h1), "") : assert_8 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_191, UInt<1>(0h1), "") : assert_9 node _T_195 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<14>(0h2000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<18>(0h2f000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<17>(0h10000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_234 = cvt(_T_233) node _T_235 = and(_T_234, asSInt(UInt<27>(0h4000000))) node _T_236 = asSInt(_T_235) node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0))) node _T_238 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_239 = cvt(_T_238) node _T_240 = and(_T_239, asSInt(UInt<13>(0h1000))) node _T_241 = asSInt(_T_240) node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = or(_T_207, _T_212) node _T_249 = or(_T_248, _T_217) node _T_250 = or(_T_249, _T_222) node _T_251 = or(_T_250, _T_227) node _T_252 = or(_T_251, _T_232) node _T_253 = or(_T_252, _T_237) node _T_254 = or(_T_253, _T_242) node _T_255 = or(_T_254, _T_247) node _T_256 = and(_T_202, _T_255) node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<29>(0h10000000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = or(_T_263, _T_268) node _T_270 = and(_T_258, _T_269) node _T_271 = or(UInt<1>(0h0), _T_256) node _T_272 = or(_T_271, _T_270) node _T_273 = and(_T_201, _T_272) node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_T_273, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_273, UInt<1>(0h1), "") : assert_10 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<18>(0h2f000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<29>(0h10000000))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = or(_T_285, _T_290) node _T_337 = or(_T_336, _T_295) node _T_338 = or(_T_337, _T_300) node _T_339 = or(_T_338, _T_305) node _T_340 = or(_T_339, _T_310) node _T_341 = or(_T_340, _T_315) node _T_342 = or(_T_341, _T_320) node _T_343 = or(_T_342, _T_325) node _T_344 = or(_T_343, _T_330) node _T_345 = or(_T_344, _T_335) node _T_346 = and(_T_280, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_348, UInt<1>(0h1), "") : assert_11 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_355 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_355, UInt<1>(0h1), "") : assert_13 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_362, UInt<1>(0h1), "") : assert_15 node _T_366 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_366, UInt<1>(0h1), "") : assert_16 node _T_370 = not(io.in.a.bits.mask) node _T_371 = eq(_T_370, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_371, UInt<1>(0h1), "") : assert_17 node _T_375 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_375, UInt<1>(0h1), "") : assert_18 node _T_379 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_379 : node _T_380 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_381 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = or(UInt<1>(0h0), _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_385, UInt<1>(0h1), "") : assert_19 node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_391 = and(_T_389, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_394 = cvt(_T_393) node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000))) node _T_396 = asSInt(_T_395) node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0))) node _T_398 = and(_T_392, _T_397) node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_400 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_401 = and(_T_399, _T_400) node _T_402 = or(UInt<1>(0h0), _T_401) node _T_403 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_404 = cvt(_T_403) node _T_405 = and(_T_404, asSInt(UInt<14>(0h2000))) node _T_406 = asSInt(_T_405) node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0))) node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_409 = cvt(_T_408) node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000))) node _T_411 = asSInt(_T_410) node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0))) node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_414 = cvt(_T_413) node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000))) node _T_416 = asSInt(_T_415) node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0))) node _T_418 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_419 = cvt(_T_418) node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000))) node _T_421 = asSInt(_T_420) node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0))) node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_424 = cvt(_T_423) node _T_425 = and(_T_424, asSInt(UInt<13>(0h1000))) node _T_426 = asSInt(_T_425) node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0))) node _T_428 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_429 = cvt(_T_428) node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000))) node _T_431 = asSInt(_T_430) node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0))) node _T_433 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_434 = cvt(_T_433) node _T_435 = and(_T_434, asSInt(UInt<27>(0h4000000))) node _T_436 = asSInt(_T_435) node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0))) node _T_438 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_439 = cvt(_T_438) node _T_440 = and(_T_439, asSInt(UInt<13>(0h1000))) node _T_441 = asSInt(_T_440) node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0))) node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_444 = cvt(_T_443) node _T_445 = and(_T_444, asSInt(UInt<13>(0h1000))) node _T_446 = asSInt(_T_445) node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0))) node _T_448 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<29>(0h10000000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = or(_T_407, _T_412) node _T_454 = or(_T_453, _T_417) node _T_455 = or(_T_454, _T_422) node _T_456 = or(_T_455, _T_427) node _T_457 = or(_T_456, _T_432) node _T_458 = or(_T_457, _T_437) node _T_459 = or(_T_458, _T_442) node _T_460 = or(_T_459, _T_447) node _T_461 = or(_T_460, _T_452) node _T_462 = and(_T_402, _T_461) node _T_463 = or(UInt<1>(0h0), _T_398) node _T_464 = or(_T_463, _T_462) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_464, UInt<1>(0h1), "") : assert_20 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(is_aligned, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_474 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_474, UInt<1>(0h1), "") : assert_23 node _T_478 = eq(io.in.a.bits.mask, mask) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_478, UInt<1>(0h1), "") : assert_24 node _T_482 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_482, UInt<1>(0h1), "") : assert_25 node _T_486 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_486 : node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_488 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_489 = and(_T_487, _T_488) node _T_490 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(UInt<1>(0h0), _T_495) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = and(_T_496, _T_501) node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_505 = and(_T_503, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<14>(0h2000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<18>(0h2f000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<17>(0h10000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<13>(0h1000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<27>(0h4000000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<13>(0h1000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<13>(0h1000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<29>(0h10000000))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = or(_T_511, _T_516) node _T_553 = or(_T_552, _T_521) node _T_554 = or(_T_553, _T_526) node _T_555 = or(_T_554, _T_531) node _T_556 = or(_T_555, _T_536) node _T_557 = or(_T_556, _T_541) node _T_558 = or(_T_557, _T_546) node _T_559 = or(_T_558, _T_551) node _T_560 = and(_T_506, _T_559) node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_562 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<17>(0h10000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = and(_T_561, _T_566) node _T_568 = or(UInt<1>(0h0), _T_502) node _T_569 = or(_T_568, _T_560) node _T_570 = or(_T_569, _T_567) node _T_571 = and(_T_492, _T_570) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_571, UInt<1>(0h1), "") : assert_26 node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(is_aligned, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_581 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_581, UInt<1>(0h1), "") : assert_29 node _T_585 = eq(io.in.a.bits.mask, mask) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_585, UInt<1>(0h1), "") : assert_30 node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_589 : node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) node _T_595 = or(UInt<1>(0h0), _T_594) node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_598 = and(_T_596, _T_597) node _T_599 = or(UInt<1>(0h0), _T_598) node _T_600 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_601 = cvt(_T_600) node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000))) node _T_603 = asSInt(_T_602) node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0))) node _T_605 = and(_T_599, _T_604) node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<14>(0h2000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<18>(0h2f000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<13>(0h1000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<17>(0h10000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<27>(0h4000000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<13>(0h1000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<29>(0h10000000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = or(_T_614, _T_619) node _T_656 = or(_T_655, _T_624) node _T_657 = or(_T_656, _T_629) node _T_658 = or(_T_657, _T_634) node _T_659 = or(_T_658, _T_639) node _T_660 = or(_T_659, _T_644) node _T_661 = or(_T_660, _T_649) node _T_662 = or(_T_661, _T_654) node _T_663 = and(_T_609, _T_662) node _T_664 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_665 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_605) node _T_672 = or(_T_671, _T_663) node _T_673 = or(_T_672, _T_670) node _T_674 = and(_T_595, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_674, UInt<1>(0h1), "") : assert_31 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_684, UInt<1>(0h1), "") : assert_34 node _T_688 = not(mask) node _T_689 = and(io.in.a.bits.mask, _T_688) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_690, UInt<1>(0h1), "") : assert_35 node _T_694 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_699 = and(_T_697, _T_698) node _T_700 = or(UInt<1>(0h0), _T_699) node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<14>(0h2000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<18>(0h2f000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<17>(0h10000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<13>(0h1000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<27>(0h4000000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<13>(0h1000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<13>(0h1000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = or(_T_709, _T_714) node _T_746 = or(_T_745, _T_719) node _T_747 = or(_T_746, _T_724) node _T_748 = or(_T_747, _T_729) node _T_749 = or(_T_748, _T_734) node _T_750 = or(_T_749, _T_739) node _T_751 = or(_T_750, _T_744) node _T_752 = and(_T_704, _T_751) node _T_753 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_754 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<17>(0h10000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = and(_T_753, _T_758) node _T_760 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_761 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_762 = and(_T_760, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<17>(0h10000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<29>(0h10000000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = or(_T_768, _T_773) node _T_775 = and(_T_763, _T_774) node _T_776 = or(UInt<1>(0h0), _T_752) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_775) node _T_779 = and(_T_700, _T_778) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_779, UInt<1>(0h1), "") : assert_36 node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(is_aligned, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_789 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_789, UInt<1>(0h1), "") : assert_39 node _T_793 = eq(io.in.a.bits.mask, mask) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_793, UInt<1>(0h1), "") : assert_40 node _T_797 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_797 : node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_800 = and(_T_798, _T_799) node _T_801 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_805 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_806 = and(_T_804, _T_805) node _T_807 = or(UInt<1>(0h0), _T_806) node _T_808 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<14>(0h2000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<13>(0h1000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<18>(0h2f000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<13>(0h1000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_834 = cvt(_T_833) node _T_835 = and(_T_834, asSInt(UInt<27>(0h4000000))) node _T_836 = asSInt(_T_835) node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) node _T_838 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<13>(0h1000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = or(_T_812, _T_817) node _T_849 = or(_T_848, _T_822) node _T_850 = or(_T_849, _T_827) node _T_851 = or(_T_850, _T_832) node _T_852 = or(_T_851, _T_837) node _T_853 = or(_T_852, _T_842) node _T_854 = or(_T_853, _T_847) node _T_855 = and(_T_807, _T_854) node _T_856 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_857 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<17>(0h10000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_864 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_865 = and(_T_863, _T_864) node _T_866 = or(UInt<1>(0h0), _T_865) node _T_867 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_873 = cvt(_T_872) node _T_874 = and(_T_873, asSInt(UInt<29>(0h10000000))) node _T_875 = asSInt(_T_874) node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0))) node _T_877 = or(_T_871, _T_876) node _T_878 = and(_T_866, _T_877) node _T_879 = or(UInt<1>(0h0), _T_855) node _T_880 = or(_T_879, _T_862) node _T_881 = or(_T_880, _T_878) node _T_882 = and(_T_803, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = and(_T_903, _T_904) node _T_906 = or(UInt<1>(0h0), _T_905) node _T_907 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_908 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_909 = and(_T_907, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = and(_T_910, _T_915) node _T_917 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<14>(0h2000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<17>(0h10000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<18>(0h2f000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<17>(0h10000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_939 = cvt(_T_938) node _T_940 = and(_T_939, asSInt(UInt<13>(0h1000))) node _T_941 = asSInt(_T_940) node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0))) node _T_943 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_944 = cvt(_T_943) node _T_945 = and(_T_944, asSInt(UInt<27>(0h4000000))) node _T_946 = asSInt(_T_945) node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0))) node _T_948 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_949 = cvt(_T_948) node _T_950 = and(_T_949, asSInt(UInt<13>(0h1000))) node _T_951 = asSInt(_T_950) node _T_952 = eq(_T_951, asSInt(UInt<1>(0h0))) node _T_953 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_954 = cvt(_T_953) node _T_955 = and(_T_954, asSInt(UInt<13>(0h1000))) node _T_956 = asSInt(_T_955) node _T_957 = eq(_T_956, asSInt(UInt<1>(0h0))) node _T_958 = or(_T_922, _T_927) node _T_959 = or(_T_958, _T_932) node _T_960 = or(_T_959, _T_937) node _T_961 = or(_T_960, _T_942) node _T_962 = or(_T_961, _T_947) node _T_963 = or(_T_962, _T_952) node _T_964 = or(_T_963, _T_957) node _T_965 = and(_T_917, _T_964) node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_967 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_968 = and(_T_966, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_971 = cvt(_T_970) node _T_972 = and(_T_971, asSInt(UInt<17>(0h10000))) node _T_973 = asSInt(_T_972) node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0))) node _T_975 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_976 = cvt(_T_975) node _T_977 = and(_T_976, asSInt(UInt<29>(0h10000000))) node _T_978 = asSInt(_T_977) node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0))) node _T_980 = or(_T_974, _T_979) node _T_981 = and(_T_969, _T_980) node _T_982 = or(UInt<1>(0h0), _T_916) node _T_983 = or(_T_982, _T_965) node _T_984 = or(_T_983, _T_981) node _T_985 = and(_T_906, _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_985, UInt<1>(0h1), "") : assert_46 node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(is_aligned, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_995 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_995, UInt<1>(0h1), "") : assert_49 node _T_999 = eq(io.in.a.bits.mask, mask) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_999, UInt<1>(0h1), "") : assert_50 node _T_1003 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1007 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1011 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1011 : node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1015 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_54 node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_55 node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_56 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_57 node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1031 : node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(sink_ok, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1038 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_60 node _T_1042 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(_T_1042, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1042, UInt<1>(0h1), "") : assert_61 node _T_1046 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_62 node _T_1050 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_63 node _T_1054 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1055 = or(UInt<1>(0h1), _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_64 node _T_1059 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1059 : node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(sink_ok, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1066 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_67 node _T_1070 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_68 node _T_1074 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_69 node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1079 = or(_T_1078, io.in.d.bits.corrupt) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_70 node _T_1083 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1084 = or(UInt<1>(0h1), _T_1083) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_71 node _T_1088 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1088 : node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1092 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_73 node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_74 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(UInt<1>(0h1), _T_1100) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_75 node _T_1105 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1105 : node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1109 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_77 node _T_1113 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1114 = or(_T_1113, io.in.d.bits.corrupt) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_78 node _T_1118 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1119 = or(UInt<1>(0h1), _T_1118) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_79 node _T_1123 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1123 : node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1127 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_81 node _T_1131 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_82 node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1136 = or(UInt<1>(0h1), _T_1135) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1140 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1144 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1148 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1152 = eq(a_first, UInt<1>(0h0)) node _T_1153 = and(io.in.a.valid, _T_1152) when _T_1153 : node _T_1154 = eq(io.in.a.bits.opcode, opcode) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_87 node _T_1158 = eq(io.in.a.bits.param, param) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_88 node _T_1162 = eq(io.in.a.bits.size, size) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_89 node _T_1166 = eq(io.in.a.bits.source, source) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_90 node _T_1170 = eq(io.in.a.bits.address, address) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_91 node _T_1174 = and(io.in.a.ready, io.in.a.valid) node _T_1175 = and(_T_1174, a_first) when _T_1175 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1176 = eq(d_first, UInt<1>(0h0)) node _T_1177 = and(io.in.d.valid, _T_1176) when _T_1177 : node _T_1178 = eq(io.in.d.bits.opcode, opcode_1) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_92 node _T_1182 = eq(io.in.d.bits.param, param_1) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_93 node _T_1186 = eq(io.in.d.bits.size, size_1) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_94 node _T_1190 = eq(io.in.d.bits.source, source_1) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_95 node _T_1194 = eq(io.in.d.bits.sink, sink) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_96 node _T_1198 = eq(io.in.d.bits.denied, denied) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_97 node _T_1202 = and(io.in.d.ready, io.in.d.valid) node _T_1203 = and(_T_1202, d_first) when _T_1203 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1204 = and(io.in.a.valid, a_first_1) node _T_1205 = and(_T_1204, UInt<1>(0h1)) when _T_1205 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1206 = and(io.in.a.ready, io.in.a.valid) node _T_1207 = and(_T_1206, a_first_1) node _T_1208 = and(_T_1207, UInt<1>(0h1)) when _T_1208 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1209 = dshr(inflight, io.in.a.bits.source) node _T_1210 = bits(_T_1209, 0, 0) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1215 = and(io.in.d.valid, d_first_1) node _T_1216 = and(_T_1215, UInt<1>(0h1)) node _T_1217 = eq(d_release_ack, UInt<1>(0h0)) node _T_1218 = and(_T_1216, _T_1217) when _T_1218 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1219 = and(io.in.d.ready, io.in.d.valid) node _T_1220 = and(_T_1219, d_first_1) node _T_1221 = and(_T_1220, UInt<1>(0h1)) node _T_1222 = eq(d_release_ack, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1224 = and(io.in.d.valid, d_first_1) node _T_1225 = and(_T_1224, UInt<1>(0h1)) node _T_1226 = eq(d_release_ack, UInt<1>(0h0)) node _T_1227 = and(_T_1225, _T_1226) when _T_1227 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1228 = dshr(inflight, io.in.d.bits.source) node _T_1229 = bits(_T_1228, 0, 0) node _T_1230 = or(_T_1229, same_cycle_resp) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1234 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1236 = or(_T_1234, _T_1235) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_100 node _T_1240 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_101 else : node _T_1244 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1245 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1246 = or(_T_1244, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_102 node _T_1250 = eq(io.in.d.bits.size, a_size_lookup) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_103 node _T_1254 = and(io.in.d.valid, d_first_1) node _T_1255 = and(_T_1254, a_first_1) node _T_1256 = and(_T_1255, io.in.a.valid) node _T_1257 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1258 = and(_T_1256, _T_1257) node _T_1259 = eq(d_release_ack, UInt<1>(0h0)) node _T_1260 = and(_T_1258, _T_1259) when _T_1260 : node _T_1261 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1262 = or(_T_1261, io.in.a.ready) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_104 node _T_1266 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1267 = orr(a_set_wo_ready) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) node _T_1269 = or(_T_1266, _T_1268) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_88 node _T_1273 = orr(inflight) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) node _T_1275 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1276 = or(_T_1274, _T_1275) node _T_1277 = lt(watchdog, plusarg_reader.out) node _T_1278 = or(_T_1276, _T_1277) node _T_1279 = asUInt(reset) node _T_1280 = eq(_T_1279, UInt<1>(0h0)) when _T_1280 : node _T_1281 = eq(_T_1278, UInt<1>(0h0)) when _T_1281 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1278, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1282 = and(io.in.a.ready, io.in.a.valid) node _T_1283 = and(io.in.d.ready, io.in.d.valid) node _T_1284 = or(_T_1282, _T_1283) when _T_1284 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1285 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1286 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1287 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1288 = and(_T_1286, _T_1287) node _T_1289 = and(_T_1285, _T_1288) when _T_1289 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1290 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1291 = and(_T_1290, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1292 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1293 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1294 = and(_T_1292, _T_1293) node _T_1295 = and(_T_1291, _T_1294) when _T_1295 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1296 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1297 = bits(_T_1296, 0, 0) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1302 = and(io.in.d.valid, d_first_2) node _T_1303 = and(_T_1302, UInt<1>(0h1)) node _T_1304 = and(_T_1303, d_release_ack_1) when _T_1304 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1305 = and(io.in.d.ready, io.in.d.valid) node _T_1306 = and(_T_1305, d_first_2) node _T_1307 = and(_T_1306, UInt<1>(0h1)) node _T_1308 = and(_T_1307, d_release_ack_1) when _T_1308 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1309 = and(io.in.d.valid, d_first_2) node _T_1310 = and(_T_1309, UInt<1>(0h1)) node _T_1311 = and(_T_1310, d_release_ack_1) when _T_1311 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1312 = dshr(inflight_1, io.in.d.bits.source) node _T_1313 = bits(_T_1312, 0, 0) node _T_1314 = or(_T_1313, same_cycle_resp_1) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1318 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_109 else : node _T_1322 = eq(io.in.d.bits.size, c_size_lookup) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_110 node _T_1326 = and(io.in.d.valid, d_first_2) node _T_1327 = and(_T_1326, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1328 = and(_T_1327, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1329 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = and(_T_1330, d_release_ack_1) node _T_1332 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1333 = and(_T_1331, _T_1332) when _T_1333 : node _T_1334 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1335 = or(_T_1334, _WIRE_23.ready) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_111 node _T_1339 = orr(c_set_wo_ready) when _T_1339 : node _T_1340 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_89 node _T_1344 = orr(inflight_1) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) node _T_1346 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1347 = or(_T_1345, _T_1346) node _T_1348 = lt(watchdog_1, plusarg_reader_1.out) node _T_1349 = or(_T_1347, _T_1348) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1353 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1354 = and(io.in.d.ready, io.in.d.valid) node _T_1355 = or(_T_1353, _T_1354) when _T_1355 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [7:0] a_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] a_first_beats1_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count_1 = 8'h0; // @[Edges.scala:234:25] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [15:0] io_in_a_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_a_bits_data = 128'h0; // @[Monitor.scala:36:7] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [7:0] a_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [7:0] a_first_beats1_decode_1 = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _T_1282 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1282; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1282; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T = a_first ? 8'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T_1 = a_first_1 ? 8'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1205 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1205; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1205; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1282 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1254 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1254 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1326 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1326 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_114 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_115 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_116 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_117 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_100 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_160 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_100( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_160 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d32s1k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d32s1k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d32s1k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_86 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a32d32s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeIn_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d32s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d32s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_5 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<2>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}} [3] wire _valids_WIRE : UInt<1>[3] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) regreset valids : UInt<1>[3], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], clock regreset enq_ptr_value : UInt<2>, clock, reset, UInt<2>(0h0) regreset deq_ptr_value : UInt<2>, clock, reset, UInt<2>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, UInt<1>(0h1)) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, UInt<1>(0h1)) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, UInt<1>(0h1)) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT.fflags, io.enq.bits.fflags connect MPORT.predicated, io.enq.bits.predicated connect MPORT.data, io.enq.bits.data connect MPORT.uop, io.enq.bits.uop connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<2>(0h2)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when wrap : connect enq_ptr_value, UInt<1>(0h0) when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<2>(0h2)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 when wrap_1 : connect deq_ptr_value, UInt<1>(0h0) node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}} infer mport out_MPORT = ram[deq_ptr_value], clock connect out.fflags, out_MPORT.fflags connect out.predicated, out_MPORT.predicated connect out.data, out_MPORT.data connect out.uop, out_MPORT.uop connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, UInt<1>(0h1)) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 when io.empty : connect io.deq.valid, io.enq.valid connect io.deq.bits, io.enq.bits node _io_deq_bits_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_3 = and(io.enq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_2) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_3 connect do_deq, UInt<1>(0h0) when io.deq.ready : connect do_enq, UInt<1>(0h0) node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = mux(maybe_full, UInt<2>(0h3), UInt<1>(0h0)) node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value) node _io_count_T_2 = add(UInt<2>(0h3), ptr_diff) node _io_count_T_3 = tail(_io_count_T_2, 1) node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff) node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4) connect io.count, _io_count_T_5	module BranchKillableQueue_5( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [7:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [64:0] io_enq_bits_data, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [7:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [64:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_predicated, // @[util.scala:453:14] output io_deq_bits_fflags_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_fflags_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_fflags_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_fflags_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_fflags_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_fflags_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_fflags_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_sfb, // @[util.scala:453:14] output [7:0] io_deq_bits_fflags_bits_uop_br_mask, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_br_tag, // @[util.scala:453:14] output [3:0] io_deq_bits_fflags_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_fflags_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_fflags_bits_uop_csr_addr, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_uop_rob_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ldq_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_rxq_idx, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_pdst, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_prs1, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_prs2, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_prs3, // @[util.scala:453:14] output [3:0] io_deq_bits_fflags_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ppred_busy, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_fflags_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_debug_tsrc, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_flags, // @[util.scala:453:14] input [7:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_is_br, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14] input io_brupdate_b2_uop_taken, // @[util.scala:453:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14] input io_brupdate_b2_uop_exception, // @[util.scala:453:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14] input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14] input io_brupdate_b2_valid, // @[util.scala:453:14] input io_brupdate_b2_mispredict, // @[util.scala:453:14] input io_brupdate_b2_taken, // @[util.scala:453:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14] input io_flush, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [460:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [7:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [64:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7] wire io_flush_0 = io_flush; // @[util.scala:448:7] wire [63:0] io_enq_bits_fflags_bits_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14] wire [11:0] io_enq_bits_fflags_bits_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14] wire [19:0] io_enq_bits_fflags_bits_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_pdst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_prs1 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_prs2 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_prs3 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14] wire [7:0] io_enq_bits_fflags_bits_uop_br_mask = 8'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_uop_rob_idx = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_flags = 5'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_enq_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_iw_state = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_mem_size = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[util.scala:448:7] wire [3:0] io_enq_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7, :453:14] wire [3:0] io_enq_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[util.scala:448:7, :453:14] wire [3:0] io_enq_bits_fflags_bits_uop_ppred = 4'h0; // @[util.scala:448:7, :453:14] wire [9:0] io_enq_bits_fflags_bits_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_br_tag = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_stq_idx = 3'h0; // @[util.scala:448:7, :453:14] wire [39:0] io_enq_bits_fflags_bits_uop_debug_pc = 40'h0; // @[util.scala:448:7, :453:14] wire [31:0] io_enq_bits_fflags_bits_uop_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [31:0] io_enq_bits_fflags_bits_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_enq_bits_fflags_bits_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14] wire io_enq_bits_predicated = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_valid = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_rvc = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_br = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_jalr = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_jal = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_sfb = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_edge_inst = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_taken = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_exception = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_bypassable = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_mem_signed = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_fence = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_fencei = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_amo = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_uses_stq = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_unique = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ldst_val = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_frs3_en = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_fp_val = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_fp_single = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _io_enq_ready_T; // @[util.scala:504:19] wire _io_empty_T_1; // @[util.scala:473:25] wire _valids_0_T_4 = io_flush_0; // @[util.scala:448:7, :481:83] wire _valids_1_T_4 = io_flush_0; // @[util.scala:448:7, :481:83] wire _valids_2_T_4 = io_flush_0; // @[util.scala:448:7, :481:83] wire _io_deq_valid_T_6 = io_flush_0; // @[util.scala:448:7, :509:122] wire [1:0] _io_count_T_5; // @[util.scala:529:20] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_fflags_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_fflags_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_fflags_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_fflags_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_fflags_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_fflags_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_fflags_bits_uop_br_mask_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_br_tag_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_fflags_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_fflags_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_fflags_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_pdst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_prs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_prs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_prs3_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_fflags_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_fflags_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_flags_0; // @[util.scala:448:7] wire io_deq_bits_fflags_valid_0; // @[util.scala:448:7] wire [64:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_predicated_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [1:0] io_count; // @[util.scala:448:7] wire [64:0] out_data = _ram_ext_R0_data[64:0]; // @[util.scala:464:20, :506:17] wire out_predicated = _ram_ext_R0_data[65]; // @[util.scala:464:20, :506:17] wire out_fflags_valid = _ram_ext_R0_data[66]; // @[util.scala:464:20, :506:17] wire [6:0] out_fflags_bits_uop_uopc = _ram_ext_R0_data[73:67]; // @[util.scala:464:20, :506:17] wire [31:0] out_fflags_bits_uop_inst = _ram_ext_R0_data[105:74]; // @[util.scala:464:20, :506:17] wire [31:0] out_fflags_bits_uop_debug_inst = _ram_ext_R0_data[137:106]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_rvc = _ram_ext_R0_data[138]; // @[util.scala:464:20, :506:17] wire [39:0] out_fflags_bits_uop_debug_pc = _ram_ext_R0_data[178:139]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_iq_type = _ram_ext_R0_data[181:179]; // @[util.scala:464:20, :506:17] wire [9:0] out_fflags_bits_uop_fu_code = _ram_ext_R0_data[191:182]; // @[util.scala:464:20, :506:17] wire [3:0] out_fflags_bits_uop_ctrl_br_type = _ram_ext_R0_data[195:192]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_ctrl_op1_sel = _ram_ext_R0_data[197:196]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ctrl_op2_sel = _ram_ext_R0_data[200:198]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ctrl_imm_sel = _ram_ext_R0_data[203:201]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_uop_ctrl_op_fcn = _ram_ext_R0_data[208:204]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_fcn_dw = _ram_ext_R0_data[209]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ctrl_csr_cmd = _ram_ext_R0_data[212:210]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_is_load = _ram_ext_R0_data[213]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_is_sta = _ram_ext_R0_data[214]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_is_std = _ram_ext_R0_data[215]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_iw_state = _ram_ext_R0_data[217:216]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_iw_p1_poisoned = _ram_ext_R0_data[218]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_iw_p2_poisoned = _ram_ext_R0_data[219]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_br = _ram_ext_R0_data[220]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_jalr = _ram_ext_R0_data[221]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_jal = _ram_ext_R0_data[222]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_sfb = _ram_ext_R0_data[223]; // @[util.scala:464:20, :506:17] wire [7:0] out_fflags_bits_uop_br_mask = _ram_ext_R0_data[231:224]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_br_tag = _ram_ext_R0_data[234:232]; // @[util.scala:464:20, :506:17] wire [3:0] out_fflags_bits_uop_ftq_idx = _ram_ext_R0_data[238:235]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_edge_inst = _ram_ext_R0_data[239]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_pc_lob = _ram_ext_R0_data[245:240]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_taken = _ram_ext_R0_data[246]; // @[util.scala:464:20, :506:17] wire [19:0] out_fflags_bits_uop_imm_packed = _ram_ext_R0_data[266:247]; // @[util.scala:464:20, :506:17] wire [11:0] out_fflags_bits_uop_csr_addr = _ram_ext_R0_data[278:267]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_uop_rob_idx = _ram_ext_R0_data[283:279]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ldq_idx = _ram_ext_R0_data[286:284]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_stq_idx = _ram_ext_R0_data[289:287]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_rxq_idx = _ram_ext_R0_data[291:290]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_pdst = _ram_ext_R0_data[297:292]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_prs1 = _ram_ext_R0_data[303:298]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_prs2 = _ram_ext_R0_data[309:304]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_prs3 = _ram_ext_R0_data[315:310]; // @[util.scala:464:20, :506:17] wire [3:0] out_fflags_bits_uop_ppred = _ram_ext_R0_data[319:316]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_prs1_busy = _ram_ext_R0_data[320]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_prs2_busy = _ram_ext_R0_data[321]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_prs3_busy = _ram_ext_R0_data[322]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ppred_busy = _ram_ext_R0_data[323]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_stale_pdst = _ram_ext_R0_data[329:324]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_exception = _ram_ext_R0_data[330]; // @[util.scala:464:20, :506:17] wire [63:0] out_fflags_bits_uop_exc_cause = _ram_ext_R0_data[394:331]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_bypassable = _ram_ext_R0_data[395]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_uop_mem_cmd = _ram_ext_R0_data[400:396]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_mem_size = _ram_ext_R0_data[402:401]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_mem_signed = _ram_ext_R0_data[403]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_fence = _ram_ext_R0_data[404]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_fencei = _ram_ext_R0_data[405]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_amo = _ram_ext_R0_data[406]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_uses_ldq = _ram_ext_R0_data[407]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_uses_stq = _ram_ext_R0_data[408]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_sys_pc2epc = _ram_ext_R0_data[409]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_unique = _ram_ext_R0_data[410]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_flush_on_commit = _ram_ext_R0_data[411]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ldst_is_rs1 = _ram_ext_R0_data[412]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_ldst = _ram_ext_R0_data[418:413]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_lrs1 = _ram_ext_R0_data[424:419]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_lrs2 = _ram_ext_R0_data[430:425]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_lrs3 = _ram_ext_R0_data[436:431]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ldst_val = _ram_ext_R0_data[437]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_dst_rtype = _ram_ext_R0_data[439:438]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_lrs1_rtype = _ram_ext_R0_data[441:440]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_lrs2_rtype = _ram_ext_R0_data[443:442]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_frs3_en = _ram_ext_R0_data[444]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_fp_val = _ram_ext_R0_data[445]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_fp_single = _ram_ext_R0_data[446]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_xcpt_pf_if = _ram_ext_R0_data[447]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_xcpt_ae_if = _ram_ext_R0_data[448]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_xcpt_ma_if = _ram_ext_R0_data[449]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_bp_debug_if = _ram_ext_R0_data[450]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_bp_xcpt_if = _ram_ext_R0_data[451]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_debug_fsrc = _ram_ext_R0_data[453:452]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_debug_tsrc = _ram_ext_R0_data[455:454]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_flags = _ram_ext_R0_data[460:456]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] reg valids_1; // @[util.scala:465:24] reg valids_2; // @[util.scala:465:24] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [39:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [7:0] uops_0_br_mask; // @[util.scala:466:20] reg [2:0] uops_0_br_tag; // @[util.scala:466:20] reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [4:0] uops_0_rob_idx; // @[util.scala:466:20] reg [2:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [2:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [5:0] uops_0_pdst; // @[util.scala:466:20] reg [5:0] uops_0_prs1; // @[util.scala:466:20] reg [5:0] uops_0_prs2; // @[util.scala:466:20] reg [5:0] uops_0_prs3; // @[util.scala:466:20] reg [3:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [5:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [39:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [7:0] uops_1_br_mask; // @[util.scala:466:20] reg [2:0] uops_1_br_tag; // @[util.scala:466:20] reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [4:0] uops_1_rob_idx; // @[util.scala:466:20] reg [2:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [2:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [5:0] uops_1_pdst; // @[util.scala:466:20] reg [5:0] uops_1_prs1; // @[util.scala:466:20] reg [5:0] uops_1_prs2; // @[util.scala:466:20] reg [5:0] uops_1_prs3; // @[util.scala:466:20] reg [3:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [5:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [39:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [7:0] uops_2_br_mask; // @[util.scala:466:20] reg [2:0] uops_2_br_tag; // @[util.scala:466:20] reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [4:0] uops_2_rob_idx; // @[util.scala:466:20] reg [2:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [2:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [5:0] uops_2_pdst; // @[util.scala:466:20] reg [5:0] uops_2_prs1; // @[util.scala:466:20] reg [5:0] uops_2_prs2; // @[util.scala:466:20] reg [5:0] uops_2_prs3; // @[util.scala:466:20] reg [3:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [5:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [1:0] enq_ptr_value; // @[Counter.scala:61:40] reg [1:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire full = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq; // @[util.scala:475:24] wire [3:0] _GEN = {{valids_0}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 \| _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq; // @[util.scala:476:24] wire [7:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_0_T_1 = \|_valids_0_T; // @[util.scala:118:{51,59}] wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32] wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}] wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}] wire [7:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [7:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [7:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_1_T_1 = \|_valids_1_T; // @[util.scala:118:{51,59}] wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32] wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}] wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}] wire [7:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [7:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [7:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_2_T_1 = \|_valids_2_T; // @[util.scala:118:{51,59}] wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32] wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}] wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}] wire [7:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [7:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire wrap = enq_ptr_value == 2'h2; // @[Counter.scala:61:40, :73:24] wire [7:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7] wire [2:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [2:0] _value_T = _GEN_1 + 3'h1; // @[Counter.scala:77:24] wire [1:0] _value_T_1 = _value_T[1:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 2'h2; // @[Counter.scala:61:40, :73:24] wire [2:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [2:0] _value_T_2 = _GEN_2 + 3'h1; // @[Counter.scala:77:24] wire [1:0] _value_T_3 = _value_T_2[1:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [39:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [7:0] out_uop_br_mask; // @[util.scala:506:17] wire [2:0] out_uop_br_tag; // @[util.scala:506:17] wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [4:0] out_uop_rob_idx; // @[util.scala:506:17] wire [2:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [2:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [5:0] out_uop_pdst; // @[util.scala:506:17] wire [5:0] out_uop_prs1; // @[util.scala:506:17] wire [5:0] out_uop_prs2; // @[util.scala:506:17] wire [5:0] out_uop_prs3; // @[util.scala:506:17] wire [3:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [5:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [3:0][6:0] _GEN_3 = {{uops_0_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][31:0] _GEN_4 = {{uops_0_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][31:0] _GEN_5 = {{uops_0_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_6 = {{uops_0_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][39:0] _GEN_7 = {{uops_0_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_8 = {{uops_0_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][9:0] _GEN_9 = {{uops_0_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][3:0] _GEN_10 = {{uops_0_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_11 = {{uops_0_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_12 = {{uops_0_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_13 = {{uops_0_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][4:0] _GEN_14 = {{uops_0_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_15 = {{uops_0_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_16 = {{uops_0_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_17 = {{uops_0_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_18 = {{uops_0_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_19 = {{uops_0_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_20 = {{uops_0_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_21 = {{uops_0_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_22 = {{uops_0_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_23 = {{uops_0_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_24 = {{uops_0_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_25 = {{uops_0_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_26 = {{uops_0_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][7:0] _GEN_27 = {{uops_0_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_28 = {{uops_0_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][3:0] _GEN_29 = {{uops_0_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_30 = {{uops_0_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_31 = {{uops_0_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_32 = {{uops_0_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][19:0] _GEN_33 = {{uops_0_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][11:0] _GEN_34 = {{uops_0_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][4:0] _GEN_35 = {{uops_0_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_36 = {{uops_0_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_37 = {{uops_0_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_38 = {{uops_0_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_39 = {{uops_0_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_40 = {{uops_0_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_41 = {{uops_0_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_42 = {{uops_0_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][3:0] _GEN_43 = {{uops_0_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_44 = {{uops_0_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_45 = {{uops_0_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_46 = {{uops_0_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_47 = {{uops_0_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_48 = {{uops_0_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_49 = {{uops_0_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][63:0] _GEN_50 = {{uops_0_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_51 = {{uops_0_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][4:0] _GEN_52 = {{uops_0_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_53 = {{uops_0_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_54 = {{uops_0_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_55 = {{uops_0_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_56 = {{uops_0_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_57 = {{uops_0_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_58 = {{uops_0_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_59 = {{uops_0_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_60 = {{uops_0_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_61 = {{uops_0_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_62 = {{uops_0_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_63 = {{uops_0_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_64 = {{uops_0_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_65 = {{uops_0_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_66 = {{uops_0_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_67 = {{uops_0_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_68 = {{uops_0_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_69 = {{uops_0_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_70 = {{uops_0_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_71 = {{uops_0_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_72 = {{uops_0_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_73 = {{uops_0_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_74 = {{uops_0_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_75 = {{uops_0_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_76 = {{uops_0_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_77 = {{uops_0_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_78 = {{uops_0_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_79 = {{uops_0_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_80 = {{uops_0_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_81 = {{uops_0_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:476:42, :509:{30,40}] wire [7:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17] wire _io_deq_valid_T_3 = \|_io_deq_valid_T_2; // @[util.scala:118:{51,59}] wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68] wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}] wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}] wire _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}] wire [7:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [7:0] _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17] assign io_deq_valid_0 = io_empty_0 ? io_enq_valid_0 : _io_deq_valid_T_8; // @[util.scala:448:7, :509:{27,108}, :515:21, :516:20] assign io_deq_bits_uop_uopc_0 = io_empty_0 ? io_enq_bits_uop_uopc_0 : out_uop_uopc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_inst_0 = io_empty_0 ? io_enq_bits_uop_inst_0 : out_uop_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_inst_0 = io_empty_0 ? io_enq_bits_uop_debug_inst_0 : out_uop_debug_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_rvc_0 = io_empty_0 ? io_enq_bits_uop_is_rvc_0 : out_uop_is_rvc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_pc_0 = io_empty_0 ? io_enq_bits_uop_debug_pc_0 : out_uop_debug_pc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iq_type_0 = io_empty_0 ? io_enq_bits_uop_iq_type_0 : out_uop_iq_type; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_fu_code_0 = io_empty_0 ? io_enq_bits_uop_fu_code_0 : out_uop_fu_code; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_br_type_0 = io_empty_0 ? io_enq_bits_uop_ctrl_br_type_0 : out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_op1_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op1_sel_0 : out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_op2_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op2_sel_0 : out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_imm_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_imm_sel_0 : out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_op_fcn_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op_fcn_0 : out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_fcn_dw_0 = io_empty_0 ? io_enq_bits_uop_ctrl_fcn_dw_0 : out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_csr_cmd_0 = io_empty_0 ? io_enq_bits_uop_ctrl_csr_cmd_0 : out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_is_load_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_load_0 : out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_is_sta_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_sta_0 : out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_is_std_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_std_0 : out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iw_state_0 = io_empty_0 ? io_enq_bits_uop_iw_state_0 : out_uop_iw_state; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iw_p1_poisoned_0 = io_empty_0 ? io_enq_bits_uop_iw_p1_poisoned_0 : out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iw_p2_poisoned_0 = io_empty_0 ? io_enq_bits_uop_iw_p2_poisoned_0 : out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_br_0 = io_empty_0 ? io_enq_bits_uop_is_br_0 : out_uop_is_br; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_jalr_0 = io_empty_0 ? io_enq_bits_uop_is_jalr_0 : out_uop_is_jalr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_jal_0 = io_empty_0 ? io_enq_bits_uop_is_jal_0 : out_uop_is_jal; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_sfb_0 = io_empty_0 ? io_enq_bits_uop_is_sfb_0 : out_uop_is_sfb; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_br_tag_0 = io_empty_0 ? io_enq_bits_uop_br_tag_0 : out_uop_br_tag; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ftq_idx_0 = io_empty_0 ? io_enq_bits_uop_ftq_idx_0 : out_uop_ftq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_edge_inst_0 = io_empty_0 ? io_enq_bits_uop_edge_inst_0 : out_uop_edge_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_pc_lob_0 = io_empty_0 ? io_enq_bits_uop_pc_lob_0 : out_uop_pc_lob; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_taken_0 = io_empty_0 ? io_enq_bits_uop_taken_0 : out_uop_taken; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_imm_packed_0 = io_empty_0 ? io_enq_bits_uop_imm_packed_0 : out_uop_imm_packed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_csr_addr_0 = io_empty_0 ? io_enq_bits_uop_csr_addr_0 : out_uop_csr_addr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_rob_idx_0 = io_empty_0 ? io_enq_bits_uop_rob_idx_0 : out_uop_rob_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldq_idx_0 = io_empty_0 ? io_enq_bits_uop_ldq_idx_0 : out_uop_ldq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_stq_idx_0 = io_empty_0 ? io_enq_bits_uop_stq_idx_0 : out_uop_stq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_rxq_idx_0 = io_empty_0 ? io_enq_bits_uop_rxq_idx_0 : out_uop_rxq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_pdst_0 = io_empty_0 ? io_enq_bits_uop_pdst_0 : out_uop_pdst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs1_0 = io_empty_0 ? io_enq_bits_uop_prs1_0 : out_uop_prs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs2_0 = io_empty_0 ? io_enq_bits_uop_prs2_0 : out_uop_prs2; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs3_0 = io_empty_0 ? io_enq_bits_uop_prs3_0 : out_uop_prs3; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ppred_0 = io_empty_0 ? io_enq_bits_uop_ppred_0 : out_uop_ppred; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs1_busy_0 = io_empty_0 ? io_enq_bits_uop_prs1_busy_0 : out_uop_prs1_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs2_busy_0 = io_empty_0 ? io_enq_bits_uop_prs2_busy_0 : out_uop_prs2_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs3_busy_0 = io_empty_0 ? io_enq_bits_uop_prs3_busy_0 : out_uop_prs3_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ppred_busy_0 = io_empty_0 ? io_enq_bits_uop_ppred_busy_0 : out_uop_ppred_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_stale_pdst_0 = io_empty_0 ? io_enq_bits_uop_stale_pdst_0 : out_uop_stale_pdst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_exception_0 = io_empty_0 ? io_enq_bits_uop_exception_0 : out_uop_exception; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_exc_cause_0 = io_empty_0 ? io_enq_bits_uop_exc_cause_0 : out_uop_exc_cause; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_bypassable_0 = io_empty_0 ? io_enq_bits_uop_bypassable_0 : out_uop_bypassable; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_mem_cmd_0 = io_empty_0 ? io_enq_bits_uop_mem_cmd_0 : out_uop_mem_cmd; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_mem_size_0 = io_empty_0 ? io_enq_bits_uop_mem_size_0 : out_uop_mem_size; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_mem_signed_0 = io_empty_0 ? io_enq_bits_uop_mem_signed_0 : out_uop_mem_signed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_fence_0 = io_empty_0 ? io_enq_bits_uop_is_fence_0 : out_uop_is_fence; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_fencei_0 = io_empty_0 ? io_enq_bits_uop_is_fencei_0 : out_uop_is_fencei; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_amo_0 = io_empty_0 ? io_enq_bits_uop_is_amo_0 : out_uop_is_amo; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_uses_ldq_0 = io_empty_0 ? io_enq_bits_uop_uses_ldq_0 : out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_uses_stq_0 = io_empty_0 ? io_enq_bits_uop_uses_stq_0 : out_uop_uses_stq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = io_empty_0 ? io_enq_bits_uop_is_sys_pc2epc_0 : out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_unique_0 = io_empty_0 ? io_enq_bits_uop_is_unique_0 : out_uop_is_unique; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_flush_on_commit_0 = io_empty_0 ? io_enq_bits_uop_flush_on_commit_0 : out_uop_flush_on_commit; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldst_is_rs1_0 = io_empty_0 ? io_enq_bits_uop_ldst_is_rs1_0 : out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldst_0 = io_empty_0 ? io_enq_bits_uop_ldst_0 : out_uop_ldst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs1_0 = io_empty_0 ? io_enq_bits_uop_lrs1_0 : out_uop_lrs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs2_0 = io_empty_0 ? io_enq_bits_uop_lrs2_0 : out_uop_lrs2; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs3_0 = io_empty_0 ? io_enq_bits_uop_lrs3_0 : out_uop_lrs3; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldst_val_0 = io_empty_0 ? io_enq_bits_uop_ldst_val_0 : out_uop_ldst_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_dst_rtype_0 = io_empty_0 ? io_enq_bits_uop_dst_rtype_0 : out_uop_dst_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs1_rtype_0 = io_empty_0 ? io_enq_bits_uop_lrs1_rtype_0 : out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs2_rtype_0 = io_empty_0 ? io_enq_bits_uop_lrs2_rtype_0 : out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_frs3_en_0 = io_empty_0 ? io_enq_bits_uop_frs3_en_0 : out_uop_frs3_en; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_fp_val_0 = io_empty_0 ? io_enq_bits_uop_fp_val_0 : out_uop_fp_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_fp_single_0 = io_empty_0 ? io_enq_bits_uop_fp_single_0 : out_uop_fp_single; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_xcpt_pf_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_pf_if_0 : out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_xcpt_ae_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_ae_if_0 : out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_xcpt_ma_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_ma_if_0 : out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_bp_debug_if_0 = io_empty_0 ? io_enq_bits_uop_bp_debug_if_0 : out_uop_bp_debug_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_bp_xcpt_if_0 = io_empty_0 ? io_enq_bits_uop_bp_xcpt_if_0 : out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_fsrc_0 = io_empty_0 ? io_enq_bits_uop_debug_fsrc_0 : out_uop_debug_fsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_tsrc_0 = io_empty_0 ? io_enq_bits_uop_debug_tsrc_0 : out_uop_debug_tsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_data_0 = io_empty_0 ? io_enq_bits_data_0 : out_data; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_predicated_0 = ~io_empty_0 & out_predicated; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_valid_0 = ~io_empty_0 & out_fflags_valid; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_uopc_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_uopc; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_inst_0 = io_empty_0 ? 32'h0 : out_fflags_bits_uop_inst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_inst_0 = io_empty_0 ? 32'h0 : out_fflags_bits_uop_debug_inst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_rvc_0 = ~io_empty_0 & out_fflags_bits_uop_is_rvc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_pc_0 = io_empty_0 ? 40'h0 : out_fflags_bits_uop_debug_pc; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iq_type_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_iq_type; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_fu_code_0 = io_empty_0 ? 10'h0 : out_fflags_bits_uop_fu_code; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_br_type_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_ctrl_br_type; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_op2_sel; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_imm_sel; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_ctrl_op_fcn; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_is_load_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_load; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_is_sta_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_is_std_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_std; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iw_state_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_iw_state; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0 = ~io_empty_0 & out_fflags_bits_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0 = ~io_empty_0 & out_fflags_bits_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_br_0 = ~io_empty_0 & out_fflags_bits_uop_is_br; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_jalr_0 = ~io_empty_0 & out_fflags_bits_uop_is_jalr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_jal_0 = ~io_empty_0 & out_fflags_bits_uop_is_jal; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_sfb_0 = ~io_empty_0 & out_fflags_bits_uop_is_sfb; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_br_mask_0 = io_empty_0 ? 8'h0 : out_fflags_bits_uop_br_mask; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_br_tag_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_br_tag; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ftq_idx_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_ftq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_edge_inst_0 = ~io_empty_0 & out_fflags_bits_uop_edge_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_pc_lob_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_pc_lob; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_taken_0 = ~io_empty_0 & out_fflags_bits_uop_taken; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_imm_packed_0 = io_empty_0 ? 20'h0 : out_fflags_bits_uop_imm_packed; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_csr_addr_0 = io_empty_0 ? 12'h0 : out_fflags_bits_uop_csr_addr; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_rob_idx_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_rob_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldq_idx_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ldq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_stq_idx_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_stq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_rxq_idx_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_rxq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_pdst_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_pdst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs1_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_prs1; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs2_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_prs2; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs3_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_prs3; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ppred_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_ppred; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs1_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs1_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs2_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs2_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs3_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs3_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ppred_busy_0 = ~io_empty_0 & out_fflags_bits_uop_ppred_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_stale_pdst_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_stale_pdst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_exception_0 = ~io_empty_0 & out_fflags_bits_uop_exception; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_exc_cause_0 = io_empty_0 ? 64'h0 : out_fflags_bits_uop_exc_cause; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_bypassable_0 = ~io_empty_0 & out_fflags_bits_uop_bypassable; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_mem_cmd_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_mem_cmd; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_mem_size_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_mem_size; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_mem_signed_0 = ~io_empty_0 & out_fflags_bits_uop_mem_signed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_fence_0 = ~io_empty_0 & out_fflags_bits_uop_is_fence; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_fencei_0 = ~io_empty_0 & out_fflags_bits_uop_is_fencei; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_amo_0 = ~io_empty_0 & out_fflags_bits_uop_is_amo; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_uses_ldq_0 = ~io_empty_0 & out_fflags_bits_uop_uses_ldq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_uses_stq_0 = ~io_empty_0 & out_fflags_bits_uop_uses_stq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0 = ~io_empty_0 & out_fflags_bits_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_unique_0 = ~io_empty_0 & out_fflags_bits_uop_is_unique; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_flush_on_commit_0 = ~io_empty_0 & out_fflags_bits_uop_flush_on_commit; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldst_is_rs1_0 = ~io_empty_0 & out_fflags_bits_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldst_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_ldst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs1_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs1; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs2_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs2; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs3_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs3; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldst_val_0 = ~io_empty_0 & out_fflags_bits_uop_ldst_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_dst_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_dst_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs1_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_lrs1_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs2_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_lrs2_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_frs3_en_0 = ~io_empty_0 & out_fflags_bits_uop_frs3_en; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_fp_val_0 = ~io_empty_0 & out_fflags_bits_uop_fp_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_fp_single_0 = ~io_empty_0 & out_fflags_bits_uop_fp_single; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_xcpt_pf_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_xcpt_ae_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_xcpt_ma_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_bp_debug_if_0 = ~io_empty_0 & out_fflags_bits_uop_bp_debug_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_bp_xcpt_if_0 = ~io_empty_0 & out_fflags_bits_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_fsrc_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_debug_fsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_tsrc_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_debug_tsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_flags_0 = io_empty_0 ? 5'h0 : out_fflags_bits_flags; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] wire [7:0] _io_deq_bits_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [7:0] _io_deq_bits_uop_br_mask_T_3 = io_enq_bits_uop_br_mask_0 & _io_deq_bits_uop_br_mask_T_2; // @[util.scala:85:{25,27}, :448:7] assign io_deq_bits_uop_br_mask_0 = io_empty_0 ? _io_deq_bits_uop_br_mask_T_3 : _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7, :511:27, :515:21, :518:31] assign do_deq = ~io_empty_0 & _do_deq_T_3; // @[util.scala:448:7, :476:{24,66}, :510:27, :515:21, :517:19, :520:14] assign do_enq = ~(io_empty_0 & io_deq_ready_0) & _do_enq_T; // @[Decoupled.scala:51:35] wire [2:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [1:0] ptr_diff = _ptr_diff_T[1:0]; // @[util.scala:524:40] wire [1:0] _io_count_T = {2{maybe_full}}; // @[util.scala:470:27, :530:24] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [2:0] _io_count_T_2 = {1'h0, ptr_diff} + 3'h3; // @[util.scala:524:40, :533:40] wire [1:0] _io_count_T_3 = _io_count_T_2[1:0]; // @[util.scala:533:40] wire [1:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:524:40, :532:{24,39}, :533:40] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:472:33, :529:20, :530:24, :532:24] assign io_count = _io_count_T_5; // @[util.scala:448:7, :529:20] wire _GEN_82 = enq_ptr_value == 2'h0; // @[Counter.scala:61:40] wire _GEN_83 = do_enq & _GEN_82; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_84 = enq_ptr_value == 2'h1; // @[Counter.scala:61:40] wire _GEN_85 = do_enq & _GEN_84; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_86 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 2'h0; // @[Counter.scala:61:40] deq_ptr_value <= 2'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_83 \| _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_85 \| _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & wrap_1) & (_GEN_86 \| _valids_2_T_6); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= wrap ? 2'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= wrap_1 ? 2'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_83) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_82) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_85) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_84) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_3x461 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({396'h0, io_enq_bits_data_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_predicated = io_deq_bits_predicated_0; // @[util.scala:448:7] assign io_deq_bits_fflags_valid = io_deq_bits_fflags_valid_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_uopc = io_deq_bits_fflags_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_inst = io_deq_bits_fflags_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_inst = io_deq_bits_fflags_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_rvc = io_deq_bits_fflags_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_pc = io_deq_bits_fflags_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iq_type = io_deq_bits_fflags_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_fu_code = io_deq_bits_fflags_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_br_type = io_deq_bits_fflags_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_op1_sel = io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_op2_sel = io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_imm_sel = io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_op_fcn = io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_fcn_dw = io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_csr_cmd = io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_is_load = io_deq_bits_fflags_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_is_sta = io_deq_bits_fflags_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_is_std = io_deq_bits_fflags_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iw_state = io_deq_bits_fflags_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iw_p1_poisoned = io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iw_p2_poisoned = io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_br = io_deq_bits_fflags_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_jalr = io_deq_bits_fflags_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_jal = io_deq_bits_fflags_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_sfb = io_deq_bits_fflags_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_br_mask = io_deq_bits_fflags_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_br_tag = io_deq_bits_fflags_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ftq_idx = io_deq_bits_fflags_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_edge_inst = io_deq_bits_fflags_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_pc_lob = io_deq_bits_fflags_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_taken = io_deq_bits_fflags_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_imm_packed = io_deq_bits_fflags_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_csr_addr = io_deq_bits_fflags_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_rob_idx = io_deq_bits_fflags_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldq_idx = io_deq_bits_fflags_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_stq_idx = io_deq_bits_fflags_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_rxq_idx = io_deq_bits_fflags_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_pdst = io_deq_bits_fflags_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs1 = io_deq_bits_fflags_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs2 = io_deq_bits_fflags_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs3 = io_deq_bits_fflags_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ppred = io_deq_bits_fflags_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs1_busy = io_deq_bits_fflags_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs2_busy = io_deq_bits_fflags_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs3_busy = io_deq_bits_fflags_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ppred_busy = io_deq_bits_fflags_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_stale_pdst = io_deq_bits_fflags_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_exception = io_deq_bits_fflags_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_exc_cause = io_deq_bits_fflags_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_bypassable = io_deq_bits_fflags_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_mem_cmd = io_deq_bits_fflags_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_mem_size = io_deq_bits_fflags_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_mem_signed = io_deq_bits_fflags_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_fence = io_deq_bits_fflags_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_fencei = io_deq_bits_fflags_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_amo = io_deq_bits_fflags_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_uses_ldq = io_deq_bits_fflags_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_uses_stq = io_deq_bits_fflags_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_sys_pc2epc = io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_unique = io_deq_bits_fflags_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_flush_on_commit = io_deq_bits_fflags_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldst_is_rs1 = io_deq_bits_fflags_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldst = io_deq_bits_fflags_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs1 = io_deq_bits_fflags_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs2 = io_deq_bits_fflags_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs3 = io_deq_bits_fflags_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldst_val = io_deq_bits_fflags_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_dst_rtype = io_deq_bits_fflags_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs1_rtype = io_deq_bits_fflags_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs2_rtype = io_deq_bits_fflags_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_frs3_en = io_deq_bits_fflags_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_fp_val = io_deq_bits_fflags_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_fp_single = io_deq_bits_fflags_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_xcpt_pf_if = io_deq_bits_fflags_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_xcpt_ae_if = io_deq_bits_fflags_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_xcpt_ma_if = io_deq_bits_fflags_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_bp_debug_if = io_deq_bits_fflags_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_bp_xcpt_if = io_deq_bits_fflags_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_fsrc = io_deq_bits_fflags_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_tsrc = io_deq_bits_fflags_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_flags = io_deq_bits_fflags_bits_flags_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_61 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in wire initval : { state : UInt<2>} connect initval.state, UInt<1>(0h0) wire _cam_s_WIRE : { state : UInt<2>}[1] connect _cam_s_WIRE[0], initval regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) node _a_canLogical_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canLogical_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canLogical_T_2 = cvt(_a_canLogical_T_1) node _a_canLogical_T_3 = and(_a_canLogical_T_2, asSInt(UInt<1>(0h0))) node _a_canLogical_T_4 = asSInt(_a_canLogical_T_3) node _a_canLogical_T_5 = eq(_a_canLogical_T_4, asSInt(UInt<1>(0h0))) node _a_canLogical_T_6 = and(_a_canLogical_T, _a_canLogical_T_5) node _a_canLogical_T_7 = or(UInt<1>(0h0), _a_canLogical_T_6) node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_7) node _a_canArithmetic_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canArithmetic_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canArithmetic_T_2 = cvt(_a_canArithmetic_T_1) node _a_canArithmetic_T_3 = and(_a_canArithmetic_T_2, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_4 = asSInt(_a_canArithmetic_T_3) node _a_canArithmetic_T_5 = eq(_a_canArithmetic_T_4, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_6 = and(_a_canArithmetic_T, _a_canArithmetic_T_5) node _a_canArithmetic_T_7 = or(UInt<1>(0h0), _a_canArithmetic_T_6) node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_7) node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_fifoId_T_1 = cvt(_a_fifoId_T) node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) node _indexes_T = bits(cam_a[0].bits.data, 0, 0) node _indexes_T_1 = bits(cam_d[0].data, 0, 0) node indexes_0 = cat(_indexes_T, _indexes_T_1) node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) node _indexes_T_3 = bits(cam_d[0].data, 1, 1) node indexes_1 = cat(_indexes_T_2, _indexes_T_3) node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) node _indexes_T_5 = bits(cam_d[0].data, 2, 2) node indexes_2 = cat(_indexes_T_4, _indexes_T_5) node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) node _indexes_T_7 = bits(cam_d[0].data, 3, 3) node indexes_3 = cat(_indexes_T_6, _indexes_T_7) node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) node _indexes_T_9 = bits(cam_d[0].data, 4, 4) node indexes_4 = cat(_indexes_T_8, _indexes_T_9) node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) node _indexes_T_11 = bits(cam_d[0].data, 5, 5) node indexes_5 = cat(_indexes_T_10, _indexes_T_11) node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) node _indexes_T_13 = bits(cam_d[0].data, 6, 6) node indexes_6 = cat(_indexes_T_12, _indexes_T_13) node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) node _indexes_T_15 = bits(cam_d[0].data, 7, 7) node indexes_7 = cat(_indexes_T_14, _indexes_T_15) node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) node _indexes_T_17 = bits(cam_d[0].data, 8, 8) node indexes_8 = cat(_indexes_T_16, _indexes_T_17) node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) node _indexes_T_19 = bits(cam_d[0].data, 9, 9) node indexes_9 = cat(_indexes_T_18, _indexes_T_19) node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) node _indexes_T_21 = bits(cam_d[0].data, 10, 10) node indexes_10 = cat(_indexes_T_20, _indexes_T_21) node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) node _indexes_T_23 = bits(cam_d[0].data, 11, 11) node indexes_11 = cat(_indexes_T_22, _indexes_T_23) node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) node _indexes_T_25 = bits(cam_d[0].data, 12, 12) node indexes_12 = cat(_indexes_T_24, _indexes_T_25) node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) node _indexes_T_27 = bits(cam_d[0].data, 13, 13) node indexes_13 = cat(_indexes_T_26, _indexes_T_27) node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) node _indexes_T_29 = bits(cam_d[0].data, 14, 14) node indexes_14 = cat(_indexes_T_28, _indexes_T_29) node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) node _indexes_T_31 = bits(cam_d[0].data, 15, 15) node indexes_15 = cat(_indexes_T_30, _indexes_T_31) node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) node _indexes_T_33 = bits(cam_d[0].data, 16, 16) node indexes_16 = cat(_indexes_T_32, _indexes_T_33) node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) node _indexes_T_35 = bits(cam_d[0].data, 17, 17) node indexes_17 = cat(_indexes_T_34, _indexes_T_35) node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) node _indexes_T_37 = bits(cam_d[0].data, 18, 18) node indexes_18 = cat(_indexes_T_36, _indexes_T_37) node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) node _indexes_T_39 = bits(cam_d[0].data, 19, 19) node indexes_19 = cat(_indexes_T_38, _indexes_T_39) node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) node _indexes_T_41 = bits(cam_d[0].data, 20, 20) node indexes_20 = cat(_indexes_T_40, _indexes_T_41) node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) node _indexes_T_43 = bits(cam_d[0].data, 21, 21) node indexes_21 = cat(_indexes_T_42, _indexes_T_43) node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) node _indexes_T_45 = bits(cam_d[0].data, 22, 22) node indexes_22 = cat(_indexes_T_44, _indexes_T_45) node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) node _indexes_T_47 = bits(cam_d[0].data, 23, 23) node indexes_23 = cat(_indexes_T_46, _indexes_T_47) node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) node _indexes_T_49 = bits(cam_d[0].data, 24, 24) node indexes_24 = cat(_indexes_T_48, _indexes_T_49) node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) node _indexes_T_51 = bits(cam_d[0].data, 25, 25) node indexes_25 = cat(_indexes_T_50, _indexes_T_51) node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) node _indexes_T_53 = bits(cam_d[0].data, 26, 26) node indexes_26 = cat(_indexes_T_52, _indexes_T_53) node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) node _indexes_T_55 = bits(cam_d[0].data, 27, 27) node indexes_27 = cat(_indexes_T_54, _indexes_T_55) node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) node _indexes_T_57 = bits(cam_d[0].data, 28, 28) node indexes_28 = cat(_indexes_T_56, _indexes_T_57) node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) node _indexes_T_59 = bits(cam_d[0].data, 29, 29) node indexes_29 = cat(_indexes_T_58, _indexes_T_59) node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) node _indexes_T_61 = bits(cam_d[0].data, 30, 30) node indexes_30 = cat(_indexes_T_60, _indexes_T_61) node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) node _indexes_T_63 = bits(cam_d[0].data, 31, 31) node indexes_31 = cat(_indexes_T_62, _indexes_T_63) node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) node _indexes_T_65 = bits(cam_d[0].data, 32, 32) node indexes_32 = cat(_indexes_T_64, _indexes_T_65) node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) node _indexes_T_67 = bits(cam_d[0].data, 33, 33) node indexes_33 = cat(_indexes_T_66, _indexes_T_67) node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) node _indexes_T_69 = bits(cam_d[0].data, 34, 34) node indexes_34 = cat(_indexes_T_68, _indexes_T_69) node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) node _indexes_T_71 = bits(cam_d[0].data, 35, 35) node indexes_35 = cat(_indexes_T_70, _indexes_T_71) node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) node _indexes_T_73 = bits(cam_d[0].data, 36, 36) node indexes_36 = cat(_indexes_T_72, _indexes_T_73) node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) node _indexes_T_75 = bits(cam_d[0].data, 37, 37) node indexes_37 = cat(_indexes_T_74, _indexes_T_75) node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) node _indexes_T_77 = bits(cam_d[0].data, 38, 38) node indexes_38 = cat(_indexes_T_76, _indexes_T_77) node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) node _indexes_T_79 = bits(cam_d[0].data, 39, 39) node indexes_39 = cat(_indexes_T_78, _indexes_T_79) node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) node _indexes_T_81 = bits(cam_d[0].data, 40, 40) node indexes_40 = cat(_indexes_T_80, _indexes_T_81) node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) node _indexes_T_83 = bits(cam_d[0].data, 41, 41) node indexes_41 = cat(_indexes_T_82, _indexes_T_83) node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) node _indexes_T_85 = bits(cam_d[0].data, 42, 42) node indexes_42 = cat(_indexes_T_84, _indexes_T_85) node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) node _indexes_T_87 = bits(cam_d[0].data, 43, 43) node indexes_43 = cat(_indexes_T_86, _indexes_T_87) node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) node _indexes_T_89 = bits(cam_d[0].data, 44, 44) node indexes_44 = cat(_indexes_T_88, _indexes_T_89) node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) node _indexes_T_91 = bits(cam_d[0].data, 45, 45) node indexes_45 = cat(_indexes_T_90, _indexes_T_91) node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) node _indexes_T_93 = bits(cam_d[0].data, 46, 46) node indexes_46 = cat(_indexes_T_92, _indexes_T_93) node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) node _indexes_T_95 = bits(cam_d[0].data, 47, 47) node indexes_47 = cat(_indexes_T_94, _indexes_T_95) node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) node _indexes_T_97 = bits(cam_d[0].data, 48, 48) node indexes_48 = cat(_indexes_T_96, _indexes_T_97) node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) node _indexes_T_99 = bits(cam_d[0].data, 49, 49) node indexes_49 = cat(_indexes_T_98, _indexes_T_99) node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) node _indexes_T_101 = bits(cam_d[0].data, 50, 50) node indexes_50 = cat(_indexes_T_100, _indexes_T_101) node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) node _indexes_T_103 = bits(cam_d[0].data, 51, 51) node indexes_51 = cat(_indexes_T_102, _indexes_T_103) node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) node _indexes_T_105 = bits(cam_d[0].data, 52, 52) node indexes_52 = cat(_indexes_T_104, _indexes_T_105) node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) node _indexes_T_107 = bits(cam_d[0].data, 53, 53) node indexes_53 = cat(_indexes_T_106, _indexes_T_107) node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) node _indexes_T_109 = bits(cam_d[0].data, 54, 54) node indexes_54 = cat(_indexes_T_108, _indexes_T_109) node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) node _indexes_T_111 = bits(cam_d[0].data, 55, 55) node indexes_55 = cat(_indexes_T_110, _indexes_T_111) node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) node _indexes_T_113 = bits(cam_d[0].data, 56, 56) node indexes_56 = cat(_indexes_T_112, _indexes_T_113) node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) node _indexes_T_115 = bits(cam_d[0].data, 57, 57) node indexes_57 = cat(_indexes_T_114, _indexes_T_115) node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) node _indexes_T_117 = bits(cam_d[0].data, 58, 58) node indexes_58 = cat(_indexes_T_116, _indexes_T_117) node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) node _indexes_T_119 = bits(cam_d[0].data, 59, 59) node indexes_59 = cat(_indexes_T_118, _indexes_T_119) node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) node _indexes_T_121 = bits(cam_d[0].data, 60, 60) node indexes_60 = cat(_indexes_T_120, _indexes_T_121) node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) node _indexes_T_123 = bits(cam_d[0].data, 61, 61) node indexes_61 = cat(_indexes_T_122, _indexes_T_123) node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) node _indexes_T_125 = bits(cam_d[0].data, 62, 62) node indexes_62 = cat(_indexes_T_124, _indexes_T_125) node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) node _indexes_T_127 = bits(cam_d[0].data, 63, 63) node indexes_63 = cat(_indexes_T_126, _indexes_T_127) node _logic_out_T = dshr(cam_a[0].lut, indexes_0) node _logic_out_T_1 = bits(_logic_out_T, 0, 0) node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) node logic_out = cat(logic_out_hi, logic_out_lo) node unsigned = bits(cam_a[0].bits.param, 1, 1) node take_max = bits(cam_a[0].bits.param, 0, 0) node adder = bits(cam_a[0].bits.param, 2, 2) node _signSel_T = not(cam_a[0].bits.mask) node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) node _signSel_T_2 = or(_signSel_T, _signSel_T_1) node signSel = not(_signSel_T_2) node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) node signbits_a = cat(signbits_a_hi, signbits_a_lo) node _signbits_d_T = bits(cam_d[0].data, 7, 7) node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) node signbits_d = cat(signbits_d_hi, signbits_d_lo) node _signbit_a_T = and(signbits_a, signSel) node _signbit_a_T_1 = shl(_signbit_a_T, 1) node signbit_a = bits(_signbit_a_T_1, 7, 0) node _signbit_d_T = and(signbits_d, signSel) node _signbit_d_T_1 = shl(_signbit_d_T, 1) node signbit_d = bits(_signbit_d_T_1, 7, 0) node _signext_a_T = shl(signbit_a, 1) node _signext_a_T_1 = bits(_signext_a_T, 7, 0) node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) node _signext_a_T_3 = shl(_signext_a_T_2, 2) node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) node _signext_a_T_6 = shl(_signext_a_T_5, 4) node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) node signext_a = cat(signext_a_hi, signext_a_lo) node _signext_d_T = shl(signbit_d, 1) node _signext_d_T_1 = bits(_signext_d_T, 7, 0) node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) node _signext_d_T_3 = shl(_signext_d_T_2, 2) node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) node _signext_d_T_6 = shl(_signext_d_T_5, 4) node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) node signext_d = cat(signext_d_hi, signext_d_lo) node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) node wide_mask = cat(wide_mask_hi, wide_mask_lo) node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) node a_a_ext = or(_a_a_ext_T, signext_a) node _a_d_ext_T = and(cam_d[0].data, wide_mask) node a_d_ext = or(_a_d_ext_T, signext_d) node _a_d_inv_T = not(a_d_ext) node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) node _adder_out_T = add(a_a_ext, a_d_inv) node adder_out = tail(_adder_out_T, 1) node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) node _a_bigger_T = bits(a_a_ext, 63, 63) node _a_bigger_T_1 = bits(a_d_ext, 63, 63) node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) node _a_bigger_T_3 = bits(adder_out, 63, 63) node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) node pick_a = eq(take_max, a_bigger) node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) node arith_out = mux(adder, adder_out, _arith_out_T) node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) node amo_data = mux(_amo_data_T, logic_out, arith_out) wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) node _a_allow_T_1 = or(a_isSupported, cam_free_0) node a_allow = and(_a_allow_T, _a_allow_T_1) node _nodeIn_a_ready_T = and(source_i.ready, a_allow) connect nodeIn.a.ready, _nodeIn_a_ready_T node _source_i_valid_T = and(nodeIn.a.valid, a_allow) connect source_i.valid, _source_i_valid_T connect source_i.bits, nodeIn.a.bits node _T = eq(a_isSupported, UInt<1>(0h0)) when _T : connect source_i.bits.opcode, UInt<3>(0h4) connect source_i.bits.param, UInt<1>(0h0) wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect source_c.valid, cam_amo_0 node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<2>(0h3)) node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<1>(0h0)) node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) node source_c_bits_legal = or(UInt<1>(0h0), _source_c_bits_legal_T_9) wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect source_c_bits_a.opcode, UInt<1>(0h0) connect source_c_bits_a.param, UInt<1>(0h0) connect source_c_bits_a.size, cam_a[0].bits.size connect source_c_bits_a.source, cam_a[0].bits.source connect source_c_bits_a.address, cam_a[0].bits.address node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) connect source_c_bits_a.mask, _source_c_bits_a_mask_T connect source_c_bits_a.data, amo_data connect source_c_bits_a.corrupt, _source_c_bits_T connect source_c.bits, source_c_bits_a node _decode_T = dshl(UInt<3>(0h7), nodeIn.a.bits.size) node _decode_T_1 = bits(_decode_T, 2, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_1 = mux(opdata, decode, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, nodeOut.a.ready) node _readys_T = cat(source_i.valid, source_c.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 1, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = bits(_readys_T_3, 1, 0) node _readys_T_5 = shl(_readys_T_4, 1) node _readys_T_6 = bits(_readys_T_5, 1, 0) node _readys_T_7 = not(_readys_T_6) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], source_c.valid) node _winner_T_1 = and(readys[1], source_i.valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_3 = eq(winner[0], UInt<1>(0h0)) node _T_4 = or(_T_2, _T_3) node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) node _T_6 = eq(winner[1], UInt<1>(0h0)) node _T_7 = or(_T_5, _T_6) node _T_8 = and(_T_4, _T_7) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_8, UInt<1>(0h1), "") : assert node _T_12 = or(source_c.valid, source_i.valid) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = or(winner[0], winner[1]) node _T_15 = or(_T_13, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) connect source_c.ready, _source_c_ready_T node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) connect source_i.ready, _source_i_ready_T node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) wire _nodeOut_a_valid_WIRE : UInt<1> connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) connect nodeOut.a.valid, _nodeOut_a_valid_T_4 wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) wire _nodeOut_a_bits_WIRE_1 : UInt<1> connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) wire _nodeOut_a_bits_WIRE_2 : UInt<64> connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) wire _nodeOut_a_bits_WIRE_3 : UInt<8> connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 wire _nodeOut_a_bits_WIRE_4 : { } connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 wire _nodeOut_a_bits_WIRE_5 : { } connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) wire _nodeOut_a_bits_WIRE_6 : UInt<29> connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11 connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6 node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) wire _nodeOut_a_bits_WIRE_7 : UInt<12> connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14 connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7 node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) wire _nodeOut_a_bits_WIRE_8 : UInt<2> connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17 connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8 node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) wire _nodeOut_a_bits_WIRE_9 : UInt<3> connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20 connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9 node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) wire _nodeOut_a_bits_WIRE_10 : UInt<3> connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23 connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10 connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode node _T_19 = and(source_i.ready, source_i.valid) node _T_20 = eq(a_isSupported, UInt<1>(0h0)) node _T_21 = and(_T_19, _T_20) when _T_21 : when a_cam_sel_free_0 : connect cam_a[0].fifoId, UInt<1>(0h0) connect cam_a[0].bits, nodeIn.a.bits node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) connect cam_a[0].lut, _cam_a_0_lut_T_6 when a_cam_sel_free_0 : connect cam_s[0].state, UInt<2>(0h3) node _T_22 = and(source_c.ready, source_c.valid) when _T_22 : when a_cam_sel_put_0 : connect cam_s[0].state, UInt<1>(0h1) node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), nodeOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) node _d_cam_sel_bypass_T = eq(nodeOut.d.bits.source, nodeIn.a.bits.source) node _d_cam_sel_bypass_T_1 = and(_d_cam_sel_bypass_T, nodeIn.a.valid) node _d_cam_sel_bypass_T_2 = eq(a_isSupported, UInt<1>(0h0)) node d_cam_sel_bypass = and(_d_cam_sel_bypass_T_1, _d_cam_sel_bypass_T_2) node d_cam_sel_0 = mux(d_cam_sel_bypass, a_cam_sel_free_0, d_cam_sel_match_0) node d_cam_sel_any = or(d_cam_sel_bypass, d_cam_sel_match_0) node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) node _T_24 = and(_T_23, d_first) when _T_24 : node _T_25 = and(d_cam_sel_0, d_ackd) when _T_25 : connect cam_d[0].data, nodeOut.d.bits.data connect cam_d[0].denied, nodeOut.d.bits.denied connect cam_d[0].corrupt, nodeOut.d.bits.corrupt when d_cam_sel_0 : node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) connect cam_s[0].state, _cam_s_0_state_T node _d_drop_T = and(d_first, d_ackd) node d_drop = and(_d_drop_T, d_cam_sel_any) node _d_replace_T = and(d_first, d_ack) node d_replace = and(_d_replace_T, d_cam_sel_match_0) node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) connect nodeIn.d.valid, _nodeIn_d_valid_T_1 node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) connect nodeOut.d.ready, _nodeOut_d_ready_T connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn.d.bits.data, nodeOut.d.bits.data connect nodeIn.d.bits.denied, nodeOut.d.bits.denied connect nodeIn.d.bits.sink, nodeOut.d.bits.sink connect nodeIn.d.bits.source, nodeOut.d.bits.source connect nodeIn.d.bits.size, nodeOut.d.bits.size connect nodeIn.d.bits.param, nodeOut.d.bits.param connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode when d_replace : connect nodeIn.d.bits.opcode, UInt<1>(0h1) connect nodeIn.d.bits.data, cam_d[0].data node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLAtomicAutomata( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_sink = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_denied = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_corrupt = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_sink = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_denied = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_corrupt = 1'h0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _a_canLogical_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canLogical_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canLogical_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canLogical = 1'h0; // @[AtomicAutomata.scala:94:45] wire _a_canArithmetic_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canArithmetic_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canArithmetic_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canArithmetic = 1'h0; // @[AtomicAutomata.scala:95:45] wire decode = 1'h0; // @[Edges.scala:220:59] wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1 = 1'h0; // @[Arbiter.scala:82:69] wire initBeats = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire _nodeIn_d_bits_corrupt_T = 1'h0; // @[AtomicAutomata.scala:248:46] wire _nodeIn_d_bits_denied_T = 1'h0; // @[AtomicAutomata.scala:249:46] wire _a_canLogical_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_canArithmetic_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83] wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60] wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85] wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _source_c_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _source_c_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _source_c_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _source_c_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _source_c_bits_legal_T_9 = 1'h1; // @[Parameters.scala:684:54] wire source_c_bits_legal = 1'h1; // @[Parameters.scala:686:26] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire [1:0] auto_in_d_bits_param = 2'h0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_param = 2'h0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27] wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50] wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [29:0] _a_canLogical_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canLogical_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_6 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_7 = 30'h0; // @[Parameters.scala:137:46] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9] wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9] wire [1:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28] wire [11:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28] wire [28:0] _a_canLogical_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28] wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28] wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28] wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [1:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [11:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [1:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] wire [1:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17] reg [11:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] wire [11:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] _source_c_bits_legal_T_4 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_T = cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24, :172:45] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = ~(\|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44] wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58] wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82] wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire cam_amo_0; // @[AtomicAutomata.scala:87:44] assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44] wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68] assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68] wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56] wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80] wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28] wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49] wire cam_abusy_0 = _cam_abusy_T \| _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}] wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96] wire cam_dmatch_0 = \|cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49] wire [29:0] _a_canLogical_T_2 = {1'h0, _a_canLogical_T_1}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_2 = {1'h0, _a_canArithmetic_T_1}; // @[Parameters.scala:137:{31,41}] wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47] wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47] wire _a_isSupported_T = ~a_isArithmetic; // @[AtomicAutomata.scala:97:47, :98:63] wire a_isSupported = ~a_isLogical & _a_isSupported_T; // @[AtomicAutomata.scala:96:47, :98:{32,63}] wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}] wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}] wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57] wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28] wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42] wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42] wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39] wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25] wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39] wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] \| _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}] wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}] wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29] wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29] wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38] wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}] wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}] wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38] wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}] wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}] wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_2 = signbit_a \| _signext_a_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_5 = _signext_a_T_2 \| _signext_a_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_8 = _signext_a_T_5 \| _signext_a_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17] wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17] wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17] wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17] wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17] wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17] wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17] wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17] wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40] wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40] wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_2 = signbit_d \| _signext_d_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_5 = _signext_d_T_2 \| _signext_d_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_8 = _signext_d_T_5 \| _signext_d_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17] wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17] wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17] wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17] wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17] wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17] wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17] wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17] wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40] wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40] wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40] wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28] wire [63:0] a_a_ext = _a_a_ext_T \| signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}] wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28] wire [63:0] a_d_ext = _a_d_ext_T \| signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}] wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43] wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}] wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33] wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33] wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49] wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35] wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}] wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50] wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}] wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65] wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}] wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}] wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31] wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50] wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}] wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34] wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}] wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17] wire _source_i_ready_T; // @[Arbiter.scala:94:31] wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38] wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28] wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28] wire source_i_ready; // @[AtomicAutomata.scala:154:28] wire source_i_valid; // @[AtomicAutomata.scala:154:28] wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23] wire _a_allow_T_1 = a_isSupported \| cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53] wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}] assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38] assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32] assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32] wire _source_c_ready_T; // @[Arbiter.scala:94:31] wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17] wire source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28] wire [11:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28] wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28] wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28] wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28] wire source_c_ready; // @[AtomicAutomata.scala:165:28] assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17] wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17] assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17] assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10] assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17] assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17] assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [2:0] _source_c_bits_a_mask_sizeOH_T = {1'h0, cam_a_0_bits_size}; // @[Misc.scala:202:34] wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire source_c_bits_a_mask_sub_sub_sub_0_1 = &cam_a_0_bits_size; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 \| _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 \| _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 \| _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 \| _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 \| _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 \| _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 \| _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 \| _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 \| _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 \| _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 \| _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 \| _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10] assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10] wire [5:0] _decode_T = 6'h7 << nodeIn_a_bits_size; // @[package.scala:243:71] wire [2:0] _decode_T_1 = _decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}] reg beatsLeft; // @[Arbiter.scala:60:30] wire idle = ~beatsLeft; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T \| _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = source_c_valid \| source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_1 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}} node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31) node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23) node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0) node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0) node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1) node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2) node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3) node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4) node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5) node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6) node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7) node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8) node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9) node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10) node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11) node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12) node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13) node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14) node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15) node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16) node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17) node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18) node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19) node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20) node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21) node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22) node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23) node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24) node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25) node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26) node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27) node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28) node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29) node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30) node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31) node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32) node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33) node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34) node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35) node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36) node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37) node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38) node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39) node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40) node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41) node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42) node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43) node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist) node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn) node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2) node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3) node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn) node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T) connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1 node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn) connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T) connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1 node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T) node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn) node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2) connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3 node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6) node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T) node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2) node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3) node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0) node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5) node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0) node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7) node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31) node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23) node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0) node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0) node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1) node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2) node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3) node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4) node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5) node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6) node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7) node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8) node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9) node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10) node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11) node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12) node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13) node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14) node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15) node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16) node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17) node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18) node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19) node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20) node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21) node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22) node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23) node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24) node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25) node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26) node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27) node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28) node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29) node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30) node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31) node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32) node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33) node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34) node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35) node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36) node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37) node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38) node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39) node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40) node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41) node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42) node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43) node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist) node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn) node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2) node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3) node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn) node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7) node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T) connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1 node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn) connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T) connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1 node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T) node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn) node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2) connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3 node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6) node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T) node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2) node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3) node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0) node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5) node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0) node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7) node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31) node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23) node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0) node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0) node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1) node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2) node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3) node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4) node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5) node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6) node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7) node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8) node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9) node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10) node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11) node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12) node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13) node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14) node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15) node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16) node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17) node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18) node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19) node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20) node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21) node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22) node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23) node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24) node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25) node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26) node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27) node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28) node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29) node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30) node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31) node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32) node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33) node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34) node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35) node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36) node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37) node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38) node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39) node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40) node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41) node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42) node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43) node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist) node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn) node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2) node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3) node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn) node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7) node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T) connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1 node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn) connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T) connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1 node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T) node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn) node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2) connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3 node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6) node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T) node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2) node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3) node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0) node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5) node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0) node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7) inst io_out_d_m1_resizer of RecFNToRecFN_150 connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_m2_resizer of RecFNToRecFN_151 connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1) inst io_out_d_muladder of MulAddRecFN_e8_s24_65 connect io_out_d_muladder.io.op, UInt<1>(0h0) connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out connect io_out_d_muladder.io.c, io_out_d_self_rec wire io_out_d_out : { bits : UInt<32>} node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23) node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6) node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7) node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T) connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1 node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6) node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1) connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2 connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32) connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp) connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T) node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0) node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2) connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3 node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0) node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T) node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1) node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1) node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist) node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0) node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0) node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81)) node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1) node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2) node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf) node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5) node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0) node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T) node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1) node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut) node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut) connect io_out_d_out.bits, _io_out_d_out_bits_T connect io.out_d, io_out_d_out

module MacUnit_1( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [31:0] io_in_a_bits, // @[PE.scala:16:14] input [31:0] io_in_b_bits, // @[PE.scala:16:14] input [31:0] io_in_c_bits, // @[PE.scala:16:14] output [31:0] io_out_d_bits // @[PE.scala:16:14] ); wire io_out_d_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_d_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _io_out_d_muladder_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _io_out_d_m2_resizer_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _io_out_d_m1_resizer_io_out; // @[Arithmetic.scala:362:32] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:14:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:14:7] wire [31:0] io_in_c_bits_0 = io_in_c_bits; // @[PE.scala:14:7] wire [31:0] io_out_d_out_bits; // @[Arithmetic.scala:387:23] wire [31:0] io_out_d_bits_0; // @[PE.scala:14:7] wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] | _io_out_d_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] | _io_out_d_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_d_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_d_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_d_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] | _io_out_d_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] assign io_out_d_bits_0 = io_out_d_out_bits; // @[PE.scala:14:7] wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_d_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_d_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_d_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_d_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN | io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 | _io_out_d_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_d_out_bits = _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12] RecFNToRecFN_150 io_out_d_m1_resizer ( // @[Arithmetic.scala:362:32] .io_in (io_out_d_m1_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m1_resizer_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_151 io_out_d_m2_resizer ( // @[Arithmetic.scala:369:32] .io_in (io_out_d_m2_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_m2_resizer_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_65 io_out_d_muladder ( // @[Arithmetic.scala:376:30] .io_a (_io_out_d_m1_resizer_io_out), // @[Arithmetic.scala:362:32] .io_b (_io_out_d_m2_resizer_io_out), // @[Arithmetic.scala:369:32] .io_c (io_out_d_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_io_out_d_muladder_io_out) ); // @[Arithmetic.scala:376:30] assign io_out_d_bits = io_out_d_bits_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_14 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `1` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `0` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8]}} regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire in_arb_reqs : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}[3] wire in_arb_vals : UInt<1>[3] node in_arb_filter_hi = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[2], in_arb_vals[1]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_vals[0]) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = mux(_in_arb_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _in_arb_filter_T_12 = mux(_in_arb_filter_T_9, UInt<6>(0h10), _in_arb_filter_T_11) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_8, UInt<6>(0h8), _in_arb_filter_T_12) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_7, UInt<6>(0h4), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_6, UInt<6>(0h2), _in_arb_filter_T_14) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<6>(0h1), _in_arb_filter_T_15) node _in_arb_sel_T = bits(in_arb_filter, 2, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 3) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) when _T_1 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = bits(in_arb_sel, 0, 0) node _mask_T_4 = bits(in_arb_sel, 1, 1) node _mask_T_5 = bits(in_arb_sel, 2, 2) node _mask_T_6 = mux(_mask_T_3, _mask_T, UInt<1>(0h0)) node _mask_T_7 = mux(_mask_T_4, _mask_T_1, UInt<1>(0h0)) node _mask_T_8 = mux(_mask_T_5, _mask_T_2, UInt<1>(0h0)) node _mask_T_9 = or(_mask_T_6, _mask_T_7) node _mask_T_10 = or(_mask_T_9, _mask_T_8) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_10 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T) connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1 node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T) connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1 node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T) connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1 node _in_arb_reqs_0_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_5_T_1 = and(io.req.`0`.bits.vc_sel.`0`[5], _in_arb_reqs_0_0_5_T) connect in_arb_reqs[0].`0`[5], _in_arb_reqs_0_0_5_T_1 node _in_arb_reqs_0_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_6_T_1 = and(io.req.`0`.bits.vc_sel.`0`[6], _in_arb_reqs_0_0_6_T) connect in_arb_reqs[0].`0`[6], _in_arb_reqs_0_0_6_T_1 node _in_arb_reqs_0_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_7_T_1 = and(io.req.`0`.bits.vc_sel.`0`[7], _in_arb_reqs_0_0_7_T) connect in_arb_reqs[0].`0`[7], _in_arb_reqs_0_0_7_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T) connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1 node _in_arb_reqs_0_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_2_T_1 = and(io.req.`0`.bits.vc_sel.`1`[2], _in_arb_reqs_0_1_2_T) connect in_arb_reqs[0].`1`[2], _in_arb_reqs_0_1_2_T_1 node _in_arb_reqs_0_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_3_T_1 = and(io.req.`0`.bits.vc_sel.`1`[3], _in_arb_reqs_0_1_3_T) connect in_arb_reqs[0].`1`[3], _in_arb_reqs_0_1_3_T_1 node _in_arb_reqs_0_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_4_T_1 = and(io.req.`0`.bits.vc_sel.`1`[4], _in_arb_reqs_0_1_4_T) connect in_arb_reqs[0].`1`[4], _in_arb_reqs_0_1_4_T_1 node _in_arb_reqs_0_1_5_T = eq(io.channel_status.`1`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_5_T_1 = and(io.req.`0`.bits.vc_sel.`1`[5], _in_arb_reqs_0_1_5_T) connect in_arb_reqs[0].`1`[5], _in_arb_reqs_0_1_5_T_1 node _in_arb_reqs_0_1_6_T = eq(io.channel_status.`1`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_6_T_1 = and(io.req.`0`.bits.vc_sel.`1`[6], _in_arb_reqs_0_1_6_T) connect in_arb_reqs[0].`1`[6], _in_arb_reqs_0_1_6_T_1 node _in_arb_reqs_0_1_7_T = eq(io.channel_status.`1`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_7_T_1 = and(io.req.`0`.bits.vc_sel.`1`[7], _in_arb_reqs_0_1_7_T) connect in_arb_reqs[0].`1`[7], _in_arb_reqs_0_1_7_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_reqs_0_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_1_T_1 = and(io.req.`0`.bits.vc_sel.`2`[1], _in_arb_reqs_0_2_1_T) connect in_arb_reqs[0].`2`[1], _in_arb_reqs_0_2_1_T_1 node _in_arb_reqs_0_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_2_T_1 = and(io.req.`0`.bits.vc_sel.`2`[2], _in_arb_reqs_0_2_2_T) connect in_arb_reqs[0].`2`[2], _in_arb_reqs_0_2_2_T_1 node _in_arb_reqs_0_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_3_T_1 = and(io.req.`0`.bits.vc_sel.`2`[3], _in_arb_reqs_0_2_3_T) connect in_arb_reqs[0].`2`[3], _in_arb_reqs_0_2_3_T_1 node _in_arb_reqs_0_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_4_T_1 = and(io.req.`0`.bits.vc_sel.`2`[4], _in_arb_reqs_0_2_4_T) connect in_arb_reqs[0].`2`[4], _in_arb_reqs_0_2_4_T_1 node _in_arb_reqs_0_2_5_T = eq(io.channel_status.`2`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_5_T_1 = and(io.req.`0`.bits.vc_sel.`2`[5], _in_arb_reqs_0_2_5_T) connect in_arb_reqs[0].`2`[5], _in_arb_reqs_0_2_5_T_1 node _in_arb_reqs_0_2_6_T = eq(io.channel_status.`2`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_6_T_1 = and(io.req.`0`.bits.vc_sel.`2`[6], _in_arb_reqs_0_2_6_T) connect in_arb_reqs[0].`2`[6], _in_arb_reqs_0_2_6_T_1 node _in_arb_reqs_0_2_7_T = eq(io.channel_status.`2`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_7_T_1 = and(io.req.`0`.bits.vc_sel.`2`[7], _in_arb_reqs_0_2_7_T) connect in_arb_reqs[0].`2`[7], _in_arb_reqs_0_2_7_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3]) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4]) node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`0`[5]) node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`0`[6]) node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`0`[7]) node _in_arb_vals_0_T_7 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1]) node _in_arb_vals_0_T_8 = or(_in_arb_vals_0_T_7, in_arb_reqs[0].`1`[2]) node _in_arb_vals_0_T_9 = or(_in_arb_vals_0_T_8, in_arb_reqs[0].`1`[3]) node _in_arb_vals_0_T_10 = or(_in_arb_vals_0_T_9, in_arb_reqs[0].`1`[4]) node _in_arb_vals_0_T_11 = or(_in_arb_vals_0_T_10, in_arb_reqs[0].`1`[5]) node _in_arb_vals_0_T_12 = or(_in_arb_vals_0_T_11, in_arb_reqs[0].`1`[6]) node _in_arb_vals_0_T_13 = or(_in_arb_vals_0_T_12, in_arb_reqs[0].`1`[7]) node _in_arb_vals_0_T_14 = or(in_arb_reqs[0].`2`[0], in_arb_reqs[0].`2`[1]) node _in_arb_vals_0_T_15 = or(_in_arb_vals_0_T_14, in_arb_reqs[0].`2`[2]) node _in_arb_vals_0_T_16 = or(_in_arb_vals_0_T_15, in_arb_reqs[0].`2`[3]) node _in_arb_vals_0_T_17 = or(_in_arb_vals_0_T_16, in_arb_reqs[0].`2`[4]) node _in_arb_vals_0_T_18 = or(_in_arb_vals_0_T_17, in_arb_reqs[0].`2`[5]) node _in_arb_vals_0_T_19 = or(_in_arb_vals_0_T_18, in_arb_reqs[0].`2`[6]) node _in_arb_vals_0_T_20 = or(_in_arb_vals_0_T_19, in_arb_reqs[0].`2`[7]) node _in_arb_vals_0_T_21 = or(_in_arb_vals_0_T_6, _in_arb_vals_0_T_13) node _in_arb_vals_0_T_22 = or(_in_arb_vals_0_T_21, _in_arb_vals_0_T_20) node _in_arb_vals_0_T_23 = and(io.req.`0`.valid, _in_arb_vals_0_T_22) connect in_arb_vals[0], _in_arb_vals_0_T_23 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T) connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1 node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T) connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1 node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T) connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1 node _in_arb_reqs_1_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_5_T_1 = and(io.req.`1`.bits.vc_sel.`0`[5], _in_arb_reqs_1_0_5_T) connect in_arb_reqs[1].`0`[5], _in_arb_reqs_1_0_5_T_1 node _in_arb_reqs_1_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_6_T_1 = and(io.req.`1`.bits.vc_sel.`0`[6], _in_arb_reqs_1_0_6_T) connect in_arb_reqs[1].`0`[6], _in_arb_reqs_1_0_6_T_1 node _in_arb_reqs_1_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_7_T_1 = and(io.req.`1`.bits.vc_sel.`0`[7], _in_arb_reqs_1_0_7_T) connect in_arb_reqs[1].`0`[7], _in_arb_reqs_1_0_7_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T) connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1 node _in_arb_reqs_1_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_2_T_1 = and(io.req.`1`.bits.vc_sel.`1`[2], _in_arb_reqs_1_1_2_T) connect in_arb_reqs[1].`1`[2], _in_arb_reqs_1_1_2_T_1 node _in_arb_reqs_1_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_3_T_1 = and(io.req.`1`.bits.vc_sel.`1`[3], _in_arb_reqs_1_1_3_T) connect in_arb_reqs[1].`1`[3], _in_arb_reqs_1_1_3_T_1 node _in_arb_reqs_1_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_4_T_1 = and(io.req.`1`.bits.vc_sel.`1`[4], _in_arb_reqs_1_1_4_T) connect in_arb_reqs[1].`1`[4], _in_arb_reqs_1_1_4_T_1 node _in_arb_reqs_1_1_5_T = eq(io.channel_status.`1`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_5_T_1 = and(io.req.`1`.bits.vc_sel.`1`[5], _in_arb_reqs_1_1_5_T) connect in_arb_reqs[1].`1`[5], _in_arb_reqs_1_1_5_T_1 node _in_arb_reqs_1_1_6_T = eq(io.channel_status.`1`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_6_T_1 = and(io.req.`1`.bits.vc_sel.`1`[6], _in_arb_reqs_1_1_6_T) connect in_arb_reqs[1].`1`[6], _in_arb_reqs_1_1_6_T_1 node _in_arb_reqs_1_1_7_T = eq(io.channel_status.`1`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_7_T_1 = and(io.req.`1`.bits.vc_sel.`1`[7], _in_arb_reqs_1_1_7_T) connect in_arb_reqs[1].`1`[7], _in_arb_reqs_1_1_7_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_reqs_1_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_1_T_1 = and(io.req.`1`.bits.vc_sel.`2`[1], _in_arb_reqs_1_2_1_T) connect in_arb_reqs[1].`2`[1], _in_arb_reqs_1_2_1_T_1 node _in_arb_reqs_1_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_2_T_1 = and(io.req.`1`.bits.vc_sel.`2`[2], _in_arb_reqs_1_2_2_T) connect in_arb_reqs[1].`2`[2], _in_arb_reqs_1_2_2_T_1 node _in_arb_reqs_1_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_3_T_1 = and(io.req.`1`.bits.vc_sel.`2`[3], _in_arb_reqs_1_2_3_T) connect in_arb_reqs[1].`2`[3], _in_arb_reqs_1_2_3_T_1 node _in_arb_reqs_1_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_4_T_1 = and(io.req.`1`.bits.vc_sel.`2`[4], _in_arb_reqs_1_2_4_T) connect in_arb_reqs[1].`2`[4], _in_arb_reqs_1_2_4_T_1 node _in_arb_reqs_1_2_5_T = eq(io.channel_status.`2`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_5_T_1 = and(io.req.`1`.bits.vc_sel.`2`[5], _in_arb_reqs_1_2_5_T) connect in_arb_reqs[1].`2`[5], _in_arb_reqs_1_2_5_T_1 node _in_arb_reqs_1_2_6_T = eq(io.channel_status.`2`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_6_T_1 = and(io.req.`1`.bits.vc_sel.`2`[6], _in_arb_reqs_1_2_6_T) connect in_arb_reqs[1].`2`[6], _in_arb_reqs_1_2_6_T_1 node _in_arb_reqs_1_2_7_T = eq(io.channel_status.`2`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_7_T_1 = and(io.req.`1`.bits.vc_sel.`2`[7], _in_arb_reqs_1_2_7_T) connect in_arb_reqs[1].`2`[7], _in_arb_reqs_1_2_7_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3]) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4]) node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`0`[5]) node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`0`[6]) node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`0`[7]) node _in_arb_vals_1_T_7 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1]) node _in_arb_vals_1_T_8 = or(_in_arb_vals_1_T_7, in_arb_reqs[1].`1`[2]) node _in_arb_vals_1_T_9 = or(_in_arb_vals_1_T_8, in_arb_reqs[1].`1`[3]) node _in_arb_vals_1_T_10 = or(_in_arb_vals_1_T_9, in_arb_reqs[1].`1`[4]) node _in_arb_vals_1_T_11 = or(_in_arb_vals_1_T_10, in_arb_reqs[1].`1`[5]) node _in_arb_vals_1_T_12 = or(_in_arb_vals_1_T_11, in_arb_reqs[1].`1`[6]) node _in_arb_vals_1_T_13 = or(_in_arb_vals_1_T_12, in_arb_reqs[1].`1`[7]) node _in_arb_vals_1_T_14 = or(in_arb_reqs[1].`2`[0], in_arb_reqs[1].`2`[1]) node _in_arb_vals_1_T_15 = or(_in_arb_vals_1_T_14, in_arb_reqs[1].`2`[2]) node _in_arb_vals_1_T_16 = or(_in_arb_vals_1_T_15, in_arb_reqs[1].`2`[3]) node _in_arb_vals_1_T_17 = or(_in_arb_vals_1_T_16, in_arb_reqs[1].`2`[4]) node _in_arb_vals_1_T_18 = or(_in_arb_vals_1_T_17, in_arb_reqs[1].`2`[5]) node _in_arb_vals_1_T_19 = or(_in_arb_vals_1_T_18, in_arb_reqs[1].`2`[6]) node _in_arb_vals_1_T_20 = or(_in_arb_vals_1_T_19, in_arb_reqs[1].`2`[7]) node _in_arb_vals_1_T_21 = or(_in_arb_vals_1_T_6, _in_arb_vals_1_T_13) node _in_arb_vals_1_T_22 = or(_in_arb_vals_1_T_21, _in_arb_vals_1_T_20) node _in_arb_vals_1_T_23 = and(io.req.`1`.valid, _in_arb_vals_1_T_22) connect in_arb_vals[1], _in_arb_vals_1_T_23 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T) connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1 node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T) connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1 node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T) connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1 node _in_arb_reqs_2_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_5_T_1 = and(io.req.`2`.bits.vc_sel.`0`[5], _in_arb_reqs_2_0_5_T) connect in_arb_reqs[2].`0`[5], _in_arb_reqs_2_0_5_T_1 node _in_arb_reqs_2_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_6_T_1 = and(io.req.`2`.bits.vc_sel.`0`[6], _in_arb_reqs_2_0_6_T) connect in_arb_reqs[2].`0`[6], _in_arb_reqs_2_0_6_T_1 node _in_arb_reqs_2_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_7_T_1 = and(io.req.`2`.bits.vc_sel.`0`[7], _in_arb_reqs_2_0_7_T) connect in_arb_reqs[2].`0`[7], _in_arb_reqs_2_0_7_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T) connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1 node _in_arb_reqs_2_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_2_T_1 = and(io.req.`2`.bits.vc_sel.`1`[2], _in_arb_reqs_2_1_2_T) connect in_arb_reqs[2].`1`[2], _in_arb_reqs_2_1_2_T_1 node _in_arb_reqs_2_1_3_T = eq(io.channel_status.`1`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_3_T_1 = and(io.req.`2`.bits.vc_sel.`1`[3], _in_arb_reqs_2_1_3_T) connect in_arb_reqs[2].`1`[3], _in_arb_reqs_2_1_3_T_1 node _in_arb_reqs_2_1_4_T = eq(io.channel_status.`1`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_4_T_1 = and(io.req.`2`.bits.vc_sel.`1`[4], _in_arb_reqs_2_1_4_T) connect in_arb_reqs[2].`1`[4], _in_arb_reqs_2_1_4_T_1 node _in_arb_reqs_2_1_5_T = eq(io.channel_status.`1`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_5_T_1 = and(io.req.`2`.bits.vc_sel.`1`[5], _in_arb_reqs_2_1_5_T) connect in_arb_reqs[2].`1`[5], _in_arb_reqs_2_1_5_T_1 node _in_arb_reqs_2_1_6_T = eq(io.channel_status.`1`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_6_T_1 = and(io.req.`2`.bits.vc_sel.`1`[6], _in_arb_reqs_2_1_6_T) connect in_arb_reqs[2].`1`[6], _in_arb_reqs_2_1_6_T_1 node _in_arb_reqs_2_1_7_T = eq(io.channel_status.`1`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_7_T_1 = and(io.req.`2`.bits.vc_sel.`1`[7], _in_arb_reqs_2_1_7_T) connect in_arb_reqs[2].`1`[7], _in_arb_reqs_2_1_7_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_reqs_2_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_1_T_1 = and(io.req.`2`.bits.vc_sel.`2`[1], _in_arb_reqs_2_2_1_T) connect in_arb_reqs[2].`2`[1], _in_arb_reqs_2_2_1_T_1 node _in_arb_reqs_2_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_2_T_1 = and(io.req.`2`.bits.vc_sel.`2`[2], _in_arb_reqs_2_2_2_T) connect in_arb_reqs[2].`2`[2], _in_arb_reqs_2_2_2_T_1 node _in_arb_reqs_2_2_3_T = eq(io.channel_status.`2`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_3_T_1 = and(io.req.`2`.bits.vc_sel.`2`[3], _in_arb_reqs_2_2_3_T) connect in_arb_reqs[2].`2`[3], _in_arb_reqs_2_2_3_T_1 node _in_arb_reqs_2_2_4_T = eq(io.channel_status.`2`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_4_T_1 = and(io.req.`2`.bits.vc_sel.`2`[4], _in_arb_reqs_2_2_4_T) connect in_arb_reqs[2].`2`[4], _in_arb_reqs_2_2_4_T_1 node _in_arb_reqs_2_2_5_T = eq(io.channel_status.`2`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_5_T_1 = and(io.req.`2`.bits.vc_sel.`2`[5], _in_arb_reqs_2_2_5_T) connect in_arb_reqs[2].`2`[5], _in_arb_reqs_2_2_5_T_1 node _in_arb_reqs_2_2_6_T = eq(io.channel_status.`2`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_6_T_1 = and(io.req.`2`.bits.vc_sel.`2`[6], _in_arb_reqs_2_2_6_T) connect in_arb_reqs[2].`2`[6], _in_arb_reqs_2_2_6_T_1 node _in_arb_reqs_2_2_7_T = eq(io.channel_status.`2`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_7_T_1 = and(io.req.`2`.bits.vc_sel.`2`[7], _in_arb_reqs_2_2_7_T) connect in_arb_reqs[2].`2`[7], _in_arb_reqs_2_2_7_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3]) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4]) node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`0`[5]) node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`0`[6]) node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`0`[7]) node _in_arb_vals_2_T_7 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1]) node _in_arb_vals_2_T_8 = or(_in_arb_vals_2_T_7, in_arb_reqs[2].`1`[2]) node _in_arb_vals_2_T_9 = or(_in_arb_vals_2_T_8, in_arb_reqs[2].`1`[3]) node _in_arb_vals_2_T_10 = or(_in_arb_vals_2_T_9, in_arb_reqs[2].`1`[4]) node _in_arb_vals_2_T_11 = or(_in_arb_vals_2_T_10, in_arb_reqs[2].`1`[5]) node _in_arb_vals_2_T_12 = or(_in_arb_vals_2_T_11, in_arb_reqs[2].`1`[6]) node _in_arb_vals_2_T_13 = or(_in_arb_vals_2_T_12, in_arb_reqs[2].`1`[7]) node _in_arb_vals_2_T_14 = or(in_arb_reqs[2].`2`[0], in_arb_reqs[2].`2`[1]) node _in_arb_vals_2_T_15 = or(_in_arb_vals_2_T_14, in_arb_reqs[2].`2`[2]) node _in_arb_vals_2_T_16 = or(_in_arb_vals_2_T_15, in_arb_reqs[2].`2`[3]) node _in_arb_vals_2_T_17 = or(_in_arb_vals_2_T_16, in_arb_reqs[2].`2`[4]) node _in_arb_vals_2_T_18 = or(_in_arb_vals_2_T_17, in_arb_reqs[2].`2`[5]) node _in_arb_vals_2_T_19 = or(_in_arb_vals_2_T_18, in_arb_reqs[2].`2`[6]) node _in_arb_vals_2_T_20 = or(_in_arb_vals_2_T_19, in_arb_reqs[2].`2`[7]) node _in_arb_vals_2_T_21 = or(_in_arb_vals_2_T_6, _in_arb_vals_2_T_13) node _in_arb_vals_2_T_22 = or(_in_arb_vals_2_T_21, _in_arb_vals_2_T_20) node _in_arb_vals_2_T_23 = and(io.req.`2`.valid, _in_arb_vals_2_T_22) connect in_arb_vals[2], _in_arb_vals_2_T_23 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) wire in_alloc : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _in_flow_T_3 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_4 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = or(_in_flow_T_3, _in_flow_T_4) node _in_flow_T_7 = or(_in_flow_T_6, _in_flow_T_5) wire _in_flow_WIRE : UInt<2> connect _in_flow_WIRE, _in_flow_T_7 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_8 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_9 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_10 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_11 = or(_in_flow_T_8, _in_flow_T_9) node _in_flow_T_12 = or(_in_flow_T_11, _in_flow_T_10) wire _in_flow_WIRE_1 : UInt<5> connect _in_flow_WIRE_1, _in_flow_T_12 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_13 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_15 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_16 = or(_in_flow_T_13, _in_flow_T_14) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_15) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_17 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_21 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_22 = or(_in_flow_T_21, _in_flow_T_20) wire _in_flow_WIRE_3 : UInt<5> connect _in_flow_WIRE_3, _in_flow_T_22 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_23 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_24 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_25 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_26 = or(_in_flow_T_23, _in_flow_T_24) node _in_flow_T_27 = or(_in_flow_T_26, _in_flow_T_25) wire _in_flow_WIRE_4 : UInt<3> connect _in_flow_WIRE_4, _in_flow_T_27 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_4 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = or(_in_vc_T_3, _in_vc_T_4) node _in_vc_T_7 = or(_in_vc_T_6, _in_vc_T_5) wire in_vc : UInt<3> connect in_vc, _in_vc_T_7 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) wire in_vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _in_vc_sel_WIRE : UInt<1>[8] node _in_vc_sel_T_3 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_4 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = or(_in_vc_sel_T_3, _in_vc_sel_T_4) node _in_vc_sel_T_7 = or(_in_vc_sel_T_6, _in_vc_sel_T_5) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_7 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_8 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_9 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_10 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_11 = or(_in_vc_sel_T_8, _in_vc_sel_T_9) node _in_vc_sel_T_12 = or(_in_vc_sel_T_11, _in_vc_sel_T_10) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_12 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 node _in_vc_sel_T_13 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_15 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_16 = or(_in_vc_sel_T_13, _in_vc_sel_T_14) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_15) wire _in_vc_sel_WIRE_3 : UInt<1> connect _in_vc_sel_WIRE_3, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3 node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_21 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_22 = or(_in_vc_sel_T_21, _in_vc_sel_T_20) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_22 connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4 node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_25 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_26 = or(_in_vc_sel_T_23, _in_vc_sel_T_24) node _in_vc_sel_T_27 = or(_in_vc_sel_T_26, _in_vc_sel_T_25) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_27 connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5 node _in_vc_sel_T_28 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_29 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_30 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_31 = or(_in_vc_sel_T_28, _in_vc_sel_T_29) node _in_vc_sel_T_32 = or(_in_vc_sel_T_31, _in_vc_sel_T_30) wire _in_vc_sel_WIRE_6 : UInt<1> connect _in_vc_sel_WIRE_6, _in_vc_sel_T_32 connect _in_vc_sel_WIRE[5], _in_vc_sel_WIRE_6 node _in_vc_sel_T_33 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_33, _in_vc_sel_T_34) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_37 connect _in_vc_sel_WIRE[6], _in_vc_sel_WIRE_7 node _in_vc_sel_T_38 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_39 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_40 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_41 = or(_in_vc_sel_T_38, _in_vc_sel_T_39) node _in_vc_sel_T_42 = or(_in_vc_sel_T_41, _in_vc_sel_T_40) wire _in_vc_sel_WIRE_8 : UInt<1> connect _in_vc_sel_WIRE_8, _in_vc_sel_T_42 connect _in_vc_sel_WIRE[7], _in_vc_sel_WIRE_8 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_9 : UInt<1>[8] node _in_vc_sel_T_43 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_44 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_45 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_46 = or(_in_vc_sel_T_43, _in_vc_sel_T_44) node _in_vc_sel_T_47 = or(_in_vc_sel_T_46, _in_vc_sel_T_45) wire _in_vc_sel_WIRE_10 : UInt<1> connect _in_vc_sel_WIRE_10, _in_vc_sel_T_47 connect _in_vc_sel_WIRE_9[0], _in_vc_sel_WIRE_10 node _in_vc_sel_T_48 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_49 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_50 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_51 = or(_in_vc_sel_T_48, _in_vc_sel_T_49) node _in_vc_sel_T_52 = or(_in_vc_sel_T_51, _in_vc_sel_T_50) wire _in_vc_sel_WIRE_11 : UInt<1> connect _in_vc_sel_WIRE_11, _in_vc_sel_T_52 connect _in_vc_sel_WIRE_9[1], _in_vc_sel_WIRE_11 node _in_vc_sel_T_53 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[2], UInt<1>(0h0)) node _in_vc_sel_T_54 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[2], UInt<1>(0h0)) node _in_vc_sel_T_55 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[2], UInt<1>(0h0)) node _in_vc_sel_T_56 = or(_in_vc_sel_T_53, _in_vc_sel_T_54) node _in_vc_sel_T_57 = or(_in_vc_sel_T_56, _in_vc_sel_T_55) wire _in_vc_sel_WIRE_12 : UInt<1> connect _in_vc_sel_WIRE_12, _in_vc_sel_T_57 connect _in_vc_sel_WIRE_9[2], _in_vc_sel_WIRE_12 node _in_vc_sel_T_58 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[3], UInt<1>(0h0)) node _in_vc_sel_T_59 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[3], UInt<1>(0h0)) node _in_vc_sel_T_60 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[3], UInt<1>(0h0)) node _in_vc_sel_T_61 = or(_in_vc_sel_T_58, _in_vc_sel_T_59) node _in_vc_sel_T_62 = or(_in_vc_sel_T_61, _in_vc_sel_T_60) wire _in_vc_sel_WIRE_13 : UInt<1> connect _in_vc_sel_WIRE_13, _in_vc_sel_T_62 connect _in_vc_sel_WIRE_9[3], _in_vc_sel_WIRE_13 node _in_vc_sel_T_63 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[4], UInt<1>(0h0)) node _in_vc_sel_T_64 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[4], UInt<1>(0h0)) node _in_vc_sel_T_65 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[4], UInt<1>(0h0)) node _in_vc_sel_T_66 = or(_in_vc_sel_T_63, _in_vc_sel_T_64) node _in_vc_sel_T_67 = or(_in_vc_sel_T_66, _in_vc_sel_T_65) wire _in_vc_sel_WIRE_14 : UInt<1> connect _in_vc_sel_WIRE_14, _in_vc_sel_T_67 connect _in_vc_sel_WIRE_9[4], _in_vc_sel_WIRE_14 node _in_vc_sel_T_68 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[5], UInt<1>(0h0)) node _in_vc_sel_T_69 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[5], UInt<1>(0h0)) node _in_vc_sel_T_70 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[5], UInt<1>(0h0)) node _in_vc_sel_T_71 = or(_in_vc_sel_T_68, _in_vc_sel_T_69) node _in_vc_sel_T_72 = or(_in_vc_sel_T_71, _in_vc_sel_T_70) wire _in_vc_sel_WIRE_15 : UInt<1> connect _in_vc_sel_WIRE_15, _in_vc_sel_T_72 connect _in_vc_sel_WIRE_9[5], _in_vc_sel_WIRE_15 node _in_vc_sel_T_73 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[6], UInt<1>(0h0)) node _in_vc_sel_T_74 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[6], UInt<1>(0h0)) node _in_vc_sel_T_75 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[6], UInt<1>(0h0)) node _in_vc_sel_T_76 = or(_in_vc_sel_T_73, _in_vc_sel_T_74) node _in_vc_sel_T_77 = or(_in_vc_sel_T_76, _in_vc_sel_T_75) wire _in_vc_sel_WIRE_16 : UInt<1> connect _in_vc_sel_WIRE_16, _in_vc_sel_T_77 connect _in_vc_sel_WIRE_9[6], _in_vc_sel_WIRE_16 node _in_vc_sel_T_78 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[7], UInt<1>(0h0)) node _in_vc_sel_T_79 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[7], UInt<1>(0h0)) node _in_vc_sel_T_80 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[7], UInt<1>(0h0)) node _in_vc_sel_T_81 = or(_in_vc_sel_T_78, _in_vc_sel_T_79) node _in_vc_sel_T_82 = or(_in_vc_sel_T_81, _in_vc_sel_T_80) wire _in_vc_sel_WIRE_17 : UInt<1> connect _in_vc_sel_WIRE_17, _in_vc_sel_T_82 connect _in_vc_sel_WIRE_9[7], _in_vc_sel_WIRE_17 connect in_vc_sel.`1`, _in_vc_sel_WIRE_9 wire _in_vc_sel_WIRE_18 : UInt<1>[8] node _in_vc_sel_T_83 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_84 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_85 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_86 = or(_in_vc_sel_T_83, _in_vc_sel_T_84) node _in_vc_sel_T_87 = or(_in_vc_sel_T_86, _in_vc_sel_T_85) wire _in_vc_sel_WIRE_19 : UInt<1> connect _in_vc_sel_WIRE_19, _in_vc_sel_T_87 connect _in_vc_sel_WIRE_18[0], _in_vc_sel_WIRE_19 node _in_vc_sel_T_88 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_89 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_90 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_91 = or(_in_vc_sel_T_88, _in_vc_sel_T_89) node _in_vc_sel_T_92 = or(_in_vc_sel_T_91, _in_vc_sel_T_90) wire _in_vc_sel_WIRE_20 : UInt<1> connect _in_vc_sel_WIRE_20, _in_vc_sel_T_92 connect _in_vc_sel_WIRE_18[1], _in_vc_sel_WIRE_20 node _in_vc_sel_T_93 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[2], UInt<1>(0h0)) node _in_vc_sel_T_94 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[2], UInt<1>(0h0)) node _in_vc_sel_T_95 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[2], UInt<1>(0h0)) node _in_vc_sel_T_96 = or(_in_vc_sel_T_93, _in_vc_sel_T_94) node _in_vc_sel_T_97 = or(_in_vc_sel_T_96, _in_vc_sel_T_95) wire _in_vc_sel_WIRE_21 : UInt<1> connect _in_vc_sel_WIRE_21, _in_vc_sel_T_97 connect _in_vc_sel_WIRE_18[2], _in_vc_sel_WIRE_21 node _in_vc_sel_T_98 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[3], UInt<1>(0h0)) node _in_vc_sel_T_99 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[3], UInt<1>(0h0)) node _in_vc_sel_T_100 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[3], UInt<1>(0h0)) node _in_vc_sel_T_101 = or(_in_vc_sel_T_98, _in_vc_sel_T_99) node _in_vc_sel_T_102 = or(_in_vc_sel_T_101, _in_vc_sel_T_100) wire _in_vc_sel_WIRE_22 : UInt<1> connect _in_vc_sel_WIRE_22, _in_vc_sel_T_102 connect _in_vc_sel_WIRE_18[3], _in_vc_sel_WIRE_22 node _in_vc_sel_T_103 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[4], UInt<1>(0h0)) node _in_vc_sel_T_104 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[4], UInt<1>(0h0)) node _in_vc_sel_T_105 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[4], UInt<1>(0h0)) node _in_vc_sel_T_106 = or(_in_vc_sel_T_103, _in_vc_sel_T_104) node _in_vc_sel_T_107 = or(_in_vc_sel_T_106, _in_vc_sel_T_105) wire _in_vc_sel_WIRE_23 : UInt<1> connect _in_vc_sel_WIRE_23, _in_vc_sel_T_107 connect _in_vc_sel_WIRE_18[4], _in_vc_sel_WIRE_23 node _in_vc_sel_T_108 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[5], UInt<1>(0h0)) node _in_vc_sel_T_109 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[5], UInt<1>(0h0)) node _in_vc_sel_T_110 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[5], UInt<1>(0h0)) node _in_vc_sel_T_111 = or(_in_vc_sel_T_108, _in_vc_sel_T_109) node _in_vc_sel_T_112 = or(_in_vc_sel_T_111, _in_vc_sel_T_110) wire _in_vc_sel_WIRE_24 : UInt<1> connect _in_vc_sel_WIRE_24, _in_vc_sel_T_112 connect _in_vc_sel_WIRE_18[5], _in_vc_sel_WIRE_24 node _in_vc_sel_T_113 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[6], UInt<1>(0h0)) node _in_vc_sel_T_114 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[6], UInt<1>(0h0)) node _in_vc_sel_T_115 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[6], UInt<1>(0h0)) node _in_vc_sel_T_116 = or(_in_vc_sel_T_113, _in_vc_sel_T_114) node _in_vc_sel_T_117 = or(_in_vc_sel_T_116, _in_vc_sel_T_115) wire _in_vc_sel_WIRE_25 : UInt<1> connect _in_vc_sel_WIRE_25, _in_vc_sel_T_117 connect _in_vc_sel_WIRE_18[6], _in_vc_sel_WIRE_25 node _in_vc_sel_T_118 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[7], UInt<1>(0h0)) node _in_vc_sel_T_119 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[7], UInt<1>(0h0)) node _in_vc_sel_T_120 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[7], UInt<1>(0h0)) node _in_vc_sel_T_121 = or(_in_vc_sel_T_118, _in_vc_sel_T_119) node _in_vc_sel_T_122 = or(_in_vc_sel_T_121, _in_vc_sel_T_120) wire _in_vc_sel_WIRE_26 : UInt<1> connect _in_vc_sel_WIRE_26, _in_vc_sel_T_122 connect _in_vc_sel_WIRE_18[7], _in_vc_sel_WIRE_26 connect in_vc_sel.`2`, _in_vc_sel_WIRE_18 node _T_2 = or(in_arb_vals[0], in_arb_vals[1]) node _T_3 = or(_T_2, in_arb_vals[2]) node hi = bits(in_arb_sel, 2, 2) node lo = bits(in_arb_sel, 1, 0) node _T_4 = orr(hi) node _T_5 = or(hi, lo) node _T_6 = bits(_T_5, 1, 1) node _T_7 = cat(_T_4, _T_6) node _T_8 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_9 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_10 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_11 = or(_T_8, _T_9) node _T_12 = or(_T_11, _T_10) node lo_lo = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node lo_hi = cat(in_vc_sel.`0`[3], in_vc_sel.`0`[2]) node lo_1 = cat(lo_hi, lo_lo) node hi_lo = cat(in_vc_sel.`0`[5], in_vc_sel.`0`[4]) node hi_hi = cat(in_vc_sel.`0`[7], in_vc_sel.`0`[6]) node hi_1 = cat(hi_hi, hi_lo) node _T_13 = cat(hi_1, lo_1) node lo_lo_1 = cat(in_vc_sel.`1`[1], in_vc_sel.`1`[0]) node lo_hi_1 = cat(in_vc_sel.`1`[3], in_vc_sel.`1`[2]) node lo_2 = cat(lo_hi_1, lo_lo_1) node hi_lo_1 = cat(in_vc_sel.`1`[5], in_vc_sel.`1`[4]) node hi_hi_1 = cat(in_vc_sel.`1`[7], in_vc_sel.`1`[6]) node hi_2 = cat(hi_hi_1, hi_lo_1) node _T_14 = cat(hi_2, lo_2) node lo_lo_2 = cat(in_vc_sel.`2`[1], in_vc_sel.`2`[0]) node lo_hi_2 = cat(in_vc_sel.`2`[3], in_vc_sel.`2`[2]) node lo_3 = cat(lo_hi_2, lo_lo_2) node hi_lo_2 = cat(in_vc_sel.`2`[5], in_vc_sel.`2`[4]) node hi_hi_2 = cat(in_vc_sel.`2`[7], in_vc_sel.`2`[6]) node hi_3 = cat(hi_hi_2, hi_lo_2) node _T_15 = cat(hi_3, lo_3) node hi_4 = cat(_T_15, _T_14) node _T_16 = cat(hi_4, _T_13) regreset mask_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_16, _full_T) node full = cat(_T_16, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = bits(full, 10, 10) node _oh_T_11 = bits(full, 11, 11) node _oh_T_12 = bits(full, 12, 12) node _oh_T_13 = bits(full, 13, 13) node _oh_T_14 = bits(full, 14, 14) node _oh_T_15 = bits(full, 15, 15) node _oh_T_16 = bits(full, 16, 16) node _oh_T_17 = bits(full, 17, 17) node _oh_T_18 = bits(full, 18, 18) node _oh_T_19 = bits(full, 19, 19) node _oh_T_20 = bits(full, 20, 20) node _oh_T_21 = bits(full, 21, 21) node _oh_T_22 = bits(full, 22, 22) node _oh_T_23 = bits(full, 23, 23) node _oh_T_24 = bits(full, 24, 24) node _oh_T_25 = bits(full, 25, 25) node _oh_T_26 = bits(full, 26, 26) node _oh_T_27 = bits(full, 27, 27) node _oh_T_28 = bits(full, 28, 28) node _oh_T_29 = bits(full, 29, 29) node _oh_T_30 = bits(full, 30, 30) node _oh_T_31 = bits(full, 31, 31) node _oh_T_32 = bits(full, 32, 32) node _oh_T_33 = bits(full, 33, 33) node _oh_T_34 = bits(full, 34, 34) node _oh_T_35 = bits(full, 35, 35) node _oh_T_36 = bits(full, 36, 36) node _oh_T_37 = bits(full, 37, 37) node _oh_T_38 = bits(full, 38, 38) node _oh_T_39 = bits(full, 39, 39) node _oh_T_40 = bits(full, 40, 40) node _oh_T_41 = bits(full, 41, 41) node _oh_T_42 = bits(full, 42, 42) node _oh_T_43 = bits(full, 43, 43) node _oh_T_44 = bits(full, 44, 44) node _oh_T_45 = bits(full, 45, 45) node _oh_T_46 = bits(full, 46, 46) node _oh_T_47 = bits(full, 47, 47) node _oh_T_48 = mux(_oh_T_47, UInt<48>(0h800000000000), UInt<48>(0h0)) node _oh_T_49 = mux(_oh_T_46, UInt<48>(0h400000000000), _oh_T_48) node _oh_T_50 = mux(_oh_T_45, UInt<48>(0h200000000000), _oh_T_49) node _oh_T_51 = mux(_oh_T_44, UInt<48>(0h100000000000), _oh_T_50) node _oh_T_52 = mux(_oh_T_43, UInt<48>(0h80000000000), _oh_T_51) node _oh_T_53 = mux(_oh_T_42, UInt<48>(0h40000000000), _oh_T_52) node _oh_T_54 = mux(_oh_T_41, UInt<48>(0h20000000000), _oh_T_53) node _oh_T_55 = mux(_oh_T_40, UInt<48>(0h10000000000), _oh_T_54) node _oh_T_56 = mux(_oh_T_39, UInt<48>(0h8000000000), _oh_T_55) node _oh_T_57 = mux(_oh_T_38, UInt<48>(0h4000000000), _oh_T_56) node _oh_T_58 = mux(_oh_T_37, UInt<48>(0h2000000000), _oh_T_57) node _oh_T_59 = mux(_oh_T_36, UInt<48>(0h1000000000), _oh_T_58) node _oh_T_60 = mux(_oh_T_35, UInt<48>(0h800000000), _oh_T_59) node _oh_T_61 = mux(_oh_T_34, UInt<48>(0h400000000), _oh_T_60) node _oh_T_62 = mux(_oh_T_33, UInt<48>(0h200000000), _oh_T_61) node _oh_T_63 = mux(_oh_T_32, UInt<48>(0h100000000), _oh_T_62) node _oh_T_64 = mux(_oh_T_31, UInt<48>(0h80000000), _oh_T_63) node _oh_T_65 = mux(_oh_T_30, UInt<48>(0h40000000), _oh_T_64) node _oh_T_66 = mux(_oh_T_29, UInt<48>(0h20000000), _oh_T_65) node _oh_T_67 = mux(_oh_T_28, UInt<48>(0h10000000), _oh_T_66) node _oh_T_68 = mux(_oh_T_27, UInt<48>(0h8000000), _oh_T_67) node _oh_T_69 = mux(_oh_T_26, UInt<48>(0h4000000), _oh_T_68) node _oh_T_70 = mux(_oh_T_25, UInt<48>(0h2000000), _oh_T_69) node _oh_T_71 = mux(_oh_T_24, UInt<48>(0h1000000), _oh_T_70) node _oh_T_72 = mux(_oh_T_23, UInt<48>(0h800000), _oh_T_71) node _oh_T_73 = mux(_oh_T_22, UInt<48>(0h400000), _oh_T_72) node _oh_T_74 = mux(_oh_T_21, UInt<48>(0h200000), _oh_T_73) node _oh_T_75 = mux(_oh_T_20, UInt<48>(0h100000), _oh_T_74) node _oh_T_76 = mux(_oh_T_19, UInt<48>(0h80000), _oh_T_75) node _oh_T_77 = mux(_oh_T_18, UInt<48>(0h40000), _oh_T_76) node _oh_T_78 = mux(_oh_T_17, UInt<48>(0h20000), _oh_T_77) node _oh_T_79 = mux(_oh_T_16, UInt<48>(0h10000), _oh_T_78) node _oh_T_80 = mux(_oh_T_15, UInt<48>(0h8000), _oh_T_79) node _oh_T_81 = mux(_oh_T_14, UInt<48>(0h4000), _oh_T_80) node _oh_T_82 = mux(_oh_T_13, UInt<48>(0h2000), _oh_T_81) node _oh_T_83 = mux(_oh_T_12, UInt<48>(0h1000), _oh_T_82) node _oh_T_84 = mux(_oh_T_11, UInt<48>(0h800), _oh_T_83) node _oh_T_85 = mux(_oh_T_10, UInt<48>(0h400), _oh_T_84) node _oh_T_86 = mux(_oh_T_9, UInt<48>(0h200), _oh_T_85) node _oh_T_87 = mux(_oh_T_8, UInt<48>(0h100), _oh_T_86) node _oh_T_88 = mux(_oh_T_7, UInt<48>(0h80), _oh_T_87) node _oh_T_89 = mux(_oh_T_6, UInt<48>(0h40), _oh_T_88) node _oh_T_90 = mux(_oh_T_5, UInt<48>(0h20), _oh_T_89) node _oh_T_91 = mux(_oh_T_4, UInt<48>(0h10), _oh_T_90) node _oh_T_92 = mux(_oh_T_3, UInt<48>(0h8), _oh_T_91) node _oh_T_93 = mux(_oh_T_2, UInt<48>(0h4), _oh_T_92) node _oh_T_94 = mux(_oh_T_1, UInt<48>(0h2), _oh_T_93) node oh = mux(_oh_T, UInt<48>(0h1), _oh_T_94) node _sel_T = bits(oh, 23, 0) node _sel_T_1 = shr(oh, 24) node sel = or(_sel_T, _sel_T_1) when _T_12 : node _mask_T_11 = bits(sel, 0, 0) node _mask_T_12 = not(UInt<1>(0h0)) node _mask_T_13 = bits(sel, 1, 1) node _mask_T_14 = not(UInt<2>(0h0)) node _mask_T_15 = bits(sel, 2, 2) node _mask_T_16 = not(UInt<3>(0h0)) node _mask_T_17 = bits(sel, 3, 3) node _mask_T_18 = not(UInt<4>(0h0)) node _mask_T_19 = bits(sel, 4, 4) node _mask_T_20 = not(UInt<5>(0h0)) node _mask_T_21 = bits(sel, 5, 5) node _mask_T_22 = not(UInt<6>(0h0)) node _mask_T_23 = bits(sel, 6, 6) node _mask_T_24 = not(UInt<7>(0h0)) node _mask_T_25 = bits(sel, 7, 7) node _mask_T_26 = not(UInt<8>(0h0)) node _mask_T_27 = bits(sel, 8, 8) node _mask_T_28 = not(UInt<9>(0h0)) node _mask_T_29 = bits(sel, 9, 9) node _mask_T_30 = not(UInt<10>(0h0)) node _mask_T_31 = bits(sel, 10, 10) node _mask_T_32 = not(UInt<11>(0h0)) node _mask_T_33 = bits(sel, 11, 11) node _mask_T_34 = not(UInt<12>(0h0)) node _mask_T_35 = bits(sel, 12, 12) node _mask_T_36 = not(UInt<13>(0h0)) node _mask_T_37 = bits(sel, 13, 13) node _mask_T_38 = not(UInt<14>(0h0)) node _mask_T_39 = bits(sel, 14, 14) node _mask_T_40 = not(UInt<15>(0h0)) node _mask_T_41 = bits(sel, 15, 15) node _mask_T_42 = not(UInt<16>(0h0)) node _mask_T_43 = bits(sel, 16, 16) node _mask_T_44 = not(UInt<17>(0h0)) node _mask_T_45 = bits(sel, 17, 17) node _mask_T_46 = not(UInt<18>(0h0)) node _mask_T_47 = bits(sel, 18, 18) node _mask_T_48 = not(UInt<19>(0h0)) node _mask_T_49 = bits(sel, 19, 19) node _mask_T_50 = not(UInt<20>(0h0)) node _mask_T_51 = bits(sel, 20, 20) node _mask_T_52 = not(UInt<21>(0h0)) node _mask_T_53 = bits(sel, 21, 21) node _mask_T_54 = not(UInt<22>(0h0)) node _mask_T_55 = bits(sel, 22, 22) node _mask_T_56 = not(UInt<23>(0h0)) node _mask_T_57 = bits(sel, 23, 23) node _mask_T_58 = not(UInt<24>(0h0)) node _mask_T_59 = mux(_mask_T_57, _mask_T_58, UInt<1>(0h0)) node _mask_T_60 = mux(_mask_T_55, _mask_T_56, _mask_T_59) node _mask_T_61 = mux(_mask_T_53, _mask_T_54, _mask_T_60) node _mask_T_62 = mux(_mask_T_51, _mask_T_52, _mask_T_61) node _mask_T_63 = mux(_mask_T_49, _mask_T_50, _mask_T_62) node _mask_T_64 = mux(_mask_T_47, _mask_T_48, _mask_T_63) node _mask_T_65 = mux(_mask_T_45, _mask_T_46, _mask_T_64) node _mask_T_66 = mux(_mask_T_43, _mask_T_44, _mask_T_65) node _mask_T_67 = mux(_mask_T_41, _mask_T_42, _mask_T_66) node _mask_T_68 = mux(_mask_T_39, _mask_T_40, _mask_T_67) node _mask_T_69 = mux(_mask_T_37, _mask_T_38, _mask_T_68) node _mask_T_70 = mux(_mask_T_35, _mask_T_36, _mask_T_69) node _mask_T_71 = mux(_mask_T_33, _mask_T_34, _mask_T_70) node _mask_T_72 = mux(_mask_T_31, _mask_T_32, _mask_T_71) node _mask_T_73 = mux(_mask_T_29, _mask_T_30, _mask_T_72) node _mask_T_74 = mux(_mask_T_27, _mask_T_28, _mask_T_73) node _mask_T_75 = mux(_mask_T_25, _mask_T_26, _mask_T_74) node _mask_T_76 = mux(_mask_T_23, _mask_T_24, _mask_T_75) node _mask_T_77 = mux(_mask_T_21, _mask_T_22, _mask_T_76) node _mask_T_78 = mux(_mask_T_19, _mask_T_20, _mask_T_77) node _mask_T_79 = mux(_mask_T_17, _mask_T_18, _mask_T_78) node _mask_T_80 = mux(_mask_T_15, _mask_T_16, _mask_T_79) node _mask_T_81 = mux(_mask_T_13, _mask_T_14, _mask_T_80) node _mask_T_82 = mux(_mask_T_11, _mask_T_12, _mask_T_81) connect mask_1, _mask_T_82 wire _WIRE : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _WIRE_1 : UInt<24> connect _WIRE_1, sel node _T_17 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_17 node _T_18 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_18 node _T_19 = bits(_WIRE_1, 2, 2) connect _WIRE.`0`[2], _T_19 node _T_20 = bits(_WIRE_1, 3, 3) connect _WIRE.`0`[3], _T_20 node _T_21 = bits(_WIRE_1, 4, 4) connect _WIRE.`0`[4], _T_21 node _T_22 = bits(_WIRE_1, 5, 5) connect _WIRE.`0`[5], _T_22 node _T_23 = bits(_WIRE_1, 6, 6) connect _WIRE.`0`[6], _T_23 node _T_24 = bits(_WIRE_1, 7, 7) connect _WIRE.`0`[7], _T_24 node _T_25 = bits(_WIRE_1, 8, 8) connect _WIRE.`1`[0], _T_25 node _T_26 = bits(_WIRE_1, 9, 9) connect _WIRE.`1`[1], _T_26 node _T_27 = bits(_WIRE_1, 10, 10) connect _WIRE.`1`[2], _T_27 node _T_28 = bits(_WIRE_1, 11, 11) connect _WIRE.`1`[3], _T_28 node _T_29 = bits(_WIRE_1, 12, 12) connect _WIRE.`1`[4], _T_29 node _T_30 = bits(_WIRE_1, 13, 13) connect _WIRE.`1`[5], _T_30 node _T_31 = bits(_WIRE_1, 14, 14) connect _WIRE.`1`[6], _T_31 node _T_32 = bits(_WIRE_1, 15, 15) connect _WIRE.`1`[7], _T_32 node _T_33 = bits(_WIRE_1, 16, 16) connect _WIRE.`2`[0], _T_33 node _T_34 = bits(_WIRE_1, 17, 17) connect _WIRE.`2`[1], _T_34 node _T_35 = bits(_WIRE_1, 18, 18) connect _WIRE.`2`[2], _T_35 node _T_36 = bits(_WIRE_1, 19, 19) connect _WIRE.`2`[3], _T_36 node _T_37 = bits(_WIRE_1, 20, 20) connect _WIRE.`2`[4], _T_37 node _T_38 = bits(_WIRE_1, 21, 21) connect _WIRE.`2`[5], _T_38 node _T_39 = bits(_WIRE_1, 22, 22) connect _WIRE.`2`[6], _T_39 node _T_40 = bits(_WIRE_1, 23, 23) connect _WIRE.`2`[7], _T_40 wire _WIRE_2 : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`0`[2], UInt<1>(0h0) connect _WIRE_2.`0`[3], UInt<1>(0h0) connect _WIRE_2.`0`[4], UInt<1>(0h0) connect _WIRE_2.`0`[5], UInt<1>(0h0) connect _WIRE_2.`0`[6], UInt<1>(0h0) connect _WIRE_2.`0`[7], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`1`[1], UInt<1>(0h0) connect _WIRE_2.`1`[2], UInt<1>(0h0) connect _WIRE_2.`1`[3], UInt<1>(0h0) connect _WIRE_2.`1`[4], UInt<1>(0h0) connect _WIRE_2.`1`[5], UInt<1>(0h0) connect _WIRE_2.`1`[6], UInt<1>(0h0) connect _WIRE_2.`1`[7], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) connect _WIRE_2.`2`[1], UInt<1>(0h0) connect _WIRE_2.`2`[2], UInt<1>(0h0) connect _WIRE_2.`2`[3], UInt<1>(0h0) connect _WIRE_2.`2`[4], UInt<1>(0h0) connect _WIRE_2.`2`[5], UInt<1>(0h0) connect _WIRE_2.`2`[6], UInt<1>(0h0) connect _WIRE_2.`2`[7], UInt<1>(0h0) node _T_41 = mux(_T_3, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_41.`0` connect in_alloc.`1`, _T_41.`1` connect in_alloc.`2`, _T_41.`2` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`0`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`0`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`0`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`0`.vc_sel.`1`[2], in_alloc.`1`[2] connect io.resp.`0`.vc_sel.`1`[3], in_alloc.`1`[3] connect io.resp.`0`.vc_sel.`1`[4], in_alloc.`1`[4] connect io.resp.`0`.vc_sel.`1`[5], in_alloc.`1`[5] connect io.resp.`0`.vc_sel.`1`[6], in_alloc.`1`[6] connect io.resp.`0`.vc_sel.`1`[7], in_alloc.`1`[7] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`0`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`0`.vc_sel.`2`[2], in_alloc.`2`[2] connect io.resp.`0`.vc_sel.`2`[3], in_alloc.`2`[3] connect io.resp.`0`.vc_sel.`2`[4], in_alloc.`2`[4] connect io.resp.`0`.vc_sel.`2`[5], in_alloc.`2`[5] connect io.resp.`0`.vc_sel.`2`[6], in_alloc.`2`[6] connect io.resp.`0`.vc_sel.`2`[7], in_alloc.`2`[7] node lo_lo_3 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node lo_hi_3 = cat(io.resp.`0`.vc_sel.`0`[3], io.resp.`0`.vc_sel.`0`[2]) node lo_4 = cat(lo_hi_3, lo_lo_3) node hi_lo_3 = cat(io.resp.`0`.vc_sel.`0`[5], io.resp.`0`.vc_sel.`0`[4]) node hi_hi_3 = cat(io.resp.`0`.vc_sel.`0`[7], io.resp.`0`.vc_sel.`0`[6]) node hi_5 = cat(hi_hi_3, hi_lo_3) node _T_42 = cat(hi_5, lo_4) node lo_lo_4 = cat(io.resp.`0`.vc_sel.`1`[1], io.resp.`0`.vc_sel.`1`[0]) node lo_hi_4 = cat(io.resp.`0`.vc_sel.`1`[3], io.resp.`0`.vc_sel.`1`[2]) node lo_5 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(io.resp.`0`.vc_sel.`1`[5], io.resp.`0`.vc_sel.`1`[4]) node hi_hi_4 = cat(io.resp.`0`.vc_sel.`1`[7], io.resp.`0`.vc_sel.`1`[6]) node hi_6 = cat(hi_hi_4, hi_lo_4) node _T_43 = cat(hi_6, lo_5) node lo_lo_5 = cat(io.resp.`0`.vc_sel.`2`[1], io.resp.`0`.vc_sel.`2`[0]) node lo_hi_5 = cat(io.resp.`0`.vc_sel.`2`[3], io.resp.`0`.vc_sel.`2`[2]) node lo_6 = cat(lo_hi_5, lo_lo_5) node hi_lo_5 = cat(io.resp.`0`.vc_sel.`2`[5], io.resp.`0`.vc_sel.`2`[4]) node hi_hi_5 = cat(io.resp.`0`.vc_sel.`2`[7], io.resp.`0`.vc_sel.`2`[6]) node hi_7 = cat(hi_hi_5, hi_lo_5) node _T_44 = cat(hi_7, lo_6) node hi_8 = cat(_T_44, _T_43) node _T_45 = cat(hi_8, _T_42) node _T_46 = bits(_T_45, 0, 0) node _T_47 = bits(_T_45, 1, 1) node _T_48 = bits(_T_45, 2, 2) node _T_49 = bits(_T_45, 3, 3) node _T_50 = bits(_T_45, 4, 4) node _T_51 = bits(_T_45, 5, 5) node _T_52 = bits(_T_45, 6, 6) node _T_53 = bits(_T_45, 7, 7) node _T_54 = bits(_T_45, 8, 8) node _T_55 = bits(_T_45, 9, 9) node _T_56 = bits(_T_45, 10, 10) node _T_57 = bits(_T_45, 11, 11) node _T_58 = bits(_T_45, 12, 12) node _T_59 = bits(_T_45, 13, 13) node _T_60 = bits(_T_45, 14, 14) node _T_61 = bits(_T_45, 15, 15) node _T_62 = bits(_T_45, 16, 16) node _T_63 = bits(_T_45, 17, 17) node _T_64 = bits(_T_45, 18, 18) node _T_65 = bits(_T_45, 19, 19) node _T_66 = bits(_T_45, 20, 20) node _T_67 = bits(_T_45, 21, 21) node _T_68 = bits(_T_45, 22, 22) node _T_69 = bits(_T_45, 23, 23) node _T_70 = add(_T_47, _T_48) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(_T_46, _T_71) node _T_73 = bits(_T_72, 1, 0) node _T_74 = add(_T_50, _T_51) node _T_75 = bits(_T_74, 1, 0) node _T_76 = add(_T_49, _T_75) node _T_77 = bits(_T_76, 1, 0) node _T_78 = add(_T_73, _T_77) node _T_79 = bits(_T_78, 2, 0) node _T_80 = add(_T_53, _T_54) node _T_81 = bits(_T_80, 1, 0) node _T_82 = add(_T_52, _T_81) node _T_83 = bits(_T_82, 1, 0) node _T_84 = add(_T_56, _T_57) node _T_85 = bits(_T_84, 1, 0) node _T_86 = add(_T_55, _T_85) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(_T_83, _T_87) node _T_89 = bits(_T_88, 2, 0) node _T_90 = add(_T_79, _T_89) node _T_91 = bits(_T_90, 3, 0) node _T_92 = add(_T_59, _T_60) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_58, _T_93) node _T_95 = bits(_T_94, 1, 0) node _T_96 = add(_T_62, _T_63) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_61, _T_97) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_95, _T_99) node _T_101 = bits(_T_100, 2, 0) node _T_102 = add(_T_65, _T_66) node _T_103 = bits(_T_102, 1, 0) node _T_104 = add(_T_64, _T_103) node _T_105 = bits(_T_104, 1, 0) node _T_106 = add(_T_68, _T_69) node _T_107 = bits(_T_106, 1, 0) node _T_108 = add(_T_67, _T_107) node _T_109 = bits(_T_108, 1, 0) node _T_110 = add(_T_105, _T_109) node _T_111 = bits(_T_110, 2, 0) node _T_112 = add(_T_101, _T_111) node _T_113 = bits(_T_112, 3, 0) node _T_114 = add(_T_91, _T_113) node _T_115 = bits(_T_114, 4, 0) node _T_116 = leq(_T_115, UInt<1>(0h1)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_116, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`1`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`1`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`1`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`1`.vc_sel.`1`[2], in_alloc.`1`[2] connect io.resp.`1`.vc_sel.`1`[3], in_alloc.`1`[3] connect io.resp.`1`.vc_sel.`1`[4], in_alloc.`1`[4] connect io.resp.`1`.vc_sel.`1`[5], in_alloc.`1`[5] connect io.resp.`1`.vc_sel.`1`[6], in_alloc.`1`[6] connect io.resp.`1`.vc_sel.`1`[7], in_alloc.`1`[7] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`1`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`1`.vc_sel.`2`[2], in_alloc.`2`[2] connect io.resp.`1`.vc_sel.`2`[3], in_alloc.`2`[3] connect io.resp.`1`.vc_sel.`2`[4], in_alloc.`2`[4] connect io.resp.`1`.vc_sel.`2`[5], in_alloc.`2`[5] connect io.resp.`1`.vc_sel.`2`[6], in_alloc.`2`[6] connect io.resp.`1`.vc_sel.`2`[7], in_alloc.`2`[7] node lo_lo_6 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node lo_hi_6 = cat(io.resp.`1`.vc_sel.`0`[3], io.resp.`1`.vc_sel.`0`[2]) node lo_7 = cat(lo_hi_6, lo_lo_6) node hi_lo_6 = cat(io.resp.`1`.vc_sel.`0`[5], io.resp.`1`.vc_sel.`0`[4]) node hi_hi_6 = cat(io.resp.`1`.vc_sel.`0`[7], io.resp.`1`.vc_sel.`0`[6]) node hi_9 = cat(hi_hi_6, hi_lo_6) node _T_120 = cat(hi_9, lo_7) node lo_lo_7 = cat(io.resp.`1`.vc_sel.`1`[1], io.resp.`1`.vc_sel.`1`[0]) node lo_hi_7 = cat(io.resp.`1`.vc_sel.`1`[3], io.resp.`1`.vc_sel.`1`[2]) node lo_8 = cat(lo_hi_7, lo_lo_7) node hi_lo_7 = cat(io.resp.`1`.vc_sel.`1`[5], io.resp.`1`.vc_sel.`1`[4]) node hi_hi_7 = cat(io.resp.`1`.vc_sel.`1`[7], io.resp.`1`.vc_sel.`1`[6]) node hi_10 = cat(hi_hi_7, hi_lo_7) node _T_121 = cat(hi_10, lo_8) node lo_lo_8 = cat(io.resp.`1`.vc_sel.`2`[1], io.resp.`1`.vc_sel.`2`[0]) node lo_hi_8 = cat(io.resp.`1`.vc_sel.`2`[3], io.resp.`1`.vc_sel.`2`[2]) node lo_9 = cat(lo_hi_8, lo_lo_8) node hi_lo_8 = cat(io.resp.`1`.vc_sel.`2`[5], io.resp.`1`.vc_sel.`2`[4]) node hi_hi_8 = cat(io.resp.`1`.vc_sel.`2`[7], io.resp.`1`.vc_sel.`2`[6]) node hi_11 = cat(hi_hi_8, hi_lo_8) node _T_122 = cat(hi_11, lo_9) node hi_12 = cat(_T_122, _T_121) node _T_123 = cat(hi_12, _T_120) node _T_124 = bits(_T_123, 0, 0) node _T_125 = bits(_T_123, 1, 1) node _T_126 = bits(_T_123, 2, 2) node _T_127 = bits(_T_123, 3, 3) node _T_128 = bits(_T_123, 4, 4) node _T_129 = bits(_T_123, 5, 5) node _T_130 = bits(_T_123, 6, 6) node _T_131 = bits(_T_123, 7, 7) node _T_132 = bits(_T_123, 8, 8) node _T_133 = bits(_T_123, 9, 9) node _T_134 = bits(_T_123, 10, 10) node _T_135 = bits(_T_123, 11, 11) node _T_136 = bits(_T_123, 12, 12) node _T_137 = bits(_T_123, 13, 13) node _T_138 = bits(_T_123, 14, 14) node _T_139 = bits(_T_123, 15, 15) node _T_140 = bits(_T_123, 16, 16) node _T_141 = bits(_T_123, 17, 17) node _T_142 = bits(_T_123, 18, 18) node _T_143 = bits(_T_123, 19, 19) node _T_144 = bits(_T_123, 20, 20) node _T_145 = bits(_T_123, 21, 21) node _T_146 = bits(_T_123, 22, 22) node _T_147 = bits(_T_123, 23, 23) node _T_148 = add(_T_125, _T_126) node _T_149 = bits(_T_148, 1, 0) node _T_150 = add(_T_124, _T_149) node _T_151 = bits(_T_150, 1, 0) node _T_152 = add(_T_128, _T_129) node _T_153 = bits(_T_152, 1, 0) node _T_154 = add(_T_127, _T_153) node _T_155 = bits(_T_154, 1, 0) node _T_156 = add(_T_151, _T_155) node _T_157 = bits(_T_156, 2, 0) node _T_158 = add(_T_131, _T_132) node _T_159 = bits(_T_158, 1, 0) node _T_160 = add(_T_130, _T_159) node _T_161 = bits(_T_160, 1, 0) node _T_162 = add(_T_134, _T_135) node _T_163 = bits(_T_162, 1, 0) node _T_164 = add(_T_133, _T_163) node _T_165 = bits(_T_164, 1, 0) node _T_166 = add(_T_161, _T_165) node _T_167 = bits(_T_166, 2, 0) node _T_168 = add(_T_157, _T_167) node _T_169 = bits(_T_168, 3, 0) node _T_170 = add(_T_137, _T_138) node _T_171 = bits(_T_170, 1, 0) node _T_172 = add(_T_136, _T_171) node _T_173 = bits(_T_172, 1, 0) node _T_174 = add(_T_140, _T_141) node _T_175 = bits(_T_174, 1, 0) node _T_176 = add(_T_139, _T_175) node _T_177 = bits(_T_176, 1, 0) node _T_178 = add(_T_173, _T_177) node _T_179 = bits(_T_178, 2, 0) node _T_180 = add(_T_143, _T_144) node _T_181 = bits(_T_180, 1, 0) node _T_182 = add(_T_142, _T_181) node _T_183 = bits(_T_182, 1, 0) node _T_184 = add(_T_146, _T_147) node _T_185 = bits(_T_184, 1, 0) node _T_186 = add(_T_145, _T_185) node _T_187 = bits(_T_186, 1, 0) node _T_188 = add(_T_183, _T_187) node _T_189 = bits(_T_188, 2, 0) node _T_190 = add(_T_179, _T_189) node _T_191 = bits(_T_190, 3, 0) node _T_192 = add(_T_169, _T_191) node _T_193 = bits(_T_192, 4, 0) node _T_194 = leq(_T_193, UInt<1>(0h1)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_194, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`2`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`2`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`2`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`2`.vc_sel.`1`[2], in_alloc.`1`[2] connect io.resp.`2`.vc_sel.`1`[3], in_alloc.`1`[3] connect io.resp.`2`.vc_sel.`1`[4], in_alloc.`1`[4] connect io.resp.`2`.vc_sel.`1`[5], in_alloc.`1`[5] connect io.resp.`2`.vc_sel.`1`[6], in_alloc.`1`[6] connect io.resp.`2`.vc_sel.`1`[7], in_alloc.`1`[7] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`2`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`2`.vc_sel.`2`[2], in_alloc.`2`[2] connect io.resp.`2`.vc_sel.`2`[3], in_alloc.`2`[3] connect io.resp.`2`.vc_sel.`2`[4], in_alloc.`2`[4] connect io.resp.`2`.vc_sel.`2`[5], in_alloc.`2`[5] connect io.resp.`2`.vc_sel.`2`[6], in_alloc.`2`[6] connect io.resp.`2`.vc_sel.`2`[7], in_alloc.`2`[7] node lo_lo_9 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node lo_hi_9 = cat(io.resp.`2`.vc_sel.`0`[3], io.resp.`2`.vc_sel.`0`[2]) node lo_10 = cat(lo_hi_9, lo_lo_9) node hi_lo_9 = cat(io.resp.`2`.vc_sel.`0`[5], io.resp.`2`.vc_sel.`0`[4]) node hi_hi_9 = cat(io.resp.`2`.vc_sel.`0`[7], io.resp.`2`.vc_sel.`0`[6]) node hi_13 = cat(hi_hi_9, hi_lo_9) node _T_198 = cat(hi_13, lo_10) node lo_lo_10 = cat(io.resp.`2`.vc_sel.`1`[1], io.resp.`2`.vc_sel.`1`[0]) node lo_hi_10 = cat(io.resp.`2`.vc_sel.`1`[3], io.resp.`2`.vc_sel.`1`[2]) node lo_11 = cat(lo_hi_10, lo_lo_10) node hi_lo_10 = cat(io.resp.`2`.vc_sel.`1`[5], io.resp.`2`.vc_sel.`1`[4]) node hi_hi_10 = cat(io.resp.`2`.vc_sel.`1`[7], io.resp.`2`.vc_sel.`1`[6]) node hi_14 = cat(hi_hi_10, hi_lo_10) node _T_199 = cat(hi_14, lo_11) node lo_lo_11 = cat(io.resp.`2`.vc_sel.`2`[1], io.resp.`2`.vc_sel.`2`[0]) node lo_hi_11 = cat(io.resp.`2`.vc_sel.`2`[3], io.resp.`2`.vc_sel.`2`[2]) node lo_12 = cat(lo_hi_11, lo_lo_11) node hi_lo_11 = cat(io.resp.`2`.vc_sel.`2`[5], io.resp.`2`.vc_sel.`2`[4]) node hi_hi_11 = cat(io.resp.`2`.vc_sel.`2`[7], io.resp.`2`.vc_sel.`2`[6]) node hi_15 = cat(hi_hi_11, hi_lo_11) node _T_200 = cat(hi_15, lo_12) node hi_16 = cat(_T_200, _T_199) node _T_201 = cat(hi_16, _T_198) node _T_202 = bits(_T_201, 0, 0) node _T_203 = bits(_T_201, 1, 1) node _T_204 = bits(_T_201, 2, 2) node _T_205 = bits(_T_201, 3, 3) node _T_206 = bits(_T_201, 4, 4) node _T_207 = bits(_T_201, 5, 5) node _T_208 = bits(_T_201, 6, 6) node _T_209 = bits(_T_201, 7, 7) node _T_210 = bits(_T_201, 8, 8) node _T_211 = bits(_T_201, 9, 9) node _T_212 = bits(_T_201, 10, 10) node _T_213 = bits(_T_201, 11, 11) node _T_214 = bits(_T_201, 12, 12) node _T_215 = bits(_T_201, 13, 13) node _T_216 = bits(_T_201, 14, 14) node _T_217 = bits(_T_201, 15, 15) node _T_218 = bits(_T_201, 16, 16) node _T_219 = bits(_T_201, 17, 17) node _T_220 = bits(_T_201, 18, 18) node _T_221 = bits(_T_201, 19, 19) node _T_222 = bits(_T_201, 20, 20) node _T_223 = bits(_T_201, 21, 21) node _T_224 = bits(_T_201, 22, 22) node _T_225 = bits(_T_201, 23, 23) node _T_226 = add(_T_203, _T_204) node _T_227 = bits(_T_226, 1, 0) node _T_228 = add(_T_202, _T_227) node _T_229 = bits(_T_228, 1, 0) node _T_230 = add(_T_206, _T_207) node _T_231 = bits(_T_230, 1, 0) node _T_232 = add(_T_205, _T_231) node _T_233 = bits(_T_232, 1, 0) node _T_234 = add(_T_229, _T_233) node _T_235 = bits(_T_234, 2, 0) node _T_236 = add(_T_209, _T_210) node _T_237 = bits(_T_236, 1, 0) node _T_238 = add(_T_208, _T_237) node _T_239 = bits(_T_238, 1, 0) node _T_240 = add(_T_212, _T_213) node _T_241 = bits(_T_240, 1, 0) node _T_242 = add(_T_211, _T_241) node _T_243 = bits(_T_242, 1, 0) node _T_244 = add(_T_239, _T_243) node _T_245 = bits(_T_244, 2, 0) node _T_246 = add(_T_235, _T_245) node _T_247 = bits(_T_246, 3, 0) node _T_248 = add(_T_215, _T_216) node _T_249 = bits(_T_248, 1, 0) node _T_250 = add(_T_214, _T_249) node _T_251 = bits(_T_250, 1, 0) node _T_252 = add(_T_218, _T_219) node _T_253 = bits(_T_252, 1, 0) node _T_254 = add(_T_217, _T_253) node _T_255 = bits(_T_254, 1, 0) node _T_256 = add(_T_251, _T_255) node _T_257 = bits(_T_256, 2, 0) node _T_258 = add(_T_221, _T_222) node _T_259 = bits(_T_258, 1, 0) node _T_260 = add(_T_220, _T_259) node _T_261 = bits(_T_260, 1, 0) node _T_262 = add(_T_224, _T_225) node _T_263 = bits(_T_262, 1, 0) node _T_264 = add(_T_223, _T_263) node _T_265 = bits(_T_264, 1, 0) node _T_266 = add(_T_261, _T_265) node _T_267 = bits(_T_266, 2, 0) node _T_268 = add(_T_257, _T_267) node _T_269 = bits(_T_268, 3, 0) node _T_270 = add(_T_247, _T_269) node _T_271 = bits(_T_270, 4, 0) node _T_272 = leq(_T_271, UInt<1>(0h1)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_272, UInt<1>(0h1), "") : assert_2 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2] connect io.out_allocs.`0`[2].flow, in_flow connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3] connect io.out_allocs.`0`[3].flow, in_flow connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4] connect io.out_allocs.`0`[4].flow, in_flow connect io.out_allocs.`0`[5].alloc, in_alloc.`0`[5] connect io.out_allocs.`0`[5].flow, in_flow connect io.out_allocs.`0`[6].alloc, in_alloc.`0`[6] connect io.out_allocs.`0`[6].flow, in_flow connect io.out_allocs.`0`[7].alloc, in_alloc.`0`[7] connect io.out_allocs.`0`[7].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1] connect io.out_allocs.`1`[1].flow, in_flow connect io.out_allocs.`1`[2].alloc, in_alloc.`1`[2] connect io.out_allocs.`1`[2].flow, in_flow connect io.out_allocs.`1`[3].alloc, in_alloc.`1`[3] connect io.out_allocs.`1`[3].flow, in_flow connect io.out_allocs.`1`[4].alloc, in_alloc.`1`[4] connect io.out_allocs.`1`[4].flow, in_flow connect io.out_allocs.`1`[5].alloc, in_alloc.`1`[5] connect io.out_allocs.`1`[5].flow, in_flow connect io.out_allocs.`1`[6].alloc, in_alloc.`1`[6] connect io.out_allocs.`1`[6].flow, in_flow connect io.out_allocs.`1`[7].alloc, in_alloc.`1`[7] connect io.out_allocs.`1`[7].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow connect io.out_allocs.`2`[1].alloc, in_alloc.`2`[1] connect io.out_allocs.`2`[1].flow, in_flow connect io.out_allocs.`2`[2].alloc, in_alloc.`2`[2] connect io.out_allocs.`2`[2].flow, in_flow connect io.out_allocs.`2`[3].alloc, in_alloc.`2`[3] connect io.out_allocs.`2`[3].flow, in_flow connect io.out_allocs.`2`[4].alloc, in_alloc.`2`[4] connect io.out_allocs.`2`[4].flow, in_flow connect io.out_allocs.`2`[5].alloc, in_alloc.`2`[5] connect io.out_allocs.`2`[5].flow, in_flow connect io.out_allocs.`2`[6].alloc, in_alloc.`2`[6] connect io.out_allocs.`2`[6].flow, in_flow connect io.out_allocs.`2`[7].alloc, in_alloc.`2`[7] connect io.out_allocs.`2`[7].flow, in_flow

module RotatingSingleVCAllocator_14( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_3, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_4, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_5, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_6, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_7, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_3, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_4, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_5, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_6, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_7, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_3, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_4, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_5, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_6, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_7, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_3, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_4, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_5, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_6, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_7, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_3, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_4, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_5, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_6, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_7, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_3, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_4, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_5, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_6, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_7, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_3, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_4, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_5, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_6, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_7, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_3, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_4, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_5, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_6, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_7, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_3_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_4_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_5_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_6_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_7_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_3_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_4_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_5_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_6_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_7_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_6_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_7_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_3_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_4_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_5_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_6_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_7_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_3_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_4_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_5_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_6_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_7_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_5_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_6_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_7_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [2:0] mask; // @[SingleVCAllocator.scala:16:21] wire [2:0] _in_arb_filter_T_3 = {in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [5:0] in_arb_filter = _in_arb_filter_T_3[0] ? 6'h1 : _in_arb_filter_T_3[1] ? 6'h2 : _in_arb_filter_T_3[2] ? 6'h4 : in_arb_vals_0 ? 6'h8 : in_arb_vals_1 ? 6'h10 : {in_arb_vals_2, 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_arb_sel = in_arb_filter[2:0] | in_arb_filter[5:3]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2; // @[package.scala:81:59] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_2 = io_req_0_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_3 = io_req_0_bits_vc_sel_1_3 & ~io_channel_status_1_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_4 = io_req_0_bits_vc_sel_1_4 & ~io_channel_status_1_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_5 = io_req_0_bits_vc_sel_1_5 & ~io_channel_status_1_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_6 = io_req_0_bits_vc_sel_1_6 & ~io_channel_status_1_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_7 = io_req_0_bits_vc_sel_1_7 & ~io_channel_status_1_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_1 = io_req_0_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_2 = io_req_0_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_3 = io_req_0_bits_vc_sel_2_3 & ~io_channel_status_2_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_4 = io_req_0_bits_vc_sel_2_4 & ~io_channel_status_2_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_5 = io_req_0_bits_vc_sel_2_5 & ~io_channel_status_2_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_6 = io_req_0_bits_vc_sel_2_6 & ~io_channel_status_2_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_7 = io_req_0_bits_vc_sel_2_7 & ~io_channel_status_2_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_1_0 | in_arb_reqs_0_1_1 | in_arb_reqs_0_1_2 | in_arb_reqs_0_1_3 | in_arb_reqs_0_1_4 | in_arb_reqs_0_1_5 | in_arb_reqs_0_1_6 | in_arb_reqs_0_1_7 | in_arb_reqs_0_2_0 | in_arb_reqs_0_2_1 | in_arb_reqs_0_2_2 | in_arb_reqs_0_2_3 | in_arb_reqs_0_2_4 | in_arb_reqs_0_2_5 | in_arb_reqs_0_2_6 | in_arb_reqs_0_2_7); // @[package.scala:81:59] wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_6 = io_req_1_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_7 = io_req_1_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_1 = io_req_1_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_2 = io_req_1_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_3 = io_req_1_bits_vc_sel_2_3 & ~io_channel_status_2_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_4 = io_req_1_bits_vc_sel_2_4 & ~io_channel_status_2_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_5 = io_req_1_bits_vc_sel_2_5 & ~io_channel_status_2_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_6 = io_req_1_bits_vc_sel_2_6 & ~io_channel_status_2_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_7 = io_req_1_bits_vc_sel_2_7 & ~io_channel_status_2_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_0_3 | in_arb_reqs_1_0_4 | in_arb_reqs_1_0_5 | in_arb_reqs_1_0_6 | in_arb_reqs_1_0_7 | in_arb_reqs_1_2_0 | in_arb_reqs_1_2_1 | in_arb_reqs_1_2_2 | in_arb_reqs_1_2_3 | in_arb_reqs_1_2_4 | in_arb_reqs_1_2_5 | in_arb_reqs_1_2_6 | in_arb_reqs_1_2_7); // @[package.scala:81:59] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_3 = io_req_2_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_4 = io_req_2_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_5 = io_req_2_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_6 = io_req_2_bits_vc_sel_0_6 & ~io_channel_status_0_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_7 = io_req_2_bits_vc_sel_0_7 & ~io_channel_status_0_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_2 = io_req_2_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_3 = io_req_2_bits_vc_sel_1_3 & ~io_channel_status_1_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_4 = io_req_2_bits_vc_sel_1_4 & ~io_channel_status_1_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_5 = io_req_2_bits_vc_sel_1_5 & ~io_channel_status_1_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_6 = io_req_2_bits_vc_sel_1_6 & ~io_channel_status_1_6_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_7 = io_req_2_bits_vc_sel_1_7 & ~io_channel_status_1_7_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_1 | in_arb_reqs_2_0_2 | in_arb_reqs_2_0_3 | in_arb_reqs_2_0_4 | in_arb_reqs_2_0_5 | in_arb_reqs_2_0_6 | in_arb_reqs_2_0_7 | in_arb_reqs_2_1_0 | in_arb_reqs_2_1_1 | in_arb_reqs_2_1_2 | in_arb_reqs_2_1_3 | in_arb_reqs_2_1_4 | in_arb_reqs_2_1_5 | in_arb_reqs_2_1_6 | in_arb_reqs_2_1_7); // @[package.scala:81:59] wire _in_vc_sel_T_12 = in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[2] & in_arb_reqs_2_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_17 = in_arb_sel[1] & in_arb_reqs_1_0_2 | in_arb_sel[2] & in_arb_reqs_2_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_22 = in_arb_sel[1] & in_arb_reqs_1_0_3 | in_arb_sel[2] & in_arb_reqs_2_0_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_27 = in_arb_sel[1] & in_arb_reqs_1_0_4 | in_arb_sel[2] & in_arb_reqs_2_0_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_32 = in_arb_sel[1] & in_arb_reqs_1_0_5 | in_arb_sel[2] & in_arb_reqs_2_0_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_37 = in_arb_sel[1] & in_arb_reqs_1_0_6 | in_arb_sel[2] & in_arb_reqs_2_0_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_42 = in_arb_sel[1] & in_arb_reqs_1_0_7 | in_arb_sel[2] & in_arb_reqs_2_0_7; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_47 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_52 = in_arb_sel[0] & in_arb_reqs_0_1_1 | in_arb_sel[2] & in_arb_reqs_2_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_57 = in_arb_sel[0] & in_arb_reqs_0_1_2 | in_arb_sel[2] & in_arb_reqs_2_1_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_62 = in_arb_sel[0] & in_arb_reqs_0_1_3 | in_arb_sel[2] & in_arb_reqs_2_1_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_67 = in_arb_sel[0] & in_arb_reqs_0_1_4 | in_arb_sel[2] & in_arb_reqs_2_1_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_72 = in_arb_sel[0] & in_arb_reqs_0_1_5 | in_arb_sel[2] & in_arb_reqs_2_1_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_77 = in_arb_sel[0] & in_arb_reqs_0_1_6 | in_arb_sel[2] & in_arb_reqs_2_1_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_82 = in_arb_sel[0] & in_arb_reqs_0_1_7 | in_arb_sel[2] & in_arb_reqs_2_1_7; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_86 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_91 = in_arb_sel[0] & in_arb_reqs_0_2_1 | in_arb_sel[1] & in_arb_reqs_1_2_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_96 = in_arb_sel[0] & in_arb_reqs_0_2_2 | in_arb_sel[1] & in_arb_reqs_1_2_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_101 = in_arb_sel[0] & in_arb_reqs_0_2_3 | in_arb_sel[1] & in_arb_reqs_1_2_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_106 = in_arb_sel[0] & in_arb_reqs_0_2_4 | in_arb_sel[1] & in_arb_reqs_1_2_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_111 = in_arb_sel[0] & in_arb_reqs_0_2_5 | in_arb_sel[1] & in_arb_reqs_1_2_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_116 = in_arb_sel[0] & in_arb_reqs_0_2_6 | in_arb_sel[1] & in_arb_reqs_1_2_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_121 = in_arb_sel[0] & in_arb_reqs_0_2_7 | in_arb_sel[1] & in_arb_reqs_1_2_7; // @[Mux.scala:30:73, :32:36] reg [23:0] mask_1; // @[ISLIP.scala:17:25] wire [23:0] _full_T_1 = {_in_vc_sel_T_121, _in_vc_sel_T_116, _in_vc_sel_T_111, _in_vc_sel_T_106, _in_vc_sel_T_101, _in_vc_sel_T_96, _in_vc_sel_T_91, _in_vc_sel_T_86, _in_vc_sel_T_82, _in_vc_sel_T_77, _in_vc_sel_T_72, _in_vc_sel_T_67, _in_vc_sel_T_62, _in_vc_sel_T_57, _in_vc_sel_T_52, _in_vc_sel_T_47, _in_vc_sel_T_42, _in_vc_sel_T_37, _in_vc_sel_T_32, _in_vc_sel_T_27, _in_vc_sel_T_22, _in_vc_sel_T_17, _in_vc_sel_T_12, 1'h0} & ~mask_1; // @[Mux.scala:30:73] wire [47:0] oh = _full_T_1[0] ? 48'h1 : _full_T_1[1] ? 48'h2 : _full_T_1[2] ? 48'h4 : _full_T_1[3] ? 48'h8 : _full_T_1[4] ? 48'h10 : _full_T_1[5] ? 48'h20 : _full_T_1[6] ? 48'h40 : _full_T_1[7] ? 48'h80 : _full_T_1[8] ? 48'h100 : _full_T_1[9] ? 48'h200 : _full_T_1[10] ? 48'h400 : _full_T_1[11] ? 48'h800 : _full_T_1[12] ? 48'h1000 : _full_T_1[13] ? 48'h2000 : _full_T_1[14] ? 48'h4000 : _full_T_1[15] ? 48'h8000 : _full_T_1[16] ? 48'h10000 : _full_T_1[17] ? 48'h20000 : _full_T_1[18] ? 48'h40000 : _full_T_1[19] ? 48'h80000 : _full_T_1[20] ? 48'h100000 : _full_T_1[21] ? 48'h200000 : _full_T_1[22] ? 48'h400000 : _full_T_1[23] ? 48'h800000 : _in_vc_sel_T_12 ? 48'h2000000 : _in_vc_sel_T_17 ? 48'h4000000 : _in_vc_sel_T_22 ? 48'h8000000 : _in_vc_sel_T_27 ? 48'h10000000 : _in_vc_sel_T_32 ? 48'h20000000 : _in_vc_sel_T_37 ? 48'h40000000 : _in_vc_sel_T_42 ? 48'h80000000 : _in_vc_sel_T_47 ? 48'h100000000 : _in_vc_sel_T_52 ? 48'h200000000 : _in_vc_sel_T_57 ? 48'h400000000 : _in_vc_sel_T_62 ? 48'h800000000 : _in_vc_sel_T_67 ? 48'h1000000000 : _in_vc_sel_T_72 ? 48'h2000000000 : _in_vc_sel_T_77 ? 48'h4000000000 : _in_vc_sel_T_82 ? 48'h8000000000 : _in_vc_sel_T_86 ? 48'h10000000000 : _in_vc_sel_T_91 ? 48'h20000000000 : _in_vc_sel_T_96 ? 48'h40000000000 : _in_vc_sel_T_101 ? 48'h80000000000 : _in_vc_sel_T_106 ? 48'h100000000000 : _in_vc_sel_T_111 ? 48'h200000000000 : _in_vc_sel_T_116 ? 48'h400000000000 : {_in_vc_sel_T_121, 47'h0}; // @[OneHot.scala:85:71] wire [23:0] sel = oh[23:0] | oh[47:24]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[16]; // @[package.scala:81:59] wire in_alloc_2_1 = _GEN & sel[17]; // @[package.scala:81:59] wire in_alloc_2_2 = _GEN & sel[18]; // @[package.scala:81:59] wire in_alloc_2_3 = _GEN & sel[19]; // @[package.scala:81:59] wire in_alloc_2_4 = _GEN & sel[20]; // @[package.scala:81:59] wire in_alloc_2_5 = _GEN & sel[21]; // @[package.scala:81:59] wire in_alloc_2_6 = _GEN & sel[22]; // @[package.scala:81:59] wire in_alloc_2_7 = _GEN & sel[23]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[9]; // @[package.scala:81:59] wire in_alloc_1_2 = _GEN & sel[10]; // @[package.scala:81:59] wire in_alloc_1_3 = _GEN & sel[11]; // @[package.scala:81:59] wire in_alloc_1_4 = _GEN & sel[12]; // @[package.scala:81:59] wire in_alloc_1_5 = _GEN & sel[13]; // @[package.scala:81:59] wire in_alloc_1_6 = _GEN & sel[14]; // @[package.scala:81:59] wire in_alloc_1_7 = _GEN & sel[15]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_6 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_0_7 = _GEN & sel[7]; // @[package.scala:81:59]

Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem : input clock : Clock input reset : Reset output auto : { } inst buffer of TLBuffer_10 connect buffer.clock, clock connect buffer.reset, reset inst shrinker of TLSourceShrinker connect shrinker.clock, clock connect shrinker.reset, reset inst widget of TLWidthWidget8_10 connect widget.clock, clock connect widget.reset, reset

module TLInterconnectCoupler_mbus_to_memory_controller_port_named_tl_mem( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset // @[LazyModuleImp.scala:138:7] ); TLBuffer_10 buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset) ); // @[Buffer.scala:75:28] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module SourceD : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<64>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip bs_rdat : { data : UInt<64>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_wdat : { data : UInt<64>}, flip evict_req : { set : UInt<10>, way : UInt<3>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<10>, way : UInt<3>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<1> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<1>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<3>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 2, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node _s1_mask_T = not(s1_bypass) node s1_mask = and(UInt<1>(0h1), _s1_mask_T) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 3) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 3) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid || queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<3>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<1>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<8>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0)) node _T_19 = and(io.rel_pop.valid, _T_18) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_20 = and(s2_valid, s3_ready) when _T_20 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_21 = eq(s3_ready, UInt<1>(0h0)) node _T_22 = and(s2_valid, _T_21) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<3>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<1>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_2 = bits(queue.io.deq.bits.data, 63, 0) node s3_rdata = mux(_s3_rdata_T, _s3_rdata_T_1, _s3_rdata_T_2) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_23 = eq(s3_full, UInt<1>(0h0)) node _T_24 = eq(s3_need_r, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = or(_T_25, queue.io.deq.valid) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n") : printf_1 assert(clock, _T_26, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_30 = and(s3_valid, s4_ready) when _T_30 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_31 = eq(s4_ready, UInt<1>(0h0)) node _T_32 = and(s3_valid, _T_31) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<3>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<64>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_9 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_10 = or(_io_bs_wadr_bits_mask_T_9, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_11 = or(_io_bs_wadr_bits_mask_T_10, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_12 = or(_io_bs_wadr_bits_mask_T_11, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_13 = or(_io_bs_wadr_bits_mask_T_12, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_14 = or(_io_bs_wadr_bits_mask_T_13, _io_bs_wadr_bits_mask_T_7) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_14 connect io.bs_wdat.data, atomics.io.data_out node _T_33 = and(s4_full, s4_need_pb) node _T_34 = and(_T_33, s4_pdata.corrupt) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_40 = and(io.bs_wadr.valid, _T_39) node _T_41 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_42 = and(s4_req.prio[0], _T_41) node _T_43 = eq(s4_req.param, UInt<3>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_46 = and(s4_req.prio[0], _T_45) node _T_47 = eq(s4_req.param, UInt<3>(0h1)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_50 = and(s4_req.prio[0], _T_49) node _T_51 = eq(s4_req.param, UInt<3>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_54 = and(s4_req.prio[0], _T_53) node _T_55 = eq(s4_req.param, UInt<3>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_58 = and(s4_req.prio[0], _T_57) node _T_59 = eq(s4_req.param, UInt<3>(0h4)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_62 = and(s4_req.prio[0], _T_61) node _T_63 = eq(s4_req.param, UInt<3>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_66 = and(s4_req.prio[0], _T_65) node _T_67 = eq(s4_req.param, UInt<3>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_70 = and(s4_req.prio[0], _T_69) node _T_71 = eq(s4_req.param, UInt<3>(0h2)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_74 = and(s4_req.prio[0], _T_73) node _T_75 = eq(s4_req.param, UInt<3>(0h3)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(s4_need_bs, UInt<1>(0h0)) node _T_78 = or(io.bs_wadr.ready, _T_77) when _T_78 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<3>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<64>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<3>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<64>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<64>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<3>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 2, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass = mux(pre_s3_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<3>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 2, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass = mux(pre_s3_5_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<3>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 2, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass = mux(pre_s3_6_match, UInt<1>(0h1), UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_2 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_3 = mux(_s3_bypass_data_T, _s3_bypass_data_T_1, _s3_bypass_data_T_2) node _s3_bypass_data_T_4 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_5 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_6 = bits(_s3_bypass_data_T_3, 63, 0) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_4, _s3_bypass_data_T_5, _s3_bypass_data_T_6) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_7 node _s3_bypass_data_T_8 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_9 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_10 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_11 = mux(_s3_bypass_data_T_8, _s3_bypass_data_T_9, _s3_bypass_data_T_10) connect s3_bypass_data, _s3_bypass_data_T_11 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_79 = and(io.req.valid, s2) node _T_80 = and(_T_79, s3) node _T_81 = and(_T_80, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_82 = and(io.req.valid, s2_1) node _T_83 = and(_T_82, s3_1) node _T_84 = and(_T_83, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_85 = and(io.req.valid, s2_2) node _T_86 = and(_T_85, s3_2) node _T_87 = and(_T_86, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_88 = and(io.req.valid, s2_3) node _T_89 = and(_T_88, s3_3) node _T_90 = and(_T_89, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_91 = and(io.req.valid, s2_4) node _T_92 = and(_T_91, s3_4) node _T_93 = and(_T_92, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_94 = and(io.req.valid, s2_5) node _T_95 = and(_T_94, s3_5) node _T_96 = and(_T_95, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_97 = and(io.req.valid, s2_6) node _T_98 = and(_T_97, s3_6) node _T_99 = and(_T_98, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_100 = and(io.req.valid, s2_7) node _T_101 = and(_T_100, s3_7) node _T_102 = and(_T_101, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<3>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 2, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass = mux(s1_2_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<3>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 2, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass = mux(s1_3_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<3>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 2, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass = mux(s1_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22

module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [63:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [7:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [63:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [63:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [63:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [7:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [63:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [7:0] _s2_pdata_raw_mask_T = 8'hFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [63:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [2:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [63:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [63:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [2:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [2:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:3]; // @[package.scala:243:46] wire [2:0] s1_beats1 = s1_single ? 3'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [2:0] _s1_beat_T = s1_req_offset[5:3]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 3'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [3:0] _s1_counter_T = {1'h0, s1_counter} + 4'h1; // @[SourceD.scala:86:27, :130:30] wire [2:0] _s1_counter_T_1 = _s1_counter_T[2:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [2:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [63:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [7:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [63:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [7:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [63:0] s2_pdata_r_data; // @[package.scala:88:63] reg [7:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [63:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [7:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 8'hFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [2:0] s3_beat; // @[SourceD.scala:192:26] wire [2:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [63:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [7:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [63:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [63:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [63:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [63:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [2:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [2:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [63:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [7:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [63:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_9 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_10 = _io_bs_wadr_bits_mask_T_9 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_11 = _io_bs_wadr_bits_mask_T_10 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_12 = _io_bs_wadr_bits_mask_T_11 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_13 = _io_bs_wadr_bits_mask_T_12 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_14 = _io_bs_wadr_bits_mask_T_13 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:48:7, :275:87]

Generate the Verilog code corresponding to this FIRRTL code module PE_323 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_67 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_323( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_67 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_163 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_163( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_17 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}}, resp : { `3` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `2` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2]}} regreset mask : UInt<4>, clock, reset, UInt<4>(0h0) wire in_arb_reqs : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}[4] wire in_arb_vals : UInt<1>[4] node in_arb_filter_lo = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo) node in_arb_filter_lo_1 = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6) node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_12, UInt<8>(0h80), UInt<8>(0h0)) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_11, UInt<8>(0h40), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_10, UInt<8>(0h20), _in_arb_filter_T_14) node _in_arb_filter_T_16 = mux(_in_arb_filter_T_9, UInt<8>(0h10), _in_arb_filter_T_15) node _in_arb_filter_T_17 = mux(_in_arb_filter_T_8, UInt<8>(0h8), _in_arb_filter_T_16) node _in_arb_filter_T_18 = mux(_in_arb_filter_T_7, UInt<8>(0h4), _in_arb_filter_T_17) node _in_arb_filter_T_19 = mux(_in_arb_filter_T_6, UInt<8>(0h2), _in_arb_filter_T_18) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<8>(0h1), _in_arb_filter_T_19) node _in_arb_sel_T = bits(in_arb_filter, 3, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 4) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) node _T_2 = or(_T_1, in_arb_vals[3]) when _T_2 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = not(UInt<4>(0h0)) node _mask_T_4 = bits(in_arb_sel, 0, 0) node _mask_T_5 = bits(in_arb_sel, 1, 1) node _mask_T_6 = bits(in_arb_sel, 2, 2) node _mask_T_7 = bits(in_arb_sel, 3, 3) node _mask_T_8 = mux(_mask_T_4, _mask_T, UInt<1>(0h0)) node _mask_T_9 = mux(_mask_T_5, _mask_T_1, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_6, _mask_T_2, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_7, _mask_T_3, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_8, _mask_T_9) node _mask_T_13 = or(_mask_T_12, _mask_T_10) node _mask_T_14 = or(_mask_T_13, _mask_T_11) wire _mask_WIRE : UInt<4> connect _mask_WIRE, _mask_T_14 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T) connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T, _in_arb_vals_0_T_1) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`2`[0]) node _in_arb_vals_0_T_4 = and(io.req.`0`.valid, _in_arb_vals_0_T_3) connect in_arb_vals[0], _in_arb_vals_0_T_4 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T) connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T, _in_arb_vals_1_T_1) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`2`[0]) node _in_arb_vals_1_T_4 = and(io.req.`1`.valid, _in_arb_vals_1_T_3) connect in_arb_vals[1], _in_arb_vals_1_T_4 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T) connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T, _in_arb_vals_2_T_1) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`2`[0]) node _in_arb_vals_2_T_4 = and(io.req.`2`.valid, _in_arb_vals_2_T_3) connect in_arb_vals[2], _in_arb_vals_2_T_4 node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T) connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1 node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T) connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1 node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T) connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1 node _in_arb_reqs_3_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_1_T_1 = and(io.req.`3`.bits.vc_sel.`1`[1], _in_arb_reqs_3_1_1_T) connect in_arb_reqs[3].`1`[1], _in_arb_reqs_3_1_1_T_1 node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T) connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1 node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1]) node _in_arb_vals_3_T_1 = or(in_arb_reqs[3].`1`[0], in_arb_reqs[3].`1`[1]) node _in_arb_vals_3_T_2 = or(_in_arb_vals_3_T, _in_arb_vals_3_T_1) node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`2`[0]) node _in_arb_vals_3_T_4 = and(io.req.`3`.valid, _in_arb_vals_3_T_3) connect in_arb_vals[3], _in_arb_vals_3_T_4 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h0) wire in_alloc : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) node _in_flow_T_3 = bits(in_arb_sel, 3, 3) wire in_flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _in_flow_T_4 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_7 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_8 = or(_in_flow_T_4, _in_flow_T_5) node _in_flow_T_9 = or(_in_flow_T_8, _in_flow_T_6) node _in_flow_T_10 = or(_in_flow_T_9, _in_flow_T_7) wire _in_flow_WIRE : UInt<2> connect _in_flow_WIRE, _in_flow_T_10 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_11 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_12 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_13 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_15 = or(_in_flow_T_11, _in_flow_T_12) node _in_flow_T_16 = or(_in_flow_T_15, _in_flow_T_13) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_14) wire _in_flow_WIRE_1 : UInt<4> connect _in_flow_WIRE_1, _in_flow_T_17 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_21 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_22 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_23 = or(_in_flow_T_22, _in_flow_T_20) node _in_flow_T_24 = or(_in_flow_T_23, _in_flow_T_21) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_24 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_25 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_26 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_27 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_28 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_29 = or(_in_flow_T_25, _in_flow_T_26) node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_27) node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_28) wire _in_flow_WIRE_3 : UInt<4> connect _in_flow_WIRE_3, _in_flow_T_31 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_32 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_33 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_34 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_35 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_36 = or(_in_flow_T_32, _in_flow_T_33) node _in_flow_T_37 = or(_in_flow_T_36, _in_flow_T_34) node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_35) wire _in_flow_WIRE_4 : UInt<1> connect _in_flow_WIRE_4, _in_flow_T_38 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = bits(in_arb_sel, 3, 3) node _in_vc_T_4 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_7 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_8 = or(_in_vc_T_4, _in_vc_T_5) node _in_vc_T_9 = or(_in_vc_T_8, _in_vc_T_6) node _in_vc_T_10 = or(_in_vc_T_9, _in_vc_T_7) wire in_vc : UInt<1> connect in_vc, _in_vc_T_10 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3) wire in_vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _in_vc_sel_WIRE : UInt<1>[2] node _in_vc_sel_T_4 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_7 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_8 = or(_in_vc_sel_T_4, _in_vc_sel_T_5) node _in_vc_sel_T_9 = or(_in_vc_sel_T_8, _in_vc_sel_T_6) node _in_vc_sel_T_10 = or(_in_vc_sel_T_9, _in_vc_sel_T_7) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_10 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_11 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_12 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_13 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_15 = or(_in_vc_sel_T_11, _in_vc_sel_T_12) node _in_vc_sel_T_16 = or(_in_vc_sel_T_15, _in_vc_sel_T_13) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_14) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_3 : UInt<1>[2] node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_21 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_22 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_23 = or(_in_vc_sel_T_22, _in_vc_sel_T_20) node _in_vc_sel_T_24 = or(_in_vc_sel_T_23, _in_vc_sel_T_21) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_24 connect _in_vc_sel_WIRE_3[0], _in_vc_sel_WIRE_4 node _in_vc_sel_T_25 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_26 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_27 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_28 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_29 = or(_in_vc_sel_T_25, _in_vc_sel_T_26) node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_27) node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_28) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_31 connect _in_vc_sel_WIRE_3[1], _in_vc_sel_WIRE_5 connect in_vc_sel.`1`, _in_vc_sel_WIRE_3 wire _in_vc_sel_WIRE_6 : UInt<1>[1] node _in_vc_sel_T_32 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_33 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_32, _in_vc_sel_T_33) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_34) node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_38 connect _in_vc_sel_WIRE_6[0], _in_vc_sel_WIRE_7 connect in_vc_sel.`2`, _in_vc_sel_WIRE_6 node _T_3 = or(in_arb_vals[0], in_arb_vals[1]) node _T_4 = or(_T_3, in_arb_vals[2]) node _T_5 = or(_T_4, in_arb_vals[3]) node hi = bits(in_arb_sel, 3, 2) node lo = bits(in_arb_sel, 1, 0) node _T_6 = orr(hi) node _T_7 = or(hi, lo) node _T_8 = bits(_T_7, 1, 1) node _T_9 = cat(_T_6, _T_8) node _T_10 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_11 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_12 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_13 = and(io.req.`3`.ready, io.req.`3`.valid) node _T_14 = or(_T_10, _T_11) node _T_15 = or(_T_14, _T_12) node _T_16 = or(_T_15, _T_13) node _T_17 = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node _T_18 = cat(in_vc_sel.`1`[1], in_vc_sel.`1`[0]) node hi_1 = cat(in_vc_sel.`2`[0], _T_18) node _T_19 = cat(hi_1, _T_17) regreset mask_1 : UInt<5>, clock, reset, UInt<5>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_19, _full_T) node full = cat(_T_19, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = mux(_oh_T_9, UInt<10>(0h200), UInt<10>(0h0)) node _oh_T_11 = mux(_oh_T_8, UInt<10>(0h100), _oh_T_10) node _oh_T_12 = mux(_oh_T_7, UInt<10>(0h80), _oh_T_11) node _oh_T_13 = mux(_oh_T_6, UInt<10>(0h40), _oh_T_12) node _oh_T_14 = mux(_oh_T_5, UInt<10>(0h20), _oh_T_13) node _oh_T_15 = mux(_oh_T_4, UInt<10>(0h10), _oh_T_14) node _oh_T_16 = mux(_oh_T_3, UInt<10>(0h8), _oh_T_15) node _oh_T_17 = mux(_oh_T_2, UInt<10>(0h4), _oh_T_16) node _oh_T_18 = mux(_oh_T_1, UInt<10>(0h2), _oh_T_17) node oh = mux(_oh_T, UInt<10>(0h1), _oh_T_18) node _sel_T = bits(oh, 4, 0) node _sel_T_1 = shr(oh, 5) node sel = or(_sel_T, _sel_T_1) when _T_16 : node _mask_T_15 = bits(sel, 0, 0) node _mask_T_16 = not(UInt<1>(0h0)) node _mask_T_17 = bits(sel, 1, 1) node _mask_T_18 = not(UInt<2>(0h0)) node _mask_T_19 = bits(sel, 2, 2) node _mask_T_20 = not(UInt<3>(0h0)) node _mask_T_21 = bits(sel, 3, 3) node _mask_T_22 = not(UInt<4>(0h0)) node _mask_T_23 = bits(sel, 4, 4) node _mask_T_24 = not(UInt<5>(0h0)) node _mask_T_25 = mux(_mask_T_23, _mask_T_24, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_21, _mask_T_22, _mask_T_25) node _mask_T_27 = mux(_mask_T_19, _mask_T_20, _mask_T_26) node _mask_T_28 = mux(_mask_T_17, _mask_T_18, _mask_T_27) node _mask_T_29 = mux(_mask_T_15, _mask_T_16, _mask_T_28) connect mask_1, _mask_T_29 wire _WIRE : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _WIRE_1 : UInt<5> connect _WIRE_1, sel node _T_20 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_20 node _T_21 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_21 node _T_22 = bits(_WIRE_1, 2, 2) connect _WIRE.`1`[0], _T_22 node _T_23 = bits(_WIRE_1, 3, 3) connect _WIRE.`1`[1], _T_23 node _T_24 = bits(_WIRE_1, 4, 4) connect _WIRE.`2`[0], _T_24 wire _WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`1`[1], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) node _T_25 = mux(_T_5, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_25.`0` connect in_alloc.`1`, _T_25.`1` connect in_alloc.`2`, _T_25.`2` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_26 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node _T_27 = cat(io.resp.`0`.vc_sel.`1`[1], io.resp.`0`.vc_sel.`1`[0]) node hi_2 = cat(io.resp.`0`.vc_sel.`2`[0], _T_27) node _T_28 = cat(hi_2, _T_26) node _T_29 = bits(_T_28, 0, 0) node _T_30 = bits(_T_28, 1, 1) node _T_31 = bits(_T_28, 2, 2) node _T_32 = bits(_T_28, 3, 3) node _T_33 = bits(_T_28, 4, 4) node _T_34 = add(_T_29, _T_30) node _T_35 = bits(_T_34, 1, 0) node _T_36 = add(_T_32, _T_33) node _T_37 = bits(_T_36, 1, 0) node _T_38 = add(_T_31, _T_37) node _T_39 = bits(_T_38, 1, 0) node _T_40 = add(_T_35, _T_39) node _T_41 = bits(_T_40, 2, 0) node _T_42 = leq(_T_41, UInt<1>(0h1)) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_42, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_46 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node _T_47 = cat(io.resp.`1`.vc_sel.`1`[1], io.resp.`1`.vc_sel.`1`[0]) node hi_3 = cat(io.resp.`1`.vc_sel.`2`[0], _T_47) node _T_48 = cat(hi_3, _T_46) node _T_49 = bits(_T_48, 0, 0) node _T_50 = bits(_T_48, 1, 1) node _T_51 = bits(_T_48, 2, 2) node _T_52 = bits(_T_48, 3, 3) node _T_53 = bits(_T_48, 4, 4) node _T_54 = add(_T_49, _T_50) node _T_55 = bits(_T_54, 1, 0) node _T_56 = add(_T_52, _T_53) node _T_57 = bits(_T_56, 1, 0) node _T_58 = add(_T_51, _T_57) node _T_59 = bits(_T_58, 1, 0) node _T_60 = add(_T_55, _T_59) node _T_61 = bits(_T_60, 2, 0) node _T_62 = leq(_T_61, UInt<1>(0h1)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_62, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_66 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node _T_67 = cat(io.resp.`2`.vc_sel.`1`[1], io.resp.`2`.vc_sel.`1`[0]) node hi_4 = cat(io.resp.`2`.vc_sel.`2`[0], _T_67) node _T_68 = cat(hi_4, _T_66) node _T_69 = bits(_T_68, 0, 0) node _T_70 = bits(_T_68, 1, 1) node _T_71 = bits(_T_68, 2, 2) node _T_72 = bits(_T_68, 3, 3) node _T_73 = bits(_T_68, 4, 4) node _T_74 = add(_T_69, _T_70) node _T_75 = bits(_T_74, 1, 0) node _T_76 = add(_T_72, _T_73) node _T_77 = bits(_T_76, 1, 0) node _T_78 = add(_T_71, _T_77) node _T_79 = bits(_T_78, 1, 0) node _T_80 = add(_T_75, _T_79) node _T_81 = bits(_T_80, 2, 0) node _T_82 = leq(_T_81, UInt<1>(0h1)) node _T_83 = asUInt(reset) node _T_84 = eq(_T_83, UInt<1>(0h0)) when _T_84 : node _T_85 = eq(_T_82, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_82, UInt<1>(0h1), "") : assert_2 node _io_req_3_ready_T = bits(in_arb_sel, 3, 3) connect io.req.`3`.ready, _io_req_3_ready_T connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`3`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0] node _T_86 = cat(io.resp.`3`.vc_sel.`0`[1], io.resp.`3`.vc_sel.`0`[0]) node _T_87 = cat(io.resp.`3`.vc_sel.`1`[1], io.resp.`3`.vc_sel.`1`[0]) node hi_5 = cat(io.resp.`3`.vc_sel.`2`[0], _T_87) node _T_88 = cat(hi_5, _T_86) node _T_89 = bits(_T_88, 0, 0) node _T_90 = bits(_T_88, 1, 1) node _T_91 = bits(_T_88, 2, 2) node _T_92 = bits(_T_88, 3, 3) node _T_93 = bits(_T_88, 4, 4) node _T_94 = add(_T_89, _T_90) node _T_95 = bits(_T_94, 1, 0) node _T_96 = add(_T_92, _T_93) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_91, _T_97) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_95, _T_99) node _T_101 = bits(_T_100, 2, 0) node _T_102 = leq(_T_101, UInt<1>(0h1)) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1] connect io.out_allocs.`1`[1].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow

module RotatingSingleVCAllocator_17( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_0_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [3:0] mask; // @[SingleVCAllocator.scala:16:21] wire [3:0] _in_arb_filter_T_3 = {in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : in_arb_vals_1 ? 8'h20 : in_arb_vals_2 ? 8'h40 : {in_arb_vals_3, 7'h0}; // @[OneHot.scala:85:71] wire [3:0] in_arb_sel = in_arb_filter[3:0] | in_arb_filter[7:4]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_3; // @[package.scala:81:59] wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | io_req_0_bits_vc_sel_0_1 | in_arb_reqs_0_1_0 | io_req_0_bits_vc_sel_1_1 | in_arb_reqs_0_2_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | io_req_1_bits_vc_sel_0_1 | in_arb_reqs_1_1_0 | io_req_1_bits_vc_sel_1_1 | in_arb_reqs_1_2_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 | io_req_2_bits_vc_sel_0_1 | in_arb_reqs_2_1_0 | io_req_2_bits_vc_sel_1_1 | in_arb_reqs_2_2_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 | io_req_3_bits_vc_sel_0_1 | in_arb_reqs_3_1_0 | io_req_3_bits_vc_sel_1_1 | in_arb_reqs_3_2_0); // @[package.scala:81:59] wire _in_vc_sel_T_10 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0 | in_arb_sel[2] & in_arb_reqs_2_0_0 | in_arb_sel[3] & in_arb_reqs_3_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_17 = in_arb_sel[0] & io_req_0_bits_vc_sel_0_1 | in_arb_sel[1] & io_req_1_bits_vc_sel_0_1 | in_arb_sel[2] & io_req_2_bits_vc_sel_0_1 | in_arb_sel[3] & io_req_3_bits_vc_sel_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_24 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0 | in_arb_sel[3] & in_arb_reqs_3_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & io_req_0_bits_vc_sel_1_1 | in_arb_sel[1] & io_req_1_bits_vc_sel_1_1 | in_arb_sel[2] & io_req_2_bits_vc_sel_1_1 | in_arb_sel[3] & io_req_3_bits_vc_sel_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_38 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0; // @[Mux.scala:30:73, :32:36] reg [4:0] mask_1; // @[ISLIP.scala:17:25] wire [4:0] _full_T_1 = {_in_vc_sel_T_38, _in_vc_sel_T_31, _in_vc_sel_T_24, _in_vc_sel_T_17, _in_vc_sel_T_10} & ~mask_1; // @[Mux.scala:30:73] wire [9:0] oh = _full_T_1[0] ? 10'h1 : _full_T_1[1] ? 10'h2 : _full_T_1[2] ? 10'h4 : _full_T_1[3] ? 10'h8 : _full_T_1[4] ? 10'h10 : _in_vc_sel_T_10 ? 10'h20 : _in_vc_sel_T_17 ? 10'h40 : _in_vc_sel_T_24 ? 10'h80 : _in_vc_sel_T_31 ? 10'h100 : {_in_vc_sel_T_38, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] sel = oh[4:0] | oh[9:5]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]

Generate the Verilog code corresponding to this FIRRTL code module PE_373 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_117 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_373( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_117 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_8 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_101 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_102 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_8( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_101 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_102 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_PutBufferCEntry_q2_e8 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<1>, data : { data : UInt<128>, corrupt : UInt<1>}}}, valid : UInt<2>, flip pop : { valid : UInt<1>, bits : UInt<1>}, data : { data : UInt<128>, corrupt : UInt<1>}} regreset valid : UInt<2>, clock, reset, UInt<2>(0h0) cmem head : UInt<3> [2] cmem tail : UInt<3> [2] regreset used : UInt<8>, clock, reset, UInt<8>(0h0) cmem next : UInt<3> [8] cmem data : { data : UInt<128>, corrupt : UInt<1>} [8] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 7, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 7, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 7, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = bits(_freeOH_T_9, 7, 0) node _freeOH_T_11 = shl(_freeOH_T_10, 1) node _freeOH_T_12 = not(_freeOH_T_11) node _freeOH_T_13 = not(used) node freeOH = and(_freeOH_T_12, _freeOH_T_13) node freeIdx_hi = bits(freeOH, 8, 8) node freeIdx_lo = bits(freeOH, 7, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 7, 4) node freeIdx_lo_1 = bits(_freeIdx_T_1, 3, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 3, 2) node freeIdx_lo_2 = bits(_freeIdx_T_3, 1, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node _freeIdx_T_6 = bits(_freeIdx_T_5, 1, 1) node _freeIdx_T_7 = cat(_freeIdx_T_4, _freeIdx_T_6) node _freeIdx_T_8 = cat(_freeIdx_T_2, _freeIdx_T_7) node freeIdx = cat(_freeIdx_T, _freeIdx_T_8) wire valid_set : UInt<2> connect valid_set, UInt<2>(0h0) wire valid_clr : UInt<2> connect valid_clr, UInt<2>(0h0) wire used_set : UInt<8> connect used_set, UInt<8>(0h0) wire used_clr : UInt<8> connect used_clr, UInt<8>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 0, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 1, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH node _T_1 = bits(freeIdx, 2, 0) write mport MPORT = data[_T_1], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_2 = eq(io.pop.valid, UInt<1>(0h0)) node _T_3 = dshr(io.valid, io.pop.bits) node _T_4 = bits(_T_3, 0, 0) node _T_5 = or(_T_2, _T_4) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_5, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 2, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 7, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_9 = eq(pop_head, MPORT_4) when _T_9 : node valid_clr_shiftAmount = bits(io.pop.bits, 0, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 1, 0) connect valid_clr, _valid_clr_T_1 node _T_10 = and(io.push.ready, io.push.valid) node _T_11 = and(_T_10, push_valid) node _T_12 = eq(push_tail, pop_head) node _T_13 = and(_T_11, _T_12) read mport MPORT_5 = next[pop_head], clock node _T_14 = mux(_T_13, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_14 node _T_15 = eq(io.pop.valid, UInt<1>(0h0)) node _T_16 = or(UInt<1>(0h1), _T_15) node _T_17 = or(_T_16, pop_valid) when _T_17 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2

module ListBuffer_PutBufferCEntry_q2_e8( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input io_push_bits_index, // @[ListBuffer.scala:39:14] input [127:0] io_push_bits_data_data, // @[ListBuffer.scala:39:14] input io_push_bits_data_corrupt, // @[ListBuffer.scala:39:14] output [1:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input io_pop_bits, // @[ListBuffer.scala:39:14] output [127:0] io_data_data, // @[ListBuffer.scala:39:14] output io_data_corrupt // @[ListBuffer.scala:39:14] ); wire [128:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [2:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [2:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [2:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [2:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] reg [1:0] valid; // @[ListBuffer.scala:47:22] reg [7:0] used; // @[ListBuffer.scala:50:22] wire [7:0] _freeOH_T_13 = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [6:0] _freeOH_T_3 = _freeOH_T_13[6:0] | {_freeOH_T_13[5:0], 1'h0}; // @[package.scala:253:{43,53}] wire [6:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[4:0], 2'h0}; // @[package.scala:253:{43,53}] wire [7:0] freeIdx_lo = {~(_freeOH_T_6 | {_freeOH_T_6[2:0], 4'h0}), 1'h1} & _freeOH_T_13; // @[package.scala:253:{43,53}] wire [2:0] _freeIdx_T_3 = freeIdx_lo[7:5] | freeIdx_lo[3:1]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_5 = _freeIdx_T_3[2] | _freeIdx_T_3[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] _GEN = {1'h0, io_push_bits_index}; // @[ListBuffer.scala:63:25] wire [1:0] _push_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :63:25] wire io_push_ready_0 = used != 8'hFF; // @[ListBuffer.scala:50:22, :65:26] wire data_MPORT_en = io_push_ready_0 & io_push_valid; // @[Decoupled.scala:51:35] wire [2:0] data_MPORT_addr = {|(freeIdx_lo[7:4]), |(_freeIdx_T_3[2:1]), _freeIdx_T_5}; // @[OneHot.scala:30:18, :32:{14,28}] wire [1:0] _GEN_0 = {1'h0, io_pop_bits}; // @[ListBuffer.scala:86:37]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_30 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_282 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_283 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_284 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_30( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_282 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_283 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_284 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_45 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_45 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_45( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_45 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_66 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_139 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_140 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_66( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s11k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_22 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s11k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s11k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_46 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_47 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBuffer_a26d64s11k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [10:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_22 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s11k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s11k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_17 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_24 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_17( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_24 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_12 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_12( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SourceA_3 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} wire a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} inst io_a_q of Queue2_TLBundleA_a32d64s4k3z3c_3 connect io_a_q.clock, clock connect io_a_q.reset, reset connect io_a_q.io.enq.valid, a.valid connect io_a_q.io.enq.bits.corrupt, a.bits.corrupt connect io_a_q.io.enq.bits.data, a.bits.data connect io_a_q.io.enq.bits.mask, a.bits.mask connect io_a_q.io.enq.bits.address, a.bits.address connect io_a_q.io.enq.bits.source, a.bits.source connect io_a_q.io.enq.bits.size, a.bits.size connect io_a_q.io.enq.bits.param, a.bits.param connect io_a_q.io.enq.bits.opcode, a.bits.opcode connect a.ready, io_a_q.io.enq.ready connect io.a.bits, io_a_q.io.deq.bits connect io.a.valid, io_a_q.io.deq.valid connect io_a_q.io.deq.ready, io.a.ready connect io.req.ready, a.ready connect a.valid, io.req.valid node _T = eq(a.ready, UInt<1>(0h0)) node _T_1 = and(a.valid, _T) node _a_bits_opcode_T = mux(io.req.bits.block, UInt<3>(0h6), UInt<3>(0h7)) connect a.bits.opcode, _a_bits_opcode_T connect a.bits.param, io.req.bits.param connect a.bits.size, UInt<3>(0h6) connect a.bits.source, io.req.bits.source node a_bits_address_base_y = or(io.req.bits.tag, UInt<9>(0h0)) node _a_bits_address_base_T = shr(a_bits_address_base_y, 9) node _a_bits_address_base_T_1 = eq(_a_bits_address_base_T, UInt<1>(0h0)) node _a_bits_address_base_T_2 = asUInt(reset) node _a_bits_address_base_T_3 = eq(_a_bits_address_base_T_2, UInt<1>(0h0)) when _a_bits_address_base_T_3 : node _a_bits_address_base_T_4 = eq(_a_bits_address_base_T_1, UInt<1>(0h0)) when _a_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf assert(clock, _a_bits_address_base_T_1, UInt<1>(0h1), "") : a_bits_address_base_assert node _a_bits_address_base_T_5 = bits(a_bits_address_base_y, 8, 0) node a_bits_address_base_y_1 = or(io.req.bits.set, UInt<11>(0h0)) node _a_bits_address_base_T_6 = shr(a_bits_address_base_y_1, 11) node _a_bits_address_base_T_7 = eq(_a_bits_address_base_T_6, UInt<1>(0h0)) node _a_bits_address_base_T_8 = asUInt(reset) node _a_bits_address_base_T_9 = eq(_a_bits_address_base_T_8, UInt<1>(0h0)) when _a_bits_address_base_T_9 : node _a_bits_address_base_T_10 = eq(_a_bits_address_base_T_7, UInt<1>(0h0)) when _a_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf_1 assert(clock, _a_bits_address_base_T_7, UInt<1>(0h1), "") : a_bits_address_base_assert_1 node _a_bits_address_base_T_11 = bits(a_bits_address_base_y_1, 10, 0) node a_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _a_bits_address_base_T_12 = shr(a_bits_address_base_y_2, 6) node _a_bits_address_base_T_13 = eq(_a_bits_address_base_T_12, UInt<1>(0h0)) node _a_bits_address_base_T_14 = asUInt(reset) node _a_bits_address_base_T_15 = eq(_a_bits_address_base_T_14, UInt<1>(0h0)) when _a_bits_address_base_T_15 : node _a_bits_address_base_T_16 = eq(_a_bits_address_base_T_13, UInt<1>(0h0)) when _a_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : a_bits_address_base_printf_2 assert(clock, _a_bits_address_base_T_13, UInt<1>(0h1), "") : a_bits_address_base_assert_2 node _a_bits_address_base_T_17 = bits(a_bits_address_base_y_2, 5, 0) node a_bits_address_base_hi = cat(_a_bits_address_base_T_5, _a_bits_address_base_T_11) node a_bits_address_base = cat(a_bits_address_base_hi, _a_bits_address_base_T_17) node _a_bits_address_T = bits(a_bits_address_base, 0, 0) node _a_bits_address_T_1 = bits(a_bits_address_base, 1, 1) node _a_bits_address_T_2 = bits(a_bits_address_base, 2, 2) node _a_bits_address_T_3 = bits(a_bits_address_base, 3, 3) node _a_bits_address_T_4 = bits(a_bits_address_base, 4, 4) node _a_bits_address_T_5 = bits(a_bits_address_base, 5, 5) node _a_bits_address_T_6 = bits(a_bits_address_base, 6, 6) node _a_bits_address_T_7 = bits(a_bits_address_base, 7, 7) node _a_bits_address_T_8 = bits(a_bits_address_base, 8, 8) node _a_bits_address_T_9 = bits(a_bits_address_base, 9, 9) node _a_bits_address_T_10 = bits(a_bits_address_base, 10, 10) node _a_bits_address_T_11 = bits(a_bits_address_base, 11, 11) node _a_bits_address_T_12 = bits(a_bits_address_base, 12, 12) node _a_bits_address_T_13 = bits(a_bits_address_base, 13, 13) node _a_bits_address_T_14 = bits(a_bits_address_base, 14, 14) node _a_bits_address_T_15 = bits(a_bits_address_base, 15, 15) node _a_bits_address_T_16 = bits(a_bits_address_base, 16, 16) node _a_bits_address_T_17 = bits(a_bits_address_base, 17, 17) node _a_bits_address_T_18 = bits(a_bits_address_base, 18, 18) node _a_bits_address_T_19 = bits(a_bits_address_base, 19, 19) node _a_bits_address_T_20 = bits(a_bits_address_base, 20, 20) node _a_bits_address_T_21 = bits(a_bits_address_base, 21, 21) node _a_bits_address_T_22 = bits(a_bits_address_base, 22, 22) node _a_bits_address_T_23 = bits(a_bits_address_base, 23, 23) node _a_bits_address_T_24 = bits(a_bits_address_base, 24, 24) node _a_bits_address_T_25 = bits(a_bits_address_base, 25, 25) node a_bits_address_lo_lo_lo_lo = cat(_a_bits_address_T_1, _a_bits_address_T) node a_bits_address_lo_lo_lo_hi = cat(_a_bits_address_T_3, _a_bits_address_T_2) node a_bits_address_lo_lo_lo = cat(a_bits_address_lo_lo_lo_hi, a_bits_address_lo_lo_lo_lo) node a_bits_address_lo_lo_hi_lo = cat(_a_bits_address_T_5, _a_bits_address_T_4) node a_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node a_bits_address_lo_lo_hi = cat(a_bits_address_lo_lo_hi_hi, a_bits_address_lo_lo_hi_lo) node a_bits_address_lo_lo = cat(a_bits_address_lo_lo_hi, a_bits_address_lo_lo_lo) node a_bits_address_lo_hi_lo_lo = cat(_a_bits_address_T_6, UInt<1>(0h0)) node a_bits_address_lo_hi_lo_hi = cat(_a_bits_address_T_8, _a_bits_address_T_7) node a_bits_address_lo_hi_lo = cat(a_bits_address_lo_hi_lo_hi, a_bits_address_lo_hi_lo_lo) node a_bits_address_lo_hi_hi_lo = cat(_a_bits_address_T_10, _a_bits_address_T_9) node a_bits_address_lo_hi_hi_hi = cat(_a_bits_address_T_12, _a_bits_address_T_11) node a_bits_address_lo_hi_hi = cat(a_bits_address_lo_hi_hi_hi, a_bits_address_lo_hi_hi_lo) node a_bits_address_lo_hi = cat(a_bits_address_lo_hi_hi, a_bits_address_lo_hi_lo) node a_bits_address_lo = cat(a_bits_address_lo_hi, a_bits_address_lo_lo) node a_bits_address_hi_lo_lo_lo = cat(_a_bits_address_T_14, _a_bits_address_T_13) node a_bits_address_hi_lo_lo_hi = cat(_a_bits_address_T_16, _a_bits_address_T_15) node a_bits_address_hi_lo_lo = cat(a_bits_address_hi_lo_lo_hi, a_bits_address_hi_lo_lo_lo) node a_bits_address_hi_lo_hi_lo = cat(_a_bits_address_T_18, _a_bits_address_T_17) node a_bits_address_hi_lo_hi_hi = cat(_a_bits_address_T_20, _a_bits_address_T_19) node a_bits_address_hi_lo_hi = cat(a_bits_address_hi_lo_hi_hi, a_bits_address_hi_lo_hi_lo) node a_bits_address_hi_lo = cat(a_bits_address_hi_lo_hi, a_bits_address_hi_lo_lo) node a_bits_address_hi_hi_lo_lo = cat(_a_bits_address_T_22, _a_bits_address_T_21) node a_bits_address_hi_hi_lo_hi = cat(_a_bits_address_T_24, _a_bits_address_T_23) node a_bits_address_hi_hi_lo = cat(a_bits_address_hi_hi_lo_hi, a_bits_address_hi_hi_lo_lo) node a_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node a_bits_address_hi_hi_hi_hi = cat(_a_bits_address_T_25, UInt<1>(0h0)) node a_bits_address_hi_hi_hi = cat(a_bits_address_hi_hi_hi_hi, a_bits_address_hi_hi_hi_lo) node a_bits_address_hi_hi = cat(a_bits_address_hi_hi_hi, a_bits_address_hi_hi_lo) node a_bits_address_hi = cat(a_bits_address_hi_hi, a_bits_address_hi_lo) node _a_bits_address_T_26 = cat(a_bits_address_hi, a_bits_address_lo) connect a.bits.address, _a_bits_address_T_26 node _a_bits_mask_T = not(UInt<8>(0h0)) connect a.bits.mask, _a_bits_mask_T connect a.bits.data, UInt<1>(0h0) connect a.bits.corrupt, UInt<1>(0h0)

module SourceA_3( // @[SourceA.scala:33:7] input clock, // @[SourceA.scala:33:7] input reset, // @[SourceA.scala:33:7] output io_req_ready, // @[SourceA.scala:35:14] input io_req_valid, // @[SourceA.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceA.scala:35:14] input [10:0] io_req_bits_set, // @[SourceA.scala:35:14] input [2:0] io_req_bits_param, // @[SourceA.scala:35:14] input [3:0] io_req_bits_source, // @[SourceA.scala:35:14] input io_req_bits_block, // @[SourceA.scala:35:14] input io_a_ready, // @[SourceA.scala:35:14] output io_a_valid, // @[SourceA.scala:35:14] output [2:0] io_a_bits_opcode, // @[SourceA.scala:35:14] output [2:0] io_a_bits_param, // @[SourceA.scala:35:14] output [2:0] io_a_bits_size, // @[SourceA.scala:35:14] output [3:0] io_a_bits_source, // @[SourceA.scala:35:14] output [31:0] io_a_bits_address, // @[SourceA.scala:35:14] output [7:0] io_a_bits_mask, // @[SourceA.scala:35:14] output [63:0] io_a_bits_data, // @[SourceA.scala:35:14] output io_a_bits_corrupt // @[SourceA.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceA.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceA.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceA.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceA.scala:33:7] wire [3:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceA.scala:33:7] wire io_req_bits_block_0 = io_req_bits_block; // @[SourceA.scala:33:7] wire io_a_ready_0 = io_a_ready; // @[SourceA.scala:33:7] wire _a_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] a_bits_size = 3'h6; // @[SourceA.scala:43:15] wire [63:0] a_bits_data = 64'h0; // @[SourceA.scala:43:15] wire a_bits_corrupt = 1'h0; // @[SourceA.scala:43:15] wire _a_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _a_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _a_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _a_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire [5:0] a_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _a_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire [1:0] a_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire a_ready; // @[SourceA.scala:43:15] wire [7:0] a_bits_mask = 8'hFF; // @[SourceA.scala:43:15] wire [7:0] _a_bits_mask_T = 8'hFF; // @[SourceA.scala:55:21] wire a_valid = io_req_valid_0; // @[SourceA.scala:33:7, :43:15] wire [8:0] a_bits_address_base_y = io_req_bits_tag_0; // @[SourceA.scala:33:7] wire [10:0] a_bits_address_base_y_1 = io_req_bits_set_0; // @[SourceA.scala:33:7] wire [2:0] a_bits_param = io_req_bits_param_0; // @[SourceA.scala:33:7, :43:15] wire [3:0] a_bits_source = io_req_bits_source_0; // @[SourceA.scala:33:7, :43:15] wire io_req_ready_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_opcode_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_param_0; // @[SourceA.scala:33:7] wire [2:0] io_a_bits_size_0; // @[SourceA.scala:33:7] wire [3:0] io_a_bits_source_0; // @[SourceA.scala:33:7] wire [31:0] io_a_bits_address_0; // @[SourceA.scala:33:7] wire [7:0] io_a_bits_mask_0; // @[SourceA.scala:33:7] wire [63:0] io_a_bits_data_0; // @[SourceA.scala:33:7] wire io_a_bits_corrupt_0; // @[SourceA.scala:33:7] wire io_a_valid_0; // @[SourceA.scala:33:7] assign io_req_ready_0 = a_ready; // @[SourceA.scala:33:7, :43:15] wire [2:0] _a_bits_opcode_T; // @[SourceA.scala:50:24] wire [31:0] _a_bits_address_T_26; // @[Parameters.scala:230:8] wire [2:0] a_bits_opcode; // @[SourceA.scala:43:15] wire [31:0] a_bits_address; // @[SourceA.scala:43:15] assign _a_bits_opcode_T = {2'h3, ~io_req_bits_block_0}; // @[SourceA.scala:33:7, :50:24] assign a_bits_opcode = _a_bits_opcode_T; // @[SourceA.scala:43:15, :50:24] wire [8:0] _a_bits_address_base_T_5 = a_bits_address_base_y; // @[Parameters.scala:221:15, :223:6] wire _a_bits_address_base_T_3 = ~_a_bits_address_base_T_2; // @[Parameters.scala:222:12] wire [10:0] _a_bits_address_base_T_11 = a_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6] wire _a_bits_address_base_T_9 = ~_a_bits_address_base_T_8; // @[Parameters.scala:222:12] wire _a_bits_address_base_T_15 = ~_a_bits_address_base_T_14; // @[Parameters.scala:222:12] wire [19:0] a_bits_address_base_hi = {_a_bits_address_base_T_5, _a_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19] wire [25:0] a_bits_address_base = {a_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19] wire _a_bits_address_T = a_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_1 = a_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_2 = a_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_3 = a_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_4 = a_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_5 = a_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_6 = a_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_7 = a_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_8 = a_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_9 = a_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_10 = a_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_11 = a_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_12 = a_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_13 = a_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_14 = a_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_15 = a_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_16 = a_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_17 = a_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_18 = a_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_19 = a_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_20 = a_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_21 = a_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_22 = a_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_23 = a_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_24 = a_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72] wire _a_bits_address_T_25 = a_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72] wire [1:0] a_bits_address_lo_lo_lo_lo = {_a_bits_address_T_1, _a_bits_address_T}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_lo_lo_hi = {_a_bits_address_T_3, _a_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_lo_lo = {a_bits_address_lo_lo_lo_hi, a_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_lo_hi_lo = {_a_bits_address_T_5, _a_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_lo_hi = {2'h0, a_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_lo_lo = {a_bits_address_lo_lo_hi, a_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_hi_lo_lo = {_a_bits_address_T_6, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_hi_lo_hi = {_a_bits_address_T_8, _a_bits_address_T_7}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_hi_lo = {a_bits_address_lo_hi_lo_hi, a_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_lo_hi_hi_lo = {_a_bits_address_T_10, _a_bits_address_T_9}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_lo_hi_hi_hi = {_a_bits_address_T_12, _a_bits_address_T_11}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_lo_hi_hi = {a_bits_address_lo_hi_hi_hi, a_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_lo_hi = {a_bits_address_lo_hi_hi, a_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] a_bits_address_lo = {a_bits_address_lo_hi, a_bits_address_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_lo_lo_lo = {_a_bits_address_T_14, _a_bits_address_T_13}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_lo_lo_hi = {_a_bits_address_T_16, _a_bits_address_T_15}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_lo_lo = {a_bits_address_hi_lo_lo_hi, a_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_lo_hi_lo = {_a_bits_address_T_18, _a_bits_address_T_17}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_lo_hi_hi = {_a_bits_address_T_20, _a_bits_address_T_19}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_lo_hi = {a_bits_address_hi_lo_hi_hi, a_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_hi_lo = {a_bits_address_hi_lo_hi, a_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_lo_lo = {_a_bits_address_T_22, _a_bits_address_T_21}; // @[Parameters.scala:229:72, :230:8] wire [1:0] a_bits_address_hi_hi_lo_hi = {_a_bits_address_T_24, _a_bits_address_T_23}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_hi_lo = {a_bits_address_hi_hi_lo_hi, a_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] a_bits_address_hi_hi_hi_hi = {_a_bits_address_T_25, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [3:0] a_bits_address_hi_hi_hi = {a_bits_address_hi_hi_hi_hi, 2'h0}; // @[Parameters.scala:230:8] wire [7:0] a_bits_address_hi_hi = {a_bits_address_hi_hi_hi, a_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] a_bits_address_hi = {a_bits_address_hi_hi, a_bits_address_hi_lo}; // @[Parameters.scala:230:8] assign _a_bits_address_T_26 = {a_bits_address_hi, a_bits_address_lo}; // @[Parameters.scala:230:8] assign a_bits_address = _a_bits_address_T_26; // @[SourceA.scala:43:15] Queue2_TLBundleA_a32d64s4k3z3c_3 io_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (a_ready), .io_enq_valid (a_valid), // @[SourceA.scala:43:15] .io_enq_bits_opcode (a_bits_opcode), // @[SourceA.scala:43:15] .io_enq_bits_param (a_bits_param), // @[SourceA.scala:43:15] .io_enq_bits_source (a_bits_source), // @[SourceA.scala:43:15] .io_enq_bits_address (a_bits_address), // @[SourceA.scala:43:15] .io_deq_ready (io_a_ready_0), // @[SourceA.scala:33:7] .io_deq_valid (io_a_valid_0), .io_deq_bits_opcode (io_a_bits_opcode_0), .io_deq_bits_param (io_a_bits_param_0), .io_deq_bits_size (io_a_bits_size_0), .io_deq_bits_source (io_a_bits_source_0), .io_deq_bits_address (io_a_bits_address_0), .io_deq_bits_mask (io_a_bits_mask_0), .io_deq_bits_data (io_a_bits_data_0), .io_deq_bits_corrupt (io_a_bits_corrupt_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceA.scala:33:7] assign io_a_valid = io_a_valid_0; // @[SourceA.scala:33:7] assign io_a_bits_opcode = io_a_bits_opcode_0; // @[SourceA.scala:33:7] assign io_a_bits_param = io_a_bits_param_0; // @[SourceA.scala:33:7] assign io_a_bits_size = io_a_bits_size_0; // @[SourceA.scala:33:7] assign io_a_bits_source = io_a_bits_source_0; // @[SourceA.scala:33:7] assign io_a_bits_address = io_a_bits_address_0; // @[SourceA.scala:33:7] assign io_a_bits_mask = io_a_bits_mask_0; // @[SourceA.scala:33:7] assign io_a_bits_data = io_a_bits_data_0; // @[SourceA.scala:33:7] assign io_a_bits_corrupt = io_a_bits_corrupt_0; // @[SourceA.scala:33:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module Switch_20 : input clock : Clock input reset : Reset output io : { in : { flip `2` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], flip `1` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], flip `0` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1]}, out : { `3` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], `2` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], `1` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], `0` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1]}, sel : { `3` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `2` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `1` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `0` : { flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1]}} wire in_flat : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[3] connect in_flat[0], io.in.`0`[0] connect in_flat[1], io.in.`1`[0] connect in_flat[2], io.in.`2`[0] node sel_flat_hi = cat(io.sel.`0`[0].`2`[0], io.sel.`0`[0].`1`[0]) node sel_flat = cat(sel_flat_hi, io.sel.`0`[0].`0`[0]) node _T = bits(sel_flat, 0, 0) node _T_1 = bits(sel_flat, 1, 1) node _T_2 = bits(sel_flat, 2, 2) node _T_3 = add(_T_1, _T_2) node _T_4 = bits(_T_3, 1, 0) node _T_5 = add(_T, _T_4) node _T_6 = bits(_T_5, 1, 0) node _T_7 = leq(_T_6, UInt<1>(0h1)) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _io_out_0_0_valid_T = bits(sel_flat, 0, 0) node _io_out_0_0_valid_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_valid_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_valid_T_3 = mux(_io_out_0_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_4 = mux(_io_out_0_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_5 = mux(_io_out_0_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_0_0_valid_T_6 = or(_io_out_0_0_valid_T_3, _io_out_0_0_valid_T_4) node _io_out_0_0_valid_T_7 = or(_io_out_0_0_valid_T_6, _io_out_0_0_valid_T_5) wire _io_out_0_0_valid_WIRE : UInt<1> connect _io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_7 node _io_out_0_0_valid_T_8 = neq(sel_flat, UInt<1>(0h0)) node _io_out_0_0_valid_T_9 = and(_io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_8) connect io.out.`0`[0].valid, _io_out_0_0_valid_T_9 node _io_out_0_0_bits_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_T_2 = bits(sel_flat, 2, 2) wire _io_out_0_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_0_0_bits_T_3 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_4 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_5 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_6 = or(_io_out_0_0_bits_T_3, _io_out_0_0_bits_T_4) node _io_out_0_0_bits_T_7 = or(_io_out_0_0_bits_T_6, _io_out_0_0_bits_T_5) wire _io_out_0_0_bits_WIRE_1 : UInt<1> connect _io_out_0_0_bits_WIRE_1, _io_out_0_0_bits_T_7 connect _io_out_0_0_bits_WIRE.virt_channel_id, _io_out_0_0_bits_WIRE_1 wire _io_out_0_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_0_0_bits_T_8 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_9 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_10 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_11 = or(_io_out_0_0_bits_T_8, _io_out_0_0_bits_T_9) node _io_out_0_0_bits_T_12 = or(_io_out_0_0_bits_T_11, _io_out_0_0_bits_T_10) wire _io_out_0_0_bits_WIRE_3 : UInt<2> connect _io_out_0_0_bits_WIRE_3, _io_out_0_0_bits_T_12 connect _io_out_0_0_bits_WIRE_2.egress_node_id, _io_out_0_0_bits_WIRE_3 node _io_out_0_0_bits_T_13 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_14 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_15 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_16 = or(_io_out_0_0_bits_T_13, _io_out_0_0_bits_T_14) node _io_out_0_0_bits_T_17 = or(_io_out_0_0_bits_T_16, _io_out_0_0_bits_T_15) wire _io_out_0_0_bits_WIRE_4 : UInt<4> connect _io_out_0_0_bits_WIRE_4, _io_out_0_0_bits_T_17 connect _io_out_0_0_bits_WIRE_2.egress_node, _io_out_0_0_bits_WIRE_4 node _io_out_0_0_bits_T_18 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_19 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_20 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_21 = or(_io_out_0_0_bits_T_18, _io_out_0_0_bits_T_19) node _io_out_0_0_bits_T_22 = or(_io_out_0_0_bits_T_21, _io_out_0_0_bits_T_20) wire _io_out_0_0_bits_WIRE_5 : UInt<2> connect _io_out_0_0_bits_WIRE_5, _io_out_0_0_bits_T_22 connect _io_out_0_0_bits_WIRE_2.ingress_node_id, _io_out_0_0_bits_WIRE_5 node _io_out_0_0_bits_T_23 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_24 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_25 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_0_0_bits_T_26 = or(_io_out_0_0_bits_T_23, _io_out_0_0_bits_T_24) node _io_out_0_0_bits_T_27 = or(_io_out_0_0_bits_T_26, _io_out_0_0_bits_T_25) wire _io_out_0_0_bits_WIRE_6 : UInt<4> connect _io_out_0_0_bits_WIRE_6, _io_out_0_0_bits_T_27 connect _io_out_0_0_bits_WIRE_2.ingress_node, _io_out_0_0_bits_WIRE_6 node _io_out_0_0_bits_T_28 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_29 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_30 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_0_0_bits_T_31 = or(_io_out_0_0_bits_T_28, _io_out_0_0_bits_T_29) node _io_out_0_0_bits_T_32 = or(_io_out_0_0_bits_T_31, _io_out_0_0_bits_T_30) wire _io_out_0_0_bits_WIRE_7 : UInt<1> connect _io_out_0_0_bits_WIRE_7, _io_out_0_0_bits_T_32 connect _io_out_0_0_bits_WIRE_2.vnet_id, _io_out_0_0_bits_WIRE_7 connect _io_out_0_0_bits_WIRE.flow, _io_out_0_0_bits_WIRE_2 node _io_out_0_0_bits_T_33 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_34 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_35 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_0_0_bits_T_36 = or(_io_out_0_0_bits_T_33, _io_out_0_0_bits_T_34) node _io_out_0_0_bits_T_37 = or(_io_out_0_0_bits_T_36, _io_out_0_0_bits_T_35) wire _io_out_0_0_bits_WIRE_8 : UInt<37> connect _io_out_0_0_bits_WIRE_8, _io_out_0_0_bits_T_37 connect _io_out_0_0_bits_WIRE.payload, _io_out_0_0_bits_WIRE_8 node _io_out_0_0_bits_T_38 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_39 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_40 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_0_0_bits_T_41 = or(_io_out_0_0_bits_T_38, _io_out_0_0_bits_T_39) node _io_out_0_0_bits_T_42 = or(_io_out_0_0_bits_T_41, _io_out_0_0_bits_T_40) wire _io_out_0_0_bits_WIRE_9 : UInt<1> connect _io_out_0_0_bits_WIRE_9, _io_out_0_0_bits_T_42 connect _io_out_0_0_bits_WIRE.tail, _io_out_0_0_bits_WIRE_9 node _io_out_0_0_bits_T_43 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_44 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_45 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_0_0_bits_T_46 = or(_io_out_0_0_bits_T_43, _io_out_0_0_bits_T_44) node _io_out_0_0_bits_T_47 = or(_io_out_0_0_bits_T_46, _io_out_0_0_bits_T_45) wire _io_out_0_0_bits_WIRE_10 : UInt<1> connect _io_out_0_0_bits_WIRE_10, _io_out_0_0_bits_T_47 connect _io_out_0_0_bits_WIRE.head, _io_out_0_0_bits_WIRE_10 connect io.out.`0`[0].bits, _io_out_0_0_bits_WIRE node _io_out_0_0_bits_virt_channel_id_T = bits(sel_flat, 0, 0) node _io_out_0_0_bits_virt_channel_id_T_1 = bits(sel_flat, 1, 1) node _io_out_0_0_bits_virt_channel_id_T_2 = bits(sel_flat, 2, 2) node _io_out_0_0_bits_virt_channel_id_T_3 = mux(_io_out_0_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_4 = mux(_io_out_0_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_5 = mux(_io_out_0_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_0_0_bits_virt_channel_id_T_6 = or(_io_out_0_0_bits_virt_channel_id_T_3, _io_out_0_0_bits_virt_channel_id_T_4) node _io_out_0_0_bits_virt_channel_id_T_7 = or(_io_out_0_0_bits_virt_channel_id_T_6, _io_out_0_0_bits_virt_channel_id_T_5) wire _io_out_0_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_0_0_bits_virt_channel_id_WIRE, _io_out_0_0_bits_virt_channel_id_T_7 connect io.out.`0`[0].bits.virt_channel_id, _io_out_0_0_bits_virt_channel_id_WIRE node sel_flat_hi_1 = cat(io.sel.`1`[0].`2`[0], io.sel.`1`[0].`1`[0]) node sel_flat_1 = cat(sel_flat_hi_1, io.sel.`1`[0].`0`[0]) node _T_11 = bits(sel_flat_1, 0, 0) node _T_12 = bits(sel_flat_1, 1, 1) node _T_13 = bits(sel_flat_1, 2, 2) node _T_14 = add(_T_12, _T_13) node _T_15 = bits(_T_14, 1, 0) node _T_16 = add(_T_11, _T_15) node _T_17 = bits(_T_16, 1, 0) node _T_18 = leq(_T_17, UInt<1>(0h1)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_1 assert(clock, _T_18, UInt<1>(0h1), "") : assert_1 node _io_out_1_0_valid_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_valid_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_valid_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_valid_T_3 = mux(_io_out_1_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_4 = mux(_io_out_1_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_5 = mux(_io_out_1_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_1_0_valid_T_6 = or(_io_out_1_0_valid_T_3, _io_out_1_0_valid_T_4) node _io_out_1_0_valid_T_7 = or(_io_out_1_0_valid_T_6, _io_out_1_0_valid_T_5) wire _io_out_1_0_valid_WIRE : UInt<1> connect _io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_7 node _io_out_1_0_valid_T_8 = neq(sel_flat_1, UInt<1>(0h0)) node _io_out_1_0_valid_T_9 = and(_io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_8) connect io.out.`1`[0].valid, _io_out_1_0_valid_T_9 node _io_out_1_0_bits_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_T_2 = bits(sel_flat_1, 2, 2) wire _io_out_1_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_1_0_bits_T_3 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_4 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_5 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_6 = or(_io_out_1_0_bits_T_3, _io_out_1_0_bits_T_4) node _io_out_1_0_bits_T_7 = or(_io_out_1_0_bits_T_6, _io_out_1_0_bits_T_5) wire _io_out_1_0_bits_WIRE_1 : UInt<1> connect _io_out_1_0_bits_WIRE_1, _io_out_1_0_bits_T_7 connect _io_out_1_0_bits_WIRE.virt_channel_id, _io_out_1_0_bits_WIRE_1 wire _io_out_1_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_1_0_bits_T_8 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_9 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_10 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_11 = or(_io_out_1_0_bits_T_8, _io_out_1_0_bits_T_9) node _io_out_1_0_bits_T_12 = or(_io_out_1_0_bits_T_11, _io_out_1_0_bits_T_10) wire _io_out_1_0_bits_WIRE_3 : UInt<2> connect _io_out_1_0_bits_WIRE_3, _io_out_1_0_bits_T_12 connect _io_out_1_0_bits_WIRE_2.egress_node_id, _io_out_1_0_bits_WIRE_3 node _io_out_1_0_bits_T_13 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_14 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_15 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_16 = or(_io_out_1_0_bits_T_13, _io_out_1_0_bits_T_14) node _io_out_1_0_bits_T_17 = or(_io_out_1_0_bits_T_16, _io_out_1_0_bits_T_15) wire _io_out_1_0_bits_WIRE_4 : UInt<4> connect _io_out_1_0_bits_WIRE_4, _io_out_1_0_bits_T_17 connect _io_out_1_0_bits_WIRE_2.egress_node, _io_out_1_0_bits_WIRE_4 node _io_out_1_0_bits_T_18 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_19 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_20 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_21 = or(_io_out_1_0_bits_T_18, _io_out_1_0_bits_T_19) node _io_out_1_0_bits_T_22 = or(_io_out_1_0_bits_T_21, _io_out_1_0_bits_T_20) wire _io_out_1_0_bits_WIRE_5 : UInt<2> connect _io_out_1_0_bits_WIRE_5, _io_out_1_0_bits_T_22 connect _io_out_1_0_bits_WIRE_2.ingress_node_id, _io_out_1_0_bits_WIRE_5 node _io_out_1_0_bits_T_23 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_24 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_25 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_1_0_bits_T_26 = or(_io_out_1_0_bits_T_23, _io_out_1_0_bits_T_24) node _io_out_1_0_bits_T_27 = or(_io_out_1_0_bits_T_26, _io_out_1_0_bits_T_25) wire _io_out_1_0_bits_WIRE_6 : UInt<4> connect _io_out_1_0_bits_WIRE_6, _io_out_1_0_bits_T_27 connect _io_out_1_0_bits_WIRE_2.ingress_node, _io_out_1_0_bits_WIRE_6 node _io_out_1_0_bits_T_28 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_29 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_30 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_1_0_bits_T_31 = or(_io_out_1_0_bits_T_28, _io_out_1_0_bits_T_29) node _io_out_1_0_bits_T_32 = or(_io_out_1_0_bits_T_31, _io_out_1_0_bits_T_30) wire _io_out_1_0_bits_WIRE_7 : UInt<1> connect _io_out_1_0_bits_WIRE_7, _io_out_1_0_bits_T_32 connect _io_out_1_0_bits_WIRE_2.vnet_id, _io_out_1_0_bits_WIRE_7 connect _io_out_1_0_bits_WIRE.flow, _io_out_1_0_bits_WIRE_2 node _io_out_1_0_bits_T_33 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_34 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_35 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_1_0_bits_T_36 = or(_io_out_1_0_bits_T_33, _io_out_1_0_bits_T_34) node _io_out_1_0_bits_T_37 = or(_io_out_1_0_bits_T_36, _io_out_1_0_bits_T_35) wire _io_out_1_0_bits_WIRE_8 : UInt<37> connect _io_out_1_0_bits_WIRE_8, _io_out_1_0_bits_T_37 connect _io_out_1_0_bits_WIRE.payload, _io_out_1_0_bits_WIRE_8 node _io_out_1_0_bits_T_38 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_39 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_40 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_1_0_bits_T_41 = or(_io_out_1_0_bits_T_38, _io_out_1_0_bits_T_39) node _io_out_1_0_bits_T_42 = or(_io_out_1_0_bits_T_41, _io_out_1_0_bits_T_40) wire _io_out_1_0_bits_WIRE_9 : UInt<1> connect _io_out_1_0_bits_WIRE_9, _io_out_1_0_bits_T_42 connect _io_out_1_0_bits_WIRE.tail, _io_out_1_0_bits_WIRE_9 node _io_out_1_0_bits_T_43 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_44 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_45 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_1_0_bits_T_46 = or(_io_out_1_0_bits_T_43, _io_out_1_0_bits_T_44) node _io_out_1_0_bits_T_47 = or(_io_out_1_0_bits_T_46, _io_out_1_0_bits_T_45) wire _io_out_1_0_bits_WIRE_10 : UInt<1> connect _io_out_1_0_bits_WIRE_10, _io_out_1_0_bits_T_47 connect _io_out_1_0_bits_WIRE.head, _io_out_1_0_bits_WIRE_10 connect io.out.`1`[0].bits, _io_out_1_0_bits_WIRE node _io_out_1_0_bits_virt_channel_id_T = bits(sel_flat_1, 0, 0) node _io_out_1_0_bits_virt_channel_id_T_1 = bits(sel_flat_1, 1, 1) node _io_out_1_0_bits_virt_channel_id_T_2 = bits(sel_flat_1, 2, 2) node _io_out_1_0_bits_virt_channel_id_T_3 = mux(_io_out_1_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_4 = mux(_io_out_1_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_5 = mux(_io_out_1_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_1_0_bits_virt_channel_id_T_6 = or(_io_out_1_0_bits_virt_channel_id_T_3, _io_out_1_0_bits_virt_channel_id_T_4) node _io_out_1_0_bits_virt_channel_id_T_7 = or(_io_out_1_0_bits_virt_channel_id_T_6, _io_out_1_0_bits_virt_channel_id_T_5) wire _io_out_1_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_1_0_bits_virt_channel_id_WIRE, _io_out_1_0_bits_virt_channel_id_T_7 connect io.out.`1`[0].bits.virt_channel_id, _io_out_1_0_bits_virt_channel_id_WIRE node sel_flat_hi_2 = cat(io.sel.`2`[0].`2`[0], io.sel.`2`[0].`1`[0]) node sel_flat_2 = cat(sel_flat_hi_2, io.sel.`2`[0].`0`[0]) node _T_22 = bits(sel_flat_2, 0, 0) node _T_23 = bits(sel_flat_2, 1, 1) node _T_24 = bits(sel_flat_2, 2, 2) node _T_25 = add(_T_23, _T_24) node _T_26 = bits(_T_25, 1, 0) node _T_27 = add(_T_22, _T_26) node _T_28 = bits(_T_27, 1, 0) node _T_29 = leq(_T_28, UInt<1>(0h1)) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_2 assert(clock, _T_29, UInt<1>(0h1), "") : assert_2 node _io_out_2_0_valid_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_valid_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_valid_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_valid_T_3 = mux(_io_out_2_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_4 = mux(_io_out_2_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_5 = mux(_io_out_2_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_2_0_valid_T_6 = or(_io_out_2_0_valid_T_3, _io_out_2_0_valid_T_4) node _io_out_2_0_valid_T_7 = or(_io_out_2_0_valid_T_6, _io_out_2_0_valid_T_5) wire _io_out_2_0_valid_WIRE : UInt<1> connect _io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_7 node _io_out_2_0_valid_T_8 = neq(sel_flat_2, UInt<1>(0h0)) node _io_out_2_0_valid_T_9 = and(_io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_8) connect io.out.`2`[0].valid, _io_out_2_0_valid_T_9 node _io_out_2_0_bits_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_T_2 = bits(sel_flat_2, 2, 2) wire _io_out_2_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_2_0_bits_T_3 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_4 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_5 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_6 = or(_io_out_2_0_bits_T_3, _io_out_2_0_bits_T_4) node _io_out_2_0_bits_T_7 = or(_io_out_2_0_bits_T_6, _io_out_2_0_bits_T_5) wire _io_out_2_0_bits_WIRE_1 : UInt<1> connect _io_out_2_0_bits_WIRE_1, _io_out_2_0_bits_T_7 connect _io_out_2_0_bits_WIRE.virt_channel_id, _io_out_2_0_bits_WIRE_1 wire _io_out_2_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_2_0_bits_T_8 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_9 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_10 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_11 = or(_io_out_2_0_bits_T_8, _io_out_2_0_bits_T_9) node _io_out_2_0_bits_T_12 = or(_io_out_2_0_bits_T_11, _io_out_2_0_bits_T_10) wire _io_out_2_0_bits_WIRE_3 : UInt<2> connect _io_out_2_0_bits_WIRE_3, _io_out_2_0_bits_T_12 connect _io_out_2_0_bits_WIRE_2.egress_node_id, _io_out_2_0_bits_WIRE_3 node _io_out_2_0_bits_T_13 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_14 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_15 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_16 = or(_io_out_2_0_bits_T_13, _io_out_2_0_bits_T_14) node _io_out_2_0_bits_T_17 = or(_io_out_2_0_bits_T_16, _io_out_2_0_bits_T_15) wire _io_out_2_0_bits_WIRE_4 : UInt<4> connect _io_out_2_0_bits_WIRE_4, _io_out_2_0_bits_T_17 connect _io_out_2_0_bits_WIRE_2.egress_node, _io_out_2_0_bits_WIRE_4 node _io_out_2_0_bits_T_18 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_19 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_20 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_21 = or(_io_out_2_0_bits_T_18, _io_out_2_0_bits_T_19) node _io_out_2_0_bits_T_22 = or(_io_out_2_0_bits_T_21, _io_out_2_0_bits_T_20) wire _io_out_2_0_bits_WIRE_5 : UInt<2> connect _io_out_2_0_bits_WIRE_5, _io_out_2_0_bits_T_22 connect _io_out_2_0_bits_WIRE_2.ingress_node_id, _io_out_2_0_bits_WIRE_5 node _io_out_2_0_bits_T_23 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_24 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_25 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_2_0_bits_T_26 = or(_io_out_2_0_bits_T_23, _io_out_2_0_bits_T_24) node _io_out_2_0_bits_T_27 = or(_io_out_2_0_bits_T_26, _io_out_2_0_bits_T_25) wire _io_out_2_0_bits_WIRE_6 : UInt<4> connect _io_out_2_0_bits_WIRE_6, _io_out_2_0_bits_T_27 connect _io_out_2_0_bits_WIRE_2.ingress_node, _io_out_2_0_bits_WIRE_6 node _io_out_2_0_bits_T_28 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_29 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_30 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_2_0_bits_T_31 = or(_io_out_2_0_bits_T_28, _io_out_2_0_bits_T_29) node _io_out_2_0_bits_T_32 = or(_io_out_2_0_bits_T_31, _io_out_2_0_bits_T_30) wire _io_out_2_0_bits_WIRE_7 : UInt<1> connect _io_out_2_0_bits_WIRE_7, _io_out_2_0_bits_T_32 connect _io_out_2_0_bits_WIRE_2.vnet_id, _io_out_2_0_bits_WIRE_7 connect _io_out_2_0_bits_WIRE.flow, _io_out_2_0_bits_WIRE_2 node _io_out_2_0_bits_T_33 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_34 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_35 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_2_0_bits_T_36 = or(_io_out_2_0_bits_T_33, _io_out_2_0_bits_T_34) node _io_out_2_0_bits_T_37 = or(_io_out_2_0_bits_T_36, _io_out_2_0_bits_T_35) wire _io_out_2_0_bits_WIRE_8 : UInt<37> connect _io_out_2_0_bits_WIRE_8, _io_out_2_0_bits_T_37 connect _io_out_2_0_bits_WIRE.payload, _io_out_2_0_bits_WIRE_8 node _io_out_2_0_bits_T_38 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_39 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_40 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_2_0_bits_T_41 = or(_io_out_2_0_bits_T_38, _io_out_2_0_bits_T_39) node _io_out_2_0_bits_T_42 = or(_io_out_2_0_bits_T_41, _io_out_2_0_bits_T_40) wire _io_out_2_0_bits_WIRE_9 : UInt<1> connect _io_out_2_0_bits_WIRE_9, _io_out_2_0_bits_T_42 connect _io_out_2_0_bits_WIRE.tail, _io_out_2_0_bits_WIRE_9 node _io_out_2_0_bits_T_43 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_44 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_45 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_2_0_bits_T_46 = or(_io_out_2_0_bits_T_43, _io_out_2_0_bits_T_44) node _io_out_2_0_bits_T_47 = or(_io_out_2_0_bits_T_46, _io_out_2_0_bits_T_45) wire _io_out_2_0_bits_WIRE_10 : UInt<1> connect _io_out_2_0_bits_WIRE_10, _io_out_2_0_bits_T_47 connect _io_out_2_0_bits_WIRE.head, _io_out_2_0_bits_WIRE_10 connect io.out.`2`[0].bits, _io_out_2_0_bits_WIRE node _io_out_2_0_bits_virt_channel_id_T = bits(sel_flat_2, 0, 0) node _io_out_2_0_bits_virt_channel_id_T_1 = bits(sel_flat_2, 1, 1) node _io_out_2_0_bits_virt_channel_id_T_2 = bits(sel_flat_2, 2, 2) node _io_out_2_0_bits_virt_channel_id_T_3 = mux(_io_out_2_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_4 = mux(_io_out_2_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_5 = mux(_io_out_2_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_2_0_bits_virt_channel_id_T_6 = or(_io_out_2_0_bits_virt_channel_id_T_3, _io_out_2_0_bits_virt_channel_id_T_4) node _io_out_2_0_bits_virt_channel_id_T_7 = or(_io_out_2_0_bits_virt_channel_id_T_6, _io_out_2_0_bits_virt_channel_id_T_5) wire _io_out_2_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_2_0_bits_virt_channel_id_WIRE, _io_out_2_0_bits_virt_channel_id_T_7 connect io.out.`2`[0].bits.virt_channel_id, _io_out_2_0_bits_virt_channel_id_WIRE node sel_flat_hi_3 = cat(io.sel.`3`[0].`2`[0], io.sel.`3`[0].`1`[0]) node sel_flat_3 = cat(sel_flat_hi_3, io.sel.`3`[0].`0`[0]) node _T_33 = bits(sel_flat_3, 0, 0) node _T_34 = bits(sel_flat_3, 1, 1) node _T_35 = bits(sel_flat_3, 2, 2) node _T_36 = add(_T_34, _T_35) node _T_37 = bits(_T_36, 1, 0) node _T_38 = add(_T_33, _T_37) node _T_39 = bits(_T_38, 1, 0) node _T_40 = leq(_T_39, UInt<1>(0h1)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_3 assert(clock, _T_40, UInt<1>(0h1), "") : assert_3 node _io_out_3_0_valid_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_valid_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_valid_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_valid_T_3 = mux(_io_out_3_0_valid_T, in_flat[0].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_4 = mux(_io_out_3_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_5 = mux(_io_out_3_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0)) node _io_out_3_0_valid_T_6 = or(_io_out_3_0_valid_T_3, _io_out_3_0_valid_T_4) node _io_out_3_0_valid_T_7 = or(_io_out_3_0_valid_T_6, _io_out_3_0_valid_T_5) wire _io_out_3_0_valid_WIRE : UInt<1> connect _io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_7 node _io_out_3_0_valid_T_8 = neq(sel_flat_3, UInt<1>(0h0)) node _io_out_3_0_valid_T_9 = and(_io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_8) connect io.out.`3`[0].valid, _io_out_3_0_valid_T_9 node _io_out_3_0_bits_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_T_2 = bits(sel_flat_3, 2, 2) wire _io_out_3_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>} node _io_out_3_0_bits_T_3 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_4 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_5 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_6 = or(_io_out_3_0_bits_T_3, _io_out_3_0_bits_T_4) node _io_out_3_0_bits_T_7 = or(_io_out_3_0_bits_T_6, _io_out_3_0_bits_T_5) wire _io_out_3_0_bits_WIRE_1 : UInt<1> connect _io_out_3_0_bits_WIRE_1, _io_out_3_0_bits_T_7 connect _io_out_3_0_bits_WIRE.virt_channel_id, _io_out_3_0_bits_WIRE_1 wire _io_out_3_0_bits_WIRE_2 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_out_3_0_bits_T_8 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_9 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_10 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_11 = or(_io_out_3_0_bits_T_8, _io_out_3_0_bits_T_9) node _io_out_3_0_bits_T_12 = or(_io_out_3_0_bits_T_11, _io_out_3_0_bits_T_10) wire _io_out_3_0_bits_WIRE_3 : UInt<2> connect _io_out_3_0_bits_WIRE_3, _io_out_3_0_bits_T_12 connect _io_out_3_0_bits_WIRE_2.egress_node_id, _io_out_3_0_bits_WIRE_3 node _io_out_3_0_bits_T_13 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_14 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_15 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_16 = or(_io_out_3_0_bits_T_13, _io_out_3_0_bits_T_14) node _io_out_3_0_bits_T_17 = or(_io_out_3_0_bits_T_16, _io_out_3_0_bits_T_15) wire _io_out_3_0_bits_WIRE_4 : UInt<4> connect _io_out_3_0_bits_WIRE_4, _io_out_3_0_bits_T_17 connect _io_out_3_0_bits_WIRE_2.egress_node, _io_out_3_0_bits_WIRE_4 node _io_out_3_0_bits_T_18 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_19 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_20 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_21 = or(_io_out_3_0_bits_T_18, _io_out_3_0_bits_T_19) node _io_out_3_0_bits_T_22 = or(_io_out_3_0_bits_T_21, _io_out_3_0_bits_T_20) wire _io_out_3_0_bits_WIRE_5 : UInt<2> connect _io_out_3_0_bits_WIRE_5, _io_out_3_0_bits_T_22 connect _io_out_3_0_bits_WIRE_2.ingress_node_id, _io_out_3_0_bits_WIRE_5 node _io_out_3_0_bits_T_23 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_24 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_25 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0)) node _io_out_3_0_bits_T_26 = or(_io_out_3_0_bits_T_23, _io_out_3_0_bits_T_24) node _io_out_3_0_bits_T_27 = or(_io_out_3_0_bits_T_26, _io_out_3_0_bits_T_25) wire _io_out_3_0_bits_WIRE_6 : UInt<4> connect _io_out_3_0_bits_WIRE_6, _io_out_3_0_bits_T_27 connect _io_out_3_0_bits_WIRE_2.ingress_node, _io_out_3_0_bits_WIRE_6 node _io_out_3_0_bits_T_28 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_29 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_30 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0)) node _io_out_3_0_bits_T_31 = or(_io_out_3_0_bits_T_28, _io_out_3_0_bits_T_29) node _io_out_3_0_bits_T_32 = or(_io_out_3_0_bits_T_31, _io_out_3_0_bits_T_30) wire _io_out_3_0_bits_WIRE_7 : UInt<1> connect _io_out_3_0_bits_WIRE_7, _io_out_3_0_bits_T_32 connect _io_out_3_0_bits_WIRE_2.vnet_id, _io_out_3_0_bits_WIRE_7 connect _io_out_3_0_bits_WIRE.flow, _io_out_3_0_bits_WIRE_2 node _io_out_3_0_bits_T_33 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_34 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_35 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0)) node _io_out_3_0_bits_T_36 = or(_io_out_3_0_bits_T_33, _io_out_3_0_bits_T_34) node _io_out_3_0_bits_T_37 = or(_io_out_3_0_bits_T_36, _io_out_3_0_bits_T_35) wire _io_out_3_0_bits_WIRE_8 : UInt<37> connect _io_out_3_0_bits_WIRE_8, _io_out_3_0_bits_T_37 connect _io_out_3_0_bits_WIRE.payload, _io_out_3_0_bits_WIRE_8 node _io_out_3_0_bits_T_38 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_39 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_40 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0)) node _io_out_3_0_bits_T_41 = or(_io_out_3_0_bits_T_38, _io_out_3_0_bits_T_39) node _io_out_3_0_bits_T_42 = or(_io_out_3_0_bits_T_41, _io_out_3_0_bits_T_40) wire _io_out_3_0_bits_WIRE_9 : UInt<1> connect _io_out_3_0_bits_WIRE_9, _io_out_3_0_bits_T_42 connect _io_out_3_0_bits_WIRE.tail, _io_out_3_0_bits_WIRE_9 node _io_out_3_0_bits_T_43 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_44 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_45 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0)) node _io_out_3_0_bits_T_46 = or(_io_out_3_0_bits_T_43, _io_out_3_0_bits_T_44) node _io_out_3_0_bits_T_47 = or(_io_out_3_0_bits_T_46, _io_out_3_0_bits_T_45) wire _io_out_3_0_bits_WIRE_10 : UInt<1> connect _io_out_3_0_bits_WIRE_10, _io_out_3_0_bits_T_47 connect _io_out_3_0_bits_WIRE.head, _io_out_3_0_bits_WIRE_10 connect io.out.`3`[0].bits, _io_out_3_0_bits_WIRE node _io_out_3_0_bits_virt_channel_id_T = bits(sel_flat_3, 0, 0) node _io_out_3_0_bits_virt_channel_id_T_1 = bits(sel_flat_3, 1, 1) node _io_out_3_0_bits_virt_channel_id_T_2 = bits(sel_flat_3, 2, 2) node _io_out_3_0_bits_virt_channel_id_T_3 = mux(_io_out_3_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_4 = mux(_io_out_3_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_5 = mux(_io_out_3_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0)) node _io_out_3_0_bits_virt_channel_id_T_6 = or(_io_out_3_0_bits_virt_channel_id_T_3, _io_out_3_0_bits_virt_channel_id_T_4) node _io_out_3_0_bits_virt_channel_id_T_7 = or(_io_out_3_0_bits_virt_channel_id_T_6, _io_out_3_0_bits_virt_channel_id_T_5) wire _io_out_3_0_bits_virt_channel_id_WIRE : UInt<1> connect _io_out_3_0_bits_virt_channel_id_WIRE, _io_out_3_0_bits_virt_channel_id_T_7 connect io.out.`3`[0].bits.virt_channel_id, _io_out_3_0_bits_virt_channel_id_WIRE

module Switch_20( // @[Switch.scala:16:7] input clock, // @[Switch.scala:16:7] input reset, // @[Switch.scala:16:7] input io_in_2_0_valid, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_tail, // @[Switch.scala:27:14] input [36:0] io_in_2_0_bits_flit_payload, // @[Switch.scala:27:14] input io_in_2_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_2_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [1:0] io_in_2_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_2_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_2_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input io_in_2_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_1_0_valid, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14] input [36:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14] input io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [1:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14] input io_in_0_0_valid, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14] input [36:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14] input io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14] input [1:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14] input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14] input [1:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14] input io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14] output io_out_3_0_valid, // @[Switch.scala:27:14] output io_out_3_0_bits_head, // @[Switch.scala:27:14] output io_out_3_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14] output [3:0] io_out_3_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_3_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output io_out_2_0_valid, // @[Switch.scala:27:14] output io_out_2_0_bits_head, // @[Switch.scala:27:14] output io_out_2_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14] output io_out_2_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_2_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_2_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_2_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_2_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output io_out_2_0_bits_virt_channel_id, // @[Switch.scala:27:14] output io_out_1_0_valid, // @[Switch.scala:27:14] output io_out_1_0_bits_head, // @[Switch.scala:27:14] output io_out_1_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14] output io_out_1_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_1_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_1_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output io_out_1_0_bits_virt_channel_id, // @[Switch.scala:27:14] output io_out_0_0_valid, // @[Switch.scala:27:14] output io_out_0_0_bits_head, // @[Switch.scala:27:14] output io_out_0_0_bits_tail, // @[Switch.scala:27:14] output [36:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14] output io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14] output [1:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14] output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14] output [1:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14] output io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14] input io_sel_3_0_2_0, // @[Switch.scala:27:14] input io_sel_3_0_1_0, // @[Switch.scala:27:14] input io_sel_3_0_0_0, // @[Switch.scala:27:14] input io_sel_2_0_2_0, // @[Switch.scala:27:14] input io_sel_2_0_1_0, // @[Switch.scala:27:14] input io_sel_2_0_0_0, // @[Switch.scala:27:14] input io_sel_1_0_2_0, // @[Switch.scala:27:14] input io_sel_0_0_2_0, // @[Switch.scala:27:14] input io_sel_0_0_1_0, // @[Switch.scala:27:14] input io_sel_0_0_0_0 // @[Switch.scala:27:14] );

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_79 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2

module NoCMonitor_79( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 6) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 6) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_37 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_47, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<6>(0h20)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<6>(0h21)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<6>(0h22)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<6>(0h23)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0) node _T_64 = shr(io.in.a.bits.source, 6) node _T_65 = eq(_T_64, UInt<1>(0h1)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0) node _T_77 = shr(io.in.a.bits.source, 6) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_93 = cvt(_T_92) node _T_94 = and(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = asSInt(_T_94) node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0))) node _T_97 = or(_T_91, _T_96) node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = and(_T_11, _T_24) node _T_115 = and(_T_114, _T_37) node _T_116 = and(_T_115, _T_50) node _T_117 = and(_T_116, _T_63) node _T_118 = and(_T_117, _T_76) node _T_119 = and(_T_118, _T_89) node _T_120 = and(_T_119, _T_97) node _T_121 = and(_T_120, _T_105) node _T_122 = and(_T_121, _T_113) node _T_123 = asUInt(reset) node _T_124 = eq(_T_123, UInt<1>(0h0)) when _T_124 : node _T_125 = eq(_T_122, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_122, UInt<1>(0h1), "") : assert_1 node _T_126 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_126 : node _T_127 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_128 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_131 = shr(io.in.a.bits.source, 2) node _T_132 = eq(_T_131, UInt<6>(0h20)) node _T_133 = leq(UInt<1>(0h0), uncommonBits_6) node _T_134 = and(_T_132, _T_133) node _T_135 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_136 = and(_T_134, _T_135) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_137 = shr(io.in.a.bits.source, 2) node _T_138 = eq(_T_137, UInt<6>(0h21)) node _T_139 = leq(UInt<1>(0h0), uncommonBits_7) node _T_140 = and(_T_138, _T_139) node _T_141 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_142 = and(_T_140, _T_141) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_143 = shr(io.in.a.bits.source, 2) node _T_144 = eq(_T_143, UInt<6>(0h22)) node _T_145 = leq(UInt<1>(0h0), uncommonBits_8) node _T_146 = and(_T_144, _T_145) node _T_147 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_149 = shr(io.in.a.bits.source, 2) node _T_150 = eq(_T_149, UInt<6>(0h23)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_9) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0) node _T_155 = shr(io.in.a.bits.source, 6) node _T_156 = eq(_T_155, UInt<1>(0h1)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_10) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_10, UInt<6>(0h3f)) node _T_160 = and(_T_158, _T_159) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0) node _T_161 = shr(io.in.a.bits.source, 6) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = leq(UInt<1>(0h0), uncommonBits_11) node _T_164 = and(_T_162, _T_163) node _T_165 = leq(uncommonBits_11, UInt<6>(0h3f)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_168 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_169 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_170 = or(_T_130, _T_136) node _T_171 = or(_T_170, _T_142) node _T_172 = or(_T_171, _T_148) node _T_173 = or(_T_172, _T_154) node _T_174 = or(_T_173, _T_160) node _T_175 = or(_T_174, _T_166) node _T_176 = or(_T_175, _T_167) node _T_177 = or(_T_176, _T_168) node _T_178 = or(_T_177, _T_169) node _T_179 = and(_T_129, _T_178) node _T_180 = or(UInt<1>(0h0), _T_179) node _T_181 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<14>(0h2000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_188 = cvt(_T_187) node _T_189 = and(_T_188, asSInt(UInt<13>(0h1000))) node _T_190 = asSInt(_T_189) node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0))) node _T_192 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<17>(0h10000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<18>(0h2f000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<17>(0h10000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<13>(0h1000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<27>(0h4000000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<13>(0h1000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = or(_T_186, _T_191) node _T_223 = or(_T_222, _T_196) node _T_224 = or(_T_223, _T_201) node _T_225 = or(_T_224, _T_206) node _T_226 = or(_T_225, _T_211) node _T_227 = or(_T_226, _T_216) node _T_228 = or(_T_227, _T_221) node _T_229 = and(_T_181, _T_228) node _T_230 = or(UInt<1>(0h0), _T_229) node _T_231 = and(_T_180, _T_230) node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : node _T_234 = eq(_T_231, UInt<1>(0h0)) when _T_234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_231, UInt<1>(0h1), "") : assert_2 node _T_235 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<6>(0h20)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_12) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<6>(0h21)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_13) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_248 = shr(io.in.a.bits.source, 2) node _T_249 = eq(_T_248, UInt<6>(0h22)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_14) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_254 = shr(io.in.a.bits.source, 2) node _T_255 = eq(_T_254, UInt<6>(0h23)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_15) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0) node _T_260 = shr(io.in.a.bits.source, 6) node _T_261 = eq(_T_260, UInt<1>(0h1)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_16) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_16, UInt<6>(0h3f)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0) node _T_266 = shr(io.in.a.bits.source, 6) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_17) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_17, UInt<6>(0h3f)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_273 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_274 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_235 connect _WIRE[1], _T_241 connect _WIRE[2], _T_247 connect _WIRE[3], _T_253 connect _WIRE[4], _T_259 connect _WIRE[5], _T_265 connect _WIRE[6], _T_271 connect _WIRE[7], _T_272 connect _WIRE[8], _T_273 connect _WIRE[9], _T_274 node _T_275 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_276 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_278 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_279 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_280 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_281 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_282 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = mux(_WIRE[7], _T_275, UInt<1>(0h0)) node _T_284 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_285 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = or(_T_276, _T_277) node _T_287 = or(_T_286, _T_278) node _T_288 = or(_T_287, _T_279) node _T_289 = or(_T_288, _T_280) node _T_290 = or(_T_289, _T_281) node _T_291 = or(_T_290, _T_282) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_284) node _T_294 = or(_T_293, _T_285) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_294 node _T_295 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_296 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_297 = and(_T_295, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_300 = cvt(_T_299) node _T_301 = and(_T_300, asSInt(UInt<14>(0h2000))) node _T_302 = asSInt(_T_301) node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0))) node _T_304 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_305 = cvt(_T_304) node _T_306 = and(_T_305, asSInt(UInt<13>(0h1000))) node _T_307 = asSInt(_T_306) node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h10000))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<18>(0h2f000))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<17>(0h10000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<27>(0h4000000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<13>(0h1000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = or(_T_303, _T_308) node _T_340 = or(_T_339, _T_313) node _T_341 = or(_T_340, _T_318) node _T_342 = or(_T_341, _T_323) node _T_343 = or(_T_342, _T_328) node _T_344 = or(_T_343, _T_333) node _T_345 = or(_T_344, _T_338) node _T_346 = and(_T_298, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(_WIRE_1, _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_348, UInt<1>(0h1), "") : assert_3 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(source_ok, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_355 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_355, UInt<1>(0h1), "") : assert_5 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_362, UInt<1>(0h1), "") : assert_7 node _T_366 = not(io.in.a.bits.mask) node _T_367 = eq(_T_366, UInt<1>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_367, UInt<1>(0h1), "") : assert_8 node _T_371 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_371, UInt<1>(0h1), "") : assert_9 node _T_375 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_375 : node _T_376 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_377 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_380 = shr(io.in.a.bits.source, 2) node _T_381 = eq(_T_380, UInt<6>(0h20)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_18) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_386 = shr(io.in.a.bits.source, 2) node _T_387 = eq(_T_386, UInt<6>(0h21)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_19) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_392 = shr(io.in.a.bits.source, 2) node _T_393 = eq(_T_392, UInt<6>(0h22)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_20) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_398 = shr(io.in.a.bits.source, 2) node _T_399 = eq(_T_398, UInt<6>(0h23)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_21) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_403 = and(_T_401, _T_402) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0) node _T_404 = shr(io.in.a.bits.source, 6) node _T_405 = eq(_T_404, UInt<1>(0h1)) node _T_406 = leq(UInt<1>(0h0), uncommonBits_22) node _T_407 = and(_T_405, _T_406) node _T_408 = leq(uncommonBits_22, UInt<6>(0h3f)) node _T_409 = and(_T_407, _T_408) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0) node _T_410 = shr(io.in.a.bits.source, 6) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = leq(UInt<1>(0h0), uncommonBits_23) node _T_413 = and(_T_411, _T_412) node _T_414 = leq(uncommonBits_23, UInt<6>(0h3f)) node _T_415 = and(_T_413, _T_414) node _T_416 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_417 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_418 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_419 = or(_T_379, _T_385) node _T_420 = or(_T_419, _T_391) node _T_421 = or(_T_420, _T_397) node _T_422 = or(_T_421, _T_403) node _T_423 = or(_T_422, _T_409) node _T_424 = or(_T_423, _T_415) node _T_425 = or(_T_424, _T_416) node _T_426 = or(_T_425, _T_417) node _T_427 = or(_T_426, _T_418) node _T_428 = and(_T_378, _T_427) node _T_429 = or(UInt<1>(0h0), _T_428) node _T_430 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<14>(0h2000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<27>(0h4000000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<13>(0h1000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = or(_T_435, _T_440) node _T_472 = or(_T_471, _T_445) node _T_473 = or(_T_472, _T_450) node _T_474 = or(_T_473, _T_455) node _T_475 = or(_T_474, _T_460) node _T_476 = or(_T_475, _T_465) node _T_477 = or(_T_476, _T_470) node _T_478 = and(_T_430, _T_477) node _T_479 = or(UInt<1>(0h0), _T_478) node _T_480 = and(_T_429, _T_479) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_480, UInt<1>(0h1), "") : assert_10 node _T_484 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_485 = shr(io.in.a.bits.source, 2) node _T_486 = eq(_T_485, UInt<6>(0h20)) node _T_487 = leq(UInt<1>(0h0), uncommonBits_24) node _T_488 = and(_T_486, _T_487) node _T_489 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_490 = and(_T_488, _T_489) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_491 = shr(io.in.a.bits.source, 2) node _T_492 = eq(_T_491, UInt<6>(0h21)) node _T_493 = leq(UInt<1>(0h0), uncommonBits_25) node _T_494 = and(_T_492, _T_493) node _T_495 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_496 = and(_T_494, _T_495) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_497 = shr(io.in.a.bits.source, 2) node _T_498 = eq(_T_497, UInt<6>(0h22)) node _T_499 = leq(UInt<1>(0h0), uncommonBits_26) node _T_500 = and(_T_498, _T_499) node _T_501 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_502 = and(_T_500, _T_501) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_503 = shr(io.in.a.bits.source, 2) node _T_504 = eq(_T_503, UInt<6>(0h23)) node _T_505 = leq(UInt<1>(0h0), uncommonBits_27) node _T_506 = and(_T_504, _T_505) node _T_507 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_508 = and(_T_506, _T_507) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0) node _T_509 = shr(io.in.a.bits.source, 6) node _T_510 = eq(_T_509, UInt<1>(0h1)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_28) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_28, UInt<6>(0h3f)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0) node _T_515 = shr(io.in.a.bits.source, 6) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_29) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_29, UInt<6>(0h3f)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_522 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_523 = eq(io.in.a.bits.source, UInt<8>(0ha2)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_484 connect _WIRE_2[1], _T_490 connect _WIRE_2[2], _T_496 connect _WIRE_2[3], _T_502 connect _WIRE_2[4], _T_508 connect _WIRE_2[5], _T_514 connect _WIRE_2[6], _T_520 connect _WIRE_2[7], _T_521 connect _WIRE_2[8], _T_522 connect _WIRE_2[9], _T_523 node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_525 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_527 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_528 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_529 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_531 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_532 = mux(_WIRE_2[7], _T_524, UInt<1>(0h0)) node _T_533 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_534 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_535 = or(_T_525, _T_526) node _T_536 = or(_T_535, _T_527) node _T_537 = or(_T_536, _T_528) node _T_538 = or(_T_537, _T_529) node _T_539 = or(_T_538, _T_530) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_532) node _T_542 = or(_T_541, _T_533) node _T_543 = or(_T_542, _T_534) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_543 node _T_544 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_545 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_546 = and(_T_544, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<14>(0h2000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_554 = cvt(_T_553) node _T_555 = and(_T_554, asSInt(UInt<13>(0h1000))) node _T_556 = asSInt(_T_555) node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0))) node _T_558 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_559 = cvt(_T_558) node _T_560 = and(_T_559, asSInt(UInt<17>(0h10000))) node _T_561 = asSInt(_T_560) node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0))) node _T_563 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_564 = cvt(_T_563) node _T_565 = and(_T_564, asSInt(UInt<18>(0h2f000))) node _T_566 = asSInt(_T_565) node _T_567 = eq(_T_566, asSInt(UInt<1>(0h0))) node _T_568 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_569 = cvt(_T_568) node _T_570 = and(_T_569, asSInt(UInt<17>(0h10000))) node _T_571 = asSInt(_T_570) node _T_572 = eq(_T_571, asSInt(UInt<1>(0h0))) node _T_573 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<27>(0h4000000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<13>(0h1000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = or(_T_552, _T_557) node _T_589 = or(_T_588, _T_562) node _T_590 = or(_T_589, _T_567) node _T_591 = or(_T_590, _T_572) node _T_592 = or(_T_591, _T_577) node _T_593 = or(_T_592, _T_582) node _T_594 = or(_T_593, _T_587) node _T_595 = and(_T_547, _T_594) node _T_596 = or(UInt<1>(0h0), _T_595) node _T_597 = and(_WIRE_3, _T_596) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_597, UInt<1>(0h1), "") : assert_11 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(source_ok, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_604 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_604, UInt<1>(0h1), "") : assert_13 node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(is_aligned, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_611 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_611, UInt<1>(0h1), "") : assert_15 node _T_615 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(_T_615, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_615, UInt<1>(0h1), "") : assert_16 node _T_619 = not(io.in.a.bits.mask) node _T_620 = eq(_T_619, UInt<1>(0h0)) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_620, UInt<1>(0h1), "") : assert_17 node _T_624 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_624, UInt<1>(0h1), "") : assert_18 node _T_628 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_628 : node _T_629 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_630 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_631 = and(_T_629, _T_630) node _T_632 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<6>(0h20)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_30) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_639 = shr(io.in.a.bits.source, 2) node _T_640 = eq(_T_639, UInt<6>(0h21)) node _T_641 = leq(UInt<1>(0h0), uncommonBits_31) node _T_642 = and(_T_640, _T_641) node _T_643 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_644 = and(_T_642, _T_643) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_645 = shr(io.in.a.bits.source, 2) node _T_646 = eq(_T_645, UInt<6>(0h22)) node _T_647 = leq(UInt<1>(0h0), uncommonBits_32) node _T_648 = and(_T_646, _T_647) node _T_649 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_650 = and(_T_648, _T_649) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_651 = shr(io.in.a.bits.source, 2) node _T_652 = eq(_T_651, UInt<6>(0h23)) node _T_653 = leq(UInt<1>(0h0), uncommonBits_33) node _T_654 = and(_T_652, _T_653) node _T_655 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_656 = and(_T_654, _T_655) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0) node _T_657 = shr(io.in.a.bits.source, 6) node _T_658 = eq(_T_657, UInt<1>(0h1)) node _T_659 = leq(UInt<1>(0h0), uncommonBits_34) node _T_660 = and(_T_658, _T_659) node _T_661 = leq(uncommonBits_34, UInt<6>(0h3f)) node _T_662 = and(_T_660, _T_661) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0) node _T_663 = shr(io.in.a.bits.source, 6) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = leq(UInt<1>(0h0), uncommonBits_35) node _T_666 = and(_T_664, _T_665) node _T_667 = leq(uncommonBits_35, UInt<6>(0h3f)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_670 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_671 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_672 = or(_T_632, _T_638) node _T_673 = or(_T_672, _T_644) node _T_674 = or(_T_673, _T_650) node _T_675 = or(_T_674, _T_656) node _T_676 = or(_T_675, _T_662) node _T_677 = or(_T_676, _T_668) node _T_678 = or(_T_677, _T_669) node _T_679 = or(_T_678, _T_670) node _T_680 = or(_T_679, _T_671) node _T_681 = and(_T_631, _T_680) node _T_682 = or(UInt<1>(0h0), _T_681) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_682, UInt<1>(0h1), "") : assert_19 node _T_686 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_687 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_688 = and(_T_686, _T_687) node _T_689 = or(UInt<1>(0h0), _T_688) node _T_690 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<13>(0h1000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = and(_T_689, _T_694) node _T_696 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_697 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_698 = and(_T_696, _T_697) node _T_699 = or(UInt<1>(0h0), _T_698) node _T_700 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<14>(0h2000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<17>(0h10000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<18>(0h2f000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<17>(0h10000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<27>(0h4000000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<13>(0h1000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = or(_T_704, _T_709) node _T_736 = or(_T_735, _T_714) node _T_737 = or(_T_736, _T_719) node _T_738 = or(_T_737, _T_724) node _T_739 = or(_T_738, _T_729) node _T_740 = or(_T_739, _T_734) node _T_741 = and(_T_699, _T_740) node _T_742 = or(UInt<1>(0h0), _T_695) node _T_743 = or(_T_742, _T_741) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_743, UInt<1>(0h1), "") : assert_20 node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(source_ok, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(is_aligned, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_753 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_754 = asUInt(reset) node _T_755 = eq(_T_754, UInt<1>(0h0)) when _T_755 : node _T_756 = eq(_T_753, UInt<1>(0h0)) when _T_756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_753, UInt<1>(0h1), "") : assert_23 node _T_757 = eq(io.in.a.bits.mask, mask) node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(_T_757, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_757, UInt<1>(0h1), "") : assert_24 node _T_761 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_761, UInt<1>(0h1), "") : assert_25 node _T_765 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<6>(0h20)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_36) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<6>(0h21)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_37) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<6>(0h22)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_38) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<6>(0h23)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_39) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0) node _T_794 = shr(io.in.a.bits.source, 6) node _T_795 = eq(_T_794, UInt<1>(0h1)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_40) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_40, UInt<6>(0h3f)) node _T_799 = and(_T_797, _T_798) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0) node _T_800 = shr(io.in.a.bits.source, 6) node _T_801 = eq(_T_800, UInt<1>(0h0)) node _T_802 = leq(UInt<1>(0h0), uncommonBits_41) node _T_803 = and(_T_801, _T_802) node _T_804 = leq(uncommonBits_41, UInt<6>(0h3f)) node _T_805 = and(_T_803, _T_804) node _T_806 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_807 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_808 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_809 = or(_T_769, _T_775) node _T_810 = or(_T_809, _T_781) node _T_811 = or(_T_810, _T_787) node _T_812 = or(_T_811, _T_793) node _T_813 = or(_T_812, _T_799) node _T_814 = or(_T_813, _T_805) node _T_815 = or(_T_814, _T_806) node _T_816 = or(_T_815, _T_807) node _T_817 = or(_T_816, _T_808) node _T_818 = and(_T_768, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = and(_T_823, _T_828) node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_831 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_832 = and(_T_830, _T_831) node _T_833 = or(UInt<1>(0h0), _T_832) node _T_834 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<14>(0h2000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<18>(0h2f000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<27>(0h4000000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<13>(0h1000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_838, _T_843) node _T_865 = or(_T_864, _T_848) node _T_866 = or(_T_865, _T_853) node _T_867 = or(_T_866, _T_858) node _T_868 = or(_T_867, _T_863) node _T_869 = and(_T_833, _T_868) node _T_870 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_871 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<17>(0h10000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = and(_T_870, _T_875) node _T_877 = or(UInt<1>(0h0), _T_829) node _T_878 = or(_T_877, _T_869) node _T_879 = or(_T_878, _T_876) node _T_880 = and(_T_819, _T_879) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_880, UInt<1>(0h1), "") : assert_26 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(source_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(is_aligned, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_890, UInt<1>(0h1), "") : assert_29 node _T_894 = eq(io.in.a.bits.mask, mask) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_894, UInt<1>(0h1), "") : assert_30 node _T_898 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_898 : node _T_899 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_900 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_901 = and(_T_899, _T_900) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_903 = shr(io.in.a.bits.source, 2) node _T_904 = eq(_T_903, UInt<6>(0h20)) node _T_905 = leq(UInt<1>(0h0), uncommonBits_42) node _T_906 = and(_T_904, _T_905) node _T_907 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_908 = and(_T_906, _T_907) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_909 = shr(io.in.a.bits.source, 2) node _T_910 = eq(_T_909, UInt<6>(0h21)) node _T_911 = leq(UInt<1>(0h0), uncommonBits_43) node _T_912 = and(_T_910, _T_911) node _T_913 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_914 = and(_T_912, _T_913) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_915 = shr(io.in.a.bits.source, 2) node _T_916 = eq(_T_915, UInt<6>(0h22)) node _T_917 = leq(UInt<1>(0h0), uncommonBits_44) node _T_918 = and(_T_916, _T_917) node _T_919 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_920 = and(_T_918, _T_919) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_921 = shr(io.in.a.bits.source, 2) node _T_922 = eq(_T_921, UInt<6>(0h23)) node _T_923 = leq(UInt<1>(0h0), uncommonBits_45) node _T_924 = and(_T_922, _T_923) node _T_925 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_926 = and(_T_924, _T_925) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0) node _T_927 = shr(io.in.a.bits.source, 6) node _T_928 = eq(_T_927, UInt<1>(0h1)) node _T_929 = leq(UInt<1>(0h0), uncommonBits_46) node _T_930 = and(_T_928, _T_929) node _T_931 = leq(uncommonBits_46, UInt<6>(0h3f)) node _T_932 = and(_T_930, _T_931) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0) node _T_933 = shr(io.in.a.bits.source, 6) node _T_934 = eq(_T_933, UInt<1>(0h0)) node _T_935 = leq(UInt<1>(0h0), uncommonBits_47) node _T_936 = and(_T_934, _T_935) node _T_937 = leq(uncommonBits_47, UInt<6>(0h3f)) node _T_938 = and(_T_936, _T_937) node _T_939 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_940 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_941 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_942 = or(_T_902, _T_908) node _T_943 = or(_T_942, _T_914) node _T_944 = or(_T_943, _T_920) node _T_945 = or(_T_944, _T_926) node _T_946 = or(_T_945, _T_932) node _T_947 = or(_T_946, _T_938) node _T_948 = or(_T_947, _T_939) node _T_949 = or(_T_948, _T_940) node _T_950 = or(_T_949, _T_941) node _T_951 = and(_T_901, _T_950) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_954 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_955 = and(_T_953, _T_954) node _T_956 = or(UInt<1>(0h0), _T_955) node _T_957 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_958 = cvt(_T_957) node _T_959 = and(_T_958, asSInt(UInt<13>(0h1000))) node _T_960 = asSInt(_T_959) node _T_961 = eq(_T_960, asSInt(UInt<1>(0h0))) node _T_962 = and(_T_956, _T_961) node _T_963 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_964 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_965 = and(_T_963, _T_964) node _T_966 = or(UInt<1>(0h0), _T_965) node _T_967 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_968 = cvt(_T_967) node _T_969 = and(_T_968, asSInt(UInt<14>(0h2000))) node _T_970 = asSInt(_T_969) node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0))) node _T_972 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<18>(0h2f000))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<17>(0h10000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<27>(0h4000000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<13>(0h1000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = or(_T_971, _T_976) node _T_998 = or(_T_997, _T_981) node _T_999 = or(_T_998, _T_986) node _T_1000 = or(_T_999, _T_991) node _T_1001 = or(_T_1000, _T_996) node _T_1002 = and(_T_966, _T_1001) node _T_1003 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1004 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = and(_T_1003, _T_1008) node _T_1010 = or(UInt<1>(0h0), _T_962) node _T_1011 = or(_T_1010, _T_1002) node _T_1012 = or(_T_1011, _T_1009) node _T_1013 = and(_T_952, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_31 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(source_ok, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1023 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_34 node _T_1027 = not(mask) node _T_1028 = and(io.in.a.bits.mask, _T_1027) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_35 node _T_1033 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1033 : node _T_1034 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1035 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1038 = shr(io.in.a.bits.source, 2) node _T_1039 = eq(_T_1038, UInt<6>(0h20)) node _T_1040 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1043 = and(_T_1041, _T_1042) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1044 = shr(io.in.a.bits.source, 2) node _T_1045 = eq(_T_1044, UInt<6>(0h21)) node _T_1046 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1049 = and(_T_1047, _T_1048) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1050 = shr(io.in.a.bits.source, 2) node _T_1051 = eq(_T_1050, UInt<6>(0h22)) node _T_1052 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1053 = and(_T_1051, _T_1052) node _T_1054 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1055 = and(_T_1053, _T_1054) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1056 = shr(io.in.a.bits.source, 2) node _T_1057 = eq(_T_1056, UInt<6>(0h23)) node _T_1058 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1061 = and(_T_1059, _T_1060) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0) node _T_1062 = shr(io.in.a.bits.source, 6) node _T_1063 = eq(_T_1062, UInt<1>(0h1)) node _T_1064 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1065 = and(_T_1063, _T_1064) node _T_1066 = leq(uncommonBits_52, UInt<6>(0h3f)) node _T_1067 = and(_T_1065, _T_1066) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0) node _T_1068 = shr(io.in.a.bits.source, 6) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) node _T_1070 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = leq(uncommonBits_53, UInt<6>(0h3f)) node _T_1073 = and(_T_1071, _T_1072) node _T_1074 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1075 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1076 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1077 = or(_T_1037, _T_1043) node _T_1078 = or(_T_1077, _T_1049) node _T_1079 = or(_T_1078, _T_1055) node _T_1080 = or(_T_1079, _T_1061) node _T_1081 = or(_T_1080, _T_1067) node _T_1082 = or(_T_1081, _T_1073) node _T_1083 = or(_T_1082, _T_1074) node _T_1084 = or(_T_1083, _T_1075) node _T_1085 = or(_T_1084, _T_1076) node _T_1086 = and(_T_1036, _T_1085) node _T_1087 = or(UInt<1>(0h0), _T_1086) node _T_1088 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1089 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = or(UInt<1>(0h0), _T_1090) node _T_1092 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1093 = cvt(_T_1092) node _T_1094 = and(_T_1093, asSInt(UInt<14>(0h2000))) node _T_1095 = asSInt(_T_1094) node _T_1096 = eq(_T_1095, asSInt(UInt<1>(0h0))) node _T_1097 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1098 = cvt(_T_1097) node _T_1099 = and(_T_1098, asSInt(UInt<13>(0h1000))) node _T_1100 = asSInt(_T_1099) node _T_1101 = eq(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1103 = cvt(_T_1102) node _T_1104 = and(_T_1103, asSInt(UInt<18>(0h2f000))) node _T_1105 = asSInt(_T_1104) node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0))) node _T_1107 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1108 = cvt(_T_1107) node _T_1109 = and(_T_1108, asSInt(UInt<17>(0h10000))) node _T_1110 = asSInt(_T_1109) node _T_1111 = eq(_T_1110, asSInt(UInt<1>(0h0))) node _T_1112 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<13>(0h1000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1118 = cvt(_T_1117) node _T_1119 = and(_T_1118, asSInt(UInt<27>(0h4000000))) node _T_1120 = asSInt(_T_1119) node _T_1121 = eq(_T_1120, asSInt(UInt<1>(0h0))) node _T_1122 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1123 = cvt(_T_1122) node _T_1124 = and(_T_1123, asSInt(UInt<13>(0h1000))) node _T_1125 = asSInt(_T_1124) node _T_1126 = eq(_T_1125, asSInt(UInt<1>(0h0))) node _T_1127 = or(_T_1096, _T_1101) node _T_1128 = or(_T_1127, _T_1106) node _T_1129 = or(_T_1128, _T_1111) node _T_1130 = or(_T_1129, _T_1116) node _T_1131 = or(_T_1130, _T_1121) node _T_1132 = or(_T_1131, _T_1126) node _T_1133 = and(_T_1091, _T_1132) node _T_1134 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1135 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1136 = cvt(_T_1135) node _T_1137 = and(_T_1136, asSInt(UInt<17>(0h10000))) node _T_1138 = asSInt(_T_1137) node _T_1139 = eq(_T_1138, asSInt(UInt<1>(0h0))) node _T_1140 = and(_T_1134, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1133) node _T_1142 = or(_T_1141, _T_1140) node _T_1143 = and(_T_1087, _T_1142) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_36 node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(source_ok, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(is_aligned, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1153 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_39 node _T_1157 = eq(io.in.a.bits.mask, mask) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_40 node _T_1161 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1161 : node _T_1162 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1163 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1164 = and(_T_1162, _T_1163) node _T_1165 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1166 = shr(io.in.a.bits.source, 2) node _T_1167 = eq(_T_1166, UInt<6>(0h20)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1171 = and(_T_1169, _T_1170) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1172 = shr(io.in.a.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<6>(0h21)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1178 = shr(io.in.a.bits.source, 2) node _T_1179 = eq(_T_1178, UInt<6>(0h22)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1184 = shr(io.in.a.bits.source, 2) node _T_1185 = eq(_T_1184, UInt<6>(0h23)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0) node _T_1190 = shr(io.in.a.bits.source, 6) node _T_1191 = eq(_T_1190, UInt<1>(0h1)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_58, UInt<6>(0h3f)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0) node _T_1196 = shr(io.in.a.bits.source, 6) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_59, UInt<6>(0h3f)) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1203 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1204 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1205 = or(_T_1165, _T_1171) node _T_1206 = or(_T_1205, _T_1177) node _T_1207 = or(_T_1206, _T_1183) node _T_1208 = or(_T_1207, _T_1189) node _T_1209 = or(_T_1208, _T_1195) node _T_1210 = or(_T_1209, _T_1201) node _T_1211 = or(_T_1210, _T_1202) node _T_1212 = or(_T_1211, _T_1203) node _T_1213 = or(_T_1212, _T_1204) node _T_1214 = and(_T_1164, _T_1213) node _T_1215 = or(UInt<1>(0h0), _T_1214) node _T_1216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1217 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = or(UInt<1>(0h0), _T_1218) node _T_1220 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<14>(0h2000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<18>(0h2f000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<17>(0h10000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<13>(0h1000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1246 = cvt(_T_1245) node _T_1247 = and(_T_1246, asSInt(UInt<27>(0h4000000))) node _T_1248 = asSInt(_T_1247) node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0))) node _T_1250 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = or(_T_1224, _T_1229) node _T_1256 = or(_T_1255, _T_1234) node _T_1257 = or(_T_1256, _T_1239) node _T_1258 = or(_T_1257, _T_1244) node _T_1259 = or(_T_1258, _T_1249) node _T_1260 = or(_T_1259, _T_1254) node _T_1261 = and(_T_1219, _T_1260) node _T_1262 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1263 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = and(_T_1262, _T_1267) node _T_1269 = or(UInt<1>(0h0), _T_1261) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = and(_T_1215, _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_41 node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(source_ok, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(is_aligned, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1281 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_44 node _T_1285 = eq(io.in.a.bits.mask, mask) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_45 node _T_1289 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1289 : node _T_1290 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1291 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1292 = and(_T_1290, _T_1291) node _T_1293 = eq(io.in.a.bits.source, UInt<8>(0h90)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1294 = shr(io.in.a.bits.source, 2) node _T_1295 = eq(_T_1294, UInt<6>(0h20)) node _T_1296 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1297 = and(_T_1295, _T_1296) node _T_1298 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1299 = and(_T_1297, _T_1298) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1300 = shr(io.in.a.bits.source, 2) node _T_1301 = eq(_T_1300, UInt<6>(0h21)) node _T_1302 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1303 = and(_T_1301, _T_1302) node _T_1304 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1305 = and(_T_1303, _T_1304) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1306 = shr(io.in.a.bits.source, 2) node _T_1307 = eq(_T_1306, UInt<6>(0h22)) node _T_1308 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1309 = and(_T_1307, _T_1308) node _T_1310 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1311 = and(_T_1309, _T_1310) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1312 = shr(io.in.a.bits.source, 2) node _T_1313 = eq(_T_1312, UInt<6>(0h23)) node _T_1314 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1315 = and(_T_1313, _T_1314) node _T_1316 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1317 = and(_T_1315, _T_1316) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0) node _T_1318 = shr(io.in.a.bits.source, 6) node _T_1319 = eq(_T_1318, UInt<1>(0h1)) node _T_1320 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1321 = and(_T_1319, _T_1320) node _T_1322 = leq(uncommonBits_64, UInt<6>(0h3f)) node _T_1323 = and(_T_1321, _T_1322) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0) node _T_1324 = shr(io.in.a.bits.source, 6) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) node _T_1326 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = leq(uncommonBits_65, UInt<6>(0h3f)) node _T_1329 = and(_T_1327, _T_1328) node _T_1330 = eq(io.in.a.bits.source, UInt<8>(0ha0)) node _T_1331 = eq(io.in.a.bits.source, UInt<8>(0ha1)) node _T_1332 = eq(io.in.a.bits.source, UInt<8>(0ha2)) node _T_1333 = or(_T_1293, _T_1299) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1311) node _T_1336 = or(_T_1335, _T_1317) node _T_1337 = or(_T_1336, _T_1323) node _T_1338 = or(_T_1337, _T_1329) node _T_1339 = or(_T_1338, _T_1330) node _T_1340 = or(_T_1339, _T_1331) node _T_1341 = or(_T_1340, _T_1332) node _T_1342 = and(_T_1292, _T_1341) node _T_1343 = or(UInt<1>(0h0), _T_1342) node _T_1344 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1345 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = or(UInt<1>(0h0), _T_1346) node _T_1348 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<13>(0h1000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = and(_T_1347, _T_1352) node _T_1354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1355 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1356 = cvt(_T_1355) node _T_1357 = and(_T_1356, asSInt(UInt<14>(0h2000))) node _T_1358 = asSInt(_T_1357) node _T_1359 = eq(_T_1358, asSInt(UInt<1>(0h0))) node _T_1360 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1361 = cvt(_T_1360) node _T_1362 = and(_T_1361, asSInt(UInt<17>(0h10000))) node _T_1363 = asSInt(_T_1362) node _T_1364 = eq(_T_1363, asSInt(UInt<1>(0h0))) node _T_1365 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1366 = cvt(_T_1365) node _T_1367 = and(_T_1366, asSInt(UInt<18>(0h2f000))) node _T_1368 = asSInt(_T_1367) node _T_1369 = eq(_T_1368, asSInt(UInt<1>(0h0))) node _T_1370 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<17>(0h10000))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1376 = cvt(_T_1375) node _T_1377 = and(_T_1376, asSInt(UInt<13>(0h1000))) node _T_1378 = asSInt(_T_1377) node _T_1379 = eq(_T_1378, asSInt(UInt<1>(0h0))) node _T_1380 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1381 = cvt(_T_1380) node _T_1382 = and(_T_1381, asSInt(UInt<27>(0h4000000))) node _T_1383 = asSInt(_T_1382) node _T_1384 = eq(_T_1383, asSInt(UInt<1>(0h0))) node _T_1385 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1386 = cvt(_T_1385) node _T_1387 = and(_T_1386, asSInt(UInt<13>(0h1000))) node _T_1388 = asSInt(_T_1387) node _T_1389 = eq(_T_1388, asSInt(UInt<1>(0h0))) node _T_1390 = or(_T_1359, _T_1364) node _T_1391 = or(_T_1390, _T_1369) node _T_1392 = or(_T_1391, _T_1374) node _T_1393 = or(_T_1392, _T_1379) node _T_1394 = or(_T_1393, _T_1384) node _T_1395 = or(_T_1394, _T_1389) node _T_1396 = and(_T_1354, _T_1395) node _T_1397 = or(UInt<1>(0h0), _T_1353) node _T_1398 = or(_T_1397, _T_1396) node _T_1399 = and(_T_1343, _T_1398) node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(_T_1399, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1399, UInt<1>(0h1), "") : assert_46 node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(source_ok, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1406 = asUInt(reset) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) when _T_1407 : node _T_1408 = eq(is_aligned, UInt<1>(0h0)) when _T_1408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1409 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_49 node _T_1413 = eq(io.in.a.bits.mask, mask) node _T_1414 = asUInt(reset) node _T_1415 = eq(_T_1414, UInt<1>(0h0)) when _T_1415 : node _T_1416 = eq(_T_1413, UInt<1>(0h0)) when _T_1416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1413, UInt<1>(0h1), "") : assert_50 node _T_1417 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1418 = asUInt(reset) node _T_1419 = eq(_T_1418, UInt<1>(0h0)) when _T_1419 : node _T_1420 = eq(_T_1417, UInt<1>(0h0)) when _T_1420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1417, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1421 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_52 node _source_ok_T_48 = eq(io.in.d.bits.source, UInt<8>(0h90)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<6>(0h20)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<6>(0h21)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<6>(0h22)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<6>(0h23)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 6) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<1>(0h1)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 6) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<8>(0ha0)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<8>(0ha1)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha2)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_48 connect _source_ok_WIRE_1[1], _source_ok_T_54 connect _source_ok_WIRE_1[2], _source_ok_T_60 connect _source_ok_WIRE_1[3], _source_ok_T_66 connect _source_ok_WIRE_1[4], _source_ok_T_72 connect _source_ok_WIRE_1[5], _source_ok_T_78 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 node _source_ok_T_88 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[2]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[3]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[4]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[5]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[6]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[7]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_95, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1425 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1425 : node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(source_ok_1, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1429 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_54 node _T_1433 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_55 node _T_1437 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(_T_1437, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1437, UInt<1>(0h1), "") : assert_56 node _T_1441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_57 node _T_1445 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1445 : node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok_1, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(sink_ok, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1452 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_60 node _T_1456 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_61 node _T_1460 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_62 node _T_1464 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_63 node _T_1468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1469 = or(UInt<1>(0h1), _T_1468) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_64 node _T_1473 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1473 : node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok_1, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(sink_ok, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1480 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_67 node _T_1484 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_68 node _T_1488 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_69 node _T_1492 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1493 = or(_T_1492, io.in.d.bits.corrupt) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_70 node _T_1497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1498 = or(UInt<1>(0h1), _T_1497) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_71 node _T_1502 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1502 : node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(source_ok_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1506 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(_T_1506, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1506, UInt<1>(0h1), "") : assert_73 node _T_1510 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_74 node _T_1514 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1515 = or(UInt<1>(0h1), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_75 node _T_1519 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1519 : node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(source_ok_1, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1523 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_77 node _T_1527 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1528 = or(_T_1527, io.in.d.bits.corrupt) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_78 node _T_1532 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1533 = or(UInt<1>(0h1), _T_1532) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_79 node _T_1537 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1537 : node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(source_ok_1, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1541 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1542 = asUInt(reset) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) when _T_1543 : node _T_1544 = eq(_T_1541, UInt<1>(0h0)) when _T_1544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1541, UInt<1>(0h1), "") : assert_81 node _T_1545 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_82 node _T_1549 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1550 = or(UInt<1>(0h1), _T_1549) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.mask, UInt<16>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1554 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1558 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(_T_1558, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1558, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1562 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1566 = eq(a_first, UInt<1>(0h0)) node _T_1567 = and(io.in.a.valid, _T_1566) when _T_1567 : node _T_1568 = eq(io.in.a.bits.opcode, opcode) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_87 node _T_1572 = eq(io.in.a.bits.param, param) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_88 node _T_1576 = eq(io.in.a.bits.size, size) node _T_1577 = asUInt(reset) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(_T_1576, UInt<1>(0h0)) when _T_1579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1576, UInt<1>(0h1), "") : assert_89 node _T_1580 = eq(io.in.a.bits.source, source) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_90 node _T_1584 = eq(io.in.a.bits.address, address) node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(_T_1584, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1584, UInt<1>(0h1), "") : assert_91 node _T_1588 = and(io.in.a.ready, io.in.a.valid) node _T_1589 = and(_T_1588, a_first) when _T_1589 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1590 = eq(d_first, UInt<1>(0h0)) node _T_1591 = and(io.in.d.valid, _T_1590) when _T_1591 : node _T_1592 = eq(io.in.d.bits.opcode, opcode_1) node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(_T_1592, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1592, UInt<1>(0h1), "") : assert_92 node _T_1596 = eq(io.in.d.bits.param, param_1) node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(_T_1596, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1596, UInt<1>(0h1), "") : assert_93 node _T_1600 = eq(io.in.d.bits.size, size_1) node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(_T_1600, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1600, UInt<1>(0h1), "") : assert_94 node _T_1604 = eq(io.in.d.bits.source, source_1) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_95 node _T_1608 = eq(io.in.d.bits.sink, sink) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_96 node _T_1612 = eq(io.in.d.bits.denied, denied) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_97 node _T_1616 = and(io.in.d.ready, io.in.d.valid) node _T_1617 = and(_T_1616, d_first) when _T_1617 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<163>, clock, reset, UInt<163>(0h0) regreset inflight_opcodes : UInt<652>, clock, reset, UInt<652>(0h0) regreset inflight_sizes : UInt<1304>, clock, reset, UInt<1304>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<163> connect a_set, UInt<163>(0h0) wire a_set_wo_ready : UInt<163> connect a_set_wo_ready, UInt<163>(0h0) wire a_opcodes_set : UInt<652> connect a_opcodes_set, UInt<652>(0h0) wire a_sizes_set : UInt<1304> connect a_sizes_set, UInt<1304>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1618 = and(io.in.a.valid, a_first_1) node _T_1619 = and(_T_1618, UInt<1>(0h1)) when _T_1619 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1620 = and(io.in.a.ready, io.in.a.valid) node _T_1621 = and(_T_1620, a_first_1) node _T_1622 = and(_T_1621, UInt<1>(0h1)) when _T_1622 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1623 = dshr(inflight, io.in.a.bits.source) node _T_1624 = bits(_T_1623, 0, 0) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) node _T_1626 = asUInt(reset) node _T_1627 = eq(_T_1626, UInt<1>(0h0)) when _T_1627 : node _T_1628 = eq(_T_1625, UInt<1>(0h0)) when _T_1628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1625, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<163> connect d_clr, UInt<163>(0h0) wire d_clr_wo_ready : UInt<163> connect d_clr_wo_ready, UInt<163>(0h0) wire d_opcodes_clr : UInt<652> connect d_opcodes_clr, UInt<652>(0h0) wire d_sizes_clr : UInt<1304> connect d_sizes_clr, UInt<1304>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1629 = and(io.in.d.valid, d_first_1) node _T_1630 = and(_T_1629, UInt<1>(0h1)) node _T_1631 = eq(d_release_ack, UInt<1>(0h0)) node _T_1632 = and(_T_1630, _T_1631) when _T_1632 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1633 = and(io.in.d.ready, io.in.d.valid) node _T_1634 = and(_T_1633, d_first_1) node _T_1635 = and(_T_1634, UInt<1>(0h1)) node _T_1636 = eq(d_release_ack, UInt<1>(0h0)) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1638 = and(io.in.d.valid, d_first_1) node _T_1639 = and(_T_1638, UInt<1>(0h1)) node _T_1640 = eq(d_release_ack, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1642 = dshr(inflight, io.in.d.bits.source) node _T_1643 = bits(_T_1642, 0, 0) node _T_1644 = or(_T_1643, same_cycle_resp) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1648 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1649 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1650 = or(_T_1648, _T_1649) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_100 node _T_1654 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_101 else : node _T_1658 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1659 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1660 = or(_T_1658, _T_1659) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_102 node _T_1664 = eq(io.in.d.bits.size, a_size_lookup) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_103 node _T_1668 = and(io.in.d.valid, d_first_1) node _T_1669 = and(_T_1668, a_first_1) node _T_1670 = and(_T_1669, io.in.a.valid) node _T_1671 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = eq(d_release_ack, UInt<1>(0h0)) node _T_1674 = and(_T_1672, _T_1673) when _T_1674 : node _T_1675 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1676 = or(_T_1675, io.in.a.ready) node _T_1677 = asUInt(reset) node _T_1678 = eq(_T_1677, UInt<1>(0h0)) when _T_1678 : node _T_1679 = eq(_T_1676, UInt<1>(0h0)) when _T_1679 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1676, UInt<1>(0h1), "") : assert_104 node _T_1680 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1681 = orr(a_set_wo_ready) node _T_1682 = eq(_T_1681, UInt<1>(0h0)) node _T_1683 = or(_T_1680, _T_1682) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_6 node _T_1687 = orr(inflight) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) node _T_1689 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1690 = or(_T_1688, _T_1689) node _T_1691 = lt(watchdog, plusarg_reader.out) node _T_1692 = or(_T_1690, _T_1691) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1696 = and(io.in.a.ready, io.in.a.valid) node _T_1697 = and(io.in.d.ready, io.in.d.valid) node _T_1698 = or(_T_1696, _T_1697) when _T_1698 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<163>, clock, reset, UInt<163>(0h0) regreset inflight_opcodes_1 : UInt<652>, clock, reset, UInt<652>(0h0) regreset inflight_sizes_1 : UInt<1304>, clock, reset, UInt<1304>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<163> connect c_set, UInt<163>(0h0) wire c_set_wo_ready : UInt<163> connect c_set_wo_ready, UInt<163>(0h0) wire c_opcodes_set : UInt<652> connect c_opcodes_set, UInt<652>(0h0) wire c_sizes_set : UInt<1304> connect c_sizes_set, UInt<1304>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1699 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1700 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1701 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1702 = and(_T_1700, _T_1701) node _T_1703 = and(_T_1699, _T_1702) when _T_1703 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1704 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1705 = and(_T_1704, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1706 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1707 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1708 = and(_T_1706, _T_1707) node _T_1709 = and(_T_1705, _T_1708) when _T_1709 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1710 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1711 = bits(_T_1710, 0, 0) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) node _T_1713 = asUInt(reset) node _T_1714 = eq(_T_1713, UInt<1>(0h0)) when _T_1714 : node _T_1715 = eq(_T_1712, UInt<1>(0h0)) when _T_1715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1712, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<163> connect d_clr_1, UInt<163>(0h0) wire d_clr_wo_ready_1 : UInt<163> connect d_clr_wo_ready_1, UInt<163>(0h0) wire d_opcodes_clr_1 : UInt<652> connect d_opcodes_clr_1, UInt<652>(0h0) wire d_sizes_clr_1 : UInt<1304> connect d_sizes_clr_1, UInt<1304>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1716 = and(io.in.d.valid, d_first_2) node _T_1717 = and(_T_1716, UInt<1>(0h1)) node _T_1718 = and(_T_1717, d_release_ack_1) when _T_1718 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1719 = and(io.in.d.ready, io.in.d.valid) node _T_1720 = and(_T_1719, d_first_2) node _T_1721 = and(_T_1720, UInt<1>(0h1)) node _T_1722 = and(_T_1721, d_release_ack_1) when _T_1722 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1723 = and(io.in.d.valid, d_first_2) node _T_1724 = and(_T_1723, UInt<1>(0h1)) node _T_1725 = and(_T_1724, d_release_ack_1) when _T_1725 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1726 = dshr(inflight_1, io.in.d.bits.source) node _T_1727 = bits(_T_1726, 0, 0) node _T_1728 = or(_T_1727, same_cycle_resp_1) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1732 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1733 = asUInt(reset) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) when _T_1734 : node _T_1735 = eq(_T_1732, UInt<1>(0h0)) when _T_1735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1732, UInt<1>(0h1), "") : assert_109 else : node _T_1736 = eq(io.in.d.bits.size, c_size_lookup) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_110 node _T_1740 = and(io.in.d.valid, d_first_2) node _T_1741 = and(_T_1740, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1742 = and(_T_1741, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1743 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1744 = and(_T_1742, _T_1743) node _T_1745 = and(_T_1744, d_release_ack_1) node _T_1746 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1747 = and(_T_1745, _T_1746) when _T_1747 : node _T_1748 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<128>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1749 = or(_T_1748, _WIRE_27.ready) node _T_1750 = asUInt(reset) node _T_1751 = eq(_T_1750, UInt<1>(0h0)) when _T_1751 : node _T_1752 = eq(_T_1749, UInt<1>(0h0)) when _T_1752 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1749, UInt<1>(0h1), "") : assert_111 node _T_1753 = orr(c_set_wo_ready) when _T_1753 : node _T_1754 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1755 = asUInt(reset) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) when _T_1756 : node _T_1757 = eq(_T_1754, UInt<1>(0h0)) when _T_1757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1754, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_7 node _T_1758 = orr(inflight_1) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1761 = or(_T_1759, _T_1760) node _T_1762 = lt(watchdog_1, plusarg_reader_1.out) node _T_1763 = or(_T_1761, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<128>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1767 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1768 = and(io.in.d.ready, io.in.d.valid) node _T_1769 = or(_T_1767, _T_1768) when _T_1769 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1303:0] c_sizes_set = 1304'h0; // @[Monitor.scala:741:34] wire [651:0] c_opcodes_set = 652'h0; // @[Monitor.scala:740:34] wire [162:0] c_set = 163'h0; // @[Monitor.scala:738:34] wire [162:0] c_set_wo_ready = 163'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_25 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_31 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h90; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_49 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_55 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_50 = _source_ok_T_49 == 6'h20; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 6'h21; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 6'h22; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 6'h23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_73 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_79 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7] wire _source_ok_T_74 = _source_ok_T_73 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'hA1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_95 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1696 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1696; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1696; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1769 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1769; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1769; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1769; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [162:0] inflight; // @[Monitor.scala:614:27] reg [651:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1303:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [162:0] a_set; // @[Monitor.scala:626:34] wire [162:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [651:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1303:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [651:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [651:0] _a_opcode_lookup_T_6 = {648'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [651:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1303:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1303:0] _a_size_lookup_T_6 = {1296'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1303:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1303:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1622 = _T_1696 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1622 ? _a_set_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1622 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1622 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1622 ? _a_opcodes_set_T_1[651:0] : 652'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1622 ? _a_sizes_set_T_1[1303:0] : 1304'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [162:0] d_clr; // @[Monitor.scala:664:34] wire [162:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [651:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1303:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1668 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1668 & ~d_release_ack ? _d_clr_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1637 = _T_1769 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1637 ? _d_clr_T[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1637 ? _d_opcodes_clr_T_5[651:0] : 652'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1637 ? _d_sizes_clr_T_5[1303:0] : 1304'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [162:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [162:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [162:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [651:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [651:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [651:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1303:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1303:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1303:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [162:0] inflight_1; // @[Monitor.scala:726:35] wire [162:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [651:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [651:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1303:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1303:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [651:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [651:0] _c_opcode_lookup_T_6 = {648'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [651:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1303:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1303:0] _c_size_lookup_T_6 = {1296'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1303:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1303:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [162:0] d_clr_1; // @[Monitor.scala:774:34] wire [162:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [651:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1303:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1740 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1740 & d_release_ack_1 ? _d_clr_wo_ready_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35] wire _T_1722 = _T_1769 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1722 ? _d_clr_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1722 ? _d_opcodes_clr_T_11[651:0] : 652'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1722 ? _d_sizes_clr_T_11[1303:0] : 1304'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [162:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [162:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [651:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [651:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1303:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1303:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AXI4UserYanker : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.extra_id invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.extra_id invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.extra_id invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.extra_id invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in inst Queue8_BundleMap of Queue8_BundleMap connect Queue8_BundleMap.clock, clock connect Queue8_BundleMap.reset, reset inst Queue8_BundleMap_1 of Queue8_BundleMap_1 connect Queue8_BundleMap_1.clock, clock connect Queue8_BundleMap_1.reset, reset inst Queue8_BundleMap_2 of Queue8_BundleMap_2 connect Queue8_BundleMap_2.clock, clock connect Queue8_BundleMap_2.reset, reset inst Queue8_BundleMap_3 of Queue8_BundleMap_3 connect Queue8_BundleMap_3.clock, clock connect Queue8_BundleMap_3.reset, reset inst Queue7_BundleMap of Queue7_BundleMap connect Queue7_BundleMap.clock, clock connect Queue7_BundleMap.reset, reset inst Queue7_BundleMap_1 of Queue7_BundleMap_1 connect Queue7_BundleMap_1.clock, clock connect Queue7_BundleMap_1.reset, reset inst Queue7_BundleMap_2 of Queue7_BundleMap_2 connect Queue7_BundleMap_2.clock, clock connect Queue7_BundleMap_2.reset, reset inst Queue7_BundleMap_3 of Queue7_BundleMap_3 connect Queue7_BundleMap_3.clock, clock connect Queue7_BundleMap_3.reset, reset inst Queue7_BundleMap_4 of Queue7_BundleMap_4 connect Queue7_BundleMap_4.clock, clock connect Queue7_BundleMap_4.reset, reset inst Queue7_BundleMap_5 of Queue7_BundleMap_5 connect Queue7_BundleMap_5.clock, clock connect Queue7_BundleMap_5.reset, reset inst Queue7_BundleMap_6 of Queue7_BundleMap_6 connect Queue7_BundleMap_6.clock, clock connect Queue7_BundleMap_6.reset, reset inst Queue7_BundleMap_7 of Queue7_BundleMap_7 connect Queue7_BundleMap_7.clock, clock connect Queue7_BundleMap_7.reset, reset inst Queue7_BundleMap_8 of Queue7_BundleMap_8 connect Queue7_BundleMap_8.clock, clock connect Queue7_BundleMap_8.reset, reset inst Queue7_BundleMap_9 of Queue7_BundleMap_9 connect Queue7_BundleMap_9.clock, clock connect Queue7_BundleMap_9.reset, reset inst Queue7_BundleMap_10 of Queue7_BundleMap_10 connect Queue7_BundleMap_10.clock, clock connect Queue7_BundleMap_10.reset, reset inst Queue7_BundleMap_11 of Queue7_BundleMap_11 connect Queue7_BundleMap_11.clock, clock connect Queue7_BundleMap_11.reset, reset inst Queue8_BundleMap_4 of Queue8_BundleMap_4 connect Queue8_BundleMap_4.clock, clock connect Queue8_BundleMap_4.reset, reset inst Queue8_BundleMap_5 of Queue8_BundleMap_5 connect Queue8_BundleMap_5.clock, clock connect Queue8_BundleMap_5.reset, reset inst Queue8_BundleMap_6 of Queue8_BundleMap_6 connect Queue8_BundleMap_6.clock, clock connect Queue8_BundleMap_6.reset, reset inst Queue8_BundleMap_7 of Queue8_BundleMap_7 connect Queue8_BundleMap_7.clock, clock connect Queue8_BundleMap_7.reset, reset inst Queue7_BundleMap_12 of Queue7_BundleMap_12 connect Queue7_BundleMap_12.clock, clock connect Queue7_BundleMap_12.reset, reset inst Queue7_BundleMap_13 of Queue7_BundleMap_13 connect Queue7_BundleMap_13.clock, clock connect Queue7_BundleMap_13.reset, reset inst Queue7_BundleMap_14 of Queue7_BundleMap_14 connect Queue7_BundleMap_14.clock, clock connect Queue7_BundleMap_14.reset, reset inst Queue7_BundleMap_15 of Queue7_BundleMap_15 connect Queue7_BundleMap_15.clock, clock connect Queue7_BundleMap_15.reset, reset inst Queue7_BundleMap_16 of Queue7_BundleMap_16 connect Queue7_BundleMap_16.clock, clock connect Queue7_BundleMap_16.reset, reset inst Queue7_BundleMap_17 of Queue7_BundleMap_17 connect Queue7_BundleMap_17.clock, clock connect Queue7_BundleMap_17.reset, reset inst Queue7_BundleMap_18 of Queue7_BundleMap_18 connect Queue7_BundleMap_18.clock, clock connect Queue7_BundleMap_18.reset, reset inst Queue7_BundleMap_19 of Queue7_BundleMap_19 connect Queue7_BundleMap_19.clock, clock connect Queue7_BundleMap_19.reset, reset inst Queue7_BundleMap_20 of Queue7_BundleMap_20 connect Queue7_BundleMap_20.clock, clock connect Queue7_BundleMap_20.reset, reset inst Queue7_BundleMap_21 of Queue7_BundleMap_21 connect Queue7_BundleMap_21.clock, clock connect Queue7_BundleMap_21.reset, reset inst Queue7_BundleMap_22 of Queue7_BundleMap_22 connect Queue7_BundleMap_22.clock, clock connect Queue7_BundleMap_22.reset, reset inst Queue7_BundleMap_23 of Queue7_BundleMap_23 connect Queue7_BundleMap_23.clock, clock connect Queue7_BundleMap_23.reset, reset wire _ar_ready_WIRE : UInt<1>[16] connect _ar_ready_WIRE[0], Queue8_BundleMap.io.enq.ready connect _ar_ready_WIRE[1], Queue8_BundleMap_1.io.enq.ready connect _ar_ready_WIRE[2], Queue8_BundleMap_2.io.enq.ready connect _ar_ready_WIRE[3], Queue8_BundleMap_3.io.enq.ready connect _ar_ready_WIRE[4], Queue7_BundleMap.io.enq.ready connect _ar_ready_WIRE[5], Queue7_BundleMap_1.io.enq.ready connect _ar_ready_WIRE[6], Queue7_BundleMap_2.io.enq.ready connect _ar_ready_WIRE[7], Queue7_BundleMap_3.io.enq.ready connect _ar_ready_WIRE[8], Queue7_BundleMap_4.io.enq.ready connect _ar_ready_WIRE[9], Queue7_BundleMap_5.io.enq.ready connect _ar_ready_WIRE[10], Queue7_BundleMap_6.io.enq.ready connect _ar_ready_WIRE[11], Queue7_BundleMap_7.io.enq.ready connect _ar_ready_WIRE[12], Queue7_BundleMap_8.io.enq.ready connect _ar_ready_WIRE[13], Queue7_BundleMap_9.io.enq.ready connect _ar_ready_WIRE[14], Queue7_BundleMap_10.io.enq.ready connect _ar_ready_WIRE[15], Queue7_BundleMap_11.io.enq.ready node _nodeIn_ar_ready_T = and(nodeOut.ar.ready, _ar_ready_WIRE[nodeIn.ar.bits.id]) connect nodeIn.ar.ready, _nodeIn_ar_ready_T node _nodeOut_ar_valid_T = and(nodeIn.ar.valid, _ar_ready_WIRE[nodeIn.ar.bits.id]) connect nodeOut.ar.valid, _nodeOut_ar_valid_T connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id wire _r_valid_WIRE : UInt<1>[16] connect _r_valid_WIRE[0], Queue8_BundleMap.io.deq.valid connect _r_valid_WIRE[1], Queue8_BundleMap_1.io.deq.valid connect _r_valid_WIRE[2], Queue8_BundleMap_2.io.deq.valid connect _r_valid_WIRE[3], Queue8_BundleMap_3.io.deq.valid connect _r_valid_WIRE[4], Queue7_BundleMap.io.deq.valid connect _r_valid_WIRE[5], Queue7_BundleMap_1.io.deq.valid connect _r_valid_WIRE[6], Queue7_BundleMap_2.io.deq.valid connect _r_valid_WIRE[7], Queue7_BundleMap_3.io.deq.valid connect _r_valid_WIRE[8], Queue7_BundleMap_4.io.deq.valid connect _r_valid_WIRE[9], Queue7_BundleMap_5.io.deq.valid connect _r_valid_WIRE[10], Queue7_BundleMap_6.io.deq.valid connect _r_valid_WIRE[11], Queue7_BundleMap_7.io.deq.valid connect _r_valid_WIRE[12], Queue7_BundleMap_8.io.deq.valid connect _r_valid_WIRE[13], Queue7_BundleMap_9.io.deq.valid connect _r_valid_WIRE[14], Queue7_BundleMap_10.io.deq.valid connect _r_valid_WIRE[15], Queue7_BundleMap_11.io.deq.valid wire _r_bits_WIRE : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}[16] connect _r_bits_WIRE[0], Queue8_BundleMap.io.deq.bits connect _r_bits_WIRE[1], Queue8_BundleMap_1.io.deq.bits connect _r_bits_WIRE[2], Queue8_BundleMap_2.io.deq.bits connect _r_bits_WIRE[3], Queue8_BundleMap_3.io.deq.bits connect _r_bits_WIRE[4], Queue7_BundleMap.io.deq.bits connect _r_bits_WIRE[5], Queue7_BundleMap_1.io.deq.bits connect _r_bits_WIRE[6], Queue7_BundleMap_2.io.deq.bits connect _r_bits_WIRE[7], Queue7_BundleMap_3.io.deq.bits connect _r_bits_WIRE[8], Queue7_BundleMap_4.io.deq.bits connect _r_bits_WIRE[9], Queue7_BundleMap_5.io.deq.bits connect _r_bits_WIRE[10], Queue7_BundleMap_6.io.deq.bits connect _r_bits_WIRE[11], Queue7_BundleMap_7.io.deq.bits connect _r_bits_WIRE[12], Queue7_BundleMap_8.io.deq.bits connect _r_bits_WIRE[13], Queue7_BundleMap_9.io.deq.bits connect _r_bits_WIRE[14], Queue7_BundleMap_10.io.deq.bits connect _r_bits_WIRE[15], Queue7_BundleMap_11.io.deq.bits node _T = eq(nodeOut.r.valid, UInt<1>(0h0)) node _T_1 = or(_T, _r_valid_WIRE[nodeOut.r.bits.id]) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at UserYanker.scala:69 assert (!out.r.valid || r_valid) // Q must be ready faster than the response\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready connect nodeIn.r.bits.echo.extra_id, _r_bits_WIRE[nodeOut.r.bits.id].extra_id connect nodeIn.r.bits.echo.tl_state.source, _r_bits_WIRE[nodeOut.r.bits.id].tl_state.source connect nodeIn.r.bits.echo.tl_state.size, _r_bits_WIRE[nodeOut.r.bits.id].tl_state.size node arsel_shiftAmount = bits(nodeIn.ar.bits.id, 3, 0) node _arsel_T = dshl(UInt<1>(0h1), arsel_shiftAmount) node _arsel_T_1 = bits(_arsel_T, 15, 0) node arsel_0 = bits(_arsel_T_1, 0, 0) node arsel_1 = bits(_arsel_T_1, 1, 1) node arsel_2 = bits(_arsel_T_1, 2, 2) node arsel_3 = bits(_arsel_T_1, 3, 3) node arsel_4 = bits(_arsel_T_1, 4, 4) node arsel_5 = bits(_arsel_T_1, 5, 5) node arsel_6 = bits(_arsel_T_1, 6, 6) node arsel_7 = bits(_arsel_T_1, 7, 7) node arsel_8 = bits(_arsel_T_1, 8, 8) node arsel_9 = bits(_arsel_T_1, 9, 9) node arsel_10 = bits(_arsel_T_1, 10, 10) node arsel_11 = bits(_arsel_T_1, 11, 11) node arsel_12 = bits(_arsel_T_1, 12, 12) node arsel_13 = bits(_arsel_T_1, 13, 13) node arsel_14 = bits(_arsel_T_1, 14, 14) node arsel_15 = bits(_arsel_T_1, 15, 15) node rsel_shiftAmount = bits(nodeOut.r.bits.id, 3, 0) node _rsel_T = dshl(UInt<1>(0h1), rsel_shiftAmount) node _rsel_T_1 = bits(_rsel_T, 15, 0) node rsel_0 = bits(_rsel_T_1, 0, 0) node rsel_1 = bits(_rsel_T_1, 1, 1) node rsel_2 = bits(_rsel_T_1, 2, 2) node rsel_3 = bits(_rsel_T_1, 3, 3) node rsel_4 = bits(_rsel_T_1, 4, 4) node rsel_5 = bits(_rsel_T_1, 5, 5) node rsel_6 = bits(_rsel_T_1, 6, 6) node rsel_7 = bits(_rsel_T_1, 7, 7) node rsel_8 = bits(_rsel_T_1, 8, 8) node rsel_9 = bits(_rsel_T_1, 9, 9) node rsel_10 = bits(_rsel_T_1, 10, 10) node rsel_11 = bits(_rsel_T_1, 11, 11) node rsel_12 = bits(_rsel_T_1, 12, 12) node rsel_13 = bits(_rsel_T_1, 13, 13) node rsel_14 = bits(_rsel_T_1, 14, 14) node rsel_15 = bits(_rsel_T_1, 15, 15) node _T_5 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_6 = and(_T_5, rsel_0) node _T_7 = and(_T_6, nodeOut.r.bits.last) connect Queue8_BundleMap.io.deq.ready, _T_7 invalidate Queue8_BundleMap.io.deq.valid invalidate Queue8_BundleMap.io.deq.bits.extra_id invalidate Queue8_BundleMap.io.deq.bits.tl_state.source invalidate Queue8_BundleMap.io.deq.bits.tl_state.size node _T_8 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_9 = and(_T_8, arsel_0) connect Queue8_BundleMap.io.enq.valid, _T_9 invalidate Queue8_BundleMap.io.enq.ready connect Queue8_BundleMap.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap.io.count node _T_10 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_11 = and(_T_10, rsel_1) node _T_12 = and(_T_11, nodeOut.r.bits.last) connect Queue8_BundleMap_1.io.deq.ready, _T_12 invalidate Queue8_BundleMap_1.io.deq.valid invalidate Queue8_BundleMap_1.io.deq.bits.extra_id invalidate Queue8_BundleMap_1.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_1.io.deq.bits.tl_state.size node _T_13 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_14 = and(_T_13, arsel_1) connect Queue8_BundleMap_1.io.enq.valid, _T_14 invalidate Queue8_BundleMap_1.io.enq.ready connect Queue8_BundleMap_1.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap_1.io.count node _T_15 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_16 = and(_T_15, rsel_2) node _T_17 = and(_T_16, nodeOut.r.bits.last) connect Queue8_BundleMap_2.io.deq.ready, _T_17 invalidate Queue8_BundleMap_2.io.deq.valid invalidate Queue8_BundleMap_2.io.deq.bits.extra_id invalidate Queue8_BundleMap_2.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_2.io.deq.bits.tl_state.size node _T_18 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_19 = and(_T_18, arsel_2) connect Queue8_BundleMap_2.io.enq.valid, _T_19 invalidate Queue8_BundleMap_2.io.enq.ready connect Queue8_BundleMap_2.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap_2.io.count node _T_20 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_21 = and(_T_20, rsel_3) node _T_22 = and(_T_21, nodeOut.r.bits.last) connect Queue8_BundleMap_3.io.deq.ready, _T_22 invalidate Queue8_BundleMap_3.io.deq.valid invalidate Queue8_BundleMap_3.io.deq.bits.extra_id invalidate Queue8_BundleMap_3.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_3.io.deq.bits.tl_state.size node _T_23 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_24 = and(_T_23, arsel_3) connect Queue8_BundleMap_3.io.enq.valid, _T_24 invalidate Queue8_BundleMap_3.io.enq.ready connect Queue8_BundleMap_3.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue8_BundleMap_3.io.count node _T_25 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_26 = and(_T_25, rsel_4) node _T_27 = and(_T_26, nodeOut.r.bits.last) connect Queue7_BundleMap.io.deq.ready, _T_27 invalidate Queue7_BundleMap.io.deq.valid invalidate Queue7_BundleMap.io.deq.bits.extra_id invalidate Queue7_BundleMap.io.deq.bits.tl_state.source invalidate Queue7_BundleMap.io.deq.bits.tl_state.size node _T_28 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_29 = and(_T_28, arsel_4) connect Queue7_BundleMap.io.enq.valid, _T_29 invalidate Queue7_BundleMap.io.enq.ready connect Queue7_BundleMap.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap.io.count node _T_30 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_31 = and(_T_30, rsel_5) node _T_32 = and(_T_31, nodeOut.r.bits.last) connect Queue7_BundleMap_1.io.deq.ready, _T_32 invalidate Queue7_BundleMap_1.io.deq.valid invalidate Queue7_BundleMap_1.io.deq.bits.extra_id invalidate Queue7_BundleMap_1.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_1.io.deq.bits.tl_state.size node _T_33 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_34 = and(_T_33, arsel_5) connect Queue7_BundleMap_1.io.enq.valid, _T_34 invalidate Queue7_BundleMap_1.io.enq.ready connect Queue7_BundleMap_1.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_1.io.count node _T_35 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_36 = and(_T_35, rsel_6) node _T_37 = and(_T_36, nodeOut.r.bits.last) connect Queue7_BundleMap_2.io.deq.ready, _T_37 invalidate Queue7_BundleMap_2.io.deq.valid invalidate Queue7_BundleMap_2.io.deq.bits.extra_id invalidate Queue7_BundleMap_2.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_2.io.deq.bits.tl_state.size node _T_38 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_39 = and(_T_38, arsel_6) connect Queue7_BundleMap_2.io.enq.valid, _T_39 invalidate Queue7_BundleMap_2.io.enq.ready connect Queue7_BundleMap_2.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_2.io.count node _T_40 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_41 = and(_T_40, rsel_7) node _T_42 = and(_T_41, nodeOut.r.bits.last) connect Queue7_BundleMap_3.io.deq.ready, _T_42 invalidate Queue7_BundleMap_3.io.deq.valid invalidate Queue7_BundleMap_3.io.deq.bits.extra_id invalidate Queue7_BundleMap_3.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_3.io.deq.bits.tl_state.size node _T_43 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_44 = and(_T_43, arsel_7) connect Queue7_BundleMap_3.io.enq.valid, _T_44 invalidate Queue7_BundleMap_3.io.enq.ready connect Queue7_BundleMap_3.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_3.io.count node _T_45 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_46 = and(_T_45, rsel_8) node _T_47 = and(_T_46, nodeOut.r.bits.last) connect Queue7_BundleMap_4.io.deq.ready, _T_47 invalidate Queue7_BundleMap_4.io.deq.valid invalidate Queue7_BundleMap_4.io.deq.bits.extra_id invalidate Queue7_BundleMap_4.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_4.io.deq.bits.tl_state.size node _T_48 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_49 = and(_T_48, arsel_8) connect Queue7_BundleMap_4.io.enq.valid, _T_49 invalidate Queue7_BundleMap_4.io.enq.ready connect Queue7_BundleMap_4.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_4.io.count node _T_50 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_51 = and(_T_50, rsel_9) node _T_52 = and(_T_51, nodeOut.r.bits.last) connect Queue7_BundleMap_5.io.deq.ready, _T_52 invalidate Queue7_BundleMap_5.io.deq.valid invalidate Queue7_BundleMap_5.io.deq.bits.extra_id invalidate Queue7_BundleMap_5.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_5.io.deq.bits.tl_state.size node _T_53 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_54 = and(_T_53, arsel_9) connect Queue7_BundleMap_5.io.enq.valid, _T_54 invalidate Queue7_BundleMap_5.io.enq.ready connect Queue7_BundleMap_5.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_5.io.count node _T_55 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_56 = and(_T_55, rsel_10) node _T_57 = and(_T_56, nodeOut.r.bits.last) connect Queue7_BundleMap_6.io.deq.ready, _T_57 invalidate Queue7_BundleMap_6.io.deq.valid invalidate Queue7_BundleMap_6.io.deq.bits.extra_id invalidate Queue7_BundleMap_6.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_6.io.deq.bits.tl_state.size node _T_58 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_59 = and(_T_58, arsel_10) connect Queue7_BundleMap_6.io.enq.valid, _T_59 invalidate Queue7_BundleMap_6.io.enq.ready connect Queue7_BundleMap_6.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_6.io.count node _T_60 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_61 = and(_T_60, rsel_11) node _T_62 = and(_T_61, nodeOut.r.bits.last) connect Queue7_BundleMap_7.io.deq.ready, _T_62 invalidate Queue7_BundleMap_7.io.deq.valid invalidate Queue7_BundleMap_7.io.deq.bits.extra_id invalidate Queue7_BundleMap_7.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_7.io.deq.bits.tl_state.size node _T_63 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_64 = and(_T_63, arsel_11) connect Queue7_BundleMap_7.io.enq.valid, _T_64 invalidate Queue7_BundleMap_7.io.enq.ready connect Queue7_BundleMap_7.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_7.io.count node _T_65 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_66 = and(_T_65, rsel_12) node _T_67 = and(_T_66, nodeOut.r.bits.last) connect Queue7_BundleMap_8.io.deq.ready, _T_67 invalidate Queue7_BundleMap_8.io.deq.valid invalidate Queue7_BundleMap_8.io.deq.bits.extra_id invalidate Queue7_BundleMap_8.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_8.io.deq.bits.tl_state.size node _T_68 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_69 = and(_T_68, arsel_12) connect Queue7_BundleMap_8.io.enq.valid, _T_69 invalidate Queue7_BundleMap_8.io.enq.ready connect Queue7_BundleMap_8.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_8.io.count node _T_70 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_71 = and(_T_70, rsel_13) node _T_72 = and(_T_71, nodeOut.r.bits.last) connect Queue7_BundleMap_9.io.deq.ready, _T_72 invalidate Queue7_BundleMap_9.io.deq.valid invalidate Queue7_BundleMap_9.io.deq.bits.extra_id invalidate Queue7_BundleMap_9.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_9.io.deq.bits.tl_state.size node _T_73 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_74 = and(_T_73, arsel_13) connect Queue7_BundleMap_9.io.enq.valid, _T_74 invalidate Queue7_BundleMap_9.io.enq.ready connect Queue7_BundleMap_9.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_9.io.count node _T_75 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_76 = and(_T_75, rsel_14) node _T_77 = and(_T_76, nodeOut.r.bits.last) connect Queue7_BundleMap_10.io.deq.ready, _T_77 invalidate Queue7_BundleMap_10.io.deq.valid invalidate Queue7_BundleMap_10.io.deq.bits.extra_id invalidate Queue7_BundleMap_10.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_10.io.deq.bits.tl_state.size node _T_78 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_79 = and(_T_78, arsel_14) connect Queue7_BundleMap_10.io.enq.valid, _T_79 invalidate Queue7_BundleMap_10.io.enq.ready connect Queue7_BundleMap_10.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_10.io.count node _T_80 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_81 = and(_T_80, rsel_15) node _T_82 = and(_T_81, nodeOut.r.bits.last) connect Queue7_BundleMap_11.io.deq.ready, _T_82 invalidate Queue7_BundleMap_11.io.deq.valid invalidate Queue7_BundleMap_11.io.deq.bits.extra_id invalidate Queue7_BundleMap_11.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_11.io.deq.bits.tl_state.size node _T_83 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_84 = and(_T_83, arsel_15) connect Queue7_BundleMap_11.io.enq.valid, _T_84 invalidate Queue7_BundleMap_11.io.enq.ready connect Queue7_BundleMap_11.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue7_BundleMap_11.io.count wire _aw_ready_WIRE : UInt<1>[16] connect _aw_ready_WIRE[0], Queue8_BundleMap_4.io.enq.ready connect _aw_ready_WIRE[1], Queue8_BundleMap_5.io.enq.ready connect _aw_ready_WIRE[2], Queue8_BundleMap_6.io.enq.ready connect _aw_ready_WIRE[3], Queue8_BundleMap_7.io.enq.ready connect _aw_ready_WIRE[4], Queue7_BundleMap_12.io.enq.ready connect _aw_ready_WIRE[5], Queue7_BundleMap_13.io.enq.ready connect _aw_ready_WIRE[6], Queue7_BundleMap_14.io.enq.ready connect _aw_ready_WIRE[7], Queue7_BundleMap_15.io.enq.ready connect _aw_ready_WIRE[8], Queue7_BundleMap_16.io.enq.ready connect _aw_ready_WIRE[9], Queue7_BundleMap_17.io.enq.ready connect _aw_ready_WIRE[10], Queue7_BundleMap_18.io.enq.ready connect _aw_ready_WIRE[11], Queue7_BundleMap_19.io.enq.ready connect _aw_ready_WIRE[12], Queue7_BundleMap_20.io.enq.ready connect _aw_ready_WIRE[13], Queue7_BundleMap_21.io.enq.ready connect _aw_ready_WIRE[14], Queue7_BundleMap_22.io.enq.ready connect _aw_ready_WIRE[15], Queue7_BundleMap_23.io.enq.ready node _nodeIn_aw_ready_T = and(nodeOut.aw.ready, _aw_ready_WIRE[nodeIn.aw.bits.id]) connect nodeIn.aw.ready, _nodeIn_aw_ready_T node _nodeOut_aw_valid_T = and(nodeIn.aw.valid, _aw_ready_WIRE[nodeIn.aw.bits.id]) connect nodeOut.aw.valid, _nodeOut_aw_valid_T connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id wire _b_valid_WIRE : UInt<1>[16] connect _b_valid_WIRE[0], Queue8_BundleMap_4.io.deq.valid connect _b_valid_WIRE[1], Queue8_BundleMap_5.io.deq.valid connect _b_valid_WIRE[2], Queue8_BundleMap_6.io.deq.valid connect _b_valid_WIRE[3], Queue8_BundleMap_7.io.deq.valid connect _b_valid_WIRE[4], Queue7_BundleMap_12.io.deq.valid connect _b_valid_WIRE[5], Queue7_BundleMap_13.io.deq.valid connect _b_valid_WIRE[6], Queue7_BundleMap_14.io.deq.valid connect _b_valid_WIRE[7], Queue7_BundleMap_15.io.deq.valid connect _b_valid_WIRE[8], Queue7_BundleMap_16.io.deq.valid connect _b_valid_WIRE[9], Queue7_BundleMap_17.io.deq.valid connect _b_valid_WIRE[10], Queue7_BundleMap_18.io.deq.valid connect _b_valid_WIRE[11], Queue7_BundleMap_19.io.deq.valid connect _b_valid_WIRE[12], Queue7_BundleMap_20.io.deq.valid connect _b_valid_WIRE[13], Queue7_BundleMap_21.io.deq.valid connect _b_valid_WIRE[14], Queue7_BundleMap_22.io.deq.valid connect _b_valid_WIRE[15], Queue7_BundleMap_23.io.deq.valid wire _b_bits_WIRE : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}[16] connect _b_bits_WIRE[0], Queue8_BundleMap_4.io.deq.bits connect _b_bits_WIRE[1], Queue8_BundleMap_5.io.deq.bits connect _b_bits_WIRE[2], Queue8_BundleMap_6.io.deq.bits connect _b_bits_WIRE[3], Queue8_BundleMap_7.io.deq.bits connect _b_bits_WIRE[4], Queue7_BundleMap_12.io.deq.bits connect _b_bits_WIRE[5], Queue7_BundleMap_13.io.deq.bits connect _b_bits_WIRE[6], Queue7_BundleMap_14.io.deq.bits connect _b_bits_WIRE[7], Queue7_BundleMap_15.io.deq.bits connect _b_bits_WIRE[8], Queue7_BundleMap_16.io.deq.bits connect _b_bits_WIRE[9], Queue7_BundleMap_17.io.deq.bits connect _b_bits_WIRE[10], Queue7_BundleMap_18.io.deq.bits connect _b_bits_WIRE[11], Queue7_BundleMap_19.io.deq.bits connect _b_bits_WIRE[12], Queue7_BundleMap_20.io.deq.bits connect _b_bits_WIRE[13], Queue7_BundleMap_21.io.deq.bits connect _b_bits_WIRE[14], Queue7_BundleMap_22.io.deq.bits connect _b_bits_WIRE[15], Queue7_BundleMap_23.io.deq.bits node _T_85 = eq(nodeOut.b.valid, UInt<1>(0h0)) node _T_86 = or(_T_85, _b_valid_WIRE[nodeOut.b.bits.id]) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at UserYanker.scala:98 assert (!out.b.valid || b_valid) // Q must be ready faster than the response\n") : printf_1 assert(clock, _T_86, UInt<1>(0h1), "") : assert_1 connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.b.bits.echo, _b_bits_WIRE[nodeOut.b.bits.id] node awsel_shiftAmount = bits(nodeIn.aw.bits.id, 3, 0) node _awsel_T = dshl(UInt<1>(0h1), awsel_shiftAmount) node _awsel_T_1 = bits(_awsel_T, 15, 0) node awsel_0 = bits(_awsel_T_1, 0, 0) node awsel_1 = bits(_awsel_T_1, 1, 1) node awsel_2 = bits(_awsel_T_1, 2, 2) node awsel_3 = bits(_awsel_T_1, 3, 3) node awsel_4 = bits(_awsel_T_1, 4, 4) node awsel_5 = bits(_awsel_T_1, 5, 5) node awsel_6 = bits(_awsel_T_1, 6, 6) node awsel_7 = bits(_awsel_T_1, 7, 7) node awsel_8 = bits(_awsel_T_1, 8, 8) node awsel_9 = bits(_awsel_T_1, 9, 9) node awsel_10 = bits(_awsel_T_1, 10, 10) node awsel_11 = bits(_awsel_T_1, 11, 11) node awsel_12 = bits(_awsel_T_1, 12, 12) node awsel_13 = bits(_awsel_T_1, 13, 13) node awsel_14 = bits(_awsel_T_1, 14, 14) node awsel_15 = bits(_awsel_T_1, 15, 15) node bsel_shiftAmount = bits(nodeOut.b.bits.id, 3, 0) node _bsel_T = dshl(UInt<1>(0h1), bsel_shiftAmount) node _bsel_T_1 = bits(_bsel_T, 15, 0) node bsel_0 = bits(_bsel_T_1, 0, 0) node bsel_1 = bits(_bsel_T_1, 1, 1) node bsel_2 = bits(_bsel_T_1, 2, 2) node bsel_3 = bits(_bsel_T_1, 3, 3) node bsel_4 = bits(_bsel_T_1, 4, 4) node bsel_5 = bits(_bsel_T_1, 5, 5) node bsel_6 = bits(_bsel_T_1, 6, 6) node bsel_7 = bits(_bsel_T_1, 7, 7) node bsel_8 = bits(_bsel_T_1, 8, 8) node bsel_9 = bits(_bsel_T_1, 9, 9) node bsel_10 = bits(_bsel_T_1, 10, 10) node bsel_11 = bits(_bsel_T_1, 11, 11) node bsel_12 = bits(_bsel_T_1, 12, 12) node bsel_13 = bits(_bsel_T_1, 13, 13) node bsel_14 = bits(_bsel_T_1, 14, 14) node bsel_15 = bits(_bsel_T_1, 15, 15) node _T_90 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_91 = and(_T_90, bsel_0) connect Queue8_BundleMap_4.io.deq.ready, _T_91 invalidate Queue8_BundleMap_4.io.deq.valid invalidate Queue8_BundleMap_4.io.deq.bits.extra_id invalidate Queue8_BundleMap_4.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_4.io.deq.bits.tl_state.size node _T_92 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_93 = and(_T_92, awsel_0) connect Queue8_BundleMap_4.io.enq.valid, _T_93 invalidate Queue8_BundleMap_4.io.enq.ready connect Queue8_BundleMap_4.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_4.io.count node _T_94 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_95 = and(_T_94, bsel_1) connect Queue8_BundleMap_5.io.deq.ready, _T_95 invalidate Queue8_BundleMap_5.io.deq.valid invalidate Queue8_BundleMap_5.io.deq.bits.extra_id invalidate Queue8_BundleMap_5.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_5.io.deq.bits.tl_state.size node _T_96 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_97 = and(_T_96, awsel_1) connect Queue8_BundleMap_5.io.enq.valid, _T_97 invalidate Queue8_BundleMap_5.io.enq.ready connect Queue8_BundleMap_5.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_5.io.count node _T_98 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_99 = and(_T_98, bsel_2) connect Queue8_BundleMap_6.io.deq.ready, _T_99 invalidate Queue8_BundleMap_6.io.deq.valid invalidate Queue8_BundleMap_6.io.deq.bits.extra_id invalidate Queue8_BundleMap_6.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_6.io.deq.bits.tl_state.size node _T_100 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_101 = and(_T_100, awsel_2) connect Queue8_BundleMap_6.io.enq.valid, _T_101 invalidate Queue8_BundleMap_6.io.enq.ready connect Queue8_BundleMap_6.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_6.io.count node _T_102 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_103 = and(_T_102, bsel_3) connect Queue8_BundleMap_7.io.deq.ready, _T_103 invalidate Queue8_BundleMap_7.io.deq.valid invalidate Queue8_BundleMap_7.io.deq.bits.extra_id invalidate Queue8_BundleMap_7.io.deq.bits.tl_state.source invalidate Queue8_BundleMap_7.io.deq.bits.tl_state.size node _T_104 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_105 = and(_T_104, awsel_3) connect Queue8_BundleMap_7.io.enq.valid, _T_105 invalidate Queue8_BundleMap_7.io.enq.ready connect Queue8_BundleMap_7.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue8_BundleMap_7.io.count node _T_106 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_107 = and(_T_106, bsel_4) connect Queue7_BundleMap_12.io.deq.ready, _T_107 invalidate Queue7_BundleMap_12.io.deq.valid invalidate Queue7_BundleMap_12.io.deq.bits.extra_id invalidate Queue7_BundleMap_12.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_12.io.deq.bits.tl_state.size node _T_108 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_109 = and(_T_108, awsel_4) connect Queue7_BundleMap_12.io.enq.valid, _T_109 invalidate Queue7_BundleMap_12.io.enq.ready connect Queue7_BundleMap_12.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_12.io.count node _T_110 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_111 = and(_T_110, bsel_5) connect Queue7_BundleMap_13.io.deq.ready, _T_111 invalidate Queue7_BundleMap_13.io.deq.valid invalidate Queue7_BundleMap_13.io.deq.bits.extra_id invalidate Queue7_BundleMap_13.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_13.io.deq.bits.tl_state.size node _T_112 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_113 = and(_T_112, awsel_5) connect Queue7_BundleMap_13.io.enq.valid, _T_113 invalidate Queue7_BundleMap_13.io.enq.ready connect Queue7_BundleMap_13.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_13.io.count node _T_114 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_115 = and(_T_114, bsel_6) connect Queue7_BundleMap_14.io.deq.ready, _T_115 invalidate Queue7_BundleMap_14.io.deq.valid invalidate Queue7_BundleMap_14.io.deq.bits.extra_id invalidate Queue7_BundleMap_14.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_14.io.deq.bits.tl_state.size node _T_116 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_117 = and(_T_116, awsel_6) connect Queue7_BundleMap_14.io.enq.valid, _T_117 invalidate Queue7_BundleMap_14.io.enq.ready connect Queue7_BundleMap_14.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_14.io.count node _T_118 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_119 = and(_T_118, bsel_7) connect Queue7_BundleMap_15.io.deq.ready, _T_119 invalidate Queue7_BundleMap_15.io.deq.valid invalidate Queue7_BundleMap_15.io.deq.bits.extra_id invalidate Queue7_BundleMap_15.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_15.io.deq.bits.tl_state.size node _T_120 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_121 = and(_T_120, awsel_7) connect Queue7_BundleMap_15.io.enq.valid, _T_121 invalidate Queue7_BundleMap_15.io.enq.ready connect Queue7_BundleMap_15.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_15.io.count node _T_122 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_123 = and(_T_122, bsel_8) connect Queue7_BundleMap_16.io.deq.ready, _T_123 invalidate Queue7_BundleMap_16.io.deq.valid invalidate Queue7_BundleMap_16.io.deq.bits.extra_id invalidate Queue7_BundleMap_16.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_16.io.deq.bits.tl_state.size node _T_124 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_125 = and(_T_124, awsel_8) connect Queue7_BundleMap_16.io.enq.valid, _T_125 invalidate Queue7_BundleMap_16.io.enq.ready connect Queue7_BundleMap_16.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_16.io.count node _T_126 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_127 = and(_T_126, bsel_9) connect Queue7_BundleMap_17.io.deq.ready, _T_127 invalidate Queue7_BundleMap_17.io.deq.valid invalidate Queue7_BundleMap_17.io.deq.bits.extra_id invalidate Queue7_BundleMap_17.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_17.io.deq.bits.tl_state.size node _T_128 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_129 = and(_T_128, awsel_9) connect Queue7_BundleMap_17.io.enq.valid, _T_129 invalidate Queue7_BundleMap_17.io.enq.ready connect Queue7_BundleMap_17.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_17.io.count node _T_130 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_131 = and(_T_130, bsel_10) connect Queue7_BundleMap_18.io.deq.ready, _T_131 invalidate Queue7_BundleMap_18.io.deq.valid invalidate Queue7_BundleMap_18.io.deq.bits.extra_id invalidate Queue7_BundleMap_18.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_18.io.deq.bits.tl_state.size node _T_132 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_133 = and(_T_132, awsel_10) connect Queue7_BundleMap_18.io.enq.valid, _T_133 invalidate Queue7_BundleMap_18.io.enq.ready connect Queue7_BundleMap_18.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_18.io.count node _T_134 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_135 = and(_T_134, bsel_11) connect Queue7_BundleMap_19.io.deq.ready, _T_135 invalidate Queue7_BundleMap_19.io.deq.valid invalidate Queue7_BundleMap_19.io.deq.bits.extra_id invalidate Queue7_BundleMap_19.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_19.io.deq.bits.tl_state.size node _T_136 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_137 = and(_T_136, awsel_11) connect Queue7_BundleMap_19.io.enq.valid, _T_137 invalidate Queue7_BundleMap_19.io.enq.ready connect Queue7_BundleMap_19.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_19.io.count node _T_138 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_139 = and(_T_138, bsel_12) connect Queue7_BundleMap_20.io.deq.ready, _T_139 invalidate Queue7_BundleMap_20.io.deq.valid invalidate Queue7_BundleMap_20.io.deq.bits.extra_id invalidate Queue7_BundleMap_20.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_20.io.deq.bits.tl_state.size node _T_140 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_141 = and(_T_140, awsel_12) connect Queue7_BundleMap_20.io.enq.valid, _T_141 invalidate Queue7_BundleMap_20.io.enq.ready connect Queue7_BundleMap_20.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_20.io.count node _T_142 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_143 = and(_T_142, bsel_13) connect Queue7_BundleMap_21.io.deq.ready, _T_143 invalidate Queue7_BundleMap_21.io.deq.valid invalidate Queue7_BundleMap_21.io.deq.bits.extra_id invalidate Queue7_BundleMap_21.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_21.io.deq.bits.tl_state.size node _T_144 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_145 = and(_T_144, awsel_13) connect Queue7_BundleMap_21.io.enq.valid, _T_145 invalidate Queue7_BundleMap_21.io.enq.ready connect Queue7_BundleMap_21.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_21.io.count node _T_146 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_147 = and(_T_146, bsel_14) connect Queue7_BundleMap_22.io.deq.ready, _T_147 invalidate Queue7_BundleMap_22.io.deq.valid invalidate Queue7_BundleMap_22.io.deq.bits.extra_id invalidate Queue7_BundleMap_22.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_22.io.deq.bits.tl_state.size node _T_148 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_149 = and(_T_148, awsel_14) connect Queue7_BundleMap_22.io.enq.valid, _T_149 invalidate Queue7_BundleMap_22.io.enq.ready connect Queue7_BundleMap_22.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_22.io.count node _T_150 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_151 = and(_T_150, bsel_15) connect Queue7_BundleMap_23.io.deq.ready, _T_151 invalidate Queue7_BundleMap_23.io.deq.valid invalidate Queue7_BundleMap_23.io.deq.bits.extra_id invalidate Queue7_BundleMap_23.io.deq.bits.tl_state.source invalidate Queue7_BundleMap_23.io.deq.bits.tl_state.size node _T_152 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_153 = and(_T_152, awsel_15) connect Queue7_BundleMap_23.io.enq.valid, _T_153 invalidate Queue7_BundleMap_23.io.enq.ready connect Queue7_BundleMap_23.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue7_BundleMap_23.io.count connect nodeOut.w, nodeIn.w

module AXI4UserYanker( // @[UserYanker.scala:36:9] input clock, // @[UserYanker.scala:36:9] input reset, // @[UserYanker.scala:36:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire _Queue7_BundleMap_23_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_23_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_23_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_23_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_23_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_22_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_22_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_22_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_22_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_22_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_21_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_21_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_21_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_21_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_21_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_20_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_20_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_20_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_20_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_20_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_19_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_19_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_19_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_19_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_19_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_18_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_18_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_18_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_18_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_18_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_17_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_17_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_17_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_17_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_17_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_16_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_16_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_16_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_16_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_16_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_15_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_15_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_15_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_15_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_15_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_14_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_14_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_14_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_14_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_14_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_13_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_13_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_13_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_13_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_13_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_12_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_12_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_12_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_12_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_12_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_7_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_7_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_7_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_7_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_7_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_6_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_6_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_6_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_6_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_6_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_5_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_5_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_5_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_5_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_5_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_4_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_4_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_4_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_4_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_4_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_11_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_11_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_11_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_11_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_11_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_10_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_10_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_10_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_10_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_10_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_9_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_9_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_9_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_9_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_9_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_8_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_8_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_8_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_8_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_8_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_7_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_7_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_7_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_7_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_7_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_6_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_6_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_6_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_6_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_6_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_5_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_5_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_5_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_5_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_5_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_4_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_4_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_4_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_4_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_4_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_3_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_3_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_3_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_3_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_3_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_2_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_2_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_2_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_2_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_2_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_1_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_1_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_1_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_1_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_1_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue7_BundleMap_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue7_BundleMap_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue7_BundleMap_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue7_BundleMap_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_3_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_3_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_3_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_3_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_3_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_2_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_2_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_2_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_2_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_2_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_1_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_1_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_1_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_1_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_1_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_io_enq_ready; // @[UserYanker.scala:51:17] wire _Queue8_BundleMap_io_deq_valid; // @[UserYanker.scala:51:17] wire [3:0] _Queue8_BundleMap_io_deq_bits_tl_state_size; // @[UserYanker.scala:51:17] wire [6:0] _Queue8_BundleMap_io_deq_bits_tl_state_source; // @[UserYanker.scala:51:17] wire [2:0] _Queue8_BundleMap_io_deq_bits_extra_id; // @[UserYanker.scala:51:17] wire [15:0] _GEN = {{_Queue7_BundleMap_11_io_enq_ready}, {_Queue7_BundleMap_10_io_enq_ready}, {_Queue7_BundleMap_9_io_enq_ready}, {_Queue7_BundleMap_8_io_enq_ready}, {_Queue7_BundleMap_7_io_enq_ready}, {_Queue7_BundleMap_6_io_enq_ready}, {_Queue7_BundleMap_5_io_enq_ready}, {_Queue7_BundleMap_4_io_enq_ready}, {_Queue7_BundleMap_3_io_enq_ready}, {_Queue7_BundleMap_2_io_enq_ready}, {_Queue7_BundleMap_1_io_enq_ready}, {_Queue7_BundleMap_io_enq_ready}, {_Queue8_BundleMap_3_io_enq_ready}, {_Queue8_BundleMap_2_io_enq_ready}, {_Queue8_BundleMap_1_io_enq_ready}, {_Queue8_BundleMap_io_enq_ready}}; // @[UserYanker.scala:51:17, :60:36] wire [15:0][3:0] _GEN_0 = {{_Queue7_BundleMap_11_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_10_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_9_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_8_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_7_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_6_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_5_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_4_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_3_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_2_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_1_io_deq_bits_tl_state_size}, {_Queue7_BundleMap_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_3_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_2_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_1_io_deq_bits_tl_state_size}, {_Queue8_BundleMap_io_deq_bits_tl_state_size}}; // @[UserYanker.scala:51:17, :73:22] wire [15:0][6:0] _GEN_1 = {{_Queue7_BundleMap_11_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_10_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_9_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_8_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_7_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_6_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_5_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_4_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_3_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_2_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_1_io_deq_bits_tl_state_source}, {_Queue7_BundleMap_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_3_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_2_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_1_io_deq_bits_tl_state_source}, {_Queue8_BundleMap_io_deq_bits_tl_state_source}}; // @[UserYanker.scala:51:17, :73:22] wire [15:0][2:0] _GEN_2 = {{_Queue7_BundleMap_11_io_deq_bits_extra_id}, {_Queue7_BundleMap_10_io_deq_bits_extra_id}, {_Queue7_BundleMap_9_io_deq_bits_extra_id}, {_Queue7_BundleMap_8_io_deq_bits_extra_id}, {_Queue7_BundleMap_7_io_deq_bits_extra_id}, {_Queue7_BundleMap_6_io_deq_bits_extra_id}, {_Queue7_BundleMap_5_io_deq_bits_extra_id}, {_Queue7_BundleMap_4_io_deq_bits_extra_id}, {_Queue7_BundleMap_3_io_deq_bits_extra_id}, {_Queue7_BundleMap_2_io_deq_bits_extra_id}, {_Queue7_BundleMap_1_io_deq_bits_extra_id}, {_Queue7_BundleMap_io_deq_bits_extra_id}, {_Queue8_BundleMap_3_io_deq_bits_extra_id}, {_Queue8_BundleMap_2_io_deq_bits_extra_id}, {_Queue8_BundleMap_1_io_deq_bits_extra_id}, {_Queue8_BundleMap_io_deq_bits_extra_id}}; // @[UserYanker.scala:51:17, :73:22] wire _GEN_3 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala:78:37] wire _GEN_4 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala:81:37] wire [15:0] _GEN_5 = {{_Queue7_BundleMap_23_io_enq_ready}, {_Queue7_BundleMap_22_io_enq_ready}, {_Queue7_BundleMap_21_io_enq_ready}, {_Queue7_BundleMap_20_io_enq_ready}, {_Queue7_BundleMap_19_io_enq_ready}, {_Queue7_BundleMap_18_io_enq_ready}, {_Queue7_BundleMap_17_io_enq_ready}, {_Queue7_BundleMap_16_io_enq_ready}, {_Queue7_BundleMap_15_io_enq_ready}, {_Queue7_BundleMap_14_io_enq_ready}, {_Queue7_BundleMap_13_io_enq_ready}, {_Queue7_BundleMap_12_io_enq_ready}, {_Queue8_BundleMap_7_io_enq_ready}, {_Queue8_BundleMap_6_io_enq_ready}, {_Queue8_BundleMap_5_io_enq_ready}, {_Queue8_BundleMap_4_io_enq_ready}}; // @[UserYanker.scala:51:17, :89:36]

Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_14 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `1` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `0` : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<20> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_14, decoded_andMatrixOutputs_andMatrixInput_15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_12, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_12_1, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_8_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_decoded_orMatrixOutputs_T_6, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs, 12, 12) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs, 13, 13) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs, 14, 14) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs, 15, 15) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs, 16, 16) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs, 17, 17) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs, 18, 18) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs, 19, 19) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs, 20, 20) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs, 21, 21) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs, 22, 22) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo) node decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_invMatrixOutputs_lo_hi_lo_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, decoded_invMatrixOutputs_lo_hi_lo) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_invMatrixOutputs_hi_lo_lo_hi, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, decoded_invMatrixOutputs_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_20, _decoded_invMatrixOutputs_T_19) node decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_invMatrixOutputs_hi_hi_lo_hi, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi, _decoded_invMatrixOutputs_T_21) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_lo) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 15, 0) node _decoded_T_1 = shl(UInt<8>(0hff), 8) node _decoded_T_2 = xor(UInt<16>(0hffff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 8) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 7, 0) node _decoded_T_6 = shl(_decoded_T_5, 8) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 11, 0) node _decoded_T_11 = shl(_decoded_T_10, 4) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 4) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 11, 0) node _decoded_T_16 = shl(_decoded_T_15, 4) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 13, 0) node _decoded_T_21 = shl(_decoded_T_20, 2) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 2) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 13, 0) node _decoded_T_26 = shl(_decoded_T_25, 2) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(_decoded_T_22, 14, 0) node _decoded_T_31 = shl(_decoded_T_30, 1) node _decoded_T_32 = xor(_decoded_T_22, _decoded_T_31) node _decoded_T_33 = shr(_decoded_T_29, 1) node _decoded_T_34 = and(_decoded_T_33, _decoded_T_32) node _decoded_T_35 = bits(_decoded_T_29, 14, 0) node _decoded_T_36 = shl(_decoded_T_35, 1) node _decoded_T_37 = not(_decoded_T_32) node _decoded_T_38 = and(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = or(_decoded_T_34, _decoded_T_38) node _decoded_T_40 = bits(decoded_plaOutput, 23, 16) node _decoded_T_41 = shl(UInt<4>(0hf), 4) node _decoded_T_42 = xor(UInt<8>(0hff), _decoded_T_41) node _decoded_T_43 = shr(_decoded_T_40, 4) node _decoded_T_44 = and(_decoded_T_43, _decoded_T_42) node _decoded_T_45 = bits(_decoded_T_40, 3, 0) node _decoded_T_46 = shl(_decoded_T_45, 4) node _decoded_T_47 = not(_decoded_T_42) node _decoded_T_48 = and(_decoded_T_46, _decoded_T_47) node _decoded_T_49 = or(_decoded_T_44, _decoded_T_48) node _decoded_T_50 = bits(_decoded_T_42, 5, 0) node _decoded_T_51 = shl(_decoded_T_50, 2) node _decoded_T_52 = xor(_decoded_T_42, _decoded_T_51) node _decoded_T_53 = shr(_decoded_T_49, 2) node _decoded_T_54 = and(_decoded_T_53, _decoded_T_52) node _decoded_T_55 = bits(_decoded_T_49, 5, 0) node _decoded_T_56 = shl(_decoded_T_55, 2) node _decoded_T_57 = not(_decoded_T_52) node _decoded_T_58 = and(_decoded_T_56, _decoded_T_57) node _decoded_T_59 = or(_decoded_T_54, _decoded_T_58) node _decoded_T_60 = bits(_decoded_T_52, 6, 0) node _decoded_T_61 = shl(_decoded_T_60, 1) node _decoded_T_62 = xor(_decoded_T_52, _decoded_T_61) node _decoded_T_63 = shr(_decoded_T_59, 1) node _decoded_T_64 = and(_decoded_T_63, _decoded_T_62) node _decoded_T_65 = bits(_decoded_T_59, 6, 0) node _decoded_T_66 = shl(_decoded_T_65, 1) node _decoded_T_67 = not(_decoded_T_62) node _decoded_T_68 = and(_decoded_T_66, _decoded_T_67) node _decoded_T_69 = or(_decoded_T_64, _decoded_T_68) node decoded = cat(_decoded_T_39, _decoded_T_69) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_1_3_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`1`[3], _io_resp_0_vc_sel_1_3_T node _io_resp_0_vc_sel_1_4_T = bits(decoded, 12, 12) connect io.resp.`0`.vc_sel.`1`[4], _io_resp_0_vc_sel_1_4_T node _io_resp_0_vc_sel_1_5_T = bits(decoded, 13, 13) connect io.resp.`0`.vc_sel.`1`[5], _io_resp_0_vc_sel_1_5_T node _io_resp_0_vc_sel_1_6_T = bits(decoded, 14, 14) connect io.resp.`0`.vc_sel.`1`[6], _io_resp_0_vc_sel_1_6_T node _io_resp_0_vc_sel_1_7_T = bits(decoded, 15, 15) connect io.resp.`0`.vc_sel.`1`[7], _io_resp_0_vc_sel_1_7_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 16, 16) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 17, 17) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 18, 18) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_2_3_T = bits(decoded, 19, 19) connect io.resp.`0`.vc_sel.`2`[3], _io_resp_0_vc_sel_2_3_T node _io_resp_0_vc_sel_2_4_T = bits(decoded, 20, 20) connect io.resp.`0`.vc_sel.`2`[4], _io_resp_0_vc_sel_2_4_T node _io_resp_0_vc_sel_2_5_T = bits(decoded, 21, 21) connect io.resp.`0`.vc_sel.`2`[5], _io_resp_0_vc_sel_2_5_T node _io_resp_0_vc_sel_2_6_T = bits(decoded, 22, 22) connect io.resp.`0`.vc_sel.`2`[6], _io_resp_0_vc_sel_2_6_T node _io_resp_0_vc_sel_2_7_T = bits(decoded, 23, 23) connect io.resp.`0`.vc_sel.`2`[7], _io_resp_0_vc_sel_2_7_T connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<20> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_14_2, decoded_andMatrixOutputs_andMatrixInput_15_1) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_14_3, decoded_andMatrixOutputs_andMatrixInput_15_2) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_12_3, decoded_andMatrixOutputs_andMatrixInput_13_3) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_lo_lo_lo_2) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_10_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_12_4, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_14_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_14_5, decoded_andMatrixOutputs_andMatrixInput_15_3) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_12_5, decoded_andMatrixOutputs_andMatrixInput_13_5) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_3) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_10_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_14_6, decoded_andMatrixOutputs_andMatrixInput_15_4) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_12_6, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_lo_lo_lo_4) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_12_7, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_14_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_hi_lo_lo_7) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_10, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_plaInput_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_11, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_14_8, decoded_andMatrixOutputs_andMatrixInput_15_5) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_12_8, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_5) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_10_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_10, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_8) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_14_9, decoded_andMatrixOutputs_andMatrixInput_15_6) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_12_9, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_lo_lo_lo_6) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_10_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_hi_lo_lo_9) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_14, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_12_10, decoded_andMatrixOutputs_andMatrixInput_13_10) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_14_10) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_10_10, decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_andMatrixOutputs_andMatrixInput_9_10) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_14, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_hi_lo_lo_10) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_15, decoded_andMatrixOutputs_andMatrixInput_3_14) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_plaInput_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_7_15, decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_5_15, decoded_andMatrixOutputs_andMatrixInput_6_15) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_plaInput_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_plaInput_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_16, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_17, decoded_andMatrixOutputs_andMatrixInput_3_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_16 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node decoded_orMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_18 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node decoded_orMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_2_2_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_13_2) node _decoded_orMatrixOutputs_T_20 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_6) node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_13_2, decoded_andMatrixOutputs_2_2_1) node decoded_orMatrixOutputs_lo_7 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_8_2) node _decoded_orMatrixOutputs_T_22 = cat(decoded_orMatrixOutputs_hi_7, decoded_orMatrixOutputs_lo_7) node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_8 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_1) node _decoded_orMatrixOutputs_T_24 = cat(decoded_orMatrixOutputs_hi_8, decoded_orMatrixOutputs_lo_8) node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_9 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_2) node _decoded_orMatrixOutputs_T_26 = cat(decoded_orMatrixOutputs_hi_9, decoded_orMatrixOutputs_lo_9) node _decoded_orMatrixOutputs_T_27 = orr(_decoded_orMatrixOutputs_T_26) node decoded_orMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_10 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_3) node _decoded_orMatrixOutputs_T_28 = cat(decoded_orMatrixOutputs_hi_10, decoded_orMatrixOutputs_lo_10) node _decoded_orMatrixOutputs_T_29 = orr(_decoded_orMatrixOutputs_T_28) node decoded_orMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_11 = cat(decoded_orMatrixOutputs_lo_hi_5, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_11 = cat(decoded_orMatrixOutputs_hi_hi_5, decoded_orMatrixOutputs_hi_lo_4) node _decoded_orMatrixOutputs_T_30 = cat(decoded_orMatrixOutputs_hi_11, decoded_orMatrixOutputs_lo_11) node _decoded_orMatrixOutputs_T_31 = orr(_decoded_orMatrixOutputs_T_30) node decoded_orMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_12 = cat(decoded_orMatrixOutputs_lo_hi_6, decoded_orMatrixOutputs_lo_lo_5) node decoded_orMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_6, decoded_orMatrixOutputs_hi_lo_5) node _decoded_orMatrixOutputs_T_32 = cat(decoded_orMatrixOutputs_hi_12, decoded_orMatrixOutputs_lo_12) node _decoded_orMatrixOutputs_T_33 = orr(_decoded_orMatrixOutputs_T_32) node decoded_orMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_13 = cat(decoded_orMatrixOutputs_lo_hi_7, decoded_orMatrixOutputs_lo_lo_6) node decoded_orMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_7, decoded_orMatrixOutputs_hi_lo_6) node _decoded_orMatrixOutputs_T_34 = cat(decoded_orMatrixOutputs_hi_13, decoded_orMatrixOutputs_lo_13) node _decoded_orMatrixOutputs_T_35 = orr(_decoded_orMatrixOutputs_T_34) node decoded_orMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_14 = cat(decoded_orMatrixOutputs_lo_hi_8, decoded_orMatrixOutputs_lo_lo_7) node decoded_orMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_9_2) node decoded_orMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_8, decoded_orMatrixOutputs_hi_lo_7) node _decoded_orMatrixOutputs_T_36 = cat(decoded_orMatrixOutputs_hi_14, decoded_orMatrixOutputs_lo_14) node _decoded_orMatrixOutputs_T_37 = orr(_decoded_orMatrixOutputs_T_36) node decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_15, _decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_1, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_21, _decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_1, _decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_lo_lo_8 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, decoded_orMatrixOutputs_lo_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_1, _decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_9 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_orMatrixOutputs_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_15 = cat(decoded_orMatrixOutputs_lo_hi_9, decoded_orMatrixOutputs_lo_lo_8) node decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_25) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_8 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, decoded_orMatrixOutputs_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_33, _decoded_orMatrixOutputs_T_31) node decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_1, _decoded_orMatrixOutputs_T_29) node decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_37) node decoded_orMatrixOutputs_hi_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_1, _decoded_orMatrixOutputs_T_35) node decoded_orMatrixOutputs_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_8, decoded_orMatrixOutputs_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_9, decoded_orMatrixOutputs_hi_lo_8) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_15, decoded_orMatrixOutputs_lo_15) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_1, 11, 11) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_1, 12, 12) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_1, 13, 13) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_1, 14, 14) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_1, 15, 15) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_1, 16, 16) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_1, 17, 17) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_1, 18, 18) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_1, 19, 19) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_1, 20, 20) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_1, 21, 21) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_1, 22, 22) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_1, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25) node decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_1, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_1, _decoded_invMatrixOutputs_T_27) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_1, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_1, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, decoded_invMatrixOutputs_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_1, _decoded_invMatrixOutputs_T_36) node decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_41, _decoded_invMatrixOutputs_T_40) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_1, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_1, _decoded_invMatrixOutputs_T_42) node decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_1, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_70 = bits(decoded_plaOutput_1, 15, 0) node _decoded_T_71 = shl(UInt<8>(0hff), 8) node _decoded_T_72 = xor(UInt<16>(0hffff), _decoded_T_71) node _decoded_T_73 = shr(_decoded_T_70, 8) node _decoded_T_74 = and(_decoded_T_73, _decoded_T_72) node _decoded_T_75 = bits(_decoded_T_70, 7, 0) node _decoded_T_76 = shl(_decoded_T_75, 8) node _decoded_T_77 = not(_decoded_T_72) node _decoded_T_78 = and(_decoded_T_76, _decoded_T_77) node _decoded_T_79 = or(_decoded_T_74, _decoded_T_78) node _decoded_T_80 = bits(_decoded_T_72, 11, 0) node _decoded_T_81 = shl(_decoded_T_80, 4) node _decoded_T_82 = xor(_decoded_T_72, _decoded_T_81) node _decoded_T_83 = shr(_decoded_T_79, 4) node _decoded_T_84 = and(_decoded_T_83, _decoded_T_82) node _decoded_T_85 = bits(_decoded_T_79, 11, 0) node _decoded_T_86 = shl(_decoded_T_85, 4) node _decoded_T_87 = not(_decoded_T_82) node _decoded_T_88 = and(_decoded_T_86, _decoded_T_87) node _decoded_T_89 = or(_decoded_T_84, _decoded_T_88) node _decoded_T_90 = bits(_decoded_T_82, 13, 0) node _decoded_T_91 = shl(_decoded_T_90, 2) node _decoded_T_92 = xor(_decoded_T_82, _decoded_T_91) node _decoded_T_93 = shr(_decoded_T_89, 2) node _decoded_T_94 = and(_decoded_T_93, _decoded_T_92) node _decoded_T_95 = bits(_decoded_T_89, 13, 0) node _decoded_T_96 = shl(_decoded_T_95, 2) node _decoded_T_97 = not(_decoded_T_92) node _decoded_T_98 = and(_decoded_T_96, _decoded_T_97) node _decoded_T_99 = or(_decoded_T_94, _decoded_T_98) node _decoded_T_100 = bits(_decoded_T_92, 14, 0) node _decoded_T_101 = shl(_decoded_T_100, 1) node _decoded_T_102 = xor(_decoded_T_92, _decoded_T_101) node _decoded_T_103 = shr(_decoded_T_99, 1) node _decoded_T_104 = and(_decoded_T_103, _decoded_T_102) node _decoded_T_105 = bits(_decoded_T_99, 14, 0) node _decoded_T_106 = shl(_decoded_T_105, 1) node _decoded_T_107 = not(_decoded_T_102) node _decoded_T_108 = and(_decoded_T_106, _decoded_T_107) node _decoded_T_109 = or(_decoded_T_104, _decoded_T_108) node _decoded_T_110 = bits(decoded_plaOutput_1, 23, 16) node _decoded_T_111 = shl(UInt<4>(0hf), 4) node _decoded_T_112 = xor(UInt<8>(0hff), _decoded_T_111) node _decoded_T_113 = shr(_decoded_T_110, 4) node _decoded_T_114 = and(_decoded_T_113, _decoded_T_112) node _decoded_T_115 = bits(_decoded_T_110, 3, 0) node _decoded_T_116 = shl(_decoded_T_115, 4) node _decoded_T_117 = not(_decoded_T_112) node _decoded_T_118 = and(_decoded_T_116, _decoded_T_117) node _decoded_T_119 = or(_decoded_T_114, _decoded_T_118) node _decoded_T_120 = bits(_decoded_T_112, 5, 0) node _decoded_T_121 = shl(_decoded_T_120, 2) node _decoded_T_122 = xor(_decoded_T_112, _decoded_T_121) node _decoded_T_123 = shr(_decoded_T_119, 2) node _decoded_T_124 = and(_decoded_T_123, _decoded_T_122) node _decoded_T_125 = bits(_decoded_T_119, 5, 0) node _decoded_T_126 = shl(_decoded_T_125, 2) node _decoded_T_127 = not(_decoded_T_122) node _decoded_T_128 = and(_decoded_T_126, _decoded_T_127) node _decoded_T_129 = or(_decoded_T_124, _decoded_T_128) node _decoded_T_130 = bits(_decoded_T_122, 6, 0) node _decoded_T_131 = shl(_decoded_T_130, 1) node _decoded_T_132 = xor(_decoded_T_122, _decoded_T_131) node _decoded_T_133 = shr(_decoded_T_129, 1) node _decoded_T_134 = and(_decoded_T_133, _decoded_T_132) node _decoded_T_135 = bits(_decoded_T_129, 6, 0) node _decoded_T_136 = shl(_decoded_T_135, 1) node _decoded_T_137 = not(_decoded_T_132) node _decoded_T_138 = and(_decoded_T_136, _decoded_T_137) node _decoded_T_139 = or(_decoded_T_134, _decoded_T_138) node decoded_1 = cat(_decoded_T_109, _decoded_T_139) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_1_3_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`1`[3], _io_resp_1_vc_sel_1_3_T node _io_resp_1_vc_sel_1_4_T = bits(decoded_1, 12, 12) connect io.resp.`1`.vc_sel.`1`[4], _io_resp_1_vc_sel_1_4_T node _io_resp_1_vc_sel_1_5_T = bits(decoded_1, 13, 13) connect io.resp.`1`.vc_sel.`1`[5], _io_resp_1_vc_sel_1_5_T node _io_resp_1_vc_sel_1_6_T = bits(decoded_1, 14, 14) connect io.resp.`1`.vc_sel.`1`[6], _io_resp_1_vc_sel_1_6_T node _io_resp_1_vc_sel_1_7_T = bits(decoded_1, 15, 15) connect io.resp.`1`.vc_sel.`1`[7], _io_resp_1_vc_sel_1_7_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 16, 16) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 17, 17) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 18, 18) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_2_3_T = bits(decoded_1, 19, 19) connect io.resp.`1`.vc_sel.`2`[3], _io_resp_1_vc_sel_2_3_T node _io_resp_1_vc_sel_2_4_T = bits(decoded_1, 20, 20) connect io.resp.`1`.vc_sel.`2`[4], _io_resp_1_vc_sel_2_4_T node _io_resp_1_vc_sel_2_5_T = bits(decoded_1, 21, 21) connect io.resp.`1`.vc_sel.`2`[5], _io_resp_1_vc_sel_2_5_T node _io_resp_1_vc_sel_2_6_T = bits(decoded_1, 22, 22) connect io.resp.`1`.vc_sel.`2`[6], _io_resp_1_vc_sel_2_6_T node _io_resp_1_vc_sel_2_7_T = bits(decoded_1, 23, 23) connect io.resp.`1`.vc_sel.`2`[7], _io_resp_1_vc_sel_2_7_T connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<20> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<24> node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_plaInput_2, 17, 17) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_plaInput_2, 18, 18) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_21) node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_plaInput_2, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_invInputs_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_plaInput_2, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_23) node _decoded_orMatrixOutputs_T_38 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_39 = orr(_decoded_orMatrixOutputs_T_38) node _decoded_orMatrixOutputs_T_40 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_41 = orr(_decoded_orMatrixOutputs_T_40) node _decoded_orMatrixOutputs_T_42 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_43 = orr(_decoded_orMatrixOutputs_T_42) node _decoded_orMatrixOutputs_T_44 = orr(decoded_andMatrixOutputs_2_2_2) node decoded_orMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_45 = cat(decoded_orMatrixOutputs_hi_16, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_46 = orr(_decoded_orMatrixOutputs_T_45) node decoded_orMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_47 = cat(decoded_orMatrixOutputs_hi_17, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_48 = orr(_decoded_orMatrixOutputs_T_47) node decoded_orMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_49 = cat(decoded_orMatrixOutputs_hi_18, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_50 = orr(_decoded_orMatrixOutputs_T_49) node decoded_orMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_51 = cat(decoded_orMatrixOutputs_hi_19, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_52 = orr(_decoded_orMatrixOutputs_T_51) node decoded_orMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_53 = cat(decoded_orMatrixOutputs_hi_20, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_54 = orr(_decoded_orMatrixOutputs_T_53) node decoded_orMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_55 = cat(decoded_orMatrixOutputs_hi_21, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_56 = orr(_decoded_orMatrixOutputs_T_55) node decoded_orMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_5_2_1, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_57 = cat(decoded_orMatrixOutputs_hi_22, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_58 = orr(_decoded_orMatrixOutputs_T_57) node decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_9 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, decoded_orMatrixOutputs_lo_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_39, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_44, _decoded_orMatrixOutputs_T_43) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_2, _decoded_orMatrixOutputs_T_41) node decoded_orMatrixOutputs_lo_hi_10 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, decoded_orMatrixOutputs_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_16 = cat(decoded_orMatrixOutputs_lo_hi_10, decoded_orMatrixOutputs_lo_lo_9) node decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_48, _decoded_orMatrixOutputs_T_46) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_9 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, decoded_orMatrixOutputs_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_54, _decoded_orMatrixOutputs_T_52) node decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_2, _decoded_orMatrixOutputs_T_50) node decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_58) node decoded_orMatrixOutputs_hi_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_2, _decoded_orMatrixOutputs_T_56) node decoded_orMatrixOutputs_hi_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_hi_9, decoded_orMatrixOutputs_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_23 = cat(decoded_orMatrixOutputs_hi_hi_10, decoded_orMatrixOutputs_hi_lo_9) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_23, decoded_orMatrixOutputs_lo_16) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_2, 11, 11) node _decoded_invMatrixOutputs_T_60 = bits(decoded_orMatrixOutputs_2, 12, 12) node _decoded_invMatrixOutputs_T_61 = bits(decoded_orMatrixOutputs_2, 13, 13) node _decoded_invMatrixOutputs_T_62 = bits(decoded_orMatrixOutputs_2, 14, 14) node _decoded_invMatrixOutputs_T_63 = bits(decoded_orMatrixOutputs_2, 15, 15) node _decoded_invMatrixOutputs_T_64 = bits(decoded_orMatrixOutputs_2, 16, 16) node _decoded_invMatrixOutputs_T_65 = bits(decoded_orMatrixOutputs_2, 17, 17) node _decoded_invMatrixOutputs_T_66 = bits(decoded_orMatrixOutputs_2, 18, 18) node _decoded_invMatrixOutputs_T_67 = bits(decoded_orMatrixOutputs_2, 19, 19) node _decoded_invMatrixOutputs_T_68 = bits(decoded_orMatrixOutputs_2, 20, 20) node _decoded_invMatrixOutputs_T_69 = bits(decoded_orMatrixOutputs_2, 21, 21) node _decoded_invMatrixOutputs_T_70 = bits(decoded_orMatrixOutputs_2, 22, 22) node _decoded_invMatrixOutputs_T_71 = bits(decoded_orMatrixOutputs_2, 23, 23) node decoded_invMatrixOutputs_lo_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_50, _decoded_invMatrixOutputs_T_49) node decoded_invMatrixOutputs_lo_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_2, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_2, _decoded_invMatrixOutputs_T_51) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_56, _decoded_invMatrixOutputs_T_55) node decoded_invMatrixOutputs_lo_hi_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_2, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_2, _decoded_invMatrixOutputs_T_57) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, decoded_invMatrixOutputs_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_62, _decoded_invMatrixOutputs_T_61) node decoded_invMatrixOutputs_hi_lo_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_2, _decoded_invMatrixOutputs_T_60) node decoded_invMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_65, _decoded_invMatrixOutputs_T_64) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_2, _decoded_invMatrixOutputs_T_63) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_68, _decoded_invMatrixOutputs_T_67) node decoded_invMatrixOutputs_hi_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_2, _decoded_invMatrixOutputs_T_66) node decoded_invMatrixOutputs_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_71, _decoded_invMatrixOutputs_T_70) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_2, _decoded_invMatrixOutputs_T_69) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_140 = bits(decoded_plaOutput_2, 15, 0) node _decoded_T_141 = shl(UInt<8>(0hff), 8) node _decoded_T_142 = xor(UInt<16>(0hffff), _decoded_T_141) node _decoded_T_143 = shr(_decoded_T_140, 8) node _decoded_T_144 = and(_decoded_T_143, _decoded_T_142) node _decoded_T_145 = bits(_decoded_T_140, 7, 0) node _decoded_T_146 = shl(_decoded_T_145, 8) node _decoded_T_147 = not(_decoded_T_142) node _decoded_T_148 = and(_decoded_T_146, _decoded_T_147) node _decoded_T_149 = or(_decoded_T_144, _decoded_T_148) node _decoded_T_150 = bits(_decoded_T_142, 11, 0) node _decoded_T_151 = shl(_decoded_T_150, 4) node _decoded_T_152 = xor(_decoded_T_142, _decoded_T_151) node _decoded_T_153 = shr(_decoded_T_149, 4) node _decoded_T_154 = and(_decoded_T_153, _decoded_T_152) node _decoded_T_155 = bits(_decoded_T_149, 11, 0) node _decoded_T_156 = shl(_decoded_T_155, 4) node _decoded_T_157 = not(_decoded_T_152) node _decoded_T_158 = and(_decoded_T_156, _decoded_T_157) node _decoded_T_159 = or(_decoded_T_154, _decoded_T_158) node _decoded_T_160 = bits(_decoded_T_152, 13, 0) node _decoded_T_161 = shl(_decoded_T_160, 2) node _decoded_T_162 = xor(_decoded_T_152, _decoded_T_161) node _decoded_T_163 = shr(_decoded_T_159, 2) node _decoded_T_164 = and(_decoded_T_163, _decoded_T_162) node _decoded_T_165 = bits(_decoded_T_159, 13, 0) node _decoded_T_166 = shl(_decoded_T_165, 2) node _decoded_T_167 = not(_decoded_T_162) node _decoded_T_168 = and(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = or(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_162, 14, 0) node _decoded_T_171 = shl(_decoded_T_170, 1) node _decoded_T_172 = xor(_decoded_T_162, _decoded_T_171) node _decoded_T_173 = shr(_decoded_T_169, 1) node _decoded_T_174 = and(_decoded_T_173, _decoded_T_172) node _decoded_T_175 = bits(_decoded_T_169, 14, 0) node _decoded_T_176 = shl(_decoded_T_175, 1) node _decoded_T_177 = not(_decoded_T_172) node _decoded_T_178 = and(_decoded_T_176, _decoded_T_177) node _decoded_T_179 = or(_decoded_T_174, _decoded_T_178) node _decoded_T_180 = bits(decoded_plaOutput_2, 23, 16) node _decoded_T_181 = shl(UInt<4>(0hf), 4) node _decoded_T_182 = xor(UInt<8>(0hff), _decoded_T_181) node _decoded_T_183 = shr(_decoded_T_180, 4) node _decoded_T_184 = and(_decoded_T_183, _decoded_T_182) node _decoded_T_185 = bits(_decoded_T_180, 3, 0) node _decoded_T_186 = shl(_decoded_T_185, 4) node _decoded_T_187 = not(_decoded_T_182) node _decoded_T_188 = and(_decoded_T_186, _decoded_T_187) node _decoded_T_189 = or(_decoded_T_184, _decoded_T_188) node _decoded_T_190 = bits(_decoded_T_182, 5, 0) node _decoded_T_191 = shl(_decoded_T_190, 2) node _decoded_T_192 = xor(_decoded_T_182, _decoded_T_191) node _decoded_T_193 = shr(_decoded_T_189, 2) node _decoded_T_194 = and(_decoded_T_193, _decoded_T_192) node _decoded_T_195 = bits(_decoded_T_189, 5, 0) node _decoded_T_196 = shl(_decoded_T_195, 2) node _decoded_T_197 = not(_decoded_T_192) node _decoded_T_198 = and(_decoded_T_196, _decoded_T_197) node _decoded_T_199 = or(_decoded_T_194, _decoded_T_198) node _decoded_T_200 = bits(_decoded_T_192, 6, 0) node _decoded_T_201 = shl(_decoded_T_200, 1) node _decoded_T_202 = xor(_decoded_T_192, _decoded_T_201) node _decoded_T_203 = shr(_decoded_T_199, 1) node _decoded_T_204 = and(_decoded_T_203, _decoded_T_202) node _decoded_T_205 = bits(_decoded_T_199, 6, 0) node _decoded_T_206 = shl(_decoded_T_205, 1) node _decoded_T_207 = not(_decoded_T_202) node _decoded_T_208 = and(_decoded_T_206, _decoded_T_207) node _decoded_T_209 = or(_decoded_T_204, _decoded_T_208) node decoded_2 = cat(_decoded_T_179, _decoded_T_209) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_1_3_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`1`[3], _io_resp_2_vc_sel_1_3_T node _io_resp_2_vc_sel_1_4_T = bits(decoded_2, 12, 12) connect io.resp.`2`.vc_sel.`1`[4], _io_resp_2_vc_sel_1_4_T node _io_resp_2_vc_sel_1_5_T = bits(decoded_2, 13, 13) connect io.resp.`2`.vc_sel.`1`[5], _io_resp_2_vc_sel_1_5_T node _io_resp_2_vc_sel_1_6_T = bits(decoded_2, 14, 14) connect io.resp.`2`.vc_sel.`1`[6], _io_resp_2_vc_sel_1_6_T node _io_resp_2_vc_sel_1_7_T = bits(decoded_2, 15, 15) connect io.resp.`2`.vc_sel.`1`[7], _io_resp_2_vc_sel_1_7_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 16, 16) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 17, 17) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 18, 18) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_2_3_T = bits(decoded_2, 19, 19) connect io.resp.`2`.vc_sel.`2`[3], _io_resp_2_vc_sel_2_3_T node _io_resp_2_vc_sel_2_4_T = bits(decoded_2, 20, 20) connect io.resp.`2`.vc_sel.`2`[4], _io_resp_2_vc_sel_2_4_T node _io_resp_2_vc_sel_2_5_T = bits(decoded_2, 21, 21) connect io.resp.`2`.vc_sel.`2`[5], _io_resp_2_vc_sel_2_5_T node _io_resp_2_vc_sel_2_6_T = bits(decoded_2, 22, 22) connect io.resp.`2`.vc_sel.`2`[6], _io_resp_2_vc_sel_2_6_T node _io_resp_2_vc_sel_2_7_T = bits(decoded_2, 23, 23) connect io.resp.`2`.vc_sel.`2`[7], _io_resp_2_vc_sel_2_7_T extmodule plusarg_reader_32 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20

module RouteComputer_14( // @[RouteComputer.scala:29:7] input [2:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_7 // @[RouteComputer.scala:40:14] ); wire [15:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id[1:0], io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] _decoded_orMatrixOutputs_T_4 = {&{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[2]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire [15:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id[1]}; // @[pla.scala:78:21] wire [15:0] _decoded_andMatrixOutputs_T_3 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_6 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_7 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_8 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_9 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_10 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_11 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_12 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_13 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_14 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _decoded_andMatrixOutputs_T_15 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_andMatrixOutputs_T_16 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _decoded_andMatrixOutputs_T_17 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_invInputs_2 = ~io_req_2_bits_flow_egress_node_id; // @[pla.scala:78:21] wire [2:0] _decoded_andMatrixOutputs_T_18 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _decoded_andMatrixOutputs_T_19 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _decoded_andMatrixOutputs_T_21 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] _decoded_orMatrixOutputs_T_42 = {&{decoded_invInputs_2[0], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] assign io_resp_2_vc_sel_1_4 = &{decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_1_5 = |_decoded_orMatrixOutputs_T_42; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_1_6 = |_decoded_orMatrixOutputs_T_42; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_1_7 = |_decoded_orMatrixOutputs_T_42; // @[pla.scala:114:{19,36}] assign io_resp_2_vc_sel_0_1 = |{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_19, &_decoded_andMatrixOutputs_T_21}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_1 = |{&{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_2 = |{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_3 = |{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_4 = |{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_5 = |{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_6 = |{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_7 = |{&_decoded_andMatrixOutputs_T_9, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_14, &_decoded_andMatrixOutputs_T_15}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_1 = |{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_17}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_5 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_2_6 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_2_7 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_1_4 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_1_5 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_1_6 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] assign io_resp_0_vc_sel_1_7 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_59 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_70 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_59( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_70 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_5 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_5 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut

module DivSqrtRecFMToRaw_small_e5_s11_5( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e5_s11_5 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_110 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_110( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_52 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_308 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_52( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_308 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SynchronizerShiftReg_w1_d3 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = bits(io.d, 0, 0) inst output_chain of NonSyncResetSynchronizerPrimitiveShiftReg_d3 connect output_chain.clock, clock connect output_chain.reset, reset connect output_chain.io.d, _output_T wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module SynchronizerShiftReg_w1_d3( // @[SynchronizerReg.scala:169:7] input clock, // @[SynchronizerReg.scala:169:7] input reset, // @[SynchronizerReg.scala:169:7] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h0; // @[SynchronizerReg.scala:169:7, :173:39] wire _output_T = 1'h0; // @[SynchronizerReg.scala:169:7, :173:39] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:169:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:169:7] NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:169:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE : UInt<1>[7] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5]) node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = and(_T_11, _T_24) node _T_81 = and(_T_80, _T_37) node _T_82 = and(_T_81, _T_50) node _T_83 = and(_T_82, _T_63) node _T_84 = and(_T_83, _T_71) node _T_85 = and(_T_84, _T_79) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_85, UInt<1>(0h1), "") : assert_1 node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_89 : node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<1>(0h0)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_4) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_100 = shr(io.in.a.bits.source, 2) node _T_101 = eq(_T_100, UInt<1>(0h1)) node _T_102 = leq(UInt<1>(0h0), uncommonBits_5) node _T_103 = and(_T_101, _T_102) node _T_104 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_105 = and(_T_103, _T_104) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_106 = shr(io.in.a.bits.source, 2) node _T_107 = eq(_T_106, UInt<2>(0h2)) node _T_108 = leq(UInt<1>(0h0), uncommonBits_6) node _T_109 = and(_T_107, _T_108) node _T_110 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_111 = and(_T_109, _T_110) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<2>(0h3)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_7) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_119 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_120 = or(_T_93, _T_99) node _T_121 = or(_T_120, _T_105) node _T_122 = or(_T_121, _T_111) node _T_123 = or(_T_122, _T_117) node _T_124 = or(_T_123, _T_118) node _T_125 = or(_T_124, _T_119) node _T_126 = and(_T_92, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_129 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<14>(0h2000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<13>(0h1000))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<17>(0h10000))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<18>(0h2f000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<17>(0h10000))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<27>(0h4000000))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<19>(0h40000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = or(_T_133, _T_138) node _T_170 = or(_T_169, _T_143) node _T_171 = or(_T_170, _T_148) node _T_172 = or(_T_171, _T_153) node _T_173 = or(_T_172, _T_158) node _T_174 = or(_T_173, _T_163) node _T_175 = or(_T_174, _T_168) node _T_176 = and(_T_128, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = and(_T_127, _T_177) node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_T_178, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_178, UInt<1>(0h1), "") : assert_2 node _T_182 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_183 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_184 = and(_T_182, _T_183) node _T_185 = or(UInt<1>(0h0), _T_184) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<14>(0h2000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<13>(0h1000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<18>(0h2f000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<17>(0h10000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<19>(0h40000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = or(_T_190, _T_195) node _T_227 = or(_T_226, _T_200) node _T_228 = or(_T_227, _T_205) node _T_229 = or(_T_228, _T_210) node _T_230 = or(_T_229, _T_215) node _T_231 = or(_T_230, _T_220) node _T_232 = or(_T_231, _T_225) node _T_233 = and(_T_185, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(UInt<1>(0h0), _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_8) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_9) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_10) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_11) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_293 = or(_T_266, _T_272) node _T_294 = or(_T_293, _T_278) node _T_295 = or(_T_294, _T_284) node _T_296 = or(_T_295, _T_290) node _T_297 = or(_T_296, _T_291) node _T_298 = or(_T_297, _T_292) node _T_299 = and(_T_265, _T_298) node _T_300 = or(UInt<1>(0h0), _T_299) node _T_301 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_302 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_303 = cvt(_T_302) node _T_304 = and(_T_303, asSInt(UInt<14>(0h2000))) node _T_305 = asSInt(_T_304) node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0))) node _T_307 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<17>(0h10000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<18>(0h2f000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<17>(0h10000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<27>(0h4000000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<19>(0h40000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = or(_T_306, _T_311) node _T_343 = or(_T_342, _T_316) node _T_344 = or(_T_343, _T_321) node _T_345 = or(_T_344, _T_326) node _T_346 = or(_T_345, _T_331) node _T_347 = or(_T_346, _T_336) node _T_348 = or(_T_347, _T_341) node _T_349 = and(_T_301, _T_348) node _T_350 = or(UInt<1>(0h0), _T_349) node _T_351 = and(_T_300, _T_350) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_351, UInt<1>(0h1), "") : assert_10 node _T_355 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_356 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_357 = and(_T_355, _T_356) node _T_358 = or(UInt<1>(0h0), _T_357) node _T_359 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<14>(0h2000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<13>(0h1000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<17>(0h10000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<18>(0h2f000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h10000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<27>(0h4000000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<19>(0h40000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = or(_T_363, _T_368) node _T_400 = or(_T_399, _T_373) node _T_401 = or(_T_400, _T_378) node _T_402 = or(_T_401, _T_383) node _T_403 = or(_T_402, _T_388) node _T_404 = or(_T_403, _T_393) node _T_405 = or(_T_404, _T_398) node _T_406 = and(_T_358, _T_405) node _T_407 = or(UInt<1>(0h0), _T_406) node _T_408 = and(UInt<1>(0h0), _T_407) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_408, UInt<1>(0h1), "") : assert_11 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(source_ok, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_415, UInt<1>(0h1), "") : assert_13 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_422, UInt<1>(0h1), "") : assert_15 node _T_426 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_426, UInt<1>(0h1), "") : assert_16 node _T_430 = not(io.in.a.bits.mask) node _T_431 = eq(_T_430, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_431, UInt<1>(0h1), "") : assert_17 node _T_435 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_435, UInt<1>(0h1), "") : assert_18 node _T_439 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_439 : node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_444 = shr(io.in.a.bits.source, 2) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = leq(UInt<1>(0h0), uncommonBits_12) node _T_447 = and(_T_445, _T_446) node _T_448 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_449 = and(_T_447, _T_448) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_450 = shr(io.in.a.bits.source, 2) node _T_451 = eq(_T_450, UInt<1>(0h1)) node _T_452 = leq(UInt<1>(0h0), uncommonBits_13) node _T_453 = and(_T_451, _T_452) node _T_454 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_455 = and(_T_453, _T_454) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_456 = shr(io.in.a.bits.source, 2) node _T_457 = eq(_T_456, UInt<2>(0h2)) node _T_458 = leq(UInt<1>(0h0), uncommonBits_14) node _T_459 = and(_T_457, _T_458) node _T_460 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_461 = and(_T_459, _T_460) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_462 = shr(io.in.a.bits.source, 2) node _T_463 = eq(_T_462, UInt<2>(0h3)) node _T_464 = leq(UInt<1>(0h0), uncommonBits_15) node _T_465 = and(_T_463, _T_464) node _T_466 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_470 = or(_T_443, _T_449) node _T_471 = or(_T_470, _T_455) node _T_472 = or(_T_471, _T_461) node _T_473 = or(_T_472, _T_467) node _T_474 = or(_T_473, _T_468) node _T_475 = or(_T_474, _T_469) node _T_476 = and(_T_442, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_477, UInt<1>(0h1), "") : assert_19 node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_482 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_483 = and(_T_481, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_486 = cvt(_T_485) node _T_487 = and(_T_486, asSInt(UInt<13>(0h1000))) node _T_488 = asSInt(_T_487) node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0))) node _T_490 = and(_T_484, _T_489) node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_493 = and(_T_491, _T_492) node _T_494 = or(UInt<1>(0h0), _T_493) node _T_495 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<14>(0h2000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<17>(0h10000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<18>(0h2f000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<17>(0h10000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<27>(0h4000000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<19>(0h40000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = or(_T_499, _T_504) node _T_531 = or(_T_530, _T_509) node _T_532 = or(_T_531, _T_514) node _T_533 = or(_T_532, _T_519) node _T_534 = or(_T_533, _T_524) node _T_535 = or(_T_534, _T_529) node _T_536 = and(_T_494, _T_535) node _T_537 = or(UInt<1>(0h0), _T_490) node _T_538 = or(_T_537, _T_536) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_538, UInt<1>(0h1), "") : assert_20 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(source_ok, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(is_aligned, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_548 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_548, UInt<1>(0h1), "") : assert_23 node _T_552 = eq(io.in.a.bits.mask, mask) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_552, UInt<1>(0h1), "") : assert_24 node _T_556 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_556, UInt<1>(0h1), "") : assert_25 node _T_560 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_560 : node _T_561 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_562 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<1>(0h0)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_16) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<1>(0h1)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_17) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_577 = shr(io.in.a.bits.source, 2) node _T_578 = eq(_T_577, UInt<2>(0h2)) node _T_579 = leq(UInt<1>(0h0), uncommonBits_18) node _T_580 = and(_T_578, _T_579) node _T_581 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_582 = and(_T_580, _T_581) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_583 = shr(io.in.a.bits.source, 2) node _T_584 = eq(_T_583, UInt<2>(0h3)) node _T_585 = leq(UInt<1>(0h0), uncommonBits_19) node _T_586 = and(_T_584, _T_585) node _T_587 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_588 = and(_T_586, _T_587) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_591 = or(_T_564, _T_570) node _T_592 = or(_T_591, _T_576) node _T_593 = or(_T_592, _T_582) node _T_594 = or(_T_593, _T_588) node _T_595 = or(_T_594, _T_589) node _T_596 = or(_T_595, _T_590) node _T_597 = and(_T_563, _T_596) node _T_598 = or(UInt<1>(0h0), _T_597) node _T_599 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_600 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_601 = and(_T_599, _T_600) node _T_602 = or(UInt<1>(0h0), _T_601) node _T_603 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = and(_T_602, _T_607) node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_611 = and(_T_609, _T_610) node _T_612 = or(UInt<1>(0h0), _T_611) node _T_613 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<14>(0h2000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<18>(0h2f000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<27>(0h4000000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<13>(0h1000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<19>(0h40000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = or(_T_617, _T_622) node _T_644 = or(_T_643, _T_627) node _T_645 = or(_T_644, _T_632) node _T_646 = or(_T_645, _T_637) node _T_647 = or(_T_646, _T_642) node _T_648 = and(_T_612, _T_647) node _T_649 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_650 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = and(_T_649, _T_654) node _T_656 = or(UInt<1>(0h0), _T_608) node _T_657 = or(_T_656, _T_648) node _T_658 = or(_T_657, _T_655) node _T_659 = and(_T_598, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_659, UInt<1>(0h1), "") : assert_26 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(source_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(is_aligned, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_669, UInt<1>(0h1), "") : assert_29 node _T_673 = eq(io.in.a.bits.mask, mask) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_673, UInt<1>(0h1), "") : assert_30 node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_677 : node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<1>(0h0)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_20) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_688 = shr(io.in.a.bits.source, 2) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_21) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_694 = shr(io.in.a.bits.source, 2) node _T_695 = eq(_T_694, UInt<2>(0h2)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_22) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_699 = and(_T_697, _T_698) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_700 = shr(io.in.a.bits.source, 2) node _T_701 = eq(_T_700, UInt<2>(0h3)) node _T_702 = leq(UInt<1>(0h0), uncommonBits_23) node _T_703 = and(_T_701, _T_702) node _T_704 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_708 = or(_T_681, _T_687) node _T_709 = or(_T_708, _T_693) node _T_710 = or(_T_709, _T_699) node _T_711 = or(_T_710, _T_705) node _T_712 = or(_T_711, _T_706) node _T_713 = or(_T_712, _T_707) node _T_714 = and(_T_680, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_717 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_718 = and(_T_716, _T_717) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = and(_T_719, _T_724) node _T_726 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_727 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_728 = and(_T_726, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<14>(0h2000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<18>(0h2f000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<17>(0h10000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<27>(0h4000000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<13>(0h1000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<19>(0h40000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = or(_T_734, _T_739) node _T_761 = or(_T_760, _T_744) node _T_762 = or(_T_761, _T_749) node _T_763 = or(_T_762, _T_754) node _T_764 = or(_T_763, _T_759) node _T_765 = and(_T_729, _T_764) node _T_766 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_767 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_768 = cvt(_T_767) node _T_769 = and(_T_768, asSInt(UInt<17>(0h10000))) node _T_770 = asSInt(_T_769) node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0))) node _T_772 = and(_T_766, _T_771) node _T_773 = or(UInt<1>(0h0), _T_725) node _T_774 = or(_T_773, _T_765) node _T_775 = or(_T_774, _T_772) node _T_776 = and(_T_715, _T_775) node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(_T_776, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_776, UInt<1>(0h1), "") : assert_31 node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(source_ok, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(is_aligned, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_786 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_786, UInt<1>(0h1), "") : assert_34 node _T_790 = not(mask) node _T_791 = and(io.in.a.bits.mask, _T_790) node _T_792 = eq(_T_791, UInt<1>(0h0)) node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(_T_792, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_792, UInt<1>(0h1), "") : assert_35 node _T_796 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_796 : node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_799 = and(_T_797, _T_798) node _T_800 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_801 = shr(io.in.a.bits.source, 2) node _T_802 = eq(_T_801, UInt<1>(0h0)) node _T_803 = leq(UInt<1>(0h0), uncommonBits_24) node _T_804 = and(_T_802, _T_803) node _T_805 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_806 = and(_T_804, _T_805) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_807 = shr(io.in.a.bits.source, 2) node _T_808 = eq(_T_807, UInt<1>(0h1)) node _T_809 = leq(UInt<1>(0h0), uncommonBits_25) node _T_810 = and(_T_808, _T_809) node _T_811 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_812 = and(_T_810, _T_811) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_813 = shr(io.in.a.bits.source, 2) node _T_814 = eq(_T_813, UInt<2>(0h2)) node _T_815 = leq(UInt<1>(0h0), uncommonBits_26) node _T_816 = and(_T_814, _T_815) node _T_817 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_819 = shr(io.in.a.bits.source, 2) node _T_820 = eq(_T_819, UInt<2>(0h3)) node _T_821 = leq(UInt<1>(0h0), uncommonBits_27) node _T_822 = and(_T_820, _T_821) node _T_823 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_824 = and(_T_822, _T_823) node _T_825 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_826 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_827 = or(_T_800, _T_806) node _T_828 = or(_T_827, _T_812) node _T_829 = or(_T_828, _T_818) node _T_830 = or(_T_829, _T_824) node _T_831 = or(_T_830, _T_825) node _T_832 = or(_T_831, _T_826) node _T_833 = and(_T_799, _T_832) node _T_834 = or(UInt<1>(0h0), _T_833) node _T_835 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_836 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _T_838 = or(UInt<1>(0h0), _T_837) node _T_839 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<14>(0h2000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<13>(0h1000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<18>(0h2f000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<17>(0h10000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<27>(0h4000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<13>(0h1000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<19>(0h40000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = or(_T_843, _T_848) node _T_875 = or(_T_874, _T_853) node _T_876 = or(_T_875, _T_858) node _T_877 = or(_T_876, _T_863) node _T_878 = or(_T_877, _T_868) node _T_879 = or(_T_878, _T_873) node _T_880 = and(_T_838, _T_879) node _T_881 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_882 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<17>(0h10000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = and(_T_881, _T_886) node _T_888 = or(UInt<1>(0h0), _T_880) node _T_889 = or(_T_888, _T_887) node _T_890 = and(_T_834, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_890, UInt<1>(0h1), "") : assert_36 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_900 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_900, UInt<1>(0h1), "") : assert_39 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_904, UInt<1>(0h1), "") : assert_40 node _T_908 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_908 : node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_913 = shr(io.in.a.bits.source, 2) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = leq(UInt<1>(0h0), uncommonBits_28) node _T_916 = and(_T_914, _T_915) node _T_917 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_918 = and(_T_916, _T_917) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_919 = shr(io.in.a.bits.source, 2) node _T_920 = eq(_T_919, UInt<1>(0h1)) node _T_921 = leq(UInt<1>(0h0), uncommonBits_29) node _T_922 = and(_T_920, _T_921) node _T_923 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_924 = and(_T_922, _T_923) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_925 = shr(io.in.a.bits.source, 2) node _T_926 = eq(_T_925, UInt<2>(0h2)) node _T_927 = leq(UInt<1>(0h0), uncommonBits_30) node _T_928 = and(_T_926, _T_927) node _T_929 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_930 = and(_T_928, _T_929) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_931 = shr(io.in.a.bits.source, 2) node _T_932 = eq(_T_931, UInt<2>(0h3)) node _T_933 = leq(UInt<1>(0h0), uncommonBits_31) node _T_934 = and(_T_932, _T_933) node _T_935 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_936 = and(_T_934, _T_935) node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_939 = or(_T_912, _T_918) node _T_940 = or(_T_939, _T_924) node _T_941 = or(_T_940, _T_930) node _T_942 = or(_T_941, _T_936) node _T_943 = or(_T_942, _T_937) node _T_944 = or(_T_943, _T_938) node _T_945 = and(_T_911, _T_944) node _T_946 = or(UInt<1>(0h0), _T_945) node _T_947 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_948 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_949 = and(_T_947, _T_948) node _T_950 = or(UInt<1>(0h0), _T_949) node _T_951 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<14>(0h2000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_957 = cvt(_T_956) node _T_958 = and(_T_957, asSInt(UInt<13>(0h1000))) node _T_959 = asSInt(_T_958) node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0))) node _T_961 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_962 = cvt(_T_961) node _T_963 = and(_T_962, asSInt(UInt<18>(0h2f000))) node _T_964 = asSInt(_T_963) node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0))) node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<17>(0h10000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_977 = cvt(_T_976) node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000))) node _T_979 = asSInt(_T_978) node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0))) node _T_981 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_982 = cvt(_T_981) node _T_983 = and(_T_982, asSInt(UInt<19>(0h40000))) node _T_984 = asSInt(_T_983) node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0))) node _T_986 = or(_T_955, _T_960) node _T_987 = or(_T_986, _T_965) node _T_988 = or(_T_987, _T_970) node _T_989 = or(_T_988, _T_975) node _T_990 = or(_T_989, _T_980) node _T_991 = or(_T_990, _T_985) node _T_992 = and(_T_950, _T_991) node _T_993 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_994 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = and(_T_993, _T_998) node _T_1000 = or(UInt<1>(0h0), _T_992) node _T_1001 = or(_T_1000, _T_999) node _T_1002 = and(_T_946, _T_1001) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_41 node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(source_ok, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(is_aligned, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1012 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_44 node _T_1016 = eq(io.in.a.bits.mask, mask) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_45 node _T_1020 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1020 : node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1022 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1025 = shr(io.in.a.bits.source, 2) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) node _T_1027 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1028 = and(_T_1026, _T_1027) node _T_1029 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1030 = and(_T_1028, _T_1029) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1031 = shr(io.in.a.bits.source, 2) node _T_1032 = eq(_T_1031, UInt<1>(0h1)) node _T_1033 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1034 = and(_T_1032, _T_1033) node _T_1035 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1036 = and(_T_1034, _T_1035) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1037 = shr(io.in.a.bits.source, 2) node _T_1038 = eq(_T_1037, UInt<2>(0h2)) node _T_1039 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1042 = and(_T_1040, _T_1041) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1043 = shr(io.in.a.bits.source, 2) node _T_1044 = eq(_T_1043, UInt<2>(0h3)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1050 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1051 = or(_T_1024, _T_1030) node _T_1052 = or(_T_1051, _T_1036) node _T_1053 = or(_T_1052, _T_1042) node _T_1054 = or(_T_1053, _T_1048) node _T_1055 = or(_T_1054, _T_1049) node _T_1056 = or(_T_1055, _T_1050) node _T_1057 = and(_T_1023, _T_1056) node _T_1058 = or(UInt<1>(0h0), _T_1057) node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = or(UInt<1>(0h0), _T_1061) node _T_1063 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1064 = cvt(_T_1063) node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000))) node _T_1066 = asSInt(_T_1065) node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0))) node _T_1068 = and(_T_1062, _T_1067) node _T_1069 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1070 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1071 = cvt(_T_1070) node _T_1072 = and(_T_1071, asSInt(UInt<14>(0h2000))) node _T_1073 = asSInt(_T_1072) node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0))) node _T_1075 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1076 = cvt(_T_1075) node _T_1077 = and(_T_1076, asSInt(UInt<17>(0h10000))) node _T_1078 = asSInt(_T_1077) node _T_1079 = eq(_T_1078, asSInt(UInt<1>(0h0))) node _T_1080 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1081 = cvt(_T_1080) node _T_1082 = and(_T_1081, asSInt(UInt<18>(0h2f000))) node _T_1083 = asSInt(_T_1082) node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0))) node _T_1085 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1086 = cvt(_T_1085) node _T_1087 = and(_T_1086, asSInt(UInt<17>(0h10000))) node _T_1088 = asSInt(_T_1087) node _T_1089 = eq(_T_1088, asSInt(UInt<1>(0h0))) node _T_1090 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1091 = cvt(_T_1090) node _T_1092 = and(_T_1091, asSInt(UInt<27>(0h4000000))) node _T_1093 = asSInt(_T_1092) node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0))) node _T_1095 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1096 = cvt(_T_1095) node _T_1097 = and(_T_1096, asSInt(UInt<13>(0h1000))) node _T_1098 = asSInt(_T_1097) node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0))) node _T_1100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1101 = cvt(_T_1100) node _T_1102 = and(_T_1101, asSInt(UInt<19>(0h40000))) node _T_1103 = asSInt(_T_1102) node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0))) node _T_1105 = or(_T_1074, _T_1079) node _T_1106 = or(_T_1105, _T_1084) node _T_1107 = or(_T_1106, _T_1089) node _T_1108 = or(_T_1107, _T_1094) node _T_1109 = or(_T_1108, _T_1099) node _T_1110 = or(_T_1109, _T_1104) node _T_1111 = and(_T_1069, _T_1110) node _T_1112 = or(UInt<1>(0h0), _T_1068) node _T_1113 = or(_T_1112, _T_1111) node _T_1114 = and(_T_1058, _T_1113) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_46 node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(source_ok, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(is_aligned, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1124 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_49 node _T_1128 = eq(io.in.a.bits.mask, mask) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_50 node _T_1132 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1136 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_52 node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_33 = shr(io.in.d.bits.source, 2) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE_1 : UInt<1>[7] connect _source_ok_WIRE_1[0], _source_ok_T_32 connect _source_ok_WIRE_1[1], _source_ok_T_38 connect _source_ok_WIRE_1[2], _source_ok_T_44 connect _source_ok_WIRE_1[3], _source_ok_T_50 connect _source_ok_WIRE_1[4], _source_ok_T_56 connect _source_ok_WIRE_1[5], _source_ok_T_57 connect _source_ok_WIRE_1[6], _source_ok_T_58 node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5]) node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1140 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1140 : node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(source_ok_1, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1144 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_54 node _T_1148 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_55 node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_56 node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_57 node _T_1160 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1160 : node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(source_ok_1, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(sink_ok, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1167 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_60 node _T_1171 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_61 node _T_1175 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_62 node _T_1179 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_63 node _T_1183 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1184 = or(UInt<1>(0h1), _T_1183) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_64 node _T_1188 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1188 : node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(source_ok_1, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(sink_ok, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1195 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_67 node _T_1199 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_68 node _T_1203 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_69 node _T_1207 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1208 = or(_T_1207, io.in.d.bits.corrupt) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_70 node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1213 = or(UInt<1>(0h1), _T_1212) node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(_T_1213, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1213, UInt<1>(0h1), "") : assert_71 node _T_1217 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1217 : node _T_1218 = asUInt(reset) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) when _T_1219 : node _T_1220 = eq(source_ok_1, UInt<1>(0h0)) when _T_1220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1221 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_73 node _T_1225 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_74 node _T_1229 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1230 = or(UInt<1>(0h1), _T_1229) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_75 node _T_1234 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1234 : node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(source_ok_1, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1238 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_77 node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1243 = or(_T_1242, io.in.d.bits.corrupt) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_78 node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1248 = or(UInt<1>(0h1), _T_1247) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_79 node _T_1252 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1252 : node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(source_ok_1, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1256 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_81 node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_82 node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1265 = or(UInt<1>(0h1), _T_1264) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1269 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1273 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1277 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(_T_1277, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1277, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1281 = eq(a_first, UInt<1>(0h0)) node _T_1282 = and(io.in.a.valid, _T_1281) when _T_1282 : node _T_1283 = eq(io.in.a.bits.opcode, opcode) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_87 node _T_1287 = eq(io.in.a.bits.param, param) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_88 node _T_1291 = eq(io.in.a.bits.size, size) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_89 node _T_1295 = eq(io.in.a.bits.source, source) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_90 node _T_1299 = eq(io.in.a.bits.address, address) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_91 node _T_1303 = and(io.in.a.ready, io.in.a.valid) node _T_1304 = and(_T_1303, a_first) when _T_1304 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1305 = eq(d_first, UInt<1>(0h0)) node _T_1306 = and(io.in.d.valid, _T_1305) when _T_1306 : node _T_1307 = eq(io.in.d.bits.opcode, opcode_1) node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(_T_1307, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1307, UInt<1>(0h1), "") : assert_92 node _T_1311 = eq(io.in.d.bits.param, param_1) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_93 node _T_1315 = eq(io.in.d.bits.size, size_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_94 node _T_1319 = eq(io.in.d.bits.source, source_1) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_95 node _T_1323 = eq(io.in.d.bits.sink, sink) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_96 node _T_1327 = eq(io.in.d.bits.denied, denied) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_97 node _T_1331 = and(io.in.d.ready, io.in.d.valid) node _T_1332 = and(_T_1331, d_first) when _T_1332 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<34>, clock, reset, UInt<34>(0h0) regreset inflight_opcodes : UInt<136>, clock, reset, UInt<136>(0h0) regreset inflight_sizes : UInt<272>, clock, reset, UInt<272>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<34> connect a_set, UInt<34>(0h0) wire a_set_wo_ready : UInt<34> connect a_set_wo_ready, UInt<34>(0h0) wire a_opcodes_set : UInt<136> connect a_opcodes_set, UInt<136>(0h0) wire a_sizes_set : UInt<272> connect a_sizes_set, UInt<272>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1333 = and(io.in.a.valid, a_first_1) node _T_1334 = and(_T_1333, UInt<1>(0h1)) when _T_1334 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(_T_1335, a_first_1) node _T_1337 = and(_T_1336, UInt<1>(0h1)) when _T_1337 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1338 = dshr(inflight, io.in.a.bits.source) node _T_1339 = bits(_T_1338, 0, 0) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<34> connect d_clr, UInt<34>(0h0) wire d_clr_wo_ready : UInt<34> connect d_clr_wo_ready, UInt<34>(0h0) wire d_opcodes_clr : UInt<136> connect d_opcodes_clr, UInt<136>(0h0) wire d_sizes_clr : UInt<272> connect d_sizes_clr, UInt<272>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1344 = and(io.in.d.valid, d_first_1) node _T_1345 = and(_T_1344, UInt<1>(0h1)) node _T_1346 = eq(d_release_ack, UInt<1>(0h0)) node _T_1347 = and(_T_1345, _T_1346) when _T_1347 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1348 = and(io.in.d.ready, io.in.d.valid) node _T_1349 = and(_T_1348, d_first_1) node _T_1350 = and(_T_1349, UInt<1>(0h1)) node _T_1351 = eq(d_release_ack, UInt<1>(0h0)) node _T_1352 = and(_T_1350, _T_1351) when _T_1352 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1353 = and(io.in.d.valid, d_first_1) node _T_1354 = and(_T_1353, UInt<1>(0h1)) node _T_1355 = eq(d_release_ack, UInt<1>(0h0)) node _T_1356 = and(_T_1354, _T_1355) when _T_1356 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1357 = dshr(inflight, io.in.d.bits.source) node _T_1358 = bits(_T_1357, 0, 0) node _T_1359 = or(_T_1358, same_cycle_resp) node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(_T_1359, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1359, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1363 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1364 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1365 = or(_T_1363, _T_1364) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_100 node _T_1369 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1370 = asUInt(reset) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) when _T_1371 : node _T_1372 = eq(_T_1369, UInt<1>(0h0)) when _T_1372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1369, UInt<1>(0h1), "") : assert_101 else : node _T_1373 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1374 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1375 = or(_T_1373, _T_1374) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_102 node _T_1379 = eq(io.in.d.bits.size, a_size_lookup) node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(_T_1379, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1379, UInt<1>(0h1), "") : assert_103 node _T_1383 = and(io.in.d.valid, d_first_1) node _T_1384 = and(_T_1383, a_first_1) node _T_1385 = and(_T_1384, io.in.a.valid) node _T_1386 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = eq(d_release_ack, UInt<1>(0h0)) node _T_1389 = and(_T_1387, _T_1388) when _T_1389 : node _T_1390 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1391 = or(_T_1390, io.in.a.ready) node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(_T_1391, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1391, UInt<1>(0h1), "") : assert_104 node _T_1395 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1396 = orr(a_set_wo_ready) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) node _T_1398 = or(_T_1395, _T_1397) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_1402 = orr(inflight) node _T_1403 = eq(_T_1402, UInt<1>(0h0)) node _T_1404 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1405 = or(_T_1403, _T_1404) node _T_1406 = lt(watchdog, plusarg_reader.out) node _T_1407 = or(_T_1405, _T_1406) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1411 = and(io.in.a.ready, io.in.a.valid) node _T_1412 = and(io.in.d.ready, io.in.d.valid) node _T_1413 = or(_T_1411, _T_1412) when _T_1413 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<34>, clock, reset, UInt<34>(0h0) regreset inflight_opcodes_1 : UInt<136>, clock, reset, UInt<136>(0h0) regreset inflight_sizes_1 : UInt<272>, clock, reset, UInt<272>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<34> connect c_set, UInt<34>(0h0) wire c_set_wo_ready : UInt<34> connect c_set_wo_ready, UInt<34>(0h0) wire c_opcodes_set : UInt<136> connect c_opcodes_set, UInt<136>(0h0) wire c_sizes_set : UInt<272> connect c_sizes_set, UInt<272>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1414 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1415 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1416 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1417 = and(_T_1415, _T_1416) node _T_1418 = and(_T_1414, _T_1417) when _T_1418 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1419 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1420 = and(_T_1419, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1421 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1422 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1423 = and(_T_1421, _T_1422) node _T_1424 = and(_T_1420, _T_1423) when _T_1424 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1425 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1426 = bits(_T_1425, 0, 0) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<34> connect d_clr_1, UInt<34>(0h0) wire d_clr_wo_ready_1 : UInt<34> connect d_clr_wo_ready_1, UInt<34>(0h0) wire d_opcodes_clr_1 : UInt<136> connect d_opcodes_clr_1, UInt<136>(0h0) wire d_sizes_clr_1 : UInt<272> connect d_sizes_clr_1, UInt<272>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1431 = and(io.in.d.valid, d_first_2) node _T_1432 = and(_T_1431, UInt<1>(0h1)) node _T_1433 = and(_T_1432, d_release_ack_1) when _T_1433 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1434 = and(io.in.d.ready, io.in.d.valid) node _T_1435 = and(_T_1434, d_first_2) node _T_1436 = and(_T_1435, UInt<1>(0h1)) node _T_1437 = and(_T_1436, d_release_ack_1) when _T_1437 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1438 = and(io.in.d.valid, d_first_2) node _T_1439 = and(_T_1438, UInt<1>(0h1)) node _T_1440 = and(_T_1439, d_release_ack_1) when _T_1440 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1441 = dshr(inflight_1, io.in.d.bits.source) node _T_1442 = bits(_T_1441, 0, 0) node _T_1443 = or(_T_1442, same_cycle_resp_1) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1447 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_109 else : node _T_1451 = eq(io.in.d.bits.size, c_size_lookup) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_110 node _T_1455 = and(io.in.d.valid, d_first_2) node _T_1456 = and(_T_1455, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1457 = and(_T_1456, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1458 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = and(_T_1459, d_release_ack_1) node _T_1461 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1462 = and(_T_1460, _T_1461) when _T_1462 : node _T_1463 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1464 = or(_T_1463, _WIRE_23.ready) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_111 node _T_1468 = orr(c_set_wo_ready) when _T_1468 : node _T_1469 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1473 = orr(inflight_1) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) node _T_1475 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1476 = or(_T_1474, _T_1475) node _T_1477 = lt(watchdog_1, plusarg_reader_1.out) node _T_1478 = or(_T_1476, _T_1477) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1482 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1483 = and(io.in.d.ready, io.in.d.valid) node _T_1484 = or(_T_1482, _T_1483) when _T_1484 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14] wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27] wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25] wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28] wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [271:0] c_sizes_set = 272'h0; // @[Monitor.scala:741:34] wire [135:0] c_opcodes_set = 136'h0; // @[Monitor.scala:740:34] wire [33:0] c_set = 34'h0; // @[Monitor.scala:738:34] wire [33:0] c_set_wo_ready = 34'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = |(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_33 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_39 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_46 = _source_ok_T_45 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = _source_ok_T_51 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire _source_ok_T_57 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire _source_ok_T_58 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _T_1411 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1411; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1411; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1484; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1484; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1484; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [33:0] inflight; // @[Monitor.scala:614:27] reg [135:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [271:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [33:0] a_set; // @[Monitor.scala:626:34] wire [33:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [135:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [271:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [135:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [135:0] _a_opcode_lookup_T_6 = {132'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [135:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [271:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [271:0] _a_size_lookup_T_6 = {264'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [271:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[271:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1337 = _T_1411 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1337 ? _a_set_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1337 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1337 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1337 ? _a_opcodes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1337 ? _a_sizes_set_T_1[271:0] : 272'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [33:0] d_clr; // @[Monitor.scala:664:34] wire [33:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [135:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [271:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1383 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1383 & ~d_release_ack ? _d_clr_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1352 = _T_1484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1352 ? _d_clr_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1352 ? _d_opcodes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1352 ? _d_sizes_clr_T_5[271:0] : 272'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [33:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [33:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [33:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [135:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [135:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [135:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [271:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [271:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [271:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [33:0] inflight_1; // @[Monitor.scala:726:35] wire [33:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [135:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [135:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [271:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [271:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_2; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [135:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [135:0] _c_opcode_lookup_T_6 = {132'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [135:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [271:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [271:0] _c_size_lookup_T_6 = {264'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [271:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[271:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [33:0] d_clr_1; // @[Monitor.scala:774:34] wire [33:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [135:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [271:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1455 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1455 & d_release_ack_1 ? _d_clr_wo_ready_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1437 = _T_1484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1437 ? _d_clr_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1437 ? _d_opcodes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1437 ? _d_sizes_clr_T_11[271:0] : 272'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [33:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [33:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [135:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [135:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [271:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [271:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_43 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_43( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_4 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_4 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_4 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_4 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d

module TLMasterACDToNoC_4( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_4 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_4 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_8 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_8 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_8 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_17 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulAddRecFN_e8_s24_8( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_8 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_8 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_17 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_111 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_112 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x2 : output auto : { flip in : { sync : UInt<1>[2]}, out : UInt<1>[2]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[2]} invalidate nodeIn.sync[0] invalidate nodeIn.sync[1] wire nodeOut : UInt<1>[2] invalidate nodeOut[0] invalidate nodeOut[1] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync

module IntSyncSyncCrossingSink_n1x2( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BoomLSUShim_1 : input clock : Clock input reset : Reset output io : { flip lsu : { exe : { flip req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<34>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}}[1], flip dis_uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[1], dis_ldq_idx : UInt<4>[1], dis_stq_idx : UInt<4>[1], ldq_full : UInt<1>[1], stq_full : UInt<1>[1], flip fp_stdata : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, flip commit : { valids : UInt<1>[1], arch_valids : UInt<1>[1], uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[1], rbk_valids : UInt<1>[1], rollback : UInt<1>, debug_wdata : UInt<64>[1]}, flip commit_load_at_rob_head : UInt<1>, clr_bsy : { valid : UInt<1>, bits : UInt<6>}[2], clr_unsafe : { valid : UInt<1>, bits : UInt<6>}[1], flip fence_dmem : UInt<1>, spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], ld_miss : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip exception : UInt<1>, fencei_rdy : UInt<1>, lxcpt : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<34>}}, flip tsc_reg : UInt, perf : { acquire : UInt<1>, release : UInt<1>, tlbMiss : UInt<1>}}, flip tracegen : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<6>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<6>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} invalidate io.tracegen.clock_enabled invalidate io.tracegen.keep_clock_enabled invalidate io.tracegen.perf.storeBufferEmptyAfterStore invalidate io.tracegen.perf.storeBufferEmptyAfterLoad invalidate io.tracegen.perf.canAcceptLoadThenLoad invalidate io.tracegen.perf.canAcceptStoreThenRMW invalidate io.tracegen.perf.canAcceptStoreThenLoad invalidate io.tracegen.perf.blocked invalidate io.tracegen.perf.tlbMiss invalidate io.tracegen.perf.grant invalidate io.tracegen.perf.release invalidate io.tracegen.perf.acquire invalidate io.tracegen.store_pending invalidate io.tracegen.ordered invalidate io.tracegen.s2_gpa_is_pte invalidate io.tracegen.s2_gpa invalidate io.tracegen.s2_xcpt.ae.st invalidate io.tracegen.s2_xcpt.ae.ld invalidate io.tracegen.s2_xcpt.gf.st invalidate io.tracegen.s2_xcpt.gf.ld invalidate io.tracegen.s2_xcpt.pf.st invalidate io.tracegen.s2_xcpt.pf.ld invalidate io.tracegen.s2_xcpt.ma.st invalidate io.tracegen.s2_xcpt.ma.ld invalidate io.tracegen.replay_next invalidate io.tracegen.resp.bits.store_data invalidate io.tracegen.resp.bits.data_raw invalidate io.tracegen.resp.bits.data_word_bypass invalidate io.tracegen.resp.bits.has_data invalidate io.tracegen.resp.bits.replay invalidate io.tracegen.resp.bits.mask invalidate io.tracegen.resp.bits.data invalidate io.tracegen.resp.bits.dv invalidate io.tracegen.resp.bits.dprv invalidate io.tracegen.resp.bits.signed invalidate io.tracegen.resp.bits.size invalidate io.tracegen.resp.bits.cmd invalidate io.tracegen.resp.bits.tag invalidate io.tracegen.resp.bits.addr invalidate io.tracegen.resp.valid invalidate io.tracegen.s2_paddr invalidate io.tracegen.s2_uncached invalidate io.tracegen.s2_kill invalidate io.tracegen.s2_nack_cause_raw invalidate io.tracegen.s2_nack invalidate io.tracegen.s1_data.mask invalidate io.tracegen.s1_data.data invalidate io.tracegen.s1_kill invalidate io.tracegen.req.bits.mask invalidate io.tracegen.req.bits.data invalidate io.tracegen.req.bits.no_xcpt invalidate io.tracegen.req.bits.no_alloc invalidate io.tracegen.req.bits.no_resp invalidate io.tracegen.req.bits.phys invalidate io.tracegen.req.bits.dv invalidate io.tracegen.req.bits.dprv invalidate io.tracegen.req.bits.signed invalidate io.tracegen.req.bits.size invalidate io.tracegen.req.bits.cmd invalidate io.tracegen.req.bits.tag invalidate io.tracegen.req.bits.addr invalidate io.tracegen.req.valid invalidate io.tracegen.req.ready invalidate io.lsu.perf.tlbMiss invalidate io.lsu.perf.release invalidate io.lsu.perf.acquire invalidate io.lsu.tsc_reg invalidate io.lsu.lxcpt.bits.badvaddr invalidate io.lsu.lxcpt.bits.cause invalidate io.lsu.lxcpt.bits.uop.debug_tsrc invalidate io.lsu.lxcpt.bits.uop.debug_fsrc invalidate io.lsu.lxcpt.bits.uop.bp_xcpt_if invalidate io.lsu.lxcpt.bits.uop.bp_debug_if invalidate io.lsu.lxcpt.bits.uop.xcpt_ma_if invalidate io.lsu.lxcpt.bits.uop.xcpt_ae_if invalidate io.lsu.lxcpt.bits.uop.xcpt_pf_if invalidate io.lsu.lxcpt.bits.uop.fp_single invalidate io.lsu.lxcpt.bits.uop.fp_val invalidate io.lsu.lxcpt.bits.uop.frs3_en invalidate io.lsu.lxcpt.bits.uop.lrs2_rtype invalidate io.lsu.lxcpt.bits.uop.lrs1_rtype invalidate io.lsu.lxcpt.bits.uop.dst_rtype invalidate io.lsu.lxcpt.bits.uop.ldst_val invalidate io.lsu.lxcpt.bits.uop.lrs3 invalidate io.lsu.lxcpt.bits.uop.lrs2 invalidate io.lsu.lxcpt.bits.uop.lrs1 invalidate io.lsu.lxcpt.bits.uop.ldst invalidate io.lsu.lxcpt.bits.uop.ldst_is_rs1 invalidate io.lsu.lxcpt.bits.uop.flush_on_commit invalidate io.lsu.lxcpt.bits.uop.is_unique invalidate io.lsu.lxcpt.bits.uop.is_sys_pc2epc invalidate io.lsu.lxcpt.bits.uop.uses_stq invalidate io.lsu.lxcpt.bits.uop.uses_ldq invalidate io.lsu.lxcpt.bits.uop.is_amo invalidate io.lsu.lxcpt.bits.uop.is_fencei invalidate io.lsu.lxcpt.bits.uop.is_fence invalidate io.lsu.lxcpt.bits.uop.mem_signed invalidate io.lsu.lxcpt.bits.uop.mem_size invalidate io.lsu.lxcpt.bits.uop.mem_cmd invalidate io.lsu.lxcpt.bits.uop.bypassable invalidate io.lsu.lxcpt.bits.uop.exc_cause invalidate io.lsu.lxcpt.bits.uop.exception invalidate io.lsu.lxcpt.bits.uop.stale_pdst invalidate io.lsu.lxcpt.bits.uop.ppred_busy invalidate io.lsu.lxcpt.bits.uop.prs3_busy invalidate io.lsu.lxcpt.bits.uop.prs2_busy invalidate io.lsu.lxcpt.bits.uop.prs1_busy invalidate io.lsu.lxcpt.bits.uop.ppred invalidate io.lsu.lxcpt.bits.uop.prs3 invalidate io.lsu.lxcpt.bits.uop.prs2 invalidate io.lsu.lxcpt.bits.uop.prs1 invalidate io.lsu.lxcpt.bits.uop.pdst invalidate io.lsu.lxcpt.bits.uop.rxq_idx invalidate io.lsu.lxcpt.bits.uop.stq_idx invalidate io.lsu.lxcpt.bits.uop.ldq_idx invalidate io.lsu.lxcpt.bits.uop.rob_idx invalidate io.lsu.lxcpt.bits.uop.csr_addr invalidate io.lsu.lxcpt.bits.uop.imm_packed invalidate io.lsu.lxcpt.bits.uop.taken invalidate io.lsu.lxcpt.bits.uop.pc_lob invalidate io.lsu.lxcpt.bits.uop.edge_inst invalidate io.lsu.lxcpt.bits.uop.ftq_idx invalidate io.lsu.lxcpt.bits.uop.br_tag invalidate io.lsu.lxcpt.bits.uop.br_mask invalidate io.lsu.lxcpt.bits.uop.is_sfb invalidate io.lsu.lxcpt.bits.uop.is_jal invalidate io.lsu.lxcpt.bits.uop.is_jalr invalidate io.lsu.lxcpt.bits.uop.is_br invalidate io.lsu.lxcpt.bits.uop.iw_p2_poisoned invalidate io.lsu.lxcpt.bits.uop.iw_p1_poisoned invalidate io.lsu.lxcpt.bits.uop.iw_state invalidate io.lsu.lxcpt.bits.uop.ctrl.is_std invalidate io.lsu.lxcpt.bits.uop.ctrl.is_sta invalidate io.lsu.lxcpt.bits.uop.ctrl.is_load invalidate io.lsu.lxcpt.bits.uop.ctrl.csr_cmd invalidate io.lsu.lxcpt.bits.uop.ctrl.fcn_dw invalidate io.lsu.lxcpt.bits.uop.ctrl.op_fcn invalidate io.lsu.lxcpt.bits.uop.ctrl.imm_sel invalidate io.lsu.lxcpt.bits.uop.ctrl.op2_sel invalidate io.lsu.lxcpt.bits.uop.ctrl.op1_sel invalidate io.lsu.lxcpt.bits.uop.ctrl.br_type invalidate io.lsu.lxcpt.bits.uop.fu_code invalidate io.lsu.lxcpt.bits.uop.iq_type invalidate io.lsu.lxcpt.bits.uop.debug_pc invalidate io.lsu.lxcpt.bits.uop.is_rvc invalidate io.lsu.lxcpt.bits.uop.debug_inst invalidate io.lsu.lxcpt.bits.uop.inst invalidate io.lsu.lxcpt.bits.uop.uopc invalidate io.lsu.lxcpt.valid invalidate io.lsu.fencei_rdy invalidate io.lsu.exception invalidate io.lsu.rob_head_idx invalidate io.lsu.rob_pnr_idx invalidate io.lsu.brupdate.b2.target_offset invalidate io.lsu.brupdate.b2.jalr_target invalidate io.lsu.brupdate.b2.pc_sel invalidate io.lsu.brupdate.b2.cfi_type invalidate io.lsu.brupdate.b2.taken invalidate io.lsu.brupdate.b2.mispredict invalidate io.lsu.brupdate.b2.valid invalidate io.lsu.brupdate.b2.uop.debug_tsrc invalidate io.lsu.brupdate.b2.uop.debug_fsrc invalidate io.lsu.brupdate.b2.uop.bp_xcpt_if invalidate io.lsu.brupdate.b2.uop.bp_debug_if invalidate io.lsu.brupdate.b2.uop.xcpt_ma_if invalidate io.lsu.brupdate.b2.uop.xcpt_ae_if invalidate io.lsu.brupdate.b2.uop.xcpt_pf_if invalidate io.lsu.brupdate.b2.uop.fp_single invalidate io.lsu.brupdate.b2.uop.fp_val invalidate io.lsu.brupdate.b2.uop.frs3_en invalidate io.lsu.brupdate.b2.uop.lrs2_rtype invalidate io.lsu.brupdate.b2.uop.lrs1_rtype invalidate io.lsu.brupdate.b2.uop.dst_rtype invalidate io.lsu.brupdate.b2.uop.ldst_val invalidate io.lsu.brupdate.b2.uop.lrs3 invalidate io.lsu.brupdate.b2.uop.lrs2 invalidate io.lsu.brupdate.b2.uop.lrs1 invalidate io.lsu.brupdate.b2.uop.ldst invalidate io.lsu.brupdate.b2.uop.ldst_is_rs1 invalidate io.lsu.brupdate.b2.uop.flush_on_commit invalidate io.lsu.brupdate.b2.uop.is_unique invalidate io.lsu.brupdate.b2.uop.is_sys_pc2epc invalidate io.lsu.brupdate.b2.uop.uses_stq invalidate io.lsu.brupdate.b2.uop.uses_ldq invalidate io.lsu.brupdate.b2.uop.is_amo invalidate io.lsu.brupdate.b2.uop.is_fencei invalidate io.lsu.brupdate.b2.uop.is_fence invalidate io.lsu.brupdate.b2.uop.mem_signed invalidate io.lsu.brupdate.b2.uop.mem_size invalidate io.lsu.brupdate.b2.uop.mem_cmd invalidate io.lsu.brupdate.b2.uop.bypassable invalidate io.lsu.brupdate.b2.uop.exc_cause invalidate io.lsu.brupdate.b2.uop.exception invalidate io.lsu.brupdate.b2.uop.stale_pdst invalidate io.lsu.brupdate.b2.uop.ppred_busy invalidate io.lsu.brupdate.b2.uop.prs3_busy invalidate io.lsu.brupdate.b2.uop.prs2_busy invalidate io.lsu.brupdate.b2.uop.prs1_busy invalidate io.lsu.brupdate.b2.uop.ppred invalidate io.lsu.brupdate.b2.uop.prs3 invalidate io.lsu.brupdate.b2.uop.prs2 invalidate io.lsu.brupdate.b2.uop.prs1 invalidate io.lsu.brupdate.b2.uop.pdst invalidate io.lsu.brupdate.b2.uop.rxq_idx invalidate io.lsu.brupdate.b2.uop.stq_idx invalidate io.lsu.brupdate.b2.uop.ldq_idx invalidate io.lsu.brupdate.b2.uop.rob_idx invalidate io.lsu.brupdate.b2.uop.csr_addr invalidate io.lsu.brupdate.b2.uop.imm_packed invalidate io.lsu.brupdate.b2.uop.taken invalidate io.lsu.brupdate.b2.uop.pc_lob invalidate io.lsu.brupdate.b2.uop.edge_inst invalidate io.lsu.brupdate.b2.uop.ftq_idx invalidate io.lsu.brupdate.b2.uop.br_tag invalidate io.lsu.brupdate.b2.uop.br_mask invalidate io.lsu.brupdate.b2.uop.is_sfb invalidate io.lsu.brupdate.b2.uop.is_jal invalidate io.lsu.brupdate.b2.uop.is_jalr invalidate io.lsu.brupdate.b2.uop.is_br invalidate io.lsu.brupdate.b2.uop.iw_p2_poisoned invalidate io.lsu.brupdate.b2.uop.iw_p1_poisoned invalidate io.lsu.brupdate.b2.uop.iw_state invalidate io.lsu.brupdate.b2.uop.ctrl.is_std invalidate io.lsu.brupdate.b2.uop.ctrl.is_sta invalidate io.lsu.brupdate.b2.uop.ctrl.is_load invalidate io.lsu.brupdate.b2.uop.ctrl.csr_cmd invalidate io.lsu.brupdate.b2.uop.ctrl.fcn_dw invalidate io.lsu.brupdate.b2.uop.ctrl.op_fcn invalidate io.lsu.brupdate.b2.uop.ctrl.imm_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op2_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op1_sel invalidate io.lsu.brupdate.b2.uop.ctrl.br_type invalidate io.lsu.brupdate.b2.uop.fu_code invalidate io.lsu.brupdate.b2.uop.iq_type invalidate io.lsu.brupdate.b2.uop.debug_pc invalidate io.lsu.brupdate.b2.uop.is_rvc invalidate io.lsu.brupdate.b2.uop.debug_inst invalidate io.lsu.brupdate.b2.uop.inst invalidate io.lsu.brupdate.b2.uop.uopc invalidate io.lsu.brupdate.b1.mispredict_mask invalidate io.lsu.brupdate.b1.resolve_mask invalidate io.lsu.ld_miss invalidate io.lsu.spec_ld_wakeup[0].bits invalidate io.lsu.spec_ld_wakeup[0].valid invalidate io.lsu.fence_dmem invalidate io.lsu.clr_unsafe[0].bits invalidate io.lsu.clr_unsafe[0].valid invalidate io.lsu.clr_bsy[0].bits invalidate io.lsu.clr_bsy[0].valid invalidate io.lsu.clr_bsy[1].bits invalidate io.lsu.clr_bsy[1].valid invalidate io.lsu.commit_load_at_rob_head invalidate io.lsu.commit.debug_wdata[0] invalidate io.lsu.commit.rollback invalidate io.lsu.commit.rbk_valids[0] invalidate io.lsu.commit.debug_insts[0] invalidate io.lsu.commit.fflags.bits invalidate io.lsu.commit.fflags.valid invalidate io.lsu.commit.uops[0].debug_tsrc invalidate io.lsu.commit.uops[0].debug_fsrc invalidate io.lsu.commit.uops[0].bp_xcpt_if invalidate io.lsu.commit.uops[0].bp_debug_if invalidate io.lsu.commit.uops[0].xcpt_ma_if invalidate io.lsu.commit.uops[0].xcpt_ae_if invalidate io.lsu.commit.uops[0].xcpt_pf_if invalidate io.lsu.commit.uops[0].fp_single invalidate io.lsu.commit.uops[0].fp_val invalidate io.lsu.commit.uops[0].frs3_en invalidate io.lsu.commit.uops[0].lrs2_rtype invalidate io.lsu.commit.uops[0].lrs1_rtype invalidate io.lsu.commit.uops[0].dst_rtype invalidate io.lsu.commit.uops[0].ldst_val invalidate io.lsu.commit.uops[0].lrs3 invalidate io.lsu.commit.uops[0].lrs2 invalidate io.lsu.commit.uops[0].lrs1 invalidate io.lsu.commit.uops[0].ldst invalidate io.lsu.commit.uops[0].ldst_is_rs1 invalidate io.lsu.commit.uops[0].flush_on_commit invalidate io.lsu.commit.uops[0].is_unique invalidate io.lsu.commit.uops[0].is_sys_pc2epc invalidate io.lsu.commit.uops[0].uses_stq invalidate io.lsu.commit.uops[0].uses_ldq invalidate io.lsu.commit.uops[0].is_amo invalidate io.lsu.commit.uops[0].is_fencei invalidate io.lsu.commit.uops[0].is_fence invalidate io.lsu.commit.uops[0].mem_signed invalidate io.lsu.commit.uops[0].mem_size invalidate io.lsu.commit.uops[0].mem_cmd invalidate io.lsu.commit.uops[0].bypassable invalidate io.lsu.commit.uops[0].exc_cause invalidate io.lsu.commit.uops[0].exception invalidate io.lsu.commit.uops[0].stale_pdst invalidate io.lsu.commit.uops[0].ppred_busy invalidate io.lsu.commit.uops[0].prs3_busy invalidate io.lsu.commit.uops[0].prs2_busy invalidate io.lsu.commit.uops[0].prs1_busy invalidate io.lsu.commit.uops[0].ppred invalidate io.lsu.commit.uops[0].prs3 invalidate io.lsu.commit.uops[0].prs2 invalidate io.lsu.commit.uops[0].prs1 invalidate io.lsu.commit.uops[0].pdst invalidate io.lsu.commit.uops[0].rxq_idx invalidate io.lsu.commit.uops[0].stq_idx invalidate io.lsu.commit.uops[0].ldq_idx invalidate io.lsu.commit.uops[0].rob_idx invalidate io.lsu.commit.uops[0].csr_addr invalidate io.lsu.commit.uops[0].imm_packed invalidate io.lsu.commit.uops[0].taken invalidate io.lsu.commit.uops[0].pc_lob invalidate io.lsu.commit.uops[0].edge_inst invalidate io.lsu.commit.uops[0].ftq_idx invalidate io.lsu.commit.uops[0].br_tag invalidate io.lsu.commit.uops[0].br_mask invalidate io.lsu.commit.uops[0].is_sfb invalidate io.lsu.commit.uops[0].is_jal invalidate io.lsu.commit.uops[0].is_jalr invalidate io.lsu.commit.uops[0].is_br invalidate io.lsu.commit.uops[0].iw_p2_poisoned invalidate io.lsu.commit.uops[0].iw_p1_poisoned invalidate io.lsu.commit.uops[0].iw_state invalidate io.lsu.commit.uops[0].ctrl.is_std invalidate io.lsu.commit.uops[0].ctrl.is_sta invalidate io.lsu.commit.uops[0].ctrl.is_load invalidate io.lsu.commit.uops[0].ctrl.csr_cmd invalidate io.lsu.commit.uops[0].ctrl.fcn_dw invalidate io.lsu.commit.uops[0].ctrl.op_fcn invalidate io.lsu.commit.uops[0].ctrl.imm_sel invalidate io.lsu.commit.uops[0].ctrl.op2_sel invalidate io.lsu.commit.uops[0].ctrl.op1_sel invalidate io.lsu.commit.uops[0].ctrl.br_type invalidate io.lsu.commit.uops[0].fu_code invalidate io.lsu.commit.uops[0].iq_type invalidate io.lsu.commit.uops[0].debug_pc invalidate io.lsu.commit.uops[0].is_rvc invalidate io.lsu.commit.uops[0].debug_inst invalidate io.lsu.commit.uops[0].inst invalidate io.lsu.commit.uops[0].uopc invalidate io.lsu.commit.arch_valids[0] invalidate io.lsu.commit.valids[0] invalidate io.lsu.fp_stdata.bits.fflags.bits.flags invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exception invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.taken invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uopc invalidate io.lsu.fp_stdata.bits.fflags.valid invalidate io.lsu.fp_stdata.bits.predicated invalidate io.lsu.fp_stdata.bits.data invalidate io.lsu.fp_stdata.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.uop.exception invalidate io.lsu.fp_stdata.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.uop.taken invalidate io.lsu.fp_stdata.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.uop.inst invalidate io.lsu.fp_stdata.bits.uop.uopc invalidate io.lsu.fp_stdata.valid invalidate io.lsu.fp_stdata.ready invalidate io.lsu.stq_full[0] invalidate io.lsu.ldq_full[0] invalidate io.lsu.dis_stq_idx[0] invalidate io.lsu.dis_ldq_idx[0] invalidate io.lsu.dis_uops[0].bits.debug_tsrc invalidate io.lsu.dis_uops[0].bits.debug_fsrc invalidate io.lsu.dis_uops[0].bits.bp_xcpt_if invalidate io.lsu.dis_uops[0].bits.bp_debug_if invalidate io.lsu.dis_uops[0].bits.xcpt_ma_if invalidate io.lsu.dis_uops[0].bits.xcpt_ae_if invalidate io.lsu.dis_uops[0].bits.xcpt_pf_if invalidate io.lsu.dis_uops[0].bits.fp_single invalidate io.lsu.dis_uops[0].bits.fp_val invalidate io.lsu.dis_uops[0].bits.frs3_en invalidate io.lsu.dis_uops[0].bits.lrs2_rtype invalidate io.lsu.dis_uops[0].bits.lrs1_rtype invalidate io.lsu.dis_uops[0].bits.dst_rtype invalidate io.lsu.dis_uops[0].bits.ldst_val invalidate io.lsu.dis_uops[0].bits.lrs3 invalidate io.lsu.dis_uops[0].bits.lrs2 invalidate io.lsu.dis_uops[0].bits.lrs1 invalidate io.lsu.dis_uops[0].bits.ldst invalidate io.lsu.dis_uops[0].bits.ldst_is_rs1 invalidate io.lsu.dis_uops[0].bits.flush_on_commit invalidate io.lsu.dis_uops[0].bits.is_unique invalidate io.lsu.dis_uops[0].bits.is_sys_pc2epc invalidate io.lsu.dis_uops[0].bits.uses_stq invalidate io.lsu.dis_uops[0].bits.uses_ldq invalidate io.lsu.dis_uops[0].bits.is_amo invalidate io.lsu.dis_uops[0].bits.is_fencei invalidate io.lsu.dis_uops[0].bits.is_fence invalidate io.lsu.dis_uops[0].bits.mem_signed invalidate io.lsu.dis_uops[0].bits.mem_size invalidate io.lsu.dis_uops[0].bits.mem_cmd invalidate io.lsu.dis_uops[0].bits.bypassable invalidate io.lsu.dis_uops[0].bits.exc_cause invalidate io.lsu.dis_uops[0].bits.exception invalidate io.lsu.dis_uops[0].bits.stale_pdst invalidate io.lsu.dis_uops[0].bits.ppred_busy invalidate io.lsu.dis_uops[0].bits.prs3_busy invalidate io.lsu.dis_uops[0].bits.prs2_busy invalidate io.lsu.dis_uops[0].bits.prs1_busy invalidate io.lsu.dis_uops[0].bits.ppred invalidate io.lsu.dis_uops[0].bits.prs3 invalidate io.lsu.dis_uops[0].bits.prs2 invalidate io.lsu.dis_uops[0].bits.prs1 invalidate io.lsu.dis_uops[0].bits.pdst invalidate io.lsu.dis_uops[0].bits.rxq_idx invalidate io.lsu.dis_uops[0].bits.stq_idx invalidate io.lsu.dis_uops[0].bits.ldq_idx invalidate io.lsu.dis_uops[0].bits.rob_idx invalidate io.lsu.dis_uops[0].bits.csr_addr invalidate io.lsu.dis_uops[0].bits.imm_packed invalidate io.lsu.dis_uops[0].bits.taken invalidate io.lsu.dis_uops[0].bits.pc_lob invalidate io.lsu.dis_uops[0].bits.edge_inst invalidate io.lsu.dis_uops[0].bits.ftq_idx invalidate io.lsu.dis_uops[0].bits.br_tag invalidate io.lsu.dis_uops[0].bits.br_mask invalidate io.lsu.dis_uops[0].bits.is_sfb invalidate io.lsu.dis_uops[0].bits.is_jal invalidate io.lsu.dis_uops[0].bits.is_jalr invalidate io.lsu.dis_uops[0].bits.is_br invalidate io.lsu.dis_uops[0].bits.iw_p2_poisoned invalidate io.lsu.dis_uops[0].bits.iw_p1_poisoned invalidate io.lsu.dis_uops[0].bits.iw_state invalidate io.lsu.dis_uops[0].bits.ctrl.is_std invalidate io.lsu.dis_uops[0].bits.ctrl.is_sta invalidate io.lsu.dis_uops[0].bits.ctrl.is_load invalidate io.lsu.dis_uops[0].bits.ctrl.csr_cmd invalidate io.lsu.dis_uops[0].bits.ctrl.fcn_dw invalidate io.lsu.dis_uops[0].bits.ctrl.op_fcn invalidate io.lsu.dis_uops[0].bits.ctrl.imm_sel invalidate io.lsu.dis_uops[0].bits.ctrl.op2_sel invalidate io.lsu.dis_uops[0].bits.ctrl.op1_sel invalidate io.lsu.dis_uops[0].bits.ctrl.br_type invalidate io.lsu.dis_uops[0].bits.fu_code invalidate io.lsu.dis_uops[0].bits.iq_type invalidate io.lsu.dis_uops[0].bits.debug_pc invalidate io.lsu.dis_uops[0].bits.is_rvc invalidate io.lsu.dis_uops[0].bits.debug_inst invalidate io.lsu.dis_uops[0].bits.inst invalidate io.lsu.dis_uops[0].bits.uopc invalidate io.lsu.dis_uops[0].valid invalidate io.lsu.exe[0].fresp.bits.fflags.bits.flags invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].fresp.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].fresp.bits.fflags.valid invalidate io.lsu.exe[0].fresp.bits.predicated invalidate io.lsu.exe[0].fresp.bits.data invalidate io.lsu.exe[0].fresp.bits.uop.debug_tsrc invalidate io.lsu.exe[0].fresp.bits.uop.debug_fsrc invalidate io.lsu.exe[0].fresp.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].fresp.bits.uop.bp_debug_if invalidate io.lsu.exe[0].fresp.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].fresp.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].fresp.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].fresp.bits.uop.fp_single invalidate io.lsu.exe[0].fresp.bits.uop.fp_val invalidate io.lsu.exe[0].fresp.bits.uop.frs3_en invalidate io.lsu.exe[0].fresp.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].fresp.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].fresp.bits.uop.dst_rtype invalidate io.lsu.exe[0].fresp.bits.uop.ldst_val invalidate io.lsu.exe[0].fresp.bits.uop.lrs3 invalidate io.lsu.exe[0].fresp.bits.uop.lrs2 invalidate io.lsu.exe[0].fresp.bits.uop.lrs1 invalidate io.lsu.exe[0].fresp.bits.uop.ldst invalidate io.lsu.exe[0].fresp.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].fresp.bits.uop.flush_on_commit invalidate io.lsu.exe[0].fresp.bits.uop.is_unique invalidate io.lsu.exe[0].fresp.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].fresp.bits.uop.uses_stq invalidate io.lsu.exe[0].fresp.bits.uop.uses_ldq invalidate io.lsu.exe[0].fresp.bits.uop.is_amo invalidate io.lsu.exe[0].fresp.bits.uop.is_fencei invalidate io.lsu.exe[0].fresp.bits.uop.is_fence invalidate io.lsu.exe[0].fresp.bits.uop.mem_signed invalidate io.lsu.exe[0].fresp.bits.uop.mem_size invalidate io.lsu.exe[0].fresp.bits.uop.mem_cmd invalidate io.lsu.exe[0].fresp.bits.uop.bypassable invalidate io.lsu.exe[0].fresp.bits.uop.exc_cause invalidate io.lsu.exe[0].fresp.bits.uop.exception invalidate io.lsu.exe[0].fresp.bits.uop.stale_pdst invalidate io.lsu.exe[0].fresp.bits.uop.ppred_busy invalidate io.lsu.exe[0].fresp.bits.uop.prs3_busy invalidate io.lsu.exe[0].fresp.bits.uop.prs2_busy invalidate io.lsu.exe[0].fresp.bits.uop.prs1_busy invalidate io.lsu.exe[0].fresp.bits.uop.ppred invalidate io.lsu.exe[0].fresp.bits.uop.prs3 invalidate io.lsu.exe[0].fresp.bits.uop.prs2 invalidate io.lsu.exe[0].fresp.bits.uop.prs1 invalidate io.lsu.exe[0].fresp.bits.uop.pdst invalidate io.lsu.exe[0].fresp.bits.uop.rxq_idx invalidate io.lsu.exe[0].fresp.bits.uop.stq_idx invalidate io.lsu.exe[0].fresp.bits.uop.ldq_idx invalidate io.lsu.exe[0].fresp.bits.uop.rob_idx invalidate io.lsu.exe[0].fresp.bits.uop.csr_addr invalidate io.lsu.exe[0].fresp.bits.uop.imm_packed invalidate io.lsu.exe[0].fresp.bits.uop.taken invalidate io.lsu.exe[0].fresp.bits.uop.pc_lob invalidate io.lsu.exe[0].fresp.bits.uop.edge_inst invalidate io.lsu.exe[0].fresp.bits.uop.ftq_idx invalidate io.lsu.exe[0].fresp.bits.uop.br_tag invalidate io.lsu.exe[0].fresp.bits.uop.br_mask invalidate io.lsu.exe[0].fresp.bits.uop.is_sfb invalidate io.lsu.exe[0].fresp.bits.uop.is_jal invalidate io.lsu.exe[0].fresp.bits.uop.is_jalr invalidate io.lsu.exe[0].fresp.bits.uop.is_br invalidate io.lsu.exe[0].fresp.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].fresp.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].fresp.bits.uop.iw_state invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].fresp.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].fresp.bits.uop.fu_code invalidate io.lsu.exe[0].fresp.bits.uop.iq_type invalidate io.lsu.exe[0].fresp.bits.uop.debug_pc invalidate io.lsu.exe[0].fresp.bits.uop.is_rvc invalidate io.lsu.exe[0].fresp.bits.uop.debug_inst invalidate io.lsu.exe[0].fresp.bits.uop.inst invalidate io.lsu.exe[0].fresp.bits.uop.uopc invalidate io.lsu.exe[0].fresp.valid invalidate io.lsu.exe[0].fresp.ready invalidate io.lsu.exe[0].iresp.bits.fflags.bits.flags invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].iresp.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].iresp.bits.fflags.valid invalidate io.lsu.exe[0].iresp.bits.predicated invalidate io.lsu.exe[0].iresp.bits.data invalidate io.lsu.exe[0].iresp.bits.uop.debug_tsrc invalidate io.lsu.exe[0].iresp.bits.uop.debug_fsrc invalidate io.lsu.exe[0].iresp.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].iresp.bits.uop.bp_debug_if invalidate io.lsu.exe[0].iresp.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].iresp.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].iresp.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].iresp.bits.uop.fp_single invalidate io.lsu.exe[0].iresp.bits.uop.fp_val invalidate io.lsu.exe[0].iresp.bits.uop.frs3_en invalidate io.lsu.exe[0].iresp.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].iresp.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].iresp.bits.uop.dst_rtype invalidate io.lsu.exe[0].iresp.bits.uop.ldst_val invalidate io.lsu.exe[0].iresp.bits.uop.lrs3 invalidate io.lsu.exe[0].iresp.bits.uop.lrs2 invalidate io.lsu.exe[0].iresp.bits.uop.lrs1 invalidate io.lsu.exe[0].iresp.bits.uop.ldst invalidate io.lsu.exe[0].iresp.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].iresp.bits.uop.flush_on_commit invalidate io.lsu.exe[0].iresp.bits.uop.is_unique invalidate io.lsu.exe[0].iresp.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].iresp.bits.uop.uses_stq invalidate io.lsu.exe[0].iresp.bits.uop.uses_ldq invalidate io.lsu.exe[0].iresp.bits.uop.is_amo invalidate io.lsu.exe[0].iresp.bits.uop.is_fencei invalidate io.lsu.exe[0].iresp.bits.uop.is_fence invalidate io.lsu.exe[0].iresp.bits.uop.mem_signed invalidate io.lsu.exe[0].iresp.bits.uop.mem_size invalidate io.lsu.exe[0].iresp.bits.uop.mem_cmd invalidate io.lsu.exe[0].iresp.bits.uop.bypassable invalidate io.lsu.exe[0].iresp.bits.uop.exc_cause invalidate io.lsu.exe[0].iresp.bits.uop.exception invalidate io.lsu.exe[0].iresp.bits.uop.stale_pdst invalidate io.lsu.exe[0].iresp.bits.uop.ppred_busy invalidate io.lsu.exe[0].iresp.bits.uop.prs3_busy invalidate io.lsu.exe[0].iresp.bits.uop.prs2_busy invalidate io.lsu.exe[0].iresp.bits.uop.prs1_busy invalidate io.lsu.exe[0].iresp.bits.uop.ppred invalidate io.lsu.exe[0].iresp.bits.uop.prs3 invalidate io.lsu.exe[0].iresp.bits.uop.prs2 invalidate io.lsu.exe[0].iresp.bits.uop.prs1 invalidate io.lsu.exe[0].iresp.bits.uop.pdst invalidate io.lsu.exe[0].iresp.bits.uop.rxq_idx invalidate io.lsu.exe[0].iresp.bits.uop.stq_idx invalidate io.lsu.exe[0].iresp.bits.uop.ldq_idx invalidate io.lsu.exe[0].iresp.bits.uop.rob_idx invalidate io.lsu.exe[0].iresp.bits.uop.csr_addr invalidate io.lsu.exe[0].iresp.bits.uop.imm_packed invalidate io.lsu.exe[0].iresp.bits.uop.taken invalidate io.lsu.exe[0].iresp.bits.uop.pc_lob invalidate io.lsu.exe[0].iresp.bits.uop.edge_inst invalidate io.lsu.exe[0].iresp.bits.uop.ftq_idx invalidate io.lsu.exe[0].iresp.bits.uop.br_tag invalidate io.lsu.exe[0].iresp.bits.uop.br_mask invalidate io.lsu.exe[0].iresp.bits.uop.is_sfb invalidate io.lsu.exe[0].iresp.bits.uop.is_jal invalidate io.lsu.exe[0].iresp.bits.uop.is_jalr invalidate io.lsu.exe[0].iresp.bits.uop.is_br invalidate io.lsu.exe[0].iresp.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].iresp.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].iresp.bits.uop.iw_state invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].iresp.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].iresp.bits.uop.fu_code invalidate io.lsu.exe[0].iresp.bits.uop.iq_type invalidate io.lsu.exe[0].iresp.bits.uop.debug_pc invalidate io.lsu.exe[0].iresp.bits.uop.is_rvc invalidate io.lsu.exe[0].iresp.bits.uop.debug_inst invalidate io.lsu.exe[0].iresp.bits.uop.inst invalidate io.lsu.exe[0].iresp.bits.uop.uopc invalidate io.lsu.exe[0].iresp.valid invalidate io.lsu.exe[0].iresp.ready invalidate io.lsu.exe[0].req.bits.sfence.bits.hg invalidate io.lsu.exe[0].req.bits.sfence.bits.hv invalidate io.lsu.exe[0].req.bits.sfence.bits.asid invalidate io.lsu.exe[0].req.bits.sfence.bits.addr invalidate io.lsu.exe[0].req.bits.sfence.bits.rs2 invalidate io.lsu.exe[0].req.bits.sfence.bits.rs1 invalidate io.lsu.exe[0].req.bits.sfence.valid invalidate io.lsu.exe[0].req.bits.mxcpt.bits invalidate io.lsu.exe[0].req.bits.mxcpt.valid invalidate io.lsu.exe[0].req.bits.addr invalidate io.lsu.exe[0].req.bits.fflags.bits.flags invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].req.bits.fflags.valid invalidate io.lsu.exe[0].req.bits.data invalidate io.lsu.exe[0].req.bits.predicated invalidate io.lsu.exe[0].req.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.uop.exception invalidate io.lsu.exe[0].req.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.uop.taken invalidate io.lsu.exe[0].req.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.uop.inst invalidate io.lsu.exe[0].req.bits.uop.uopc invalidate io.lsu.exe[0].req.valid connect io.lsu.tsc_reg, UInt<1>(0h0) reg rob : { addr : UInt<34>, tag : UInt<6>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}[64], clock node _rob_respd_T = not(UInt<64>(0h0)) node _rob_respd_T_1 = bits(_rob_respd_T, 0, 0) node _rob_respd_T_2 = bits(_rob_respd_T, 1, 1) node _rob_respd_T_3 = bits(_rob_respd_T, 2, 2) node _rob_respd_T_4 = bits(_rob_respd_T, 3, 3) node _rob_respd_T_5 = bits(_rob_respd_T, 4, 4) node _rob_respd_T_6 = bits(_rob_respd_T, 5, 5) node _rob_respd_T_7 = bits(_rob_respd_T, 6, 6) node _rob_respd_T_8 = bits(_rob_respd_T, 7, 7) node _rob_respd_T_9 = bits(_rob_respd_T, 8, 8) node _rob_respd_T_10 = bits(_rob_respd_T, 9, 9) node _rob_respd_T_11 = bits(_rob_respd_T, 10, 10) node _rob_respd_T_12 = bits(_rob_respd_T, 11, 11) node _rob_respd_T_13 = bits(_rob_respd_T, 12, 12) node _rob_respd_T_14 = bits(_rob_respd_T, 13, 13) node _rob_respd_T_15 = bits(_rob_respd_T, 14, 14) node _rob_respd_T_16 = bits(_rob_respd_T, 15, 15) node _rob_respd_T_17 = bits(_rob_respd_T, 16, 16) node _rob_respd_T_18 = bits(_rob_respd_T, 17, 17) node _rob_respd_T_19 = bits(_rob_respd_T, 18, 18) node _rob_respd_T_20 = bits(_rob_respd_T, 19, 19) node _rob_respd_T_21 = bits(_rob_respd_T, 20, 20) node _rob_respd_T_22 = bits(_rob_respd_T, 21, 21) node _rob_respd_T_23 = bits(_rob_respd_T, 22, 22) node _rob_respd_T_24 = bits(_rob_respd_T, 23, 23) node _rob_respd_T_25 = bits(_rob_respd_T, 24, 24) node _rob_respd_T_26 = bits(_rob_respd_T, 25, 25) node _rob_respd_T_27 = bits(_rob_respd_T, 26, 26) node _rob_respd_T_28 = bits(_rob_respd_T, 27, 27) node _rob_respd_T_29 = bits(_rob_respd_T, 28, 28) node _rob_respd_T_30 = bits(_rob_respd_T, 29, 29) node _rob_respd_T_31 = bits(_rob_respd_T, 30, 30) node _rob_respd_T_32 = bits(_rob_respd_T, 31, 31) node _rob_respd_T_33 = bits(_rob_respd_T, 32, 32) node _rob_respd_T_34 = bits(_rob_respd_T, 33, 33) node _rob_respd_T_35 = bits(_rob_respd_T, 34, 34) node _rob_respd_T_36 = bits(_rob_respd_T, 35, 35) node _rob_respd_T_37 = bits(_rob_respd_T, 36, 36) node _rob_respd_T_38 = bits(_rob_respd_T, 37, 37) node _rob_respd_T_39 = bits(_rob_respd_T, 38, 38) node _rob_respd_T_40 = bits(_rob_respd_T, 39, 39) node _rob_respd_T_41 = bits(_rob_respd_T, 40, 40) node _rob_respd_T_42 = bits(_rob_respd_T, 41, 41) node _rob_respd_T_43 = bits(_rob_respd_T, 42, 42) node _rob_respd_T_44 = bits(_rob_respd_T, 43, 43) node _rob_respd_T_45 = bits(_rob_respd_T, 44, 44) node _rob_respd_T_46 = bits(_rob_respd_T, 45, 45) node _rob_respd_T_47 = bits(_rob_respd_T, 46, 46) node _rob_respd_T_48 = bits(_rob_respd_T, 47, 47) node _rob_respd_T_49 = bits(_rob_respd_T, 48, 48) node _rob_respd_T_50 = bits(_rob_respd_T, 49, 49) node _rob_respd_T_51 = bits(_rob_respd_T, 50, 50) node _rob_respd_T_52 = bits(_rob_respd_T, 51, 51) node _rob_respd_T_53 = bits(_rob_respd_T, 52, 52) node _rob_respd_T_54 = bits(_rob_respd_T, 53, 53) node _rob_respd_T_55 = bits(_rob_respd_T, 54, 54) node _rob_respd_T_56 = bits(_rob_respd_T, 55, 55) node _rob_respd_T_57 = bits(_rob_respd_T, 56, 56) node _rob_respd_T_58 = bits(_rob_respd_T, 57, 57) node _rob_respd_T_59 = bits(_rob_respd_T, 58, 58) node _rob_respd_T_60 = bits(_rob_respd_T, 59, 59) node _rob_respd_T_61 = bits(_rob_respd_T, 60, 60) node _rob_respd_T_62 = bits(_rob_respd_T, 61, 61) node _rob_respd_T_63 = bits(_rob_respd_T, 62, 62) node _rob_respd_T_64 = bits(_rob_respd_T, 63, 63) wire _rob_respd_WIRE : UInt<1>[64] connect _rob_respd_WIRE[0], _rob_respd_T_1 connect _rob_respd_WIRE[1], _rob_respd_T_2 connect _rob_respd_WIRE[2], _rob_respd_T_3 connect _rob_respd_WIRE[3], _rob_respd_T_4 connect _rob_respd_WIRE[4], _rob_respd_T_5 connect _rob_respd_WIRE[5], _rob_respd_T_6 connect _rob_respd_WIRE[6], _rob_respd_T_7 connect _rob_respd_WIRE[7], _rob_respd_T_8 connect _rob_respd_WIRE[8], _rob_respd_T_9 connect _rob_respd_WIRE[9], _rob_respd_T_10 connect _rob_respd_WIRE[10], _rob_respd_T_11 connect _rob_respd_WIRE[11], _rob_respd_T_12 connect _rob_respd_WIRE[12], _rob_respd_T_13 connect _rob_respd_WIRE[13], _rob_respd_T_14 connect _rob_respd_WIRE[14], _rob_respd_T_15 connect _rob_respd_WIRE[15], _rob_respd_T_16 connect _rob_respd_WIRE[16], _rob_respd_T_17 connect _rob_respd_WIRE[17], _rob_respd_T_18 connect _rob_respd_WIRE[18], _rob_respd_T_19 connect _rob_respd_WIRE[19], _rob_respd_T_20 connect _rob_respd_WIRE[20], _rob_respd_T_21 connect _rob_respd_WIRE[21], _rob_respd_T_22 connect _rob_respd_WIRE[22], _rob_respd_T_23 connect _rob_respd_WIRE[23], _rob_respd_T_24 connect _rob_respd_WIRE[24], _rob_respd_T_25 connect _rob_respd_WIRE[25], _rob_respd_T_26 connect _rob_respd_WIRE[26], _rob_respd_T_27 connect _rob_respd_WIRE[27], _rob_respd_T_28 connect _rob_respd_WIRE[28], _rob_respd_T_29 connect _rob_respd_WIRE[29], _rob_respd_T_30 connect _rob_respd_WIRE[30], _rob_respd_T_31 connect _rob_respd_WIRE[31], _rob_respd_T_32 connect _rob_respd_WIRE[32], _rob_respd_T_33 connect _rob_respd_WIRE[33], _rob_respd_T_34 connect _rob_respd_WIRE[34], _rob_respd_T_35 connect _rob_respd_WIRE[35], _rob_respd_T_36 connect _rob_respd_WIRE[36], _rob_respd_T_37 connect _rob_respd_WIRE[37], _rob_respd_T_38 connect _rob_respd_WIRE[38], _rob_respd_T_39 connect _rob_respd_WIRE[39], _rob_respd_T_40 connect _rob_respd_WIRE[40], _rob_respd_T_41 connect _rob_respd_WIRE[41], _rob_respd_T_42 connect _rob_respd_WIRE[42], _rob_respd_T_43 connect _rob_respd_WIRE[43], _rob_respd_T_44 connect _rob_respd_WIRE[44], _rob_respd_T_45 connect _rob_respd_WIRE[45], _rob_respd_T_46 connect _rob_respd_WIRE[46], _rob_respd_T_47 connect _rob_respd_WIRE[47], _rob_respd_T_48 connect _rob_respd_WIRE[48], _rob_respd_T_49 connect _rob_respd_WIRE[49], _rob_respd_T_50 connect _rob_respd_WIRE[50], _rob_respd_T_51 connect _rob_respd_WIRE[51], _rob_respd_T_52 connect _rob_respd_WIRE[52], _rob_respd_T_53 connect _rob_respd_WIRE[53], _rob_respd_T_54 connect _rob_respd_WIRE[54], _rob_respd_T_55 connect _rob_respd_WIRE[55], _rob_respd_T_56 connect _rob_respd_WIRE[56], _rob_respd_T_57 connect _rob_respd_WIRE[57], _rob_respd_T_58 connect _rob_respd_WIRE[58], _rob_respd_T_59 connect _rob_respd_WIRE[59], _rob_respd_T_60 connect _rob_respd_WIRE[60], _rob_respd_T_61 connect _rob_respd_WIRE[61], _rob_respd_T_62 connect _rob_respd_WIRE[62], _rob_respd_T_63 connect _rob_respd_WIRE[63], _rob_respd_T_64 regreset rob_respd : UInt<1>[64], clock, reset, _rob_respd_WIRE reg rob_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[64], clock wire _rob_bsy_WIRE : UInt<1>[64] connect _rob_bsy_WIRE[0], UInt<1>(0h0) connect _rob_bsy_WIRE[1], UInt<1>(0h0) connect _rob_bsy_WIRE[2], UInt<1>(0h0) connect _rob_bsy_WIRE[3], UInt<1>(0h0) connect _rob_bsy_WIRE[4], UInt<1>(0h0) connect _rob_bsy_WIRE[5], UInt<1>(0h0) connect _rob_bsy_WIRE[6], UInt<1>(0h0) connect _rob_bsy_WIRE[7], UInt<1>(0h0) connect _rob_bsy_WIRE[8], UInt<1>(0h0) connect _rob_bsy_WIRE[9], UInt<1>(0h0) connect _rob_bsy_WIRE[10], UInt<1>(0h0) connect _rob_bsy_WIRE[11], UInt<1>(0h0) connect _rob_bsy_WIRE[12], UInt<1>(0h0) connect _rob_bsy_WIRE[13], UInt<1>(0h0) connect _rob_bsy_WIRE[14], UInt<1>(0h0) connect _rob_bsy_WIRE[15], UInt<1>(0h0) connect _rob_bsy_WIRE[16], UInt<1>(0h0) connect _rob_bsy_WIRE[17], UInt<1>(0h0) connect _rob_bsy_WIRE[18], UInt<1>(0h0) connect _rob_bsy_WIRE[19], UInt<1>(0h0) connect _rob_bsy_WIRE[20], UInt<1>(0h0) connect _rob_bsy_WIRE[21], UInt<1>(0h0) connect _rob_bsy_WIRE[22], UInt<1>(0h0) connect _rob_bsy_WIRE[23], UInt<1>(0h0) connect _rob_bsy_WIRE[24], UInt<1>(0h0) connect _rob_bsy_WIRE[25], UInt<1>(0h0) connect _rob_bsy_WIRE[26], UInt<1>(0h0) connect _rob_bsy_WIRE[27], UInt<1>(0h0) connect _rob_bsy_WIRE[28], UInt<1>(0h0) connect _rob_bsy_WIRE[29], UInt<1>(0h0) connect _rob_bsy_WIRE[30], UInt<1>(0h0) connect _rob_bsy_WIRE[31], UInt<1>(0h0) connect _rob_bsy_WIRE[32], UInt<1>(0h0) connect _rob_bsy_WIRE[33], UInt<1>(0h0) connect _rob_bsy_WIRE[34], UInt<1>(0h0) connect _rob_bsy_WIRE[35], UInt<1>(0h0) connect _rob_bsy_WIRE[36], UInt<1>(0h0) connect _rob_bsy_WIRE[37], UInt<1>(0h0) connect _rob_bsy_WIRE[38], UInt<1>(0h0) connect _rob_bsy_WIRE[39], UInt<1>(0h0) connect _rob_bsy_WIRE[40], UInt<1>(0h0) connect _rob_bsy_WIRE[41], UInt<1>(0h0) connect _rob_bsy_WIRE[42], UInt<1>(0h0) connect _rob_bsy_WIRE[43], UInt<1>(0h0) connect _rob_bsy_WIRE[44], UInt<1>(0h0) connect _rob_bsy_WIRE[45], UInt<1>(0h0) connect _rob_bsy_WIRE[46], UInt<1>(0h0) connect _rob_bsy_WIRE[47], UInt<1>(0h0) connect _rob_bsy_WIRE[48], UInt<1>(0h0) connect _rob_bsy_WIRE[49], UInt<1>(0h0) connect _rob_bsy_WIRE[50], UInt<1>(0h0) connect _rob_bsy_WIRE[51], UInt<1>(0h0) connect _rob_bsy_WIRE[52], UInt<1>(0h0) connect _rob_bsy_WIRE[53], UInt<1>(0h0) connect _rob_bsy_WIRE[54], UInt<1>(0h0) connect _rob_bsy_WIRE[55], UInt<1>(0h0) connect _rob_bsy_WIRE[56], UInt<1>(0h0) connect _rob_bsy_WIRE[57], UInt<1>(0h0) connect _rob_bsy_WIRE[58], UInt<1>(0h0) connect _rob_bsy_WIRE[59], UInt<1>(0h0) connect _rob_bsy_WIRE[60], UInt<1>(0h0) connect _rob_bsy_WIRE[61], UInt<1>(0h0) connect _rob_bsy_WIRE[62], UInt<1>(0h0) connect _rob_bsy_WIRE[63], UInt<1>(0h0) regreset rob_bsy : UInt<1>[64], clock, reset, _rob_bsy_WIRE regreset rob_head : UInt<6>, clock, reset, UInt<6>(0h0) regreset rob_tail : UInt<6>, clock, reset, UInt<6>(0h0) regreset rob_wait_till_empty : UInt<1>, clock, reset, UInt<1>(0h0) node _ready_for_amo_T = eq(rob_tail, rob_head) node ready_for_amo = and(_ready_for_amo_T, io.lsu.fencei_rdy) when ready_for_amo : connect rob_wait_till_empty, UInt<1>(0h0) node _io_tracegen_req_ready_T = eq(rob_bsy[rob_tail], UInt<1>(0h0)) node _io_tracegen_req_ready_T_1 = eq(rob_wait_till_empty, UInt<1>(0h0)) node _io_tracegen_req_ready_T_2 = and(_io_tracegen_req_ready_T, _io_tracegen_req_ready_T_1) node _io_tracegen_req_ready_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _io_tracegen_req_ready_T_4 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _io_tracegen_req_ready_T_5 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _io_tracegen_req_ready_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _io_tracegen_req_ready_T_7 = or(_io_tracegen_req_ready_T_3, _io_tracegen_req_ready_T_4) node _io_tracegen_req_ready_T_8 = or(_io_tracegen_req_ready_T_7, _io_tracegen_req_ready_T_5) node _io_tracegen_req_ready_T_9 = or(_io_tracegen_req_ready_T_8, _io_tracegen_req_ready_T_6) node _io_tracegen_req_ready_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _io_tracegen_req_ready_T_11 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _io_tracegen_req_ready_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _io_tracegen_req_ready_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _io_tracegen_req_ready_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _io_tracegen_req_ready_T_15 = or(_io_tracegen_req_ready_T_10, _io_tracegen_req_ready_T_11) node _io_tracegen_req_ready_T_16 = or(_io_tracegen_req_ready_T_15, _io_tracegen_req_ready_T_12) node _io_tracegen_req_ready_T_17 = or(_io_tracegen_req_ready_T_16, _io_tracegen_req_ready_T_13) node _io_tracegen_req_ready_T_18 = or(_io_tracegen_req_ready_T_17, _io_tracegen_req_ready_T_14) node _io_tracegen_req_ready_T_19 = or(_io_tracegen_req_ready_T_9, _io_tracegen_req_ready_T_18) node _io_tracegen_req_ready_T_20 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _io_tracegen_req_ready_T_21 = or(_io_tracegen_req_ready_T_19, _io_tracegen_req_ready_T_20) node _io_tracegen_req_ready_T_22 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _io_tracegen_req_ready_T_23 = or(_io_tracegen_req_ready_T_21, _io_tracegen_req_ready_T_22) node _io_tracegen_req_ready_T_24 = eq(_io_tracegen_req_ready_T_23, UInt<1>(0h0)) node _io_tracegen_req_ready_T_25 = or(ready_for_amo, _io_tracegen_req_ready_T_24) node _io_tracegen_req_ready_T_26 = and(_io_tracegen_req_ready_T_2, _io_tracegen_req_ready_T_25) node _io_tracegen_req_ready_T_27 = eq(rob_tail, UInt<6>(0h3f)) node _io_tracegen_req_ready_T_28 = add(rob_tail, UInt<1>(0h1)) node _io_tracegen_req_ready_T_29 = tail(_io_tracegen_req_ready_T_28, 1) node _io_tracegen_req_ready_T_30 = mux(_io_tracegen_req_ready_T_27, UInt<1>(0h0), _io_tracegen_req_ready_T_29) node _io_tracegen_req_ready_T_31 = neq(_io_tracegen_req_ready_T_30, rob_head) node _io_tracegen_req_ready_T_32 = and(_io_tracegen_req_ready_T_26, _io_tracegen_req_ready_T_31) node _io_tracegen_req_ready_T_33 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h0)) node _io_tracegen_req_ready_T_34 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h10)) node _io_tracegen_req_ready_T_35 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _io_tracegen_req_ready_T_36 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _io_tracegen_req_ready_T_37 = or(_io_tracegen_req_ready_T_33, _io_tracegen_req_ready_T_34) node _io_tracegen_req_ready_T_38 = or(_io_tracegen_req_ready_T_37, _io_tracegen_req_ready_T_35) node _io_tracegen_req_ready_T_39 = or(_io_tracegen_req_ready_T_38, _io_tracegen_req_ready_T_36) node _io_tracegen_req_ready_T_40 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _io_tracegen_req_ready_T_41 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _io_tracegen_req_ready_T_42 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _io_tracegen_req_ready_T_43 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _io_tracegen_req_ready_T_44 = or(_io_tracegen_req_ready_T_40, _io_tracegen_req_ready_T_41) node _io_tracegen_req_ready_T_45 = or(_io_tracegen_req_ready_T_44, _io_tracegen_req_ready_T_42) node _io_tracegen_req_ready_T_46 = or(_io_tracegen_req_ready_T_45, _io_tracegen_req_ready_T_43) node _io_tracegen_req_ready_T_47 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _io_tracegen_req_ready_T_48 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _io_tracegen_req_ready_T_49 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _io_tracegen_req_ready_T_50 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _io_tracegen_req_ready_T_51 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _io_tracegen_req_ready_T_52 = or(_io_tracegen_req_ready_T_47, _io_tracegen_req_ready_T_48) node _io_tracegen_req_ready_T_53 = or(_io_tracegen_req_ready_T_52, _io_tracegen_req_ready_T_49) node _io_tracegen_req_ready_T_54 = or(_io_tracegen_req_ready_T_53, _io_tracegen_req_ready_T_50) node _io_tracegen_req_ready_T_55 = or(_io_tracegen_req_ready_T_54, _io_tracegen_req_ready_T_51) node _io_tracegen_req_ready_T_56 = or(_io_tracegen_req_ready_T_46, _io_tracegen_req_ready_T_55) node _io_tracegen_req_ready_T_57 = or(_io_tracegen_req_ready_T_39, _io_tracegen_req_ready_T_56) node _io_tracegen_req_ready_T_58 = and(io.lsu.ldq_full[0], _io_tracegen_req_ready_T_57) node _io_tracegen_req_ready_T_59 = eq(_io_tracegen_req_ready_T_58, UInt<1>(0h0)) node _io_tracegen_req_ready_T_60 = and(_io_tracegen_req_ready_T_32, _io_tracegen_req_ready_T_59) node _io_tracegen_req_ready_T_61 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _io_tracegen_req_ready_T_62 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _io_tracegen_req_ready_T_63 = or(_io_tracegen_req_ready_T_61, _io_tracegen_req_ready_T_62) node _io_tracegen_req_ready_T_64 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _io_tracegen_req_ready_T_65 = or(_io_tracegen_req_ready_T_63, _io_tracegen_req_ready_T_64) node _io_tracegen_req_ready_T_66 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _io_tracegen_req_ready_T_67 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _io_tracegen_req_ready_T_68 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _io_tracegen_req_ready_T_69 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _io_tracegen_req_ready_T_70 = or(_io_tracegen_req_ready_T_66, _io_tracegen_req_ready_T_67) node _io_tracegen_req_ready_T_71 = or(_io_tracegen_req_ready_T_70, _io_tracegen_req_ready_T_68) node _io_tracegen_req_ready_T_72 = or(_io_tracegen_req_ready_T_71, _io_tracegen_req_ready_T_69) node _io_tracegen_req_ready_T_73 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _io_tracegen_req_ready_T_74 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _io_tracegen_req_ready_T_75 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _io_tracegen_req_ready_T_76 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _io_tracegen_req_ready_T_77 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _io_tracegen_req_ready_T_78 = or(_io_tracegen_req_ready_T_73, _io_tracegen_req_ready_T_74) node _io_tracegen_req_ready_T_79 = or(_io_tracegen_req_ready_T_78, _io_tracegen_req_ready_T_75) node _io_tracegen_req_ready_T_80 = or(_io_tracegen_req_ready_T_79, _io_tracegen_req_ready_T_76) node _io_tracegen_req_ready_T_81 = or(_io_tracegen_req_ready_T_80, _io_tracegen_req_ready_T_77) node _io_tracegen_req_ready_T_82 = or(_io_tracegen_req_ready_T_72, _io_tracegen_req_ready_T_81) node _io_tracegen_req_ready_T_83 = or(_io_tracegen_req_ready_T_65, _io_tracegen_req_ready_T_82) node _io_tracegen_req_ready_T_84 = and(io.lsu.stq_full[0], _io_tracegen_req_ready_T_83) node _io_tracegen_req_ready_T_85 = eq(_io_tracegen_req_ready_T_84, UInt<1>(0h0)) node _io_tracegen_req_ready_T_86 = and(_io_tracegen_req_ready_T_60, _io_tracegen_req_ready_T_85) connect io.tracegen.req.ready, _io_tracegen_req_ready_T_86 wire _tracegen_uop_WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect _tracegen_uop_WIRE.debug_tsrc, UInt<2>(0h0) connect _tracegen_uop_WIRE.debug_fsrc, UInt<2>(0h0) connect _tracegen_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _tracegen_uop_WIRE.fp_single, UInt<1>(0h0) connect _tracegen_uop_WIRE.fp_val, UInt<1>(0h0) connect _tracegen_uop_WIRE.frs3_en, UInt<1>(0h0) connect _tracegen_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _tracegen_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _tracegen_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _tracegen_uop_WIRE.ldst_val, UInt<1>(0h0) connect _tracegen_uop_WIRE.lrs3, UInt<6>(0h0) connect _tracegen_uop_WIRE.lrs2, UInt<6>(0h0) connect _tracegen_uop_WIRE.lrs1, UInt<6>(0h0) connect _tracegen_uop_WIRE.ldst, UInt<6>(0h0) connect _tracegen_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _tracegen_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_unique, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _tracegen_uop_WIRE.uses_stq, UInt<1>(0h0) connect _tracegen_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_amo, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_fencei, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_fence, UInt<1>(0h0) connect _tracegen_uop_WIRE.mem_signed, UInt<1>(0h0) connect _tracegen_uop_WIRE.mem_size, UInt<2>(0h0) connect _tracegen_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _tracegen_uop_WIRE.bypassable, UInt<1>(0h0) connect _tracegen_uop_WIRE.exc_cause, UInt<64>(0h0) connect _tracegen_uop_WIRE.exception, UInt<1>(0h0) connect _tracegen_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _tracegen_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _tracegen_uop_WIRE.ppred, UInt<4>(0h0) connect _tracegen_uop_WIRE.prs3, UInt<7>(0h0) connect _tracegen_uop_WIRE.prs2, UInt<7>(0h0) connect _tracegen_uop_WIRE.prs1, UInt<7>(0h0) connect _tracegen_uop_WIRE.pdst, UInt<7>(0h0) connect _tracegen_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _tracegen_uop_WIRE.stq_idx, UInt<4>(0h0) connect _tracegen_uop_WIRE.ldq_idx, UInt<4>(0h0) connect _tracegen_uop_WIRE.rob_idx, UInt<6>(0h0) connect _tracegen_uop_WIRE.csr_addr, UInt<12>(0h0) connect _tracegen_uop_WIRE.imm_packed, UInt<20>(0h0) connect _tracegen_uop_WIRE.taken, UInt<1>(0h0) connect _tracegen_uop_WIRE.pc_lob, UInt<6>(0h0) connect _tracegen_uop_WIRE.edge_inst, UInt<1>(0h0) connect _tracegen_uop_WIRE.ftq_idx, UInt<4>(0h0) connect _tracegen_uop_WIRE.br_tag, UInt<2>(0h0) connect _tracegen_uop_WIRE.br_mask, UInt<4>(0h0) connect _tracegen_uop_WIRE.is_sfb, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_jal, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_jalr, UInt<1>(0h0) connect _tracegen_uop_WIRE.is_br, UInt<1>(0h0) connect _tracegen_uop_WIRE.iw_p2_poisoned, UInt<1>(0h0) connect _tracegen_uop_WIRE.iw_p1_poisoned, UInt<1>(0h0) connect _tracegen_uop_WIRE.iw_state, UInt<2>(0h0) connect _tracegen_uop_WIRE.ctrl.is_std, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.is_sta, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.is_load, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.csr_cmd, UInt<3>(0h0) connect _tracegen_uop_WIRE.ctrl.fcn_dw, UInt<1>(0h0) connect _tracegen_uop_WIRE.ctrl.op_fcn, UInt<5>(0h0) connect _tracegen_uop_WIRE.ctrl.imm_sel, UInt<3>(0h0) connect _tracegen_uop_WIRE.ctrl.op2_sel, UInt<3>(0h0) connect _tracegen_uop_WIRE.ctrl.op1_sel, UInt<2>(0h0) connect _tracegen_uop_WIRE.ctrl.br_type, UInt<4>(0h0) connect _tracegen_uop_WIRE.fu_code, UInt<10>(0h0) connect _tracegen_uop_WIRE.iq_type, UInt<3>(0h0) connect _tracegen_uop_WIRE.debug_pc, UInt<34>(0h0) connect _tracegen_uop_WIRE.is_rvc, UInt<1>(0h0) connect _tracegen_uop_WIRE.debug_inst, UInt<32>(0h0) connect _tracegen_uop_WIRE.inst, UInt<32>(0h0) connect _tracegen_uop_WIRE.uopc, UInt<7>(0h0) wire tracegen_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect tracegen_uop, _tracegen_uop_WIRE node _tracegen_uop_uses_ldq_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h0)) node _tracegen_uop_uses_ldq_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h10)) node _tracegen_uop_uses_ldq_T_2 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _tracegen_uop_uses_ldq_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_uses_ldq_T_4 = or(_tracegen_uop_uses_ldq_T, _tracegen_uop_uses_ldq_T_1) node _tracegen_uop_uses_ldq_T_5 = or(_tracegen_uop_uses_ldq_T_4, _tracegen_uop_uses_ldq_T_2) node _tracegen_uop_uses_ldq_T_6 = or(_tracegen_uop_uses_ldq_T_5, _tracegen_uop_uses_ldq_T_3) node _tracegen_uop_uses_ldq_T_7 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_uses_ldq_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_uses_ldq_T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_uses_ldq_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_uses_ldq_T_11 = or(_tracegen_uop_uses_ldq_T_7, _tracegen_uop_uses_ldq_T_8) node _tracegen_uop_uses_ldq_T_12 = or(_tracegen_uop_uses_ldq_T_11, _tracegen_uop_uses_ldq_T_9) node _tracegen_uop_uses_ldq_T_13 = or(_tracegen_uop_uses_ldq_T_12, _tracegen_uop_uses_ldq_T_10) node _tracegen_uop_uses_ldq_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_uses_ldq_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_uses_ldq_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_uses_ldq_T_17 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_uses_ldq_T_18 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_uses_ldq_T_19 = or(_tracegen_uop_uses_ldq_T_14, _tracegen_uop_uses_ldq_T_15) node _tracegen_uop_uses_ldq_T_20 = or(_tracegen_uop_uses_ldq_T_19, _tracegen_uop_uses_ldq_T_16) node _tracegen_uop_uses_ldq_T_21 = or(_tracegen_uop_uses_ldq_T_20, _tracegen_uop_uses_ldq_T_17) node _tracegen_uop_uses_ldq_T_22 = or(_tracegen_uop_uses_ldq_T_21, _tracegen_uop_uses_ldq_T_18) node _tracegen_uop_uses_ldq_T_23 = or(_tracegen_uop_uses_ldq_T_13, _tracegen_uop_uses_ldq_T_22) node _tracegen_uop_uses_ldq_T_24 = or(_tracegen_uop_uses_ldq_T_6, _tracegen_uop_uses_ldq_T_23) node _tracegen_uop_uses_ldq_T_25 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_uses_ldq_T_26 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_uses_ldq_T_27 = or(_tracegen_uop_uses_ldq_T_25, _tracegen_uop_uses_ldq_T_26) node _tracegen_uop_uses_ldq_T_28 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_uses_ldq_T_29 = or(_tracegen_uop_uses_ldq_T_27, _tracegen_uop_uses_ldq_T_28) node _tracegen_uop_uses_ldq_T_30 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_uses_ldq_T_31 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_uses_ldq_T_32 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_uses_ldq_T_33 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_uses_ldq_T_34 = or(_tracegen_uop_uses_ldq_T_30, _tracegen_uop_uses_ldq_T_31) node _tracegen_uop_uses_ldq_T_35 = or(_tracegen_uop_uses_ldq_T_34, _tracegen_uop_uses_ldq_T_32) node _tracegen_uop_uses_ldq_T_36 = or(_tracegen_uop_uses_ldq_T_35, _tracegen_uop_uses_ldq_T_33) node _tracegen_uop_uses_ldq_T_37 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_uses_ldq_T_38 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_uses_ldq_T_39 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_uses_ldq_T_40 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_uses_ldq_T_41 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_uses_ldq_T_42 = or(_tracegen_uop_uses_ldq_T_37, _tracegen_uop_uses_ldq_T_38) node _tracegen_uop_uses_ldq_T_43 = or(_tracegen_uop_uses_ldq_T_42, _tracegen_uop_uses_ldq_T_39) node _tracegen_uop_uses_ldq_T_44 = or(_tracegen_uop_uses_ldq_T_43, _tracegen_uop_uses_ldq_T_40) node _tracegen_uop_uses_ldq_T_45 = or(_tracegen_uop_uses_ldq_T_44, _tracegen_uop_uses_ldq_T_41) node _tracegen_uop_uses_ldq_T_46 = or(_tracegen_uop_uses_ldq_T_36, _tracegen_uop_uses_ldq_T_45) node _tracegen_uop_uses_ldq_T_47 = or(_tracegen_uop_uses_ldq_T_29, _tracegen_uop_uses_ldq_T_46) node _tracegen_uop_uses_ldq_T_48 = eq(_tracegen_uop_uses_ldq_T_47, UInt<1>(0h0)) node _tracegen_uop_uses_ldq_T_49 = and(_tracegen_uop_uses_ldq_T_24, _tracegen_uop_uses_ldq_T_48) connect tracegen_uop.uses_ldq, _tracegen_uop_uses_ldq_T_49 node _tracegen_uop_uses_stq_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_uses_stq_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_uses_stq_T_2 = or(_tracegen_uop_uses_stq_T, _tracegen_uop_uses_stq_T_1) node _tracegen_uop_uses_stq_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_uses_stq_T_4 = or(_tracegen_uop_uses_stq_T_2, _tracegen_uop_uses_stq_T_3) node _tracegen_uop_uses_stq_T_5 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_uses_stq_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_uses_stq_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_uses_stq_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_uses_stq_T_9 = or(_tracegen_uop_uses_stq_T_5, _tracegen_uop_uses_stq_T_6) node _tracegen_uop_uses_stq_T_10 = or(_tracegen_uop_uses_stq_T_9, _tracegen_uop_uses_stq_T_7) node _tracegen_uop_uses_stq_T_11 = or(_tracegen_uop_uses_stq_T_10, _tracegen_uop_uses_stq_T_8) node _tracegen_uop_uses_stq_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_uses_stq_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_uses_stq_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_uses_stq_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_uses_stq_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_uses_stq_T_17 = or(_tracegen_uop_uses_stq_T_12, _tracegen_uop_uses_stq_T_13) node _tracegen_uop_uses_stq_T_18 = or(_tracegen_uop_uses_stq_T_17, _tracegen_uop_uses_stq_T_14) node _tracegen_uop_uses_stq_T_19 = or(_tracegen_uop_uses_stq_T_18, _tracegen_uop_uses_stq_T_15) node _tracegen_uop_uses_stq_T_20 = or(_tracegen_uop_uses_stq_T_19, _tracegen_uop_uses_stq_T_16) node _tracegen_uop_uses_stq_T_21 = or(_tracegen_uop_uses_stq_T_11, _tracegen_uop_uses_stq_T_20) node _tracegen_uop_uses_stq_T_22 = or(_tracegen_uop_uses_stq_T_4, _tracegen_uop_uses_stq_T_21) connect tracegen_uop.uses_stq, _tracegen_uop_uses_stq_T_22 connect tracegen_uop.rob_idx, rob_tail connect tracegen_uop.uopc, io.tracegen.req.bits.tag connect tracegen_uop.mem_size, io.tracegen.req.bits.size connect tracegen_uop.mem_cmd, io.tracegen.req.bits.cmd connect tracegen_uop.mem_signed, io.tracegen.req.bits.signed connect tracegen_uop.ldq_idx, io.lsu.dis_ldq_idx[0] connect tracegen_uop.stq_idx, io.lsu.dis_stq_idx[0] node _tracegen_uop_is_amo_T = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_is_amo_T_1 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_is_amo_T_2 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_is_amo_T_3 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_is_amo_T_4 = or(_tracegen_uop_is_amo_T, _tracegen_uop_is_amo_T_1) node _tracegen_uop_is_amo_T_5 = or(_tracegen_uop_is_amo_T_4, _tracegen_uop_is_amo_T_2) node _tracegen_uop_is_amo_T_6 = or(_tracegen_uop_is_amo_T_5, _tracegen_uop_is_amo_T_3) node _tracegen_uop_is_amo_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_is_amo_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_is_amo_T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_is_amo_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_is_amo_T_11 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_is_amo_T_12 = or(_tracegen_uop_is_amo_T_7, _tracegen_uop_is_amo_T_8) node _tracegen_uop_is_amo_T_13 = or(_tracegen_uop_is_amo_T_12, _tracegen_uop_is_amo_T_9) node _tracegen_uop_is_amo_T_14 = or(_tracegen_uop_is_amo_T_13, _tracegen_uop_is_amo_T_10) node _tracegen_uop_is_amo_T_15 = or(_tracegen_uop_is_amo_T_14, _tracegen_uop_is_amo_T_11) node _tracegen_uop_is_amo_T_16 = or(_tracegen_uop_is_amo_T_6, _tracegen_uop_is_amo_T_15) node _tracegen_uop_is_amo_T_17 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_is_amo_T_18 = or(_tracegen_uop_is_amo_T_16, _tracegen_uop_is_amo_T_17) connect tracegen_uop.is_amo, _tracegen_uop_is_amo_T_18 node _tracegen_uop_ctrl_is_load_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h0)) node _tracegen_uop_ctrl_is_load_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h10)) node _tracegen_uop_ctrl_is_load_T_2 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _tracegen_uop_ctrl_is_load_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_load_T_4 = or(_tracegen_uop_ctrl_is_load_T, _tracegen_uop_ctrl_is_load_T_1) node _tracegen_uop_ctrl_is_load_T_5 = or(_tracegen_uop_ctrl_is_load_T_4, _tracegen_uop_ctrl_is_load_T_2) node _tracegen_uop_ctrl_is_load_T_6 = or(_tracegen_uop_ctrl_is_load_T_5, _tracegen_uop_ctrl_is_load_T_3) node _tracegen_uop_ctrl_is_load_T_7 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_load_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_load_T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_load_T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_load_T_11 = or(_tracegen_uop_ctrl_is_load_T_7, _tracegen_uop_ctrl_is_load_T_8) node _tracegen_uop_ctrl_is_load_T_12 = or(_tracegen_uop_ctrl_is_load_T_11, _tracegen_uop_ctrl_is_load_T_9) node _tracegen_uop_ctrl_is_load_T_13 = or(_tracegen_uop_ctrl_is_load_T_12, _tracegen_uop_ctrl_is_load_T_10) node _tracegen_uop_ctrl_is_load_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_load_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_load_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_load_T_17 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_load_T_18 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_load_T_19 = or(_tracegen_uop_ctrl_is_load_T_14, _tracegen_uop_ctrl_is_load_T_15) node _tracegen_uop_ctrl_is_load_T_20 = or(_tracegen_uop_ctrl_is_load_T_19, _tracegen_uop_ctrl_is_load_T_16) node _tracegen_uop_ctrl_is_load_T_21 = or(_tracegen_uop_ctrl_is_load_T_20, _tracegen_uop_ctrl_is_load_T_17) node _tracegen_uop_ctrl_is_load_T_22 = or(_tracegen_uop_ctrl_is_load_T_21, _tracegen_uop_ctrl_is_load_T_18) node _tracegen_uop_ctrl_is_load_T_23 = or(_tracegen_uop_ctrl_is_load_T_13, _tracegen_uop_ctrl_is_load_T_22) node _tracegen_uop_ctrl_is_load_T_24 = or(_tracegen_uop_ctrl_is_load_T_6, _tracegen_uop_ctrl_is_load_T_23) node _tracegen_uop_ctrl_is_load_T_25 = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_ctrl_is_load_T_26 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_ctrl_is_load_T_27 = or(_tracegen_uop_ctrl_is_load_T_25, _tracegen_uop_ctrl_is_load_T_26) node _tracegen_uop_ctrl_is_load_T_28 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_load_T_29 = or(_tracegen_uop_ctrl_is_load_T_27, _tracegen_uop_ctrl_is_load_T_28) node _tracegen_uop_ctrl_is_load_T_30 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_load_T_31 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_load_T_32 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_load_T_33 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_load_T_34 = or(_tracegen_uop_ctrl_is_load_T_30, _tracegen_uop_ctrl_is_load_T_31) node _tracegen_uop_ctrl_is_load_T_35 = or(_tracegen_uop_ctrl_is_load_T_34, _tracegen_uop_ctrl_is_load_T_32) node _tracegen_uop_ctrl_is_load_T_36 = or(_tracegen_uop_ctrl_is_load_T_35, _tracegen_uop_ctrl_is_load_T_33) node _tracegen_uop_ctrl_is_load_T_37 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_load_T_38 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_load_T_39 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_load_T_40 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_load_T_41 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_load_T_42 = or(_tracegen_uop_ctrl_is_load_T_37, _tracegen_uop_ctrl_is_load_T_38) node _tracegen_uop_ctrl_is_load_T_43 = or(_tracegen_uop_ctrl_is_load_T_42, _tracegen_uop_ctrl_is_load_T_39) node _tracegen_uop_ctrl_is_load_T_44 = or(_tracegen_uop_ctrl_is_load_T_43, _tracegen_uop_ctrl_is_load_T_40) node _tracegen_uop_ctrl_is_load_T_45 = or(_tracegen_uop_ctrl_is_load_T_44, _tracegen_uop_ctrl_is_load_T_41) node _tracegen_uop_ctrl_is_load_T_46 = or(_tracegen_uop_ctrl_is_load_T_36, _tracegen_uop_ctrl_is_load_T_45) node _tracegen_uop_ctrl_is_load_T_47 = or(_tracegen_uop_ctrl_is_load_T_29, _tracegen_uop_ctrl_is_load_T_46) node _tracegen_uop_ctrl_is_load_T_48 = eq(_tracegen_uop_ctrl_is_load_T_47, UInt<1>(0h0)) node _tracegen_uop_ctrl_is_load_T_49 = and(_tracegen_uop_ctrl_is_load_T_24, _tracegen_uop_ctrl_is_load_T_48) connect tracegen_uop.ctrl.is_load, _tracegen_uop_ctrl_is_load_T_49 node _tracegen_uop_ctrl_is_sta_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_ctrl_is_sta_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_ctrl_is_sta_T_2 = or(_tracegen_uop_ctrl_is_sta_T, _tracegen_uop_ctrl_is_sta_T_1) node _tracegen_uop_ctrl_is_sta_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_sta_T_4 = or(_tracegen_uop_ctrl_is_sta_T_2, _tracegen_uop_ctrl_is_sta_T_3) node _tracegen_uop_ctrl_is_sta_T_5 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_sta_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_sta_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_sta_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_sta_T_9 = or(_tracegen_uop_ctrl_is_sta_T_5, _tracegen_uop_ctrl_is_sta_T_6) node _tracegen_uop_ctrl_is_sta_T_10 = or(_tracegen_uop_ctrl_is_sta_T_9, _tracegen_uop_ctrl_is_sta_T_7) node _tracegen_uop_ctrl_is_sta_T_11 = or(_tracegen_uop_ctrl_is_sta_T_10, _tracegen_uop_ctrl_is_sta_T_8) node _tracegen_uop_ctrl_is_sta_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_sta_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_sta_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_sta_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_sta_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_sta_T_17 = or(_tracegen_uop_ctrl_is_sta_T_12, _tracegen_uop_ctrl_is_sta_T_13) node _tracegen_uop_ctrl_is_sta_T_18 = or(_tracegen_uop_ctrl_is_sta_T_17, _tracegen_uop_ctrl_is_sta_T_14) node _tracegen_uop_ctrl_is_sta_T_19 = or(_tracegen_uop_ctrl_is_sta_T_18, _tracegen_uop_ctrl_is_sta_T_15) node _tracegen_uop_ctrl_is_sta_T_20 = or(_tracegen_uop_ctrl_is_sta_T_19, _tracegen_uop_ctrl_is_sta_T_16) node _tracegen_uop_ctrl_is_sta_T_21 = or(_tracegen_uop_ctrl_is_sta_T_11, _tracegen_uop_ctrl_is_sta_T_20) node _tracegen_uop_ctrl_is_sta_T_22 = or(_tracegen_uop_ctrl_is_sta_T_4, _tracegen_uop_ctrl_is_sta_T_21) connect tracegen_uop.ctrl.is_sta, _tracegen_uop_ctrl_is_sta_T_22 node _tracegen_uop_ctrl_is_std_T = eq(io.tracegen.req.bits.cmd, UInt<1>(0h1)) node _tracegen_uop_ctrl_is_std_T_1 = eq(io.tracegen.req.bits.cmd, UInt<5>(0h11)) node _tracegen_uop_ctrl_is_std_T_2 = or(_tracegen_uop_ctrl_is_std_T, _tracegen_uop_ctrl_is_std_T_1) node _tracegen_uop_ctrl_is_std_T_3 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _tracegen_uop_ctrl_is_std_T_4 = or(_tracegen_uop_ctrl_is_std_T_2, _tracegen_uop_ctrl_is_std_T_3) node _tracegen_uop_ctrl_is_std_T_5 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _tracegen_uop_ctrl_is_std_T_6 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _tracegen_uop_ctrl_is_std_T_7 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _tracegen_uop_ctrl_is_std_T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _tracegen_uop_ctrl_is_std_T_9 = or(_tracegen_uop_ctrl_is_std_T_5, _tracegen_uop_ctrl_is_std_T_6) node _tracegen_uop_ctrl_is_std_T_10 = or(_tracegen_uop_ctrl_is_std_T_9, _tracegen_uop_ctrl_is_std_T_7) node _tracegen_uop_ctrl_is_std_T_11 = or(_tracegen_uop_ctrl_is_std_T_10, _tracegen_uop_ctrl_is_std_T_8) node _tracegen_uop_ctrl_is_std_T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _tracegen_uop_ctrl_is_std_T_13 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _tracegen_uop_ctrl_is_std_T_14 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _tracegen_uop_ctrl_is_std_T_15 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _tracegen_uop_ctrl_is_std_T_16 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _tracegen_uop_ctrl_is_std_T_17 = or(_tracegen_uop_ctrl_is_std_T_12, _tracegen_uop_ctrl_is_std_T_13) node _tracegen_uop_ctrl_is_std_T_18 = or(_tracegen_uop_ctrl_is_std_T_17, _tracegen_uop_ctrl_is_std_T_14) node _tracegen_uop_ctrl_is_std_T_19 = or(_tracegen_uop_ctrl_is_std_T_18, _tracegen_uop_ctrl_is_std_T_15) node _tracegen_uop_ctrl_is_std_T_20 = or(_tracegen_uop_ctrl_is_std_T_19, _tracegen_uop_ctrl_is_std_T_16) node _tracegen_uop_ctrl_is_std_T_21 = or(_tracegen_uop_ctrl_is_std_T_11, _tracegen_uop_ctrl_is_std_T_20) node _tracegen_uop_ctrl_is_std_T_22 = or(_tracegen_uop_ctrl_is_std_T_4, _tracegen_uop_ctrl_is_std_T_21) connect tracegen_uop.ctrl.is_std, _tracegen_uop_ctrl_is_std_T_22 node _io_lsu_dis_uops_0_valid_T = and(io.tracegen.req.ready, io.tracegen.req.valid) connect io.lsu.dis_uops[0].valid, _io_lsu_dis_uops_0_valid_T connect io.lsu.dis_uops[0].bits, tracegen_uop node _T = and(io.tracegen.req.ready, io.tracegen.req.valid) when _T : node _rob_tail_T = eq(rob_tail, UInt<6>(0h3f)) node _rob_tail_T_1 = add(rob_tail, UInt<1>(0h1)) node _rob_tail_T_2 = tail(_rob_tail_T_1, 1) node _rob_tail_T_3 = mux(_rob_tail_T, UInt<1>(0h0), _rob_tail_T_2) connect rob_tail, _rob_tail_T_3 connect rob_bsy[rob_tail], UInt<1>(0h1) connect rob_uop[rob_tail], tracegen_uop connect rob_respd[rob_tail], UInt<1>(0h0) connect rob[rob_tail], io.tracegen.req.bits node _T_1 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h4)) node _T_2 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h9)) node _T_3 = eq(io.tracegen.req.bits.cmd, UInt<4>(0ha)) node _T_4 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hb)) node _T_5 = or(_T_1, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = or(_T_6, _T_4) node _T_8 = eq(io.tracegen.req.bits.cmd, UInt<4>(0h8)) node _T_9 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hc)) node _T_10 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hd)) node _T_11 = eq(io.tracegen.req.bits.cmd, UInt<4>(0he)) node _T_12 = eq(io.tracegen.req.bits.cmd, UInt<4>(0hf)) node _T_13 = or(_T_8, _T_9) node _T_14 = or(_T_13, _T_10) node _T_15 = or(_T_14, _T_11) node _T_16 = or(_T_15, _T_12) node _T_17 = or(_T_7, _T_16) node _T_18 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h6)) node _T_19 = or(_T_17, _T_18) node _T_20 = eq(io.tracegen.req.bits.cmd, UInt<3>(0h7)) node _T_21 = or(_T_19, _T_20) when _T_21 : connect rob_wait_till_empty, UInt<1>(0h1) connect io.lsu.fp_stdata.valid, UInt<1>(0h0) invalidate io.lsu.fp_stdata.bits.fflags.bits.flags invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.exception invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.taken invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.inst invalidate io.lsu.fp_stdata.bits.fflags.bits.uop.uopc invalidate io.lsu.fp_stdata.bits.fflags.valid invalidate io.lsu.fp_stdata.bits.predicated invalidate io.lsu.fp_stdata.bits.data invalidate io.lsu.fp_stdata.bits.uop.debug_tsrc invalidate io.lsu.fp_stdata.bits.uop.debug_fsrc invalidate io.lsu.fp_stdata.bits.uop.bp_xcpt_if invalidate io.lsu.fp_stdata.bits.uop.bp_debug_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ma_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_ae_if invalidate io.lsu.fp_stdata.bits.uop.xcpt_pf_if invalidate io.lsu.fp_stdata.bits.uop.fp_single invalidate io.lsu.fp_stdata.bits.uop.fp_val invalidate io.lsu.fp_stdata.bits.uop.frs3_en invalidate io.lsu.fp_stdata.bits.uop.lrs2_rtype invalidate io.lsu.fp_stdata.bits.uop.lrs1_rtype invalidate io.lsu.fp_stdata.bits.uop.dst_rtype invalidate io.lsu.fp_stdata.bits.uop.ldst_val invalidate io.lsu.fp_stdata.bits.uop.lrs3 invalidate io.lsu.fp_stdata.bits.uop.lrs2 invalidate io.lsu.fp_stdata.bits.uop.lrs1 invalidate io.lsu.fp_stdata.bits.uop.ldst invalidate io.lsu.fp_stdata.bits.uop.ldst_is_rs1 invalidate io.lsu.fp_stdata.bits.uop.flush_on_commit invalidate io.lsu.fp_stdata.bits.uop.is_unique invalidate io.lsu.fp_stdata.bits.uop.is_sys_pc2epc invalidate io.lsu.fp_stdata.bits.uop.uses_stq invalidate io.lsu.fp_stdata.bits.uop.uses_ldq invalidate io.lsu.fp_stdata.bits.uop.is_amo invalidate io.lsu.fp_stdata.bits.uop.is_fencei invalidate io.lsu.fp_stdata.bits.uop.is_fence invalidate io.lsu.fp_stdata.bits.uop.mem_signed invalidate io.lsu.fp_stdata.bits.uop.mem_size invalidate io.lsu.fp_stdata.bits.uop.mem_cmd invalidate io.lsu.fp_stdata.bits.uop.bypassable invalidate io.lsu.fp_stdata.bits.uop.exc_cause invalidate io.lsu.fp_stdata.bits.uop.exception invalidate io.lsu.fp_stdata.bits.uop.stale_pdst invalidate io.lsu.fp_stdata.bits.uop.ppred_busy invalidate io.lsu.fp_stdata.bits.uop.prs3_busy invalidate io.lsu.fp_stdata.bits.uop.prs2_busy invalidate io.lsu.fp_stdata.bits.uop.prs1_busy invalidate io.lsu.fp_stdata.bits.uop.ppred invalidate io.lsu.fp_stdata.bits.uop.prs3 invalidate io.lsu.fp_stdata.bits.uop.prs2 invalidate io.lsu.fp_stdata.bits.uop.prs1 invalidate io.lsu.fp_stdata.bits.uop.pdst invalidate io.lsu.fp_stdata.bits.uop.rxq_idx invalidate io.lsu.fp_stdata.bits.uop.stq_idx invalidate io.lsu.fp_stdata.bits.uop.ldq_idx invalidate io.lsu.fp_stdata.bits.uop.rob_idx invalidate io.lsu.fp_stdata.bits.uop.csr_addr invalidate io.lsu.fp_stdata.bits.uop.imm_packed invalidate io.lsu.fp_stdata.bits.uop.taken invalidate io.lsu.fp_stdata.bits.uop.pc_lob invalidate io.lsu.fp_stdata.bits.uop.edge_inst invalidate io.lsu.fp_stdata.bits.uop.ftq_idx invalidate io.lsu.fp_stdata.bits.uop.br_tag invalidate io.lsu.fp_stdata.bits.uop.br_mask invalidate io.lsu.fp_stdata.bits.uop.is_sfb invalidate io.lsu.fp_stdata.bits.uop.is_jal invalidate io.lsu.fp_stdata.bits.uop.is_jalr invalidate io.lsu.fp_stdata.bits.uop.is_br invalidate io.lsu.fp_stdata.bits.uop.iw_p2_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_p1_poisoned invalidate io.lsu.fp_stdata.bits.uop.iw_state invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_std invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_sta invalidate io.lsu.fp_stdata.bits.uop.ctrl.is_load invalidate io.lsu.fp_stdata.bits.uop.ctrl.csr_cmd invalidate io.lsu.fp_stdata.bits.uop.ctrl.fcn_dw invalidate io.lsu.fp_stdata.bits.uop.ctrl.op_fcn invalidate io.lsu.fp_stdata.bits.uop.ctrl.imm_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op2_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.op1_sel invalidate io.lsu.fp_stdata.bits.uop.ctrl.br_type invalidate io.lsu.fp_stdata.bits.uop.fu_code invalidate io.lsu.fp_stdata.bits.uop.iq_type invalidate io.lsu.fp_stdata.bits.uop.debug_pc invalidate io.lsu.fp_stdata.bits.uop.is_rvc invalidate io.lsu.fp_stdata.bits.uop.debug_inst invalidate io.lsu.fp_stdata.bits.uop.inst invalidate io.lsu.fp_stdata.bits.uop.uopc node _io_lsu_commit_valids_0_T = eq(rob_bsy[rob_head], UInt<1>(0h0)) node _io_lsu_commit_valids_0_T_1 = neq(rob_head, rob_tail) node _io_lsu_commit_valids_0_T_2 = and(_io_lsu_commit_valids_0_T, _io_lsu_commit_valids_0_T_1) node _io_lsu_commit_valids_0_T_3 = and(_io_lsu_commit_valids_0_T_2, rob_respd[rob_head]) connect io.lsu.commit.valids[0], _io_lsu_commit_valids_0_T_3 connect io.lsu.commit.uops[0], rob_uop[rob_head] connect io.lsu.commit.rbk_valids[0], UInt<1>(0h0) connect io.lsu.commit.rollback, UInt<1>(0h0) invalidate io.lsu.commit.fflags.bits invalidate io.lsu.commit.fflags.valid when io.lsu.commit.valids[0] : node _rob_head_T = eq(rob_head, UInt<6>(0h3f)) node _rob_head_T_1 = add(rob_head, UInt<1>(0h1)) node _rob_head_T_2 = tail(_rob_head_T_1, 1) node _rob_head_T_3 = mux(_rob_head_T, UInt<1>(0h0), _rob_head_T_2) connect rob_head, _rob_head_T_3 when io.lsu.clr_bsy[0].valid : connect rob_bsy[io.lsu.clr_bsy[0].bits], UInt<1>(0h0) node _T_22 = neq(rob[io.lsu.clr_unsafe[0].bits].cmd, UInt<3>(0h6)) node _T_23 = and(io.lsu.clr_unsafe[0].valid, _T_22) when _T_23 : connect rob_bsy[io.lsu.clr_unsafe[0].bits], UInt<1>(0h0) when io.lsu.exe[0].iresp.valid : connect rob_bsy[io.lsu.exe[0].iresp.bits.uop.rob_idx], UInt<1>(0h0) node _T_24 = eq(io.lsu.lxcpt.valid, UInt<1>(0h0)) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at tracegen.scala:115 assert(!io.lsu.lxcpt.valid)\n") : printf assert(clock, _T_24, UInt<1>(0h1), "") : assert node _io_lsu_exe_0_req_valid_T = and(io.tracegen.req.ready, io.tracegen.req.valid) reg io_lsu_exe_0_req_valid_REG : UInt<1>, clock connect io_lsu_exe_0_req_valid_REG, _io_lsu_exe_0_req_valid_T connect io.lsu.exe[0].req.valid, io_lsu_exe_0_req_valid_REG invalidate io.lsu.exe[0].req.bits.sfence.bits.hg invalidate io.lsu.exe[0].req.bits.sfence.bits.hv invalidate io.lsu.exe[0].req.bits.sfence.bits.asid invalidate io.lsu.exe[0].req.bits.sfence.bits.addr invalidate io.lsu.exe[0].req.bits.sfence.bits.rs2 invalidate io.lsu.exe[0].req.bits.sfence.bits.rs1 invalidate io.lsu.exe[0].req.bits.sfence.valid invalidate io.lsu.exe[0].req.bits.mxcpt.bits invalidate io.lsu.exe[0].req.bits.mxcpt.valid invalidate io.lsu.exe[0].req.bits.addr invalidate io.lsu.exe[0].req.bits.fflags.bits.flags invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.exception invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.taken invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.inst invalidate io.lsu.exe[0].req.bits.fflags.bits.uop.uopc invalidate io.lsu.exe[0].req.bits.fflags.valid invalidate io.lsu.exe[0].req.bits.data invalidate io.lsu.exe[0].req.bits.predicated invalidate io.lsu.exe[0].req.bits.uop.debug_tsrc invalidate io.lsu.exe[0].req.bits.uop.debug_fsrc invalidate io.lsu.exe[0].req.bits.uop.bp_xcpt_if invalidate io.lsu.exe[0].req.bits.uop.bp_debug_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ma_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_ae_if invalidate io.lsu.exe[0].req.bits.uop.xcpt_pf_if invalidate io.lsu.exe[0].req.bits.uop.fp_single invalidate io.lsu.exe[0].req.bits.uop.fp_val invalidate io.lsu.exe[0].req.bits.uop.frs3_en invalidate io.lsu.exe[0].req.bits.uop.lrs2_rtype invalidate io.lsu.exe[0].req.bits.uop.lrs1_rtype invalidate io.lsu.exe[0].req.bits.uop.dst_rtype invalidate io.lsu.exe[0].req.bits.uop.ldst_val invalidate io.lsu.exe[0].req.bits.uop.lrs3 invalidate io.lsu.exe[0].req.bits.uop.lrs2 invalidate io.lsu.exe[0].req.bits.uop.lrs1 invalidate io.lsu.exe[0].req.bits.uop.ldst invalidate io.lsu.exe[0].req.bits.uop.ldst_is_rs1 invalidate io.lsu.exe[0].req.bits.uop.flush_on_commit invalidate io.lsu.exe[0].req.bits.uop.is_unique invalidate io.lsu.exe[0].req.bits.uop.is_sys_pc2epc invalidate io.lsu.exe[0].req.bits.uop.uses_stq invalidate io.lsu.exe[0].req.bits.uop.uses_ldq invalidate io.lsu.exe[0].req.bits.uop.is_amo invalidate io.lsu.exe[0].req.bits.uop.is_fencei invalidate io.lsu.exe[0].req.bits.uop.is_fence invalidate io.lsu.exe[0].req.bits.uop.mem_signed invalidate io.lsu.exe[0].req.bits.uop.mem_size invalidate io.lsu.exe[0].req.bits.uop.mem_cmd invalidate io.lsu.exe[0].req.bits.uop.bypassable invalidate io.lsu.exe[0].req.bits.uop.exc_cause invalidate io.lsu.exe[0].req.bits.uop.exception invalidate io.lsu.exe[0].req.bits.uop.stale_pdst invalidate io.lsu.exe[0].req.bits.uop.ppred_busy invalidate io.lsu.exe[0].req.bits.uop.prs3_busy invalidate io.lsu.exe[0].req.bits.uop.prs2_busy invalidate io.lsu.exe[0].req.bits.uop.prs1_busy invalidate io.lsu.exe[0].req.bits.uop.ppred invalidate io.lsu.exe[0].req.bits.uop.prs3 invalidate io.lsu.exe[0].req.bits.uop.prs2 invalidate io.lsu.exe[0].req.bits.uop.prs1 invalidate io.lsu.exe[0].req.bits.uop.pdst invalidate io.lsu.exe[0].req.bits.uop.rxq_idx invalidate io.lsu.exe[0].req.bits.uop.stq_idx invalidate io.lsu.exe[0].req.bits.uop.ldq_idx invalidate io.lsu.exe[0].req.bits.uop.rob_idx invalidate io.lsu.exe[0].req.bits.uop.csr_addr invalidate io.lsu.exe[0].req.bits.uop.imm_packed invalidate io.lsu.exe[0].req.bits.uop.taken invalidate io.lsu.exe[0].req.bits.uop.pc_lob invalidate io.lsu.exe[0].req.bits.uop.edge_inst invalidate io.lsu.exe[0].req.bits.uop.ftq_idx invalidate io.lsu.exe[0].req.bits.uop.br_tag invalidate io.lsu.exe[0].req.bits.uop.br_mask invalidate io.lsu.exe[0].req.bits.uop.is_sfb invalidate io.lsu.exe[0].req.bits.uop.is_jal invalidate io.lsu.exe[0].req.bits.uop.is_jalr invalidate io.lsu.exe[0].req.bits.uop.is_br invalidate io.lsu.exe[0].req.bits.uop.iw_p2_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_p1_poisoned invalidate io.lsu.exe[0].req.bits.uop.iw_state invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_std invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_sta invalidate io.lsu.exe[0].req.bits.uop.ctrl.is_load invalidate io.lsu.exe[0].req.bits.uop.ctrl.csr_cmd invalidate io.lsu.exe[0].req.bits.uop.ctrl.fcn_dw invalidate io.lsu.exe[0].req.bits.uop.ctrl.op_fcn invalidate io.lsu.exe[0].req.bits.uop.ctrl.imm_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op2_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.op1_sel invalidate io.lsu.exe[0].req.bits.uop.ctrl.br_type invalidate io.lsu.exe[0].req.bits.uop.fu_code invalidate io.lsu.exe[0].req.bits.uop.iq_type invalidate io.lsu.exe[0].req.bits.uop.debug_pc invalidate io.lsu.exe[0].req.bits.uop.is_rvc invalidate io.lsu.exe[0].req.bits.uop.debug_inst invalidate io.lsu.exe[0].req.bits.uop.inst invalidate io.lsu.exe[0].req.bits.uop.uopc reg io_lsu_exe_0_req_bits_uop_REG : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock connect io_lsu_exe_0_req_bits_uop_REG, tracegen_uop connect io.lsu.exe[0].req.bits.uop, io_lsu_exe_0_req_bits_uop_REG reg io_lsu_exe_0_req_bits_addr_REG : UInt, clock connect io_lsu_exe_0_req_bits_addr_REG, io.tracegen.req.bits.addr connect io.lsu.exe[0].req.bits.addr, io_lsu_exe_0_req_bits_addr_REG reg io_lsu_exe_0_req_bits_data_REG : UInt, clock connect io_lsu_exe_0_req_bits_data_REG, io.tracegen.req.bits.data connect io.lsu.exe[0].req.bits.data, io_lsu_exe_0_req_bits_data_REG connect io.tracegen.resp.valid, io.lsu.exe[0].iresp.valid invalidate io.tracegen.resp.bits.store_data invalidate io.tracegen.resp.bits.data_raw invalidate io.tracegen.resp.bits.data_word_bypass invalidate io.tracegen.resp.bits.has_data invalidate io.tracegen.resp.bits.replay invalidate io.tracegen.resp.bits.mask invalidate io.tracegen.resp.bits.data invalidate io.tracegen.resp.bits.dv invalidate io.tracegen.resp.bits.dprv invalidate io.tracegen.resp.bits.signed invalidate io.tracegen.resp.bits.size invalidate io.tracegen.resp.bits.cmd invalidate io.tracegen.resp.bits.tag invalidate io.tracegen.resp.bits.addr connect io.tracegen.resp.bits.tag, io.lsu.exe[0].iresp.bits.uop.uopc connect io.tracegen.resp.bits.size, io.lsu.exe[0].iresp.bits.uop.mem_size connect io.tracegen.resp.bits.data, io.lsu.exe[0].iresp.bits.data node _store_resp_idx_T = eq(rob_respd[0], UInt<1>(0h0)) node _store_resp_idx_T_1 = eq(rob[0].cmd, UInt<1>(0h1)) node _store_resp_idx_T_2 = eq(rob[0].cmd, UInt<5>(0h11)) node _store_resp_idx_T_3 = or(_store_resp_idx_T_1, _store_resp_idx_T_2) node _store_resp_idx_T_4 = eq(rob[0].cmd, UInt<3>(0h7)) node _store_resp_idx_T_5 = or(_store_resp_idx_T_3, _store_resp_idx_T_4) node _store_resp_idx_T_6 = eq(rob[0].cmd, UInt<3>(0h4)) node _store_resp_idx_T_7 = eq(rob[0].cmd, UInt<4>(0h9)) node _store_resp_idx_T_8 = eq(rob[0].cmd, UInt<4>(0ha)) node _store_resp_idx_T_9 = eq(rob[0].cmd, UInt<4>(0hb)) node _store_resp_idx_T_10 = or(_store_resp_idx_T_6, _store_resp_idx_T_7) node _store_resp_idx_T_11 = or(_store_resp_idx_T_10, _store_resp_idx_T_8) node _store_resp_idx_T_12 = or(_store_resp_idx_T_11, _store_resp_idx_T_9) node _store_resp_idx_T_13 = eq(rob[0].cmd, UInt<4>(0h8)) node _store_resp_idx_T_14 = eq(rob[0].cmd, UInt<4>(0hc)) node _store_resp_idx_T_15 = eq(rob[0].cmd, UInt<4>(0hd)) node _store_resp_idx_T_16 = eq(rob[0].cmd, UInt<4>(0he)) node _store_resp_idx_T_17 = eq(rob[0].cmd, UInt<4>(0hf)) node _store_resp_idx_T_18 = or(_store_resp_idx_T_13, _store_resp_idx_T_14) node _store_resp_idx_T_19 = or(_store_resp_idx_T_18, _store_resp_idx_T_15) node _store_resp_idx_T_20 = or(_store_resp_idx_T_19, _store_resp_idx_T_16) node _store_resp_idx_T_21 = or(_store_resp_idx_T_20, _store_resp_idx_T_17) node _store_resp_idx_T_22 = or(_store_resp_idx_T_12, _store_resp_idx_T_21) node _store_resp_idx_T_23 = or(_store_resp_idx_T_5, _store_resp_idx_T_22) node _store_resp_idx_T_24 = and(_store_resp_idx_T, _store_resp_idx_T_23) node _store_resp_idx_T_25 = eq(rob_respd[1], UInt<1>(0h0)) node _store_resp_idx_T_26 = eq(rob[1].cmd, UInt<1>(0h1)) node _store_resp_idx_T_27 = eq(rob[1].cmd, UInt<5>(0h11)) node _store_resp_idx_T_28 = or(_store_resp_idx_T_26, _store_resp_idx_T_27) node _store_resp_idx_T_29 = eq(rob[1].cmd, UInt<3>(0h7)) node _store_resp_idx_T_30 = or(_store_resp_idx_T_28, _store_resp_idx_T_29) node _store_resp_idx_T_31 = eq(rob[1].cmd, UInt<3>(0h4)) node _store_resp_idx_T_32 = eq(rob[1].cmd, UInt<4>(0h9)) node _store_resp_idx_T_33 = eq(rob[1].cmd, UInt<4>(0ha)) node _store_resp_idx_T_34 = eq(rob[1].cmd, UInt<4>(0hb)) node _store_resp_idx_T_35 = or(_store_resp_idx_T_31, _store_resp_idx_T_32) node _store_resp_idx_T_36 = or(_store_resp_idx_T_35, _store_resp_idx_T_33) node _store_resp_idx_T_37 = or(_store_resp_idx_T_36, _store_resp_idx_T_34) node _store_resp_idx_T_38 = eq(rob[1].cmd, UInt<4>(0h8)) node _store_resp_idx_T_39 = eq(rob[1].cmd, UInt<4>(0hc)) node _store_resp_idx_T_40 = eq(rob[1].cmd, UInt<4>(0hd)) node _store_resp_idx_T_41 = eq(rob[1].cmd, UInt<4>(0he)) node _store_resp_idx_T_42 = eq(rob[1].cmd, UInt<4>(0hf)) node _store_resp_idx_T_43 = or(_store_resp_idx_T_38, _store_resp_idx_T_39) node _store_resp_idx_T_44 = or(_store_resp_idx_T_43, _store_resp_idx_T_40) node _store_resp_idx_T_45 = or(_store_resp_idx_T_44, _store_resp_idx_T_41) node _store_resp_idx_T_46 = or(_store_resp_idx_T_45, _store_resp_idx_T_42) node _store_resp_idx_T_47 = or(_store_resp_idx_T_37, _store_resp_idx_T_46) node _store_resp_idx_T_48 = or(_store_resp_idx_T_30, _store_resp_idx_T_47) node _store_resp_idx_T_49 = and(_store_resp_idx_T_25, _store_resp_idx_T_48) node _store_resp_idx_T_50 = eq(rob_respd[2], UInt<1>(0h0)) node _store_resp_idx_T_51 = eq(rob[2].cmd, UInt<1>(0h1)) node _store_resp_idx_T_52 = eq(rob[2].cmd, UInt<5>(0h11)) node _store_resp_idx_T_53 = or(_store_resp_idx_T_51, _store_resp_idx_T_52) node _store_resp_idx_T_54 = eq(rob[2].cmd, UInt<3>(0h7)) node _store_resp_idx_T_55 = or(_store_resp_idx_T_53, _store_resp_idx_T_54) node _store_resp_idx_T_56 = eq(rob[2].cmd, UInt<3>(0h4)) node _store_resp_idx_T_57 = eq(rob[2].cmd, UInt<4>(0h9)) node _store_resp_idx_T_58 = eq(rob[2].cmd, UInt<4>(0ha)) node _store_resp_idx_T_59 = eq(rob[2].cmd, UInt<4>(0hb)) node _store_resp_idx_T_60 = or(_store_resp_idx_T_56, _store_resp_idx_T_57) node _store_resp_idx_T_61 = or(_store_resp_idx_T_60, _store_resp_idx_T_58) node _store_resp_idx_T_62 = or(_store_resp_idx_T_61, _store_resp_idx_T_59) node _store_resp_idx_T_63 = eq(rob[2].cmd, UInt<4>(0h8)) node _store_resp_idx_T_64 = eq(rob[2].cmd, UInt<4>(0hc)) node _store_resp_idx_T_65 = eq(rob[2].cmd, UInt<4>(0hd)) node _store_resp_idx_T_66 = eq(rob[2].cmd, UInt<4>(0he)) node _store_resp_idx_T_67 = eq(rob[2].cmd, UInt<4>(0hf)) node _store_resp_idx_T_68 = or(_store_resp_idx_T_63, _store_resp_idx_T_64) node _store_resp_idx_T_69 = or(_store_resp_idx_T_68, _store_resp_idx_T_65) node _store_resp_idx_T_70 = or(_store_resp_idx_T_69, _store_resp_idx_T_66) node _store_resp_idx_T_71 = or(_store_resp_idx_T_70, _store_resp_idx_T_67) node _store_resp_idx_T_72 = or(_store_resp_idx_T_62, _store_resp_idx_T_71) node _store_resp_idx_T_73 = or(_store_resp_idx_T_55, _store_resp_idx_T_72) node _store_resp_idx_T_74 = and(_store_resp_idx_T_50, _store_resp_idx_T_73) node _store_resp_idx_T_75 = eq(rob_respd[3], UInt<1>(0h0)) node _store_resp_idx_T_76 = eq(rob[3].cmd, UInt<1>(0h1)) node _store_resp_idx_T_77 = eq(rob[3].cmd, UInt<5>(0h11)) node _store_resp_idx_T_78 = or(_store_resp_idx_T_76, _store_resp_idx_T_77) node _store_resp_idx_T_79 = eq(rob[3].cmd, UInt<3>(0h7)) node _store_resp_idx_T_80 = or(_store_resp_idx_T_78, _store_resp_idx_T_79) node _store_resp_idx_T_81 = eq(rob[3].cmd, UInt<3>(0h4)) node _store_resp_idx_T_82 = eq(rob[3].cmd, UInt<4>(0h9)) node _store_resp_idx_T_83 = eq(rob[3].cmd, UInt<4>(0ha)) node _store_resp_idx_T_84 = eq(rob[3].cmd, UInt<4>(0hb)) node _store_resp_idx_T_85 = or(_store_resp_idx_T_81, _store_resp_idx_T_82) node _store_resp_idx_T_86 = or(_store_resp_idx_T_85, _store_resp_idx_T_83) node _store_resp_idx_T_87 = or(_store_resp_idx_T_86, _store_resp_idx_T_84) node _store_resp_idx_T_88 = eq(rob[3].cmd, UInt<4>(0h8)) node _store_resp_idx_T_89 = eq(rob[3].cmd, UInt<4>(0hc)) node _store_resp_idx_T_90 = eq(rob[3].cmd, UInt<4>(0hd)) node _store_resp_idx_T_91 = eq(rob[3].cmd, UInt<4>(0he)) node _store_resp_idx_T_92 = eq(rob[3].cmd, UInt<4>(0hf)) node _store_resp_idx_T_93 = or(_store_resp_idx_T_88, _store_resp_idx_T_89) node _store_resp_idx_T_94 = or(_store_resp_idx_T_93, _store_resp_idx_T_90) node _store_resp_idx_T_95 = or(_store_resp_idx_T_94, _store_resp_idx_T_91) node _store_resp_idx_T_96 = or(_store_resp_idx_T_95, _store_resp_idx_T_92) node _store_resp_idx_T_97 = or(_store_resp_idx_T_87, _store_resp_idx_T_96) node _store_resp_idx_T_98 = or(_store_resp_idx_T_80, _store_resp_idx_T_97) node _store_resp_idx_T_99 = and(_store_resp_idx_T_75, _store_resp_idx_T_98) node _store_resp_idx_T_100 = eq(rob_respd[4], UInt<1>(0h0)) node _store_resp_idx_T_101 = eq(rob[4].cmd, UInt<1>(0h1)) node _store_resp_idx_T_102 = eq(rob[4].cmd, UInt<5>(0h11)) node _store_resp_idx_T_103 = or(_store_resp_idx_T_101, _store_resp_idx_T_102) node _store_resp_idx_T_104 = eq(rob[4].cmd, UInt<3>(0h7)) node _store_resp_idx_T_105 = or(_store_resp_idx_T_103, _store_resp_idx_T_104) node _store_resp_idx_T_106 = eq(rob[4].cmd, UInt<3>(0h4)) node _store_resp_idx_T_107 = eq(rob[4].cmd, UInt<4>(0h9)) node _store_resp_idx_T_108 = eq(rob[4].cmd, UInt<4>(0ha)) node _store_resp_idx_T_109 = eq(rob[4].cmd, UInt<4>(0hb)) node _store_resp_idx_T_110 = or(_store_resp_idx_T_106, _store_resp_idx_T_107) node _store_resp_idx_T_111 = or(_store_resp_idx_T_110, _store_resp_idx_T_108) node _store_resp_idx_T_112 = or(_store_resp_idx_T_111, _store_resp_idx_T_109) node _store_resp_idx_T_113 = eq(rob[4].cmd, UInt<4>(0h8)) node _store_resp_idx_T_114 = eq(rob[4].cmd, UInt<4>(0hc)) node _store_resp_idx_T_115 = eq(rob[4].cmd, UInt<4>(0hd)) node _store_resp_idx_T_116 = eq(rob[4].cmd, UInt<4>(0he)) node _store_resp_idx_T_117 = eq(rob[4].cmd, UInt<4>(0hf)) node _store_resp_idx_T_118 = or(_store_resp_idx_T_113, _store_resp_idx_T_114) node _store_resp_idx_T_119 = or(_store_resp_idx_T_118, _store_resp_idx_T_115) node _store_resp_idx_T_120 = or(_store_resp_idx_T_119, _store_resp_idx_T_116) node _store_resp_idx_T_121 = or(_store_resp_idx_T_120, _store_resp_idx_T_117) node _store_resp_idx_T_122 = or(_store_resp_idx_T_112, _store_resp_idx_T_121) node _store_resp_idx_T_123 = or(_store_resp_idx_T_105, _store_resp_idx_T_122) node _store_resp_idx_T_124 = and(_store_resp_idx_T_100, _store_resp_idx_T_123) node _store_resp_idx_T_125 = eq(rob_respd[5], UInt<1>(0h0)) node _store_resp_idx_T_126 = eq(rob[5].cmd, UInt<1>(0h1)) node _store_resp_idx_T_127 = eq(rob[5].cmd, UInt<5>(0h11)) node _store_resp_idx_T_128 = or(_store_resp_idx_T_126, _store_resp_idx_T_127) node _store_resp_idx_T_129 = eq(rob[5].cmd, UInt<3>(0h7)) node _store_resp_idx_T_130 = or(_store_resp_idx_T_128, _store_resp_idx_T_129) node _store_resp_idx_T_131 = eq(rob[5].cmd, UInt<3>(0h4)) node _store_resp_idx_T_132 = eq(rob[5].cmd, UInt<4>(0h9)) node _store_resp_idx_T_133 = eq(rob[5].cmd, UInt<4>(0ha)) node _store_resp_idx_T_134 = eq(rob[5].cmd, UInt<4>(0hb)) node _store_resp_idx_T_135 = or(_store_resp_idx_T_131, _store_resp_idx_T_132) node _store_resp_idx_T_136 = or(_store_resp_idx_T_135, _store_resp_idx_T_133) node _store_resp_idx_T_137 = or(_store_resp_idx_T_136, _store_resp_idx_T_134) node _store_resp_idx_T_138 = eq(rob[5].cmd, UInt<4>(0h8)) node _store_resp_idx_T_139 = eq(rob[5].cmd, UInt<4>(0hc)) node _store_resp_idx_T_140 = eq(rob[5].cmd, UInt<4>(0hd)) node _store_resp_idx_T_141 = eq(rob[5].cmd, UInt<4>(0he)) node _store_resp_idx_T_142 = eq(rob[5].cmd, UInt<4>(0hf)) node _store_resp_idx_T_143 = or(_store_resp_idx_T_138, _store_resp_idx_T_139) node _store_resp_idx_T_144 = or(_store_resp_idx_T_143, _store_resp_idx_T_140) node _store_resp_idx_T_145 = or(_store_resp_idx_T_144, _store_resp_idx_T_141) node _store_resp_idx_T_146 = or(_store_resp_idx_T_145, _store_resp_idx_T_142) node _store_resp_idx_T_147 = or(_store_resp_idx_T_137, _store_resp_idx_T_146) node _store_resp_idx_T_148 = or(_store_resp_idx_T_130, _store_resp_idx_T_147) node _store_resp_idx_T_149 = and(_store_resp_idx_T_125, _store_resp_idx_T_148) node _store_resp_idx_T_150 = eq(rob_respd[6], UInt<1>(0h0)) node _store_resp_idx_T_151 = eq(rob[6].cmd, UInt<1>(0h1)) node _store_resp_idx_T_152 = eq(rob[6].cmd, UInt<5>(0h11)) node _store_resp_idx_T_153 = or(_store_resp_idx_T_151, _store_resp_idx_T_152) node _store_resp_idx_T_154 = eq(rob[6].cmd, UInt<3>(0h7)) node _store_resp_idx_T_155 = or(_store_resp_idx_T_153, _store_resp_idx_T_154) node _store_resp_idx_T_156 = eq(rob[6].cmd, UInt<3>(0h4)) node _store_resp_idx_T_157 = eq(rob[6].cmd, UInt<4>(0h9)) node _store_resp_idx_T_158 = eq(rob[6].cmd, UInt<4>(0ha)) node _store_resp_idx_T_159 = eq(rob[6].cmd, UInt<4>(0hb)) node _store_resp_idx_T_160 = or(_store_resp_idx_T_156, _store_resp_idx_T_157) node _store_resp_idx_T_161 = or(_store_resp_idx_T_160, _store_resp_idx_T_158) node _store_resp_idx_T_162 = or(_store_resp_idx_T_161, _store_resp_idx_T_159) node _store_resp_idx_T_163 = eq(rob[6].cmd, UInt<4>(0h8)) node _store_resp_idx_T_164 = eq(rob[6].cmd, UInt<4>(0hc)) node _store_resp_idx_T_165 = eq(rob[6].cmd, UInt<4>(0hd)) node _store_resp_idx_T_166 = eq(rob[6].cmd, UInt<4>(0he)) node _store_resp_idx_T_167 = eq(rob[6].cmd, UInt<4>(0hf)) node _store_resp_idx_T_168 = or(_store_resp_idx_T_163, _store_resp_idx_T_164) node _store_resp_idx_T_169 = or(_store_resp_idx_T_168, _store_resp_idx_T_165) node _store_resp_idx_T_170 = or(_store_resp_idx_T_169, _store_resp_idx_T_166) node _store_resp_idx_T_171 = or(_store_resp_idx_T_170, _store_resp_idx_T_167) node _store_resp_idx_T_172 = or(_store_resp_idx_T_162, _store_resp_idx_T_171) node _store_resp_idx_T_173 = or(_store_resp_idx_T_155, _store_resp_idx_T_172) node _store_resp_idx_T_174 = and(_store_resp_idx_T_150, _store_resp_idx_T_173) node _store_resp_idx_T_175 = eq(rob_respd[7], UInt<1>(0h0)) node _store_resp_idx_T_176 = eq(rob[7].cmd, UInt<1>(0h1)) node _store_resp_idx_T_177 = eq(rob[7].cmd, UInt<5>(0h11)) node _store_resp_idx_T_178 = or(_store_resp_idx_T_176, _store_resp_idx_T_177) node _store_resp_idx_T_179 = eq(rob[7].cmd, UInt<3>(0h7)) node _store_resp_idx_T_180 = or(_store_resp_idx_T_178, _store_resp_idx_T_179) node _store_resp_idx_T_181 = eq(rob[7].cmd, UInt<3>(0h4)) node _store_resp_idx_T_182 = eq(rob[7].cmd, UInt<4>(0h9)) node _store_resp_idx_T_183 = eq(rob[7].cmd, UInt<4>(0ha)) node _store_resp_idx_T_184 = eq(rob[7].cmd, UInt<4>(0hb)) node _store_resp_idx_T_185 = or(_store_resp_idx_T_181, _store_resp_idx_T_182) node _store_resp_idx_T_186 = or(_store_resp_idx_T_185, _store_resp_idx_T_183) node _store_resp_idx_T_187 = or(_store_resp_idx_T_186, _store_resp_idx_T_184) node _store_resp_idx_T_188 = eq(rob[7].cmd, UInt<4>(0h8)) node _store_resp_idx_T_189 = eq(rob[7].cmd, UInt<4>(0hc)) node _store_resp_idx_T_190 = eq(rob[7].cmd, UInt<4>(0hd)) node _store_resp_idx_T_191 = eq(rob[7].cmd, UInt<4>(0he)) node _store_resp_idx_T_192 = eq(rob[7].cmd, UInt<4>(0hf)) node _store_resp_idx_T_193 = or(_store_resp_idx_T_188, _store_resp_idx_T_189) node _store_resp_idx_T_194 = or(_store_resp_idx_T_193, _store_resp_idx_T_190) node _store_resp_idx_T_195 = or(_store_resp_idx_T_194, _store_resp_idx_T_191) node _store_resp_idx_T_196 = or(_store_resp_idx_T_195, _store_resp_idx_T_192) node _store_resp_idx_T_197 = or(_store_resp_idx_T_187, _store_resp_idx_T_196) node _store_resp_idx_T_198 = or(_store_resp_idx_T_180, _store_resp_idx_T_197) node _store_resp_idx_T_199 = and(_store_resp_idx_T_175, _store_resp_idx_T_198) node _store_resp_idx_T_200 = eq(rob_respd[8], UInt<1>(0h0)) node _store_resp_idx_T_201 = eq(rob[8].cmd, UInt<1>(0h1)) node _store_resp_idx_T_202 = eq(rob[8].cmd, UInt<5>(0h11)) node _store_resp_idx_T_203 = or(_store_resp_idx_T_201, _store_resp_idx_T_202) node _store_resp_idx_T_204 = eq(rob[8].cmd, UInt<3>(0h7)) node _store_resp_idx_T_205 = or(_store_resp_idx_T_203, _store_resp_idx_T_204) node _store_resp_idx_T_206 = eq(rob[8].cmd, UInt<3>(0h4)) node _store_resp_idx_T_207 = eq(rob[8].cmd, UInt<4>(0h9)) node _store_resp_idx_T_208 = eq(rob[8].cmd, UInt<4>(0ha)) node _store_resp_idx_T_209 = eq(rob[8].cmd, UInt<4>(0hb)) node _store_resp_idx_T_210 = or(_store_resp_idx_T_206, _store_resp_idx_T_207) node _store_resp_idx_T_211 = or(_store_resp_idx_T_210, _store_resp_idx_T_208) node _store_resp_idx_T_212 = or(_store_resp_idx_T_211, _store_resp_idx_T_209) node _store_resp_idx_T_213 = eq(rob[8].cmd, UInt<4>(0h8)) node _store_resp_idx_T_214 = eq(rob[8].cmd, UInt<4>(0hc)) node _store_resp_idx_T_215 = eq(rob[8].cmd, UInt<4>(0hd)) node _store_resp_idx_T_216 = eq(rob[8].cmd, UInt<4>(0he)) node _store_resp_idx_T_217 = eq(rob[8].cmd, UInt<4>(0hf)) node _store_resp_idx_T_218 = or(_store_resp_idx_T_213, _store_resp_idx_T_214) node _store_resp_idx_T_219 = or(_store_resp_idx_T_218, _store_resp_idx_T_215) node _store_resp_idx_T_220 = or(_store_resp_idx_T_219, _store_resp_idx_T_216) node _store_resp_idx_T_221 = or(_store_resp_idx_T_220, _store_resp_idx_T_217) node _store_resp_idx_T_222 = or(_store_resp_idx_T_212, _store_resp_idx_T_221) node _store_resp_idx_T_223 = or(_store_resp_idx_T_205, _store_resp_idx_T_222) node _store_resp_idx_T_224 = and(_store_resp_idx_T_200, _store_resp_idx_T_223) node _store_resp_idx_T_225 = eq(rob_respd[9], UInt<1>(0h0)) node _store_resp_idx_T_226 = eq(rob[9].cmd, UInt<1>(0h1)) node _store_resp_idx_T_227 = eq(rob[9].cmd, UInt<5>(0h11)) node _store_resp_idx_T_228 = or(_store_resp_idx_T_226, _store_resp_idx_T_227) node _store_resp_idx_T_229 = eq(rob[9].cmd, UInt<3>(0h7)) node _store_resp_idx_T_230 = or(_store_resp_idx_T_228, _store_resp_idx_T_229) node _store_resp_idx_T_231 = eq(rob[9].cmd, UInt<3>(0h4)) node _store_resp_idx_T_232 = eq(rob[9].cmd, UInt<4>(0h9)) node _store_resp_idx_T_233 = eq(rob[9].cmd, UInt<4>(0ha)) node _store_resp_idx_T_234 = eq(rob[9].cmd, UInt<4>(0hb)) node _store_resp_idx_T_235 = or(_store_resp_idx_T_231, _store_resp_idx_T_232) node _store_resp_idx_T_236 = or(_store_resp_idx_T_235, _store_resp_idx_T_233) node _store_resp_idx_T_237 = or(_store_resp_idx_T_236, _store_resp_idx_T_234) node _store_resp_idx_T_238 = eq(rob[9].cmd, UInt<4>(0h8)) node _store_resp_idx_T_239 = eq(rob[9].cmd, UInt<4>(0hc)) node _store_resp_idx_T_240 = eq(rob[9].cmd, UInt<4>(0hd)) node _store_resp_idx_T_241 = eq(rob[9].cmd, UInt<4>(0he)) node _store_resp_idx_T_242 = eq(rob[9].cmd, UInt<4>(0hf)) node _store_resp_idx_T_243 = or(_store_resp_idx_T_238, _store_resp_idx_T_239) node _store_resp_idx_T_244 = or(_store_resp_idx_T_243, _store_resp_idx_T_240) node _store_resp_idx_T_245 = or(_store_resp_idx_T_244, _store_resp_idx_T_241) node _store_resp_idx_T_246 = or(_store_resp_idx_T_245, _store_resp_idx_T_242) node _store_resp_idx_T_247 = or(_store_resp_idx_T_237, _store_resp_idx_T_246) node _store_resp_idx_T_248 = or(_store_resp_idx_T_230, _store_resp_idx_T_247) node _store_resp_idx_T_249 = and(_store_resp_idx_T_225, _store_resp_idx_T_248) node _store_resp_idx_T_250 = eq(rob_respd[10], UInt<1>(0h0)) node _store_resp_idx_T_251 = eq(rob[10].cmd, UInt<1>(0h1)) node _store_resp_idx_T_252 = eq(rob[10].cmd, UInt<5>(0h11)) node _store_resp_idx_T_253 = or(_store_resp_idx_T_251, _store_resp_idx_T_252) node _store_resp_idx_T_254 = eq(rob[10].cmd, UInt<3>(0h7)) node _store_resp_idx_T_255 = or(_store_resp_idx_T_253, _store_resp_idx_T_254) node _store_resp_idx_T_256 = eq(rob[10].cmd, UInt<3>(0h4)) node _store_resp_idx_T_257 = eq(rob[10].cmd, UInt<4>(0h9)) node _store_resp_idx_T_258 = eq(rob[10].cmd, UInt<4>(0ha)) node _store_resp_idx_T_259 = eq(rob[10].cmd, UInt<4>(0hb)) node _store_resp_idx_T_260 = or(_store_resp_idx_T_256, _store_resp_idx_T_257) node _store_resp_idx_T_261 = or(_store_resp_idx_T_260, _store_resp_idx_T_258) node _store_resp_idx_T_262 = or(_store_resp_idx_T_261, _store_resp_idx_T_259) node _store_resp_idx_T_263 = eq(rob[10].cmd, UInt<4>(0h8)) node _store_resp_idx_T_264 = eq(rob[10].cmd, UInt<4>(0hc)) node _store_resp_idx_T_265 = eq(rob[10].cmd, UInt<4>(0hd)) node _store_resp_idx_T_266 = eq(rob[10].cmd, UInt<4>(0he)) node _store_resp_idx_T_267 = eq(rob[10].cmd, UInt<4>(0hf)) node _store_resp_idx_T_268 = or(_store_resp_idx_T_263, _store_resp_idx_T_264) node _store_resp_idx_T_269 = or(_store_resp_idx_T_268, _store_resp_idx_T_265) node _store_resp_idx_T_270 = or(_store_resp_idx_T_269, _store_resp_idx_T_266) node _store_resp_idx_T_271 = or(_store_resp_idx_T_270, _store_resp_idx_T_267) node _store_resp_idx_T_272 = or(_store_resp_idx_T_262, _store_resp_idx_T_271) node _store_resp_idx_T_273 = or(_store_resp_idx_T_255, _store_resp_idx_T_272) node _store_resp_idx_T_274 = and(_store_resp_idx_T_250, _store_resp_idx_T_273) node _store_resp_idx_T_275 = eq(rob_respd[11], UInt<1>(0h0)) node _store_resp_idx_T_276 = eq(rob[11].cmd, UInt<1>(0h1)) node _store_resp_idx_T_277 = eq(rob[11].cmd, UInt<5>(0h11)) node _store_resp_idx_T_278 = or(_store_resp_idx_T_276, _store_resp_idx_T_277) node _store_resp_idx_T_279 = eq(rob[11].cmd, UInt<3>(0h7)) node _store_resp_idx_T_280 = or(_store_resp_idx_T_278, _store_resp_idx_T_279) node _store_resp_idx_T_281 = eq(rob[11].cmd, UInt<3>(0h4)) node _store_resp_idx_T_282 = eq(rob[11].cmd, UInt<4>(0h9)) node _store_resp_idx_T_283 = eq(rob[11].cmd, UInt<4>(0ha)) node _store_resp_idx_T_284 = eq(rob[11].cmd, UInt<4>(0hb)) node _store_resp_idx_T_285 = or(_store_resp_idx_T_281, _store_resp_idx_T_282) node _store_resp_idx_T_286 = or(_store_resp_idx_T_285, _store_resp_idx_T_283) node _store_resp_idx_T_287 = or(_store_resp_idx_T_286, _store_resp_idx_T_284) node _store_resp_idx_T_288 = eq(rob[11].cmd, UInt<4>(0h8)) node _store_resp_idx_T_289 = eq(rob[11].cmd, UInt<4>(0hc)) node _store_resp_idx_T_290 = eq(rob[11].cmd, UInt<4>(0hd)) node _store_resp_idx_T_291 = eq(rob[11].cmd, UInt<4>(0he)) node _store_resp_idx_T_292 = eq(rob[11].cmd, UInt<4>(0hf)) node _store_resp_idx_T_293 = or(_store_resp_idx_T_288, _store_resp_idx_T_289) node _store_resp_idx_T_294 = or(_store_resp_idx_T_293, _store_resp_idx_T_290) node _store_resp_idx_T_295 = or(_store_resp_idx_T_294, _store_resp_idx_T_291) node _store_resp_idx_T_296 = or(_store_resp_idx_T_295, _store_resp_idx_T_292) node _store_resp_idx_T_297 = or(_store_resp_idx_T_287, _store_resp_idx_T_296) node _store_resp_idx_T_298 = or(_store_resp_idx_T_280, _store_resp_idx_T_297) node _store_resp_idx_T_299 = and(_store_resp_idx_T_275, _store_resp_idx_T_298) node _store_resp_idx_T_300 = eq(rob_respd[12], UInt<1>(0h0)) node _store_resp_idx_T_301 = eq(rob[12].cmd, UInt<1>(0h1)) node _store_resp_idx_T_302 = eq(rob[12].cmd, UInt<5>(0h11)) node _store_resp_idx_T_303 = or(_store_resp_idx_T_301, _store_resp_idx_T_302) node _store_resp_idx_T_304 = eq(rob[12].cmd, UInt<3>(0h7)) node _store_resp_idx_T_305 = or(_store_resp_idx_T_303, _store_resp_idx_T_304) node _store_resp_idx_T_306 = eq(rob[12].cmd, UInt<3>(0h4)) node _store_resp_idx_T_307 = eq(rob[12].cmd, UInt<4>(0h9)) node _store_resp_idx_T_308 = eq(rob[12].cmd, UInt<4>(0ha)) node _store_resp_idx_T_309 = eq(rob[12].cmd, UInt<4>(0hb)) node _store_resp_idx_T_310 = or(_store_resp_idx_T_306, _store_resp_idx_T_307) node _store_resp_idx_T_311 = or(_store_resp_idx_T_310, _store_resp_idx_T_308) node _store_resp_idx_T_312 = or(_store_resp_idx_T_311, _store_resp_idx_T_309) node _store_resp_idx_T_313 = eq(rob[12].cmd, UInt<4>(0h8)) node _store_resp_idx_T_314 = eq(rob[12].cmd, UInt<4>(0hc)) node _store_resp_idx_T_315 = eq(rob[12].cmd, UInt<4>(0hd)) node _store_resp_idx_T_316 = eq(rob[12].cmd, UInt<4>(0he)) node _store_resp_idx_T_317 = eq(rob[12].cmd, UInt<4>(0hf)) node _store_resp_idx_T_318 = or(_store_resp_idx_T_313, _store_resp_idx_T_314) node _store_resp_idx_T_319 = or(_store_resp_idx_T_318, _store_resp_idx_T_315) node _store_resp_idx_T_320 = or(_store_resp_idx_T_319, _store_resp_idx_T_316) node _store_resp_idx_T_321 = or(_store_resp_idx_T_320, _store_resp_idx_T_317) node _store_resp_idx_T_322 = or(_store_resp_idx_T_312, _store_resp_idx_T_321) node _store_resp_idx_T_323 = or(_store_resp_idx_T_305, _store_resp_idx_T_322) node _store_resp_idx_T_324 = and(_store_resp_idx_T_300, _store_resp_idx_T_323) node _store_resp_idx_T_325 = eq(rob_respd[13], UInt<1>(0h0)) node _store_resp_idx_T_326 = eq(rob[13].cmd, UInt<1>(0h1)) node _store_resp_idx_T_327 = eq(rob[13].cmd, UInt<5>(0h11)) node _store_resp_idx_T_328 = or(_store_resp_idx_T_326, _store_resp_idx_T_327) node _store_resp_idx_T_329 = eq(rob[13].cmd, UInt<3>(0h7)) node _store_resp_idx_T_330 = or(_store_resp_idx_T_328, _store_resp_idx_T_329) node _store_resp_idx_T_331 = eq(rob[13].cmd, UInt<3>(0h4)) node _store_resp_idx_T_332 = eq(rob[13].cmd, UInt<4>(0h9)) node _store_resp_idx_T_333 = eq(rob[13].cmd, UInt<4>(0ha)) node _store_resp_idx_T_334 = eq(rob[13].cmd, UInt<4>(0hb)) node _store_resp_idx_T_335 = or(_store_resp_idx_T_331, _store_resp_idx_T_332) node _store_resp_idx_T_336 = or(_store_resp_idx_T_335, _store_resp_idx_T_333) node _store_resp_idx_T_337 = or(_store_resp_idx_T_336, _store_resp_idx_T_334) node _store_resp_idx_T_338 = eq(rob[13].cmd, UInt<4>(0h8)) node _store_resp_idx_T_339 = eq(rob[13].cmd, UInt<4>(0hc)) node _store_resp_idx_T_340 = eq(rob[13].cmd, UInt<4>(0hd)) node _store_resp_idx_T_341 = eq(rob[13].cmd, UInt<4>(0he)) node _store_resp_idx_T_342 = eq(rob[13].cmd, UInt<4>(0hf)) node _store_resp_idx_T_343 = or(_store_resp_idx_T_338, _store_resp_idx_T_339) node _store_resp_idx_T_344 = or(_store_resp_idx_T_343, _store_resp_idx_T_340) node _store_resp_idx_T_345 = or(_store_resp_idx_T_344, _store_resp_idx_T_341) node _store_resp_idx_T_346 = or(_store_resp_idx_T_345, _store_resp_idx_T_342) node _store_resp_idx_T_347 = or(_store_resp_idx_T_337, _store_resp_idx_T_346) node _store_resp_idx_T_348 = or(_store_resp_idx_T_330, _store_resp_idx_T_347) node _store_resp_idx_T_349 = and(_store_resp_idx_T_325, _store_resp_idx_T_348) node _store_resp_idx_T_350 = eq(rob_respd[14], UInt<1>(0h0)) node _store_resp_idx_T_351 = eq(rob[14].cmd, UInt<1>(0h1)) node _store_resp_idx_T_352 = eq(rob[14].cmd, UInt<5>(0h11)) node _store_resp_idx_T_353 = or(_store_resp_idx_T_351, _store_resp_idx_T_352) node _store_resp_idx_T_354 = eq(rob[14].cmd, UInt<3>(0h7)) node _store_resp_idx_T_355 = or(_store_resp_idx_T_353, _store_resp_idx_T_354) node _store_resp_idx_T_356 = eq(rob[14].cmd, UInt<3>(0h4)) node _store_resp_idx_T_357 = eq(rob[14].cmd, UInt<4>(0h9)) node _store_resp_idx_T_358 = eq(rob[14].cmd, UInt<4>(0ha)) node _store_resp_idx_T_359 = eq(rob[14].cmd, UInt<4>(0hb)) node _store_resp_idx_T_360 = or(_store_resp_idx_T_356, _store_resp_idx_T_357) node _store_resp_idx_T_361 = or(_store_resp_idx_T_360, _store_resp_idx_T_358) node _store_resp_idx_T_362 = or(_store_resp_idx_T_361, _store_resp_idx_T_359) node _store_resp_idx_T_363 = eq(rob[14].cmd, UInt<4>(0h8)) node _store_resp_idx_T_364 = eq(rob[14].cmd, UInt<4>(0hc)) node _store_resp_idx_T_365 = eq(rob[14].cmd, UInt<4>(0hd)) node _store_resp_idx_T_366 = eq(rob[14].cmd, UInt<4>(0he)) node _store_resp_idx_T_367 = eq(rob[14].cmd, UInt<4>(0hf)) node _store_resp_idx_T_368 = or(_store_resp_idx_T_363, _store_resp_idx_T_364) node _store_resp_idx_T_369 = or(_store_resp_idx_T_368, _store_resp_idx_T_365) node _store_resp_idx_T_370 = or(_store_resp_idx_T_369, _store_resp_idx_T_366) node _store_resp_idx_T_371 = or(_store_resp_idx_T_370, _store_resp_idx_T_367) node _store_resp_idx_T_372 = or(_store_resp_idx_T_362, _store_resp_idx_T_371) node _store_resp_idx_T_373 = or(_store_resp_idx_T_355, _store_resp_idx_T_372) node _store_resp_idx_T_374 = and(_store_resp_idx_T_350, _store_resp_idx_T_373) node _store_resp_idx_T_375 = eq(rob_respd[15], UInt<1>(0h0)) node _store_resp_idx_T_376 = eq(rob[15].cmd, UInt<1>(0h1)) node _store_resp_idx_T_377 = eq(rob[15].cmd, UInt<5>(0h11)) node _store_resp_idx_T_378 = or(_store_resp_idx_T_376, _store_resp_idx_T_377) node _store_resp_idx_T_379 = eq(rob[15].cmd, UInt<3>(0h7)) node _store_resp_idx_T_380 = or(_store_resp_idx_T_378, _store_resp_idx_T_379) node _store_resp_idx_T_381 = eq(rob[15].cmd, UInt<3>(0h4)) node _store_resp_idx_T_382 = eq(rob[15].cmd, UInt<4>(0h9)) node _store_resp_idx_T_383 = eq(rob[15].cmd, UInt<4>(0ha)) node _store_resp_idx_T_384 = eq(rob[15].cmd, UInt<4>(0hb)) node _store_resp_idx_T_385 = or(_store_resp_idx_T_381, _store_resp_idx_T_382) node _store_resp_idx_T_386 = or(_store_resp_idx_T_385, _store_resp_idx_T_383) node _store_resp_idx_T_387 = or(_store_resp_idx_T_386, _store_resp_idx_T_384) node _store_resp_idx_T_388 = eq(rob[15].cmd, UInt<4>(0h8)) node _store_resp_idx_T_389 = eq(rob[15].cmd, UInt<4>(0hc)) node _store_resp_idx_T_390 = eq(rob[15].cmd, UInt<4>(0hd)) node _store_resp_idx_T_391 = eq(rob[15].cmd, UInt<4>(0he)) node _store_resp_idx_T_392 = eq(rob[15].cmd, UInt<4>(0hf)) node _store_resp_idx_T_393 = or(_store_resp_idx_T_388, _store_resp_idx_T_389) node _store_resp_idx_T_394 = or(_store_resp_idx_T_393, _store_resp_idx_T_390) node _store_resp_idx_T_395 = or(_store_resp_idx_T_394, _store_resp_idx_T_391) node _store_resp_idx_T_396 = or(_store_resp_idx_T_395, _store_resp_idx_T_392) node _store_resp_idx_T_397 = or(_store_resp_idx_T_387, _store_resp_idx_T_396) node _store_resp_idx_T_398 = or(_store_resp_idx_T_380, _store_resp_idx_T_397) node _store_resp_idx_T_399 = and(_store_resp_idx_T_375, _store_resp_idx_T_398) node _store_resp_idx_T_400 = eq(rob_respd[16], UInt<1>(0h0)) node _store_resp_idx_T_401 = eq(rob[16].cmd, UInt<1>(0h1)) node _store_resp_idx_T_402 = eq(rob[16].cmd, UInt<5>(0h11)) node _store_resp_idx_T_403 = or(_store_resp_idx_T_401, _store_resp_idx_T_402) node _store_resp_idx_T_404 = eq(rob[16].cmd, UInt<3>(0h7)) node _store_resp_idx_T_405 = or(_store_resp_idx_T_403, _store_resp_idx_T_404) node _store_resp_idx_T_406 = eq(rob[16].cmd, UInt<3>(0h4)) node _store_resp_idx_T_407 = eq(rob[16].cmd, UInt<4>(0h9)) node _store_resp_idx_T_408 = eq(rob[16].cmd, UInt<4>(0ha)) node _store_resp_idx_T_409 = eq(rob[16].cmd, UInt<4>(0hb)) node _store_resp_idx_T_410 = or(_store_resp_idx_T_406, _store_resp_idx_T_407) node _store_resp_idx_T_411 = or(_store_resp_idx_T_410, _store_resp_idx_T_408) node _store_resp_idx_T_412 = or(_store_resp_idx_T_411, _store_resp_idx_T_409) node _store_resp_idx_T_413 = eq(rob[16].cmd, UInt<4>(0h8)) node _store_resp_idx_T_414 = eq(rob[16].cmd, UInt<4>(0hc)) node _store_resp_idx_T_415 = eq(rob[16].cmd, UInt<4>(0hd)) node _store_resp_idx_T_416 = eq(rob[16].cmd, UInt<4>(0he)) node _store_resp_idx_T_417 = eq(rob[16].cmd, UInt<4>(0hf)) node _store_resp_idx_T_418 = or(_store_resp_idx_T_413, _store_resp_idx_T_414) node _store_resp_idx_T_419 = or(_store_resp_idx_T_418, _store_resp_idx_T_415) node _store_resp_idx_T_420 = or(_store_resp_idx_T_419, _store_resp_idx_T_416) node _store_resp_idx_T_421 = or(_store_resp_idx_T_420, _store_resp_idx_T_417) node _store_resp_idx_T_422 = or(_store_resp_idx_T_412, _store_resp_idx_T_421) node _store_resp_idx_T_423 = or(_store_resp_idx_T_405, _store_resp_idx_T_422) node _store_resp_idx_T_424 = and(_store_resp_idx_T_400, _store_resp_idx_T_423) node _store_resp_idx_T_425 = eq(rob_respd[17], UInt<1>(0h0)) node _store_resp_idx_T_426 = eq(rob[17].cmd, UInt<1>(0h1)) node _store_resp_idx_T_427 = eq(rob[17].cmd, UInt<5>(0h11)) node _store_resp_idx_T_428 = or(_store_resp_idx_T_426, _store_resp_idx_T_427) node _store_resp_idx_T_429 = eq(rob[17].cmd, UInt<3>(0h7)) node _store_resp_idx_T_430 = or(_store_resp_idx_T_428, _store_resp_idx_T_429) node _store_resp_idx_T_431 = eq(rob[17].cmd, UInt<3>(0h4)) node _store_resp_idx_T_432 = eq(rob[17].cmd, UInt<4>(0h9)) node _store_resp_idx_T_433 = eq(rob[17].cmd, UInt<4>(0ha)) node _store_resp_idx_T_434 = eq(rob[17].cmd, UInt<4>(0hb)) node _store_resp_idx_T_435 = or(_store_resp_idx_T_431, _store_resp_idx_T_432) node _store_resp_idx_T_436 = or(_store_resp_idx_T_435, _store_resp_idx_T_433) node _store_resp_idx_T_437 = or(_store_resp_idx_T_436, _store_resp_idx_T_434) node _store_resp_idx_T_438 = eq(rob[17].cmd, UInt<4>(0h8)) node _store_resp_idx_T_439 = eq(rob[17].cmd, UInt<4>(0hc)) node _store_resp_idx_T_440 = eq(rob[17].cmd, UInt<4>(0hd)) node _store_resp_idx_T_441 = eq(rob[17].cmd, UInt<4>(0he)) node _store_resp_idx_T_442 = eq(rob[17].cmd, UInt<4>(0hf)) node _store_resp_idx_T_443 = or(_store_resp_idx_T_438, _store_resp_idx_T_439) node _store_resp_idx_T_444 = or(_store_resp_idx_T_443, _store_resp_idx_T_440) node _store_resp_idx_T_445 = or(_store_resp_idx_T_444, _store_resp_idx_T_441) node _store_resp_idx_T_446 = or(_store_resp_idx_T_445, _store_resp_idx_T_442) node _store_resp_idx_T_447 = or(_store_resp_idx_T_437, _store_resp_idx_T_446) node _store_resp_idx_T_448 = or(_store_resp_idx_T_430, _store_resp_idx_T_447) node _store_resp_idx_T_449 = and(_store_resp_idx_T_425, _store_resp_idx_T_448) node _store_resp_idx_T_450 = eq(rob_respd[18], UInt<1>(0h0)) node _store_resp_idx_T_451 = eq(rob[18].cmd, UInt<1>(0h1)) node _store_resp_idx_T_452 = eq(rob[18].cmd, UInt<5>(0h11)) node _store_resp_idx_T_453 = or(_store_resp_idx_T_451, _store_resp_idx_T_452) node _store_resp_idx_T_454 = eq(rob[18].cmd, UInt<3>(0h7)) node _store_resp_idx_T_455 = or(_store_resp_idx_T_453, _store_resp_idx_T_454) node _store_resp_idx_T_456 = eq(rob[18].cmd, UInt<3>(0h4)) node _store_resp_idx_T_457 = eq(rob[18].cmd, UInt<4>(0h9)) node _store_resp_idx_T_458 = eq(rob[18].cmd, UInt<4>(0ha)) node _store_resp_idx_T_459 = eq(rob[18].cmd, UInt<4>(0hb)) node _store_resp_idx_T_460 = or(_store_resp_idx_T_456, _store_resp_idx_T_457) node _store_resp_idx_T_461 = or(_store_resp_idx_T_460, _store_resp_idx_T_458) node _store_resp_idx_T_462 = or(_store_resp_idx_T_461, _store_resp_idx_T_459) node _store_resp_idx_T_463 = eq(rob[18].cmd, UInt<4>(0h8)) node _store_resp_idx_T_464 = eq(rob[18].cmd, UInt<4>(0hc)) node _store_resp_idx_T_465 = eq(rob[18].cmd, UInt<4>(0hd)) node _store_resp_idx_T_466 = eq(rob[18].cmd, UInt<4>(0he)) node _store_resp_idx_T_467 = eq(rob[18].cmd, UInt<4>(0hf)) node _store_resp_idx_T_468 = or(_store_resp_idx_T_463, _store_resp_idx_T_464) node _store_resp_idx_T_469 = or(_store_resp_idx_T_468, _store_resp_idx_T_465) node _store_resp_idx_T_470 = or(_store_resp_idx_T_469, _store_resp_idx_T_466) node _store_resp_idx_T_471 = or(_store_resp_idx_T_470, _store_resp_idx_T_467) node _store_resp_idx_T_472 = or(_store_resp_idx_T_462, _store_resp_idx_T_471) node _store_resp_idx_T_473 = or(_store_resp_idx_T_455, _store_resp_idx_T_472) node _store_resp_idx_T_474 = and(_store_resp_idx_T_450, _store_resp_idx_T_473) node _store_resp_idx_T_475 = eq(rob_respd[19], UInt<1>(0h0)) node _store_resp_idx_T_476 = eq(rob[19].cmd, UInt<1>(0h1)) node _store_resp_idx_T_477 = eq(rob[19].cmd, UInt<5>(0h11)) node _store_resp_idx_T_478 = or(_store_resp_idx_T_476, _store_resp_idx_T_477) node _store_resp_idx_T_479 = eq(rob[19].cmd, UInt<3>(0h7)) node _store_resp_idx_T_480 = or(_store_resp_idx_T_478, _store_resp_idx_T_479) node _store_resp_idx_T_481 = eq(rob[19].cmd, UInt<3>(0h4)) node _store_resp_idx_T_482 = eq(rob[19].cmd, UInt<4>(0h9)) node _store_resp_idx_T_483 = eq(rob[19].cmd, UInt<4>(0ha)) node _store_resp_idx_T_484 = eq(rob[19].cmd, UInt<4>(0hb)) node _store_resp_idx_T_485 = or(_store_resp_idx_T_481, _store_resp_idx_T_482) node _store_resp_idx_T_486 = or(_store_resp_idx_T_485, _store_resp_idx_T_483) node _store_resp_idx_T_487 = or(_store_resp_idx_T_486, _store_resp_idx_T_484) node _store_resp_idx_T_488 = eq(rob[19].cmd, UInt<4>(0h8)) node _store_resp_idx_T_489 = eq(rob[19].cmd, UInt<4>(0hc)) node _store_resp_idx_T_490 = eq(rob[19].cmd, UInt<4>(0hd)) node _store_resp_idx_T_491 = eq(rob[19].cmd, UInt<4>(0he)) node _store_resp_idx_T_492 = eq(rob[19].cmd, UInt<4>(0hf)) node _store_resp_idx_T_493 = or(_store_resp_idx_T_488, _store_resp_idx_T_489) node _store_resp_idx_T_494 = or(_store_resp_idx_T_493, _store_resp_idx_T_490) node _store_resp_idx_T_495 = or(_store_resp_idx_T_494, _store_resp_idx_T_491) node _store_resp_idx_T_496 = or(_store_resp_idx_T_495, _store_resp_idx_T_492) node _store_resp_idx_T_497 = or(_store_resp_idx_T_487, _store_resp_idx_T_496) node _store_resp_idx_T_498 = or(_store_resp_idx_T_480, _store_resp_idx_T_497) node _store_resp_idx_T_499 = and(_store_resp_idx_T_475, _store_resp_idx_T_498) node _store_resp_idx_T_500 = eq(rob_respd[20], UInt<1>(0h0)) node _store_resp_idx_T_501 = eq(rob[20].cmd, UInt<1>(0h1)) node _store_resp_idx_T_502 = eq(rob[20].cmd, UInt<5>(0h11)) node _store_resp_idx_T_503 = or(_store_resp_idx_T_501, _store_resp_idx_T_502) node _store_resp_idx_T_504 = eq(rob[20].cmd, UInt<3>(0h7)) node _store_resp_idx_T_505 = or(_store_resp_idx_T_503, _store_resp_idx_T_504) node _store_resp_idx_T_506 = eq(rob[20].cmd, UInt<3>(0h4)) node _store_resp_idx_T_507 = eq(rob[20].cmd, UInt<4>(0h9)) node _store_resp_idx_T_508 = eq(rob[20].cmd, UInt<4>(0ha)) node _store_resp_idx_T_509 = eq(rob[20].cmd, UInt<4>(0hb)) node _store_resp_idx_T_510 = or(_store_resp_idx_T_506, _store_resp_idx_T_507) node _store_resp_idx_T_511 = or(_store_resp_idx_T_510, _store_resp_idx_T_508) node _store_resp_idx_T_512 = or(_store_resp_idx_T_511, _store_resp_idx_T_509) node _store_resp_idx_T_513 = eq(rob[20].cmd, UInt<4>(0h8)) node _store_resp_idx_T_514 = eq(rob[20].cmd, UInt<4>(0hc)) node _store_resp_idx_T_515 = eq(rob[20].cmd, UInt<4>(0hd)) node _store_resp_idx_T_516 = eq(rob[20].cmd, UInt<4>(0he)) node _store_resp_idx_T_517 = eq(rob[20].cmd, UInt<4>(0hf)) node _store_resp_idx_T_518 = or(_store_resp_idx_T_513, _store_resp_idx_T_514) node _store_resp_idx_T_519 = or(_store_resp_idx_T_518, _store_resp_idx_T_515) node _store_resp_idx_T_520 = or(_store_resp_idx_T_519, _store_resp_idx_T_516) node _store_resp_idx_T_521 = or(_store_resp_idx_T_520, _store_resp_idx_T_517) node _store_resp_idx_T_522 = or(_store_resp_idx_T_512, _store_resp_idx_T_521) node _store_resp_idx_T_523 = or(_store_resp_idx_T_505, _store_resp_idx_T_522) node _store_resp_idx_T_524 = and(_store_resp_idx_T_500, _store_resp_idx_T_523) node _store_resp_idx_T_525 = eq(rob_respd[21], UInt<1>(0h0)) node _store_resp_idx_T_526 = eq(rob[21].cmd, UInt<1>(0h1)) node _store_resp_idx_T_527 = eq(rob[21].cmd, UInt<5>(0h11)) node _store_resp_idx_T_528 = or(_store_resp_idx_T_526, _store_resp_idx_T_527) node _store_resp_idx_T_529 = eq(rob[21].cmd, UInt<3>(0h7)) node _store_resp_idx_T_530 = or(_store_resp_idx_T_528, _store_resp_idx_T_529) node _store_resp_idx_T_531 = eq(rob[21].cmd, UInt<3>(0h4)) node _store_resp_idx_T_532 = eq(rob[21].cmd, UInt<4>(0h9)) node _store_resp_idx_T_533 = eq(rob[21].cmd, UInt<4>(0ha)) node _store_resp_idx_T_534 = eq(rob[21].cmd, UInt<4>(0hb)) node _store_resp_idx_T_535 = or(_store_resp_idx_T_531, _store_resp_idx_T_532) node _store_resp_idx_T_536 = or(_store_resp_idx_T_535, _store_resp_idx_T_533) node _store_resp_idx_T_537 = or(_store_resp_idx_T_536, _store_resp_idx_T_534) node _store_resp_idx_T_538 = eq(rob[21].cmd, UInt<4>(0h8)) node _store_resp_idx_T_539 = eq(rob[21].cmd, UInt<4>(0hc)) node _store_resp_idx_T_540 = eq(rob[21].cmd, UInt<4>(0hd)) node _store_resp_idx_T_541 = eq(rob[21].cmd, UInt<4>(0he)) node _store_resp_idx_T_542 = eq(rob[21].cmd, UInt<4>(0hf)) node _store_resp_idx_T_543 = or(_store_resp_idx_T_538, _store_resp_idx_T_539) node _store_resp_idx_T_544 = or(_store_resp_idx_T_543, _store_resp_idx_T_540) node _store_resp_idx_T_545 = or(_store_resp_idx_T_544, _store_resp_idx_T_541) node _store_resp_idx_T_546 = or(_store_resp_idx_T_545, _store_resp_idx_T_542) node _store_resp_idx_T_547 = or(_store_resp_idx_T_537, _store_resp_idx_T_546) node _store_resp_idx_T_548 = or(_store_resp_idx_T_530, _store_resp_idx_T_547) node _store_resp_idx_T_549 = and(_store_resp_idx_T_525, _store_resp_idx_T_548) node _store_resp_idx_T_550 = eq(rob_respd[22], UInt<1>(0h0)) node _store_resp_idx_T_551 = eq(rob[22].cmd, UInt<1>(0h1)) node _store_resp_idx_T_552 = eq(rob[22].cmd, UInt<5>(0h11)) node _store_resp_idx_T_553 = or(_store_resp_idx_T_551, _store_resp_idx_T_552) node _store_resp_idx_T_554 = eq(rob[22].cmd, UInt<3>(0h7)) node _store_resp_idx_T_555 = or(_store_resp_idx_T_553, _store_resp_idx_T_554) node _store_resp_idx_T_556 = eq(rob[22].cmd, UInt<3>(0h4)) node _store_resp_idx_T_557 = eq(rob[22].cmd, UInt<4>(0h9)) node _store_resp_idx_T_558 = eq(rob[22].cmd, UInt<4>(0ha)) node _store_resp_idx_T_559 = eq(rob[22].cmd, UInt<4>(0hb)) node _store_resp_idx_T_560 = or(_store_resp_idx_T_556, _store_resp_idx_T_557) node _store_resp_idx_T_561 = or(_store_resp_idx_T_560, _store_resp_idx_T_558) node _store_resp_idx_T_562 = or(_store_resp_idx_T_561, _store_resp_idx_T_559) node _store_resp_idx_T_563 = eq(rob[22].cmd, UInt<4>(0h8)) node _store_resp_idx_T_564 = eq(rob[22].cmd, UInt<4>(0hc)) node _store_resp_idx_T_565 = eq(rob[22].cmd, UInt<4>(0hd)) node _store_resp_idx_T_566 = eq(rob[22].cmd, UInt<4>(0he)) node _store_resp_idx_T_567 = eq(rob[22].cmd, UInt<4>(0hf)) node _store_resp_idx_T_568 = or(_store_resp_idx_T_563, _store_resp_idx_T_564) node _store_resp_idx_T_569 = or(_store_resp_idx_T_568, _store_resp_idx_T_565) node _store_resp_idx_T_570 = or(_store_resp_idx_T_569, _store_resp_idx_T_566) node _store_resp_idx_T_571 = or(_store_resp_idx_T_570, _store_resp_idx_T_567) node _store_resp_idx_T_572 = or(_store_resp_idx_T_562, _store_resp_idx_T_571) node _store_resp_idx_T_573 = or(_store_resp_idx_T_555, _store_resp_idx_T_572) node _store_resp_idx_T_574 = and(_store_resp_idx_T_550, _store_resp_idx_T_573) node _store_resp_idx_T_575 = eq(rob_respd[23], UInt<1>(0h0)) node _store_resp_idx_T_576 = eq(rob[23].cmd, UInt<1>(0h1)) node _store_resp_idx_T_577 = eq(rob[23].cmd, UInt<5>(0h11)) node _store_resp_idx_T_578 = or(_store_resp_idx_T_576, _store_resp_idx_T_577) node _store_resp_idx_T_579 = eq(rob[23].cmd, UInt<3>(0h7)) node _store_resp_idx_T_580 = or(_store_resp_idx_T_578, _store_resp_idx_T_579) node _store_resp_idx_T_581 = eq(rob[23].cmd, UInt<3>(0h4)) node _store_resp_idx_T_582 = eq(rob[23].cmd, UInt<4>(0h9)) node _store_resp_idx_T_583 = eq(rob[23].cmd, UInt<4>(0ha)) node _store_resp_idx_T_584 = eq(rob[23].cmd, UInt<4>(0hb)) node _store_resp_idx_T_585 = or(_store_resp_idx_T_581, _store_resp_idx_T_582) node _store_resp_idx_T_586 = or(_store_resp_idx_T_585, _store_resp_idx_T_583) node _store_resp_idx_T_587 = or(_store_resp_idx_T_586, _store_resp_idx_T_584) node _store_resp_idx_T_588 = eq(rob[23].cmd, UInt<4>(0h8)) node _store_resp_idx_T_589 = eq(rob[23].cmd, UInt<4>(0hc)) node _store_resp_idx_T_590 = eq(rob[23].cmd, UInt<4>(0hd)) node _store_resp_idx_T_591 = eq(rob[23].cmd, UInt<4>(0he)) node _store_resp_idx_T_592 = eq(rob[23].cmd, UInt<4>(0hf)) node _store_resp_idx_T_593 = or(_store_resp_idx_T_588, _store_resp_idx_T_589) node _store_resp_idx_T_594 = or(_store_resp_idx_T_593, _store_resp_idx_T_590) node _store_resp_idx_T_595 = or(_store_resp_idx_T_594, _store_resp_idx_T_591) node _store_resp_idx_T_596 = or(_store_resp_idx_T_595, _store_resp_idx_T_592) node _store_resp_idx_T_597 = or(_store_resp_idx_T_587, _store_resp_idx_T_596) node _store_resp_idx_T_598 = or(_store_resp_idx_T_580, _store_resp_idx_T_597) node _store_resp_idx_T_599 = and(_store_resp_idx_T_575, _store_resp_idx_T_598) node _store_resp_idx_T_600 = eq(rob_respd[24], UInt<1>(0h0)) node _store_resp_idx_T_601 = eq(rob[24].cmd, UInt<1>(0h1)) node _store_resp_idx_T_602 = eq(rob[24].cmd, UInt<5>(0h11)) node _store_resp_idx_T_603 = or(_store_resp_idx_T_601, _store_resp_idx_T_602) node _store_resp_idx_T_604 = eq(rob[24].cmd, UInt<3>(0h7)) node _store_resp_idx_T_605 = or(_store_resp_idx_T_603, _store_resp_idx_T_604) node _store_resp_idx_T_606 = eq(rob[24].cmd, UInt<3>(0h4)) node _store_resp_idx_T_607 = eq(rob[24].cmd, UInt<4>(0h9)) node _store_resp_idx_T_608 = eq(rob[24].cmd, UInt<4>(0ha)) node _store_resp_idx_T_609 = eq(rob[24].cmd, UInt<4>(0hb)) node _store_resp_idx_T_610 = or(_store_resp_idx_T_606, _store_resp_idx_T_607) node _store_resp_idx_T_611 = or(_store_resp_idx_T_610, _store_resp_idx_T_608) node _store_resp_idx_T_612 = or(_store_resp_idx_T_611, _store_resp_idx_T_609) node _store_resp_idx_T_613 = eq(rob[24].cmd, UInt<4>(0h8)) node _store_resp_idx_T_614 = eq(rob[24].cmd, UInt<4>(0hc)) node _store_resp_idx_T_615 = eq(rob[24].cmd, UInt<4>(0hd)) node _store_resp_idx_T_616 = eq(rob[24].cmd, UInt<4>(0he)) node _store_resp_idx_T_617 = eq(rob[24].cmd, UInt<4>(0hf)) node _store_resp_idx_T_618 = or(_store_resp_idx_T_613, _store_resp_idx_T_614) node _store_resp_idx_T_619 = or(_store_resp_idx_T_618, _store_resp_idx_T_615) node _store_resp_idx_T_620 = or(_store_resp_idx_T_619, _store_resp_idx_T_616) node _store_resp_idx_T_621 = or(_store_resp_idx_T_620, _store_resp_idx_T_617) node _store_resp_idx_T_622 = or(_store_resp_idx_T_612, _store_resp_idx_T_621) node _store_resp_idx_T_623 = or(_store_resp_idx_T_605, _store_resp_idx_T_622) node _store_resp_idx_T_624 = and(_store_resp_idx_T_600, _store_resp_idx_T_623) node _store_resp_idx_T_625 = eq(rob_respd[25], UInt<1>(0h0)) node _store_resp_idx_T_626 = eq(rob[25].cmd, UInt<1>(0h1)) node _store_resp_idx_T_627 = eq(rob[25].cmd, UInt<5>(0h11)) node _store_resp_idx_T_628 = or(_store_resp_idx_T_626, _store_resp_idx_T_627) node _store_resp_idx_T_629 = eq(rob[25].cmd, UInt<3>(0h7)) node _store_resp_idx_T_630 = or(_store_resp_idx_T_628, _store_resp_idx_T_629) node _store_resp_idx_T_631 = eq(rob[25].cmd, UInt<3>(0h4)) node _store_resp_idx_T_632 = eq(rob[25].cmd, UInt<4>(0h9)) node _store_resp_idx_T_633 = eq(rob[25].cmd, UInt<4>(0ha)) node _store_resp_idx_T_634 = eq(rob[25].cmd, UInt<4>(0hb)) node _store_resp_idx_T_635 = or(_store_resp_idx_T_631, _store_resp_idx_T_632) node _store_resp_idx_T_636 = or(_store_resp_idx_T_635, _store_resp_idx_T_633) node _store_resp_idx_T_637 = or(_store_resp_idx_T_636, _store_resp_idx_T_634) node _store_resp_idx_T_638 = eq(rob[25].cmd, UInt<4>(0h8)) node _store_resp_idx_T_639 = eq(rob[25].cmd, UInt<4>(0hc)) node _store_resp_idx_T_640 = eq(rob[25].cmd, UInt<4>(0hd)) node _store_resp_idx_T_641 = eq(rob[25].cmd, UInt<4>(0he)) node _store_resp_idx_T_642 = eq(rob[25].cmd, UInt<4>(0hf)) node _store_resp_idx_T_643 = or(_store_resp_idx_T_638, _store_resp_idx_T_639) node _store_resp_idx_T_644 = or(_store_resp_idx_T_643, _store_resp_idx_T_640) node _store_resp_idx_T_645 = or(_store_resp_idx_T_644, _store_resp_idx_T_641) node _store_resp_idx_T_646 = or(_store_resp_idx_T_645, _store_resp_idx_T_642) node _store_resp_idx_T_647 = or(_store_resp_idx_T_637, _store_resp_idx_T_646) node _store_resp_idx_T_648 = or(_store_resp_idx_T_630, _store_resp_idx_T_647) node _store_resp_idx_T_649 = and(_store_resp_idx_T_625, _store_resp_idx_T_648) node _store_resp_idx_T_650 = eq(rob_respd[26], UInt<1>(0h0)) node _store_resp_idx_T_651 = eq(rob[26].cmd, UInt<1>(0h1)) node _store_resp_idx_T_652 = eq(rob[26].cmd, UInt<5>(0h11)) node _store_resp_idx_T_653 = or(_store_resp_idx_T_651, _store_resp_idx_T_652) node _store_resp_idx_T_654 = eq(rob[26].cmd, UInt<3>(0h7)) node _store_resp_idx_T_655 = or(_store_resp_idx_T_653, _store_resp_idx_T_654) node _store_resp_idx_T_656 = eq(rob[26].cmd, UInt<3>(0h4)) node _store_resp_idx_T_657 = eq(rob[26].cmd, UInt<4>(0h9)) node _store_resp_idx_T_658 = eq(rob[26].cmd, UInt<4>(0ha)) node _store_resp_idx_T_659 = eq(rob[26].cmd, UInt<4>(0hb)) node _store_resp_idx_T_660 = or(_store_resp_idx_T_656, _store_resp_idx_T_657) node _store_resp_idx_T_661 = or(_store_resp_idx_T_660, _store_resp_idx_T_658) node _store_resp_idx_T_662 = or(_store_resp_idx_T_661, _store_resp_idx_T_659) node _store_resp_idx_T_663 = eq(rob[26].cmd, UInt<4>(0h8)) node _store_resp_idx_T_664 = eq(rob[26].cmd, UInt<4>(0hc)) node _store_resp_idx_T_665 = eq(rob[26].cmd, UInt<4>(0hd)) node _store_resp_idx_T_666 = eq(rob[26].cmd, UInt<4>(0he)) node _store_resp_idx_T_667 = eq(rob[26].cmd, UInt<4>(0hf)) node _store_resp_idx_T_668 = or(_store_resp_idx_T_663, _store_resp_idx_T_664) node _store_resp_idx_T_669 = or(_store_resp_idx_T_668, _store_resp_idx_T_665) node _store_resp_idx_T_670 = or(_store_resp_idx_T_669, _store_resp_idx_T_666) node _store_resp_idx_T_671 = or(_store_resp_idx_T_670, _store_resp_idx_T_667) node _store_resp_idx_T_672 = or(_store_resp_idx_T_662, _store_resp_idx_T_671) node _store_resp_idx_T_673 = or(_store_resp_idx_T_655, _store_resp_idx_T_672) node _store_resp_idx_T_674 = and(_store_resp_idx_T_650, _store_resp_idx_T_673) node _store_resp_idx_T_675 = eq(rob_respd[27], UInt<1>(0h0)) node _store_resp_idx_T_676 = eq(rob[27].cmd, UInt<1>(0h1)) node _store_resp_idx_T_677 = eq(rob[27].cmd, UInt<5>(0h11)) node _store_resp_idx_T_678 = or(_store_resp_idx_T_676, _store_resp_idx_T_677) node _store_resp_idx_T_679 = eq(rob[27].cmd, UInt<3>(0h7)) node _store_resp_idx_T_680 = or(_store_resp_idx_T_678, _store_resp_idx_T_679) node _store_resp_idx_T_681 = eq(rob[27].cmd, UInt<3>(0h4)) node _store_resp_idx_T_682 = eq(rob[27].cmd, UInt<4>(0h9)) node _store_resp_idx_T_683 = eq(rob[27].cmd, UInt<4>(0ha)) node _store_resp_idx_T_684 = eq(rob[27].cmd, UInt<4>(0hb)) node _store_resp_idx_T_685 = or(_store_resp_idx_T_681, _store_resp_idx_T_682) node _store_resp_idx_T_686 = or(_store_resp_idx_T_685, _store_resp_idx_T_683) node _store_resp_idx_T_687 = or(_store_resp_idx_T_686, _store_resp_idx_T_684) node _store_resp_idx_T_688 = eq(rob[27].cmd, UInt<4>(0h8)) node _store_resp_idx_T_689 = eq(rob[27].cmd, UInt<4>(0hc)) node _store_resp_idx_T_690 = eq(rob[27].cmd, UInt<4>(0hd)) node _store_resp_idx_T_691 = eq(rob[27].cmd, UInt<4>(0he)) node _store_resp_idx_T_692 = eq(rob[27].cmd, UInt<4>(0hf)) node _store_resp_idx_T_693 = or(_store_resp_idx_T_688, _store_resp_idx_T_689) node _store_resp_idx_T_694 = or(_store_resp_idx_T_693, _store_resp_idx_T_690) node _store_resp_idx_T_695 = or(_store_resp_idx_T_694, _store_resp_idx_T_691) node _store_resp_idx_T_696 = or(_store_resp_idx_T_695, _store_resp_idx_T_692) node _store_resp_idx_T_697 = or(_store_resp_idx_T_687, _store_resp_idx_T_696) node _store_resp_idx_T_698 = or(_store_resp_idx_T_680, _store_resp_idx_T_697) node _store_resp_idx_T_699 = and(_store_resp_idx_T_675, _store_resp_idx_T_698) node _store_resp_idx_T_700 = eq(rob_respd[28], UInt<1>(0h0)) node _store_resp_idx_T_701 = eq(rob[28].cmd, UInt<1>(0h1)) node _store_resp_idx_T_702 = eq(rob[28].cmd, UInt<5>(0h11)) node _store_resp_idx_T_703 = or(_store_resp_idx_T_701, _store_resp_idx_T_702) node _store_resp_idx_T_704 = eq(rob[28].cmd, UInt<3>(0h7)) node _store_resp_idx_T_705 = or(_store_resp_idx_T_703, _store_resp_idx_T_704) node _store_resp_idx_T_706 = eq(rob[28].cmd, UInt<3>(0h4)) node _store_resp_idx_T_707 = eq(rob[28].cmd, UInt<4>(0h9)) node _store_resp_idx_T_708 = eq(rob[28].cmd, UInt<4>(0ha)) node _store_resp_idx_T_709 = eq(rob[28].cmd, UInt<4>(0hb)) node _store_resp_idx_T_710 = or(_store_resp_idx_T_706, _store_resp_idx_T_707) node _store_resp_idx_T_711 = or(_store_resp_idx_T_710, _store_resp_idx_T_708) node _store_resp_idx_T_712 = or(_store_resp_idx_T_711, _store_resp_idx_T_709) node _store_resp_idx_T_713 = eq(rob[28].cmd, UInt<4>(0h8)) node _store_resp_idx_T_714 = eq(rob[28].cmd, UInt<4>(0hc)) node _store_resp_idx_T_715 = eq(rob[28].cmd, UInt<4>(0hd)) node _store_resp_idx_T_716 = eq(rob[28].cmd, UInt<4>(0he)) node _store_resp_idx_T_717 = eq(rob[28].cmd, UInt<4>(0hf)) node _store_resp_idx_T_718 = or(_store_resp_idx_T_713, _store_resp_idx_T_714) node _store_resp_idx_T_719 = or(_store_resp_idx_T_718, _store_resp_idx_T_715) node _store_resp_idx_T_720 = or(_store_resp_idx_T_719, _store_resp_idx_T_716) node _store_resp_idx_T_721 = or(_store_resp_idx_T_720, _store_resp_idx_T_717) node _store_resp_idx_T_722 = or(_store_resp_idx_T_712, _store_resp_idx_T_721) node _store_resp_idx_T_723 = or(_store_resp_idx_T_705, _store_resp_idx_T_722) node _store_resp_idx_T_724 = and(_store_resp_idx_T_700, _store_resp_idx_T_723) node _store_resp_idx_T_725 = eq(rob_respd[29], UInt<1>(0h0)) node _store_resp_idx_T_726 = eq(rob[29].cmd, UInt<1>(0h1)) node _store_resp_idx_T_727 = eq(rob[29].cmd, UInt<5>(0h11)) node _store_resp_idx_T_728 = or(_store_resp_idx_T_726, _store_resp_idx_T_727) node _store_resp_idx_T_729 = eq(rob[29].cmd, UInt<3>(0h7)) node _store_resp_idx_T_730 = or(_store_resp_idx_T_728, _store_resp_idx_T_729) node _store_resp_idx_T_731 = eq(rob[29].cmd, UInt<3>(0h4)) node _store_resp_idx_T_732 = eq(rob[29].cmd, UInt<4>(0h9)) node _store_resp_idx_T_733 = eq(rob[29].cmd, UInt<4>(0ha)) node _store_resp_idx_T_734 = eq(rob[29].cmd, UInt<4>(0hb)) node _store_resp_idx_T_735 = or(_store_resp_idx_T_731, _store_resp_idx_T_732) node _store_resp_idx_T_736 = or(_store_resp_idx_T_735, _store_resp_idx_T_733) node _store_resp_idx_T_737 = or(_store_resp_idx_T_736, _store_resp_idx_T_734) node _store_resp_idx_T_738 = eq(rob[29].cmd, UInt<4>(0h8)) node _store_resp_idx_T_739 = eq(rob[29].cmd, UInt<4>(0hc)) node _store_resp_idx_T_740 = eq(rob[29].cmd, UInt<4>(0hd)) node _store_resp_idx_T_741 = eq(rob[29].cmd, UInt<4>(0he)) node _store_resp_idx_T_742 = eq(rob[29].cmd, UInt<4>(0hf)) node _store_resp_idx_T_743 = or(_store_resp_idx_T_738, _store_resp_idx_T_739) node _store_resp_idx_T_744 = or(_store_resp_idx_T_743, _store_resp_idx_T_740) node _store_resp_idx_T_745 = or(_store_resp_idx_T_744, _store_resp_idx_T_741) node _store_resp_idx_T_746 = or(_store_resp_idx_T_745, _store_resp_idx_T_742) node _store_resp_idx_T_747 = or(_store_resp_idx_T_737, _store_resp_idx_T_746) node _store_resp_idx_T_748 = or(_store_resp_idx_T_730, _store_resp_idx_T_747) node _store_resp_idx_T_749 = and(_store_resp_idx_T_725, _store_resp_idx_T_748) node _store_resp_idx_T_750 = eq(rob_respd[30], UInt<1>(0h0)) node _store_resp_idx_T_751 = eq(rob[30].cmd, UInt<1>(0h1)) node _store_resp_idx_T_752 = eq(rob[30].cmd, UInt<5>(0h11)) node _store_resp_idx_T_753 = or(_store_resp_idx_T_751, _store_resp_idx_T_752) node _store_resp_idx_T_754 = eq(rob[30].cmd, UInt<3>(0h7)) node _store_resp_idx_T_755 = or(_store_resp_idx_T_753, _store_resp_idx_T_754) node _store_resp_idx_T_756 = eq(rob[30].cmd, UInt<3>(0h4)) node _store_resp_idx_T_757 = eq(rob[30].cmd, UInt<4>(0h9)) node _store_resp_idx_T_758 = eq(rob[30].cmd, UInt<4>(0ha)) node _store_resp_idx_T_759 = eq(rob[30].cmd, UInt<4>(0hb)) node _store_resp_idx_T_760 = or(_store_resp_idx_T_756, _store_resp_idx_T_757) node _store_resp_idx_T_761 = or(_store_resp_idx_T_760, _store_resp_idx_T_758) node _store_resp_idx_T_762 = or(_store_resp_idx_T_761, _store_resp_idx_T_759) node _store_resp_idx_T_763 = eq(rob[30].cmd, UInt<4>(0h8)) node _store_resp_idx_T_764 = eq(rob[30].cmd, UInt<4>(0hc)) node _store_resp_idx_T_765 = eq(rob[30].cmd, UInt<4>(0hd)) node _store_resp_idx_T_766 = eq(rob[30].cmd, UInt<4>(0he)) node _store_resp_idx_T_767 = eq(rob[30].cmd, UInt<4>(0hf)) node _store_resp_idx_T_768 = or(_store_resp_idx_T_763, _store_resp_idx_T_764) node _store_resp_idx_T_769 = or(_store_resp_idx_T_768, _store_resp_idx_T_765) node _store_resp_idx_T_770 = or(_store_resp_idx_T_769, _store_resp_idx_T_766) node _store_resp_idx_T_771 = or(_store_resp_idx_T_770, _store_resp_idx_T_767) node _store_resp_idx_T_772 = or(_store_resp_idx_T_762, _store_resp_idx_T_771) node _store_resp_idx_T_773 = or(_store_resp_idx_T_755, _store_resp_idx_T_772) node _store_resp_idx_T_774 = and(_store_resp_idx_T_750, _store_resp_idx_T_773) node _store_resp_idx_T_775 = eq(rob_respd[31], UInt<1>(0h0)) node _store_resp_idx_T_776 = eq(rob[31].cmd, UInt<1>(0h1)) node _store_resp_idx_T_777 = eq(rob[31].cmd, UInt<5>(0h11)) node _store_resp_idx_T_778 = or(_store_resp_idx_T_776, _store_resp_idx_T_777) node _store_resp_idx_T_779 = eq(rob[31].cmd, UInt<3>(0h7)) node _store_resp_idx_T_780 = or(_store_resp_idx_T_778, _store_resp_idx_T_779) node _store_resp_idx_T_781 = eq(rob[31].cmd, UInt<3>(0h4)) node _store_resp_idx_T_782 = eq(rob[31].cmd, UInt<4>(0h9)) node _store_resp_idx_T_783 = eq(rob[31].cmd, UInt<4>(0ha)) node _store_resp_idx_T_784 = eq(rob[31].cmd, UInt<4>(0hb)) node _store_resp_idx_T_785 = or(_store_resp_idx_T_781, _store_resp_idx_T_782) node _store_resp_idx_T_786 = or(_store_resp_idx_T_785, _store_resp_idx_T_783) node _store_resp_idx_T_787 = or(_store_resp_idx_T_786, _store_resp_idx_T_784) node _store_resp_idx_T_788 = eq(rob[31].cmd, UInt<4>(0h8)) node _store_resp_idx_T_789 = eq(rob[31].cmd, UInt<4>(0hc)) node _store_resp_idx_T_790 = eq(rob[31].cmd, UInt<4>(0hd)) node _store_resp_idx_T_791 = eq(rob[31].cmd, UInt<4>(0he)) node _store_resp_idx_T_792 = eq(rob[31].cmd, UInt<4>(0hf)) node _store_resp_idx_T_793 = or(_store_resp_idx_T_788, _store_resp_idx_T_789) node _store_resp_idx_T_794 = or(_store_resp_idx_T_793, _store_resp_idx_T_790) node _store_resp_idx_T_795 = or(_store_resp_idx_T_794, _store_resp_idx_T_791) node _store_resp_idx_T_796 = or(_store_resp_idx_T_795, _store_resp_idx_T_792) node _store_resp_idx_T_797 = or(_store_resp_idx_T_787, _store_resp_idx_T_796) node _store_resp_idx_T_798 = or(_store_resp_idx_T_780, _store_resp_idx_T_797) node _store_resp_idx_T_799 = and(_store_resp_idx_T_775, _store_resp_idx_T_798) node _store_resp_idx_T_800 = eq(rob_respd[32], UInt<1>(0h0)) node _store_resp_idx_T_801 = eq(rob[32].cmd, UInt<1>(0h1)) node _store_resp_idx_T_802 = eq(rob[32].cmd, UInt<5>(0h11)) node _store_resp_idx_T_803 = or(_store_resp_idx_T_801, _store_resp_idx_T_802) node _store_resp_idx_T_804 = eq(rob[32].cmd, UInt<3>(0h7)) node _store_resp_idx_T_805 = or(_store_resp_idx_T_803, _store_resp_idx_T_804) node _store_resp_idx_T_806 = eq(rob[32].cmd, UInt<3>(0h4)) node _store_resp_idx_T_807 = eq(rob[32].cmd, UInt<4>(0h9)) node _store_resp_idx_T_808 = eq(rob[32].cmd, UInt<4>(0ha)) node _store_resp_idx_T_809 = eq(rob[32].cmd, UInt<4>(0hb)) node _store_resp_idx_T_810 = or(_store_resp_idx_T_806, _store_resp_idx_T_807) node _store_resp_idx_T_811 = or(_store_resp_idx_T_810, _store_resp_idx_T_808) node _store_resp_idx_T_812 = or(_store_resp_idx_T_811, _store_resp_idx_T_809) node _store_resp_idx_T_813 = eq(rob[32].cmd, UInt<4>(0h8)) node _store_resp_idx_T_814 = eq(rob[32].cmd, UInt<4>(0hc)) node _store_resp_idx_T_815 = eq(rob[32].cmd, UInt<4>(0hd)) node _store_resp_idx_T_816 = eq(rob[32].cmd, UInt<4>(0he)) node _store_resp_idx_T_817 = eq(rob[32].cmd, UInt<4>(0hf)) node _store_resp_idx_T_818 = or(_store_resp_idx_T_813, _store_resp_idx_T_814) node _store_resp_idx_T_819 = or(_store_resp_idx_T_818, _store_resp_idx_T_815) node _store_resp_idx_T_820 = or(_store_resp_idx_T_819, _store_resp_idx_T_816) node _store_resp_idx_T_821 = or(_store_resp_idx_T_820, _store_resp_idx_T_817) node _store_resp_idx_T_822 = or(_store_resp_idx_T_812, _store_resp_idx_T_821) node _store_resp_idx_T_823 = or(_store_resp_idx_T_805, _store_resp_idx_T_822) node _store_resp_idx_T_824 = and(_store_resp_idx_T_800, _store_resp_idx_T_823) node _store_resp_idx_T_825 = eq(rob_respd[33], UInt<1>(0h0)) node _store_resp_idx_T_826 = eq(rob[33].cmd, UInt<1>(0h1)) node _store_resp_idx_T_827 = eq(rob[33].cmd, UInt<5>(0h11)) node _store_resp_idx_T_828 = or(_store_resp_idx_T_826, _store_resp_idx_T_827) node _store_resp_idx_T_829 = eq(rob[33].cmd, UInt<3>(0h7)) node _store_resp_idx_T_830 = or(_store_resp_idx_T_828, _store_resp_idx_T_829) node _store_resp_idx_T_831 = eq(rob[33].cmd, UInt<3>(0h4)) node _store_resp_idx_T_832 = eq(rob[33].cmd, UInt<4>(0h9)) node _store_resp_idx_T_833 = eq(rob[33].cmd, UInt<4>(0ha)) node _store_resp_idx_T_834 = eq(rob[33].cmd, UInt<4>(0hb)) node _store_resp_idx_T_835 = or(_store_resp_idx_T_831, _store_resp_idx_T_832) node _store_resp_idx_T_836 = or(_store_resp_idx_T_835, _store_resp_idx_T_833) node _store_resp_idx_T_837 = or(_store_resp_idx_T_836, _store_resp_idx_T_834) node _store_resp_idx_T_838 = eq(rob[33].cmd, UInt<4>(0h8)) node _store_resp_idx_T_839 = eq(rob[33].cmd, UInt<4>(0hc)) node _store_resp_idx_T_840 = eq(rob[33].cmd, UInt<4>(0hd)) node _store_resp_idx_T_841 = eq(rob[33].cmd, UInt<4>(0he)) node _store_resp_idx_T_842 = eq(rob[33].cmd, UInt<4>(0hf)) node _store_resp_idx_T_843 = or(_store_resp_idx_T_838, _store_resp_idx_T_839) node _store_resp_idx_T_844 = or(_store_resp_idx_T_843, _store_resp_idx_T_840) node _store_resp_idx_T_845 = or(_store_resp_idx_T_844, _store_resp_idx_T_841) node _store_resp_idx_T_846 = or(_store_resp_idx_T_845, _store_resp_idx_T_842) node _store_resp_idx_T_847 = or(_store_resp_idx_T_837, _store_resp_idx_T_846) node _store_resp_idx_T_848 = or(_store_resp_idx_T_830, _store_resp_idx_T_847) node _store_resp_idx_T_849 = and(_store_resp_idx_T_825, _store_resp_idx_T_848) node _store_resp_idx_T_850 = eq(rob_respd[34], UInt<1>(0h0)) node _store_resp_idx_T_851 = eq(rob[34].cmd, UInt<1>(0h1)) node _store_resp_idx_T_852 = eq(rob[34].cmd, UInt<5>(0h11)) node _store_resp_idx_T_853 = or(_store_resp_idx_T_851, _store_resp_idx_T_852) node _store_resp_idx_T_854 = eq(rob[34].cmd, UInt<3>(0h7)) node _store_resp_idx_T_855 = or(_store_resp_idx_T_853, _store_resp_idx_T_854) node _store_resp_idx_T_856 = eq(rob[34].cmd, UInt<3>(0h4)) node _store_resp_idx_T_857 = eq(rob[34].cmd, UInt<4>(0h9)) node _store_resp_idx_T_858 = eq(rob[34].cmd, UInt<4>(0ha)) node _store_resp_idx_T_859 = eq(rob[34].cmd, UInt<4>(0hb)) node _store_resp_idx_T_860 = or(_store_resp_idx_T_856, _store_resp_idx_T_857) node _store_resp_idx_T_861 = or(_store_resp_idx_T_860, _store_resp_idx_T_858) node _store_resp_idx_T_862 = or(_store_resp_idx_T_861, _store_resp_idx_T_859) node _store_resp_idx_T_863 = eq(rob[34].cmd, UInt<4>(0h8)) node _store_resp_idx_T_864 = eq(rob[34].cmd, UInt<4>(0hc)) node _store_resp_idx_T_865 = eq(rob[34].cmd, UInt<4>(0hd)) node _store_resp_idx_T_866 = eq(rob[34].cmd, UInt<4>(0he)) node _store_resp_idx_T_867 = eq(rob[34].cmd, UInt<4>(0hf)) node _store_resp_idx_T_868 = or(_store_resp_idx_T_863, _store_resp_idx_T_864) node _store_resp_idx_T_869 = or(_store_resp_idx_T_868, _store_resp_idx_T_865) node _store_resp_idx_T_870 = or(_store_resp_idx_T_869, _store_resp_idx_T_866) node _store_resp_idx_T_871 = or(_store_resp_idx_T_870, _store_resp_idx_T_867) node _store_resp_idx_T_872 = or(_store_resp_idx_T_862, _store_resp_idx_T_871) node _store_resp_idx_T_873 = or(_store_resp_idx_T_855, _store_resp_idx_T_872) node _store_resp_idx_T_874 = and(_store_resp_idx_T_850, _store_resp_idx_T_873) node _store_resp_idx_T_875 = eq(rob_respd[35], UInt<1>(0h0)) node _store_resp_idx_T_876 = eq(rob[35].cmd, UInt<1>(0h1)) node _store_resp_idx_T_877 = eq(rob[35].cmd, UInt<5>(0h11)) node _store_resp_idx_T_878 = or(_store_resp_idx_T_876, _store_resp_idx_T_877) node _store_resp_idx_T_879 = eq(rob[35].cmd, UInt<3>(0h7)) node _store_resp_idx_T_880 = or(_store_resp_idx_T_878, _store_resp_idx_T_879) node _store_resp_idx_T_881 = eq(rob[35].cmd, UInt<3>(0h4)) node _store_resp_idx_T_882 = eq(rob[35].cmd, UInt<4>(0h9)) node _store_resp_idx_T_883 = eq(rob[35].cmd, UInt<4>(0ha)) node _store_resp_idx_T_884 = eq(rob[35].cmd, UInt<4>(0hb)) node _store_resp_idx_T_885 = or(_store_resp_idx_T_881, _store_resp_idx_T_882) node _store_resp_idx_T_886 = or(_store_resp_idx_T_885, _store_resp_idx_T_883) node _store_resp_idx_T_887 = or(_store_resp_idx_T_886, _store_resp_idx_T_884) node _store_resp_idx_T_888 = eq(rob[35].cmd, UInt<4>(0h8)) node _store_resp_idx_T_889 = eq(rob[35].cmd, UInt<4>(0hc)) node _store_resp_idx_T_890 = eq(rob[35].cmd, UInt<4>(0hd)) node _store_resp_idx_T_891 = eq(rob[35].cmd, UInt<4>(0he)) node _store_resp_idx_T_892 = eq(rob[35].cmd, UInt<4>(0hf)) node _store_resp_idx_T_893 = or(_store_resp_idx_T_888, _store_resp_idx_T_889) node _store_resp_idx_T_894 = or(_store_resp_idx_T_893, _store_resp_idx_T_890) node _store_resp_idx_T_895 = or(_store_resp_idx_T_894, _store_resp_idx_T_891) node _store_resp_idx_T_896 = or(_store_resp_idx_T_895, _store_resp_idx_T_892) node _store_resp_idx_T_897 = or(_store_resp_idx_T_887, _store_resp_idx_T_896) node _store_resp_idx_T_898 = or(_store_resp_idx_T_880, _store_resp_idx_T_897) node _store_resp_idx_T_899 = and(_store_resp_idx_T_875, _store_resp_idx_T_898) node _store_resp_idx_T_900 = eq(rob_respd[36], UInt<1>(0h0)) node _store_resp_idx_T_901 = eq(rob[36].cmd, UInt<1>(0h1)) node _store_resp_idx_T_902 = eq(rob[36].cmd, UInt<5>(0h11)) node _store_resp_idx_T_903 = or(_store_resp_idx_T_901, _store_resp_idx_T_902) node _store_resp_idx_T_904 = eq(rob[36].cmd, UInt<3>(0h7)) node _store_resp_idx_T_905 = or(_store_resp_idx_T_903, _store_resp_idx_T_904) node _store_resp_idx_T_906 = eq(rob[36].cmd, UInt<3>(0h4)) node _store_resp_idx_T_907 = eq(rob[36].cmd, UInt<4>(0h9)) node _store_resp_idx_T_908 = eq(rob[36].cmd, UInt<4>(0ha)) node _store_resp_idx_T_909 = eq(rob[36].cmd, UInt<4>(0hb)) node _store_resp_idx_T_910 = or(_store_resp_idx_T_906, _store_resp_idx_T_907) node _store_resp_idx_T_911 = or(_store_resp_idx_T_910, _store_resp_idx_T_908) node _store_resp_idx_T_912 = or(_store_resp_idx_T_911, _store_resp_idx_T_909) node _store_resp_idx_T_913 = eq(rob[36].cmd, UInt<4>(0h8)) node _store_resp_idx_T_914 = eq(rob[36].cmd, UInt<4>(0hc)) node _store_resp_idx_T_915 = eq(rob[36].cmd, UInt<4>(0hd)) node _store_resp_idx_T_916 = eq(rob[36].cmd, UInt<4>(0he)) node _store_resp_idx_T_917 = eq(rob[36].cmd, UInt<4>(0hf)) node _store_resp_idx_T_918 = or(_store_resp_idx_T_913, _store_resp_idx_T_914) node _store_resp_idx_T_919 = or(_store_resp_idx_T_918, _store_resp_idx_T_915) node _store_resp_idx_T_920 = or(_store_resp_idx_T_919, _store_resp_idx_T_916) node _store_resp_idx_T_921 = or(_store_resp_idx_T_920, _store_resp_idx_T_917) node _store_resp_idx_T_922 = or(_store_resp_idx_T_912, _store_resp_idx_T_921) node _store_resp_idx_T_923 = or(_store_resp_idx_T_905, _store_resp_idx_T_922) node _store_resp_idx_T_924 = and(_store_resp_idx_T_900, _store_resp_idx_T_923) node _store_resp_idx_T_925 = eq(rob_respd[37], UInt<1>(0h0)) node _store_resp_idx_T_926 = eq(rob[37].cmd, UInt<1>(0h1)) node _store_resp_idx_T_927 = eq(rob[37].cmd, UInt<5>(0h11)) node _store_resp_idx_T_928 = or(_store_resp_idx_T_926, _store_resp_idx_T_927) node _store_resp_idx_T_929 = eq(rob[37].cmd, UInt<3>(0h7)) node _store_resp_idx_T_930 = or(_store_resp_idx_T_928, _store_resp_idx_T_929) node _store_resp_idx_T_931 = eq(rob[37].cmd, UInt<3>(0h4)) node _store_resp_idx_T_932 = eq(rob[37].cmd, UInt<4>(0h9)) node _store_resp_idx_T_933 = eq(rob[37].cmd, UInt<4>(0ha)) node _store_resp_idx_T_934 = eq(rob[37].cmd, UInt<4>(0hb)) node _store_resp_idx_T_935 = or(_store_resp_idx_T_931, _store_resp_idx_T_932) node _store_resp_idx_T_936 = or(_store_resp_idx_T_935, _store_resp_idx_T_933) node _store_resp_idx_T_937 = or(_store_resp_idx_T_936, _store_resp_idx_T_934) node _store_resp_idx_T_938 = eq(rob[37].cmd, UInt<4>(0h8)) node _store_resp_idx_T_939 = eq(rob[37].cmd, UInt<4>(0hc)) node _store_resp_idx_T_940 = eq(rob[37].cmd, UInt<4>(0hd)) node _store_resp_idx_T_941 = eq(rob[37].cmd, UInt<4>(0he)) node _store_resp_idx_T_942 = eq(rob[37].cmd, UInt<4>(0hf)) node _store_resp_idx_T_943 = or(_store_resp_idx_T_938, _store_resp_idx_T_939) node _store_resp_idx_T_944 = or(_store_resp_idx_T_943, _store_resp_idx_T_940) node _store_resp_idx_T_945 = or(_store_resp_idx_T_944, _store_resp_idx_T_941) node _store_resp_idx_T_946 = or(_store_resp_idx_T_945, _store_resp_idx_T_942) node _store_resp_idx_T_947 = or(_store_resp_idx_T_937, _store_resp_idx_T_946) node _store_resp_idx_T_948 = or(_store_resp_idx_T_930, _store_resp_idx_T_947) node _store_resp_idx_T_949 = and(_store_resp_idx_T_925, _store_resp_idx_T_948) node _store_resp_idx_T_950 = eq(rob_respd[38], UInt<1>(0h0)) node _store_resp_idx_T_951 = eq(rob[38].cmd, UInt<1>(0h1)) node _store_resp_idx_T_952 = eq(rob[38].cmd, UInt<5>(0h11)) node _store_resp_idx_T_953 = or(_store_resp_idx_T_951, _store_resp_idx_T_952) node _store_resp_idx_T_954 = eq(rob[38].cmd, UInt<3>(0h7)) node _store_resp_idx_T_955 = or(_store_resp_idx_T_953, _store_resp_idx_T_954) node _store_resp_idx_T_956 = eq(rob[38].cmd, UInt<3>(0h4)) node _store_resp_idx_T_957 = eq(rob[38].cmd, UInt<4>(0h9)) node _store_resp_idx_T_958 = eq(rob[38].cmd, UInt<4>(0ha)) node _store_resp_idx_T_959 = eq(rob[38].cmd, UInt<4>(0hb)) node _store_resp_idx_T_960 = or(_store_resp_idx_T_956, _store_resp_idx_T_957) node _store_resp_idx_T_961 = or(_store_resp_idx_T_960, _store_resp_idx_T_958) node _store_resp_idx_T_962 = or(_store_resp_idx_T_961, _store_resp_idx_T_959) node _store_resp_idx_T_963 = eq(rob[38].cmd, UInt<4>(0h8)) node _store_resp_idx_T_964 = eq(rob[38].cmd, UInt<4>(0hc)) node _store_resp_idx_T_965 = eq(rob[38].cmd, UInt<4>(0hd)) node _store_resp_idx_T_966 = eq(rob[38].cmd, UInt<4>(0he)) node _store_resp_idx_T_967 = eq(rob[38].cmd, UInt<4>(0hf)) node _store_resp_idx_T_968 = or(_store_resp_idx_T_963, _store_resp_idx_T_964) node _store_resp_idx_T_969 = or(_store_resp_idx_T_968, _store_resp_idx_T_965) node _store_resp_idx_T_970 = or(_store_resp_idx_T_969, _store_resp_idx_T_966) node _store_resp_idx_T_971 = or(_store_resp_idx_T_970, _store_resp_idx_T_967) node _store_resp_idx_T_972 = or(_store_resp_idx_T_962, _store_resp_idx_T_971) node _store_resp_idx_T_973 = or(_store_resp_idx_T_955, _store_resp_idx_T_972) node _store_resp_idx_T_974 = and(_store_resp_idx_T_950, _store_resp_idx_T_973) node _store_resp_idx_T_975 = eq(rob_respd[39], UInt<1>(0h0)) node _store_resp_idx_T_976 = eq(rob[39].cmd, UInt<1>(0h1)) node _store_resp_idx_T_977 = eq(rob[39].cmd, UInt<5>(0h11)) node _store_resp_idx_T_978 = or(_store_resp_idx_T_976, _store_resp_idx_T_977) node _store_resp_idx_T_979 = eq(rob[39].cmd, UInt<3>(0h7)) node _store_resp_idx_T_980 = or(_store_resp_idx_T_978, _store_resp_idx_T_979) node _store_resp_idx_T_981 = eq(rob[39].cmd, UInt<3>(0h4)) node _store_resp_idx_T_982 = eq(rob[39].cmd, UInt<4>(0h9)) node _store_resp_idx_T_983 = eq(rob[39].cmd, UInt<4>(0ha)) node _store_resp_idx_T_984 = eq(rob[39].cmd, UInt<4>(0hb)) node _store_resp_idx_T_985 = or(_store_resp_idx_T_981, _store_resp_idx_T_982) node _store_resp_idx_T_986 = or(_store_resp_idx_T_985, _store_resp_idx_T_983) node _store_resp_idx_T_987 = or(_store_resp_idx_T_986, _store_resp_idx_T_984) node _store_resp_idx_T_988 = eq(rob[39].cmd, UInt<4>(0h8)) node _store_resp_idx_T_989 = eq(rob[39].cmd, UInt<4>(0hc)) node _store_resp_idx_T_990 = eq(rob[39].cmd, UInt<4>(0hd)) node _store_resp_idx_T_991 = eq(rob[39].cmd, UInt<4>(0he)) node _store_resp_idx_T_992 = eq(rob[39].cmd, UInt<4>(0hf)) node _store_resp_idx_T_993 = or(_store_resp_idx_T_988, _store_resp_idx_T_989) node _store_resp_idx_T_994 = or(_store_resp_idx_T_993, _store_resp_idx_T_990) node _store_resp_idx_T_995 = or(_store_resp_idx_T_994, _store_resp_idx_T_991) node _store_resp_idx_T_996 = or(_store_resp_idx_T_995, _store_resp_idx_T_992) node _store_resp_idx_T_997 = or(_store_resp_idx_T_987, _store_resp_idx_T_996) node _store_resp_idx_T_998 = or(_store_resp_idx_T_980, _store_resp_idx_T_997) node _store_resp_idx_T_999 = and(_store_resp_idx_T_975, _store_resp_idx_T_998) node _store_resp_idx_T_1000 = eq(rob_respd[40], UInt<1>(0h0)) node _store_resp_idx_T_1001 = eq(rob[40].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1002 = eq(rob[40].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1003 = or(_store_resp_idx_T_1001, _store_resp_idx_T_1002) node _store_resp_idx_T_1004 = eq(rob[40].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1005 = or(_store_resp_idx_T_1003, _store_resp_idx_T_1004) node _store_resp_idx_T_1006 = eq(rob[40].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1007 = eq(rob[40].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1008 = eq(rob[40].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1009 = eq(rob[40].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1010 = or(_store_resp_idx_T_1006, _store_resp_idx_T_1007) node _store_resp_idx_T_1011 = or(_store_resp_idx_T_1010, _store_resp_idx_T_1008) node _store_resp_idx_T_1012 = or(_store_resp_idx_T_1011, _store_resp_idx_T_1009) node _store_resp_idx_T_1013 = eq(rob[40].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1014 = eq(rob[40].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1015 = eq(rob[40].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1016 = eq(rob[40].cmd, UInt<4>(0he)) node _store_resp_idx_T_1017 = eq(rob[40].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1018 = or(_store_resp_idx_T_1013, _store_resp_idx_T_1014) node _store_resp_idx_T_1019 = or(_store_resp_idx_T_1018, _store_resp_idx_T_1015) node _store_resp_idx_T_1020 = or(_store_resp_idx_T_1019, _store_resp_idx_T_1016) node _store_resp_idx_T_1021 = or(_store_resp_idx_T_1020, _store_resp_idx_T_1017) node _store_resp_idx_T_1022 = or(_store_resp_idx_T_1012, _store_resp_idx_T_1021) node _store_resp_idx_T_1023 = or(_store_resp_idx_T_1005, _store_resp_idx_T_1022) node _store_resp_idx_T_1024 = and(_store_resp_idx_T_1000, _store_resp_idx_T_1023) node _store_resp_idx_T_1025 = eq(rob_respd[41], UInt<1>(0h0)) node _store_resp_idx_T_1026 = eq(rob[41].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1027 = eq(rob[41].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1028 = or(_store_resp_idx_T_1026, _store_resp_idx_T_1027) node _store_resp_idx_T_1029 = eq(rob[41].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1030 = or(_store_resp_idx_T_1028, _store_resp_idx_T_1029) node _store_resp_idx_T_1031 = eq(rob[41].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1032 = eq(rob[41].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1033 = eq(rob[41].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1034 = eq(rob[41].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1035 = or(_store_resp_idx_T_1031, _store_resp_idx_T_1032) node _store_resp_idx_T_1036 = or(_store_resp_idx_T_1035, _store_resp_idx_T_1033) node _store_resp_idx_T_1037 = or(_store_resp_idx_T_1036, _store_resp_idx_T_1034) node _store_resp_idx_T_1038 = eq(rob[41].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1039 = eq(rob[41].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1040 = eq(rob[41].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1041 = eq(rob[41].cmd, UInt<4>(0he)) node _store_resp_idx_T_1042 = eq(rob[41].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1043 = or(_store_resp_idx_T_1038, _store_resp_idx_T_1039) node _store_resp_idx_T_1044 = or(_store_resp_idx_T_1043, _store_resp_idx_T_1040) node _store_resp_idx_T_1045 = or(_store_resp_idx_T_1044, _store_resp_idx_T_1041) node _store_resp_idx_T_1046 = or(_store_resp_idx_T_1045, _store_resp_idx_T_1042) node _store_resp_idx_T_1047 = or(_store_resp_idx_T_1037, _store_resp_idx_T_1046) node _store_resp_idx_T_1048 = or(_store_resp_idx_T_1030, _store_resp_idx_T_1047) node _store_resp_idx_T_1049 = and(_store_resp_idx_T_1025, _store_resp_idx_T_1048) node _store_resp_idx_T_1050 = eq(rob_respd[42], UInt<1>(0h0)) node _store_resp_idx_T_1051 = eq(rob[42].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1052 = eq(rob[42].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1053 = or(_store_resp_idx_T_1051, _store_resp_idx_T_1052) node _store_resp_idx_T_1054 = eq(rob[42].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1055 = or(_store_resp_idx_T_1053, _store_resp_idx_T_1054) node _store_resp_idx_T_1056 = eq(rob[42].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1057 = eq(rob[42].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1058 = eq(rob[42].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1059 = eq(rob[42].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1060 = or(_store_resp_idx_T_1056, _store_resp_idx_T_1057) node _store_resp_idx_T_1061 = or(_store_resp_idx_T_1060, _store_resp_idx_T_1058) node _store_resp_idx_T_1062 = or(_store_resp_idx_T_1061, _store_resp_idx_T_1059) node _store_resp_idx_T_1063 = eq(rob[42].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1064 = eq(rob[42].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1065 = eq(rob[42].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1066 = eq(rob[42].cmd, UInt<4>(0he)) node _store_resp_idx_T_1067 = eq(rob[42].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1068 = or(_store_resp_idx_T_1063, _store_resp_idx_T_1064) node _store_resp_idx_T_1069 = or(_store_resp_idx_T_1068, _store_resp_idx_T_1065) node _store_resp_idx_T_1070 = or(_store_resp_idx_T_1069, _store_resp_idx_T_1066) node _store_resp_idx_T_1071 = or(_store_resp_idx_T_1070, _store_resp_idx_T_1067) node _store_resp_idx_T_1072 = or(_store_resp_idx_T_1062, _store_resp_idx_T_1071) node _store_resp_idx_T_1073 = or(_store_resp_idx_T_1055, _store_resp_idx_T_1072) node _store_resp_idx_T_1074 = and(_store_resp_idx_T_1050, _store_resp_idx_T_1073) node _store_resp_idx_T_1075 = eq(rob_respd[43], UInt<1>(0h0)) node _store_resp_idx_T_1076 = eq(rob[43].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1077 = eq(rob[43].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1078 = or(_store_resp_idx_T_1076, _store_resp_idx_T_1077) node _store_resp_idx_T_1079 = eq(rob[43].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1080 = or(_store_resp_idx_T_1078, _store_resp_idx_T_1079) node _store_resp_idx_T_1081 = eq(rob[43].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1082 = eq(rob[43].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1083 = eq(rob[43].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1084 = eq(rob[43].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1085 = or(_store_resp_idx_T_1081, _store_resp_idx_T_1082) node _store_resp_idx_T_1086 = or(_store_resp_idx_T_1085, _store_resp_idx_T_1083) node _store_resp_idx_T_1087 = or(_store_resp_idx_T_1086, _store_resp_idx_T_1084) node _store_resp_idx_T_1088 = eq(rob[43].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1089 = eq(rob[43].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1090 = eq(rob[43].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1091 = eq(rob[43].cmd, UInt<4>(0he)) node _store_resp_idx_T_1092 = eq(rob[43].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1093 = or(_store_resp_idx_T_1088, _store_resp_idx_T_1089) node _store_resp_idx_T_1094 = or(_store_resp_idx_T_1093, _store_resp_idx_T_1090) node _store_resp_idx_T_1095 = or(_store_resp_idx_T_1094, _store_resp_idx_T_1091) node _store_resp_idx_T_1096 = or(_store_resp_idx_T_1095, _store_resp_idx_T_1092) node _store_resp_idx_T_1097 = or(_store_resp_idx_T_1087, _store_resp_idx_T_1096) node _store_resp_idx_T_1098 = or(_store_resp_idx_T_1080, _store_resp_idx_T_1097) node _store_resp_idx_T_1099 = and(_store_resp_idx_T_1075, _store_resp_idx_T_1098) node _store_resp_idx_T_1100 = eq(rob_respd[44], UInt<1>(0h0)) node _store_resp_idx_T_1101 = eq(rob[44].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1102 = eq(rob[44].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1103 = or(_store_resp_idx_T_1101, _store_resp_idx_T_1102) node _store_resp_idx_T_1104 = eq(rob[44].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1105 = or(_store_resp_idx_T_1103, _store_resp_idx_T_1104) node _store_resp_idx_T_1106 = eq(rob[44].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1107 = eq(rob[44].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1108 = eq(rob[44].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1109 = eq(rob[44].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1110 = or(_store_resp_idx_T_1106, _store_resp_idx_T_1107) node _store_resp_idx_T_1111 = or(_store_resp_idx_T_1110, _store_resp_idx_T_1108) node _store_resp_idx_T_1112 = or(_store_resp_idx_T_1111, _store_resp_idx_T_1109) node _store_resp_idx_T_1113 = eq(rob[44].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1114 = eq(rob[44].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1115 = eq(rob[44].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1116 = eq(rob[44].cmd, UInt<4>(0he)) node _store_resp_idx_T_1117 = eq(rob[44].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1118 = or(_store_resp_idx_T_1113, _store_resp_idx_T_1114) node _store_resp_idx_T_1119 = or(_store_resp_idx_T_1118, _store_resp_idx_T_1115) node _store_resp_idx_T_1120 = or(_store_resp_idx_T_1119, _store_resp_idx_T_1116) node _store_resp_idx_T_1121 = or(_store_resp_idx_T_1120, _store_resp_idx_T_1117) node _store_resp_idx_T_1122 = or(_store_resp_idx_T_1112, _store_resp_idx_T_1121) node _store_resp_idx_T_1123 = or(_store_resp_idx_T_1105, _store_resp_idx_T_1122) node _store_resp_idx_T_1124 = and(_store_resp_idx_T_1100, _store_resp_idx_T_1123) node _store_resp_idx_T_1125 = eq(rob_respd[45], UInt<1>(0h0)) node _store_resp_idx_T_1126 = eq(rob[45].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1127 = eq(rob[45].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1128 = or(_store_resp_idx_T_1126, _store_resp_idx_T_1127) node _store_resp_idx_T_1129 = eq(rob[45].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1130 = or(_store_resp_idx_T_1128, _store_resp_idx_T_1129) node _store_resp_idx_T_1131 = eq(rob[45].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1132 = eq(rob[45].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1133 = eq(rob[45].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1134 = eq(rob[45].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1135 = or(_store_resp_idx_T_1131, _store_resp_idx_T_1132) node _store_resp_idx_T_1136 = or(_store_resp_idx_T_1135, _store_resp_idx_T_1133) node _store_resp_idx_T_1137 = or(_store_resp_idx_T_1136, _store_resp_idx_T_1134) node _store_resp_idx_T_1138 = eq(rob[45].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1139 = eq(rob[45].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1140 = eq(rob[45].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1141 = eq(rob[45].cmd, UInt<4>(0he)) node _store_resp_idx_T_1142 = eq(rob[45].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1143 = or(_store_resp_idx_T_1138, _store_resp_idx_T_1139) node _store_resp_idx_T_1144 = or(_store_resp_idx_T_1143, _store_resp_idx_T_1140) node _store_resp_idx_T_1145 = or(_store_resp_idx_T_1144, _store_resp_idx_T_1141) node _store_resp_idx_T_1146 = or(_store_resp_idx_T_1145, _store_resp_idx_T_1142) node _store_resp_idx_T_1147 = or(_store_resp_idx_T_1137, _store_resp_idx_T_1146) node _store_resp_idx_T_1148 = or(_store_resp_idx_T_1130, _store_resp_idx_T_1147) node _store_resp_idx_T_1149 = and(_store_resp_idx_T_1125, _store_resp_idx_T_1148) node _store_resp_idx_T_1150 = eq(rob_respd[46], UInt<1>(0h0)) node _store_resp_idx_T_1151 = eq(rob[46].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1152 = eq(rob[46].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1153 = or(_store_resp_idx_T_1151, _store_resp_idx_T_1152) node _store_resp_idx_T_1154 = eq(rob[46].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1155 = or(_store_resp_idx_T_1153, _store_resp_idx_T_1154) node _store_resp_idx_T_1156 = eq(rob[46].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1157 = eq(rob[46].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1158 = eq(rob[46].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1159 = eq(rob[46].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1160 = or(_store_resp_idx_T_1156, _store_resp_idx_T_1157) node _store_resp_idx_T_1161 = or(_store_resp_idx_T_1160, _store_resp_idx_T_1158) node _store_resp_idx_T_1162 = or(_store_resp_idx_T_1161, _store_resp_idx_T_1159) node _store_resp_idx_T_1163 = eq(rob[46].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1164 = eq(rob[46].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1165 = eq(rob[46].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1166 = eq(rob[46].cmd, UInt<4>(0he)) node _store_resp_idx_T_1167 = eq(rob[46].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1168 = or(_store_resp_idx_T_1163, _store_resp_idx_T_1164) node _store_resp_idx_T_1169 = or(_store_resp_idx_T_1168, _store_resp_idx_T_1165) node _store_resp_idx_T_1170 = or(_store_resp_idx_T_1169, _store_resp_idx_T_1166) node _store_resp_idx_T_1171 = or(_store_resp_idx_T_1170, _store_resp_idx_T_1167) node _store_resp_idx_T_1172 = or(_store_resp_idx_T_1162, _store_resp_idx_T_1171) node _store_resp_idx_T_1173 = or(_store_resp_idx_T_1155, _store_resp_idx_T_1172) node _store_resp_idx_T_1174 = and(_store_resp_idx_T_1150, _store_resp_idx_T_1173) node _store_resp_idx_T_1175 = eq(rob_respd[47], UInt<1>(0h0)) node _store_resp_idx_T_1176 = eq(rob[47].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1177 = eq(rob[47].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1178 = or(_store_resp_idx_T_1176, _store_resp_idx_T_1177) node _store_resp_idx_T_1179 = eq(rob[47].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1180 = or(_store_resp_idx_T_1178, _store_resp_idx_T_1179) node _store_resp_idx_T_1181 = eq(rob[47].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1182 = eq(rob[47].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1183 = eq(rob[47].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1184 = eq(rob[47].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1185 = or(_store_resp_idx_T_1181, _store_resp_idx_T_1182) node _store_resp_idx_T_1186 = or(_store_resp_idx_T_1185, _store_resp_idx_T_1183) node _store_resp_idx_T_1187 = or(_store_resp_idx_T_1186, _store_resp_idx_T_1184) node _store_resp_idx_T_1188 = eq(rob[47].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1189 = eq(rob[47].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1190 = eq(rob[47].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1191 = eq(rob[47].cmd, UInt<4>(0he)) node _store_resp_idx_T_1192 = eq(rob[47].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1193 = or(_store_resp_idx_T_1188, _store_resp_idx_T_1189) node _store_resp_idx_T_1194 = or(_store_resp_idx_T_1193, _store_resp_idx_T_1190) node _store_resp_idx_T_1195 = or(_store_resp_idx_T_1194, _store_resp_idx_T_1191) node _store_resp_idx_T_1196 = or(_store_resp_idx_T_1195, _store_resp_idx_T_1192) node _store_resp_idx_T_1197 = or(_store_resp_idx_T_1187, _store_resp_idx_T_1196) node _store_resp_idx_T_1198 = or(_store_resp_idx_T_1180, _store_resp_idx_T_1197) node _store_resp_idx_T_1199 = and(_store_resp_idx_T_1175, _store_resp_idx_T_1198) node _store_resp_idx_T_1200 = eq(rob_respd[48], UInt<1>(0h0)) node _store_resp_idx_T_1201 = eq(rob[48].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1202 = eq(rob[48].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1203 = or(_store_resp_idx_T_1201, _store_resp_idx_T_1202) node _store_resp_idx_T_1204 = eq(rob[48].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1205 = or(_store_resp_idx_T_1203, _store_resp_idx_T_1204) node _store_resp_idx_T_1206 = eq(rob[48].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1207 = eq(rob[48].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1208 = eq(rob[48].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1209 = eq(rob[48].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1210 = or(_store_resp_idx_T_1206, _store_resp_idx_T_1207) node _store_resp_idx_T_1211 = or(_store_resp_idx_T_1210, _store_resp_idx_T_1208) node _store_resp_idx_T_1212 = or(_store_resp_idx_T_1211, _store_resp_idx_T_1209) node _store_resp_idx_T_1213 = eq(rob[48].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1214 = eq(rob[48].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1215 = eq(rob[48].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1216 = eq(rob[48].cmd, UInt<4>(0he)) node _store_resp_idx_T_1217 = eq(rob[48].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1218 = or(_store_resp_idx_T_1213, _store_resp_idx_T_1214) node _store_resp_idx_T_1219 = or(_store_resp_idx_T_1218, _store_resp_idx_T_1215) node _store_resp_idx_T_1220 = or(_store_resp_idx_T_1219, _store_resp_idx_T_1216) node _store_resp_idx_T_1221 = or(_store_resp_idx_T_1220, _store_resp_idx_T_1217) node _store_resp_idx_T_1222 = or(_store_resp_idx_T_1212, _store_resp_idx_T_1221) node _store_resp_idx_T_1223 = or(_store_resp_idx_T_1205, _store_resp_idx_T_1222) node _store_resp_idx_T_1224 = and(_store_resp_idx_T_1200, _store_resp_idx_T_1223) node _store_resp_idx_T_1225 = eq(rob_respd[49], UInt<1>(0h0)) node _store_resp_idx_T_1226 = eq(rob[49].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1227 = eq(rob[49].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1228 = or(_store_resp_idx_T_1226, _store_resp_idx_T_1227) node _store_resp_idx_T_1229 = eq(rob[49].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1230 = or(_store_resp_idx_T_1228, _store_resp_idx_T_1229) node _store_resp_idx_T_1231 = eq(rob[49].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1232 = eq(rob[49].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1233 = eq(rob[49].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1234 = eq(rob[49].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1235 = or(_store_resp_idx_T_1231, _store_resp_idx_T_1232) node _store_resp_idx_T_1236 = or(_store_resp_idx_T_1235, _store_resp_idx_T_1233) node _store_resp_idx_T_1237 = or(_store_resp_idx_T_1236, _store_resp_idx_T_1234) node _store_resp_idx_T_1238 = eq(rob[49].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1239 = eq(rob[49].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1240 = eq(rob[49].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1241 = eq(rob[49].cmd, UInt<4>(0he)) node _store_resp_idx_T_1242 = eq(rob[49].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1243 = or(_store_resp_idx_T_1238, _store_resp_idx_T_1239) node _store_resp_idx_T_1244 = or(_store_resp_idx_T_1243, _store_resp_idx_T_1240) node _store_resp_idx_T_1245 = or(_store_resp_idx_T_1244, _store_resp_idx_T_1241) node _store_resp_idx_T_1246 = or(_store_resp_idx_T_1245, _store_resp_idx_T_1242) node _store_resp_idx_T_1247 = or(_store_resp_idx_T_1237, _store_resp_idx_T_1246) node _store_resp_idx_T_1248 = or(_store_resp_idx_T_1230, _store_resp_idx_T_1247) node _store_resp_idx_T_1249 = and(_store_resp_idx_T_1225, _store_resp_idx_T_1248) node _store_resp_idx_T_1250 = eq(rob_respd[50], UInt<1>(0h0)) node _store_resp_idx_T_1251 = eq(rob[50].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1252 = eq(rob[50].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1253 = or(_store_resp_idx_T_1251, _store_resp_idx_T_1252) node _store_resp_idx_T_1254 = eq(rob[50].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1255 = or(_store_resp_idx_T_1253, _store_resp_idx_T_1254) node _store_resp_idx_T_1256 = eq(rob[50].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1257 = eq(rob[50].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1258 = eq(rob[50].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1259 = eq(rob[50].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1260 = or(_store_resp_idx_T_1256, _store_resp_idx_T_1257) node _store_resp_idx_T_1261 = or(_store_resp_idx_T_1260, _store_resp_idx_T_1258) node _store_resp_idx_T_1262 = or(_store_resp_idx_T_1261, _store_resp_idx_T_1259) node _store_resp_idx_T_1263 = eq(rob[50].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1264 = eq(rob[50].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1265 = eq(rob[50].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1266 = eq(rob[50].cmd, UInt<4>(0he)) node _store_resp_idx_T_1267 = eq(rob[50].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1268 = or(_store_resp_idx_T_1263, _store_resp_idx_T_1264) node _store_resp_idx_T_1269 = or(_store_resp_idx_T_1268, _store_resp_idx_T_1265) node _store_resp_idx_T_1270 = or(_store_resp_idx_T_1269, _store_resp_idx_T_1266) node _store_resp_idx_T_1271 = or(_store_resp_idx_T_1270, _store_resp_idx_T_1267) node _store_resp_idx_T_1272 = or(_store_resp_idx_T_1262, _store_resp_idx_T_1271) node _store_resp_idx_T_1273 = or(_store_resp_idx_T_1255, _store_resp_idx_T_1272) node _store_resp_idx_T_1274 = and(_store_resp_idx_T_1250, _store_resp_idx_T_1273) node _store_resp_idx_T_1275 = eq(rob_respd[51], UInt<1>(0h0)) node _store_resp_idx_T_1276 = eq(rob[51].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1277 = eq(rob[51].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1278 = or(_store_resp_idx_T_1276, _store_resp_idx_T_1277) node _store_resp_idx_T_1279 = eq(rob[51].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1280 = or(_store_resp_idx_T_1278, _store_resp_idx_T_1279) node _store_resp_idx_T_1281 = eq(rob[51].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1282 = eq(rob[51].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1283 = eq(rob[51].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1284 = eq(rob[51].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1285 = or(_store_resp_idx_T_1281, _store_resp_idx_T_1282) node _store_resp_idx_T_1286 = or(_store_resp_idx_T_1285, _store_resp_idx_T_1283) node _store_resp_idx_T_1287 = or(_store_resp_idx_T_1286, _store_resp_idx_T_1284) node _store_resp_idx_T_1288 = eq(rob[51].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1289 = eq(rob[51].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1290 = eq(rob[51].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1291 = eq(rob[51].cmd, UInt<4>(0he)) node _store_resp_idx_T_1292 = eq(rob[51].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1293 = or(_store_resp_idx_T_1288, _store_resp_idx_T_1289) node _store_resp_idx_T_1294 = or(_store_resp_idx_T_1293, _store_resp_idx_T_1290) node _store_resp_idx_T_1295 = or(_store_resp_idx_T_1294, _store_resp_idx_T_1291) node _store_resp_idx_T_1296 = or(_store_resp_idx_T_1295, _store_resp_idx_T_1292) node _store_resp_idx_T_1297 = or(_store_resp_idx_T_1287, _store_resp_idx_T_1296) node _store_resp_idx_T_1298 = or(_store_resp_idx_T_1280, _store_resp_idx_T_1297) node _store_resp_idx_T_1299 = and(_store_resp_idx_T_1275, _store_resp_idx_T_1298) node _store_resp_idx_T_1300 = eq(rob_respd[52], UInt<1>(0h0)) node _store_resp_idx_T_1301 = eq(rob[52].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1302 = eq(rob[52].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1303 = or(_store_resp_idx_T_1301, _store_resp_idx_T_1302) node _store_resp_idx_T_1304 = eq(rob[52].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1305 = or(_store_resp_idx_T_1303, _store_resp_idx_T_1304) node _store_resp_idx_T_1306 = eq(rob[52].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1307 = eq(rob[52].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1308 = eq(rob[52].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1309 = eq(rob[52].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1310 = or(_store_resp_idx_T_1306, _store_resp_idx_T_1307) node _store_resp_idx_T_1311 = or(_store_resp_idx_T_1310, _store_resp_idx_T_1308) node _store_resp_idx_T_1312 = or(_store_resp_idx_T_1311, _store_resp_idx_T_1309) node _store_resp_idx_T_1313 = eq(rob[52].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1314 = eq(rob[52].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1315 = eq(rob[52].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1316 = eq(rob[52].cmd, UInt<4>(0he)) node _store_resp_idx_T_1317 = eq(rob[52].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1318 = or(_store_resp_idx_T_1313, _store_resp_idx_T_1314) node _store_resp_idx_T_1319 = or(_store_resp_idx_T_1318, _store_resp_idx_T_1315) node _store_resp_idx_T_1320 = or(_store_resp_idx_T_1319, _store_resp_idx_T_1316) node _store_resp_idx_T_1321 = or(_store_resp_idx_T_1320, _store_resp_idx_T_1317) node _store_resp_idx_T_1322 = or(_store_resp_idx_T_1312, _store_resp_idx_T_1321) node _store_resp_idx_T_1323 = or(_store_resp_idx_T_1305, _store_resp_idx_T_1322) node _store_resp_idx_T_1324 = and(_store_resp_idx_T_1300, _store_resp_idx_T_1323) node _store_resp_idx_T_1325 = eq(rob_respd[53], UInt<1>(0h0)) node _store_resp_idx_T_1326 = eq(rob[53].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1327 = eq(rob[53].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1328 = or(_store_resp_idx_T_1326, _store_resp_idx_T_1327) node _store_resp_idx_T_1329 = eq(rob[53].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1330 = or(_store_resp_idx_T_1328, _store_resp_idx_T_1329) node _store_resp_idx_T_1331 = eq(rob[53].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1332 = eq(rob[53].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1333 = eq(rob[53].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1334 = eq(rob[53].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1335 = or(_store_resp_idx_T_1331, _store_resp_idx_T_1332) node _store_resp_idx_T_1336 = or(_store_resp_idx_T_1335, _store_resp_idx_T_1333) node _store_resp_idx_T_1337 = or(_store_resp_idx_T_1336, _store_resp_idx_T_1334) node _store_resp_idx_T_1338 = eq(rob[53].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1339 = eq(rob[53].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1340 = eq(rob[53].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1341 = eq(rob[53].cmd, UInt<4>(0he)) node _store_resp_idx_T_1342 = eq(rob[53].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1343 = or(_store_resp_idx_T_1338, _store_resp_idx_T_1339) node _store_resp_idx_T_1344 = or(_store_resp_idx_T_1343, _store_resp_idx_T_1340) node _store_resp_idx_T_1345 = or(_store_resp_idx_T_1344, _store_resp_idx_T_1341) node _store_resp_idx_T_1346 = or(_store_resp_idx_T_1345, _store_resp_idx_T_1342) node _store_resp_idx_T_1347 = or(_store_resp_idx_T_1337, _store_resp_idx_T_1346) node _store_resp_idx_T_1348 = or(_store_resp_idx_T_1330, _store_resp_idx_T_1347) node _store_resp_idx_T_1349 = and(_store_resp_idx_T_1325, _store_resp_idx_T_1348) node _store_resp_idx_T_1350 = eq(rob_respd[54], UInt<1>(0h0)) node _store_resp_idx_T_1351 = eq(rob[54].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1352 = eq(rob[54].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1353 = or(_store_resp_idx_T_1351, _store_resp_idx_T_1352) node _store_resp_idx_T_1354 = eq(rob[54].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1355 = or(_store_resp_idx_T_1353, _store_resp_idx_T_1354) node _store_resp_idx_T_1356 = eq(rob[54].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1357 = eq(rob[54].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1358 = eq(rob[54].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1359 = eq(rob[54].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1360 = or(_store_resp_idx_T_1356, _store_resp_idx_T_1357) node _store_resp_idx_T_1361 = or(_store_resp_idx_T_1360, _store_resp_idx_T_1358) node _store_resp_idx_T_1362 = or(_store_resp_idx_T_1361, _store_resp_idx_T_1359) node _store_resp_idx_T_1363 = eq(rob[54].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1364 = eq(rob[54].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1365 = eq(rob[54].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1366 = eq(rob[54].cmd, UInt<4>(0he)) node _store_resp_idx_T_1367 = eq(rob[54].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1368 = or(_store_resp_idx_T_1363, _store_resp_idx_T_1364) node _store_resp_idx_T_1369 = or(_store_resp_idx_T_1368, _store_resp_idx_T_1365) node _store_resp_idx_T_1370 = or(_store_resp_idx_T_1369, _store_resp_idx_T_1366) node _store_resp_idx_T_1371 = or(_store_resp_idx_T_1370, _store_resp_idx_T_1367) node _store_resp_idx_T_1372 = or(_store_resp_idx_T_1362, _store_resp_idx_T_1371) node _store_resp_idx_T_1373 = or(_store_resp_idx_T_1355, _store_resp_idx_T_1372) node _store_resp_idx_T_1374 = and(_store_resp_idx_T_1350, _store_resp_idx_T_1373) node _store_resp_idx_T_1375 = eq(rob_respd[55], UInt<1>(0h0)) node _store_resp_idx_T_1376 = eq(rob[55].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1377 = eq(rob[55].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1378 = or(_store_resp_idx_T_1376, _store_resp_idx_T_1377) node _store_resp_idx_T_1379 = eq(rob[55].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1380 = or(_store_resp_idx_T_1378, _store_resp_idx_T_1379) node _store_resp_idx_T_1381 = eq(rob[55].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1382 = eq(rob[55].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1383 = eq(rob[55].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1384 = eq(rob[55].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1385 = or(_store_resp_idx_T_1381, _store_resp_idx_T_1382) node _store_resp_idx_T_1386 = or(_store_resp_idx_T_1385, _store_resp_idx_T_1383) node _store_resp_idx_T_1387 = or(_store_resp_idx_T_1386, _store_resp_idx_T_1384) node _store_resp_idx_T_1388 = eq(rob[55].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1389 = eq(rob[55].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1390 = eq(rob[55].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1391 = eq(rob[55].cmd, UInt<4>(0he)) node _store_resp_idx_T_1392 = eq(rob[55].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1393 = or(_store_resp_idx_T_1388, _store_resp_idx_T_1389) node _store_resp_idx_T_1394 = or(_store_resp_idx_T_1393, _store_resp_idx_T_1390) node _store_resp_idx_T_1395 = or(_store_resp_idx_T_1394, _store_resp_idx_T_1391) node _store_resp_idx_T_1396 = or(_store_resp_idx_T_1395, _store_resp_idx_T_1392) node _store_resp_idx_T_1397 = or(_store_resp_idx_T_1387, _store_resp_idx_T_1396) node _store_resp_idx_T_1398 = or(_store_resp_idx_T_1380, _store_resp_idx_T_1397) node _store_resp_idx_T_1399 = and(_store_resp_idx_T_1375, _store_resp_idx_T_1398) node _store_resp_idx_T_1400 = eq(rob_respd[56], UInt<1>(0h0)) node _store_resp_idx_T_1401 = eq(rob[56].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1402 = eq(rob[56].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1403 = or(_store_resp_idx_T_1401, _store_resp_idx_T_1402) node _store_resp_idx_T_1404 = eq(rob[56].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1405 = or(_store_resp_idx_T_1403, _store_resp_idx_T_1404) node _store_resp_idx_T_1406 = eq(rob[56].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1407 = eq(rob[56].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1408 = eq(rob[56].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1409 = eq(rob[56].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1410 = or(_store_resp_idx_T_1406, _store_resp_idx_T_1407) node _store_resp_idx_T_1411 = or(_store_resp_idx_T_1410, _store_resp_idx_T_1408) node _store_resp_idx_T_1412 = or(_store_resp_idx_T_1411, _store_resp_idx_T_1409) node _store_resp_idx_T_1413 = eq(rob[56].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1414 = eq(rob[56].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1415 = eq(rob[56].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1416 = eq(rob[56].cmd, UInt<4>(0he)) node _store_resp_idx_T_1417 = eq(rob[56].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1418 = or(_store_resp_idx_T_1413, _store_resp_idx_T_1414) node _store_resp_idx_T_1419 = or(_store_resp_idx_T_1418, _store_resp_idx_T_1415) node _store_resp_idx_T_1420 = or(_store_resp_idx_T_1419, _store_resp_idx_T_1416) node _store_resp_idx_T_1421 = or(_store_resp_idx_T_1420, _store_resp_idx_T_1417) node _store_resp_idx_T_1422 = or(_store_resp_idx_T_1412, _store_resp_idx_T_1421) node _store_resp_idx_T_1423 = or(_store_resp_idx_T_1405, _store_resp_idx_T_1422) node _store_resp_idx_T_1424 = and(_store_resp_idx_T_1400, _store_resp_idx_T_1423) node _store_resp_idx_T_1425 = eq(rob_respd[57], UInt<1>(0h0)) node _store_resp_idx_T_1426 = eq(rob[57].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1427 = eq(rob[57].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1428 = or(_store_resp_idx_T_1426, _store_resp_idx_T_1427) node _store_resp_idx_T_1429 = eq(rob[57].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1430 = or(_store_resp_idx_T_1428, _store_resp_idx_T_1429) node _store_resp_idx_T_1431 = eq(rob[57].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1432 = eq(rob[57].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1433 = eq(rob[57].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1434 = eq(rob[57].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1435 = or(_store_resp_idx_T_1431, _store_resp_idx_T_1432) node _store_resp_idx_T_1436 = or(_store_resp_idx_T_1435, _store_resp_idx_T_1433) node _store_resp_idx_T_1437 = or(_store_resp_idx_T_1436, _store_resp_idx_T_1434) node _store_resp_idx_T_1438 = eq(rob[57].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1439 = eq(rob[57].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1440 = eq(rob[57].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1441 = eq(rob[57].cmd, UInt<4>(0he)) node _store_resp_idx_T_1442 = eq(rob[57].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1443 = or(_store_resp_idx_T_1438, _store_resp_idx_T_1439) node _store_resp_idx_T_1444 = or(_store_resp_idx_T_1443, _store_resp_idx_T_1440) node _store_resp_idx_T_1445 = or(_store_resp_idx_T_1444, _store_resp_idx_T_1441) node _store_resp_idx_T_1446 = or(_store_resp_idx_T_1445, _store_resp_idx_T_1442) node _store_resp_idx_T_1447 = or(_store_resp_idx_T_1437, _store_resp_idx_T_1446) node _store_resp_idx_T_1448 = or(_store_resp_idx_T_1430, _store_resp_idx_T_1447) node _store_resp_idx_T_1449 = and(_store_resp_idx_T_1425, _store_resp_idx_T_1448) node _store_resp_idx_T_1450 = eq(rob_respd[58], UInt<1>(0h0)) node _store_resp_idx_T_1451 = eq(rob[58].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1452 = eq(rob[58].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1453 = or(_store_resp_idx_T_1451, _store_resp_idx_T_1452) node _store_resp_idx_T_1454 = eq(rob[58].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1455 = or(_store_resp_idx_T_1453, _store_resp_idx_T_1454) node _store_resp_idx_T_1456 = eq(rob[58].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1457 = eq(rob[58].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1458 = eq(rob[58].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1459 = eq(rob[58].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1460 = or(_store_resp_idx_T_1456, _store_resp_idx_T_1457) node _store_resp_idx_T_1461 = or(_store_resp_idx_T_1460, _store_resp_idx_T_1458) node _store_resp_idx_T_1462 = or(_store_resp_idx_T_1461, _store_resp_idx_T_1459) node _store_resp_idx_T_1463 = eq(rob[58].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1464 = eq(rob[58].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1465 = eq(rob[58].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1466 = eq(rob[58].cmd, UInt<4>(0he)) node _store_resp_idx_T_1467 = eq(rob[58].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1468 = or(_store_resp_idx_T_1463, _store_resp_idx_T_1464) node _store_resp_idx_T_1469 = or(_store_resp_idx_T_1468, _store_resp_idx_T_1465) node _store_resp_idx_T_1470 = or(_store_resp_idx_T_1469, _store_resp_idx_T_1466) node _store_resp_idx_T_1471 = or(_store_resp_idx_T_1470, _store_resp_idx_T_1467) node _store_resp_idx_T_1472 = or(_store_resp_idx_T_1462, _store_resp_idx_T_1471) node _store_resp_idx_T_1473 = or(_store_resp_idx_T_1455, _store_resp_idx_T_1472) node _store_resp_idx_T_1474 = and(_store_resp_idx_T_1450, _store_resp_idx_T_1473) node _store_resp_idx_T_1475 = eq(rob_respd[59], UInt<1>(0h0)) node _store_resp_idx_T_1476 = eq(rob[59].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1477 = eq(rob[59].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1478 = or(_store_resp_idx_T_1476, _store_resp_idx_T_1477) node _store_resp_idx_T_1479 = eq(rob[59].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1480 = or(_store_resp_idx_T_1478, _store_resp_idx_T_1479) node _store_resp_idx_T_1481 = eq(rob[59].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1482 = eq(rob[59].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1483 = eq(rob[59].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1484 = eq(rob[59].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1485 = or(_store_resp_idx_T_1481, _store_resp_idx_T_1482) node _store_resp_idx_T_1486 = or(_store_resp_idx_T_1485, _store_resp_idx_T_1483) node _store_resp_idx_T_1487 = or(_store_resp_idx_T_1486, _store_resp_idx_T_1484) node _store_resp_idx_T_1488 = eq(rob[59].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1489 = eq(rob[59].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1490 = eq(rob[59].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1491 = eq(rob[59].cmd, UInt<4>(0he)) node _store_resp_idx_T_1492 = eq(rob[59].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1493 = or(_store_resp_idx_T_1488, _store_resp_idx_T_1489) node _store_resp_idx_T_1494 = or(_store_resp_idx_T_1493, _store_resp_idx_T_1490) node _store_resp_idx_T_1495 = or(_store_resp_idx_T_1494, _store_resp_idx_T_1491) node _store_resp_idx_T_1496 = or(_store_resp_idx_T_1495, _store_resp_idx_T_1492) node _store_resp_idx_T_1497 = or(_store_resp_idx_T_1487, _store_resp_idx_T_1496) node _store_resp_idx_T_1498 = or(_store_resp_idx_T_1480, _store_resp_idx_T_1497) node _store_resp_idx_T_1499 = and(_store_resp_idx_T_1475, _store_resp_idx_T_1498) node _store_resp_idx_T_1500 = eq(rob_respd[60], UInt<1>(0h0)) node _store_resp_idx_T_1501 = eq(rob[60].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1502 = eq(rob[60].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1503 = or(_store_resp_idx_T_1501, _store_resp_idx_T_1502) node _store_resp_idx_T_1504 = eq(rob[60].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1505 = or(_store_resp_idx_T_1503, _store_resp_idx_T_1504) node _store_resp_idx_T_1506 = eq(rob[60].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1507 = eq(rob[60].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1508 = eq(rob[60].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1509 = eq(rob[60].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1510 = or(_store_resp_idx_T_1506, _store_resp_idx_T_1507) node _store_resp_idx_T_1511 = or(_store_resp_idx_T_1510, _store_resp_idx_T_1508) node _store_resp_idx_T_1512 = or(_store_resp_idx_T_1511, _store_resp_idx_T_1509) node _store_resp_idx_T_1513 = eq(rob[60].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1514 = eq(rob[60].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1515 = eq(rob[60].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1516 = eq(rob[60].cmd, UInt<4>(0he)) node _store_resp_idx_T_1517 = eq(rob[60].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1518 = or(_store_resp_idx_T_1513, _store_resp_idx_T_1514) node _store_resp_idx_T_1519 = or(_store_resp_idx_T_1518, _store_resp_idx_T_1515) node _store_resp_idx_T_1520 = or(_store_resp_idx_T_1519, _store_resp_idx_T_1516) node _store_resp_idx_T_1521 = or(_store_resp_idx_T_1520, _store_resp_idx_T_1517) node _store_resp_idx_T_1522 = or(_store_resp_idx_T_1512, _store_resp_idx_T_1521) node _store_resp_idx_T_1523 = or(_store_resp_idx_T_1505, _store_resp_idx_T_1522) node _store_resp_idx_T_1524 = and(_store_resp_idx_T_1500, _store_resp_idx_T_1523) node _store_resp_idx_T_1525 = eq(rob_respd[61], UInt<1>(0h0)) node _store_resp_idx_T_1526 = eq(rob[61].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1527 = eq(rob[61].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1528 = or(_store_resp_idx_T_1526, _store_resp_idx_T_1527) node _store_resp_idx_T_1529 = eq(rob[61].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1530 = or(_store_resp_idx_T_1528, _store_resp_idx_T_1529) node _store_resp_idx_T_1531 = eq(rob[61].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1532 = eq(rob[61].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1533 = eq(rob[61].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1534 = eq(rob[61].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1535 = or(_store_resp_idx_T_1531, _store_resp_idx_T_1532) node _store_resp_idx_T_1536 = or(_store_resp_idx_T_1535, _store_resp_idx_T_1533) node _store_resp_idx_T_1537 = or(_store_resp_idx_T_1536, _store_resp_idx_T_1534) node _store_resp_idx_T_1538 = eq(rob[61].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1539 = eq(rob[61].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1540 = eq(rob[61].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1541 = eq(rob[61].cmd, UInt<4>(0he)) node _store_resp_idx_T_1542 = eq(rob[61].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1543 = or(_store_resp_idx_T_1538, _store_resp_idx_T_1539) node _store_resp_idx_T_1544 = or(_store_resp_idx_T_1543, _store_resp_idx_T_1540) node _store_resp_idx_T_1545 = or(_store_resp_idx_T_1544, _store_resp_idx_T_1541) node _store_resp_idx_T_1546 = or(_store_resp_idx_T_1545, _store_resp_idx_T_1542) node _store_resp_idx_T_1547 = or(_store_resp_idx_T_1537, _store_resp_idx_T_1546) node _store_resp_idx_T_1548 = or(_store_resp_idx_T_1530, _store_resp_idx_T_1547) node _store_resp_idx_T_1549 = and(_store_resp_idx_T_1525, _store_resp_idx_T_1548) node _store_resp_idx_T_1550 = eq(rob_respd[62], UInt<1>(0h0)) node _store_resp_idx_T_1551 = eq(rob[62].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1552 = eq(rob[62].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1553 = or(_store_resp_idx_T_1551, _store_resp_idx_T_1552) node _store_resp_idx_T_1554 = eq(rob[62].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1555 = or(_store_resp_idx_T_1553, _store_resp_idx_T_1554) node _store_resp_idx_T_1556 = eq(rob[62].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1557 = eq(rob[62].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1558 = eq(rob[62].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1559 = eq(rob[62].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1560 = or(_store_resp_idx_T_1556, _store_resp_idx_T_1557) node _store_resp_idx_T_1561 = or(_store_resp_idx_T_1560, _store_resp_idx_T_1558) node _store_resp_idx_T_1562 = or(_store_resp_idx_T_1561, _store_resp_idx_T_1559) node _store_resp_idx_T_1563 = eq(rob[62].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1564 = eq(rob[62].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1565 = eq(rob[62].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1566 = eq(rob[62].cmd, UInt<4>(0he)) node _store_resp_idx_T_1567 = eq(rob[62].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1568 = or(_store_resp_idx_T_1563, _store_resp_idx_T_1564) node _store_resp_idx_T_1569 = or(_store_resp_idx_T_1568, _store_resp_idx_T_1565) node _store_resp_idx_T_1570 = or(_store_resp_idx_T_1569, _store_resp_idx_T_1566) node _store_resp_idx_T_1571 = or(_store_resp_idx_T_1570, _store_resp_idx_T_1567) node _store_resp_idx_T_1572 = or(_store_resp_idx_T_1562, _store_resp_idx_T_1571) node _store_resp_idx_T_1573 = or(_store_resp_idx_T_1555, _store_resp_idx_T_1572) node _store_resp_idx_T_1574 = and(_store_resp_idx_T_1550, _store_resp_idx_T_1573) node _store_resp_idx_T_1575 = eq(rob_respd[63], UInt<1>(0h0)) node _store_resp_idx_T_1576 = eq(rob[63].cmd, UInt<1>(0h1)) node _store_resp_idx_T_1577 = eq(rob[63].cmd, UInt<5>(0h11)) node _store_resp_idx_T_1578 = or(_store_resp_idx_T_1576, _store_resp_idx_T_1577) node _store_resp_idx_T_1579 = eq(rob[63].cmd, UInt<3>(0h7)) node _store_resp_idx_T_1580 = or(_store_resp_idx_T_1578, _store_resp_idx_T_1579) node _store_resp_idx_T_1581 = eq(rob[63].cmd, UInt<3>(0h4)) node _store_resp_idx_T_1582 = eq(rob[63].cmd, UInt<4>(0h9)) node _store_resp_idx_T_1583 = eq(rob[63].cmd, UInt<4>(0ha)) node _store_resp_idx_T_1584 = eq(rob[63].cmd, UInt<4>(0hb)) node _store_resp_idx_T_1585 = or(_store_resp_idx_T_1581, _store_resp_idx_T_1582) node _store_resp_idx_T_1586 = or(_store_resp_idx_T_1585, _store_resp_idx_T_1583) node _store_resp_idx_T_1587 = or(_store_resp_idx_T_1586, _store_resp_idx_T_1584) node _store_resp_idx_T_1588 = eq(rob[63].cmd, UInt<4>(0h8)) node _store_resp_idx_T_1589 = eq(rob[63].cmd, UInt<4>(0hc)) node _store_resp_idx_T_1590 = eq(rob[63].cmd, UInt<4>(0hd)) node _store_resp_idx_T_1591 = eq(rob[63].cmd, UInt<4>(0he)) node _store_resp_idx_T_1592 = eq(rob[63].cmd, UInt<4>(0hf)) node _store_resp_idx_T_1593 = or(_store_resp_idx_T_1588, _store_resp_idx_T_1589) node _store_resp_idx_T_1594 = or(_store_resp_idx_T_1593, _store_resp_idx_T_1590) node _store_resp_idx_T_1595 = or(_store_resp_idx_T_1594, _store_resp_idx_T_1591) node _store_resp_idx_T_1596 = or(_store_resp_idx_T_1595, _store_resp_idx_T_1592) node _store_resp_idx_T_1597 = or(_store_resp_idx_T_1587, _store_resp_idx_T_1596) node _store_resp_idx_T_1598 = or(_store_resp_idx_T_1580, _store_resp_idx_T_1597) node _store_resp_idx_T_1599 = and(_store_resp_idx_T_1575, _store_resp_idx_T_1598) node _store_resp_idx_T_1600 = mux(_store_resp_idx_T_1574, UInt<6>(0h3e), UInt<6>(0h3f)) node _store_resp_idx_T_1601 = mux(_store_resp_idx_T_1549, UInt<6>(0h3d), _store_resp_idx_T_1600) node _store_resp_idx_T_1602 = mux(_store_resp_idx_T_1524, UInt<6>(0h3c), _store_resp_idx_T_1601) node _store_resp_idx_T_1603 = mux(_store_resp_idx_T_1499, UInt<6>(0h3b), _store_resp_idx_T_1602) node _store_resp_idx_T_1604 = mux(_store_resp_idx_T_1474, UInt<6>(0h3a), _store_resp_idx_T_1603) node _store_resp_idx_T_1605 = mux(_store_resp_idx_T_1449, UInt<6>(0h39), _store_resp_idx_T_1604) node _store_resp_idx_T_1606 = mux(_store_resp_idx_T_1424, UInt<6>(0h38), _store_resp_idx_T_1605) node _store_resp_idx_T_1607 = mux(_store_resp_idx_T_1399, UInt<6>(0h37), _store_resp_idx_T_1606) node _store_resp_idx_T_1608 = mux(_store_resp_idx_T_1374, UInt<6>(0h36), _store_resp_idx_T_1607) node _store_resp_idx_T_1609 = mux(_store_resp_idx_T_1349, UInt<6>(0h35), _store_resp_idx_T_1608) node _store_resp_idx_T_1610 = mux(_store_resp_idx_T_1324, UInt<6>(0h34), _store_resp_idx_T_1609) node _store_resp_idx_T_1611 = mux(_store_resp_idx_T_1299, UInt<6>(0h33), _store_resp_idx_T_1610) node _store_resp_idx_T_1612 = mux(_store_resp_idx_T_1274, UInt<6>(0h32), _store_resp_idx_T_1611) node _store_resp_idx_T_1613 = mux(_store_resp_idx_T_1249, UInt<6>(0h31), _store_resp_idx_T_1612) node _store_resp_idx_T_1614 = mux(_store_resp_idx_T_1224, UInt<6>(0h30), _store_resp_idx_T_1613) node _store_resp_idx_T_1615 = mux(_store_resp_idx_T_1199, UInt<6>(0h2f), _store_resp_idx_T_1614) node _store_resp_idx_T_1616 = mux(_store_resp_idx_T_1174, UInt<6>(0h2e), _store_resp_idx_T_1615) node _store_resp_idx_T_1617 = mux(_store_resp_idx_T_1149, UInt<6>(0h2d), _store_resp_idx_T_1616) node _store_resp_idx_T_1618 = mux(_store_resp_idx_T_1124, UInt<6>(0h2c), _store_resp_idx_T_1617) node _store_resp_idx_T_1619 = mux(_store_resp_idx_T_1099, UInt<6>(0h2b), _store_resp_idx_T_1618) node _store_resp_idx_T_1620 = mux(_store_resp_idx_T_1074, UInt<6>(0h2a), _store_resp_idx_T_1619) node _store_resp_idx_T_1621 = mux(_store_resp_idx_T_1049, UInt<6>(0h29), _store_resp_idx_T_1620) node _store_resp_idx_T_1622 = mux(_store_resp_idx_T_1024, UInt<6>(0h28), _store_resp_idx_T_1621) node _store_resp_idx_T_1623 = mux(_store_resp_idx_T_999, UInt<6>(0h27), _store_resp_idx_T_1622) node _store_resp_idx_T_1624 = mux(_store_resp_idx_T_974, UInt<6>(0h26), _store_resp_idx_T_1623) node _store_resp_idx_T_1625 = mux(_store_resp_idx_T_949, UInt<6>(0h25), _store_resp_idx_T_1624) node _store_resp_idx_T_1626 = mux(_store_resp_idx_T_924, UInt<6>(0h24), _store_resp_idx_T_1625) node _store_resp_idx_T_1627 = mux(_store_resp_idx_T_899, UInt<6>(0h23), _store_resp_idx_T_1626) node _store_resp_idx_T_1628 = mux(_store_resp_idx_T_874, UInt<6>(0h22), _store_resp_idx_T_1627) node _store_resp_idx_T_1629 = mux(_store_resp_idx_T_849, UInt<6>(0h21), _store_resp_idx_T_1628) node _store_resp_idx_T_1630 = mux(_store_resp_idx_T_824, UInt<6>(0h20), _store_resp_idx_T_1629) node _store_resp_idx_T_1631 = mux(_store_resp_idx_T_799, UInt<5>(0h1f), _store_resp_idx_T_1630) node _store_resp_idx_T_1632 = mux(_store_resp_idx_T_774, UInt<5>(0h1e), _store_resp_idx_T_1631) node _store_resp_idx_T_1633 = mux(_store_resp_idx_T_749, UInt<5>(0h1d), _store_resp_idx_T_1632) node _store_resp_idx_T_1634 = mux(_store_resp_idx_T_724, UInt<5>(0h1c), _store_resp_idx_T_1633) node _store_resp_idx_T_1635 = mux(_store_resp_idx_T_699, UInt<5>(0h1b), _store_resp_idx_T_1634) node _store_resp_idx_T_1636 = mux(_store_resp_idx_T_674, UInt<5>(0h1a), _store_resp_idx_T_1635) node _store_resp_idx_T_1637 = mux(_store_resp_idx_T_649, UInt<5>(0h19), _store_resp_idx_T_1636) node _store_resp_idx_T_1638 = mux(_store_resp_idx_T_624, UInt<5>(0h18), _store_resp_idx_T_1637) node _store_resp_idx_T_1639 = mux(_store_resp_idx_T_599, UInt<5>(0h17), _store_resp_idx_T_1638) node _store_resp_idx_T_1640 = mux(_store_resp_idx_T_574, UInt<5>(0h16), _store_resp_idx_T_1639) node _store_resp_idx_T_1641 = mux(_store_resp_idx_T_549, UInt<5>(0h15), _store_resp_idx_T_1640) node _store_resp_idx_T_1642 = mux(_store_resp_idx_T_524, UInt<5>(0h14), _store_resp_idx_T_1641) node _store_resp_idx_T_1643 = mux(_store_resp_idx_T_499, UInt<5>(0h13), _store_resp_idx_T_1642) node _store_resp_idx_T_1644 = mux(_store_resp_idx_T_474, UInt<5>(0h12), _store_resp_idx_T_1643) node _store_resp_idx_T_1645 = mux(_store_resp_idx_T_449, UInt<5>(0h11), _store_resp_idx_T_1644) node _store_resp_idx_T_1646 = mux(_store_resp_idx_T_424, UInt<5>(0h10), _store_resp_idx_T_1645) node _store_resp_idx_T_1647 = mux(_store_resp_idx_T_399, UInt<4>(0hf), _store_resp_idx_T_1646) node _store_resp_idx_T_1648 = mux(_store_resp_idx_T_374, UInt<4>(0he), _store_resp_idx_T_1647) node _store_resp_idx_T_1649 = mux(_store_resp_idx_T_349, UInt<4>(0hd), _store_resp_idx_T_1648) node _store_resp_idx_T_1650 = mux(_store_resp_idx_T_324, UInt<4>(0hc), _store_resp_idx_T_1649) node _store_resp_idx_T_1651 = mux(_store_resp_idx_T_299, UInt<4>(0hb), _store_resp_idx_T_1650) node _store_resp_idx_T_1652 = mux(_store_resp_idx_T_274, UInt<4>(0ha), _store_resp_idx_T_1651) node _store_resp_idx_T_1653 = mux(_store_resp_idx_T_249, UInt<4>(0h9), _store_resp_idx_T_1652) node _store_resp_idx_T_1654 = mux(_store_resp_idx_T_224, UInt<4>(0h8), _store_resp_idx_T_1653) node _store_resp_idx_T_1655 = mux(_store_resp_idx_T_199, UInt<3>(0h7), _store_resp_idx_T_1654) node _store_resp_idx_T_1656 = mux(_store_resp_idx_T_174, UInt<3>(0h6), _store_resp_idx_T_1655) node _store_resp_idx_T_1657 = mux(_store_resp_idx_T_149, UInt<3>(0h5), _store_resp_idx_T_1656) node _store_resp_idx_T_1658 = mux(_store_resp_idx_T_124, UInt<3>(0h4), _store_resp_idx_T_1657) node _store_resp_idx_T_1659 = mux(_store_resp_idx_T_99, UInt<2>(0h3), _store_resp_idx_T_1658) node _store_resp_idx_T_1660 = mux(_store_resp_idx_T_74, UInt<2>(0h2), _store_resp_idx_T_1659) node _store_resp_idx_T_1661 = mux(_store_resp_idx_T_49, UInt<1>(0h1), _store_resp_idx_T_1660) node store_resp_idx = mux(_store_resp_idx_T_24, UInt<1>(0h0), _store_resp_idx_T_1661) node _can_do_store_resp_T = not(rob_respd[store_resp_idx]) node _can_do_store_resp_T_1 = eq(rob[store_resp_idx].cmd, UInt<1>(0h1)) node _can_do_store_resp_T_2 = eq(rob[store_resp_idx].cmd, UInt<5>(0h11)) node _can_do_store_resp_T_3 = or(_can_do_store_resp_T_1, _can_do_store_resp_T_2) node _can_do_store_resp_T_4 = eq(rob[store_resp_idx].cmd, UInt<3>(0h7)) node _can_do_store_resp_T_5 = or(_can_do_store_resp_T_3, _can_do_store_resp_T_4) node _can_do_store_resp_T_6 = eq(rob[store_resp_idx].cmd, UInt<3>(0h4)) node _can_do_store_resp_T_7 = eq(rob[store_resp_idx].cmd, UInt<4>(0h9)) node _can_do_store_resp_T_8 = eq(rob[store_resp_idx].cmd, UInt<4>(0ha)) node _can_do_store_resp_T_9 = eq(rob[store_resp_idx].cmd, UInt<4>(0hb)) node _can_do_store_resp_T_10 = or(_can_do_store_resp_T_6, _can_do_store_resp_T_7) node _can_do_store_resp_T_11 = or(_can_do_store_resp_T_10, _can_do_store_resp_T_8) node _can_do_store_resp_T_12 = or(_can_do_store_resp_T_11, _can_do_store_resp_T_9) node _can_do_store_resp_T_13 = eq(rob[store_resp_idx].cmd, UInt<4>(0h8)) node _can_do_store_resp_T_14 = eq(rob[store_resp_idx].cmd, UInt<4>(0hc)) node _can_do_store_resp_T_15 = eq(rob[store_resp_idx].cmd, UInt<4>(0hd)) node _can_do_store_resp_T_16 = eq(rob[store_resp_idx].cmd, UInt<4>(0he)) node _can_do_store_resp_T_17 = eq(rob[store_resp_idx].cmd, UInt<4>(0hf)) node _can_do_store_resp_T_18 = or(_can_do_store_resp_T_13, _can_do_store_resp_T_14) node _can_do_store_resp_T_19 = or(_can_do_store_resp_T_18, _can_do_store_resp_T_15) node _can_do_store_resp_T_20 = or(_can_do_store_resp_T_19, _can_do_store_resp_T_16) node _can_do_store_resp_T_21 = or(_can_do_store_resp_T_20, _can_do_store_resp_T_17) node _can_do_store_resp_T_22 = or(_can_do_store_resp_T_12, _can_do_store_resp_T_21) node _can_do_store_resp_T_23 = or(_can_do_store_resp_T_5, _can_do_store_resp_T_22) node _can_do_store_resp_T_24 = and(_can_do_store_resp_T, _can_do_store_resp_T_23) node _can_do_store_resp_T_25 = eq(rob[store_resp_idx].cmd, UInt<1>(0h0)) node _can_do_store_resp_T_26 = eq(rob[store_resp_idx].cmd, UInt<5>(0h10)) node _can_do_store_resp_T_27 = eq(rob[store_resp_idx].cmd, UInt<3>(0h6)) node _can_do_store_resp_T_28 = eq(rob[store_resp_idx].cmd, UInt<3>(0h7)) node _can_do_store_resp_T_29 = or(_can_do_store_resp_T_25, _can_do_store_resp_T_26) node _can_do_store_resp_T_30 = or(_can_do_store_resp_T_29, _can_do_store_resp_T_27) node _can_do_store_resp_T_31 = or(_can_do_store_resp_T_30, _can_do_store_resp_T_28) node _can_do_store_resp_T_32 = eq(rob[store_resp_idx].cmd, UInt<3>(0h4)) node _can_do_store_resp_T_33 = eq(rob[store_resp_idx].cmd, UInt<4>(0h9)) node _can_do_store_resp_T_34 = eq(rob[store_resp_idx].cmd, UInt<4>(0ha)) node _can_do_store_resp_T_35 = eq(rob[store_resp_idx].cmd, UInt<4>(0hb)) node _can_do_store_resp_T_36 = or(_can_do_store_resp_T_32, _can_do_store_resp_T_33) node _can_do_store_resp_T_37 = or(_can_do_store_resp_T_36, _can_do_store_resp_T_34) node _can_do_store_resp_T_38 = or(_can_do_store_resp_T_37, _can_do_store_resp_T_35) node _can_do_store_resp_T_39 = eq(rob[store_resp_idx].cmd, UInt<4>(0h8)) node _can_do_store_resp_T_40 = eq(rob[store_resp_idx].cmd, UInt<4>(0hc)) node _can_do_store_resp_T_41 = eq(rob[store_resp_idx].cmd, UInt<4>(0hd)) node _can_do_store_resp_T_42 = eq(rob[store_resp_idx].cmd, UInt<4>(0he)) node _can_do_store_resp_T_43 = eq(rob[store_resp_idx].cmd, UInt<4>(0hf)) node _can_do_store_resp_T_44 = or(_can_do_store_resp_T_39, _can_do_store_resp_T_40) node _can_do_store_resp_T_45 = or(_can_do_store_resp_T_44, _can_do_store_resp_T_41) node _can_do_store_resp_T_46 = or(_can_do_store_resp_T_45, _can_do_store_resp_T_42) node _can_do_store_resp_T_47 = or(_can_do_store_resp_T_46, _can_do_store_resp_T_43) node _can_do_store_resp_T_48 = or(_can_do_store_resp_T_38, _can_do_store_resp_T_47) node _can_do_store_resp_T_49 = or(_can_do_store_resp_T_31, _can_do_store_resp_T_48) node _can_do_store_resp_T_50 = eq(_can_do_store_resp_T_49, UInt<1>(0h0)) node can_do_store_resp = and(_can_do_store_resp_T_24, _can_do_store_resp_T_50) node _T_28 = eq(io.lsu.exe[0].iresp.valid, UInt<1>(0h0)) node _T_29 = and(can_do_store_resp, _T_28) when _T_29 : connect rob_respd[store_resp_idx], UInt<1>(0h1) connect io.tracegen.resp.valid, UInt<1>(0h1) connect io.tracegen.resp.bits.tag, rob[store_resp_idx].tag when io.lsu.exe[0].iresp.valid : connect rob_respd[io.lsu.exe[0].iresp.bits.uop.rob_idx], UInt<1>(0h1) connect io.lsu.exe[0].fresp.ready, UInt<1>(0h1) connect io.lsu.exe[0].iresp.ready, UInt<1>(0h1) connect io.lsu.exception, UInt<1>(0h0) connect io.lsu.fence_dmem, UInt<1>(0h0) connect io.lsu.rob_pnr_idx, rob_tail connect io.lsu.commit_load_at_rob_head, UInt<1>(0h0) wire _io_lsu_brupdate_b1_WIRE : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>} connect _io_lsu_brupdate_b1_WIRE.mispredict_mask, UInt<4>(0h0) connect _io_lsu_brupdate_b1_WIRE.resolve_mask, UInt<4>(0h0) connect io.lsu.brupdate.b1, _io_lsu_brupdate_b1_WIRE invalidate io.lsu.brupdate.b2.uop.debug_tsrc invalidate io.lsu.brupdate.b2.uop.debug_fsrc invalidate io.lsu.brupdate.b2.uop.bp_xcpt_if invalidate io.lsu.brupdate.b2.uop.bp_debug_if invalidate io.lsu.brupdate.b2.uop.xcpt_ma_if invalidate io.lsu.brupdate.b2.uop.xcpt_ae_if invalidate io.lsu.brupdate.b2.uop.xcpt_pf_if invalidate io.lsu.brupdate.b2.uop.fp_single invalidate io.lsu.brupdate.b2.uop.fp_val invalidate io.lsu.brupdate.b2.uop.frs3_en invalidate io.lsu.brupdate.b2.uop.lrs2_rtype invalidate io.lsu.brupdate.b2.uop.lrs1_rtype invalidate io.lsu.brupdate.b2.uop.dst_rtype invalidate io.lsu.brupdate.b2.uop.ldst_val invalidate io.lsu.brupdate.b2.uop.lrs3 invalidate io.lsu.brupdate.b2.uop.lrs2 invalidate io.lsu.brupdate.b2.uop.lrs1 invalidate io.lsu.brupdate.b2.uop.ldst invalidate io.lsu.brupdate.b2.uop.ldst_is_rs1 invalidate io.lsu.brupdate.b2.uop.flush_on_commit invalidate io.lsu.brupdate.b2.uop.is_unique invalidate io.lsu.brupdate.b2.uop.is_sys_pc2epc invalidate io.lsu.brupdate.b2.uop.uses_stq invalidate io.lsu.brupdate.b2.uop.uses_ldq invalidate io.lsu.brupdate.b2.uop.is_amo invalidate io.lsu.brupdate.b2.uop.is_fencei invalidate io.lsu.brupdate.b2.uop.is_fence invalidate io.lsu.brupdate.b2.uop.mem_signed invalidate io.lsu.brupdate.b2.uop.mem_size invalidate io.lsu.brupdate.b2.uop.mem_cmd invalidate io.lsu.brupdate.b2.uop.bypassable invalidate io.lsu.brupdate.b2.uop.exc_cause invalidate io.lsu.brupdate.b2.uop.exception invalidate io.lsu.brupdate.b2.uop.stale_pdst invalidate io.lsu.brupdate.b2.uop.ppred_busy invalidate io.lsu.brupdate.b2.uop.prs3_busy invalidate io.lsu.brupdate.b2.uop.prs2_busy invalidate io.lsu.brupdate.b2.uop.prs1_busy invalidate io.lsu.brupdate.b2.uop.ppred invalidate io.lsu.brupdate.b2.uop.prs3 invalidate io.lsu.brupdate.b2.uop.prs2 invalidate io.lsu.brupdate.b2.uop.prs1 invalidate io.lsu.brupdate.b2.uop.pdst invalidate io.lsu.brupdate.b2.uop.rxq_idx invalidate io.lsu.brupdate.b2.uop.stq_idx invalidate io.lsu.brupdate.b2.uop.ldq_idx invalidate io.lsu.brupdate.b2.uop.rob_idx invalidate io.lsu.brupdate.b2.uop.csr_addr invalidate io.lsu.brupdate.b2.uop.imm_packed invalidate io.lsu.brupdate.b2.uop.taken invalidate io.lsu.brupdate.b2.uop.pc_lob invalidate io.lsu.brupdate.b2.uop.edge_inst invalidate io.lsu.brupdate.b2.uop.ftq_idx invalidate io.lsu.brupdate.b2.uop.br_tag invalidate io.lsu.brupdate.b2.uop.br_mask invalidate io.lsu.brupdate.b2.uop.is_sfb invalidate io.lsu.brupdate.b2.uop.is_jal invalidate io.lsu.brupdate.b2.uop.is_jalr invalidate io.lsu.brupdate.b2.uop.is_br invalidate io.lsu.brupdate.b2.uop.iw_p2_poisoned invalidate io.lsu.brupdate.b2.uop.iw_p1_poisoned invalidate io.lsu.brupdate.b2.uop.iw_state invalidate io.lsu.brupdate.b2.uop.ctrl.is_std invalidate io.lsu.brupdate.b2.uop.ctrl.is_sta invalidate io.lsu.brupdate.b2.uop.ctrl.is_load invalidate io.lsu.brupdate.b2.uop.ctrl.csr_cmd invalidate io.lsu.brupdate.b2.uop.ctrl.fcn_dw invalidate io.lsu.brupdate.b2.uop.ctrl.op_fcn invalidate io.lsu.brupdate.b2.uop.ctrl.imm_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op2_sel invalidate io.lsu.brupdate.b2.uop.ctrl.op1_sel invalidate io.lsu.brupdate.b2.uop.ctrl.br_type invalidate io.lsu.brupdate.b2.uop.fu_code invalidate io.lsu.brupdate.b2.uop.iq_type invalidate io.lsu.brupdate.b2.uop.debug_pc invalidate io.lsu.brupdate.b2.uop.is_rvc invalidate io.lsu.brupdate.b2.uop.debug_inst invalidate io.lsu.brupdate.b2.uop.inst invalidate io.lsu.brupdate.b2.uop.uopc connect io.lsu.brupdate.b2.mispredict, UInt<1>(0h0) connect io.lsu.brupdate.b2.taken, UInt<1>(0h0) connect io.lsu.brupdate.b2.cfi_type, UInt<1>(0h0) connect io.lsu.brupdate.b2.pc_sel, UInt<1>(0h0) connect io.lsu.brupdate.b2.jalr_target, UInt<1>(0h0) connect io.lsu.brupdate.b2.target_offset, asSInt(UInt<2>(0h0)) connect io.lsu.rob_head_idx, rob_head node _io_tracegen_ordered_T = and(ready_for_amo, io.lsu.fencei_rdy) connect io.tracegen.ordered, _io_tracegen_ordered_T

module BoomLSUShim_1( // @[tracegen.scala:20:7] input clock, // @[tracegen.scala:20:7] input reset, // @[tracegen.scala:20:7] output io_lsu_exe_0_req_valid, // @[tracegen.scala:22:14] output [6:0] io_lsu_exe_0_req_bits_uop_uopc, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] output [5:0] io_lsu_exe_0_req_bits_uop_rob_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_exe_0_req_bits_uop_ldq_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_exe_0_req_bits_uop_stq_idx, // @[tracegen.scala:22:14] output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_is_amo, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_uses_ldq, // @[tracegen.scala:22:14] output io_lsu_exe_0_req_bits_uop_uses_stq, // @[tracegen.scala:22:14] output [63:0] io_lsu_exe_0_req_bits_data, // @[tracegen.scala:22:14] output [33:0] io_lsu_exe_0_req_bits_addr, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_inst, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_rvc, // @[tracegen.scala:22:14] input [33:0] io_lsu_exe_0_iresp_bits_uop_debug_pc, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type, // @[tracegen.scala:22:14] input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_br, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_jalr, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_jal, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_sfb, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_br_mask, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_br_tag, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_edge_inst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_taken, // @[tracegen.scala:22:14] input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed, // @[tracegen.scala:22:14] input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_rob_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_stq_idx, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_pdst, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs1, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs2, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs3, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ppred, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_prs1_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_prs2_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_prs3_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ppred_busy, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_exception, // @[tracegen.scala:22:14] input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_bypassable, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_mem_signed, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_fence, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_fencei, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_amo, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_uses_ldq, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_uses_stq, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_is_unique, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_flush_on_commit, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_ldst_val, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_frs3_en, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_fp_val, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_fp_single, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_bp_debug_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc, // @[tracegen.scala:22:14] input [63:0] io_lsu_exe_0_iresp_bits_data, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_inst, // @[tracegen.scala:22:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_rvc, // @[tracegen.scala:22:14] input [33:0] io_lsu_exe_0_fresp_bits_uop_debug_pc, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type, // @[tracegen.scala:22:14] input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_br, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_jalr, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_jal, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_sfb, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_br_mask, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_br_tag, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_edge_inst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_taken, // @[tracegen.scala:22:14] input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed, // @[tracegen.scala:22:14] input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_rob_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_stq_idx, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_pdst, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs1, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs2, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs3, // @[tracegen.scala:22:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ppred, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_prs1_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_prs2_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_prs3_busy, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ppred_busy, // @[tracegen.scala:22:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_exception, // @[tracegen.scala:22:14] input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_bypassable, // @[tracegen.scala:22:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_mem_signed, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_fence, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_fencei, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_amo, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_uses_ldq, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_uses_stq, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_is_unique, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_flush_on_commit, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2, // @[tracegen.scala:22:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_ldst_val, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_frs3_en, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_fp_val, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_fp_single, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_bp_debug_if, // @[tracegen.scala:22:14] input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc, // @[tracegen.scala:22:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc, // @[tracegen.scala:22:14] input [64:0] io_lsu_exe_0_fresp_bits_data, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_valid, // @[tracegen.scala:22:14] output [6:0] io_lsu_dis_uops_0_bits_uopc, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_ctrl_is_load, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_ctrl_is_sta, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_ctrl_is_std, // @[tracegen.scala:22:14] output [5:0] io_lsu_dis_uops_0_bits_rob_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_dis_uops_0_bits_stq_idx, // @[tracegen.scala:22:14] output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_is_amo, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_uses_ldq, // @[tracegen.scala:22:14] output io_lsu_dis_uops_0_bits_uses_stq, // @[tracegen.scala:22:14] input [3:0] io_lsu_dis_ldq_idx_0, // @[tracegen.scala:22:14] input [3:0] io_lsu_dis_stq_idx_0, // @[tracegen.scala:22:14] input io_lsu_ldq_full_0, // @[tracegen.scala:22:14] input io_lsu_stq_full_0, // @[tracegen.scala:22:14] input io_lsu_fp_stdata_ready, // @[tracegen.scala:22:14] output io_lsu_commit_valids_0, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_uopc, // @[tracegen.scala:22:14] output [31:0] io_lsu_commit_uops_0_inst, // @[tracegen.scala:22:14] output [31:0] io_lsu_commit_uops_0_debug_inst, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_rvc, // @[tracegen.scala:22:14] output [33:0] io_lsu_commit_uops_0_debug_pc, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_iq_type, // @[tracegen.scala:22:14] output [9:0] io_lsu_commit_uops_0_fu_code, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ctrl_br_type, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel, // @[tracegen.scala:22:14] output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_fcn_dw, // @[tracegen.scala:22:14] output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_is_load, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_is_sta, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ctrl_is_std, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_iw_state, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_iw_p1_poisoned, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_iw_p2_poisoned, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_br, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_jalr, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_jal, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_sfb, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_br_mask, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_br_tag, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ftq_idx, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_edge_inst, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_pc_lob, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_taken, // @[tracegen.scala:22:14] output [19:0] io_lsu_commit_uops_0_imm_packed, // @[tracegen.scala:22:14] output [11:0] io_lsu_commit_uops_0_csr_addr, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_rob_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ldq_idx, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_stq_idx, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_pdst, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_prs1, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_prs2, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_prs3, // @[tracegen.scala:22:14] output [3:0] io_lsu_commit_uops_0_ppred, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_prs1_busy, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_prs2_busy, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_prs3_busy, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ppred_busy, // @[tracegen.scala:22:14] output [6:0] io_lsu_commit_uops_0_stale_pdst, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_exception, // @[tracegen.scala:22:14] output [63:0] io_lsu_commit_uops_0_exc_cause, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_bypassable, // @[tracegen.scala:22:14] output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_mem_size, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_mem_signed, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_fence, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_fencei, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_amo, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_uses_ldq, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_uses_stq, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_sys_pc2epc, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_is_unique, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_flush_on_commit, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ldst_is_rs1, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_ldst, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_lrs1, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_lrs2, // @[tracegen.scala:22:14] output [5:0] io_lsu_commit_uops_0_lrs3, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_ldst_val, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_frs3_en, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_fp_val, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_fp_single, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_xcpt_pf_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_xcpt_ae_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_xcpt_ma_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_bp_debug_if, // @[tracegen.scala:22:14] output io_lsu_commit_uops_0_bp_xcpt_if, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_debug_fsrc, // @[tracegen.scala:22:14] output [1:0] io_lsu_commit_uops_0_debug_tsrc, // @[tracegen.scala:22:14] input io_lsu_clr_bsy_0_valid, // @[tracegen.scala:22:14] input [5:0] io_lsu_clr_bsy_0_bits, // @[tracegen.scala:22:14] input io_lsu_clr_bsy_1_valid, // @[tracegen.scala:22:14] input [5:0] io_lsu_clr_bsy_1_bits, // @[tracegen.scala:22:14] input [5:0] io_lsu_clr_unsafe_0_bits, // @[tracegen.scala:22:14] input io_lsu_spec_ld_wakeup_0_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_spec_ld_wakeup_0_bits, // @[tracegen.scala:22:14] input io_lsu_ld_miss, // @[tracegen.scala:22:14] output [5:0] io_lsu_rob_pnr_idx, // @[tracegen.scala:22:14] output [5:0] io_lsu_rob_head_idx, // @[tracegen.scala:22:14] input io_lsu_fencei_rdy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_valid, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_uopc, // @[tracegen.scala:22:14] input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[tracegen.scala:22:14] input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_rvc, // @[tracegen.scala:22:14] input [33:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_iq_type, // @[tracegen.scala:22:14] input [9:0] io_lsu_lxcpt_bits_uop_fu_code, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14] input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_iw_state, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_br, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_jalr, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_jal, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_sfb, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_br_mask, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_br_tag, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_edge_inst, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_taken, // @[tracegen.scala:22:14] input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[tracegen.scala:22:14] input [11:0] io_lsu_lxcpt_bits_uop_csr_addr, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_pdst, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_prs1, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_prs2, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_prs3, // @[tracegen.scala:22:14] input [3:0] io_lsu_lxcpt_bits_uop_ppred, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_prs1_busy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_prs2_busy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_prs3_busy, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ppred_busy, // @[tracegen.scala:22:14] input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_exception, // @[tracegen.scala:22:14] input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_bypassable, // @[tracegen.scala:22:14] input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_mem_signed, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_fence, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_fencei, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_amo, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_uses_ldq, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_uses_stq, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_is_unique, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[tracegen.scala:22:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_ldst_val, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_frs3_en, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_fp_val, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_fp_single, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[tracegen.scala:22:14] input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[tracegen.scala:22:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[tracegen.scala:22:14] input [4:0] io_lsu_lxcpt_bits_cause, // @[tracegen.scala:22:14] input [33:0] io_lsu_lxcpt_bits_badvaddr, // @[tracegen.scala:22:14] input io_lsu_perf_acquire, // @[tracegen.scala:22:14] input io_lsu_perf_release, // @[tracegen.scala:22:14] output io_tracegen_req_ready, // @[tracegen.scala:22:14] input io_tracegen_req_valid, // @[tracegen.scala:22:14] input [33:0] io_tracegen_req_bits_addr, // @[tracegen.scala:22:14] input [5:0] io_tracegen_req_bits_tag, // @[tracegen.scala:22:14] input [4:0] io_tracegen_req_bits_cmd, // @[tracegen.scala:22:14] input [63:0] io_tracegen_req_bits_data, // @[tracegen.scala:22:14] input [63:0] io_tracegen_s1_data_data, // @[tracegen.scala:22:14] output io_tracegen_resp_valid, // @[tracegen.scala:22:14] output [5:0] io_tracegen_resp_bits_tag, // @[tracegen.scala:22:14] output [1:0] io_tracegen_resp_bits_size, // @[tracegen.scala:22:14] output [63:0] io_tracegen_resp_bits_data, // @[tracegen.scala:22:14] output io_tracegen_ordered // @[tracegen.scala:22:14] ); wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc; // @[tracegen.scala:20:7] wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[tracegen.scala:20:7] wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[tracegen.scala:20:7] wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready; // @[tracegen.scala:20:7] wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[tracegen.scala:20:7] wire [5:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[tracegen.scala:20:7] wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[tracegen.scala:20:7] wire [5:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[tracegen.scala:20:7] wire [5:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[tracegen.scala:20:7] wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits; // @[tracegen.scala:20:7] wire io_lsu_ld_miss_0 = io_lsu_ld_miss; // @[tracegen.scala:20:7] wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc; // @[tracegen.scala:20:7] wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[tracegen.scala:20:7] wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:20:7] wire [33:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type; // @[tracegen.scala:20:7] wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7] wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[tracegen.scala:20:7] wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:20:7] wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[tracegen.scala:20:7] wire [3:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:20:7] wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[tracegen.scala:20:7] wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable; // @[tracegen.scala:20:7] wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[tracegen.scala:20:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:20:7] wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:20:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:20:7] wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[tracegen.scala:20:7] wire [33:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[tracegen.scala:20:7] wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[tracegen.scala:20:7] wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[tracegen.scala:20:7] wire io_tracegen_req_valid_0 = io_tracegen_req_valid; // @[tracegen.scala:20:7] wire [33:0] io_tracegen_req_bits_addr_0 = io_tracegen_req_bits_addr; // @[tracegen.scala:20:7] wire [5:0] io_tracegen_req_bits_tag_0 = io_tracegen_req_bits_tag; // @[tracegen.scala:20:7] wire [4:0] io_tracegen_req_bits_cmd_0 = io_tracegen_req_bits_cmd; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_req_bits_data_0 = io_tracegen_req_bits_data; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_s1_data_data_0 = io_tracegen_s1_data_data; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_dis_uops_0_bits_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_dis_uops_0_bits_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_commit_uops_0_inst_0 = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_commit_uops_0_debug_inst_0 = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_commit_debug_insts_0 = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7] wire [31:0] io_tracegen_s2_paddr = 32'h0; // @[tracegen.scala:20:7] wire [31:0] _tracegen_uop_WIRE_inst = 32'h0; // @[tracegen.scala:57:45] wire [31:0] _tracegen_uop_WIRE_debug_inst = 32'h0; // @[tracegen.scala:57:45] wire [31:0] tracegen_uop_inst = 32'h0; // @[tracegen.scala:57:30] wire [31:0] tracegen_uop_debug_inst = 32'h0; // @[tracegen.scala:57:30] wire io_lsu_exe_0_req_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_mxcpt_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs2 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_asid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_predicated = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_arch_valids_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_rvc_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_fcn_dw_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_iw_p1_poisoned_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_iw_p2_poisoned_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_br_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_jalr_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_jal_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_sfb_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_edge_inst_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_taken_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_prs1_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_prs2_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_prs3_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ppred_busy_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_exception_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_bypassable_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_mem_signed_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_fence_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_fencei_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_sys_pc2epc_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_unique_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_flush_on_commit_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ldst_is_rs1_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ldst_val_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_frs3_en_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_fp_val_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_fp_single_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_xcpt_pf_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_xcpt_ae_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_xcpt_ma_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_bp_debug_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_bp_xcpt_if_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_fflags_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_rbk_valids_0 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_rollback = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_commit_load_at_rob_head = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_fence_dmem = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_br = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_jal = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_bypassable = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_fence = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_amo = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_is_unique = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_fp_val = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_fp_single = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_valid = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_mispredict = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_brupdate_b2_taken = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_exception = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_tsc_reg = 1'h0; // @[tracegen.scala:20:7] wire io_lsu_perf_tlbMiss = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_signed = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_dv = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_phys = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_no_resp = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_no_alloc = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_req_bits_no_xcpt = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s1_kill = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_nack = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_nack_cause_raw = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_kill = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_uncached = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_signed = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_dv = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_replay = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_resp_bits_has_data = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_replay_next = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ma_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ma_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_pf_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_pf_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_gf_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_gf_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ae_ld = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_xcpt_ae_st = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_s2_gpa_is_pte = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_store_pending = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_acquire = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_release = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_grant = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_tlbMiss = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_blocked = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_canAcceptStoreThenLoad = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_canAcceptStoreThenRMW = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_canAcceptLoadThenLoad = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_storeBufferEmptyAfterLoad = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_perf_storeBufferEmptyAfterStore = 1'h0; // @[tracegen.scala:20:7] wire io_tracegen_clock_enabled = 1'h0; // @[tracegen.scala:20:7] wire _rob_bsy_WIRE_0 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_1 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_2 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_3 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_4 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_5 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_6 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_7 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_8 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_9 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_10 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_11 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_12 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_13 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_14 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_15 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_16 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_17 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_18 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_19 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_20 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_21 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_22 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_23 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_24 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_25 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_26 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_27 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_28 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_29 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_30 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_31 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_32 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_33 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_34 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_35 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_36 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_37 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_38 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_39 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_40 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_41 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_42 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_43 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_44 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_45 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_46 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_47 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_48 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_49 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_50 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_51 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_52 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_53 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_54 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_55 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_56 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_57 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_58 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_59 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_60 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_61 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_62 = 1'h0; // @[tracegen.scala:35:33] wire _rob_bsy_WIRE_63 = 1'h0; // @[tracegen.scala:35:33] wire _tracegen_uop_WIRE_is_rvc = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_is_load = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_is_sta = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ctrl_is_std = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_iw_p1_poisoned = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_iw_p2_poisoned = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_br = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_jalr = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_jal = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_sfb = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_edge_inst = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_taken = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_prs1_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_prs2_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_prs3_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ppred_busy = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_exception = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_bypassable = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_mem_signed = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_fence = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_fencei = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_amo = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_uses_ldq = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_uses_stq = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_sys_pc2epc = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_is_unique = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_flush_on_commit = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ldst_is_rs1 = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_ldst_val = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_frs3_en = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_fp_val = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_fp_single = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_xcpt_pf_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_xcpt_ae_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_xcpt_ma_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_bp_debug_if = 1'h0; // @[tracegen.scala:57:45] wire _tracegen_uop_WIRE_bp_xcpt_if = 1'h0; // @[tracegen.scala:57:45] wire tracegen_uop_is_rvc = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_br = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_jalr = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_jal = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_sfb = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_edge_inst = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_taken = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_prs1_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_prs2_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_prs3_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ppred_busy = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_exception = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_bypassable = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_mem_signed = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_fence = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_fencei = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_is_unique = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_flush_on_commit = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_ldst_val = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_frs3_en = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_fp_val = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_fp_single = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_bp_debug_if = 1'h0; // @[tracegen.scala:57:30] wire tracegen_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:57:30] wire [33:0] io_lsu_exe_0_req_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_dis_uops_0_bits_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_fp_stdata_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_commit_uops_0_debug_pc_0 = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_tracegen_resp_bits_addr = 34'h0; // @[tracegen.scala:20:7] wire [33:0] io_tracegen_s2_gpa = 34'h0; // @[tracegen.scala:20:7] wire [33:0] _tracegen_uop_WIRE_debug_pc = 34'h0; // @[tracegen.scala:57:45] wire [33:0] tracegen_uop_debug_pc = 34'h0; // @[tracegen.scala:57:30] wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_iq_type_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0 = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_iq_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7] wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0; // @[tracegen.scala:20:7] wire [2:0] _tracegen_uop_WIRE_iq_type = 3'h0; // @[tracegen.scala:57:45] wire [2:0] _tracegen_uop_WIRE_ctrl_op2_sel = 3'h0; // @[tracegen.scala:57:45] wire [2:0] _tracegen_uop_WIRE_ctrl_imm_sel = 3'h0; // @[tracegen.scala:57:45] wire [2:0] _tracegen_uop_WIRE_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:57:45] wire [2:0] tracegen_uop_iq_type = 3'h0; // @[tracegen.scala:57:30] wire [2:0] tracegen_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:57:30] wire [2:0] tracegen_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:57:30] wire [2:0] tracegen_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:57:30] wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_dis_uops_0_bits_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_commit_uops_0_fu_code_0 = 10'h0; // @[tracegen.scala:20:7] wire [9:0] io_lsu_brupdate_b2_uop_fu_code = 10'h0; // @[tracegen.scala:20:7] wire [9:0] _tracegen_uop_WIRE_fu_code = 10'h0; // @[tracegen.scala:57:45] wire [9:0] tracegen_uop_fu_code = 10'h0; // @[tracegen.scala:57:30] wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_br_mask_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ftq_idx_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ppred_0 = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0; // @[tracegen.scala:20:7] wire [3:0] _tracegen_uop_WIRE_ctrl_br_type = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_br_mask = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_ftq_idx = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_ldq_idx = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_stq_idx = 4'h0; // @[tracegen.scala:57:45] wire [3:0] _tracegen_uop_WIRE_ppred = 4'h0; // @[tracegen.scala:57:45] wire [3:0] tracegen_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_br_mask = 4'h0; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_ftq_idx = 4'h0; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_ppred = 4'h0; // @[tracegen.scala:57:30] wire [3:0] _io_lsu_brupdate_b1_WIRE_resolve_mask = 4'h0; // @[tracegen.scala:153:39] wire [3:0] _io_lsu_brupdate_b1_WIRE_mispredict_mask = 4'h0; // @[tracegen.scala:153:39] wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_iw_state_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_br_tag_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_rxq_idx_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_dst_rtype_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0 = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_iw_state = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_lsu_brupdate_b2_target_offset = 2'h0; // @[tracegen.scala:20:7] wire [1:0] io_tracegen_resp_bits_dprv = 2'h0; // @[tracegen.scala:20:7] wire [1:0] _tracegen_uop_WIRE_ctrl_op1_sel = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_iw_state = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_br_tag = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_rxq_idx = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_mem_size = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_dst_rtype = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_lrs1_rtype = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_lrs2_rtype = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_debug_fsrc = 2'h0; // @[tracegen.scala:57:45] wire [1:0] _tracegen_uop_WIRE_debug_tsrc = 2'h0; // @[tracegen.scala:57:45] wire [1:0] tracegen_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_iw_state = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_br_tag = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_rxq_idx = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_dst_rtype = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_debug_fsrc = 2'h0; // @[tracegen.scala:57:30] wire [1:0] tracegen_uop_debug_tsrc = 2'h0; // @[tracegen.scala:57:30] wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0 = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_commit_fflags_bits = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] io_tracegen_resp_bits_cmd = 5'h0; // @[tracegen.scala:20:7] wire [4:0] _tracegen_uop_WIRE_ctrl_op_fcn = 5'h0; // @[tracegen.scala:57:45] wire [4:0] _tracegen_uop_WIRE_mem_cmd = 5'h0; // @[tracegen.scala:57:45] wire [4:0] tracegen_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:57:30] wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_pc_lob_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_ldst_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_lrs1_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_lrs2_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_lrs3_0 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7] wire [5:0] _tracegen_uop_WIRE_pc_lob = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_rob_idx = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_ldst = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_lrs1 = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_lrs2 = 6'h0; // @[tracegen.scala:57:45] wire [5:0] _tracegen_uop_WIRE_lrs3 = 6'h0; // @[tracegen.scala:57:45] wire [5:0] tracegen_uop_pc_lob = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_ldst = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_lrs1 = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_lrs2 = 6'h0; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_lrs3 = 6'h0; // @[tracegen.scala:57:30] wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_dis_uops_0_bits_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_commit_uops_0_imm_packed_0 = 20'h0; // @[tracegen.scala:20:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7] wire [19:0] _tracegen_uop_WIRE_imm_packed = 20'h0; // @[tracegen.scala:57:45] wire [19:0] tracegen_uop_imm_packed = 20'h0; // @[tracegen.scala:57:30] wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_dis_uops_0_bits_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_commit_uops_0_csr_addr_0 = 12'h0; // @[tracegen.scala:20:7] wire [11:0] io_lsu_brupdate_b2_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7] wire [11:0] _tracegen_uop_WIRE_csr_addr = 12'h0; // @[tracegen.scala:57:45] wire [11:0] tracegen_uop_csr_addr = 12'h0; // @[tracegen.scala:57:30] wire [6:0] io_lsu_exe_0_req_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_pdst_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_prs1_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_prs2_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_prs3_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_stale_pdst_0 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_uopc = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_prs1 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_prs2 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_prs3 = 7'h0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7] wire [6:0] _tracegen_uop_WIRE_uopc = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_pdst = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_prs1 = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_prs2 = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_prs3 = 7'h0; // @[tracegen.scala:57:45] wire [6:0] _tracegen_uop_WIRE_stale_pdst = 7'h0; // @[tracegen.scala:57:45] wire [6:0] tracegen_uop_pdst = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_prs1 = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_prs2 = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_prs3 = 7'h0; // @[tracegen.scala:57:30] wire [6:0] tracegen_uop_stale_pdst = 7'h0; // @[tracegen.scala:57:30] wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_dis_uops_0_bits_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_fp_stdata_bits_data = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_commit_uops_0_exc_cause_0 = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_commit_debug_wdata_0 = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_data_word_bypass = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_data_raw = 64'h0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_store_data = 64'h0; // @[tracegen.scala:20:7] wire [63:0] _tracegen_uop_WIRE_exc_cause = 64'h0; // @[tracegen.scala:57:45] wire [63:0] tracegen_uop_exc_cause = 64'h0; // @[tracegen.scala:57:30] wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_lsu_dis_uops_0_bits_mem_size = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_lsu_commit_uops_0_mem_size_0 = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_tracegen_req_bits_size = 2'h3; // @[tracegen.scala:20:7] wire [1:0] io_tracegen_req_bits_dprv = 2'h3; // @[tracegen.scala:20:7] wire [1:0] tracegen_uop_mem_size = 2'h3; // @[tracegen.scala:57:30] wire [7:0] io_tracegen_req_bits_mask = 8'hFF; // @[tracegen.scala:20:7] wire [7:0] io_tracegen_s1_data_mask = 8'hFF; // @[tracegen.scala:20:7] wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits = 25'h0; // @[tracegen.scala:20:7] wire [32:0] io_lsu_exe_0_req_bits_sfence_bits_addr = 33'h0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_iresp_ready = 1'h1; // @[tracegen.scala:20:7] wire io_lsu_exe_0_fresp_ready = 1'h1; // @[tracegen.scala:20:7] wire io_tracegen_keep_clock_enabled = 1'h1; // @[tracegen.scala:20:7] wire _rob_respd_T_1 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_2 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_3 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_4 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_5 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_6 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_7 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_8 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_9 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_10 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_11 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_12 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_13 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_14 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_15 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_16 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_17 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_18 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_19 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_20 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_21 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_22 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_23 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_24 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_25 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_26 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_27 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_28 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_29 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_30 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_31 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_32 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_33 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_34 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_35 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_36 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_37 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_38 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_39 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_40 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_41 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_42 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_43 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_44 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_45 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_46 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_47 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_48 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_49 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_50 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_51 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_52 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_53 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_54 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_55 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_56 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_57 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_58 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_59 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_60 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_61 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_62 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_63 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_T_64 = 1'h1; // @[tracegen.scala:33:54] wire _rob_respd_WIRE_0 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_1 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_2 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_3 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_4 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_5 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_6 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_7 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_8 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_9 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_10 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_11 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_12 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_13 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_14 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_15 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_16 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_17 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_18 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_19 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_20 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_21 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_22 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_23 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_24 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_25 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_26 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_27 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_28 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_29 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_30 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_31 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_32 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_33 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_34 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_35 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_36 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_37 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_38 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_39 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_40 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_41 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_42 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_43 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_44 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_45 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_46 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_47 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_48 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_49 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_50 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_51 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_52 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_53 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_54 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_55 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_56 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_57 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_58 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_59 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_60 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_61 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_62 = 1'h1; // @[tracegen.scala:33:34] wire _rob_respd_WIRE_63 = 1'h1; // @[tracegen.scala:33:34] wire [7:0] io_tracegen_resp_bits_mask = 8'h0; // @[tracegen.scala:20:7] wire [63:0] _rob_respd_T = 64'hFFFFFFFFFFFFFFFF; // @[tracegen.scala:33:36] wire [1:0] io_tracegen_resp_bits_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size_0; // @[tracegen.scala:20:7] wire [63:0] io_tracegen_resp_bits_data_0 = io_lsu_exe_0_iresp_bits_data_0; // @[tracegen.scala:20:7] wire _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire [6:0] tracegen_uop_uopc; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_is_load; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_is_sta; // @[tracegen.scala:57:30] wire tracegen_uop_ctrl_is_std; // @[tracegen.scala:57:30] wire [5:0] tracegen_uop_rob_idx; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_ldq_idx; // @[tracegen.scala:57:30] wire [3:0] tracegen_uop_stq_idx; // @[tracegen.scala:57:30] wire [4:0] tracegen_uop_mem_cmd; // @[tracegen.scala:57:30] wire tracegen_uop_is_amo; // @[tracegen.scala:57:30] wire tracegen_uop_uses_ldq; // @[tracegen.scala:57:30] wire tracegen_uop_uses_stq; // @[tracegen.scala:57:30] assign tracegen_uop_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[tracegen.scala:20:7, :57:30] assign tracegen_uop_stq_idx = io_lsu_dis_stq_idx_0_0; // @[tracegen.scala:20:7, :57:30] wire _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:95:75] wire _io_tracegen_req_ready_T_86; // @[tracegen.scala:53:63] assign tracegen_uop_mem_cmd = io_tracegen_req_bits_cmd_0; // @[tracegen.scala:20:7, :57:30] wire _io_tracegen_ordered_T; // @[tracegen.scala:164:40] wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_exe_0_req_bits_uop_rob_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_exe_0_req_bits_uop_stq_idx_0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_is_amo_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_uses_ldq_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_bits_uop_uses_stq_0; // @[tracegen.scala:20:7] wire [63:0] io_lsu_exe_0_req_bits_data_0; // @[tracegen.scala:20:7] wire [33:0] io_lsu_exe_0_req_bits_addr_0; // @[tracegen.scala:20:7] wire io_lsu_exe_0_req_valid_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_is_load_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_ctrl_is_std_0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_dis_uops_0_bits_uopc_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_is_amo_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[tracegen.scala:20:7] wire io_lsu_dis_uops_0_valid_0; // @[tracegen.scala:20:7] wire io_lsu_commit_valids_0_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_is_load_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_is_sta_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_ctrl_is_std_0; // @[tracegen.scala:20:7] wire [6:0] io_lsu_commit_uops_0_uopc_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_commit_uops_0_rob_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_ldq_idx_0; // @[tracegen.scala:20:7] wire [3:0] io_lsu_commit_uops_0_stq_idx_0; // @[tracegen.scala:20:7] wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_is_amo_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_uses_ldq_0; // @[tracegen.scala:20:7] wire io_lsu_commit_uops_0_uses_stq_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_rob_pnr_idx_0; // @[tracegen.scala:20:7] wire [5:0] io_lsu_rob_head_idx_0; // @[tracegen.scala:20:7] wire io_tracegen_req_ready_0; // @[tracegen.scala:20:7] wire [5:0] io_tracegen_resp_bits_tag_0; // @[tracegen.scala:20:7] wire io_tracegen_resp_valid_0; // @[tracegen.scala:20:7] wire io_tracegen_ordered_0; // @[tracegen.scala:20:7] reg [33:0] rob_0_addr; // @[tracegen.scala:32:16] reg [5:0] rob_0_tag; // @[tracegen.scala:32:16] reg [4:0] rob_0_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_0_data; // @[tracegen.scala:32:16] reg [33:0] rob_1_addr; // @[tracegen.scala:32:16] reg [5:0] rob_1_tag; // @[tracegen.scala:32:16] reg [4:0] rob_1_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_1_data; // @[tracegen.scala:32:16] reg [33:0] rob_2_addr; // @[tracegen.scala:32:16] reg [5:0] rob_2_tag; // @[tracegen.scala:32:16] reg [4:0] rob_2_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_2_data; // @[tracegen.scala:32:16] reg [33:0] rob_3_addr; // @[tracegen.scala:32:16] reg [5:0] rob_3_tag; // @[tracegen.scala:32:16] reg [4:0] rob_3_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_3_data; // @[tracegen.scala:32:16] reg [33:0] rob_4_addr; // @[tracegen.scala:32:16] reg [5:0] rob_4_tag; // @[tracegen.scala:32:16] reg [4:0] rob_4_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_4_data; // @[tracegen.scala:32:16] reg [33:0] rob_5_addr; // @[tracegen.scala:32:16] reg [5:0] rob_5_tag; // @[tracegen.scala:32:16] reg [4:0] rob_5_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_5_data; // @[tracegen.scala:32:16] reg [33:0] rob_6_addr; // @[tracegen.scala:32:16] reg [5:0] rob_6_tag; // @[tracegen.scala:32:16] reg [4:0] rob_6_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_6_data; // @[tracegen.scala:32:16] reg [33:0] rob_7_addr; // @[tracegen.scala:32:16] reg [5:0] rob_7_tag; // @[tracegen.scala:32:16] reg [4:0] rob_7_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_7_data; // @[tracegen.scala:32:16] reg [33:0] rob_8_addr; // @[tracegen.scala:32:16] reg [5:0] rob_8_tag; // @[tracegen.scala:32:16] reg [4:0] rob_8_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_8_data; // @[tracegen.scala:32:16] reg [33:0] rob_9_addr; // @[tracegen.scala:32:16] reg [5:0] rob_9_tag; // @[tracegen.scala:32:16] reg [4:0] rob_9_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_9_data; // @[tracegen.scala:32:16] reg [33:0] rob_10_addr; // @[tracegen.scala:32:16] reg [5:0] rob_10_tag; // @[tracegen.scala:32:16] reg [4:0] rob_10_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_10_data; // @[tracegen.scala:32:16] reg [33:0] rob_11_addr; // @[tracegen.scala:32:16] reg [5:0] rob_11_tag; // @[tracegen.scala:32:16] reg [4:0] rob_11_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_11_data; // @[tracegen.scala:32:16] reg [33:0] rob_12_addr; // @[tracegen.scala:32:16] reg [5:0] rob_12_tag; // @[tracegen.scala:32:16] reg [4:0] rob_12_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_12_data; // @[tracegen.scala:32:16] reg [33:0] rob_13_addr; // @[tracegen.scala:32:16] reg [5:0] rob_13_tag; // @[tracegen.scala:32:16] reg [4:0] rob_13_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_13_data; // @[tracegen.scala:32:16] reg [33:0] rob_14_addr; // @[tracegen.scala:32:16] reg [5:0] rob_14_tag; // @[tracegen.scala:32:16] reg [4:0] rob_14_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_14_data; // @[tracegen.scala:32:16] reg [33:0] rob_15_addr; // @[tracegen.scala:32:16] reg [5:0] rob_15_tag; // @[tracegen.scala:32:16] reg [4:0] rob_15_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_15_data; // @[tracegen.scala:32:16] reg [33:0] rob_16_addr; // @[tracegen.scala:32:16] reg [5:0] rob_16_tag; // @[tracegen.scala:32:16] reg [4:0] rob_16_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_16_data; // @[tracegen.scala:32:16] reg [33:0] rob_17_addr; // @[tracegen.scala:32:16] reg [5:0] rob_17_tag; // @[tracegen.scala:32:16] reg [4:0] rob_17_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_17_data; // @[tracegen.scala:32:16] reg [33:0] rob_18_addr; // @[tracegen.scala:32:16] reg [5:0] rob_18_tag; // @[tracegen.scala:32:16] reg [4:0] rob_18_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_18_data; // @[tracegen.scala:32:16] reg [33:0] rob_19_addr; // @[tracegen.scala:32:16] reg [5:0] rob_19_tag; // @[tracegen.scala:32:16] reg [4:0] rob_19_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_19_data; // @[tracegen.scala:32:16] reg [33:0] rob_20_addr; // @[tracegen.scala:32:16] reg [5:0] rob_20_tag; // @[tracegen.scala:32:16] reg [4:0] rob_20_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_20_data; // @[tracegen.scala:32:16] reg [33:0] rob_21_addr; // @[tracegen.scala:32:16] reg [5:0] rob_21_tag; // @[tracegen.scala:32:16] reg [4:0] rob_21_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_21_data; // @[tracegen.scala:32:16] reg [33:0] rob_22_addr; // @[tracegen.scala:32:16] reg [5:0] rob_22_tag; // @[tracegen.scala:32:16] reg [4:0] rob_22_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_22_data; // @[tracegen.scala:32:16] reg [33:0] rob_23_addr; // @[tracegen.scala:32:16] reg [5:0] rob_23_tag; // @[tracegen.scala:32:16] reg [4:0] rob_23_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_23_data; // @[tracegen.scala:32:16] reg [33:0] rob_24_addr; // @[tracegen.scala:32:16] reg [5:0] rob_24_tag; // @[tracegen.scala:32:16] reg [4:0] rob_24_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_24_data; // @[tracegen.scala:32:16] reg [33:0] rob_25_addr; // @[tracegen.scala:32:16] reg [5:0] rob_25_tag; // @[tracegen.scala:32:16] reg [4:0] rob_25_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_25_data; // @[tracegen.scala:32:16] reg [33:0] rob_26_addr; // @[tracegen.scala:32:16] reg [5:0] rob_26_tag; // @[tracegen.scala:32:16] reg [4:0] rob_26_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_26_data; // @[tracegen.scala:32:16] reg [33:0] rob_27_addr; // @[tracegen.scala:32:16] reg [5:0] rob_27_tag; // @[tracegen.scala:32:16] reg [4:0] rob_27_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_27_data; // @[tracegen.scala:32:16] reg [33:0] rob_28_addr; // @[tracegen.scala:32:16] reg [5:0] rob_28_tag; // @[tracegen.scala:32:16] reg [4:0] rob_28_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_28_data; // @[tracegen.scala:32:16] reg [33:0] rob_29_addr; // @[tracegen.scala:32:16] reg [5:0] rob_29_tag; // @[tracegen.scala:32:16] reg [4:0] rob_29_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_29_data; // @[tracegen.scala:32:16] reg [33:0] rob_30_addr; // @[tracegen.scala:32:16] reg [5:0] rob_30_tag; // @[tracegen.scala:32:16] reg [4:0] rob_30_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_30_data; // @[tracegen.scala:32:16] reg [33:0] rob_31_addr; // @[tracegen.scala:32:16] reg [5:0] rob_31_tag; // @[tracegen.scala:32:16] reg [4:0] rob_31_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_31_data; // @[tracegen.scala:32:16] reg [33:0] rob_32_addr; // @[tracegen.scala:32:16] reg [5:0] rob_32_tag; // @[tracegen.scala:32:16] reg [4:0] rob_32_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_32_data; // @[tracegen.scala:32:16] reg [33:0] rob_33_addr; // @[tracegen.scala:32:16] reg [5:0] rob_33_tag; // @[tracegen.scala:32:16] reg [4:0] rob_33_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_33_data; // @[tracegen.scala:32:16] reg [33:0] rob_34_addr; // @[tracegen.scala:32:16] reg [5:0] rob_34_tag; // @[tracegen.scala:32:16] reg [4:0] rob_34_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_34_data; // @[tracegen.scala:32:16] reg [33:0] rob_35_addr; // @[tracegen.scala:32:16] reg [5:0] rob_35_tag; // @[tracegen.scala:32:16] reg [4:0] rob_35_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_35_data; // @[tracegen.scala:32:16] reg [33:0] rob_36_addr; // @[tracegen.scala:32:16] reg [5:0] rob_36_tag; // @[tracegen.scala:32:16] reg [4:0] rob_36_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_36_data; // @[tracegen.scala:32:16] reg [33:0] rob_37_addr; // @[tracegen.scala:32:16] reg [5:0] rob_37_tag; // @[tracegen.scala:32:16] reg [4:0] rob_37_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_37_data; // @[tracegen.scala:32:16] reg [33:0] rob_38_addr; // @[tracegen.scala:32:16] reg [5:0] rob_38_tag; // @[tracegen.scala:32:16] reg [4:0] rob_38_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_38_data; // @[tracegen.scala:32:16] reg [33:0] rob_39_addr; // @[tracegen.scala:32:16] reg [5:0] rob_39_tag; // @[tracegen.scala:32:16] reg [4:0] rob_39_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_39_data; // @[tracegen.scala:32:16] reg [33:0] rob_40_addr; // @[tracegen.scala:32:16] reg [5:0] rob_40_tag; // @[tracegen.scala:32:16] reg [4:0] rob_40_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_40_data; // @[tracegen.scala:32:16] reg [33:0] rob_41_addr; // @[tracegen.scala:32:16] reg [5:0] rob_41_tag; // @[tracegen.scala:32:16] reg [4:0] rob_41_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_41_data; // @[tracegen.scala:32:16] reg [33:0] rob_42_addr; // @[tracegen.scala:32:16] reg [5:0] rob_42_tag; // @[tracegen.scala:32:16] reg [4:0] rob_42_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_42_data; // @[tracegen.scala:32:16] reg [33:0] rob_43_addr; // @[tracegen.scala:32:16] reg [5:0] rob_43_tag; // @[tracegen.scala:32:16] reg [4:0] rob_43_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_43_data; // @[tracegen.scala:32:16] reg [33:0] rob_44_addr; // @[tracegen.scala:32:16] reg [5:0] rob_44_tag; // @[tracegen.scala:32:16] reg [4:0] rob_44_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_44_data; // @[tracegen.scala:32:16] reg [33:0] rob_45_addr; // @[tracegen.scala:32:16] reg [5:0] rob_45_tag; // @[tracegen.scala:32:16] reg [4:0] rob_45_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_45_data; // @[tracegen.scala:32:16] reg [33:0] rob_46_addr; // @[tracegen.scala:32:16] reg [5:0] rob_46_tag; // @[tracegen.scala:32:16] reg [4:0] rob_46_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_46_data; // @[tracegen.scala:32:16] reg [33:0] rob_47_addr; // @[tracegen.scala:32:16] reg [5:0] rob_47_tag; // @[tracegen.scala:32:16] reg [4:0] rob_47_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_47_data; // @[tracegen.scala:32:16] reg [33:0] rob_48_addr; // @[tracegen.scala:32:16] reg [5:0] rob_48_tag; // @[tracegen.scala:32:16] reg [4:0] rob_48_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_48_data; // @[tracegen.scala:32:16] reg [33:0] rob_49_addr; // @[tracegen.scala:32:16] reg [5:0] rob_49_tag; // @[tracegen.scala:32:16] reg [4:0] rob_49_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_49_data; // @[tracegen.scala:32:16] reg [33:0] rob_50_addr; // @[tracegen.scala:32:16] reg [5:0] rob_50_tag; // @[tracegen.scala:32:16] reg [4:0] rob_50_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_50_data; // @[tracegen.scala:32:16] reg [33:0] rob_51_addr; // @[tracegen.scala:32:16] reg [5:0] rob_51_tag; // @[tracegen.scala:32:16] reg [4:0] rob_51_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_51_data; // @[tracegen.scala:32:16] reg [33:0] rob_52_addr; // @[tracegen.scala:32:16] reg [5:0] rob_52_tag; // @[tracegen.scala:32:16] reg [4:0] rob_52_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_52_data; // @[tracegen.scala:32:16] reg [33:0] rob_53_addr; // @[tracegen.scala:32:16] reg [5:0] rob_53_tag; // @[tracegen.scala:32:16] reg [4:0] rob_53_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_53_data; // @[tracegen.scala:32:16] reg [33:0] rob_54_addr; // @[tracegen.scala:32:16] reg [5:0] rob_54_tag; // @[tracegen.scala:32:16] reg [4:0] rob_54_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_54_data; // @[tracegen.scala:32:16] reg [33:0] rob_55_addr; // @[tracegen.scala:32:16] reg [5:0] rob_55_tag; // @[tracegen.scala:32:16] reg [4:0] rob_55_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_55_data; // @[tracegen.scala:32:16] reg [33:0] rob_56_addr; // @[tracegen.scala:32:16] reg [5:0] rob_56_tag; // @[tracegen.scala:32:16] reg [4:0] rob_56_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_56_data; // @[tracegen.scala:32:16] reg [33:0] rob_57_addr; // @[tracegen.scala:32:16] reg [5:0] rob_57_tag; // @[tracegen.scala:32:16] reg [4:0] rob_57_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_57_data; // @[tracegen.scala:32:16] reg [33:0] rob_58_addr; // @[tracegen.scala:32:16] reg [5:0] rob_58_tag; // @[tracegen.scala:32:16] reg [4:0] rob_58_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_58_data; // @[tracegen.scala:32:16] reg [33:0] rob_59_addr; // @[tracegen.scala:32:16] reg [5:0] rob_59_tag; // @[tracegen.scala:32:16] reg [4:0] rob_59_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_59_data; // @[tracegen.scala:32:16] reg [33:0] rob_60_addr; // @[tracegen.scala:32:16] reg [5:0] rob_60_tag; // @[tracegen.scala:32:16] reg [4:0] rob_60_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_60_data; // @[tracegen.scala:32:16] reg [33:0] rob_61_addr; // @[tracegen.scala:32:16] reg [5:0] rob_61_tag; // @[tracegen.scala:32:16] reg [4:0] rob_61_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_61_data; // @[tracegen.scala:32:16] reg [33:0] rob_62_addr; // @[tracegen.scala:32:16] reg [5:0] rob_62_tag; // @[tracegen.scala:32:16] reg [4:0] rob_62_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_62_data; // @[tracegen.scala:32:16] reg [33:0] rob_63_addr; // @[tracegen.scala:32:16] reg [5:0] rob_63_tag; // @[tracegen.scala:32:16] reg [4:0] rob_63_cmd; // @[tracegen.scala:32:16] reg [63:0] rob_63_data; // @[tracegen.scala:32:16] reg rob_respd_0; // @[tracegen.scala:33:26] reg rob_respd_1; // @[tracegen.scala:33:26] reg rob_respd_2; // @[tracegen.scala:33:26] reg rob_respd_3; // @[tracegen.scala:33:26] reg rob_respd_4; // @[tracegen.scala:33:26] reg rob_respd_5; // @[tracegen.scala:33:26] reg rob_respd_6; // @[tracegen.scala:33:26] reg rob_respd_7; // @[tracegen.scala:33:26] reg rob_respd_8; // @[tracegen.scala:33:26] reg rob_respd_9; // @[tracegen.scala:33:26] reg rob_respd_10; // @[tracegen.scala:33:26] reg rob_respd_11; // @[tracegen.scala:33:26] reg rob_respd_12; // @[tracegen.scala:33:26] reg rob_respd_13; // @[tracegen.scala:33:26] reg rob_respd_14; // @[tracegen.scala:33:26] reg rob_respd_15; // @[tracegen.scala:33:26] reg rob_respd_16; // @[tracegen.scala:33:26] reg rob_respd_17; // @[tracegen.scala:33:26] reg rob_respd_18; // @[tracegen.scala:33:26] reg rob_respd_19; // @[tracegen.scala:33:26] reg rob_respd_20; // @[tracegen.scala:33:26] reg rob_respd_21; // @[tracegen.scala:33:26] reg rob_respd_22; // @[tracegen.scala:33:26] reg rob_respd_23; // @[tracegen.scala:33:26] reg rob_respd_24; // @[tracegen.scala:33:26] reg rob_respd_25; // @[tracegen.scala:33:26] reg rob_respd_26; // @[tracegen.scala:33:26] reg rob_respd_27; // @[tracegen.scala:33:26] reg rob_respd_28; // @[tracegen.scala:33:26] reg rob_respd_29; // @[tracegen.scala:33:26] reg rob_respd_30; // @[tracegen.scala:33:26] reg rob_respd_31; // @[tracegen.scala:33:26] reg rob_respd_32; // @[tracegen.scala:33:26] reg rob_respd_33; // @[tracegen.scala:33:26] reg rob_respd_34; // @[tracegen.scala:33:26] reg rob_respd_35; // @[tracegen.scala:33:26] reg rob_respd_36; // @[tracegen.scala:33:26] reg rob_respd_37; // @[tracegen.scala:33:26] reg rob_respd_38; // @[tracegen.scala:33:26] reg rob_respd_39; // @[tracegen.scala:33:26] reg rob_respd_40; // @[tracegen.scala:33:26] reg rob_respd_41; // @[tracegen.scala:33:26] reg rob_respd_42; // @[tracegen.scala:33:26] reg rob_respd_43; // @[tracegen.scala:33:26] reg rob_respd_44; // @[tracegen.scala:33:26] reg rob_respd_45; // @[tracegen.scala:33:26] reg rob_respd_46; // @[tracegen.scala:33:26] reg rob_respd_47; // @[tracegen.scala:33:26] reg rob_respd_48; // @[tracegen.scala:33:26] reg rob_respd_49; // @[tracegen.scala:33:26] reg rob_respd_50; // @[tracegen.scala:33:26] reg rob_respd_51; // @[tracegen.scala:33:26] reg rob_respd_52; // @[tracegen.scala:33:26] reg rob_respd_53; // @[tracegen.scala:33:26] reg rob_respd_54; // @[tracegen.scala:33:26] reg rob_respd_55; // @[tracegen.scala:33:26] reg rob_respd_56; // @[tracegen.scala:33:26] reg rob_respd_57; // @[tracegen.scala:33:26] reg rob_respd_58; // @[tracegen.scala:33:26] reg rob_respd_59; // @[tracegen.scala:33:26] reg rob_respd_60; // @[tracegen.scala:33:26] reg rob_respd_61; // @[tracegen.scala:33:26] reg rob_respd_62; // @[tracegen.scala:33:26] reg rob_respd_63; // @[tracegen.scala:33:26] reg [6:0] rob_uop_0_uopc; // @[tracegen.scala:34:20] reg rob_uop_0_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_0_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_0_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_0_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_0_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_0_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_0_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_0_is_amo; // @[tracegen.scala:34:20] reg rob_uop_0_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_0_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_1_uopc; // @[tracegen.scala:34:20] reg rob_uop_1_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_1_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_1_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_1_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_1_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_1_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_1_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_1_is_amo; // @[tracegen.scala:34:20] reg rob_uop_1_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_1_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_2_uopc; // @[tracegen.scala:34:20] reg rob_uop_2_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_2_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_2_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_2_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_2_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_2_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_2_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_2_is_amo; // @[tracegen.scala:34:20] reg rob_uop_2_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_2_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_3_uopc; // @[tracegen.scala:34:20] reg rob_uop_3_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_3_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_3_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_3_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_3_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_3_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_3_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_3_is_amo; // @[tracegen.scala:34:20] reg rob_uop_3_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_3_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_4_uopc; // @[tracegen.scala:34:20] reg rob_uop_4_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_4_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_4_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_4_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_4_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_4_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_4_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_4_is_amo; // @[tracegen.scala:34:20] reg rob_uop_4_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_4_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_5_uopc; // @[tracegen.scala:34:20] reg rob_uop_5_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_5_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_5_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_5_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_5_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_5_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_5_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_5_is_amo; // @[tracegen.scala:34:20] reg rob_uop_5_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_5_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_6_uopc; // @[tracegen.scala:34:20] reg rob_uop_6_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_6_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_6_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_6_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_6_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_6_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_6_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_6_is_amo; // @[tracegen.scala:34:20] reg rob_uop_6_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_6_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_7_uopc; // @[tracegen.scala:34:20] reg rob_uop_7_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_7_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_7_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_7_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_7_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_7_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_7_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_7_is_amo; // @[tracegen.scala:34:20] reg rob_uop_7_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_7_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_8_uopc; // @[tracegen.scala:34:20] reg rob_uop_8_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_8_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_8_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_8_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_8_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_8_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_8_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_8_is_amo; // @[tracegen.scala:34:20] reg rob_uop_8_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_8_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_9_uopc; // @[tracegen.scala:34:20] reg rob_uop_9_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_9_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_9_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_9_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_9_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_9_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_9_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_9_is_amo; // @[tracegen.scala:34:20] reg rob_uop_9_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_9_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_10_uopc; // @[tracegen.scala:34:20] reg rob_uop_10_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_10_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_10_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_10_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_10_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_10_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_10_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_10_is_amo; // @[tracegen.scala:34:20] reg rob_uop_10_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_10_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_11_uopc; // @[tracegen.scala:34:20] reg rob_uop_11_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_11_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_11_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_11_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_11_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_11_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_11_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_11_is_amo; // @[tracegen.scala:34:20] reg rob_uop_11_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_11_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_12_uopc; // @[tracegen.scala:34:20] reg rob_uop_12_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_12_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_12_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_12_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_12_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_12_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_12_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_12_is_amo; // @[tracegen.scala:34:20] reg rob_uop_12_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_12_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_13_uopc; // @[tracegen.scala:34:20] reg rob_uop_13_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_13_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_13_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_13_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_13_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_13_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_13_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_13_is_amo; // @[tracegen.scala:34:20] reg rob_uop_13_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_13_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_14_uopc; // @[tracegen.scala:34:20] reg rob_uop_14_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_14_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_14_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_14_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_14_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_14_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_14_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_14_is_amo; // @[tracegen.scala:34:20] reg rob_uop_14_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_14_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_15_uopc; // @[tracegen.scala:34:20] reg rob_uop_15_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_15_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_15_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_15_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_15_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_15_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_15_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_15_is_amo; // @[tracegen.scala:34:20] reg rob_uop_15_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_15_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_16_uopc; // @[tracegen.scala:34:20] reg rob_uop_16_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_16_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_16_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_16_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_16_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_16_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_16_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_16_is_amo; // @[tracegen.scala:34:20] reg rob_uop_16_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_16_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_17_uopc; // @[tracegen.scala:34:20] reg rob_uop_17_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_17_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_17_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_17_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_17_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_17_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_17_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_17_is_amo; // @[tracegen.scala:34:20] reg rob_uop_17_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_17_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_18_uopc; // @[tracegen.scala:34:20] reg rob_uop_18_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_18_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_18_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_18_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_18_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_18_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_18_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_18_is_amo; // @[tracegen.scala:34:20] reg rob_uop_18_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_18_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_19_uopc; // @[tracegen.scala:34:20] reg rob_uop_19_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_19_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_19_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_19_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_19_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_19_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_19_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_19_is_amo; // @[tracegen.scala:34:20] reg rob_uop_19_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_19_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_20_uopc; // @[tracegen.scala:34:20] reg rob_uop_20_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_20_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_20_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_20_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_20_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_20_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_20_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_20_is_amo; // @[tracegen.scala:34:20] reg rob_uop_20_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_20_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_21_uopc; // @[tracegen.scala:34:20] reg rob_uop_21_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_21_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_21_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_21_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_21_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_21_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_21_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_21_is_amo; // @[tracegen.scala:34:20] reg rob_uop_21_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_21_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_22_uopc; // @[tracegen.scala:34:20] reg rob_uop_22_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_22_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_22_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_22_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_22_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_22_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_22_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_22_is_amo; // @[tracegen.scala:34:20] reg rob_uop_22_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_22_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_23_uopc; // @[tracegen.scala:34:20] reg rob_uop_23_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_23_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_23_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_23_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_23_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_23_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_23_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_23_is_amo; // @[tracegen.scala:34:20] reg rob_uop_23_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_23_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_24_uopc; // @[tracegen.scala:34:20] reg rob_uop_24_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_24_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_24_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_24_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_24_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_24_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_24_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_24_is_amo; // @[tracegen.scala:34:20] reg rob_uop_24_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_24_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_25_uopc; // @[tracegen.scala:34:20] reg rob_uop_25_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_25_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_25_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_25_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_25_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_25_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_25_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_25_is_amo; // @[tracegen.scala:34:20] reg rob_uop_25_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_25_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_26_uopc; // @[tracegen.scala:34:20] reg rob_uop_26_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_26_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_26_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_26_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_26_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_26_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_26_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_26_is_amo; // @[tracegen.scala:34:20] reg rob_uop_26_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_26_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_27_uopc; // @[tracegen.scala:34:20] reg rob_uop_27_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_27_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_27_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_27_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_27_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_27_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_27_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_27_is_amo; // @[tracegen.scala:34:20] reg rob_uop_27_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_27_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_28_uopc; // @[tracegen.scala:34:20] reg rob_uop_28_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_28_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_28_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_28_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_28_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_28_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_28_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_28_is_amo; // @[tracegen.scala:34:20] reg rob_uop_28_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_28_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_29_uopc; // @[tracegen.scala:34:20] reg rob_uop_29_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_29_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_29_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_29_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_29_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_29_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_29_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_29_is_amo; // @[tracegen.scala:34:20] reg rob_uop_29_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_29_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_30_uopc; // @[tracegen.scala:34:20] reg rob_uop_30_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_30_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_30_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_30_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_30_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_30_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_30_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_30_is_amo; // @[tracegen.scala:34:20] reg rob_uop_30_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_30_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_31_uopc; // @[tracegen.scala:34:20] reg rob_uop_31_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_31_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_31_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_31_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_31_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_31_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_31_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_31_is_amo; // @[tracegen.scala:34:20] reg rob_uop_31_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_31_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_32_uopc; // @[tracegen.scala:34:20] reg rob_uop_32_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_32_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_32_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_32_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_32_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_32_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_32_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_32_is_amo; // @[tracegen.scala:34:20] reg rob_uop_32_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_32_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_33_uopc; // @[tracegen.scala:34:20] reg rob_uop_33_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_33_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_33_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_33_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_33_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_33_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_33_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_33_is_amo; // @[tracegen.scala:34:20] reg rob_uop_33_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_33_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_34_uopc; // @[tracegen.scala:34:20] reg rob_uop_34_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_34_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_34_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_34_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_34_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_34_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_34_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_34_is_amo; // @[tracegen.scala:34:20] reg rob_uop_34_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_34_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_35_uopc; // @[tracegen.scala:34:20] reg rob_uop_35_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_35_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_35_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_35_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_35_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_35_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_35_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_35_is_amo; // @[tracegen.scala:34:20] reg rob_uop_35_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_35_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_36_uopc; // @[tracegen.scala:34:20] reg rob_uop_36_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_36_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_36_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_36_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_36_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_36_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_36_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_36_is_amo; // @[tracegen.scala:34:20] reg rob_uop_36_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_36_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_37_uopc; // @[tracegen.scala:34:20] reg rob_uop_37_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_37_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_37_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_37_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_37_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_37_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_37_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_37_is_amo; // @[tracegen.scala:34:20] reg rob_uop_37_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_37_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_38_uopc; // @[tracegen.scala:34:20] reg rob_uop_38_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_38_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_38_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_38_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_38_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_38_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_38_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_38_is_amo; // @[tracegen.scala:34:20] reg rob_uop_38_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_38_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_39_uopc; // @[tracegen.scala:34:20] reg rob_uop_39_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_39_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_39_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_39_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_39_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_39_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_39_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_39_is_amo; // @[tracegen.scala:34:20] reg rob_uop_39_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_39_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_40_uopc; // @[tracegen.scala:34:20] reg rob_uop_40_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_40_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_40_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_40_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_40_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_40_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_40_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_40_is_amo; // @[tracegen.scala:34:20] reg rob_uop_40_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_40_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_41_uopc; // @[tracegen.scala:34:20] reg rob_uop_41_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_41_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_41_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_41_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_41_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_41_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_41_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_41_is_amo; // @[tracegen.scala:34:20] reg rob_uop_41_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_41_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_42_uopc; // @[tracegen.scala:34:20] reg rob_uop_42_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_42_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_42_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_42_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_42_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_42_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_42_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_42_is_amo; // @[tracegen.scala:34:20] reg rob_uop_42_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_42_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_43_uopc; // @[tracegen.scala:34:20] reg rob_uop_43_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_43_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_43_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_43_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_43_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_43_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_43_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_43_is_amo; // @[tracegen.scala:34:20] reg rob_uop_43_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_43_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_44_uopc; // @[tracegen.scala:34:20] reg rob_uop_44_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_44_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_44_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_44_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_44_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_44_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_44_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_44_is_amo; // @[tracegen.scala:34:20] reg rob_uop_44_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_44_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_45_uopc; // @[tracegen.scala:34:20] reg rob_uop_45_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_45_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_45_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_45_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_45_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_45_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_45_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_45_is_amo; // @[tracegen.scala:34:20] reg rob_uop_45_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_45_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_46_uopc; // @[tracegen.scala:34:20] reg rob_uop_46_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_46_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_46_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_46_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_46_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_46_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_46_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_46_is_amo; // @[tracegen.scala:34:20] reg rob_uop_46_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_46_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_47_uopc; // @[tracegen.scala:34:20] reg rob_uop_47_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_47_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_47_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_47_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_47_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_47_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_47_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_47_is_amo; // @[tracegen.scala:34:20] reg rob_uop_47_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_47_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_48_uopc; // @[tracegen.scala:34:20] reg rob_uop_48_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_48_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_48_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_48_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_48_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_48_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_48_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_48_is_amo; // @[tracegen.scala:34:20] reg rob_uop_48_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_48_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_49_uopc; // @[tracegen.scala:34:20] reg rob_uop_49_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_49_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_49_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_49_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_49_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_49_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_49_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_49_is_amo; // @[tracegen.scala:34:20] reg rob_uop_49_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_49_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_50_uopc; // @[tracegen.scala:34:20] reg rob_uop_50_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_50_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_50_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_50_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_50_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_50_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_50_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_50_is_amo; // @[tracegen.scala:34:20] reg rob_uop_50_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_50_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_51_uopc; // @[tracegen.scala:34:20] reg rob_uop_51_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_51_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_51_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_51_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_51_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_51_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_51_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_51_is_amo; // @[tracegen.scala:34:20] reg rob_uop_51_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_51_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_52_uopc; // @[tracegen.scala:34:20] reg rob_uop_52_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_52_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_52_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_52_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_52_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_52_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_52_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_52_is_amo; // @[tracegen.scala:34:20] reg rob_uop_52_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_52_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_53_uopc; // @[tracegen.scala:34:20] reg rob_uop_53_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_53_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_53_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_53_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_53_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_53_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_53_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_53_is_amo; // @[tracegen.scala:34:20] reg rob_uop_53_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_53_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_54_uopc; // @[tracegen.scala:34:20] reg rob_uop_54_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_54_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_54_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_54_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_54_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_54_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_54_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_54_is_amo; // @[tracegen.scala:34:20] reg rob_uop_54_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_54_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_55_uopc; // @[tracegen.scala:34:20] reg rob_uop_55_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_55_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_55_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_55_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_55_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_55_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_55_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_55_is_amo; // @[tracegen.scala:34:20] reg rob_uop_55_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_55_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_56_uopc; // @[tracegen.scala:34:20] reg rob_uop_56_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_56_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_56_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_56_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_56_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_56_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_56_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_56_is_amo; // @[tracegen.scala:34:20] reg rob_uop_56_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_56_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_57_uopc; // @[tracegen.scala:34:20] reg rob_uop_57_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_57_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_57_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_57_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_57_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_57_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_57_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_57_is_amo; // @[tracegen.scala:34:20] reg rob_uop_57_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_57_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_58_uopc; // @[tracegen.scala:34:20] reg rob_uop_58_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_58_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_58_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_58_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_58_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_58_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_58_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_58_is_amo; // @[tracegen.scala:34:20] reg rob_uop_58_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_58_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_59_uopc; // @[tracegen.scala:34:20] reg rob_uop_59_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_59_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_59_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_59_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_59_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_59_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_59_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_59_is_amo; // @[tracegen.scala:34:20] reg rob_uop_59_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_59_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_60_uopc; // @[tracegen.scala:34:20] reg rob_uop_60_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_60_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_60_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_60_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_60_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_60_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_60_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_60_is_amo; // @[tracegen.scala:34:20] reg rob_uop_60_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_60_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_61_uopc; // @[tracegen.scala:34:20] reg rob_uop_61_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_61_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_61_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_61_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_61_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_61_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_61_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_61_is_amo; // @[tracegen.scala:34:20] reg rob_uop_61_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_61_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_62_uopc; // @[tracegen.scala:34:20] reg rob_uop_62_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_62_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_62_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_62_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_62_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_62_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_62_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_62_is_amo; // @[tracegen.scala:34:20] reg rob_uop_62_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_62_uses_stq; // @[tracegen.scala:34:20] reg [6:0] rob_uop_63_uopc; // @[tracegen.scala:34:20] reg rob_uop_63_ctrl_is_load; // @[tracegen.scala:34:20] reg rob_uop_63_ctrl_is_sta; // @[tracegen.scala:34:20] reg rob_uop_63_ctrl_is_std; // @[tracegen.scala:34:20] reg [5:0] rob_uop_63_rob_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_63_ldq_idx; // @[tracegen.scala:34:20] reg [3:0] rob_uop_63_stq_idx; // @[tracegen.scala:34:20] reg [4:0] rob_uop_63_mem_cmd; // @[tracegen.scala:34:20] reg rob_uop_63_is_amo; // @[tracegen.scala:34:20] reg rob_uop_63_uses_ldq; // @[tracegen.scala:34:20] reg rob_uop_63_uses_stq; // @[tracegen.scala:34:20] reg rob_bsy_0; // @[tracegen.scala:35:25] reg rob_bsy_1; // @[tracegen.scala:35:25] reg rob_bsy_2; // @[tracegen.scala:35:25] reg rob_bsy_3; // @[tracegen.scala:35:25] reg rob_bsy_4; // @[tracegen.scala:35:25] reg rob_bsy_5; // @[tracegen.scala:35:25] reg rob_bsy_6; // @[tracegen.scala:35:25] reg rob_bsy_7; // @[tracegen.scala:35:25] reg rob_bsy_8; // @[tracegen.scala:35:25] reg rob_bsy_9; // @[tracegen.scala:35:25] reg rob_bsy_10; // @[tracegen.scala:35:25] reg rob_bsy_11; // @[tracegen.scala:35:25] reg rob_bsy_12; // @[tracegen.scala:35:25] reg rob_bsy_13; // @[tracegen.scala:35:25] reg rob_bsy_14; // @[tracegen.scala:35:25] reg rob_bsy_15; // @[tracegen.scala:35:25] reg rob_bsy_16; // @[tracegen.scala:35:25] reg rob_bsy_17; // @[tracegen.scala:35:25] reg rob_bsy_18; // @[tracegen.scala:35:25] reg rob_bsy_19; // @[tracegen.scala:35:25] reg rob_bsy_20; // @[tracegen.scala:35:25] reg rob_bsy_21; // @[tracegen.scala:35:25] reg rob_bsy_22; // @[tracegen.scala:35:25] reg rob_bsy_23; // @[tracegen.scala:35:25] reg rob_bsy_24; // @[tracegen.scala:35:25] reg rob_bsy_25; // @[tracegen.scala:35:25] reg rob_bsy_26; // @[tracegen.scala:35:25] reg rob_bsy_27; // @[tracegen.scala:35:25] reg rob_bsy_28; // @[tracegen.scala:35:25] reg rob_bsy_29; // @[tracegen.scala:35:25] reg rob_bsy_30; // @[tracegen.scala:35:25] reg rob_bsy_31; // @[tracegen.scala:35:25] reg rob_bsy_32; // @[tracegen.scala:35:25] reg rob_bsy_33; // @[tracegen.scala:35:25] reg rob_bsy_34; // @[tracegen.scala:35:25] reg rob_bsy_35; // @[tracegen.scala:35:25] reg rob_bsy_36; // @[tracegen.scala:35:25] reg rob_bsy_37; // @[tracegen.scala:35:25] reg rob_bsy_38; // @[tracegen.scala:35:25] reg rob_bsy_39; // @[tracegen.scala:35:25] reg rob_bsy_40; // @[tracegen.scala:35:25] reg rob_bsy_41; // @[tracegen.scala:35:25] reg rob_bsy_42; // @[tracegen.scala:35:25] reg rob_bsy_43; // @[tracegen.scala:35:25] reg rob_bsy_44; // @[tracegen.scala:35:25] reg rob_bsy_45; // @[tracegen.scala:35:25] reg rob_bsy_46; // @[tracegen.scala:35:25] reg rob_bsy_47; // @[tracegen.scala:35:25] reg rob_bsy_48; // @[tracegen.scala:35:25] reg rob_bsy_49; // @[tracegen.scala:35:25] reg rob_bsy_50; // @[tracegen.scala:35:25] reg rob_bsy_51; // @[tracegen.scala:35:25] reg rob_bsy_52; // @[tracegen.scala:35:25] reg rob_bsy_53; // @[tracegen.scala:35:25] reg rob_bsy_54; // @[tracegen.scala:35:25] reg rob_bsy_55; // @[tracegen.scala:35:25] reg rob_bsy_56; // @[tracegen.scala:35:25] reg rob_bsy_57; // @[tracegen.scala:35:25] reg rob_bsy_58; // @[tracegen.scala:35:25] reg rob_bsy_59; // @[tracegen.scala:35:25] reg rob_bsy_60; // @[tracegen.scala:35:25] reg rob_bsy_61; // @[tracegen.scala:35:25] reg rob_bsy_62; // @[tracegen.scala:35:25] reg rob_bsy_63; // @[tracegen.scala:35:25] reg [5:0] rob_head; // @[tracegen.scala:36:25] assign io_lsu_rob_head_idx_0 = rob_head; // @[tracegen.scala:20:7, :36:25] reg [5:0] rob_tail; // @[tracegen.scala:37:25] assign io_lsu_rob_pnr_idx_0 = rob_tail; // @[tracegen.scala:20:7, :37:25] assign tracegen_uop_rob_idx = rob_tail; // @[tracegen.scala:37:25, :57:30] reg rob_wait_till_empty; // @[tracegen.scala:38:36] wire _ready_for_amo_T = rob_tail == rob_head; // @[tracegen.scala:36:25, :37:25, :39:32] wire ready_for_amo = _ready_for_amo_T & io_lsu_fencei_rdy_0; // @[tracegen.scala:20:7, :39:{32,45}] wire [63:0] _GEN = {{rob_bsy_63}, {rob_bsy_62}, {rob_bsy_61}, {rob_bsy_60}, {rob_bsy_59}, {rob_bsy_58}, {rob_bsy_57}, {rob_bsy_56}, {rob_bsy_55}, {rob_bsy_54}, {rob_bsy_53}, {rob_bsy_52}, {rob_bsy_51}, {rob_bsy_50}, {rob_bsy_49}, {rob_bsy_48}, {rob_bsy_47}, {rob_bsy_46}, {rob_bsy_45}, {rob_bsy_44}, {rob_bsy_43}, {rob_bsy_42}, {rob_bsy_41}, {rob_bsy_40}, {rob_bsy_39}, {rob_bsy_38}, {rob_bsy_37}, {rob_bsy_36}, {rob_bsy_35}, {rob_bsy_34}, {rob_bsy_33}, {rob_bsy_32}, {rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[tracegen.scala:35:25, :49:29] wire _io_tracegen_req_ready_T = ~_GEN[rob_tail]; // @[tracegen.scala:37:25, :49:29] wire _io_tracegen_req_ready_T_1 = ~rob_wait_till_empty; // @[tracegen.scala:38:36, :50:5] wire _io_tracegen_req_ready_T_2 = _io_tracegen_req_ready_T & _io_tracegen_req_ready_T_1; // @[tracegen.scala:49:{29,48}, :50:5] wire _T_1 = io_tracegen_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_3; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_3 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_40; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_40 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_66; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_66 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_7 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_30; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_30 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_5; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_5 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_7; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_7 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_30; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_30 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_5; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_5 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_5; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_5 = _T_1; // @[package.scala:16:47] wire _T_2 = io_tracegen_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_4; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_4 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_41; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_41 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_67; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_67 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_8 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_31 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_6 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_1; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_1 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_8; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_8 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_31; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_31 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_6; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_6 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_6; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_6 = _T_2; // @[package.scala:16:47] wire _T_3 = io_tracegen_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_5; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_5 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_42; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_42 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_68; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_68 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_9 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_32 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_7 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_2; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_2 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_9; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_9 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_32; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_32 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_7; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_7 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_7; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_7 = _T_3; // @[package.scala:16:47] wire _T_4 = io_tracegen_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_6; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_6 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_43; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_43 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_69; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_69 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_10 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_33 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_8 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_3; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_3 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_10; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_10 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_33; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_33 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_8; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_8 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_8; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_8 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_7 = _io_tracegen_req_ready_T_3 | _io_tracegen_req_ready_T_4; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_8 = _io_tracegen_req_ready_T_7 | _io_tracegen_req_ready_T_5; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_9 = _io_tracegen_req_ready_T_8 | _io_tracegen_req_ready_T_6; // @[package.scala:16:47, :81:59] wire _T_8 = io_tracegen_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_10; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_10 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_47; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_47 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_73; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_73 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_14 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_37; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_37 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_12; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_12 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_7; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_7 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_14; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_14 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_37; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_37 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_12; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_12 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_12; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_12 = _T_8; // @[package.scala:16:47] wire _T_9 = io_tracegen_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_11; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_11 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_48; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_48 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_74; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_74 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_15 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_38 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_13 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_8; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_8 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_15; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_15 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_38; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_38 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_13; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_13 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_13; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_13 = _T_9; // @[package.scala:16:47] wire _T_10 = io_tracegen_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_12; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_12 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_49; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_49 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_75; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_75 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_16 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_39 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_14 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_9; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_9 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_16; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_16 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_39; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_39 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_14; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_14 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_14; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_14 = _T_10; // @[package.scala:16:47] wire _T_11 = io_tracegen_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_13; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_13 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_50; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_50 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_76; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_76 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_17 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_40 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_15 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_10; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_10 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_17; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_17 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_40; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_40 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_15; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_15 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_15; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_15 = _T_11; // @[package.scala:16:47] wire _T_12 = io_tracegen_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_14; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_14 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_51; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_51 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_77; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_77 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_18 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_41 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_16 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_11; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_11 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_18; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_18 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_41; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_41 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_sta_T_16; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_sta_T_16 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_std_T_16; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_std_T_16 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_15 = _io_tracegen_req_ready_T_10 | _io_tracegen_req_ready_T_11; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_16 = _io_tracegen_req_ready_T_15 | _io_tracegen_req_ready_T_12; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_17 = _io_tracegen_req_ready_T_16 | _io_tracegen_req_ready_T_13; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_18 = _io_tracegen_req_ready_T_17 | _io_tracegen_req_ready_T_14; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_19 = _io_tracegen_req_ready_T_9 | _io_tracegen_req_ready_T_18; // @[package.scala:81:59] wire _T_18 = io_tracegen_req_bits_cmd_0 == 5'h6; // @[tracegen.scala:20:7, :51:85] wire _io_tracegen_req_ready_T_20; // @[tracegen.scala:51:85] assign _io_tracegen_req_ready_T_20 = _T_18; // @[tracegen.scala:51:85] wire _io_tracegen_req_ready_T_35; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_35 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_2 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_2; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_2 = _T_18; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_21 = _io_tracegen_req_ready_T_19 | _io_tracegen_req_ready_T_20; // @[Consts.scala:87:44] wire _T_20 = io_tracegen_req_bits_cmd_0 == 5'h7; // @[tracegen.scala:20:7, :51:123] wire _io_tracegen_req_ready_T_22; // @[tracegen.scala:51:123] assign _io_tracegen_req_ready_T_22 = _T_20; // @[tracegen.scala:51:123] wire _io_tracegen_req_ready_T_36; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_36 = _T_20; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_64; // @[Consts.scala:90:66] assign _io_tracegen_req_ready_T_64 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_3 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:66] assign _tracegen_uop_uses_ldq_T_28 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_uses_stq_T_3 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_is_amo_T_17; // @[tracegen.scala:67:92] assign _tracegen_uop_is_amo_T_17 = _T_20; // @[tracegen.scala:51:123, :67:92] wire _tracegen_uop_ctrl_is_load_T_3; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_3 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_28; // @[Consts.scala:90:66] assign _tracegen_uop_ctrl_is_load_T_28 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_ctrl_is_sta_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_ctrl_is_sta_T_3 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_ctrl_is_std_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_ctrl_is_std_T_3 = _T_20; // @[Consts.scala:90:66] wire _io_tracegen_req_ready_T_23 = _io_tracegen_req_ready_T_21 | _io_tracegen_req_ready_T_22; // @[tracegen.scala:51:{57,95,123}] wire _io_tracegen_req_ready_T_24 = ~_io_tracegen_req_ready_T_23; // @[tracegen.scala:51:{23,95}] wire _io_tracegen_req_ready_T_25 = ready_for_amo | _io_tracegen_req_ready_T_24; // @[tracegen.scala:39:45, :51:{20,23}] wire _io_tracegen_req_ready_T_26 = _io_tracegen_req_ready_T_2 & _io_tracegen_req_ready_T_25; // @[tracegen.scala:49:48, :50:26, :51:20] wire _io_tracegen_req_ready_T_27 = &rob_tail; // @[tracegen.scala:37:25, :45:13] wire [6:0] _GEN_0 = {1'h0, rob_tail} + 7'h1; // @[tracegen.scala:37:25, :45:37] wire [6:0] _io_tracegen_req_ready_T_28; // @[tracegen.scala:45:37] assign _io_tracegen_req_ready_T_28 = _GEN_0; // @[tracegen.scala:45:37] wire [6:0] _rob_tail_T_1; // @[tracegen.scala:45:37] assign _rob_tail_T_1 = _GEN_0; // @[tracegen.scala:45:37] wire [5:0] _io_tracegen_req_ready_T_29 = _io_tracegen_req_ready_T_28[5:0]; // @[tracegen.scala:45:37] wire [5:0] _io_tracegen_req_ready_T_30 = _io_tracegen_req_ready_T_27 ? 6'h0 : _io_tracegen_req_ready_T_29; // @[tracegen.scala:45:{8,13,37}] wire _io_tracegen_req_ready_T_31 = _io_tracegen_req_ready_T_30 != rob_head; // @[tracegen.scala:36:25, :45:8, :52:32] wire _io_tracegen_req_ready_T_32 = _io_tracegen_req_ready_T_26 & _io_tracegen_req_ready_T_31; // @[tracegen.scala:50:26, :51:135, :52:32] wire _GEN_1 = io_tracegen_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_33; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_33 = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T = _GEN_1; // @[package.scala:16:47] wire _GEN_2 = io_tracegen_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_34; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_34 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_1 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_ctrl_is_load_T_1; // @[package.scala:16:47] assign _tracegen_uop_ctrl_is_load_T_1 = _GEN_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_37 = _io_tracegen_req_ready_T_33 | _io_tracegen_req_ready_T_34; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_38 = _io_tracegen_req_ready_T_37 | _io_tracegen_req_ready_T_35; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_39 = _io_tracegen_req_ready_T_38 | _io_tracegen_req_ready_T_36; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_44 = _io_tracegen_req_ready_T_40 | _io_tracegen_req_ready_T_41; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_45 = _io_tracegen_req_ready_T_44 | _io_tracegen_req_ready_T_42; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_46 = _io_tracegen_req_ready_T_45 | _io_tracegen_req_ready_T_43; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_52 = _io_tracegen_req_ready_T_47 | _io_tracegen_req_ready_T_48; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_53 = _io_tracegen_req_ready_T_52 | _io_tracegen_req_ready_T_49; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_54 = _io_tracegen_req_ready_T_53 | _io_tracegen_req_ready_T_50; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_55 = _io_tracegen_req_ready_T_54 | _io_tracegen_req_ready_T_51; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_56 = _io_tracegen_req_ready_T_46 | _io_tracegen_req_ready_T_55; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_57 = _io_tracegen_req_ready_T_39 | _io_tracegen_req_ready_T_56; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_58 = io_lsu_ldq_full_0_0 & _io_tracegen_req_ready_T_57; // @[Consts.scala:89:68] wire _io_tracegen_req_ready_T_59 = ~_io_tracegen_req_ready_T_58; // @[tracegen.scala:53:{5,26}] wire _io_tracegen_req_ready_T_60 = _io_tracegen_req_ready_T_32 & _io_tracegen_req_ready_T_59; // @[tracegen.scala:51:135, :52:46, :53:5] wire _GEN_3 = io_tracegen_req_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _io_tracegen_req_ready_T_61; // @[Consts.scala:90:32] assign _io_tracegen_req_ready_T_61 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_ldq_T_25; // @[Consts.scala:90:32] assign _tracegen_uop_uses_ldq_T_25 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_stq_T; // @[Consts.scala:90:32] assign _tracegen_uop_uses_stq_T = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_ctrl_is_load_T_25; // @[Consts.scala:90:32] assign _tracegen_uop_ctrl_is_load_T_25 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_ctrl_is_sta_T; // @[Consts.scala:90:32] assign _tracegen_uop_ctrl_is_sta_T = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_ctrl_is_std_T; // @[Consts.scala:90:32] assign _tracegen_uop_ctrl_is_std_T = _GEN_3; // @[Consts.scala:90:32] wire _GEN_4 = io_tracegen_req_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_62; // @[Consts.scala:90:49] assign _io_tracegen_req_ready_T_62 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:49] assign _tracegen_uop_uses_ldq_T_26 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_uses_stq_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_ctrl_is_load_T_26; // @[Consts.scala:90:49] assign _tracegen_uop_ctrl_is_load_T_26 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_ctrl_is_sta_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_ctrl_is_sta_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_ctrl_is_std_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_ctrl_is_std_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_63 = _io_tracegen_req_ready_T_61 | _io_tracegen_req_ready_T_62; // @[Consts.scala:90:{32,42,49}] wire _io_tracegen_req_ready_T_65 = _io_tracegen_req_ready_T_63 | _io_tracegen_req_ready_T_64; // @[Consts.scala:90:{42,59,66}] wire _io_tracegen_req_ready_T_70 = _io_tracegen_req_ready_T_66 | _io_tracegen_req_ready_T_67; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_71 = _io_tracegen_req_ready_T_70 | _io_tracegen_req_ready_T_68; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_72 = _io_tracegen_req_ready_T_71 | _io_tracegen_req_ready_T_69; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_78 = _io_tracegen_req_ready_T_73 | _io_tracegen_req_ready_T_74; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_79 = _io_tracegen_req_ready_T_78 | _io_tracegen_req_ready_T_75; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_80 = _io_tracegen_req_ready_T_79 | _io_tracegen_req_ready_T_76; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_81 = _io_tracegen_req_ready_T_80 | _io_tracegen_req_ready_T_77; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_82 = _io_tracegen_req_ready_T_72 | _io_tracegen_req_ready_T_81; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_83 = _io_tracegen_req_ready_T_65 | _io_tracegen_req_ready_T_82; // @[Consts.scala:87:44, :90:{59,76}] wire _io_tracegen_req_ready_T_84 = io_lsu_stq_full_0_0 & _io_tracegen_req_ready_T_83; // @[Consts.scala:90:76] wire _io_tracegen_req_ready_T_85 = ~_io_tracegen_req_ready_T_84; // @[tracegen.scala:54:{5,26}] assign _io_tracegen_req_ready_T_86 = _io_tracegen_req_ready_T_60 & _io_tracegen_req_ready_T_85; // @[tracegen.scala:52:46, :53:63, :54:5] assign io_tracegen_req_ready_0 = _io_tracegen_req_ready_T_86; // @[tracegen.scala:20:7, :53:63] assign io_lsu_dis_uops_0_bits_uopc_0 = tracegen_uop_uopc; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_ctrl_is_load_T_49; // @[tracegen.scala:68:65] assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = tracegen_uop_ctrl_is_load; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_ctrl_is_sta_T_22; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = tracegen_uop_ctrl_is_sta; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_ctrl_is_std_T_22; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = tracegen_uop_ctrl_is_std; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_rob_idx_0 = tracegen_uop_rob_idx; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_ldq_idx_0 = tracegen_uop_ldq_idx; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_stq_idx_0 = tracegen_uop_stq_idx; // @[tracegen.scala:20:7, :57:30] assign io_lsu_dis_uops_0_bits_mem_cmd_0 = tracegen_uop_mem_cmd; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_is_amo_T_18; // @[tracegen.scala:67:64] assign io_lsu_dis_uops_0_bits_is_amo_0 = tracegen_uop_is_amo; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_uses_ldq_T_49; // @[tracegen.scala:58:65] assign io_lsu_dis_uops_0_bits_uses_ldq_0 = tracegen_uop_uses_ldq; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_uses_stq_T_22; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_uses_stq_0 = tracegen_uop_uses_stq; // @[tracegen.scala:20:7, :57:30] wire _tracegen_uop_uses_ldq_T_4 = _tracegen_uop_uses_ldq_T | _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_5 = _tracegen_uop_uses_ldq_T_4 | _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_6 = _tracegen_uop_uses_ldq_T_5 | _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_11 = _tracegen_uop_uses_ldq_T_7 | _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_12 = _tracegen_uop_uses_ldq_T_11 | _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_13 = _tracegen_uop_uses_ldq_T_12 | _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_19 = _tracegen_uop_uses_ldq_T_14 | _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_20 = _tracegen_uop_uses_ldq_T_19 | _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_21 = _tracegen_uop_uses_ldq_T_20 | _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_22 = _tracegen_uop_uses_ldq_T_21 | _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_23 = _tracegen_uop_uses_ldq_T_13 | _tracegen_uop_uses_ldq_T_22; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_24 = _tracegen_uop_uses_ldq_T_6 | _tracegen_uop_uses_ldq_T_23; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_27 = _tracegen_uop_uses_ldq_T_25 | _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_ldq_T_29 = _tracegen_uop_uses_ldq_T_27 | _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_ldq_T_34 = _tracegen_uop_uses_ldq_T_30 | _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_35 = _tracegen_uop_uses_ldq_T_34 | _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_36 = _tracegen_uop_uses_ldq_T_35 | _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_42 = _tracegen_uop_uses_ldq_T_37 | _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_43 = _tracegen_uop_uses_ldq_T_42 | _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_44 = _tracegen_uop_uses_ldq_T_43 | _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_45 = _tracegen_uop_uses_ldq_T_44 | _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_46 = _tracegen_uop_uses_ldq_T_36 | _tracegen_uop_uses_ldq_T_45; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_47 = _tracegen_uop_uses_ldq_T_29 | _tracegen_uop_uses_ldq_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_uses_ldq_T_48 = ~_tracegen_uop_uses_ldq_T_47; // @[Consts.scala:90:76] assign _tracegen_uop_uses_ldq_T_49 = _tracegen_uop_uses_ldq_T_24 & _tracegen_uop_uses_ldq_T_48; // @[Consts.scala:89:68] assign tracegen_uop_uses_ldq = _tracegen_uop_uses_ldq_T_49; // @[tracegen.scala:57:30, :58:65] wire _tracegen_uop_uses_stq_T_2 = _tracegen_uop_uses_stq_T | _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_stq_T_4 = _tracegen_uop_uses_stq_T_2 | _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_stq_T_9 = _tracegen_uop_uses_stq_T_5 | _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_10 = _tracegen_uop_uses_stq_T_9 | _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_11 = _tracegen_uop_uses_stq_T_10 | _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_17 = _tracegen_uop_uses_stq_T_12 | _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_18 = _tracegen_uop_uses_stq_T_17 | _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_19 = _tracegen_uop_uses_stq_T_18 | _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_20 = _tracegen_uop_uses_stq_T_19 | _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_21 = _tracegen_uop_uses_stq_T_11 | _tracegen_uop_uses_stq_T_20; // @[package.scala:81:59] assign _tracegen_uop_uses_stq_T_22 = _tracegen_uop_uses_stq_T_4 | _tracegen_uop_uses_stq_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_uses_stq = _tracegen_uop_uses_stq_T_22; // @[Consts.scala:90:76] assign tracegen_uop_uopc = {1'h0, io_tracegen_req_bits_tag_0}; // @[tracegen.scala:20:7, :57:30, :61:29] wire _tracegen_uop_is_amo_T_4 = _tracegen_uop_is_amo_T | _tracegen_uop_is_amo_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_5 = _tracegen_uop_is_amo_T_4 | _tracegen_uop_is_amo_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_6 = _tracegen_uop_is_amo_T_5 | _tracegen_uop_is_amo_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_12 = _tracegen_uop_is_amo_T_7 | _tracegen_uop_is_amo_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_13 = _tracegen_uop_is_amo_T_12 | _tracegen_uop_is_amo_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_14 = _tracegen_uop_is_amo_T_13 | _tracegen_uop_is_amo_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_15 = _tracegen_uop_is_amo_T_14 | _tracegen_uop_is_amo_T_11; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_16 = _tracegen_uop_is_amo_T_6 | _tracegen_uop_is_amo_T_15; // @[package.scala:81:59] assign _tracegen_uop_is_amo_T_18 = _tracegen_uop_is_amo_T_16 | _tracegen_uop_is_amo_T_17; // @[Consts.scala:87:44] assign tracegen_uop_is_amo = _tracegen_uop_is_amo_T_18; // @[tracegen.scala:57:30, :67:64] wire _tracegen_uop_ctrl_is_load_T_4 = _tracegen_uop_ctrl_is_load_T | _tracegen_uop_ctrl_is_load_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_5 = _tracegen_uop_ctrl_is_load_T_4 | _tracegen_uop_ctrl_is_load_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_6 = _tracegen_uop_ctrl_is_load_T_5 | _tracegen_uop_ctrl_is_load_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_11 = _tracegen_uop_ctrl_is_load_T_7 | _tracegen_uop_ctrl_is_load_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_12 = _tracegen_uop_ctrl_is_load_T_11 | _tracegen_uop_ctrl_is_load_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_13 = _tracegen_uop_ctrl_is_load_T_12 | _tracegen_uop_ctrl_is_load_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_19 = _tracegen_uop_ctrl_is_load_T_14 | _tracegen_uop_ctrl_is_load_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_20 = _tracegen_uop_ctrl_is_load_T_19 | _tracegen_uop_ctrl_is_load_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_21 = _tracegen_uop_ctrl_is_load_T_20 | _tracegen_uop_ctrl_is_load_T_17; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_22 = _tracegen_uop_ctrl_is_load_T_21 | _tracegen_uop_ctrl_is_load_T_18; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_23 = _tracegen_uop_ctrl_is_load_T_13 | _tracegen_uop_ctrl_is_load_T_22; // @[package.scala:81:59] wire _tracegen_uop_ctrl_is_load_T_24 = _tracegen_uop_ctrl_is_load_T_6 | _tracegen_uop_ctrl_is_load_T_23; // @[package.scala:81:59] wire _tracegen_uop_ctrl_is_load_T_27 = _tracegen_uop_ctrl_is_load_T_25 | _tracegen_uop_ctrl_is_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_ctrl_is_load_T_29 = _tracegen_uop_ctrl_is_load_T_27 | _tracegen_uop_ctrl_is_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_ctrl_is_load_T_34 = _tracegen_uop_ctrl_is_load_T_30 | _tracegen_uop_ctrl_is_load_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_35 = _tracegen_uop_ctrl_is_load_T_34 | _tracegen_uop_ctrl_is_load_T_32; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_36 = _tracegen_uop_ctrl_is_load_T_35 | _tracegen_uop_ctrl_is_load_T_33; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_42 = _tracegen_uop_ctrl_is_load_T_37 | _tracegen_uop_ctrl_is_load_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_43 = _tracegen_uop_ctrl_is_load_T_42 | _tracegen_uop_ctrl_is_load_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_44 = _tracegen_uop_ctrl_is_load_T_43 | _tracegen_uop_ctrl_is_load_T_40; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_45 = _tracegen_uop_ctrl_is_load_T_44 | _tracegen_uop_ctrl_is_load_T_41; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_load_T_46 = _tracegen_uop_ctrl_is_load_T_36 | _tracegen_uop_ctrl_is_load_T_45; // @[package.scala:81:59] wire _tracegen_uop_ctrl_is_load_T_47 = _tracegen_uop_ctrl_is_load_T_29 | _tracegen_uop_ctrl_is_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_ctrl_is_load_T_48 = ~_tracegen_uop_ctrl_is_load_T_47; // @[Consts.scala:90:76] assign _tracegen_uop_ctrl_is_load_T_49 = _tracegen_uop_ctrl_is_load_T_24 & _tracegen_uop_ctrl_is_load_T_48; // @[Consts.scala:89:68] assign tracegen_uop_ctrl_is_load = _tracegen_uop_ctrl_is_load_T_49; // @[tracegen.scala:57:30, :68:65] wire _tracegen_uop_ctrl_is_sta_T_2 = _tracegen_uop_ctrl_is_sta_T | _tracegen_uop_ctrl_is_sta_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_ctrl_is_sta_T_4 = _tracegen_uop_ctrl_is_sta_T_2 | _tracegen_uop_ctrl_is_sta_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_ctrl_is_sta_T_9 = _tracegen_uop_ctrl_is_sta_T_5 | _tracegen_uop_ctrl_is_sta_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_10 = _tracegen_uop_ctrl_is_sta_T_9 | _tracegen_uop_ctrl_is_sta_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_11 = _tracegen_uop_ctrl_is_sta_T_10 | _tracegen_uop_ctrl_is_sta_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_17 = _tracegen_uop_ctrl_is_sta_T_12 | _tracegen_uop_ctrl_is_sta_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_18 = _tracegen_uop_ctrl_is_sta_T_17 | _tracegen_uop_ctrl_is_sta_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_19 = _tracegen_uop_ctrl_is_sta_T_18 | _tracegen_uop_ctrl_is_sta_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_20 = _tracegen_uop_ctrl_is_sta_T_19 | _tracegen_uop_ctrl_is_sta_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_sta_T_21 = _tracegen_uop_ctrl_is_sta_T_11 | _tracegen_uop_ctrl_is_sta_T_20; // @[package.scala:81:59] assign _tracegen_uop_ctrl_is_sta_T_22 = _tracegen_uop_ctrl_is_sta_T_4 | _tracegen_uop_ctrl_is_sta_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_ctrl_is_sta = _tracegen_uop_ctrl_is_sta_T_22; // @[Consts.scala:90:76] wire _tracegen_uop_ctrl_is_std_T_2 = _tracegen_uop_ctrl_is_std_T | _tracegen_uop_ctrl_is_std_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_ctrl_is_std_T_4 = _tracegen_uop_ctrl_is_std_T_2 | _tracegen_uop_ctrl_is_std_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_ctrl_is_std_T_9 = _tracegen_uop_ctrl_is_std_T_5 | _tracegen_uop_ctrl_is_std_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_10 = _tracegen_uop_ctrl_is_std_T_9 | _tracegen_uop_ctrl_is_std_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_11 = _tracegen_uop_ctrl_is_std_T_10 | _tracegen_uop_ctrl_is_std_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_17 = _tracegen_uop_ctrl_is_std_T_12 | _tracegen_uop_ctrl_is_std_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_18 = _tracegen_uop_ctrl_is_std_T_17 | _tracegen_uop_ctrl_is_std_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_19 = _tracegen_uop_ctrl_is_std_T_18 | _tracegen_uop_ctrl_is_std_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_20 = _tracegen_uop_ctrl_is_std_T_19 | _tracegen_uop_ctrl_is_std_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_ctrl_is_std_T_21 = _tracegen_uop_ctrl_is_std_T_11 | _tracegen_uop_ctrl_is_std_T_20; // @[package.scala:81:59] assign _tracegen_uop_ctrl_is_std_T_22 = _tracegen_uop_ctrl_is_std_T_4 | _tracegen_uop_ctrl_is_std_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_ctrl_is_std = _tracegen_uop_ctrl_is_std_T_22; // @[Consts.scala:90:76] wire _T = io_tracegen_req_ready_0 & io_tracegen_req_valid_0; // @[Decoupled.scala:51:35] assign _io_lsu_dis_uops_0_valid_T = _T; // @[Decoupled.scala:51:35] wire _io_lsu_exe_0_req_valid_T; // @[Decoupled.scala:51:35] assign _io_lsu_exe_0_req_valid_T = _T; // @[Decoupled.scala:51:35] assign io_lsu_dis_uops_0_valid_0 = _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire _rob_tail_T = &rob_tail; // @[tracegen.scala:37:25, :45:13] wire [5:0] _rob_tail_T_2 = _rob_tail_T_1[5:0]; // @[tracegen.scala:45:37] wire [5:0] _rob_tail_T_3 = _rob_tail_T ? 6'h0 : _rob_tail_T_2; // @[tracegen.scala:45:{8,13,37}] wire _io_lsu_commit_valids_0_T = ~_GEN[rob_head]; // @[tracegen.scala:36:25, :49:29, :95:31] wire _io_lsu_commit_valids_0_T_1 = rob_head != rob_tail; // @[tracegen.scala:36:25, :37:25, :95:62] wire _io_lsu_commit_valids_0_T_2 = _io_lsu_commit_valids_0_T & _io_lsu_commit_valids_0_T_1; // @[tracegen.scala:95:{31,50,62}] wire [63:0] _GEN_5 = {{rob_respd_63}, {rob_respd_62}, {rob_respd_61}, {rob_respd_60}, {rob_respd_59}, {rob_respd_58}, {rob_respd_57}, {rob_respd_56}, {rob_respd_55}, {rob_respd_54}, {rob_respd_53}, {rob_respd_52}, {rob_respd_51}, {rob_respd_50}, {rob_respd_49}, {rob_respd_48}, {rob_respd_47}, {rob_respd_46}, {rob_respd_45}, {rob_respd_44}, {rob_respd_43}, {rob_respd_42}, {rob_respd_41}, {rob_respd_40}, {rob_respd_39}, {rob_respd_38}, {rob_respd_37}, {rob_respd_36}, {rob_respd_35}, {rob_respd_34}, {rob_respd_33}, {rob_respd_32}, {rob_respd_31}, {rob_respd_30}, {rob_respd_29}, {rob_respd_28}, {rob_respd_27}, {rob_respd_26}, {rob_respd_25}, {rob_respd_24}, {rob_respd_23}, {rob_respd_22}, {rob_respd_21}, {rob_respd_20}, {rob_respd_19}, {rob_respd_18}, {rob_respd_17}, {rob_respd_16}, {rob_respd_15}, {rob_respd_14}, {rob_respd_13}, {rob_respd_12}, {rob_respd_11}, {rob_respd_10}, {rob_respd_9}, {rob_respd_8}, {rob_respd_7}, {rob_respd_6}, {rob_respd_5}, {rob_respd_4}, {rob_respd_3}, {rob_respd_2}, {rob_respd_1}, {rob_respd_0}}; // @[tracegen.scala:33:26, :95:75] assign _io_lsu_commit_valids_0_T_3 = _io_lsu_commit_valids_0_T_2 & _GEN_5[rob_head]; // @[tracegen.scala:36:25, :95:{50,75}] assign io_lsu_commit_valids_0_0 = _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:20:7, :95:75] wire [63:0][6:0] _GEN_6 = {{rob_uop_63_uopc}, {rob_uop_62_uopc}, {rob_uop_61_uopc}, {rob_uop_60_uopc}, {rob_uop_59_uopc}, {rob_uop_58_uopc}, {rob_uop_57_uopc}, {rob_uop_56_uopc}, {rob_uop_55_uopc}, {rob_uop_54_uopc}, {rob_uop_53_uopc}, {rob_uop_52_uopc}, {rob_uop_51_uopc}, {rob_uop_50_uopc}, {rob_uop_49_uopc}, {rob_uop_48_uopc}, {rob_uop_47_uopc}, {rob_uop_46_uopc}, {rob_uop_45_uopc}, {rob_uop_44_uopc}, {rob_uop_43_uopc}, {rob_uop_42_uopc}, {rob_uop_41_uopc}, {rob_uop_40_uopc}, {rob_uop_39_uopc}, {rob_uop_38_uopc}, {rob_uop_37_uopc}, {rob_uop_36_uopc}, {rob_uop_35_uopc}, {rob_uop_34_uopc}, {rob_uop_33_uopc}, {rob_uop_32_uopc}, {rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_uopc_0 = _GEN_6[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_7 = {{rob_uop_63_ctrl_is_load}, {rob_uop_62_ctrl_is_load}, {rob_uop_61_ctrl_is_load}, {rob_uop_60_ctrl_is_load}, {rob_uop_59_ctrl_is_load}, {rob_uop_58_ctrl_is_load}, {rob_uop_57_ctrl_is_load}, {rob_uop_56_ctrl_is_load}, {rob_uop_55_ctrl_is_load}, {rob_uop_54_ctrl_is_load}, {rob_uop_53_ctrl_is_load}, {rob_uop_52_ctrl_is_load}, {rob_uop_51_ctrl_is_load}, {rob_uop_50_ctrl_is_load}, {rob_uop_49_ctrl_is_load}, {rob_uop_48_ctrl_is_load}, {rob_uop_47_ctrl_is_load}, {rob_uop_46_ctrl_is_load}, {rob_uop_45_ctrl_is_load}, {rob_uop_44_ctrl_is_load}, {rob_uop_43_ctrl_is_load}, {rob_uop_42_ctrl_is_load}, {rob_uop_41_ctrl_is_load}, {rob_uop_40_ctrl_is_load}, {rob_uop_39_ctrl_is_load}, {rob_uop_38_ctrl_is_load}, {rob_uop_37_ctrl_is_load}, {rob_uop_36_ctrl_is_load}, {rob_uop_35_ctrl_is_load}, {rob_uop_34_ctrl_is_load}, {rob_uop_33_ctrl_is_load}, {rob_uop_32_ctrl_is_load}, {rob_uop_31_ctrl_is_load}, {rob_uop_30_ctrl_is_load}, {rob_uop_29_ctrl_is_load}, {rob_uop_28_ctrl_is_load}, {rob_uop_27_ctrl_is_load}, {rob_uop_26_ctrl_is_load}, {rob_uop_25_ctrl_is_load}, {rob_uop_24_ctrl_is_load}, {rob_uop_23_ctrl_is_load}, {rob_uop_22_ctrl_is_load}, {rob_uop_21_ctrl_is_load}, {rob_uop_20_ctrl_is_load}, {rob_uop_19_ctrl_is_load}, {rob_uop_18_ctrl_is_load}, {rob_uop_17_ctrl_is_load}, {rob_uop_16_ctrl_is_load}, {rob_uop_15_ctrl_is_load}, {rob_uop_14_ctrl_is_load}, {rob_uop_13_ctrl_is_load}, {rob_uop_12_ctrl_is_load}, {rob_uop_11_ctrl_is_load}, {rob_uop_10_ctrl_is_load}, {rob_uop_9_ctrl_is_load}, {rob_uop_8_ctrl_is_load}, {rob_uop_7_ctrl_is_load}, {rob_uop_6_ctrl_is_load}, {rob_uop_5_ctrl_is_load}, {rob_uop_4_ctrl_is_load}, {rob_uop_3_ctrl_is_load}, {rob_uop_2_ctrl_is_load}, {rob_uop_1_ctrl_is_load}, {rob_uop_0_ctrl_is_load}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ctrl_is_load_0 = _GEN_7[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_8 = {{rob_uop_63_ctrl_is_sta}, {rob_uop_62_ctrl_is_sta}, {rob_uop_61_ctrl_is_sta}, {rob_uop_60_ctrl_is_sta}, {rob_uop_59_ctrl_is_sta}, {rob_uop_58_ctrl_is_sta}, {rob_uop_57_ctrl_is_sta}, {rob_uop_56_ctrl_is_sta}, {rob_uop_55_ctrl_is_sta}, {rob_uop_54_ctrl_is_sta}, {rob_uop_53_ctrl_is_sta}, {rob_uop_52_ctrl_is_sta}, {rob_uop_51_ctrl_is_sta}, {rob_uop_50_ctrl_is_sta}, {rob_uop_49_ctrl_is_sta}, {rob_uop_48_ctrl_is_sta}, {rob_uop_47_ctrl_is_sta}, {rob_uop_46_ctrl_is_sta}, {rob_uop_45_ctrl_is_sta}, {rob_uop_44_ctrl_is_sta}, {rob_uop_43_ctrl_is_sta}, {rob_uop_42_ctrl_is_sta}, {rob_uop_41_ctrl_is_sta}, {rob_uop_40_ctrl_is_sta}, {rob_uop_39_ctrl_is_sta}, {rob_uop_38_ctrl_is_sta}, {rob_uop_37_ctrl_is_sta}, {rob_uop_36_ctrl_is_sta}, {rob_uop_35_ctrl_is_sta}, {rob_uop_34_ctrl_is_sta}, {rob_uop_33_ctrl_is_sta}, {rob_uop_32_ctrl_is_sta}, {rob_uop_31_ctrl_is_sta}, {rob_uop_30_ctrl_is_sta}, {rob_uop_29_ctrl_is_sta}, {rob_uop_28_ctrl_is_sta}, {rob_uop_27_ctrl_is_sta}, {rob_uop_26_ctrl_is_sta}, {rob_uop_25_ctrl_is_sta}, {rob_uop_24_ctrl_is_sta}, {rob_uop_23_ctrl_is_sta}, {rob_uop_22_ctrl_is_sta}, {rob_uop_21_ctrl_is_sta}, {rob_uop_20_ctrl_is_sta}, {rob_uop_19_ctrl_is_sta}, {rob_uop_18_ctrl_is_sta}, {rob_uop_17_ctrl_is_sta}, {rob_uop_16_ctrl_is_sta}, {rob_uop_15_ctrl_is_sta}, {rob_uop_14_ctrl_is_sta}, {rob_uop_13_ctrl_is_sta}, {rob_uop_12_ctrl_is_sta}, {rob_uop_11_ctrl_is_sta}, {rob_uop_10_ctrl_is_sta}, {rob_uop_9_ctrl_is_sta}, {rob_uop_8_ctrl_is_sta}, {rob_uop_7_ctrl_is_sta}, {rob_uop_6_ctrl_is_sta}, {rob_uop_5_ctrl_is_sta}, {rob_uop_4_ctrl_is_sta}, {rob_uop_3_ctrl_is_sta}, {rob_uop_2_ctrl_is_sta}, {rob_uop_1_ctrl_is_sta}, {rob_uop_0_ctrl_is_sta}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ctrl_is_sta_0 = _GEN_8[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_9 = {{rob_uop_63_ctrl_is_std}, {rob_uop_62_ctrl_is_std}, {rob_uop_61_ctrl_is_std}, {rob_uop_60_ctrl_is_std}, {rob_uop_59_ctrl_is_std}, {rob_uop_58_ctrl_is_std}, {rob_uop_57_ctrl_is_std}, {rob_uop_56_ctrl_is_std}, {rob_uop_55_ctrl_is_std}, {rob_uop_54_ctrl_is_std}, {rob_uop_53_ctrl_is_std}, {rob_uop_52_ctrl_is_std}, {rob_uop_51_ctrl_is_std}, {rob_uop_50_ctrl_is_std}, {rob_uop_49_ctrl_is_std}, {rob_uop_48_ctrl_is_std}, {rob_uop_47_ctrl_is_std}, {rob_uop_46_ctrl_is_std}, {rob_uop_45_ctrl_is_std}, {rob_uop_44_ctrl_is_std}, {rob_uop_43_ctrl_is_std}, {rob_uop_42_ctrl_is_std}, {rob_uop_41_ctrl_is_std}, {rob_uop_40_ctrl_is_std}, {rob_uop_39_ctrl_is_std}, {rob_uop_38_ctrl_is_std}, {rob_uop_37_ctrl_is_std}, {rob_uop_36_ctrl_is_std}, {rob_uop_35_ctrl_is_std}, {rob_uop_34_ctrl_is_std}, {rob_uop_33_ctrl_is_std}, {rob_uop_32_ctrl_is_std}, {rob_uop_31_ctrl_is_std}, {rob_uop_30_ctrl_is_std}, {rob_uop_29_ctrl_is_std}, {rob_uop_28_ctrl_is_std}, {rob_uop_27_ctrl_is_std}, {rob_uop_26_ctrl_is_std}, {rob_uop_25_ctrl_is_std}, {rob_uop_24_ctrl_is_std}, {rob_uop_23_ctrl_is_std}, {rob_uop_22_ctrl_is_std}, {rob_uop_21_ctrl_is_std}, {rob_uop_20_ctrl_is_std}, {rob_uop_19_ctrl_is_std}, {rob_uop_18_ctrl_is_std}, {rob_uop_17_ctrl_is_std}, {rob_uop_16_ctrl_is_std}, {rob_uop_15_ctrl_is_std}, {rob_uop_14_ctrl_is_std}, {rob_uop_13_ctrl_is_std}, {rob_uop_12_ctrl_is_std}, {rob_uop_11_ctrl_is_std}, {rob_uop_10_ctrl_is_std}, {rob_uop_9_ctrl_is_std}, {rob_uop_8_ctrl_is_std}, {rob_uop_7_ctrl_is_std}, {rob_uop_6_ctrl_is_std}, {rob_uop_5_ctrl_is_std}, {rob_uop_4_ctrl_is_std}, {rob_uop_3_ctrl_is_std}, {rob_uop_2_ctrl_is_std}, {rob_uop_1_ctrl_is_std}, {rob_uop_0_ctrl_is_std}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ctrl_is_std_0 = _GEN_9[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][5:0] _GEN_10 = {{rob_uop_63_rob_idx}, {rob_uop_62_rob_idx}, {rob_uop_61_rob_idx}, {rob_uop_60_rob_idx}, {rob_uop_59_rob_idx}, {rob_uop_58_rob_idx}, {rob_uop_57_rob_idx}, {rob_uop_56_rob_idx}, {rob_uop_55_rob_idx}, {rob_uop_54_rob_idx}, {rob_uop_53_rob_idx}, {rob_uop_52_rob_idx}, {rob_uop_51_rob_idx}, {rob_uop_50_rob_idx}, {rob_uop_49_rob_idx}, {rob_uop_48_rob_idx}, {rob_uop_47_rob_idx}, {rob_uop_46_rob_idx}, {rob_uop_45_rob_idx}, {rob_uop_44_rob_idx}, {rob_uop_43_rob_idx}, {rob_uop_42_rob_idx}, {rob_uop_41_rob_idx}, {rob_uop_40_rob_idx}, {rob_uop_39_rob_idx}, {rob_uop_38_rob_idx}, {rob_uop_37_rob_idx}, {rob_uop_36_rob_idx}, {rob_uop_35_rob_idx}, {rob_uop_34_rob_idx}, {rob_uop_33_rob_idx}, {rob_uop_32_rob_idx}, {rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_rob_idx_0 = _GEN_10[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][3:0] _GEN_11 = {{rob_uop_63_ldq_idx}, {rob_uop_62_ldq_idx}, {rob_uop_61_ldq_idx}, {rob_uop_60_ldq_idx}, {rob_uop_59_ldq_idx}, {rob_uop_58_ldq_idx}, {rob_uop_57_ldq_idx}, {rob_uop_56_ldq_idx}, {rob_uop_55_ldq_idx}, {rob_uop_54_ldq_idx}, {rob_uop_53_ldq_idx}, {rob_uop_52_ldq_idx}, {rob_uop_51_ldq_idx}, {rob_uop_50_ldq_idx}, {rob_uop_49_ldq_idx}, {rob_uop_48_ldq_idx}, {rob_uop_47_ldq_idx}, {rob_uop_46_ldq_idx}, {rob_uop_45_ldq_idx}, {rob_uop_44_ldq_idx}, {rob_uop_43_ldq_idx}, {rob_uop_42_ldq_idx}, {rob_uop_41_ldq_idx}, {rob_uop_40_ldq_idx}, {rob_uop_39_ldq_idx}, {rob_uop_38_ldq_idx}, {rob_uop_37_ldq_idx}, {rob_uop_36_ldq_idx}, {rob_uop_35_ldq_idx}, {rob_uop_34_ldq_idx}, {rob_uop_33_ldq_idx}, {rob_uop_32_ldq_idx}, {rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_ldq_idx_0 = _GEN_11[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][3:0] _GEN_12 = {{rob_uop_63_stq_idx}, {rob_uop_62_stq_idx}, {rob_uop_61_stq_idx}, {rob_uop_60_stq_idx}, {rob_uop_59_stq_idx}, {rob_uop_58_stq_idx}, {rob_uop_57_stq_idx}, {rob_uop_56_stq_idx}, {rob_uop_55_stq_idx}, {rob_uop_54_stq_idx}, {rob_uop_53_stq_idx}, {rob_uop_52_stq_idx}, {rob_uop_51_stq_idx}, {rob_uop_50_stq_idx}, {rob_uop_49_stq_idx}, {rob_uop_48_stq_idx}, {rob_uop_47_stq_idx}, {rob_uop_46_stq_idx}, {rob_uop_45_stq_idx}, {rob_uop_44_stq_idx}, {rob_uop_43_stq_idx}, {rob_uop_42_stq_idx}, {rob_uop_41_stq_idx}, {rob_uop_40_stq_idx}, {rob_uop_39_stq_idx}, {rob_uop_38_stq_idx}, {rob_uop_37_stq_idx}, {rob_uop_36_stq_idx}, {rob_uop_35_stq_idx}, {rob_uop_34_stq_idx}, {rob_uop_33_stq_idx}, {rob_uop_32_stq_idx}, {rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_stq_idx_0 = _GEN_12[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0][4:0] _GEN_13 = {{rob_uop_63_mem_cmd}, {rob_uop_62_mem_cmd}, {rob_uop_61_mem_cmd}, {rob_uop_60_mem_cmd}, {rob_uop_59_mem_cmd}, {rob_uop_58_mem_cmd}, {rob_uop_57_mem_cmd}, {rob_uop_56_mem_cmd}, {rob_uop_55_mem_cmd}, {rob_uop_54_mem_cmd}, {rob_uop_53_mem_cmd}, {rob_uop_52_mem_cmd}, {rob_uop_51_mem_cmd}, {rob_uop_50_mem_cmd}, {rob_uop_49_mem_cmd}, {rob_uop_48_mem_cmd}, {rob_uop_47_mem_cmd}, {rob_uop_46_mem_cmd}, {rob_uop_45_mem_cmd}, {rob_uop_44_mem_cmd}, {rob_uop_43_mem_cmd}, {rob_uop_42_mem_cmd}, {rob_uop_41_mem_cmd}, {rob_uop_40_mem_cmd}, {rob_uop_39_mem_cmd}, {rob_uop_38_mem_cmd}, {rob_uop_37_mem_cmd}, {rob_uop_36_mem_cmd}, {rob_uop_35_mem_cmd}, {rob_uop_34_mem_cmd}, {rob_uop_33_mem_cmd}, {rob_uop_32_mem_cmd}, {rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_mem_cmd_0 = _GEN_13[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_14 = {{rob_uop_63_is_amo}, {rob_uop_62_is_amo}, {rob_uop_61_is_amo}, {rob_uop_60_is_amo}, {rob_uop_59_is_amo}, {rob_uop_58_is_amo}, {rob_uop_57_is_amo}, {rob_uop_56_is_amo}, {rob_uop_55_is_amo}, {rob_uop_54_is_amo}, {rob_uop_53_is_amo}, {rob_uop_52_is_amo}, {rob_uop_51_is_amo}, {rob_uop_50_is_amo}, {rob_uop_49_is_amo}, {rob_uop_48_is_amo}, {rob_uop_47_is_amo}, {rob_uop_46_is_amo}, {rob_uop_45_is_amo}, {rob_uop_44_is_amo}, {rob_uop_43_is_amo}, {rob_uop_42_is_amo}, {rob_uop_41_is_amo}, {rob_uop_40_is_amo}, {rob_uop_39_is_amo}, {rob_uop_38_is_amo}, {rob_uop_37_is_amo}, {rob_uop_36_is_amo}, {rob_uop_35_is_amo}, {rob_uop_34_is_amo}, {rob_uop_33_is_amo}, {rob_uop_32_is_amo}, {rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_is_amo_0 = _GEN_14[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_15 = {{rob_uop_63_uses_ldq}, {rob_uop_62_uses_ldq}, {rob_uop_61_uses_ldq}, {rob_uop_60_uses_ldq}, {rob_uop_59_uses_ldq}, {rob_uop_58_uses_ldq}, {rob_uop_57_uses_ldq}, {rob_uop_56_uses_ldq}, {rob_uop_55_uses_ldq}, {rob_uop_54_uses_ldq}, {rob_uop_53_uses_ldq}, {rob_uop_52_uses_ldq}, {rob_uop_51_uses_ldq}, {rob_uop_50_uses_ldq}, {rob_uop_49_uses_ldq}, {rob_uop_48_uses_ldq}, {rob_uop_47_uses_ldq}, {rob_uop_46_uses_ldq}, {rob_uop_45_uses_ldq}, {rob_uop_44_uses_ldq}, {rob_uop_43_uses_ldq}, {rob_uop_42_uses_ldq}, {rob_uop_41_uses_ldq}, {rob_uop_40_uses_ldq}, {rob_uop_39_uses_ldq}, {rob_uop_38_uses_ldq}, {rob_uop_37_uses_ldq}, {rob_uop_36_uses_ldq}, {rob_uop_35_uses_ldq}, {rob_uop_34_uses_ldq}, {rob_uop_33_uses_ldq}, {rob_uop_32_uses_ldq}, {rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_uses_ldq_0 = _GEN_15[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire [63:0] _GEN_16 = {{rob_uop_63_uses_stq}, {rob_uop_62_uses_stq}, {rob_uop_61_uses_stq}, {rob_uop_60_uses_stq}, {rob_uop_59_uses_stq}, {rob_uop_58_uses_stq}, {rob_uop_57_uses_stq}, {rob_uop_56_uses_stq}, {rob_uop_55_uses_stq}, {rob_uop_54_uses_stq}, {rob_uop_53_uses_stq}, {rob_uop_52_uses_stq}, {rob_uop_51_uses_stq}, {rob_uop_50_uses_stq}, {rob_uop_49_uses_stq}, {rob_uop_48_uses_stq}, {rob_uop_47_uses_stq}, {rob_uop_46_uses_stq}, {rob_uop_45_uses_stq}, {rob_uop_44_uses_stq}, {rob_uop_43_uses_stq}, {rob_uop_42_uses_stq}, {rob_uop_41_uses_stq}, {rob_uop_40_uses_stq}, {rob_uop_39_uses_stq}, {rob_uop_38_uses_stq}, {rob_uop_37_uses_stq}, {rob_uop_36_uses_stq}, {rob_uop_35_uses_stq}, {rob_uop_34_uses_stq}, {rob_uop_33_uses_stq}, {rob_uop_32_uses_stq}, {rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[tracegen.scala:34:20, :96:27] assign io_lsu_commit_uops_0_uses_stq_0 = _GEN_16[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27] wire _rob_head_T = &rob_head; // @[tracegen.scala:36:25, :45:13] wire [6:0] _rob_head_T_1 = {1'h0, rob_head} + 7'h1; // @[tracegen.scala:36:25, :45:37] wire [5:0] _rob_head_T_2 = _rob_head_T_1[5:0]; // @[tracegen.scala:45:37] wire [5:0] _rob_head_T_3 = _rob_head_T ? 6'h0 : _rob_head_T_2; // @[tracegen.scala:45:{8,13,37}]

Generate the Verilog code corresponding to this FIRRTL code module InputUnit_14 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_14 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_14 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_11 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_12 : connect states[2].g, UInt<3>(0h2) node _T_13 = and(io.router_req.ready, io.router_req.valid) when _T_13 : node _T_14 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_14, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_18 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_18 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_19 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_19 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_20 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_20 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.router_resp.vc_sel.`5` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_21 = and(io.router_req.ready, io.router_req.valid) when _T_21 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_22 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_23 = or(_T_22, vcalloc_vals[2]) when _T_23 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[3] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE_14[1], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_14[2], _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>[1] node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_18[0], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_18 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[1] node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE_1.`5`, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_22 wire _io_vcalloc_req_bits_WIRE_23 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_24 : UInt<2> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_23.egress_node_id, _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_87 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_85) wire _io_vcalloc_req_bits_WIRE_25 : UInt<4> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_87 connect _io_vcalloc_req_bits_WIRE_23.egress_node, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_88, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_26 : UInt<3> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_92 connect _io_vcalloc_req_bits_WIRE_23.ingress_node_id, _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_27 : UInt<4> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_23.ingress_node, _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_100) wire _io_vcalloc_req_bits_WIRE_28 : UInt<2> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_102 connect _io_vcalloc_req_bits_WIRE_23.vnet_id, _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_23 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`4`[0] invalidate vcalloc_reqs[0].vc_sel.`5`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, states[1].vc_sel.`5` connect vcalloc_reqs[1].flow, states[1].flow node _T_24 = bits(vcalloc_sel, 1, 1) node _T_25 = and(vcalloc_vals[1], _T_24) node _T_26 = and(_T_25, io.vcalloc_req.ready) when _T_26 : connect states[1].g, UInt<3>(0h3) node _T_27 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_27 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, states[2].vc_sel.`5` connect vcalloc_reqs[2].flow, states[2].flow node _T_28 = bits(vcalloc_sel, 2, 2) node _T_29 = and(vcalloc_vals[2], _T_28) node _T_30 = and(_T_29, io.vcalloc_req.ready) when _T_30 : connect states[2].g, UInt<3>(0h3) node _T_31 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_31 : connect vcalloc_vals[2], UInt<1>(0h1) connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, io.router_resp.vc_sel.`5` node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_32 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_32 : node _T_33 = bits(vcalloc_sel, 0, 0) when _T_33 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[0].g, UInt<3>(0h3) node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[1].g, UInt<3>(0h3) node _T_35 = bits(vcalloc_sel, 2, 2) when _T_35 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_35 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`5`[0] node credit_available_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[1].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[1].vc_sel.`1`[2], states[1].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[1].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[1].vc_sel.`2`[2], states[1].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[1].vc_sel.`2`[0]) node credit_available_hi_3 = cat(states[1].vc_sel.`3`[2], states[1].vc_sel.`3`[1]) node _credit_available_T_3 = cat(credit_available_hi_3, states[1].vc_sel.`3`[0]) node credit_available_lo_hi = cat(_credit_available_T_2, _credit_available_T_1) node credit_available_lo = cat(credit_available_lo_hi, _credit_available_T) node credit_available_hi_hi = cat(states[1].vc_sel.`5`[0], states[1].vc_sel.`4`[0]) node credit_available_hi_4 = cat(credit_available_hi_hi, _credit_available_T_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo) node credit_available_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`1`[0]) node credit_available_hi_7 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_7 = cat(credit_available_hi_7, io.out_credit_available.`2`[0]) node credit_available_hi_8 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_8 = cat(credit_available_hi_8, io.out_credit_available.`3`[0]) node credit_available_lo_hi_1 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_lo_1 = cat(credit_available_lo_hi_1, _credit_available_T_5) node credit_available_hi_hi_1 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_9 = cat(credit_available_hi_hi_1, _credit_available_T_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_1) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`5`[0], states[1].vc_sel.`5`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_36 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_37 = and(_T_36, input_buffer.io.deq[1].bits.tail) when _T_37 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_hi_10 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node _credit_available_T_11 = cat(credit_available_hi_10, states[2].vc_sel.`0`[0]) node credit_available_hi_11 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1]) node _credit_available_T_12 = cat(credit_available_hi_11, states[2].vc_sel.`1`[0]) node credit_available_hi_12 = cat(states[2].vc_sel.`2`[2], states[2].vc_sel.`2`[1]) node _credit_available_T_13 = cat(credit_available_hi_12, states[2].vc_sel.`2`[0]) node credit_available_hi_13 = cat(states[2].vc_sel.`3`[2], states[2].vc_sel.`3`[1]) node _credit_available_T_14 = cat(credit_available_hi_13, states[2].vc_sel.`3`[0]) node credit_available_lo_hi_2 = cat(_credit_available_T_13, _credit_available_T_12) node credit_available_lo_2 = cat(credit_available_lo_hi_2, _credit_available_T_11) node credit_available_hi_hi_2 = cat(states[2].vc_sel.`5`[0], states[2].vc_sel.`4`[0]) node credit_available_hi_14 = cat(credit_available_hi_hi_2, _credit_available_T_14) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_2) node credit_available_hi_15 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_16 = cat(credit_available_hi_15, io.out_credit_available.`0`[0]) node credit_available_hi_16 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_17 = cat(credit_available_hi_16, io.out_credit_available.`1`[0]) node credit_available_hi_17 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_18 = cat(credit_available_hi_17, io.out_credit_available.`2`[0]) node credit_available_hi_18 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_19 = cat(credit_available_hi_18, io.out_credit_available.`3`[0]) node credit_available_lo_hi_3 = cat(_credit_available_T_18, _credit_available_T_17) node credit_available_lo_3 = cat(credit_available_lo_hi_3, _credit_available_T_16) node credit_available_hi_hi_3 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_19 = cat(credit_available_hi_hi_3, _credit_available_T_19) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_3) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`5`[0], states[2].vc_sel.`5`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_38 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_39 = and(_T_38, input_buffer.io.deq[2].bits.tail) when _T_39 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[3] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_55) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_57 connect _vc_sel_WIRE_12[1], _vc_sel_WIRE_14 node _vc_sel_T_58 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_58, _vc_sel_T_59) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_60) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_62 connect _vc_sel_WIRE_12[2], _vc_sel_WIRE_15 connect vc_sel.`3`, _vc_sel_WIRE_12 wire _vc_sel_WIRE_16 : UInt<1>[1] node _vc_sel_T_63 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_66 = or(_vc_sel_T_63, _vc_sel_T_64) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_65) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_67 connect _vc_sel_WIRE_16[0], _vc_sel_WIRE_17 connect vc_sel.`4`, _vc_sel_WIRE_16 wire _vc_sel_WIRE_18 : UInt<1>[1] node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_71 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_72 = or(_vc_sel_T_71, _vc_sel_T_70) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_72 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 connect vc_sel.`5`, _vc_sel_WIRE_18 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node _channel_oh_T_3 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node channel_oh_3 = or(_channel_oh_T_3, vc_sel.`3`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node virt_channel_hi_6 = cat(vc_sel.`3`[2], vc_sel.`3`[1]) node _virt_channel_T_15 = cat(virt_channel_hi_6, vc_sel.`3`[0]) node virt_channel_hi_7 = bits(_virt_channel_T_15, 2, 2) node virt_channel_lo_3 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_3) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_21 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_22 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_23 = mux(channel_oh_3, _virt_channel_T_19, UInt<1>(0h0)) node _virt_channel_T_24 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_25 = mux(vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_26 = or(_virt_channel_T_20, _virt_channel_T_21) node _virt_channel_T_27 = or(_virt_channel_T_26, _virt_channel_T_22) node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_23) node _virt_channel_T_29 = or(_virt_channel_T_28, _virt_channel_T_24) node _virt_channel_T_30 = or(_virt_channel_T_29, _virt_channel_T_25) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_30 node _T_40 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_40 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`4`[0] invalidate states[0].vc_sel.`5`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[1], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) node _T_41 = asUInt(reset) when _T_41 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)

module InputUnit_14( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire _GEN_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_3_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_2_2; // @[MixedVec.scala:116:9] wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_1; // @[MixedVec.scala:116:9] wire _GEN_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_3_1; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_2_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_3 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_4 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_5 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_128 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_129 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_130 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 1 parameter FORMAT = "uart_tx=%d" parameter WIDTH = 32 extmodule plusarg_reader_131 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "uart_tx_printf=%d" parameter WIDTH = 32

module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_Phit_19 : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<4> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_39 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<4> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) node _index_T = bits(ridx, 2, 0) node _index_T_1 = bits(ridx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w32_19 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset connect io_deq_bits_deq_bits_reg.io.d, io.async.mem[index].phit connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { phit : UInt<32>} wire _io_deq_bits_WIRE_1 : UInt<32> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 31, 0) connect _io_deq_bits_WIRE.phit, _io_deq_bits_T connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_180 inst sink_valid_1 of AsyncValidSync_181 inst source_extend of AsyncValidSync_182 inst source_valid of AsyncValidSync_183 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1

module AsyncQueueSink_Phit_19( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18] wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_198 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_198( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_63 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_63( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_32 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_32( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Pipeline_4 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}, busy : UInt<1>} reg stages : { data : UInt<128>, fromDMA : UInt<1>}[4], clock wire _valids_WIRE : UInt<1>[4] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) regreset valids : UInt<1>[4], clock, reset, _valids_WIRE wire stalling : UInt<1>[4] connect stalling[0], UInt<1>(0h0) connect stalling[1], UInt<1>(0h0) connect stalling[2], UInt<1>(0h0) connect stalling[3], UInt<1>(0h0) node _io_busy_T = or(valids[0], valids[1]) node _io_busy_T_1 = or(_io_busy_T, valids[2]) node _io_busy_T_2 = or(_io_busy_T_1, valids[3]) node _io_busy_T_3 = or(io.in.valid, _io_busy_T_2) connect io.busy, _io_busy_T_3 node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_3_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_3_T_1 = and(valids[3], _stalling_3_T) connect stalling[3], _stalling_3_T_1 node _stalling_0_T = and(valids[0], stalling[1]) connect stalling[0], _stalling_0_T node _stalling_1_T = and(valids[1], stalling[2]) connect stalling[1], _stalling_1_T node _stalling_2_T = and(valids[2], stalling[3]) connect stalling[2], _stalling_2_T connect io.out.valid, valids[3] when io.out.ready : connect valids[3], UInt<1>(0h0) node _T = eq(stalling[1], UInt<1>(0h0)) when _T : connect valids[0], UInt<1>(0h0) node _T_1 = eq(stalling[2], UInt<1>(0h0)) when _T_1 : connect valids[1], UInt<1>(0h0) node _T_2 = eq(stalling[3], UInt<1>(0h0)) when _T_2 : connect valids[2], UInt<1>(0h0) node _T_3 = and(io.in.ready, io.in.valid) when _T_3 : connect valids[0], UInt<1>(0h1) when valids[0] : connect valids[1], UInt<1>(0h1) when valids[1] : connect valids[2], UInt<1>(0h1) when valids[2] : connect valids[3], UInt<1>(0h1) node _T_4 = and(io.in.ready, io.in.valid) when _T_4 : connect stages[0], io.in.bits connect io.out.bits, stages[3] node _T_5 = eq(stalling[1], UInt<1>(0h0)) when _T_5 : connect stages[1], stages[0] node _T_6 = eq(stalling[2], UInt<1>(0h0)) when _T_6 : connect stages[2], stages[1] node _T_7 = eq(stalling[3], UInt<1>(0h0)) when _T_7 : connect stages[3], stages[2]

module Pipeline_4( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [127:0] io_in_bits_data, // @[Pipeline.scala:7:14] input io_in_bits_fromDMA, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [127:0] io_out_bits_data, // @[Pipeline.scala:7:14] output io_out_bits_fromDMA // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[Pipeline.scala:6:7] wire io_in_bits_fromDMA_0 = io_in_bits_fromDMA; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_3; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [127:0] io_out_bits_data_0; // @[Pipeline.scala:6:7] wire io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [127:0] stages_0_data; // @[Pipeline.scala:21:21] reg stages_0_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_1_data; // @[Pipeline.scala:21:21] reg stages_1_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_2_data; // @[Pipeline.scala:21:21] reg stages_2_fromDMA; // @[Pipeline.scala:21:21] reg [127:0] stages_3_data; // @[Pipeline.scala:21:21] assign io_out_bits_data_0 = stages_3_data; // @[Pipeline.scala:6:7, :21:21] reg stages_3_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_fromDMA_0 = stages_3_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T | valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 | valids_3; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_3 = io_in_valid_0 | _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_4) begin // @[Decoupled.scala:51:35] stages_0_data <= io_in_bits_data_0; // @[Pipeline.scala:6:7, :21:21] stages_0_fromDMA <= io_in_bits_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_data <= stages_0_data; // @[Pipeline.scala:21:21] stages_1_fromDMA <= stages_0_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_data <= stages_1_data; // @[Pipeline.scala:21:21] stages_2_fromDMA <= stages_1_fromDMA; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_data <= stages_2_data; // @[Pipeline.scala:21:21] stages_3_fromDMA <= stages_2_fromDMA; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_4 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 | stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 | ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_data = io_out_bits_data_0; // @[Pipeline.scala:6:7] assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[Pipeline.scala:6:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AXI4IdIndexer : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<7>}, extra_id : UInt<3>}, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.echo.extra_id invalidate nodeOut.r.bits.echo.tl_state.source invalidate nodeOut.r.bits.echo.tl_state.size invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.echo.extra_id invalidate nodeOut.ar.bits.echo.tl_state.source invalidate nodeOut.ar.bits.echo.tl_state.size invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.echo.extra_id invalidate nodeOut.b.bits.echo.tl_state.source invalidate nodeOut.b.bits.echo.tl_state.size invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.echo.extra_id invalidate nodeOut.aw.bits.echo.tl_state.source invalidate nodeOut.aw.bits.echo.tl_state.size invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.ar.bits.echo.tl_state.source, nodeIn.ar.bits.echo.tl_state.source connect nodeOut.ar.bits.echo.tl_state.size, nodeIn.ar.bits.echo.tl_state.size connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id connect nodeOut.ar.valid, nodeIn.ar.valid connect nodeIn.ar.ready, nodeOut.ar.ready connect nodeOut.aw.bits.echo.tl_state.source, nodeIn.aw.bits.echo.tl_state.source connect nodeOut.aw.bits.echo.tl_state.size, nodeIn.aw.bits.echo.tl_state.size connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id connect nodeOut.aw.valid, nodeIn.aw.valid connect nodeIn.aw.ready, nodeOut.aw.ready connect nodeOut.w.bits.last, nodeIn.w.bits.last connect nodeOut.w.bits.strb, nodeIn.w.bits.strb connect nodeOut.w.bits.data, nodeIn.w.bits.data connect nodeOut.w.valid, nodeIn.w.valid connect nodeIn.w.ready, nodeOut.w.ready connect nodeIn.b.bits.echo.tl_state.source, nodeOut.b.bits.echo.tl_state.source connect nodeIn.b.bits.echo.tl_state.size, nodeOut.b.bits.echo.tl_state.size connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.echo.tl_state.source, nodeOut.r.bits.echo.tl_state.source connect nodeIn.r.bits.echo.tl_state.size, nodeOut.r.bits.echo.tl_state.size connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready node _nodeOut_ar_bits_echo_extra_id_T = shr(nodeIn.ar.bits.id, 4) connect nodeOut.ar.bits.echo.extra_id, _nodeOut_ar_bits_echo_extra_id_T node _nodeOut_aw_bits_echo_extra_id_T = shr(nodeIn.aw.bits.id, 4) connect nodeOut.aw.bits.echo.extra_id, _nodeOut_aw_bits_echo_extra_id_T node _nodeIn_r_bits_id_T = cat(nodeOut.r.bits.echo.extra_id, nodeOut.r.bits.id) connect nodeIn.r.bits.id, _nodeIn_r_bits_id_T node _nodeIn_b_bits_id_T = cat(nodeOut.b.bits.echo.extra_id, nodeOut.b.bits.id) connect nodeIn.b.bits.id, _nodeIn_b_bits_id_T extmodule plusarg_reader_126 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_127 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module AXI4IdIndexer( // @[IdIndexer.scala:63:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); assign auto_in_aw_ready = auto_out_aw_ready; // @[IdIndexer.scala:63:9] assign auto_in_w_ready = auto_out_w_ready; // @[IdIndexer.scala:63:9] assign auto_in_b_valid = auto_out_b_valid; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_id = {auto_out_b_bits_echo_extra_id, auto_out_b_bits_id}; // @[IdIndexer.scala:63:9, :97:30] assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_ar_ready = auto_out_ar_ready; // @[IdIndexer.scala:63:9] assign auto_in_r_valid = auto_out_r_valid; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_id = {auto_out_r_bits_echo_extra_id, auto_out_r_bits_id}; // @[IdIndexer.scala:63:9, :96:30] assign auto_in_r_bits_data = auto_out_r_bits_data; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_in_r_bits_last = auto_out_r_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_aw_valid = auto_in_aw_valid; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_id = auto_in_aw_bits_id[3:0]; // @[IdIndexer.scala:63:9, :72:43] assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_aw_bits_echo_extra_id = auto_in_aw_bits_id[6:4]; // @[IdIndexer.scala:63:9, :88:56] assign auto_out_w_valid = auto_in_w_valid; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_data = auto_in_w_bits_data; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[IdIndexer.scala:63:9] assign auto_out_w_bits_last = auto_in_w_bits_last; // @[IdIndexer.scala:63:9] assign auto_out_b_ready = auto_in_b_ready; // @[IdIndexer.scala:63:9] assign auto_out_ar_valid = auto_in_ar_valid; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_id = auto_in_ar_bits_id[3:0]; // @[IdIndexer.scala:63:9, :69:43] assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:63:9] assign auto_out_ar_bits_echo_extra_id = auto_in_ar_bits_id[6:4]; // @[IdIndexer.scala:63:9, :87:56] assign auto_out_r_ready = auto_in_r_ready; // @[IdIndexer.scala:63:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_97 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_114 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_97( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_114 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IceNicController : input clock : Clock input reset : Reset output auto : { flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_xing_out : { sync : UInt<1>[2]}} output io : { send : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip comp : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}}, recv : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip comp : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}}, flip macAddr : UInt<48>, txcsumReq : { flip ready : UInt<1>, valid : UInt<1>, bits : { check : UInt<1>, offset : UInt<16>, start : UInt<16>, init : UInt<16>}}, flip rxcsumRes : { flip ready : UInt<1>, valid : UInt<1>, bits : { correct : UInt<1>, checked : UInt<1>}}, csumEnable : UInt<1>} inst intsource of IntSyncCrossingSource_n1x2_1 connect intsource.clock, clock connect intsource.reset, reset inst buffer of TLBuffer_a29d64s12k1z2u_1 connect buffer.clock, clock connect buffer.reset, reset wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_60 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire intnodeOut : UInt<1>[2] invalidate intnodeOut[0] invalidate intnodeOut[1] wire intXingOut : { sync : UInt<1>[2]} invalidate intXingOut.sync[0] invalidate intXingOut.sync[1] wire intXingIn : { sync : UInt<1>[2]} invalidate intXingIn.sync[0] invalidate intXingIn.sync[1] connect intXingOut, intXingIn wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn connect intsource.auto.in[0], intnodeOut[0] connect intsource.auto.in[1], intnodeOut[1] connect intXingIn, intsource.auto.out connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect auto.int_xing_out, intXingOut connect controlXingIn, auto.control_xing_in wire sendCompDown : UInt<1> connect sendCompDown, UInt<1>(0h0) inst sendReqQueue of HellaQueue connect sendReqQueue.clock, clock connect sendReqQueue.reset, reset node _sendReqCount_T = and(sendReqQueue.io.enq.ready, sendReqQueue.io.enq.valid) node _sendReqCount_T_1 = and(sendReqQueue.io.deq.ready, sendReqQueue.io.deq.valid) regreset sendReqCount : UInt<7>, clock, reset, UInt<7>(0h0) node _sendReqCount_T_2 = eq(_sendReqCount_T_1, UInt<1>(0h0)) node _sendReqCount_T_3 = and(_sendReqCount_T, _sendReqCount_T_2) when _sendReqCount_T_3 : node _sendReqCount_cnt_T = add(sendReqCount, UInt<1>(0h1)) node _sendReqCount_cnt_T_1 = tail(_sendReqCount_cnt_T, 1) connect sendReqCount, _sendReqCount_cnt_T_1 node _sendReqCount_T_4 = eq(_sendReqCount_T, UInt<1>(0h0)) node _sendReqCount_T_5 = and(_sendReqCount_T_1, _sendReqCount_T_4) when _sendReqCount_T_5 : node _sendReqCount_cnt_T_2 = sub(sendReqCount, UInt<1>(0h1)) node _sendReqCount_cnt_T_3 = tail(_sendReqCount_cnt_T_2, 1) connect sendReqCount, _sendReqCount_cnt_T_3 inst recvReqQueue of HellaQueue_1 connect recvReqQueue.clock, clock connect recvReqQueue.reset, reset node _recvReqCount_T = and(recvReqQueue.io.enq.ready, recvReqQueue.io.enq.valid) node _recvReqCount_T_1 = and(recvReqQueue.io.deq.ready, recvReqQueue.io.deq.valid) regreset recvReqCount : UInt<7>, clock, reset, UInt<7>(0h0) node _recvReqCount_T_2 = eq(_recvReqCount_T_1, UInt<1>(0h0)) node _recvReqCount_T_3 = and(_recvReqCount_T, _recvReqCount_T_2) when _recvReqCount_T_3 : node _recvReqCount_cnt_T = add(recvReqCount, UInt<1>(0h1)) node _recvReqCount_cnt_T_1 = tail(_recvReqCount_cnt_T, 1) connect recvReqCount, _recvReqCount_cnt_T_1 node _recvReqCount_T_4 = eq(_recvReqCount_T, UInt<1>(0h0)) node _recvReqCount_T_5 = and(_recvReqCount_T_1, _recvReqCount_T_4) when _recvReqCount_T_5 : node _recvReqCount_cnt_T_2 = sub(recvReqCount, UInt<1>(0h1)) node _recvReqCount_cnt_T_3 = tail(_recvReqCount_cnt_T_2, 1) connect recvReqCount, _recvReqCount_cnt_T_3 node _sendCompCount_T = and(io.send.comp.ready, io.send.comp.valid) regreset sendCompCount : UInt<7>, clock, reset, UInt<7>(0h0) node _sendCompCount_T_1 = eq(sendCompDown, UInt<1>(0h0)) node _sendCompCount_T_2 = and(_sendCompCount_T, _sendCompCount_T_1) when _sendCompCount_T_2 : node _sendCompCount_cnt_T = add(sendCompCount, UInt<1>(0h1)) node _sendCompCount_cnt_T_1 = tail(_sendCompCount_cnt_T, 1) connect sendCompCount, _sendCompCount_cnt_T_1 node _sendCompCount_T_3 = eq(_sendCompCount_T, UInt<1>(0h0)) node _sendCompCount_T_4 = and(sendCompDown, _sendCompCount_T_3) when _sendCompCount_T_4 : node _sendCompCount_cnt_T_2 = sub(sendCompCount, UInt<1>(0h1)) node _sendCompCount_cnt_T_3 = tail(_sendCompCount_cnt_T_2, 1) connect sendCompCount, _sendCompCount_cnt_T_3 inst recvCompQueue of HellaQueue_2 connect recvCompQueue.clock, clock connect recvCompQueue.reset, reset node _recvCompCount_T = and(recvCompQueue.io.enq.ready, recvCompQueue.io.enq.valid) node _recvCompCount_T_1 = and(recvCompQueue.io.deq.ready, recvCompQueue.io.deq.valid) regreset recvCompCount : UInt<7>, clock, reset, UInt<7>(0h0) node _recvCompCount_T_2 = eq(_recvCompCount_T_1, UInt<1>(0h0)) node _recvCompCount_T_3 = and(_recvCompCount_T, _recvCompCount_T_2) when _recvCompCount_T_3 : node _recvCompCount_cnt_T = add(recvCompCount, UInt<1>(0h1)) node _recvCompCount_cnt_T_1 = tail(_recvCompCount_cnt_T, 1) connect recvCompCount, _recvCompCount_cnt_T_1 node _recvCompCount_T_4 = eq(_recvCompCount_T, UInt<1>(0h0)) node _recvCompCount_T_5 = and(_recvCompCount_T_1, _recvCompCount_T_4) when _recvCompCount_T_5 : node _recvCompCount_cnt_T_2 = sub(recvCompCount, UInt<1>(0h1)) node _recvCompCount_cnt_T_3 = tail(_recvCompCount_cnt_T_2, 1) connect recvCompCount, _recvCompCount_cnt_T_3 node sendCompValid = gt(sendCompCount, UInt<1>(0h0)) regreset intMask : UInt<2>, clock, reset, UInt<2>(0h0) connect io.send.req.bits, sendReqQueue.io.deq.bits connect io.send.req.valid, sendReqQueue.io.deq.valid connect sendReqQueue.io.deq.ready, io.send.req.ready connect io.recv.req.bits, recvReqQueue.io.deq.bits connect io.recv.req.valid, recvReqQueue.io.deq.valid connect recvReqQueue.io.deq.ready, io.recv.req.ready node _io_send_comp_ready_T = lt(sendCompCount, UInt<7>(0h40)) connect io.send.comp.ready, _io_send_comp_ready_T connect recvCompQueue.io.enq, io.recv.comp node _intnodeOut_0_T = bits(intMask, 0, 0) node _intnodeOut_0_T_1 = and(sendCompValid, _intnodeOut_0_T) connect intnodeOut[0], _intnodeOut_0_T_1 node _intnodeOut_1_T = bits(intMask, 1, 1) node _intnodeOut_1_T_1 = and(recvCompQueue.io.deq.valid, _intnodeOut_1_T) connect intnodeOut[1], _intnodeOut_1_T_1 node _sendReqSpace_T = sub(UInt<7>(0h40), sendReqCount) node sendReqSpace = tail(_sendReqSpace_T, 1) node _recvReqSpace_T = sub(UInt<7>(0h40), recvReqCount) node recvReqSpace = tail(_recvReqSpace_T, 1) inst txcsumReqQueue of HellaQueue_3 connect txcsumReqQueue.clock, clock connect txcsumReqQueue.reset, reset inst rxcsumResQueue of HellaQueue_4 connect rxcsumResQueue.clock, clock connect rxcsumResQueue.reset, reset regreset csumEnable : UInt<1>, clock, reset, UInt<1>(0h0) connect io.txcsumReq.valid, txcsumReqQueue.io.deq.valid wire _io_txcsumReq_bits_WIRE : { check : UInt<1>, offset : UInt<16>, start : UInt<16>, init : UInt<16>} wire _io_txcsumReq_bits_WIRE_1 : UInt<49> connect _io_txcsumReq_bits_WIRE_1, txcsumReqQueue.io.deq.bits node _io_txcsumReq_bits_T = bits(_io_txcsumReq_bits_WIRE_1, 15, 0) connect _io_txcsumReq_bits_WIRE.init, _io_txcsumReq_bits_T node _io_txcsumReq_bits_T_1 = bits(_io_txcsumReq_bits_WIRE_1, 31, 16) connect _io_txcsumReq_bits_WIRE.start, _io_txcsumReq_bits_T_1 node _io_txcsumReq_bits_T_2 = bits(_io_txcsumReq_bits_WIRE_1, 47, 32) connect _io_txcsumReq_bits_WIRE.offset, _io_txcsumReq_bits_T_2 node _io_txcsumReq_bits_T_3 = bits(_io_txcsumReq_bits_WIRE_1, 48, 48) connect _io_txcsumReq_bits_WIRE.check, _io_txcsumReq_bits_T_3 connect io.txcsumReq.bits, _io_txcsumReq_bits_WIRE connect txcsumReqQueue.io.deq.ready, io.txcsumReq.ready connect rxcsumResQueue.io.enq.valid, io.rxcsumRes.valid node _rxcsumResQueue_io_enq_bits_T = cat(io.rxcsumRes.bits.correct, io.rxcsumRes.bits.checked) connect rxcsumResQueue.io.enq.bits, _rxcsumResQueue_io_enq_bits_T connect io.rxcsumRes.ready, rxcsumResQueue.io.enq.ready connect io.csumEnable, csumEnable wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h7)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) node _out_T_8 = eq(out_findex, UInt<9>(0h0)) node _out_T_9 = eq(out_bindex, UInt<9>(0h0)) node _out_T_10 = eq(out_findex, UInt<9>(0h0)) node _out_T_11 = eq(out_bindex, UInt<9>(0h0)) node _out_T_12 = eq(out_findex, UInt<9>(0h0)) node _out_T_13 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[13] wire out_wivalid : UInt<1>[13] wire out_roready : UInt<1>[13] wire out_woready : UInt<1>[13] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 63, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 63, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 63, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 63, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_14 = bits(out_front.bits.data, 63, 0) connect sendReqQueue.io.enq.valid, out_f_woready connect sendReqQueue.io.enq.bits, _out_T_14 node _out_T_15 = eq(out_rimask, UInt<1>(0h0)) node _out_T_16 = eq(out_wimask, UInt<1>(0h0)) node _out_T_17 = eq(out_romask, UInt<1>(0h0)) node _out_T_18 = eq(out_womask, UInt<1>(0h0)) node _out_T_19 = or(sendReqQueue.io.enq.ready, _out_T_18) node _out_T_20 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_21 = bits(_out_T_20, 63, 0) node _out_rimask_T_1 = bits(out_frontMask, 48, 0) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 48, 0) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 48, 0) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 48, 0) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_22 = bits(out_front.bits.data, 48, 0) connect txcsumReqQueue.io.enq.valid, out_f_woready_1 connect txcsumReqQueue.io.enq.bits, _out_T_22 node _out_T_23 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_24 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_25 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_26 = eq(out_womask_1, UInt<1>(0h0)) node _out_T_27 = or(txcsumReqQueue.io.enq.ready, _out_T_26) node _out_T_28 = or(UInt<1>(0h0), UInt<49>(0h0)) node _out_T_29 = bits(_out_T_28, 48, 0) node _out_rimask_T_2 = bits(out_frontMask, 63, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 63, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 63, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 63, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_30 = bits(out_front.bits.data, 63, 0) connect recvReqQueue.io.enq.valid, out_f_woready_2 connect recvReqQueue.io.enq.bits, _out_T_30 node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_35 = or(recvReqQueue.io.enq.ready, _out_T_34) node _out_T_36 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_37 = bits(_out_T_36, 63, 0) node _out_rimask_T_3 = bits(out_frontMask, 1, 0) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 1, 0) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 1, 0) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 1, 0) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxcsumResQueue.io.deq.ready, out_f_roready_3 node _out_T_38 = bits(out_front.bits.data, 1, 0) node _out_T_39 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_42 = or(rxcsumResQueue.io.deq.valid, _out_T_41) node _out_T_43 = eq(out_womask_3, UInt<1>(0h0)) node _out_T_44 = or(rxcsumResQueue.io.deq.bits, UInt<2>(0h0)) node _out_T_45 = bits(_out_T_44, 1, 0) node _out_rimask_T_4 = bits(out_frontMask, 8, 8) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 8, 8) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 8, 8) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 8, 8) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_46 = bits(out_front.bits.data, 8, 8) when out_f_woready_4 : connect csumEnable, _out_T_46 node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_45, UInt<8>(0h0)) node out_prepend = cat(csumEnable, _out_prepend_T) node _out_T_51 = or(out_prepend, UInt<9>(0h0)) node _out_T_52 = bits(_out_T_51, 8, 0) node _out_rimask_T_5 = bits(out_frontMask, 0, 0) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 0, 0) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 0, 0) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 0, 0) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_sendCompDown_T = and(sendCompValid, out_f_roready_5) connect sendCompDown, _out_sendCompDown_T node _out_T_53 = bits(out_front.bits.data, 0, 0) node _out_T_54 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_55 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_56 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_57 = or(sendCompValid, _out_T_56) node _out_T_58 = eq(out_womask_5, UInt<1>(0h0)) node _out_T_59 = or(UInt<1>(0h1), UInt<1>(0h0)) node _out_T_60 = bits(_out_T_59, 0, 0) node _out_rimask_T_6 = bits(out_frontMask, 31, 16) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 31, 16) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 31, 16) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 31, 16) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) connect recvCompQueue.io.deq.ready, out_f_roready_6 node _out_T_61 = bits(out_front.bits.data, 31, 16) node _out_T_62 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_63 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_64 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_65 = or(recvCompQueue.io.deq.valid, _out_T_64) node _out_T_66 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_60, UInt<16>(0h0)) node out_prepend_1 = cat(recvCompQueue.io.deq.bits, _out_prepend_T_1) node _out_T_67 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_68 = bits(_out_T_67, 31, 0) node _out_rimask_T_7 = bits(out_frontMask, 39, 32) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 39, 32) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 39, 32) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 39, 32) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_69 = bits(out_front.bits.data, 39, 32) node _out_T_70 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_71 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_72 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_73 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_68, UInt<32>(0h0)) node out_prepend_2 = cat(sendReqSpace, _out_prepend_T_2) node _out_T_74 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_75 = bits(_out_T_74, 39, 0) node _out_rimask_T_8 = bits(out_frontMask, 47, 40) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 47, 40) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 47, 40) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 47, 40) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_76 = bits(out_front.bits.data, 47, 40) node _out_T_77 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_78 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_79 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_80 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_75, UInt<40>(0h0)) node out_prepend_3 = cat(recvReqSpace, _out_prepend_T_3) node _out_T_81 = or(out_prepend_3, UInt<48>(0h0)) node _out_T_82 = bits(_out_T_81, 47, 0) node _out_rimask_T_9 = bits(out_frontMask, 55, 48) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 55, 48) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 55, 48) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 55, 48) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_83 = bits(out_front.bits.data, 55, 48) node _out_T_84 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_85 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_86 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_87 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_82, UInt<48>(0h0)) node out_prepend_4 = cat(sendCompCount, _out_prepend_T_4) node _out_T_88 = or(out_prepend_4, UInt<56>(0h0)) node _out_T_89 = bits(_out_T_88, 55, 0) node _out_rimask_T_10 = bits(out_frontMask, 63, 56) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 63, 56) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 63, 56) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 63, 56) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_90 = bits(out_front.bits.data, 63, 56) node _out_T_91 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_92 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_93 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_94 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_89, UInt<56>(0h0)) node out_prepend_5 = cat(recvCompCount, _out_prepend_T_5) node _out_T_95 = or(out_prepend_5, UInt<64>(0h0)) node _out_T_96 = bits(_out_T_95, 63, 0) node _out_rimask_T_11 = bits(out_frontMask, 47, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 47, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 47, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 47, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_97 = bits(out_front.bits.data, 47, 0) node _out_T_98 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_99 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_100 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_101 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_102 = or(io.macAddr, UInt<48>(0h0)) node _out_T_103 = bits(_out_T_102, 47, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 0) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 0) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 0) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 0) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_104 = bits(out_front.bits.data, 1, 0) when out_f_woready_12 : connect intMask, _out_T_104 node _out_T_105 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_106 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_107 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_108 = eq(out_womask_12, UInt<1>(0h0)) node _out_T_109 = or(intMask, UInt<2>(0h0)) node _out_T_110 = bits(_out_T_109, 1, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex_hi = cat(_out_iindex_T_2, _out_iindex_T_1) node out_iindex = cat(out_iindex_hi, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex_hi = cat(_out_oindex_T_2, _out_oindex_T_1) node out_oindex = cat(out_oindex_hi, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node out_backSel_4 = bits(_out_backSel_T, 4, 4) node out_backSel_5 = bits(_out_backSel_T, 5, 5) node out_backSel_6 = bits(_out_backSel_T, 6, 6) node out_backSel_7 = bits(_out_backSel_T, 7, 7) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[2], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_8) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_11 connect out_rivalid[9], _out_rifireMux_T_11 connect out_rivalid[8], _out_rifireMux_T_11 connect out_rivalid[7], _out_rifireMux_T_11 connect out_rivalid[6], _out_rifireMux_T_11 connect out_rivalid[5], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_8, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_10) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[11], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_10, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) wire out_rifireMux_out_4 : UInt<1> node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_12) connect out_rifireMux_out_4, UInt<1>(0h1) connect out_rivalid[12], _out_rifireMux_T_19 node _out_rifireMux_T_20 = eq(_out_T_12, UInt<1>(0h0)) node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) wire out_rifireMux_out_5 : UInt<1> node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, _out_T_2) connect out_rifireMux_out_5, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_23 node _out_rifireMux_T_24 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) wire out_rifireMux_out_6 : UInt<1> node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, _out_T_6) connect out_rifireMux_out_6, UInt<1>(0h1) connect out_rivalid[4], _out_rifireMux_T_27 connect out_rivalid[3], _out_rifireMux_T_27 node _out_rifireMux_T_28 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) wire out_rifireMux_out_7 : UInt<1> node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1)) connect out_rifireMux_out_7, UInt<1>(0h1) node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) node _out_rifireMux_T_34 = geq(out_iindex, UInt<4>(0h8)) wire _out_rifireMux_WIRE : UInt<1>[8] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 node out_rifireMux = mux(_out_rifireMux_T_34, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[2], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_8) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_12 connect out_wivalid[9], _out_wifireMux_T_12 connect out_wivalid[8], _out_wifireMux_T_12 connect out_wivalid[7], _out_wifireMux_T_12 connect out_wivalid[6], _out_wifireMux_T_12 connect out_wivalid[5], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_8, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_10) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[11], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_10, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) wire out_wifireMux_out_4 : UInt<1> node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_12) connect out_wifireMux_out_4, UInt<1>(0h1) connect out_wivalid[12], _out_wifireMux_T_20 node _out_wifireMux_T_21 = eq(_out_T_12, UInt<1>(0h0)) node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) wire out_wifireMux_out_5 : UInt<1> node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, _out_T_2) connect out_wifireMux_out_5, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_24 node _out_wifireMux_T_25 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) wire out_wifireMux_out_6 : UInt<1> node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, _out_T_6) connect out_wifireMux_out_6, UInt<1>(0h1) connect out_wivalid[4], _out_wifireMux_T_28 connect out_wivalid[3], _out_wifireMux_T_28 node _out_wifireMux_T_29 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) wire out_wifireMux_out_7 : UInt<1> node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1)) connect out_wifireMux_out_7, UInt<1>(0h1) node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) node _out_wifireMux_T_35 = geq(out_iindex, UInt<4>(0h8)) wire _out_wifireMux_WIRE : UInt<1>[8] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 node out_wifireMux = mux(_out_wifireMux_T_35, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[2], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_9) node out_rofireMux_out_0 = and(_out_T_65, _out_T_57) node out_rofireMux_out_1_1 = and(_out_rofireMux_T_11, _out_T_57) node out_rofireMux_out_2_1 = and(_out_rofireMux_T_11, _out_T_65) node _out_rofireMux_T_12 = and(_out_rofireMux_T_11, _out_T_65) node out_rofireMux_all = and(_out_rofireMux_T_12, _out_T_57) connect out_rofireMux_out_2, out_rofireMux_out_0 connect out_roready[10], out_rofireMux_all connect out_roready[9], out_rofireMux_all connect out_roready[8], out_rofireMux_all connect out_roready[7], out_rofireMux_all connect out_roready[6], out_rofireMux_out_1_1 connect out_roready[5], out_rofireMux_out_2_1 node _out_rofireMux_T_13 = eq(_out_T_9, UInt<1>(0h0)) node _out_rofireMux_T_14 = or(out_rofireMux_out_2, _out_rofireMux_T_13) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_15 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_16 = and(_out_rofireMux_T_15, _out_T_11) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[11], _out_rofireMux_T_16 node _out_rofireMux_T_17 = eq(_out_T_11, UInt<1>(0h0)) node _out_rofireMux_T_18 = or(out_rofireMux_out_3, _out_rofireMux_T_17) wire out_rofireMux_out_4 : UInt<1> node _out_rofireMux_T_19 = and(_out_rofireMux_T_1, out_backSel_4) node _out_rofireMux_T_20 = and(_out_rofireMux_T_19, _out_T_13) connect out_rofireMux_out_4, UInt<1>(0h1) connect out_roready[12], _out_rofireMux_T_20 node _out_rofireMux_T_21 = eq(_out_T_13, UInt<1>(0h0)) node _out_rofireMux_T_22 = or(out_rofireMux_out_4, _out_rofireMux_T_21) wire out_rofireMux_out_5 : UInt<1> node _out_rofireMux_T_23 = and(_out_rofireMux_T_1, out_backSel_5) node _out_rofireMux_T_24 = and(_out_rofireMux_T_23, _out_T_3) connect out_rofireMux_out_5, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_24 node _out_rofireMux_T_25 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_26 = or(out_rofireMux_out_5, _out_rofireMux_T_25) wire out_rofireMux_out_6 : UInt<1> node _out_rofireMux_T_27 = and(_out_rofireMux_T_1, out_backSel_6) node _out_rofireMux_T_28 = and(_out_rofireMux_T_27, _out_T_7) node out_rofireMux_all_1 = and(_out_rofireMux_T_28, _out_T_42) connect out_rofireMux_out_6, _out_T_42 connect out_roready[4], out_rofireMux_all_1 connect out_roready[3], _out_rofireMux_T_28 node _out_rofireMux_T_29 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_30 = or(out_rofireMux_out_6, _out_rofireMux_T_29) wire out_rofireMux_out_7 : UInt<1> node _out_rofireMux_T_31 = and(_out_rofireMux_T_1, out_backSel_7) node _out_rofireMux_T_32 = and(_out_rofireMux_T_31, UInt<1>(0h1)) connect out_rofireMux_out_7, UInt<1>(0h1) node _out_rofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_34 = or(out_rofireMux_out_7, _out_rofireMux_T_33) node _out_rofireMux_T_35 = geq(out_oindex, UInt<4>(0h8)) wire _out_rofireMux_WIRE : UInt<1>[8] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_14 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_18 connect _out_rofireMux_WIRE[4], _out_rofireMux_T_22 connect _out_rofireMux_WIRE[5], _out_rofireMux_T_26 connect _out_rofireMux_WIRE[6], _out_rofireMux_T_30 connect _out_rofireMux_WIRE[7], _out_rofireMux_T_34 node out_rofireMux = mux(_out_rofireMux_T_35, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) node out_wofireMux_all = and(_out_wofireMux_T_4, _out_T_19) connect out_wofireMux_out, _out_T_19 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) node out_wofireMux_all_1 = and(_out_wofireMux_T_8, _out_T_35) connect out_wofireMux_out_1, _out_T_35 connect out_woready[2], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_9) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_12 connect out_woready[9], _out_wofireMux_T_12 connect out_woready[8], _out_wofireMux_T_12 connect out_woready[7], _out_wofireMux_T_12 connect out_woready[6], _out_wofireMux_T_12 connect out_woready[5], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_9, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_11) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[11], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_11, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) wire out_wofireMux_out_4 : UInt<1> node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_13) connect out_wofireMux_out_4, UInt<1>(0h1) connect out_woready[12], _out_wofireMux_T_20 node _out_wofireMux_T_21 = eq(_out_T_13, UInt<1>(0h0)) node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) wire out_wofireMux_out_5 : UInt<1> node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, _out_T_3) node out_wofireMux_all_2 = and(_out_wofireMux_T_24, _out_T_27) connect out_wofireMux_out_5, _out_T_27 connect out_woready[1], _out_wofireMux_T_24 node _out_wofireMux_T_25 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) wire out_wofireMux_out_6 : UInt<1> node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, _out_T_7) connect out_wofireMux_out_6, UInt<1>(0h1) connect out_woready[4], _out_wofireMux_T_28 connect out_woready[3], _out_wofireMux_T_28 node _out_wofireMux_T_29 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) wire out_wofireMux_out_7 : UInt<1> node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1)) connect out_wofireMux_out_7, UInt<1>(0h1) node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) node _out_wofireMux_T_35 = geq(out_oindex, UInt<4>(0h8)) wire _out_wofireMux_WIRE : UInt<1>[8] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 node out_wofireMux = mux(_out_wofireMux_T_35, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<4>(0h8)) wire _out_out_bits_data_WIRE : UInt<1>[8] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_5 connect _out_out_bits_data_WIRE[2], _out_T_9 connect _out_out_bits_data_WIRE[3], _out_T_11 connect _out_out_bits_data_WIRE[4], _out_T_13 connect _out_out_bits_data_WIRE[5], _out_T_3 connect _out_out_bits_data_WIRE[6], _out_T_7 connect _out_out_bits_data_WIRE[7], UInt<1>(0h1) node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<4>(0h8)) wire _out_out_bits_data_WIRE_1 : UInt<64>[8] connect _out_out_bits_data_WIRE_1[0], _out_T_21 connect _out_out_bits_data_WIRE_1[1], _out_T_37 connect _out_out_bits_data_WIRE_1[2], _out_T_96 connect _out_out_bits_data_WIRE_1[3], _out_T_103 connect _out_out_bits_data_WIRE_1[4], _out_T_110 connect _out_out_bits_data_WIRE_1[5], _out_T_29 connect _out_out_bits_data_WIRE_1[6], _out_T_52 connect _out_out_bits_data_WIRE_1[7], UInt<1>(0h0) node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)

module IceNicController( // @[NIC.scala:112:7] input clock, // @[NIC.scala:112:7] input reset, // @[NIC.scala:112:7] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_xing_out_sync_1, // @[LazyModuleImp.scala:107:25] input io_send_req_ready, // @[NIC.scala:113:14] output io_send_req_valid, // @[NIC.scala:113:14] output [63:0] io_send_req_bits, // @[NIC.scala:113:14] output io_send_comp_ready, // @[NIC.scala:113:14] input io_send_comp_valid, // @[NIC.scala:113:14] input io_recv_req_ready, // @[NIC.scala:113:14] output io_recv_req_valid, // @[NIC.scala:113:14] output [63:0] io_recv_req_bits, // @[NIC.scala:113:14] output io_recv_comp_ready, // @[NIC.scala:113:14] input io_recv_comp_valid, // @[NIC.scala:113:14] input [15:0] io_recv_comp_bits, // @[NIC.scala:113:14] input [47:0] io_macAddr, // @[NIC.scala:113:14] input io_txcsumReq_ready, // @[NIC.scala:113:14] output io_txcsumReq_valid, // @[NIC.scala:113:14] output io_txcsumReq_bits_check, // @[NIC.scala:113:14] output [15:0] io_txcsumReq_bits_offset, // @[NIC.scala:113:14] output [15:0] io_txcsumReq_bits_start, // @[NIC.scala:113:14] output [15:0] io_txcsumReq_bits_init, // @[NIC.scala:113:14] output io_rxcsumRes_ready, // @[NIC.scala:113:14] input io_rxcsumRes_valid, // @[NIC.scala:113:14] input io_rxcsumRes_bits_correct, // @[NIC.scala:113:14] input io_rxcsumRes_bits_checked, // @[NIC.scala:113:14] output io_csumEnable // @[NIC.scala:113:14] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxcsumResQueue_io_deq_valid; // @[NIC.scala:155:30] wire _txcsumReqQueue_io_enq_ready; // @[NIC.scala:154:30] wire _recvCompQueue_io_enq_ready; // @[NIC.scala:132:29] wire _recvCompQueue_io_deq_valid; // @[NIC.scala:132:29] wire [15:0] _recvCompQueue_io_deq_bits; // @[NIC.scala:132:29] wire _recvReqQueue_io_enq_ready; // @[NIC.scala:127:28] wire _recvReqQueue_io_deq_valid; // @[NIC.scala:127:28] wire _sendReqQueue_io_enq_ready; // @[NIC.scala:124:28] wire _sendReqQueue_io_deq_valid; // @[NIC.scala:124:28] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[NIC.scala:112:7] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[NIC.scala:112:7] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[NIC.scala:112:7] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[NIC.scala:112:7] wire [11:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[NIC.scala:112:7] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[NIC.scala:112:7] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[NIC.scala:112:7] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[NIC.scala:112:7] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[NIC.scala:112:7] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[NIC.scala:112:7] wire io_send_req_ready_0 = io_send_req_ready; // @[NIC.scala:112:7] wire io_send_comp_valid_0 = io_send_comp_valid; // @[NIC.scala:112:7] wire io_recv_req_ready_0 = io_recv_req_ready; // @[NIC.scala:112:7] wire io_recv_comp_valid_0 = io_recv_comp_valid; // @[NIC.scala:112:7] wire [15:0] io_recv_comp_bits_0 = io_recv_comp_bits; // @[NIC.scala:112:7] wire [47:0] io_macAddr_0 = io_macAddr; // @[NIC.scala:112:7] wire io_txcsumReq_ready_0 = io_txcsumReq_ready; // @[NIC.scala:112:7] wire io_rxcsumRes_valid_0 = io_rxcsumRes_valid; // @[NIC.scala:112:7] wire io_rxcsumRes_bits_correct_0 = io_rxcsumRes_bits_correct; // @[NIC.scala:112:7] wire io_rxcsumRes_bits_checked_0 = io_rxcsumRes_bits_checked; // @[NIC.scala:112:7] wire [8:0] out_maskMatch = 9'h1F8; // @[RegisterRouter.scala:87:24] wire [48:0] _out_T_28 = 49'h0; // @[RegisterRouter.scala:87:24] wire [48:0] _out_T_29 = 49'h0; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h1; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_20 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_21 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_36 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_37 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_5 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_7 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[NIC.scala:112:7] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[NIC.scala:112:7] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[NIC.scala:112:7] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[NIC.scala:112:7] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire io_send_comp_bits = 1'h1; // @[NIC.scala:112:7] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire _out_T_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_T_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[NIC.scala:112:7] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[NIC.scala:112:7] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[NIC.scala:112:7] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[NIC.scala:112:7] wire [11:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[NIC.scala:112:7] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[NIC.scala:112:7] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[NIC.scala:112:7] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[NIC.scala:112:7] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[NIC.scala:112:7] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[NIC.scala:112:7] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire intXingOut_sync_1; // @[MixedNode.scala:542:17] wire _io_send_comp_ready_T; // @[NIC.scala:140:39] wire [47:0] _out_T_102 = io_macAddr_0; // @[RegisterRouter.scala:87:24] wire _io_txcsumReq_bits_WIRE_check; // @[NIC.scala:159:59] wire [15:0] _io_txcsumReq_bits_WIRE_offset; // @[NIC.scala:159:59] wire [15:0] _io_txcsumReq_bits_WIRE_start; // @[NIC.scala:159:59] wire [15:0] _io_txcsumReq_bits_WIRE_init; // @[NIC.scala:159:59] wire auto_control_xing_in_a_ready_0; // @[NIC.scala:112:7] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[NIC.scala:112:7] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[NIC.scala:112:7] wire [11:0] auto_control_xing_in_d_bits_source_0; // @[NIC.scala:112:7] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[NIC.scala:112:7] wire auto_control_xing_in_d_valid_0; // @[NIC.scala:112:7] wire auto_int_xing_out_sync_0_0; // @[NIC.scala:112:7] wire auto_int_xing_out_sync_1_0; // @[NIC.scala:112:7] wire io_send_req_valid_0; // @[NIC.scala:112:7] wire [63:0] io_send_req_bits_0; // @[NIC.scala:112:7] wire io_send_comp_ready_0; // @[NIC.scala:112:7] wire io_recv_req_valid_0; // @[NIC.scala:112:7] wire [63:0] io_recv_req_bits_0; // @[NIC.scala:112:7] wire io_recv_comp_ready_0; // @[NIC.scala:112:7] wire io_txcsumReq_bits_check_0; // @[NIC.scala:112:7] wire [15:0] io_txcsumReq_bits_offset_0; // @[NIC.scala:112:7] wire [15:0] io_txcsumReq_bits_start_0; // @[NIC.scala:112:7] wire [15:0] io_txcsumReq_bits_init_0; // @[NIC.scala:112:7] wire io_txcsumReq_valid_0; // @[NIC.scala:112:7] wire io_rxcsumRes_ready_0; // @[NIC.scala:112:7] wire io_csumEnable_0; // @[NIC.scala:112:7] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [11:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [11:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] wire _intnodeOut_0_T_1; // @[NIC.scala:143:40] wire _intnodeOut_1_T_1; // @[NIC.scala:144:53] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[NIC.scala:112:7] wire intXingIn_sync_1; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_1_0 = intXingOut_sync_1; // @[NIC.scala:112:7] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intXingOut_sync_1 = intXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[NIC.scala:112:7] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[NIC.scala:112:7] wire _out_sendCompDown_T; // @[NIC.scala:150:35] wire sendCompDown; // @[NIC.scala:115:30] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire _sendReqCount_T = _sendReqQueue_io_enq_ready & out_f_woready; // @[Decoupled.scala:51:35] wire _sendReqCount_T_1 = io_send_req_ready_0 & _sendReqQueue_io_deq_valid; // @[Decoupled.scala:51:35] reg [6:0] sendReqCount; // @[Counters.scala:34:22] wire _sendReqCount_T_2 = ~_sendReqCount_T_1; // @[Decoupled.scala:51:35] wire _sendReqCount_T_3 = _sendReqCount_T & _sendReqCount_T_2; // @[Decoupled.scala:51:35] wire [7:0] _GEN = {1'h0, sendReqCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _sendReqCount_cnt_T = _GEN + 8'h1; // @[Counters.scala:35:37] wire [6:0] _sendReqCount_cnt_T_1 = _sendReqCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _sendReqCount_T_4 = ~_sendReqCount_T; // @[Decoupled.scala:51:35] wire _sendReqCount_T_5 = _sendReqCount_T_1 & _sendReqCount_T_4; // @[Decoupled.scala:51:35] wire [7:0] _sendReqCount_cnt_T_2 = _GEN - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _sendReqCount_cnt_T_3 = _sendReqCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _recvReqCount_T = _recvReqQueue_io_enq_ready & out_f_woready_2; // @[Decoupled.scala:51:35] wire _recvReqCount_T_1 = io_recv_req_ready_0 & _recvReqQueue_io_deq_valid; // @[Decoupled.scala:51:35] reg [6:0] recvReqCount; // @[Counters.scala:34:22] wire _recvReqCount_T_2 = ~_recvReqCount_T_1; // @[Decoupled.scala:51:35] wire _recvReqCount_T_3 = _recvReqCount_T & _recvReqCount_T_2; // @[Decoupled.scala:51:35] wire [7:0] _GEN_0 = {1'h0, recvReqCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _recvReqCount_cnt_T = _GEN_0 + 8'h1; // @[Counters.scala:35:37] wire [6:0] _recvReqCount_cnt_T_1 = _recvReqCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _recvReqCount_T_4 = ~_recvReqCount_T; // @[Decoupled.scala:51:35] wire _recvReqCount_T_5 = _recvReqCount_T_1 & _recvReqCount_T_4; // @[Decoupled.scala:51:35] wire [7:0] _recvReqCount_cnt_T_2 = _GEN_0 - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _recvReqCount_cnt_T_3 = _recvReqCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire _sendCompCount_T = io_send_comp_ready_0 & io_send_comp_valid_0; // @[Decoupled.scala:51:35] reg [6:0] sendCompCount; // @[Counters.scala:34:22] wire _sendCompCount_T_1 = ~sendCompDown; // @[Counters.scala:35:17] wire _sendCompCount_T_2 = _sendCompCount_T & _sendCompCount_T_1; // @[Decoupled.scala:51:35] wire [7:0] _GEN_1 = {1'h0, sendCompCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _sendCompCount_cnt_T = _GEN_1 + 8'h1; // @[Counters.scala:35:37] wire [6:0] _sendCompCount_cnt_T_1 = _sendCompCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _sendCompCount_T_3 = ~_sendCompCount_T; // @[Decoupled.scala:51:35] wire _sendCompCount_T_4 = sendCompDown & _sendCompCount_T_3; // @[Counters.scala:36:{16,19}] wire [7:0] _sendCompCount_cnt_T_2 = _GEN_1 - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _sendCompCount_cnt_T_3 = _sendCompCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire _recvCompCount_T = _recvCompQueue_io_enq_ready & io_recv_comp_valid_0; // @[Decoupled.scala:51:35] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _recvCompCount_T_1 = out_f_roready_6 & _recvCompQueue_io_deq_valid; // @[Decoupled.scala:51:35] reg [6:0] recvCompCount; // @[Counters.scala:34:22] wire _recvCompCount_T_2 = ~_recvCompCount_T_1; // @[Decoupled.scala:51:35] wire _recvCompCount_T_3 = _recvCompCount_T & _recvCompCount_T_2; // @[Decoupled.scala:51:35] wire [7:0] _GEN_2 = {1'h0, recvCompCount}; // @[Counters.scala:34:22, :35:37] wire [7:0] _recvCompCount_cnt_T = _GEN_2 + 8'h1; // @[Counters.scala:35:37] wire [6:0] _recvCompCount_cnt_T_1 = _recvCompCount_cnt_T[6:0]; // @[Counters.scala:35:37] wire _recvCompCount_T_4 = ~_recvCompCount_T; // @[Decoupled.scala:51:35] wire _recvCompCount_T_5 = _recvCompCount_T_1 & _recvCompCount_T_4; // @[Decoupled.scala:51:35] wire [7:0] _recvCompCount_cnt_T_2 = _GEN_2 - 8'h1; // @[Counters.scala:35:37, :36:37] wire [6:0] _recvCompCount_cnt_T_3 = _recvCompCount_cnt_T_2[6:0]; // @[Counters.scala:36:37] wire sendCompValid = |sendCompCount; // @[Counters.scala:34:22] reg [1:0] intMask; // @[NIC.scala:136:24] wire [1:0] _out_T_109 = intMask; // @[RegisterRouter.scala:87:24] assign _io_send_comp_ready_T = ~(sendCompCount[6]); // @[Counters.scala:34:22] assign io_send_comp_ready_0 = _io_send_comp_ready_T; // @[NIC.scala:112:7, :140:39] wire _intnodeOut_0_T = intMask[0]; // @[NIC.scala:136:24, :143:50] assign _intnodeOut_0_T_1 = sendCompValid & _intnodeOut_0_T; // @[NIC.scala:135:37, :143:{40,50}] assign intnodeOut_0 = _intnodeOut_0_T_1; // @[NIC.scala:143:40] wire _intnodeOut_1_T = intMask[1]; // @[NIC.scala:136:24, :144:63] assign _intnodeOut_1_T_1 = _recvCompQueue_io_deq_valid & _intnodeOut_1_T; // @[NIC.scala:132:29, :144:{53,63}] assign intnodeOut_1 = _intnodeOut_1_T_1; // @[NIC.scala:144:53] wire [7:0] _sendReqSpace_T = 8'h40 - _GEN; // @[Counters.scala:35:37] wire [6:0] sendReqSpace = _sendReqSpace_T[6:0]; // @[NIC.scala:146:32] wire [7:0] _recvReqSpace_T = 8'h40 - _GEN_0; // @[Counters.scala:35:37] wire [6:0] recvReqSpace = _recvReqSpace_T[6:0]; // @[NIC.scala:147:32] reg csumEnable; // @[NIC.scala:156:27] assign io_csumEnable_0 = csumEnable; // @[NIC.scala:112:7, :156:27] wire _io_txcsumReq_bits_T_3; // @[NIC.scala:159:59] assign io_txcsumReq_bits_check_0 = _io_txcsumReq_bits_WIRE_check; // @[NIC.scala:112:7, :159:59] wire [15:0] _io_txcsumReq_bits_T_2; // @[NIC.scala:159:59] assign io_txcsumReq_bits_offset_0 = _io_txcsumReq_bits_WIRE_offset; // @[NIC.scala:112:7, :159:59] wire [15:0] _io_txcsumReq_bits_T_1; // @[NIC.scala:159:59] assign io_txcsumReq_bits_start_0 = _io_txcsumReq_bits_WIRE_start; // @[NIC.scala:112:7, :159:59] wire [15:0] _io_txcsumReq_bits_T; // @[NIC.scala:159:59] assign io_txcsumReq_bits_init_0 = _io_txcsumReq_bits_WIRE_init; // @[NIC.scala:112:7, :159:59] wire [48:0] _io_txcsumReq_bits_WIRE_1; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T = _io_txcsumReq_bits_WIRE_1[15:0]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_init = _io_txcsumReq_bits_T; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T_1 = _io_txcsumReq_bits_WIRE_1[31:16]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_start = _io_txcsumReq_bits_T_1; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T_2 = _io_txcsumReq_bits_WIRE_1[47:32]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_offset = _io_txcsumReq_bits_T_2; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_T_3 = _io_txcsumReq_bits_WIRE_1[48]; // @[NIC.scala:159:59] assign _io_txcsumReq_bits_WIRE_check = _io_txcsumReq_bits_T_3; // @[NIC.scala:159:59] wire [1:0] _rxcsumResQueue_io_enq_bits_T = {io_rxcsumRes_bits_correct_0, io_rxcsumRes_bits_checked_0}; // @[NIC.scala:112:7, :163:51] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_14 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_30 = out_front_bits_data; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN_3 = out_front_bits_index & 9'h1F8; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN_3; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN_3; // @[RegisterRouter.scala:87:24] wire _GEN_4 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_4; // @[RegisterRouter.scala:87:24] wire _GEN_5 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_5; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_5 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_6 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_9; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_3 = _out_T_11; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_4 = _out_T_13; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28; // @[RegisterRouter.scala:87:24] wire out_rofireMux_all_1; // @[ReduceOthers.scala:47:21] wire out_rofireMux_out_2_1; // @[ReduceOthers.scala:46:45] wire out_rofireMux_out_1_1; // @[ReduceOthers.scala:46:45] wire out_rofireMux_all; // @[ReduceOthers.scala:47:21] wire _out_rofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_2 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_2 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_2 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_2 = out_backMask; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_15 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_19 = _sendReqQueue_io_enq_ready | _out_T_18; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out = _out_T_19; // @[RegisterRouter.scala:87:24] wire [48:0] _out_rimask_T_1 = out_frontMask[48:0]; // @[RegisterRouter.scala:87:24] wire [48:0] _out_wimask_T_1 = out_frontMask[48:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [48:0] _out_romask_T_1 = out_backMask[48:0]; // @[RegisterRouter.scala:87:24] wire [48:0] _out_womask_T_1 = out_backMask[48:0]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [48:0] _out_T_22 = out_front_bits_data[48:0]; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = _txcsumReqQueue_io_enq_ready | _out_T_26; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = _out_T_27; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = _recvReqQueue_io_enq_ready | _out_T_34; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_3 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_3 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_12 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_12 = out_frontMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_3 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_3 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_12 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_12 = out_backMask[1:0]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_38 = out_front_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_104 = out_front_bits_data[1:0]; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_42 = _rxcsumResQueue_io_deq_valid | _out_T_41; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = _out_T_42; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_44; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_45 = _out_T_44; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = {6'h0, _out_T_45}; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = {csumEnable, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_51 = out_prepend; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign _out_sendCompDown_T = sendCompValid & out_f_roready_5; // @[RegisterRouter.scala:87:24] assign sendCompDown = _out_sendCompDown_T; // @[NIC.scala:115:30, :150:35] wire _out_T_53 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = sendCompValid | _out_T_56; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_6 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_6 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_6 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_6 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_61 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24] wire _out_T_62 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = _recvCompQueue_io_deq_valid | _out_T_64; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {_recvCompQueue_io_deq_bits, 16'h1}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = _out_T_67; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_69 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_71 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_72 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [38:0] out_prepend_2 = {sendReqSpace, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_74 = {1'h0, out_prepend_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_75 = _out_T_74; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_75; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_76 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [46:0] out_prepend_3 = {recvReqSpace, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_81 = {1'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_82 = _out_T_81; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_4 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_83 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_85 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [54:0] out_prepend_4 = {sendCompCount, _out_prepend_T_4}; // @[Counters.scala:34:22] wire [55:0] _out_T_88 = {1'h0, out_prepend_4}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_5 = _out_T_89; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_90 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_93 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_94 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [62:0] out_prepend_5 = {recvCompCount, _out_prepend_T_5}; // @[Counters.scala:34:22] wire [63:0] _out_T_95 = {1'h0, out_prepend_5}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_96 = _out_T_95; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_96; // @[MuxLiteral.scala:49:48] wire [47:0] _out_rimask_T_11 = out_frontMask[47:0]; // @[RegisterRouter.scala:87:24] wire [47:0] _out_wimask_T_11 = out_frontMask[47:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire [47:0] _out_romask_T_11 = out_backMask[47:0]; // @[RegisterRouter.scala:87:24] wire [47:0] _out_womask_T_11 = out_backMask[47:0]; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_97 = out_front_bits_data[47:0]; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_103 = _out_T_102; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_105 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_110 = _out_T_109; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex = {out_iindex_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex = {out_oindex_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontSel_T = 8'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35] wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35] wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35] wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35] wire [7:0] _out_backSel_T = 8'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35] wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35] wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35] wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35] wire _GEN_6 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_31 = _out_rifireMux_T_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_32 = _out_wifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _GEN_7 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_0; // @[ReduceOthers.scala:46:45] wire out_rofireMux_out_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_rofireMux_out_0 = _out_T_65 & _out_T_57; // @[ReduceOthers.scala:46:45] assign out_rofireMux_out_2 = out_rofireMux_out_0; // @[ReduceOthers.scala:46:45] assign out_rofireMux_out_1_1 = _out_rofireMux_T_11 & _out_T_57; // @[ReduceOthers.scala:46:45] assign out_roready_6 = out_rofireMux_out_1_1; // @[ReduceOthers.scala:46:45] wire _GEN_8 = _out_rofireMux_T_11 & _out_T_65; // @[ReduceOthers.scala:46:45] assign out_rofireMux_out_2_1 = _GEN_8; // @[ReduceOthers.scala:46:45] wire _out_rofireMux_T_12; // @[ReduceOthers.scala:47:21] assign _out_rofireMux_T_12 = _GEN_8; // @[ReduceOthers.scala:46:45, :47:21] assign out_roready_5 = out_rofireMux_out_2_1; // @[ReduceOthers.scala:46:45] assign out_rofireMux_all = _out_rofireMux_T_12 & _out_T_57; // @[ReduceOthers.scala:47:21] assign out_roready_7 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] assign out_roready_8 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] assign out_roready_9 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] assign out_roready_10 = out_rofireMux_all; // @[ReduceOthers.scala:47:21] wire _out_rofireMux_T_13 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = out_rofireMux_out_2 | _out_rofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_2 = _out_rofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_T_15 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_16 = _out_rofireMux_T_15 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_20 = _out_rofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_24 = _out_rofireMux_T_23 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_27 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_28 = _out_rofireMux_T_27 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_rofireMux_all_1 = _out_rofireMux_T_28 & _out_T_42; // @[ReduceOthers.scala:47:21] assign out_roready_4 = out_rofireMux_all_1; // @[ReduceOthers.scala:47:21] wire _out_rofireMux_T_29 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_30 = out_rofireMux_out_6 | _out_rofireMux_T_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_6 = _out_rofireMux_T_30; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_T_31 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire [7:0] _GEN_9 = {{1'h1}, {_out_rofireMux_WIRE_6}, {1'h1}, {1'h1}, {1'h1}, {_out_rofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_rofireMux = _GEN_9[out_oindex]; // @[MuxLiteral.scala:49:10] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_4 & _out_T_19; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = out_wofireMux_out | _out_wofireMux_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = _out_wofireMux_T_6; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_8 & _out_T_35; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = out_wofireMux_out_1 | _out_wofireMux_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_1 = _out_wofireMux_T_10; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_2 = _out_wofireMux_T_24 & _out_T_27; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_25 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = out_wofireMux_out_5 | _out_wofireMux_T_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_5 = _out_wofireMux_T_26; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_32 = _out_wofireMux_T_31; // @[RegisterRouter.scala:87:24] wire [7:0] _GEN_10 = {{1'h1}, {1'h1}, {_out_wofireMux_WIRE_5}, {1'h1}, {1'h1}, {1'h1}, {_out_wofireMux_WIRE_1}, {_out_wofireMux_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_10[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_oready = out_front_bits_read ? out_rofireMux : out_wofireMux; // @[MuxLiteral.scala:49:10] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign _out_front_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [7:0] _GEN_11 = {{1'h1}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_11[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_3 = {16'h0, _out_T_103}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_4 = {62'h0, _out_T_110}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_6 = {55'h0, _out_T_52}; // @[MuxLiteral.scala:49:48] wire [7:0][63:0] _GEN_12 = {{64'h0}, {_out_out_bits_data_WIRE_1_6}, {64'h0}, {_out_out_bits_data_WIRE_1_4}, {_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {64'h0}, {64'h0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_12[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[NIC.scala:112:7] if (reset) begin // @[NIC.scala:112:7] sendReqCount <= 7'h0; // @[Counters.scala:34:22] recvReqCount <= 7'h0; // @[Counters.scala:34:22] sendCompCount <= 7'h0; // @[Counters.scala:34:22] recvCompCount <= 7'h0; // @[Counters.scala:34:22] intMask <= 2'h0; // @[NIC.scala:136:24] csumEnable <= 1'h0; // @[NIC.scala:156:27] end else begin // @[NIC.scala:112:7] if (_sendReqCount_T_5) // @[Counters.scala:36:16] sendReqCount <= _sendReqCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_sendReqCount_T_3) // @[Counters.scala:35:14] sendReqCount <= _sendReqCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (_recvReqCount_T_5) // @[Counters.scala:36:16] recvReqCount <= _recvReqCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_recvReqCount_T_3) // @[Counters.scala:35:14] recvReqCount <= _recvReqCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (_sendCompCount_T_4) // @[Counters.scala:36:16] sendCompCount <= _sendCompCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_sendCompCount_T_2) // @[Counters.scala:35:14] sendCompCount <= _sendCompCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (_recvCompCount_T_5) // @[Counters.scala:36:16] recvCompCount <= _recvCompCount_cnt_T_3; // @[Counters.scala:34:22, :36:37] else if (_recvCompCount_T_3) // @[Counters.scala:35:14] recvCompCount <= _recvCompCount_cnt_T_1; // @[Counters.scala:34:22, :35:37] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] intMask <= _out_T_104; // @[RegisterRouter.scala:87:24] if (out_f_woready_4) // @[RegisterRouter.scala:87:24] csumEnable <= _out_T_46; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x2_1 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_in_1 (intnodeOut_1), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0), .auto_out_sync_1 (intXingIn_sync_1) ); // @[Crossing.scala:29:31] TLMonitor_60 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] HellaQueue sendReqQueue ( // @[NIC.scala:124:28] .clock (clock), .reset (reset), .io_enq_ready (_sendReqQueue_io_enq_ready), .io_enq_valid (out_f_woready), // @[RegisterRouter.scala:87:24] .io_enq_bits (_out_T_14), // @[RegisterRouter.scala:87:24] .io_deq_ready (io_send_req_ready_0), // @[NIC.scala:112:7] .io_deq_valid (_sendReqQueue_io_deq_valid), .io_deq_bits (io_send_req_bits_0) ); // @[NIC.scala:124:28] assign io_send_req_valid_0 = _sendReqQueue_io_deq_valid; // @[NIC.scala:112:7, :124:28] HellaQueue_1 recvReqQueue ( // @[NIC.scala:127:28] .clock (clock), .reset (reset), .io_enq_ready (_recvReqQueue_io_enq_ready), .io_enq_valid (out_f_woready_2), // @[RegisterRouter.scala:87:24] .io_enq_bits (_out_T_30), // @[RegisterRouter.scala:87:24] .io_deq_ready (io_recv_req_ready_0), // @[NIC.scala:112:7] .io_deq_valid (_recvReqQueue_io_deq_valid), .io_deq_bits (io_recv_req_bits_0) ); // @[NIC.scala:127:28] assign io_recv_req_valid_0 = _recvReqQueue_io_deq_valid; // @[NIC.scala:112:7, :127:28] HellaQueue_2 recvCompQueue ( // @[NIC.scala:132:29] .clock (clock), .reset (reset), .io_enq_ready (_recvCompQueue_io_enq_ready), .io_enq_valid (io_recv_comp_valid_0), // @[NIC.scala:112:7] .io_enq_bits (io_recv_comp_bits_0), // @[NIC.scala:112:7] .io_deq_ready (out_f_roready_6), // @[RegisterRouter.scala:87:24] .io_deq_valid (_recvCompQueue_io_deq_valid), .io_deq_bits (_recvCompQueue_io_deq_bits) ); // @[NIC.scala:132:29] assign io_recv_comp_ready_0 = _recvCompQueue_io_enq_ready; // @[NIC.scala:112:7, :132:29] HellaQueue_3 txcsumReqQueue ( // @[NIC.scala:154:30] .clock (clock), .reset (reset), .io_enq_ready (_txcsumReqQueue_io_enq_ready), .io_enq_valid (out_f_woready_1), // @[RegisterRouter.scala:87:24] .io_enq_bits (_out_T_22), // @[RegisterRouter.scala:87:24] .io_deq_ready (io_txcsumReq_ready_0), // @[NIC.scala:112:7] .io_deq_valid (io_txcsumReq_valid_0), .io_deq_bits (_io_txcsumReq_bits_WIRE_1) ); // @[NIC.scala:154:30] HellaQueue_4 rxcsumResQueue ( // @[NIC.scala:155:30] .clock (clock), .reset (reset), .io_enq_ready (io_rxcsumRes_ready_0), .io_enq_valid (io_rxcsumRes_valid_0), // @[NIC.scala:112:7] .io_enq_bits (_rxcsumResQueue_io_enq_bits_T), // @[NIC.scala:163:51] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxcsumResQueue_io_deq_valid), .io_deq_bits (_out_T_44) ); // @[NIC.scala:155:30] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[NIC.scala:112:7] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[NIC.scala:112:7] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[NIC.scala:112:7] assign auto_int_xing_out_sync_1 = auto_int_xing_out_sync_1_0; // @[NIC.scala:112:7] assign io_send_req_valid = io_send_req_valid_0; // @[NIC.scala:112:7] assign io_send_req_bits = io_send_req_bits_0; // @[NIC.scala:112:7] assign io_send_comp_ready = io_send_comp_ready_0; // @[NIC.scala:112:7] assign io_recv_req_valid = io_recv_req_valid_0; // @[NIC.scala:112:7] assign io_recv_req_bits = io_recv_req_bits_0; // @[NIC.scala:112:7] assign io_recv_comp_ready = io_recv_comp_ready_0; // @[NIC.scala:112:7] assign io_txcsumReq_valid = io_txcsumReq_valid_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_check = io_txcsumReq_bits_check_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_offset = io_txcsumReq_bits_offset_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_start = io_txcsumReq_bits_start_0; // @[NIC.scala:112:7] assign io_txcsumReq_bits_init = io_txcsumReq_bits_init_0; // @[NIC.scala:112:7] assign io_rxcsumRes_ready = io_rxcsumRes_ready_0; // @[NIC.scala:112:7] assign io_csumEnable = io_csumEnable_0; // @[NIC.scala:112:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_DebugInternalBundle : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]}}, flip async : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<1> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_31 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<1> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w21 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset node io_deq_bits_deq_bits_reg_io_d_lo = cat(io.async.mem[0].hrmask[1], io.async.mem[0].hrmask[0]) node io_deq_bits_deq_bits_reg_io_d_hi = cat(io.async.mem[0].hrmask[3], io.async.mem[0].hrmask[2]) node _io_deq_bits_deq_bits_reg_io_d_T = cat(io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo) node io_deq_bits_deq_bits_reg_io_d_lo_1 = cat(io.async.mem[0].hamask[1], io.async.mem[0].hamask[0]) node io_deq_bits_deq_bits_reg_io_d_hi_1 = cat(io.async.mem[0].hamask[3], io.async.mem[0].hamask[2]) node _io_deq_bits_deq_bits_reg_io_d_T_1 = cat(io_deq_bits_deq_bits_reg_io_d_hi_1, io_deq_bits_deq_bits_reg_io_d_lo_1) node io_deq_bits_deq_bits_reg_io_d_lo_hi = cat(io.async.mem[0].hasel, _io_deq_bits_deq_bits_reg_io_d_T_1) node io_deq_bits_deq_bits_reg_io_d_lo_2 = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi, _io_deq_bits_deq_bits_reg_io_d_T) node io_deq_bits_deq_bits_reg_io_d_hi_hi = cat(io.async.mem[0].resumereq, io.async.mem[0].hartsel) node io_deq_bits_deq_bits_reg_io_d_hi_2 = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi, io.async.mem[0].ackhavereset) node _io_deq_bits_deq_bits_reg_io_d_T_2 = cat(io_deq_bits_deq_bits_reg_io_d_hi_2, io_deq_bits_deq_bits_reg_io_d_lo_2) connect io_deq_bits_deq_bits_reg.io.d, _io_deq_bits_deq_bits_reg_io_d_T_2 connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[4], hrmask : UInt<1>[4]} wire _io_deq_bits_WIRE_1 : UInt<21> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 0, 0) connect _io_deq_bits_WIRE.hrmask[0], _io_deq_bits_T node _io_deq_bits_T_1 = bits(_io_deq_bits_WIRE_1, 1, 1) connect _io_deq_bits_WIRE.hrmask[1], _io_deq_bits_T_1 node _io_deq_bits_T_2 = bits(_io_deq_bits_WIRE_1, 2, 2) connect _io_deq_bits_WIRE.hrmask[2], _io_deq_bits_T_2 node _io_deq_bits_T_3 = bits(_io_deq_bits_WIRE_1, 3, 3) connect _io_deq_bits_WIRE.hrmask[3], _io_deq_bits_T_3 node _io_deq_bits_T_4 = bits(_io_deq_bits_WIRE_1, 4, 4) connect _io_deq_bits_WIRE.hamask[0], _io_deq_bits_T_4 node _io_deq_bits_T_5 = bits(_io_deq_bits_WIRE_1, 5, 5) connect _io_deq_bits_WIRE.hamask[1], _io_deq_bits_T_5 node _io_deq_bits_T_6 = bits(_io_deq_bits_WIRE_1, 6, 6) connect _io_deq_bits_WIRE.hamask[2], _io_deq_bits_T_6 node _io_deq_bits_T_7 = bits(_io_deq_bits_WIRE_1, 7, 7) connect _io_deq_bits_WIRE.hamask[3], _io_deq_bits_T_7 node _io_deq_bits_T_8 = bits(_io_deq_bits_WIRE_1, 8, 8) connect _io_deq_bits_WIRE.hasel, _io_deq_bits_T_8 node _io_deq_bits_T_9 = bits(_io_deq_bits_WIRE_1, 9, 9) connect _io_deq_bits_WIRE.ackhavereset, _io_deq_bits_T_9 node _io_deq_bits_T_10 = bits(_io_deq_bits_WIRE_1, 19, 10) connect _io_deq_bits_WIRE.hartsel, _io_deq_bits_T_10 node _io_deq_bits_T_11 = bits(_io_deq_bits_WIRE_1, 20, 20) connect _io_deq_bits_WIRE.resumereq, _io_deq_bits_T_11 connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_20 inst sink_valid_1 of AsyncValidSync_21 inst source_extend of AsyncValidSync_22 inst source_valid of AsyncValidSync_23 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1

module AsyncQueueSink_DebugInternalBundle( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] output io_deq_valid, // @[AsyncQueue.scala:139:14] output io_deq_bits_resumereq, // @[AsyncQueue.scala:139:14] output [9:0] io_deq_bits_hartsel, // @[AsyncQueue.scala:139:14] output io_deq_bits_ackhavereset, // @[AsyncQueue.scala:139:14] output io_deq_bits_hasel, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_0, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_1, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_2, // @[AsyncQueue.scala:139:14] output io_deq_bits_hamask_3, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_0, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_1, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_2, // @[AsyncQueue.scala:139:14] output io_deq_bits_hrmask_3, // @[AsyncQueue.scala:139:14] input io_async_mem_0_resumereq, // @[AsyncQueue.scala:139:14] input [9:0] io_async_mem_0_hartsel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_ackhavereset, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hasel, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_1, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_2, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hamask_3, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_0, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_1, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_2, // @[AsyncQueue.scala:139:14] input io_async_mem_0_hrmask_3, // @[AsyncQueue.scala:139:14] output io_async_ridx, // @[AsyncQueue.scala:139:14] input io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire io_deq_valid_0; // @[AsyncQueue.scala:166:29] wire _source_valid_io_out; // @[AsyncQueue.scala:176:31] wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire [20:0] _io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala:207:25] wire _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire ridx = _source_valid_io_out & ridx_ridx_bin + io_deq_valid_0; // @[AsyncQueue.scala:52:25, :53:{23,43}, :166:29, :176:31] wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg valid_reg; // @[AsyncQueue.scala:165:56] assign io_deq_valid_0 = valid_reg & _source_valid_io_out; // @[AsyncQueue.scala:165:56, :166:29, :176:31] reg ridx_gray; // @[AsyncQueue.scala:168:55] always @(posedge clock or posedge reset) begin // @[AsyncQueue.scala:136:7] if (reset) begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25, :136:7] valid_reg <= 1'h0; // @[AsyncQueue.scala:136:7, :165:56] ridx_gray <= 1'h0; // @[AsyncQueue.scala:136:7, :168:55] end else begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx; // @[AsyncQueue.scala:52:25, :53:23] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] ridx_gray <= ridx; // @[AsyncQueue.scala:53:23, :168:55] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_33 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_46 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_33( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_46 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_39 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_39( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_38 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1294 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = and(_T_1296, _T_1301) node _T_1303 = or(UInt<1>(0h0), _T_1302) node _T_1304 = and(_T_1292, _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_26 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(is_aligned, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1314 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_29 node _T_1318 = eq(io.in.a.bits.mask, mask) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_30 node _T_1322 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1322 : node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<1>(0h1)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h2)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1345 = shr(io.in.a.bits.source, 2) node _T_1346 = eq(_T_1345, UInt<2>(0h3)) node _T_1347 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1362 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1384 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1385 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1386 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1387 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1388 = or(_T_1326, _T_1332) node _T_1389 = or(_T_1388, _T_1338) node _T_1390 = or(_T_1389, _T_1344) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = or(_T_1425, _T_1385) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = and(_T_1325, _T_1428) node _T_1430 = or(UInt<1>(0h0), _T_1429) node _T_1431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(UInt<1>(0h0), _T_1433) node _T_1435 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<13>(0h1000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = and(_T_1434, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = and(_T_1430, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_31 node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(is_aligned, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1452 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_34 node _T_1456 = not(mask) node _T_1457 = and(io.in.a.bits.mask, _T_1456) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_35 node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1462 : node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1465 = and(_T_1463, _T_1464) node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<1>(0h1)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h2)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1485 = shr(io.in.a.bits.source, 2) node _T_1486 = eq(_T_1485, UInt<2>(0h3)) node _T_1487 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1488 = and(_T_1486, _T_1487) node _T_1489 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1497 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1498 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1499 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1500 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1501 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1502 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1521 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1522 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1523 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1524 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1526 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1527 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1528 = or(_T_1466, _T_1472) node _T_1529 = or(_T_1528, _T_1478) node _T_1530 = or(_T_1529, _T_1484) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = or(_T_1562, _T_1522) node _T_1564 = or(_T_1563, _T_1523) node _T_1565 = or(_T_1564, _T_1524) node _T_1566 = or(_T_1565, _T_1525) node _T_1567 = or(_T_1566, _T_1526) node _T_1568 = or(_T_1567, _T_1527) node _T_1569 = and(_T_1465, _T_1568) node _T_1570 = or(UInt<1>(0h0), _T_1569) node _T_1571 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1572 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1573 = cvt(_T_1572) node _T_1574 = and(_T_1573, asSInt(UInt<13>(0h1000))) node _T_1575 = asSInt(_T_1574) node _T_1576 = eq(_T_1575, asSInt(UInt<1>(0h0))) node _T_1577 = and(_T_1571, _T_1576) node _T_1578 = or(UInt<1>(0h0), _T_1577) node _T_1579 = and(_T_1570, _T_1578) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_36 node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(source_ok, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(is_aligned, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1589 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_39 node _T_1593 = eq(io.in.a.bits.mask, mask) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_40 node _T_1597 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1597 : node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<1>(0h1)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h2)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<2>(0h3)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1632 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1633 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1634 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1635 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1636 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1637 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1662 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1663 = or(_T_1601, _T_1607) node _T_1664 = or(_T_1663, _T_1613) node _T_1665 = or(_T_1664, _T_1619) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = or(_T_1697, _T_1657) node _T_1699 = or(_T_1698, _T_1658) node _T_1700 = or(_T_1699, _T_1659) node _T_1701 = or(_T_1700, _T_1660) node _T_1702 = or(_T_1701, _T_1661) node _T_1703 = or(_T_1702, _T_1662) node _T_1704 = and(_T_1600, _T_1703) node _T_1705 = or(UInt<1>(0h0), _T_1704) node _T_1706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1707 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = and(_T_1706, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = and(_T_1705, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_41 node _T_1718 = asUInt(reset) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) when _T_1719 : node _T_1720 = eq(source_ok, UInt<1>(0h0)) when _T_1720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(is_aligned, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1724 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1725 = asUInt(reset) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) when _T_1726 : node _T_1727 = eq(_T_1724, UInt<1>(0h0)) when _T_1727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1724, UInt<1>(0h1), "") : assert_44 node _T_1728 = eq(io.in.a.bits.mask, mask) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_45 node _T_1732 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1732 : node _T_1733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1735 = and(_T_1733, _T_1734) node _T_1736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<1>(0h1)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h2)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<2>(0h3)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1798 = or(_T_1736, _T_1742) node _T_1799 = or(_T_1798, _T_1748) node _T_1800 = or(_T_1799, _T_1754) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = or(_T_1832, _T_1792) node _T_1834 = or(_T_1833, _T_1793) node _T_1835 = or(_T_1834, _T_1794) node _T_1836 = or(_T_1835, _T_1795) node _T_1837 = or(_T_1836, _T_1796) node _T_1838 = or(_T_1837, _T_1797) node _T_1839 = and(_T_1735, _T_1838) node _T_1840 = or(UInt<1>(0h0), _T_1839) node _T_1841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1842 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1843 = cvt(_T_1842) node _T_1844 = and(_T_1843, asSInt(UInt<13>(0h1000))) node _T_1845 = asSInt(_T_1844) node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0))) node _T_1847 = and(_T_1841, _T_1846) node _T_1848 = or(UInt<1>(0h0), _T_1847) node _T_1849 = and(_T_1840, _T_1848) node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(_T_1849, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1849, UInt<1>(0h1), "") : assert_46 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(source_ok, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(is_aligned, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1859 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(_T_1859, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1859, UInt<1>(0h1), "") : assert_49 node _T_1863 = eq(io.in.a.bits.mask, mask) node _T_1864 = asUInt(reset) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) when _T_1865 : node _T_1866 = eq(_T_1863, UInt<1>(0h0)) when _T_1866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1863, UInt<1>(0h1), "") : assert_50 node _T_1867 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(_T_1867, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1867, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1871 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(_T_1871, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1871, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1875 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1875 : node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_1, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1879 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_54 node _T_1883 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_55 node _T_1887 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1888 = asUInt(reset) node _T_1889 = eq(_T_1888, UInt<1>(0h0)) when _T_1889 : node _T_1890 = eq(_T_1887, UInt<1>(0h0)) when _T_1890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1887, UInt<1>(0h1), "") : assert_56 node _T_1891 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1892 = asUInt(reset) node _T_1893 = eq(_T_1892, UInt<1>(0h0)) when _T_1893 : node _T_1894 = eq(_T_1891, UInt<1>(0h0)) when _T_1894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1891, UInt<1>(0h1), "") : assert_57 node _T_1895 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1895 : node _T_1896 = asUInt(reset) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) when _T_1897 : node _T_1898 = eq(source_ok_1, UInt<1>(0h0)) when _T_1898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(sink_ok, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1902 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(_T_1902, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1902, UInt<1>(0h1), "") : assert_60 node _T_1906 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_61 node _T_1910 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1911 = asUInt(reset) node _T_1912 = eq(_T_1911, UInt<1>(0h0)) when _T_1912 : node _T_1913 = eq(_T_1910, UInt<1>(0h0)) when _T_1913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1910, UInt<1>(0h1), "") : assert_62 node _T_1914 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_63 node _T_1918 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1919 = or(UInt<1>(0h0), _T_1918) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_64 node _T_1923 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1923 : node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(source_ok_1, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(sink_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_67 node _T_1934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(_T_1934, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1934, UInt<1>(0h1), "") : assert_68 node _T_1938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_69 node _T_1942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1943 = or(_T_1942, io.in.d.bits.corrupt) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_70 node _T_1947 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_71 node _T_1952 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(source_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1956 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1957 = asUInt(reset) node _T_1958 = eq(_T_1957, UInt<1>(0h0)) when _T_1958 : node _T_1959 = eq(_T_1956, UInt<1>(0h0)) when _T_1959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1956, UInt<1>(0h1), "") : assert_73 node _T_1960 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(_T_1960, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1960, UInt<1>(0h1), "") : assert_74 node _T_1964 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1965 = or(UInt<1>(0h0), _T_1964) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_75 node _T_1969 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1973 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1974 = asUInt(reset) node _T_1975 = eq(_T_1974, UInt<1>(0h0)) when _T_1975 : node _T_1976 = eq(_T_1973, UInt<1>(0h0)) when _T_1976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1973, UInt<1>(0h1), "") : assert_77 node _T_1977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1978 = or(_T_1977, io.in.d.bits.corrupt) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_78 node _T_1982 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1983 = or(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_79 node _T_1987 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1987 : node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(source_ok_1, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1991 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(_T_1991, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1991, UInt<1>(0h1), "") : assert_81 node _T_1995 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_82 node _T_1999 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2000 = or(UInt<1>(0h0), _T_1999) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2004 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2008 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2012 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2016 = eq(a_first, UInt<1>(0h0)) node _T_2017 = and(io.in.a.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.a.bits.opcode, opcode) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_87 node _T_2022 = eq(io.in.a.bits.param, param) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_88 node _T_2026 = eq(io.in.a.bits.size, size) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_89 node _T_2030 = eq(io.in.a.bits.source, source) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_90 node _T_2034 = eq(io.in.a.bits.address, address) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_91 node _T_2038 = and(io.in.a.ready, io.in.a.valid) node _T_2039 = and(_T_2038, a_first) when _T_2039 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2040 = eq(d_first, UInt<1>(0h0)) node _T_2041 = and(io.in.d.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.d.bits.opcode, opcode_1) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_92 node _T_2046 = eq(io.in.d.bits.param, param_1) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_93 node _T_2050 = eq(io.in.d.bits.size, size_1) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_94 node _T_2054 = eq(io.in.d.bits.source, source_1) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_95 node _T_2058 = eq(io.in.d.bits.sink, sink) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_96 node _T_2062 = eq(io.in.d.bits.denied, denied) node _T_2063 = asUInt(reset) node _T_2064 = eq(_T_2063, UInt<1>(0h0)) when _T_2064 : node _T_2065 = eq(_T_2062, UInt<1>(0h0)) when _T_2065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2062, UInt<1>(0h1), "") : assert_97 node _T_2066 = and(io.in.d.ready, io.in.d.valid) node _T_2067 = and(_T_2066, d_first) when _T_2067 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2068 = and(io.in.a.valid, a_first_1) node _T_2069 = and(_T_2068, UInt<1>(0h1)) when _T_2069 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2070 = and(io.in.a.ready, io.in.a.valid) node _T_2071 = and(_T_2070, a_first_1) node _T_2072 = and(_T_2071, UInt<1>(0h1)) when _T_2072 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2073 = dshr(inflight, io.in.a.bits.source) node _T_2074 = bits(_T_2073, 0, 0) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) node _T_2076 = asUInt(reset) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) when _T_2077 : node _T_2078 = eq(_T_2075, UInt<1>(0h0)) when _T_2078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2075, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2079 = and(io.in.d.valid, d_first_1) node _T_2080 = and(_T_2079, UInt<1>(0h1)) node _T_2081 = eq(d_release_ack, UInt<1>(0h0)) node _T_2082 = and(_T_2080, _T_2081) when _T_2082 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2083 = and(io.in.d.ready, io.in.d.valid) node _T_2084 = and(_T_2083, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2088 = and(io.in.d.valid, d_first_1) node _T_2089 = and(_T_2088, UInt<1>(0h1)) node _T_2090 = eq(d_release_ack, UInt<1>(0h0)) node _T_2091 = and(_T_2089, _T_2090) when _T_2091 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2092 = dshr(inflight, io.in.d.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = or(_T_2093, same_cycle_resp) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2098 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2099 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2100 = or(_T_2098, _T_2099) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_100 node _T_2104 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_101 else : node _T_2108 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2109 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2110 = or(_T_2108, _T_2109) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_102 node _T_2114 = eq(io.in.d.bits.size, a_size_lookup) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_103 node _T_2118 = and(io.in.d.valid, d_first_1) node _T_2119 = and(_T_2118, a_first_1) node _T_2120 = and(_T_2119, io.in.a.valid) node _T_2121 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2122 = and(_T_2120, _T_2121) node _T_2123 = eq(d_release_ack, UInt<1>(0h0)) node _T_2124 = and(_T_2122, _T_2123) when _T_2124 : node _T_2125 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2126 = or(_T_2125, io.in.a.ready) node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(_T_2126, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2126, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_108 node _T_2130 = orr(inflight) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) node _T_2132 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2133 = or(_T_2131, _T_2132) node _T_2134 = lt(watchdog, plusarg_reader.out) node _T_2135 = or(_T_2133, _T_2134) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2139 = and(io.in.a.ready, io.in.a.valid) node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = or(_T_2139, _T_2140) when _T_2141 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2142 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2143 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2147 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2148 = and(_T_2147, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2149 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2150 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2151 = and(_T_2149, _T_2150) node _T_2152 = and(_T_2148, _T_2151) when _T_2152 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2153 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2154 = bits(_T_2153, 0, 0) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = asUInt(reset) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) when _T_2157 : node _T_2158 = eq(_T_2155, UInt<1>(0h0)) when _T_2158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2155, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2159 = and(io.in.d.valid, d_first_2) node _T_2160 = and(_T_2159, UInt<1>(0h1)) node _T_2161 = and(_T_2160, d_release_ack_1) when _T_2161 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2162 = and(io.in.d.ready, io.in.d.valid) node _T_2163 = and(_T_2162, d_first_2) node _T_2164 = and(_T_2163, UInt<1>(0h1)) node _T_2165 = and(_T_2164, d_release_ack_1) when _T_2165 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2166 = and(io.in.d.valid, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2169 = dshr(inflight_1, io.in.d.bits.source) node _T_2170 = bits(_T_2169, 0, 0) node _T_2171 = or(_T_2170, same_cycle_resp_1) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2175 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_108 else : node _T_2179 = eq(io.in.d.bits.size, c_size_lookup) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_109 node _T_2183 = and(io.in.d.valid, d_first_2) node _T_2184 = and(_T_2183, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2185 = and(_T_2184, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2186 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = and(_T_2187, d_release_ack_1) node _T_2189 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : node _T_2191 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2192 = or(_T_2191, _WIRE_27.ready) node _T_2193 = asUInt(reset) node _T_2194 = eq(_T_2193, UInt<1>(0h0)) when _T_2194 : node _T_2195 = eq(_T_2192, UInt<1>(0h0)) when _T_2195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2192, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_109 node _T_2196 = orr(inflight_1) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) node _T_2198 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2199 = or(_T_2197, _T_2198) node _T_2200 = lt(watchdog_1, plusarg_reader_1.out) node _T_2201 = or(_T_2199, _T_2200) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2205 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2206 = and(io.in.d.ready, io.in.d.valid) node _T_2207 = or(_T_2205, _T_2206) when _T_2207 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_38( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_2 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node sAdjustedExp = add(io.in.sExp, asSInt(UInt<12>(0h900))) node _adjustedSig_T = bits(io.in.sig, 53, 28) node _adjustedSig_T_1 = bits(io.in.sig, 27, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(sAdjustedExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, UInt<1>(0h0)) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(sAdjustedExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(UInt<1>(0h0), _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(UInt<1>(0h0), _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_2( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [53:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [53:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [13:0] sAdjustedExp = {io_in_sExp_0[12], io_in_sExp_0} - 14'h700; // @[RoundAnyRawFNToRecFN.scala:48:5, :110:24] wire [25:0] _adjustedSig_T = io_in_sig_0[53:28]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [27:0] _adjustedSig_T_1 = io_in_sig_0[27:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = sAdjustedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:110:24, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = _roundMask_T_73; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {{12{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:110:24, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [7:0] _common_overflow_T = sRoundedExp[14:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 8'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 15'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] wire [5:0] _common_underflow_T = sAdjustedExp[13:8]; // @[RoundAnyRawFNToRecFN.scala:110:24, :220:49] wire _common_underflow_T_1 = $signed(_common_underflow_T) < 6'sh1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:221:{30,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:223:39, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_12 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock inst q of Queue3_EgressFlit_12 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0hd), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_25 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_26 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0ha), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h19), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<6>(0h7), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<6>(0h13), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<6>(0h4), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_32 = or(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_33 = or(_q_io_enq_bits_ingress_id_T_32, _q_io_enq_bits_ingress_id_T_26) node _q_io_enq_bits_ingress_id_T_34 = or(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_27) node _q_io_enq_bits_ingress_id_T_35 = or(_q_io_enq_bits_ingress_id_T_34, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_35, _q_io_enq_bits_ingress_id_T_29) node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_30) node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_31) wire _q_io_enq_bits_ingress_id_WIRE : UInt<6> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_38 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow

module EgressUnit_12( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e11_s53_3 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e11_s53_3 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e11_s53_3 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<107>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<107>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_6 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulAddRecFNPipe_l2_e11_s53_3( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [64:0] io_a, // @[FPU.scala:638:16] input [64:0] io_b, // @[FPU.scala:638:16] input [64:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [64:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [64:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [64:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [64:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [105:0] _mulAddResult_T = {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [106:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [12:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [55:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e11_s53_3 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e11_s53_3 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e11_s53_6 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PhitDemux_p32_f32_n5 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}[5]} regreset beat : UInt<1>, clock, reset, UInt<1>(0h0) reg channel_vec : UInt<32>[1], clock node channel = bits(channel_vec[0], 2, 0) node _io_in_ready_T = lt(beat, UInt<1>(0h1)) wire _io_in_ready_WIRE : UInt<1>[5] connect _io_in_ready_WIRE[0], io.out[0].ready connect _io_in_ready_WIRE[1], io.out[1].ready connect _io_in_ready_WIRE[2], io.out[2].ready connect _io_in_ready_WIRE[3], io.out[3].ready connect _io_in_ready_WIRE[4], io.out[4].ready node _io_in_ready_T_1 = or(_io_in_ready_T, _io_in_ready_WIRE[channel]) connect io.in.ready, _io_in_ready_T_1 node _io_out_0_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_0_valid_T_1 = and(io.in.valid, _io_out_0_valid_T) node _io_out_0_valid_T_2 = eq(channel, UInt<1>(0h0)) node _io_out_0_valid_T_3 = and(_io_out_0_valid_T_1, _io_out_0_valid_T_2) connect io.out[0].valid, _io_out_0_valid_T_3 connect io.out[0].bits.phit, io.in.bits.phit node _io_out_1_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_1_valid_T_1 = and(io.in.valid, _io_out_1_valid_T) node _io_out_1_valid_T_2 = eq(channel, UInt<1>(0h1)) node _io_out_1_valid_T_3 = and(_io_out_1_valid_T_1, _io_out_1_valid_T_2) connect io.out[1].valid, _io_out_1_valid_T_3 connect io.out[1].bits.phit, io.in.bits.phit node _io_out_2_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_2_valid_T_1 = and(io.in.valid, _io_out_2_valid_T) node _io_out_2_valid_T_2 = eq(channel, UInt<2>(0h2)) node _io_out_2_valid_T_3 = and(_io_out_2_valid_T_1, _io_out_2_valid_T_2) connect io.out[2].valid, _io_out_2_valid_T_3 connect io.out[2].bits.phit, io.in.bits.phit node _io_out_3_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_3_valid_T_1 = and(io.in.valid, _io_out_3_valid_T) node _io_out_3_valid_T_2 = eq(channel, UInt<2>(0h3)) node _io_out_3_valid_T_3 = and(_io_out_3_valid_T_1, _io_out_3_valid_T_2) connect io.out[3].valid, _io_out_3_valid_T_3 connect io.out[3].bits.phit, io.in.bits.phit node _io_out_4_valid_T = geq(beat, UInt<1>(0h1)) node _io_out_4_valid_T_1 = and(io.in.valid, _io_out_4_valid_T) node _io_out_4_valid_T_2 = eq(channel, UInt<3>(0h4)) node _io_out_4_valid_T_3 = and(_io_out_4_valid_T_1, _io_out_4_valid_T_2) connect io.out[4].valid, _io_out_4_valid_T_3 connect io.out[4].bits.phit, io.in.bits.phit node _T = and(io.in.ready, io.in.valid) when _T : node _beat_T = eq(beat, UInt<1>(0h1)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = lt(beat, UInt<1>(0h1)) when _T_1 : connect channel_vec[0], io.in.bits.phit

module PhitDemux_p32_f32_n5( // @[Serdes.scala:183:7] input clock, // @[Serdes.scala:183:7] input reset, // @[Serdes.scala:183:7] output io_in_ready, // @[Serdes.scala:185:14] input io_in_valid, // @[Serdes.scala:185:14] input [31:0] io_in_bits_phit, // @[Serdes.scala:185:14] input io_out_0_ready, // @[Serdes.scala:185:14] output io_out_0_valid, // @[Serdes.scala:185:14] output [31:0] io_out_0_bits_phit, // @[Serdes.scala:185:14] input io_out_1_ready, // @[Serdes.scala:185:14] output io_out_1_valid, // @[Serdes.scala:185:14] output [31:0] io_out_1_bits_phit, // @[Serdes.scala:185:14] input io_out_2_ready, // @[Serdes.scala:185:14] output io_out_2_valid, // @[Serdes.scala:185:14] output [31:0] io_out_2_bits_phit, // @[Serdes.scala:185:14] input io_out_3_ready, // @[Serdes.scala:185:14] output io_out_3_valid, // @[Serdes.scala:185:14] output [31:0] io_out_3_bits_phit, // @[Serdes.scala:185:14] input io_out_4_ready, // @[Serdes.scala:185:14] output io_out_4_valid, // @[Serdes.scala:185:14] output [31:0] io_out_4_bits_phit // @[Serdes.scala:185:14] ); reg beat; // @[Serdes.scala:196:23] reg [31:0] channel_vec_0; // @[Serdes.scala:197:26] wire [7:0] _GEN = {{io_out_0_ready}, {io_out_0_ready}, {io_out_0_ready}, {io_out_4_ready}, {io_out_3_ready}, {io_out_2_ready}, {io_out_1_ready}, {io_out_0_ready}}; // @[Serdes.scala:201:41] wire io_in_ready_0 = ~beat | _GEN[channel_vec_0[2:0]]; // @[Serdes.scala:196:23, :197:26, :198:37, :201:{25,41}] wire _GEN_0 = io_in_ready_0 & io_in_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Serdes.scala:183:7] if (reset) // @[Serdes.scala:183:7] beat <= 1'h0; // @[Serdes.scala:183:7, :196:23] else if (_GEN_0) // @[Decoupled.scala:51:35] beat <= ~beat & beat - 1'h1; // @[Serdes.scala:196:23, :208:{18,51}] if (_GEN_0 & ~beat) // @[Decoupled.scala:51:35] channel_vec_0 <= io_in_bits_phit; // @[Serdes.scala:197:26] always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_3 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [16] wire _valids_WIRE : UInt<1>[16] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) connect _valids_WIRE[15], UInt<1>(0h0) regreset valids : UInt<1>[16], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = and(valids[3], _valids_3_T_2) node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0)) node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5) connect valids[3], _valids_3_T_6 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = and(valids[4], _valids_4_T_2) node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0)) node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5) connect valids[4], _valids_4_T_6 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = and(valids[5], _valids_5_T_2) node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0)) node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5) connect valids[5], _valids_5_T_6 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = and(valids[6], _valids_6_T_2) node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0)) node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5) connect valids[6], _valids_6_T_6 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = and(valids[7], _valids_7_T_2) node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0)) node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5) connect valids[7], _valids_7_T_6 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = and(valids[8], _valids_8_T_2) node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0)) node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5) connect valids[8], _valids_8_T_6 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = and(valids[9], _valids_9_T_2) node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0)) node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5) connect valids[9], _valids_9_T_6 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = and(valids[10], _valids_10_T_2) node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0)) node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5) connect valids[10], _valids_10_T_6 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = and(valids[11], _valids_11_T_2) node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0)) node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5) connect valids[11], _valids_11_T_6 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = and(valids[12], _valids_12_T_2) node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0)) node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5) connect valids[12], _valids_12_T_6 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = and(valids[13], _valids_13_T_2) node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0)) node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5) connect valids[13], _valids_13_T_6 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = and(valids[14], _valids_14_T_2) node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0)) node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5) connect valids[14], _valids_14_T_6 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask) node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0)) node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0)) node _valids_15_T_3 = and(valids[15], _valids_15_T_2) node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq) node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0)) node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5) connect valids[15], _valids_15_T_6 when valids[15] : node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T) connect uops[15].br_mask, _uops_15_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0hf)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = cat(_io_count_T, ptr_diff) connect io.count, _io_count_T_1

module BranchKillableQueue_3( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [39:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [7:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [39:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_is_br, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14] input io_brupdate_b2_uop_taken, // @[util.scala:453:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14] input io_brupdate_b2_uop_exception, // @[util.scala:453:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14] input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14] input io_brupdate_b2_valid, // @[util.scala:453:14] input io_brupdate_b2_mispredict, // @[util.scala:453:14] input io_brupdate_b2_taken, // @[util.scala:453:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14] input io_flush, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [140:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7] wire io_flush_0 = io_flush; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _io_enq_ready_T; // @[util.scala:504:19] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [39:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [15:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [3:0] out_uop_br_tag; // @[util.scala:506:17] wire [4:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [6:0] out_uop_rob_idx; // @[util.scala:506:17] wire [4:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [4:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [4:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [39:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [19:0] out_old_meta_tag; // @[util.scala:506:17] wire [7:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] reg valids_1; // @[util.scala:465:24] reg valids_2; // @[util.scala:465:24] reg valids_3; // @[util.scala:465:24] reg valids_4; // @[util.scala:465:24] reg valids_5; // @[util.scala:465:24] reg valids_6; // @[util.scala:465:24] reg valids_7; // @[util.scala:465:24] reg valids_8; // @[util.scala:465:24] reg valids_9; // @[util.scala:465:24] reg valids_10; // @[util.scala:465:24] reg valids_11; // @[util.scala:465:24] reg valids_12; // @[util.scala:465:24] reg valids_13; // @[util.scala:465:24] reg valids_14; // @[util.scala:465:24] reg valids_15; // @[util.scala:465:24] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [39:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [15:0] uops_0_br_mask; // @[util.scala:466:20] reg [3:0] uops_0_br_tag; // @[util.scala:466:20] reg [4:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [6:0] uops_0_rob_idx; // @[util.scala:466:20] reg [4:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [4:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [39:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [15:0] uops_1_br_mask; // @[util.scala:466:20] reg [3:0] uops_1_br_tag; // @[util.scala:466:20] reg [4:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [6:0] uops_1_rob_idx; // @[util.scala:466:20] reg [4:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [4:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [39:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [15:0] uops_2_br_mask; // @[util.scala:466:20] reg [3:0] uops_2_br_tag; // @[util.scala:466:20] reg [4:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [6:0] uops_2_rob_idx; // @[util.scala:466:20] reg [4:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [4:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [39:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [15:0] uops_3_br_mask; // @[util.scala:466:20] reg [3:0] uops_3_br_tag; // @[util.scala:466:20] reg [4:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [6:0] uops_3_rob_idx; // @[util.scala:466:20] reg [4:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [4:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [39:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [15:0] uops_4_br_mask; // @[util.scala:466:20] reg [3:0] uops_4_br_tag; // @[util.scala:466:20] reg [4:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [6:0] uops_4_rob_idx; // @[util.scala:466:20] reg [4:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [4:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [39:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [15:0] uops_5_br_mask; // @[util.scala:466:20] reg [3:0] uops_5_br_tag; // @[util.scala:466:20] reg [4:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [6:0] uops_5_rob_idx; // @[util.scala:466:20] reg [4:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [4:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [39:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [15:0] uops_6_br_mask; // @[util.scala:466:20] reg [3:0] uops_6_br_tag; // @[util.scala:466:20] reg [4:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [6:0] uops_6_rob_idx; // @[util.scala:466:20] reg [4:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [4:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [39:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [15:0] uops_7_br_mask; // @[util.scala:466:20] reg [3:0] uops_7_br_tag; // @[util.scala:466:20] reg [4:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [6:0] uops_7_rob_idx; // @[util.scala:466:20] reg [4:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [4:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [39:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [15:0] uops_8_br_mask; // @[util.scala:466:20] reg [3:0] uops_8_br_tag; // @[util.scala:466:20] reg [4:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [6:0] uops_8_rob_idx; // @[util.scala:466:20] reg [4:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [4:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [39:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [15:0] uops_9_br_mask; // @[util.scala:466:20] reg [3:0] uops_9_br_tag; // @[util.scala:466:20] reg [4:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [6:0] uops_9_rob_idx; // @[util.scala:466:20] reg [4:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [4:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [39:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [15:0] uops_10_br_mask; // @[util.scala:466:20] reg [3:0] uops_10_br_tag; // @[util.scala:466:20] reg [4:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [6:0] uops_10_rob_idx; // @[util.scala:466:20] reg [4:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [4:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [39:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [15:0] uops_11_br_mask; // @[util.scala:466:20] reg [3:0] uops_11_br_tag; // @[util.scala:466:20] reg [4:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [6:0] uops_11_rob_idx; // @[util.scala:466:20] reg [4:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [4:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [39:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [15:0] uops_12_br_mask; // @[util.scala:466:20] reg [3:0] uops_12_br_tag; // @[util.scala:466:20] reg [4:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [6:0] uops_12_rob_idx; // @[util.scala:466:20] reg [4:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [4:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [39:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [15:0] uops_13_br_mask; // @[util.scala:466:20] reg [3:0] uops_13_br_tag; // @[util.scala:466:20] reg [4:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [6:0] uops_13_rob_idx; // @[util.scala:466:20] reg [4:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [4:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [39:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [15:0] uops_14_br_mask; // @[util.scala:466:20] reg [3:0] uops_14_br_tag; // @[util.scala:466:20] reg [4:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [6:0] uops_14_rob_idx; // @[util.scala:466:20] reg [4:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [4:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [39:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [15:0] uops_15_br_mask; // @[util.scala:466:20] reg [3:0] uops_15_br_tag; // @[util.scala:466:20] reg [4:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [6:0] uops_15_rob_idx; // @[util.scala:466:20] reg [4:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [4:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}] wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32] wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_0_T_4 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}] wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}] wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32] wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_1_T_4 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}] wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}] wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32] wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_2_T_4 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}] wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:118:{51,59}] wire _valids_3_T_2 = ~_valids_3_T_1; // @[util.scala:118:59, :481:32] wire _valids_3_T_3 = valids_3 & _valids_3_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_3_T_4 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_3_T_5 = ~_valids_3_T_4; // @[util.scala:481:{72,83}] wire _valids_3_T_6 = _valids_3_T_3 & _valids_3_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:118:{51,59}] wire _valids_4_T_2 = ~_valids_4_T_1; // @[util.scala:118:59, :481:32] wire _valids_4_T_3 = valids_4 & _valids_4_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_4_T_4 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_4_T_5 = ~_valids_4_T_4; // @[util.scala:481:{72,83}] wire _valids_4_T_6 = _valids_4_T_3 & _valids_4_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:118:{51,59}] wire _valids_5_T_2 = ~_valids_5_T_1; // @[util.scala:118:59, :481:32] wire _valids_5_T_3 = valids_5 & _valids_5_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_5_T_4 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_5_T_5 = ~_valids_5_T_4; // @[util.scala:481:{72,83}] wire _valids_5_T_6 = _valids_5_T_3 & _valids_5_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:118:{51,59}] wire _valids_6_T_2 = ~_valids_6_T_1; // @[util.scala:118:59, :481:32] wire _valids_6_T_3 = valids_6 & _valids_6_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_6_T_4 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_6_T_5 = ~_valids_6_T_4; // @[util.scala:481:{72,83}] wire _valids_6_T_6 = _valids_6_T_3 & _valids_6_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:118:{51,59}] wire _valids_7_T_2 = ~_valids_7_T_1; // @[util.scala:118:59, :481:32] wire _valids_7_T_3 = valids_7 & _valids_7_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_7_T_4 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_7_T_5 = ~_valids_7_T_4; // @[util.scala:481:{72,83}] wire _valids_7_T_6 = _valids_7_T_3 & _valids_7_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:118:{51,59}] wire _valids_8_T_2 = ~_valids_8_T_1; // @[util.scala:118:59, :481:32] wire _valids_8_T_3 = valids_8 & _valids_8_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_8_T_4 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_8_T_5 = ~_valids_8_T_4; // @[util.scala:481:{72,83}] wire _valids_8_T_6 = _valids_8_T_3 & _valids_8_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:118:{51,59}] wire _valids_9_T_2 = ~_valids_9_T_1; // @[util.scala:118:59, :481:32] wire _valids_9_T_3 = valids_9 & _valids_9_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_9_T_4 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_9_T_5 = ~_valids_9_T_4; // @[util.scala:481:{72,83}] wire _valids_9_T_6 = _valids_9_T_3 & _valids_9_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:118:{51,59}] wire _valids_10_T_2 = ~_valids_10_T_1; // @[util.scala:118:59, :481:32] wire _valids_10_T_3 = valids_10 & _valids_10_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_10_T_4 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_10_T_5 = ~_valids_10_T_4; // @[util.scala:481:{72,83}] wire _valids_10_T_6 = _valids_10_T_3 & _valids_10_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:118:{51,59}] wire _valids_11_T_2 = ~_valids_11_T_1; // @[util.scala:118:59, :481:32] wire _valids_11_T_3 = valids_11 & _valids_11_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_11_T_4 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_11_T_5 = ~_valids_11_T_4; // @[util.scala:481:{72,83}] wire _valids_11_T_6 = _valids_11_T_3 & _valids_11_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:118:{51,59}] wire _valids_12_T_2 = ~_valids_12_T_1; // @[util.scala:118:59, :481:32] wire _valids_12_T_3 = valids_12 & _valids_12_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_12_T_4 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_12_T_5 = ~_valids_12_T_4; // @[util.scala:481:{72,83}] wire _valids_12_T_6 = _valids_12_T_3 & _valids_12_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:118:{51,59}] wire _valids_13_T_2 = ~_valids_13_T_1; // @[util.scala:118:59, :481:32] wire _valids_13_T_3 = valids_13 & _valids_13_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_13_T_4 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_13_T_5 = ~_valids_13_T_4; // @[util.scala:481:{72,83}] wire _valids_13_T_6 = _valids_13_T_3 & _valids_13_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:118:{51,59}] wire _valids_14_T_2 = ~_valids_14_T_1; // @[util.scala:118:59, :481:32] wire _valids_14_T_3 = valids_14 & _valids_14_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_14_T_4 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_14_T_5 = ~_valids_14_T_4; // @[util.scala:481:{72,83}] wire _valids_14_T_6 = _valids_14_T_3 & _valids_14_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_15_T = io_brupdate_b1_mispredict_mask_0 & uops_15_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_15_T_1 = |_valids_15_T; // @[util.scala:118:{51,59}] wire _valids_15_T_2 = ~_valids_15_T_1; // @[util.scala:118:59, :481:32] wire _valids_15_T_3 = valids_15 & _valids_15_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_15_T_4 = io_flush_0 & uops_15_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_15_T_5 = ~_valids_15_T_4; // @[util.scala:481:{72,83}] wire _valids_15_T_6 = _valids_15_T_3 & _valids_15_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_15_br_mask_T_1 = uops_15_br_mask & _uops_15_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0] out_uop_br_mask; // @[util.scala:506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][39:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][15:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire [15:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17] wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}] wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68] wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}] wire _io_deq_valid_T_6 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :509:122] wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] wire [15:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x141 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_135 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} wire _in_flight_WIRE : UInt<1>[10] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) connect _in_flight_WIRE[8], UInt<1>(0h0) connect _in_flight_WIRE[9], UInt<1>(0h0) regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = or(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_21, UInt<1>(0h1), "") : assert_4 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_26 = or(_T_25, UInt<1>(0h0)) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_26, UInt<1>(0h1), "") : assert_5 node _T_30 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_31 = or(_T_30, UInt<1>(0h0)) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_31, UInt<1>(0h1), "") : assert_6 node _T_35 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_36 = or(_T_35, UInt<1>(0h0)) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_36, UInt<1>(0h1), "") : assert_7 node _T_40 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_41 = or(_T_40, UInt<1>(0h0)) node _T_42 = asUInt(reset) node _T_43 = eq(_T_42, UInt<1>(0h0)) when _T_43 : node _T_44 = eq(_T_41, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_41, UInt<1>(0h1), "") : assert_8 node _T_45 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_46 = or(_T_45, UInt<1>(0h0)) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9 assert(clock, _T_46, UInt<1>(0h1), "") : assert_9 node _T_50 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h3)) node _T_71 = and(_T_69, _T_70) node _T_72 = or(_T_57, _T_64) node _T_73 = or(_T_72, _T_71) node _T_74 = or(_T_50, _T_73) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10 assert(clock, _T_74, UInt<1>(0h1), "") : assert_10

module NoCMonitor_135( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 4'h3; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 4'h4; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 4'h5; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 4'h7; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 4'h8; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_88 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_88( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_107 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_124 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_107( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_124 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = and(_T_11, _T_24) node _T_105 = and(_T_104, _T_37) node _T_106 = and(_T_105, _T_50) node _T_107 = and(_T_106, _T_63) node _T_108 = and(_T_107, _T_71) node _T_109 = and(_T_108, _T_79) node _T_110 = and(_T_109, _T_87) node _T_111 = and(_T_110, _T_95) node _T_112 = and(_T_111, _T_103) node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(_T_112, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_112, UInt<1>(0h1), "") : assert_1 node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_116 : node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_4) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_127 = shr(io.in.a.bits.source, 2) node _T_128 = eq(_T_127, UInt<1>(0h1)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_5) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_132 = and(_T_130, _T_131) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_133 = shr(io.in.a.bits.source, 2) node _T_134 = eq(_T_133, UInt<2>(0h2)) node _T_135 = leq(UInt<1>(0h0), uncommonBits_6) node _T_136 = and(_T_134, _T_135) node _T_137 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<2>(0h3)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_7) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_120, _T_126) node _T_151 = or(_T_150, _T_132) node _T_152 = or(_T_151, _T_138) node _T_153 = or(_T_152, _T_144) node _T_154 = or(_T_153, _T_145) node _T_155 = or(_T_154, _T_146) node _T_156 = or(_T_155, _T_147) node _T_157 = or(_T_156, _T_148) node _T_158 = or(_T_157, _T_149) node _T_159 = and(_T_119, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<14>(0h2000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<11>(0h400))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<9>(0h100))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_178 = cvt(_T_177) node _T_179 = and(_T_178, asSInt(UInt<13>(0h1000))) node _T_180 = asSInt(_T_179) node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0))) node _T_182 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<17>(0h10000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_188 = cvt(_T_187) node _T_189 = and(_T_188, asSInt(UInt<18>(0h2f000))) node _T_190 = asSInt(_T_189) node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0))) node _T_192 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_193 = cvt(_T_192) node _T_194 = and(_T_193, asSInt(UInt<17>(0h10000))) node _T_195 = asSInt(_T_194) node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<13>(0h1000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<27>(0h4000000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<13>(0h1000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = or(_T_166, _T_171) node _T_213 = or(_T_212, _T_176) node _T_214 = or(_T_213, _T_181) node _T_215 = or(_T_214, _T_186) node _T_216 = or(_T_215, _T_191) node _T_217 = or(_T_216, _T_196) node _T_218 = or(_T_217, _T_201) node _T_219 = or(_T_218, _T_206) node _T_220 = or(_T_219, _T_211) node _T_221 = and(_T_161, _T_220) node _T_222 = or(UInt<1>(0h0), _T_221) node _T_223 = and(_T_160, _T_222) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_223, UInt<1>(0h1), "") : assert_2 node _T_227 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_228 = shr(io.in.a.bits.source, 2) node _T_229 = eq(_T_228, UInt<1>(0h0)) node _T_230 = leq(UInt<1>(0h0), uncommonBits_8) node _T_231 = and(_T_229, _T_230) node _T_232 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_233 = and(_T_231, _T_232) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_234 = shr(io.in.a.bits.source, 2) node _T_235 = eq(_T_234, UInt<1>(0h1)) node _T_236 = leq(UInt<1>(0h0), uncommonBits_9) node _T_237 = and(_T_235, _T_236) node _T_238 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_240 = shr(io.in.a.bits.source, 2) node _T_241 = eq(_T_240, UInt<2>(0h2)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_10) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_245 = and(_T_243, _T_244) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_246 = shr(io.in.a.bits.source, 2) node _T_247 = eq(_T_246, UInt<2>(0h3)) node _T_248 = leq(UInt<1>(0h0), uncommonBits_11) node _T_249 = and(_T_247, _T_248) node _T_250 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_253 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_227 connect _WIRE[1], _T_233 connect _WIRE[2], _T_239 connect _WIRE[3], _T_245 connect _WIRE[4], _T_251 connect _WIRE[5], _T_252 connect _WIRE[6], _T_253 connect _WIRE[7], _T_254 connect _WIRE[8], _T_255 connect _WIRE[9], _T_256 node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_258 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_259 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_260 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_261 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_262 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_264 = mux(_WIRE[6], _T_257, UInt<1>(0h0)) node _T_265 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_266 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_267 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_268 = or(_T_258, _T_259) node _T_269 = or(_T_268, _T_260) node _T_270 = or(_T_269, _T_261) node _T_271 = or(_T_270, _T_262) node _T_272 = or(_T_271, _T_263) node _T_273 = or(_T_272, _T_264) node _T_274 = or(_T_273, _T_265) node _T_275 = or(_T_274, _T_266) node _T_276 = or(_T_275, _T_267) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_276 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<11>(0h400))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<9>(0h100))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<13>(0h1000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<18>(0h2f000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<13>(0h1000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<27>(0h4000000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = or(_T_285, _T_290) node _T_332 = or(_T_331, _T_295) node _T_333 = or(_T_332, _T_300) node _T_334 = or(_T_333, _T_305) node _T_335 = or(_T_334, _T_310) node _T_336 = or(_T_335, _T_315) node _T_337 = or(_T_336, _T_320) node _T_338 = or(_T_337, _T_325) node _T_339 = or(_T_338, _T_330) node _T_340 = and(_T_280, _T_339) node _T_341 = or(UInt<1>(0h0), _T_340) node _T_342 = and(_WIRE_1, _T_341) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_342, UInt<1>(0h1), "") : assert_3 node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(source_ok, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_349 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_349, UInt<1>(0h1), "") : assert_5 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(is_aligned, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_356 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_356, UInt<1>(0h1), "") : assert_7 node _T_360 = not(io.in.a.bits.mask) node _T_361 = eq(_T_360, UInt<1>(0h0)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_361, UInt<1>(0h1), "") : assert_8 node _T_365 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_365, UInt<1>(0h1), "") : assert_9 node _T_369 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_369 : node _T_370 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_371 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_374 = shr(io.in.a.bits.source, 2) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_12) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_379 = and(_T_377, _T_378) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_380 = shr(io.in.a.bits.source, 2) node _T_381 = eq(_T_380, UInt<1>(0h1)) node _T_382 = leq(UInt<1>(0h0), uncommonBits_13) node _T_383 = and(_T_381, _T_382) node _T_384 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_385 = and(_T_383, _T_384) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_386 = shr(io.in.a.bits.source, 2) node _T_387 = eq(_T_386, UInt<2>(0h2)) node _T_388 = leq(UInt<1>(0h0), uncommonBits_14) node _T_389 = and(_T_387, _T_388) node _T_390 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_391 = and(_T_389, _T_390) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_392 = shr(io.in.a.bits.source, 2) node _T_393 = eq(_T_392, UInt<2>(0h3)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_15) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_397 = and(_T_395, _T_396) node _T_398 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_401 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_402 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_403 = or(_T_373, _T_379) node _T_404 = or(_T_403, _T_385) node _T_405 = or(_T_404, _T_391) node _T_406 = or(_T_405, _T_397) node _T_407 = or(_T_406, _T_398) node _T_408 = or(_T_407, _T_399) node _T_409 = or(_T_408, _T_400) node _T_410 = or(_T_409, _T_401) node _T_411 = or(_T_410, _T_402) node _T_412 = and(_T_372, _T_411) node _T_413 = or(UInt<1>(0h0), _T_412) node _T_414 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_415 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<14>(0h2000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<11>(0h400))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_426 = cvt(_T_425) node _T_427 = and(_T_426, asSInt(UInt<9>(0h100))) node _T_428 = asSInt(_T_427) node _T_429 = eq(_T_428, asSInt(UInt<1>(0h0))) node _T_430 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<13>(0h1000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<17>(0h10000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_441 = cvt(_T_440) node _T_442 = and(_T_441, asSInt(UInt<18>(0h2f000))) node _T_443 = asSInt(_T_442) node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0))) node _T_445 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_446 = cvt(_T_445) node _T_447 = and(_T_446, asSInt(UInt<17>(0h10000))) node _T_448 = asSInt(_T_447) node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0))) node _T_450 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_451 = cvt(_T_450) node _T_452 = and(_T_451, asSInt(UInt<13>(0h1000))) node _T_453 = asSInt(_T_452) node _T_454 = eq(_T_453, asSInt(UInt<1>(0h0))) node _T_455 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<27>(0h4000000))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<13>(0h1000))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = or(_T_419, _T_424) node _T_466 = or(_T_465, _T_429) node _T_467 = or(_T_466, _T_434) node _T_468 = or(_T_467, _T_439) node _T_469 = or(_T_468, _T_444) node _T_470 = or(_T_469, _T_449) node _T_471 = or(_T_470, _T_454) node _T_472 = or(_T_471, _T_459) node _T_473 = or(_T_472, _T_464) node _T_474 = and(_T_414, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = and(_T_413, _T_475) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_476, UInt<1>(0h1), "") : assert_10 node _T_480 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_481 = shr(io.in.a.bits.source, 2) node _T_482 = eq(_T_481, UInt<1>(0h0)) node _T_483 = leq(UInt<1>(0h0), uncommonBits_16) node _T_484 = and(_T_482, _T_483) node _T_485 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_486 = and(_T_484, _T_485) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_487 = shr(io.in.a.bits.source, 2) node _T_488 = eq(_T_487, UInt<1>(0h1)) node _T_489 = leq(UInt<1>(0h0), uncommonBits_17) node _T_490 = and(_T_488, _T_489) node _T_491 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_492 = and(_T_490, _T_491) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_493 = shr(io.in.a.bits.source, 2) node _T_494 = eq(_T_493, UInt<2>(0h2)) node _T_495 = leq(UInt<1>(0h0), uncommonBits_18) node _T_496 = and(_T_494, _T_495) node _T_497 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_498 = and(_T_496, _T_497) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_499 = shr(io.in.a.bits.source, 2) node _T_500 = eq(_T_499, UInt<2>(0h3)) node _T_501 = leq(UInt<1>(0h0), uncommonBits_19) node _T_502 = and(_T_500, _T_501) node _T_503 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_504 = and(_T_502, _T_503) node _T_505 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_506 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_507 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_509 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_480 connect _WIRE_2[1], _T_486 connect _WIRE_2[2], _T_492 connect _WIRE_2[3], _T_498 connect _WIRE_2[4], _T_504 connect _WIRE_2[5], _T_505 connect _WIRE_2[6], _T_506 connect _WIRE_2[7], _T_507 connect _WIRE_2[8], _T_508 connect _WIRE_2[9], _T_509 node _T_510 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_511 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_512 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_513 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_515 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_516 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_517 = mux(_WIRE_2[6], _T_510, UInt<1>(0h0)) node _T_518 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_520 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_521 = or(_T_511, _T_512) node _T_522 = or(_T_521, _T_513) node _T_523 = or(_T_522, _T_514) node _T_524 = or(_T_523, _T_515) node _T_525 = or(_T_524, _T_516) node _T_526 = or(_T_525, _T_517) node _T_527 = or(_T_526, _T_518) node _T_528 = or(_T_527, _T_519) node _T_529 = or(_T_528, _T_520) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_529 node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_532 = and(_T_530, _T_531) node _T_533 = or(UInt<1>(0h0), _T_532) node _T_534 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<14>(0h2000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<11>(0h400))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<9>(0h100))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<13>(0h1000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<17>(0h10000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<18>(0h2f000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<13>(0h1000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<27>(0h4000000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = or(_T_538, _T_543) node _T_585 = or(_T_584, _T_548) node _T_586 = or(_T_585, _T_553) node _T_587 = or(_T_586, _T_558) node _T_588 = or(_T_587, _T_563) node _T_589 = or(_T_588, _T_568) node _T_590 = or(_T_589, _T_573) node _T_591 = or(_T_590, _T_578) node _T_592 = or(_T_591, _T_583) node _T_593 = and(_T_533, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_WIRE_3, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_595, UInt<1>(0h1), "") : assert_11 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_602 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_602, UInt<1>(0h1), "") : assert_13 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(is_aligned, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_609 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_610 = asUInt(reset) node _T_611 = eq(_T_610, UInt<1>(0h0)) when _T_611 : node _T_612 = eq(_T_609, UInt<1>(0h0)) when _T_612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_609, UInt<1>(0h1), "") : assert_15 node _T_613 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_613, UInt<1>(0h1), "") : assert_16 node _T_617 = not(io.in.a.bits.mask) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_618, UInt<1>(0h1), "") : assert_17 node _T_622 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_622, UInt<1>(0h1), "") : assert_18 node _T_626 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_626 : node _T_627 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_628 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_629 = and(_T_627, _T_628) node _T_630 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_631 = shr(io.in.a.bits.source, 2) node _T_632 = eq(_T_631, UInt<1>(0h0)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_20) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<1>(0h1)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_21) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<2>(0h2)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_22) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_649 = shr(io.in.a.bits.source, 2) node _T_650 = eq(_T_649, UInt<2>(0h3)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_23) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_656 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_657 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_658 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_659 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_660 = or(_T_630, _T_636) node _T_661 = or(_T_660, _T_642) node _T_662 = or(_T_661, _T_648) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_655) node _T_665 = or(_T_664, _T_656) node _T_666 = or(_T_665, _T_657) node _T_667 = or(_T_666, _T_658) node _T_668 = or(_T_667, _T_659) node _T_669 = and(_T_629, _T_668) node _T_670 = or(UInt<1>(0h0), _T_669) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_670, UInt<1>(0h1), "") : assert_19 node _T_674 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_675 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_676 = and(_T_674, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = and(_T_677, _T_682) node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_686 = and(_T_684, _T_685) node _T_687 = or(UInt<1>(0h0), _T_686) node _T_688 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<14>(0h2000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<11>(0h400))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<9>(0h100))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<17>(0h10000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<27>(0h4000000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = or(_T_692, _T_697) node _T_734 = or(_T_733, _T_702) node _T_735 = or(_T_734, _T_707) node _T_736 = or(_T_735, _T_712) node _T_737 = or(_T_736, _T_717) node _T_738 = or(_T_737, _T_722) node _T_739 = or(_T_738, _T_727) node _T_740 = or(_T_739, _T_732) node _T_741 = and(_T_687, _T_740) node _T_742 = or(UInt<1>(0h0), _T_683) node _T_743 = or(_T_742, _T_741) node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(_T_743, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_743, UInt<1>(0h1), "") : assert_20 node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(source_ok, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(is_aligned, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_753 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_754 = asUInt(reset) node _T_755 = eq(_T_754, UInt<1>(0h0)) when _T_755 : node _T_756 = eq(_T_753, UInt<1>(0h0)) when _T_756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_753, UInt<1>(0h1), "") : assert_23 node _T_757 = eq(io.in.a.bits.mask, mask) node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(_T_757, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_757, UInt<1>(0h1), "") : assert_24 node _T_761 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_761, UInt<1>(0h1), "") : assert_25 node _T_765 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<1>(0h0)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_24) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<1>(0h1)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_25) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<2>(0h2)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_26) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<2>(0h3)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_27) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_795 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_798 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_799 = or(_T_769, _T_775) node _T_800 = or(_T_799, _T_781) node _T_801 = or(_T_800, _T_787) node _T_802 = or(_T_801, _T_793) node _T_803 = or(_T_802, _T_794) node _T_804 = or(_T_803, _T_795) node _T_805 = or(_T_804, _T_796) node _T_806 = or(_T_805, _T_797) node _T_807 = or(_T_806, _T_798) node _T_808 = and(_T_768, _T_807) node _T_809 = or(UInt<1>(0h0), _T_808) node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_811 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_812 = and(_T_810, _T_811) node _T_813 = or(UInt<1>(0h0), _T_812) node _T_814 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_815 = cvt(_T_814) node _T_816 = and(_T_815, asSInt(UInt<13>(0h1000))) node _T_817 = asSInt(_T_816) node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0))) node _T_819 = and(_T_813, _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<14>(0h2000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<11>(0h400))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<9>(0h100))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<18>(0h2f000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<27>(0h4000000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<13>(0h1000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_828, _T_833) node _T_865 = or(_T_864, _T_838) node _T_866 = or(_T_865, _T_843) node _T_867 = or(_T_866, _T_848) node _T_868 = or(_T_867, _T_853) node _T_869 = or(_T_868, _T_858) node _T_870 = or(_T_869, _T_863) node _T_871 = and(_T_823, _T_870) node _T_872 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_873 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<17>(0h10000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = and(_T_872, _T_877) node _T_879 = or(UInt<1>(0h0), _T_819) node _T_880 = or(_T_879, _T_871) node _T_881 = or(_T_880, _T_878) node _T_882 = and(_T_809, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_882, UInt<1>(0h1), "") : assert_26 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_892 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_892, UInt<1>(0h1), "") : assert_29 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_896, UInt<1>(0h1), "") : assert_30 node _T_900 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_905 = shr(io.in.a.bits.source, 2) node _T_906 = eq(_T_905, UInt<1>(0h0)) node _T_907 = leq(UInt<1>(0h0), uncommonBits_28) node _T_908 = and(_T_906, _T_907) node _T_909 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_910 = and(_T_908, _T_909) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_911 = shr(io.in.a.bits.source, 2) node _T_912 = eq(_T_911, UInt<1>(0h1)) node _T_913 = leq(UInt<1>(0h0), uncommonBits_29) node _T_914 = and(_T_912, _T_913) node _T_915 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_916 = and(_T_914, _T_915) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_917 = shr(io.in.a.bits.source, 2) node _T_918 = eq(_T_917, UInt<2>(0h2)) node _T_919 = leq(UInt<1>(0h0), uncommonBits_30) node _T_920 = and(_T_918, _T_919) node _T_921 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_922 = and(_T_920, _T_921) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_923 = shr(io.in.a.bits.source, 2) node _T_924 = eq(_T_923, UInt<2>(0h3)) node _T_925 = leq(UInt<1>(0h0), uncommonBits_31) node _T_926 = and(_T_924, _T_925) node _T_927 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_928 = and(_T_926, _T_927) node _T_929 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_930 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_931 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_932 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_933 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_934 = or(_T_904, _T_910) node _T_935 = or(_T_934, _T_916) node _T_936 = or(_T_935, _T_922) node _T_937 = or(_T_936, _T_928) node _T_938 = or(_T_937, _T_929) node _T_939 = or(_T_938, _T_930) node _T_940 = or(_T_939, _T_931) node _T_941 = or(_T_940, _T_932) node _T_942 = or(_T_941, _T_933) node _T_943 = and(_T_903, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_947 = and(_T_945, _T_946) node _T_948 = or(UInt<1>(0h0), _T_947) node _T_949 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_950 = cvt(_T_949) node _T_951 = and(_T_950, asSInt(UInt<13>(0h1000))) node _T_952 = asSInt(_T_951) node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0))) node _T_954 = and(_T_948, _T_953) node _T_955 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_956 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_957 = and(_T_955, _T_956) node _T_958 = or(UInt<1>(0h0), _T_957) node _T_959 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_960 = cvt(_T_959) node _T_961 = and(_T_960, asSInt(UInt<14>(0h2000))) node _T_962 = asSInt(_T_961) node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0))) node _T_964 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_965 = cvt(_T_964) node _T_966 = and(_T_965, asSInt(UInt<11>(0h400))) node _T_967 = asSInt(_T_966) node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0))) node _T_969 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_970 = cvt(_T_969) node _T_971 = and(_T_970, asSInt(UInt<9>(0h100))) node _T_972 = asSInt(_T_971) node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0))) node _T_974 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_975 = cvt(_T_974) node _T_976 = and(_T_975, asSInt(UInt<18>(0h2f000))) node _T_977 = asSInt(_T_976) node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0))) node _T_979 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<17>(0h10000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_985 = cvt(_T_984) node _T_986 = and(_T_985, asSInt(UInt<13>(0h1000))) node _T_987 = asSInt(_T_986) node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0))) node _T_989 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<27>(0h4000000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<13>(0h1000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = or(_T_963, _T_968) node _T_1000 = or(_T_999, _T_973) node _T_1001 = or(_T_1000, _T_978) node _T_1002 = or(_T_1001, _T_983) node _T_1003 = or(_T_1002, _T_988) node _T_1004 = or(_T_1003, _T_993) node _T_1005 = or(_T_1004, _T_998) node _T_1006 = and(_T_958, _T_1005) node _T_1007 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1008 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<17>(0h10000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = and(_T_1007, _T_1012) node _T_1014 = or(UInt<1>(0h0), _T_954) node _T_1015 = or(_T_1014, _T_1006) node _T_1016 = or(_T_1015, _T_1013) node _T_1017 = and(_T_944, _T_1016) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_31 node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(source_ok, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1027 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_34 node _T_1031 = not(mask) node _T_1032 = and(io.in.a.bits.mask, _T_1031) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_35 node _T_1037 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1039 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1042 = shr(io.in.a.bits.source, 2) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) node _T_1044 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1045 = and(_T_1043, _T_1044) node _T_1046 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1047 = and(_T_1045, _T_1046) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1048 = shr(io.in.a.bits.source, 2) node _T_1049 = eq(_T_1048, UInt<1>(0h1)) node _T_1050 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1053 = and(_T_1051, _T_1052) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<2>(0h2)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<2>(0h3)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _T_1066 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1071 = or(_T_1041, _T_1047) node _T_1072 = or(_T_1071, _T_1053) node _T_1073 = or(_T_1072, _T_1059) node _T_1074 = or(_T_1073, _T_1065) node _T_1075 = or(_T_1074, _T_1066) node _T_1076 = or(_T_1075, _T_1067) node _T_1077 = or(_T_1076, _T_1068) node _T_1078 = or(_T_1077, _T_1069) node _T_1079 = or(_T_1078, _T_1070) node _T_1080 = and(_T_1040, _T_1079) node _T_1081 = or(UInt<1>(0h0), _T_1080) node _T_1082 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1083 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<14>(0h2000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_1092 = cvt(_T_1091) node _T_1093 = and(_T_1092, asSInt(UInt<11>(0h400))) node _T_1094 = asSInt(_T_1093) node _T_1095 = eq(_T_1094, asSInt(UInt<1>(0h0))) node _T_1096 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_1097 = cvt(_T_1096) node _T_1098 = and(_T_1097, asSInt(UInt<9>(0h100))) node _T_1099 = asSInt(_T_1098) node _T_1100 = eq(_T_1099, asSInt(UInt<1>(0h0))) node _T_1101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1102 = cvt(_T_1101) node _T_1103 = and(_T_1102, asSInt(UInt<13>(0h1000))) node _T_1104 = asSInt(_T_1103) node _T_1105 = eq(_T_1104, asSInt(UInt<1>(0h0))) node _T_1106 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<18>(0h2f000))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1112 = cvt(_T_1111) node _T_1113 = and(_T_1112, asSInt(UInt<17>(0h10000))) node _T_1114 = asSInt(_T_1113) node _T_1115 = eq(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1117 = cvt(_T_1116) node _T_1118 = and(_T_1117, asSInt(UInt<13>(0h1000))) node _T_1119 = asSInt(_T_1118) node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0))) node _T_1121 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<27>(0h4000000))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1127 = cvt(_T_1126) node _T_1128 = and(_T_1127, asSInt(UInt<13>(0h1000))) node _T_1129 = asSInt(_T_1128) node _T_1130 = eq(_T_1129, asSInt(UInt<1>(0h0))) node _T_1131 = or(_T_1090, _T_1095) node _T_1132 = or(_T_1131, _T_1100) node _T_1133 = or(_T_1132, _T_1105) node _T_1134 = or(_T_1133, _T_1110) node _T_1135 = or(_T_1134, _T_1115) node _T_1136 = or(_T_1135, _T_1120) node _T_1137 = or(_T_1136, _T_1125) node _T_1138 = or(_T_1137, _T_1130) node _T_1139 = and(_T_1085, _T_1138) node _T_1140 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1141 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<17>(0h10000))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = and(_T_1140, _T_1145) node _T_1147 = or(UInt<1>(0h0), _T_1139) node _T_1148 = or(_T_1147, _T_1146) node _T_1149 = and(_T_1081, _T_1148) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_36 node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(source_ok, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(is_aligned, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1159 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_39 node _T_1163 = eq(io.in.a.bits.mask, mask) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_40 node _T_1167 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1167 : node _T_1168 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1169 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1170 = and(_T_1168, _T_1169) node _T_1171 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1172 = shr(io.in.a.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1178 = shr(io.in.a.bits.source, 2) node _T_1179 = eq(_T_1178, UInt<1>(0h1)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1184 = shr(io.in.a.bits.source, 2) node _T_1185 = eq(_T_1184, UInt<2>(0h2)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1190 = shr(io.in.a.bits.source, 2) node _T_1191 = eq(_T_1190, UInt<2>(0h3)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1200 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1201 = or(_T_1171, _T_1177) node _T_1202 = or(_T_1201, _T_1183) node _T_1203 = or(_T_1202, _T_1189) node _T_1204 = or(_T_1203, _T_1195) node _T_1205 = or(_T_1204, _T_1196) node _T_1206 = or(_T_1205, _T_1197) node _T_1207 = or(_T_1206, _T_1198) node _T_1208 = or(_T_1207, _T_1199) node _T_1209 = or(_T_1208, _T_1200) node _T_1210 = and(_T_1170, _T_1209) node _T_1211 = or(UInt<1>(0h0), _T_1210) node _T_1212 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1213 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = or(UInt<1>(0h0), _T_1214) node _T_1216 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1217 = cvt(_T_1216) node _T_1218 = and(_T_1217, asSInt(UInt<14>(0h2000))) node _T_1219 = asSInt(_T_1218) node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_1222 = cvt(_T_1221) node _T_1223 = and(_T_1222, asSInt(UInt<11>(0h400))) node _T_1224 = asSInt(_T_1223) node _T_1225 = eq(_T_1224, asSInt(UInt<1>(0h0))) node _T_1226 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_1227 = cvt(_T_1226) node _T_1228 = and(_T_1227, asSInt(UInt<9>(0h100))) node _T_1229 = asSInt(_T_1228) node _T_1230 = eq(_T_1229, asSInt(UInt<1>(0h0))) node _T_1231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1232 = cvt(_T_1231) node _T_1233 = and(_T_1232, asSInt(UInt<13>(0h1000))) node _T_1234 = asSInt(_T_1233) node _T_1235 = eq(_T_1234, asSInt(UInt<1>(0h0))) node _T_1236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1237 = cvt(_T_1236) node _T_1238 = and(_T_1237, asSInt(UInt<18>(0h2f000))) node _T_1239 = asSInt(_T_1238) node _T_1240 = eq(_T_1239, asSInt(UInt<1>(0h0))) node _T_1241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1242 = cvt(_T_1241) node _T_1243 = and(_T_1242, asSInt(UInt<17>(0h10000))) node _T_1244 = asSInt(_T_1243) node _T_1245 = eq(_T_1244, asSInt(UInt<1>(0h0))) node _T_1246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1247 = cvt(_T_1246) node _T_1248 = and(_T_1247, asSInt(UInt<13>(0h1000))) node _T_1249 = asSInt(_T_1248) node _T_1250 = eq(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1252 = cvt(_T_1251) node _T_1253 = and(_T_1252, asSInt(UInt<27>(0h4000000))) node _T_1254 = asSInt(_T_1253) node _T_1255 = eq(_T_1254, asSInt(UInt<1>(0h0))) node _T_1256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1257 = cvt(_T_1256) node _T_1258 = and(_T_1257, asSInt(UInt<13>(0h1000))) node _T_1259 = asSInt(_T_1258) node _T_1260 = eq(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = or(_T_1220, _T_1225) node _T_1262 = or(_T_1261, _T_1230) node _T_1263 = or(_T_1262, _T_1235) node _T_1264 = or(_T_1263, _T_1240) node _T_1265 = or(_T_1264, _T_1245) node _T_1266 = or(_T_1265, _T_1250) node _T_1267 = or(_T_1266, _T_1255) node _T_1268 = or(_T_1267, _T_1260) node _T_1269 = and(_T_1215, _T_1268) node _T_1270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1271 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1272 = cvt(_T_1271) node _T_1273 = and(_T_1272, asSInt(UInt<17>(0h10000))) node _T_1274 = asSInt(_T_1273) node _T_1275 = eq(_T_1274, asSInt(UInt<1>(0h0))) node _T_1276 = and(_T_1270, _T_1275) node _T_1277 = or(UInt<1>(0h0), _T_1269) node _T_1278 = or(_T_1277, _T_1276) node _T_1279 = and(_T_1211, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_41 node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(source_ok, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(is_aligned, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1289 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_44 node _T_1293 = eq(io.in.a.bits.mask, mask) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_45 node _T_1297 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1297 : node _T_1298 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1299 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1300 = and(_T_1298, _T_1299) node _T_1301 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1302 = shr(io.in.a.bits.source, 2) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1307 = and(_T_1305, _T_1306) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1308 = shr(io.in.a.bits.source, 2) node _T_1309 = eq(_T_1308, UInt<1>(0h1)) node _T_1310 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1313 = and(_T_1311, _T_1312) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1314 = shr(io.in.a.bits.source, 2) node _T_1315 = eq(_T_1314, UInt<2>(0h2)) node _T_1316 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1317 = and(_T_1315, _T_1316) node _T_1318 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1319 = and(_T_1317, _T_1318) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1320 = shr(io.in.a.bits.source, 2) node _T_1321 = eq(_T_1320, UInt<2>(0h3)) node _T_1322 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_1327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1330 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1331 = or(_T_1301, _T_1307) node _T_1332 = or(_T_1331, _T_1313) node _T_1333 = or(_T_1332, _T_1319) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = or(_T_1334, _T_1326) node _T_1336 = or(_T_1335, _T_1327) node _T_1337 = or(_T_1336, _T_1328) node _T_1338 = or(_T_1337, _T_1329) node _T_1339 = or(_T_1338, _T_1330) node _T_1340 = and(_T_1300, _T_1339) node _T_1341 = or(UInt<1>(0h0), _T_1340) node _T_1342 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1343 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1344 = and(_T_1342, _T_1343) node _T_1345 = or(UInt<1>(0h0), _T_1344) node _T_1346 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1347 = cvt(_T_1346) node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000))) node _T_1349 = asSInt(_T_1348) node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0))) node _T_1351 = and(_T_1345, _T_1350) node _T_1352 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1353 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1354 = cvt(_T_1353) node _T_1355 = and(_T_1354, asSInt(UInt<14>(0h2000))) node _T_1356 = asSInt(_T_1355) node _T_1357 = eq(_T_1356, asSInt(UInt<1>(0h0))) node _T_1358 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_1359 = cvt(_T_1358) node _T_1360 = and(_T_1359, asSInt(UInt<11>(0h400))) node _T_1361 = asSInt(_T_1360) node _T_1362 = eq(_T_1361, asSInt(UInt<1>(0h0))) node _T_1363 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_1364 = cvt(_T_1363) node _T_1365 = and(_T_1364, asSInt(UInt<9>(0h100))) node _T_1366 = asSInt(_T_1365) node _T_1367 = eq(_T_1366, asSInt(UInt<1>(0h0))) node _T_1368 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1369 = cvt(_T_1368) node _T_1370 = and(_T_1369, asSInt(UInt<17>(0h10000))) node _T_1371 = asSInt(_T_1370) node _T_1372 = eq(_T_1371, asSInt(UInt<1>(0h0))) node _T_1373 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1374 = cvt(_T_1373) node _T_1375 = and(_T_1374, asSInt(UInt<18>(0h2f000))) node _T_1376 = asSInt(_T_1375) node _T_1377 = eq(_T_1376, asSInt(UInt<1>(0h0))) node _T_1378 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1379 = cvt(_T_1378) node _T_1380 = and(_T_1379, asSInt(UInt<17>(0h10000))) node _T_1381 = asSInt(_T_1380) node _T_1382 = eq(_T_1381, asSInt(UInt<1>(0h0))) node _T_1383 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1384 = cvt(_T_1383) node _T_1385 = and(_T_1384, asSInt(UInt<13>(0h1000))) node _T_1386 = asSInt(_T_1385) node _T_1387 = eq(_T_1386, asSInt(UInt<1>(0h0))) node _T_1388 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1389 = cvt(_T_1388) node _T_1390 = and(_T_1389, asSInt(UInt<27>(0h4000000))) node _T_1391 = asSInt(_T_1390) node _T_1392 = eq(_T_1391, asSInt(UInt<1>(0h0))) node _T_1393 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1394 = cvt(_T_1393) node _T_1395 = and(_T_1394, asSInt(UInt<13>(0h1000))) node _T_1396 = asSInt(_T_1395) node _T_1397 = eq(_T_1396, asSInt(UInt<1>(0h0))) node _T_1398 = or(_T_1357, _T_1362) node _T_1399 = or(_T_1398, _T_1367) node _T_1400 = or(_T_1399, _T_1372) node _T_1401 = or(_T_1400, _T_1377) node _T_1402 = or(_T_1401, _T_1382) node _T_1403 = or(_T_1402, _T_1387) node _T_1404 = or(_T_1403, _T_1392) node _T_1405 = or(_T_1404, _T_1397) node _T_1406 = and(_T_1352, _T_1405) node _T_1407 = or(UInt<1>(0h0), _T_1351) node _T_1408 = or(_T_1407, _T_1406) node _T_1409 = and(_T_1341, _T_1408) node _T_1410 = asUInt(reset) node _T_1411 = eq(_T_1410, UInt<1>(0h0)) when _T_1411 : node _T_1412 = eq(_T_1409, UInt<1>(0h0)) when _T_1412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1409, UInt<1>(0h1), "") : assert_46 node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(source_ok, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(is_aligned, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1419 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(_T_1419, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1419, UInt<1>(0h1), "") : assert_49 node _T_1423 = eq(io.in.a.bits.mask, mask) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_50 node _T_1427 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1431 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_52 node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_38 connect _source_ok_WIRE_1[1], _source_ok_T_44 connect _source_ok_WIRE_1[2], _source_ok_T_50 connect _source_ok_WIRE_1[3], _source_ok_T_56 connect _source_ok_WIRE_1[4], _source_ok_T_62 connect _source_ok_WIRE_1[5], _source_ok_T_63 connect _source_ok_WIRE_1[6], _source_ok_T_64 connect _source_ok_WIRE_1[7], _source_ok_T_65 connect _source_ok_WIRE_1[8], _source_ok_T_66 connect _source_ok_WIRE_1[9], _source_ok_T_67 node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1435 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1435 : node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(source_ok_1, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1439 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_54 node _T_1443 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_55 node _T_1447 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_56 node _T_1451 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_57 node _T_1455 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1455 : node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(source_ok_1, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(sink_ok, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1462 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_60 node _T_1466 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_61 node _T_1470 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_62 node _T_1474 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_63 node _T_1478 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1479 = or(UInt<1>(0h1), _T_1478) node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(_T_1479, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1479, UInt<1>(0h1), "") : assert_64 node _T_1483 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1483 : node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(source_ok_1, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(sink_ok, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1490 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1491 = asUInt(reset) node _T_1492 = eq(_T_1491, UInt<1>(0h0)) when _T_1492 : node _T_1493 = eq(_T_1490, UInt<1>(0h0)) when _T_1493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1490, UInt<1>(0h1), "") : assert_67 node _T_1494 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_68 node _T_1498 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_69 node _T_1502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1503 = or(_T_1502, io.in.d.bits.corrupt) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_70 node _T_1507 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1508 = or(UInt<1>(0h1), _T_1507) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_71 node _T_1512 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1512 : node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(source_ok_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1516 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_73 node _T_1520 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_74 node _T_1524 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1525 = or(UInt<1>(0h1), _T_1524) node _T_1526 = asUInt(reset) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) when _T_1527 : node _T_1528 = eq(_T_1525, UInt<1>(0h0)) when _T_1528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1525, UInt<1>(0h1), "") : assert_75 node _T_1529 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1529 : node _T_1530 = asUInt(reset) node _T_1531 = eq(_T_1530, UInt<1>(0h0)) when _T_1531 : node _T_1532 = eq(source_ok_1, UInt<1>(0h0)) when _T_1532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1533 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_77 node _T_1537 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1538 = or(_T_1537, io.in.d.bits.corrupt) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_78 node _T_1542 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1543 = or(UInt<1>(0h1), _T_1542) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_79 node _T_1547 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1547 : node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(source_ok_1, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1551 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_81 node _T_1555 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_82 node _T_1559 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1560 = or(UInt<1>(0h1), _T_1559) node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(_T_1560, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1560, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1564 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(_T_1564, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1564, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1568 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1572 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1576 = eq(a_first, UInt<1>(0h0)) node _T_1577 = and(io.in.a.valid, _T_1576) when _T_1577 : node _T_1578 = eq(io.in.a.bits.opcode, opcode) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_87 node _T_1582 = eq(io.in.a.bits.param, param) node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(_T_1582, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1582, UInt<1>(0h1), "") : assert_88 node _T_1586 = eq(io.in.a.bits.size, size) node _T_1587 = asUInt(reset) node _T_1588 = eq(_T_1587, UInt<1>(0h0)) when _T_1588 : node _T_1589 = eq(_T_1586, UInt<1>(0h0)) when _T_1589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1586, UInt<1>(0h1), "") : assert_89 node _T_1590 = eq(io.in.a.bits.source, source) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_90 node _T_1594 = eq(io.in.a.bits.address, address) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_91 node _T_1598 = and(io.in.a.ready, io.in.a.valid) node _T_1599 = and(_T_1598, a_first) when _T_1599 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1600 = eq(d_first, UInt<1>(0h0)) node _T_1601 = and(io.in.d.valid, _T_1600) when _T_1601 : node _T_1602 = eq(io.in.d.bits.opcode, opcode_1) node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(_T_1602, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1602, UInt<1>(0h1), "") : assert_92 node _T_1606 = eq(io.in.d.bits.param, param_1) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_93 node _T_1610 = eq(io.in.d.bits.size, size_1) node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(_T_1610, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1610, UInt<1>(0h1), "") : assert_94 node _T_1614 = eq(io.in.d.bits.source, source_1) node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(_T_1614, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1614, UInt<1>(0h1), "") : assert_95 node _T_1618 = eq(io.in.d.bits.sink, sink) node _T_1619 = asUInt(reset) node _T_1620 = eq(_T_1619, UInt<1>(0h0)) when _T_1620 : node _T_1621 = eq(_T_1618, UInt<1>(0h0)) when _T_1621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1618, UInt<1>(0h1), "") : assert_96 node _T_1622 = eq(io.in.d.bits.denied, denied) node _T_1623 = asUInt(reset) node _T_1624 = eq(_T_1623, UInt<1>(0h0)) when _T_1624 : node _T_1625 = eq(_T_1622, UInt<1>(0h0)) when _T_1625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1622, UInt<1>(0h1), "") : assert_97 node _T_1626 = and(io.in.d.ready, io.in.d.valid) node _T_1627 = and(_T_1626, d_first) when _T_1627 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1628 = and(io.in.a.valid, a_first_1) node _T_1629 = and(_T_1628, UInt<1>(0h1)) when _T_1629 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1630 = and(io.in.a.ready, io.in.a.valid) node _T_1631 = and(_T_1630, a_first_1) node _T_1632 = and(_T_1631, UInt<1>(0h1)) when _T_1632 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1633 = dshr(inflight, io.in.a.bits.source) node _T_1634 = bits(_T_1633, 0, 0) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(_T_1635, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1635, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1639 = and(io.in.d.valid, d_first_1) node _T_1640 = and(_T_1639, UInt<1>(0h1)) node _T_1641 = eq(d_release_ack, UInt<1>(0h0)) node _T_1642 = and(_T_1640, _T_1641) when _T_1642 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1643 = and(io.in.d.ready, io.in.d.valid) node _T_1644 = and(_T_1643, d_first_1) node _T_1645 = and(_T_1644, UInt<1>(0h1)) node _T_1646 = eq(d_release_ack, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1648 = and(io.in.d.valid, d_first_1) node _T_1649 = and(_T_1648, UInt<1>(0h1)) node _T_1650 = eq(d_release_ack, UInt<1>(0h0)) node _T_1651 = and(_T_1649, _T_1650) when _T_1651 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1652 = dshr(inflight, io.in.d.bits.source) node _T_1653 = bits(_T_1652, 0, 0) node _T_1654 = or(_T_1653, same_cycle_resp) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1658 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1659 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1660 = or(_T_1658, _T_1659) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_100 node _T_1664 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_101 else : node _T_1668 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1669 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1670 = or(_T_1668, _T_1669) node _T_1671 = asUInt(reset) node _T_1672 = eq(_T_1671, UInt<1>(0h0)) when _T_1672 : node _T_1673 = eq(_T_1670, UInt<1>(0h0)) when _T_1673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1670, UInt<1>(0h1), "") : assert_102 node _T_1674 = eq(io.in.d.bits.size, a_size_lookup) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_103 node _T_1678 = and(io.in.d.valid, d_first_1) node _T_1679 = and(_T_1678, a_first_1) node _T_1680 = and(_T_1679, io.in.a.valid) node _T_1681 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = eq(d_release_ack, UInt<1>(0h0)) node _T_1684 = and(_T_1682, _T_1683) when _T_1684 : node _T_1685 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1686 = or(_T_1685, io.in.a.ready) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_104 node _T_1690 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1691 = orr(a_set_wo_ready) node _T_1692 = eq(_T_1691, UInt<1>(0h0)) node _T_1693 = or(_T_1690, _T_1692) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_38 node _T_1697 = orr(inflight) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) node _T_1699 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1700 = or(_T_1698, _T_1699) node _T_1701 = lt(watchdog, plusarg_reader.out) node _T_1702 = or(_T_1700, _T_1701) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1706 = and(io.in.a.ready, io.in.a.valid) node _T_1707 = and(io.in.d.ready, io.in.d.valid) node _T_1708 = or(_T_1706, _T_1707) when _T_1708 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1709 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1710 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1711 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1712 = and(_T_1710, _T_1711) node _T_1713 = and(_T_1709, _T_1712) when _T_1713 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1714 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1715 = and(_T_1714, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1716 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1717 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1718 = and(_T_1716, _T_1717) node _T_1719 = and(_T_1715, _T_1718) when _T_1719 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1720 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1721 = bits(_T_1720, 0, 0) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(_T_1722, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1722, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1726 = and(io.in.d.valid, d_first_2) node _T_1727 = and(_T_1726, UInt<1>(0h1)) node _T_1728 = and(_T_1727, d_release_ack_1) when _T_1728 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1729 = and(io.in.d.ready, io.in.d.valid) node _T_1730 = and(_T_1729, d_first_2) node _T_1731 = and(_T_1730, UInt<1>(0h1)) node _T_1732 = and(_T_1731, d_release_ack_1) when _T_1732 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1733 = and(io.in.d.valid, d_first_2) node _T_1734 = and(_T_1733, UInt<1>(0h1)) node _T_1735 = and(_T_1734, d_release_ack_1) when _T_1735 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1736 = dshr(inflight_1, io.in.d.bits.source) node _T_1737 = bits(_T_1736, 0, 0) node _T_1738 = or(_T_1737, same_cycle_resp_1) node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(_T_1738, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1738, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1742 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(_T_1742, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1742, UInt<1>(0h1), "") : assert_109 else : node _T_1746 = eq(io.in.d.bits.size, c_size_lookup) node _T_1747 = asUInt(reset) node _T_1748 = eq(_T_1747, UInt<1>(0h0)) when _T_1748 : node _T_1749 = eq(_T_1746, UInt<1>(0h0)) when _T_1749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1746, UInt<1>(0h1), "") : assert_110 node _T_1750 = and(io.in.d.valid, d_first_2) node _T_1751 = and(_T_1750, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1752 = and(_T_1751, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1753 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1754 = and(_T_1752, _T_1753) node _T_1755 = and(_T_1754, d_release_ack_1) node _T_1756 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1757 = and(_T_1755, _T_1756) when _T_1757 : node _T_1758 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1759 = or(_T_1758, _WIRE_27.ready) node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(_T_1759, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1759, UInt<1>(0h1), "") : assert_111 node _T_1763 = orr(c_set_wo_ready) when _T_1763 : node _T_1764 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1765 = asUInt(reset) node _T_1766 = eq(_T_1765, UInt<1>(0h0)) when _T_1766 : node _T_1767 = eq(_T_1764, UInt<1>(0h0)) when _T_1767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1764, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_39 node _T_1768 = orr(inflight_1) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = lt(watchdog_1, plusarg_reader_1.out) node _T_1773 = or(_T_1771, _T_1772) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1777 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1778 = and(io.in.d.ready, io.in.d.valid) node _T_1779 = or(_T_1777, _T_1778) when _T_1779 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_1 : output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51) node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0)) node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1) connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2 connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RecFNToRecFN_1( // @[RecFNToRecFN.scala:44:5] input [64:0] io_in, // @[RecFNToRecFN.scala:48:16] input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out, // @[RecFNToRecFN.scala:48:16] output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16] ); wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (rawIn_isNaN & ~(io_in[51])), // @[rawFloatFromRecFN.scala:56:33] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:56:33] .io_in_isInf ((&(io_in[63:62])) & ~(io_in[61])), // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}] .io_in_isZero (~(|(io_in[63:61]))), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}] .io_in_sign (io_in[64]), // @[rawFloatFromRecFN.scala:59:25] .io_in_sExp ({1'h0, io_in[63:52]}), // @[rawFloatFromRecFN.scala:51:21, :60:27] .io_in_sig ({1'h0, |(io_in[63:61]), io_in[51:0]}), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}] .io_roundingMode (io_roundingMode), .io_out (io_out), .io_exceptionFlags (io_exceptionFlags) ); // @[RecFNToRecFN.scala:72:19] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BoomMSHRFile : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}[1], flip req_is_probe : UInt<1>[1], resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, secondary_miss : UInt<1>[1], block_hit : UInt<1>[1], flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, prefetch : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<2>, param : UInt<3>, way_en : UInt<4>, voluntary : UInt<1>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, flip clear_all : UInt<1>, flip wb_resp : UInt<1>, fence_rdy : UInt<1>, probe_rdy : UInt<1>} wire req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}} connect req.bits, io.req[0].bits connect req.valid, io.req[0].valid connect req.ready, io.req[0].ready connect io.req[0].ready, UInt<1>(0h0) inst prefetcher of NullPrefetcher connect prefetcher.clock, clock connect prefetcher.reset, reset connect io.prefetch.bits, prefetcher.io.prefetch.bits connect io.prefetch.valid, prefetcher.io.prefetch.valid connect prefetcher.io.prefetch.ready, io.prefetch.ready node _cacheable_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _cacheable_T_1 = xor(req.bits.addr, UInt<1>(0h0)) node _cacheable_T_2 = cvt(_cacheable_T_1) node _cacheable_T_3 = and(_cacheable_T_2, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_4 = asSInt(_cacheable_T_3) node _cacheable_T_5 = eq(_cacheable_T_4, asSInt(UInt<1>(0h0))) node _cacheable_T_6 = xor(req.bits.addr, UInt<17>(0h10000)) node _cacheable_T_7 = cvt(_cacheable_T_6) node _cacheable_T_8 = and(_cacheable_T_7, asSInt(UInt<33>(0h8c011000))) node _cacheable_T_9 = asSInt(_cacheable_T_8) node _cacheable_T_10 = eq(_cacheable_T_9, asSInt(UInt<1>(0h0))) node _cacheable_T_11 = xor(req.bits.addr, UInt<28>(0hc000000)) node _cacheable_T_12 = cvt(_cacheable_T_11) node _cacheable_T_13 = and(_cacheable_T_12, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_14 = asSInt(_cacheable_T_13) node _cacheable_T_15 = eq(_cacheable_T_14, asSInt(UInt<1>(0h0))) node _cacheable_T_16 = or(_cacheable_T_5, _cacheable_T_10) node _cacheable_T_17 = or(_cacheable_T_16, _cacheable_T_15) node _cacheable_T_18 = and(_cacheable_T, _cacheable_T_17) node _cacheable_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _cacheable_T_20 = or(UInt<1>(0h0), _cacheable_T_19) node _cacheable_T_21 = xor(req.bits.addr, UInt<28>(0h8000000)) node _cacheable_T_22 = cvt(_cacheable_T_21) node _cacheable_T_23 = and(_cacheable_T_22, asSInt(UInt<33>(0h8c010000))) node _cacheable_T_24 = asSInt(_cacheable_T_23) node _cacheable_T_25 = eq(_cacheable_T_24, asSInt(UInt<1>(0h0))) node _cacheable_T_26 = xor(req.bits.addr, UInt<32>(0h80000000)) node _cacheable_T_27 = cvt(_cacheable_T_26) node _cacheable_T_28 = and(_cacheable_T_27, asSInt(UInt<33>(0h80000000))) node _cacheable_T_29 = asSInt(_cacheable_T_28) node _cacheable_T_30 = eq(_cacheable_T_29, asSInt(UInt<1>(0h0))) node _cacheable_T_31 = or(_cacheable_T_25, _cacheable_T_30) node _cacheable_T_32 = and(_cacheable_T_20, _cacheable_T_31) node _cacheable_T_33 = or(UInt<1>(0h0), _cacheable_T_18) node cacheable = or(_cacheable_T_33, _cacheable_T_32) regreset sdq_val : UInt<17>, clock, reset, UInt<17>(0h0) node _sdq_alloc_id_T = bits(sdq_val, 16, 0) node _sdq_alloc_id_T_1 = not(_sdq_alloc_id_T) node _sdq_alloc_id_T_2 = bits(_sdq_alloc_id_T_1, 0, 0) node _sdq_alloc_id_T_3 = bits(_sdq_alloc_id_T_1, 1, 1) node _sdq_alloc_id_T_4 = bits(_sdq_alloc_id_T_1, 2, 2) node _sdq_alloc_id_T_5 = bits(_sdq_alloc_id_T_1, 3, 3) node _sdq_alloc_id_T_6 = bits(_sdq_alloc_id_T_1, 4, 4) node _sdq_alloc_id_T_7 = bits(_sdq_alloc_id_T_1, 5, 5) node _sdq_alloc_id_T_8 = bits(_sdq_alloc_id_T_1, 6, 6) node _sdq_alloc_id_T_9 = bits(_sdq_alloc_id_T_1, 7, 7) node _sdq_alloc_id_T_10 = bits(_sdq_alloc_id_T_1, 8, 8) node _sdq_alloc_id_T_11 = bits(_sdq_alloc_id_T_1, 9, 9) node _sdq_alloc_id_T_12 = bits(_sdq_alloc_id_T_1, 10, 10) node _sdq_alloc_id_T_13 = bits(_sdq_alloc_id_T_1, 11, 11) node _sdq_alloc_id_T_14 = bits(_sdq_alloc_id_T_1, 12, 12) node _sdq_alloc_id_T_15 = bits(_sdq_alloc_id_T_1, 13, 13) node _sdq_alloc_id_T_16 = bits(_sdq_alloc_id_T_1, 14, 14) node _sdq_alloc_id_T_17 = bits(_sdq_alloc_id_T_1, 15, 15) node _sdq_alloc_id_T_18 = bits(_sdq_alloc_id_T_1, 16, 16) node _sdq_alloc_id_T_19 = mux(_sdq_alloc_id_T_17, UInt<4>(0hf), UInt<5>(0h10)) node _sdq_alloc_id_T_20 = mux(_sdq_alloc_id_T_16, UInt<4>(0he), _sdq_alloc_id_T_19) node _sdq_alloc_id_T_21 = mux(_sdq_alloc_id_T_15, UInt<4>(0hd), _sdq_alloc_id_T_20) node _sdq_alloc_id_T_22 = mux(_sdq_alloc_id_T_14, UInt<4>(0hc), _sdq_alloc_id_T_21) node _sdq_alloc_id_T_23 = mux(_sdq_alloc_id_T_13, UInt<4>(0hb), _sdq_alloc_id_T_22) node _sdq_alloc_id_T_24 = mux(_sdq_alloc_id_T_12, UInt<4>(0ha), _sdq_alloc_id_T_23) node _sdq_alloc_id_T_25 = mux(_sdq_alloc_id_T_11, UInt<4>(0h9), _sdq_alloc_id_T_24) node _sdq_alloc_id_T_26 = mux(_sdq_alloc_id_T_10, UInt<4>(0h8), _sdq_alloc_id_T_25) node _sdq_alloc_id_T_27 = mux(_sdq_alloc_id_T_9, UInt<3>(0h7), _sdq_alloc_id_T_26) node _sdq_alloc_id_T_28 = mux(_sdq_alloc_id_T_8, UInt<3>(0h6), _sdq_alloc_id_T_27) node _sdq_alloc_id_T_29 = mux(_sdq_alloc_id_T_7, UInt<3>(0h5), _sdq_alloc_id_T_28) node _sdq_alloc_id_T_30 = mux(_sdq_alloc_id_T_6, UInt<3>(0h4), _sdq_alloc_id_T_29) node _sdq_alloc_id_T_31 = mux(_sdq_alloc_id_T_5, UInt<2>(0h3), _sdq_alloc_id_T_30) node _sdq_alloc_id_T_32 = mux(_sdq_alloc_id_T_4, UInt<2>(0h2), _sdq_alloc_id_T_31) node _sdq_alloc_id_T_33 = mux(_sdq_alloc_id_T_3, UInt<1>(0h1), _sdq_alloc_id_T_32) node sdq_alloc_id = mux(_sdq_alloc_id_T_2, UInt<1>(0h0), _sdq_alloc_id_T_33) node _sdq_rdy_T = andr(sdq_val) node sdq_rdy = eq(_sdq_rdy_T, UInt<1>(0h0)) node _sdq_enq_T = and(req.ready, req.valid) node _sdq_enq_T_1 = and(_sdq_enq_T, cacheable) node _sdq_enq_T_2 = eq(req.bits.uop.mem_cmd, UInt<1>(0h1)) node _sdq_enq_T_3 = eq(req.bits.uop.mem_cmd, UInt<5>(0h11)) node _sdq_enq_T_4 = or(_sdq_enq_T_2, _sdq_enq_T_3) node _sdq_enq_T_5 = eq(req.bits.uop.mem_cmd, UInt<3>(0h7)) node _sdq_enq_T_6 = or(_sdq_enq_T_4, _sdq_enq_T_5) node _sdq_enq_T_7 = eq(req.bits.uop.mem_cmd, UInt<3>(0h4)) node _sdq_enq_T_8 = eq(req.bits.uop.mem_cmd, UInt<4>(0h9)) node _sdq_enq_T_9 = eq(req.bits.uop.mem_cmd, UInt<4>(0ha)) node _sdq_enq_T_10 = eq(req.bits.uop.mem_cmd, UInt<4>(0hb)) node _sdq_enq_T_11 = or(_sdq_enq_T_7, _sdq_enq_T_8) node _sdq_enq_T_12 = or(_sdq_enq_T_11, _sdq_enq_T_9) node _sdq_enq_T_13 = or(_sdq_enq_T_12, _sdq_enq_T_10) node _sdq_enq_T_14 = eq(req.bits.uop.mem_cmd, UInt<4>(0h8)) node _sdq_enq_T_15 = eq(req.bits.uop.mem_cmd, UInt<4>(0hc)) node _sdq_enq_T_16 = eq(req.bits.uop.mem_cmd, UInt<4>(0hd)) node _sdq_enq_T_17 = eq(req.bits.uop.mem_cmd, UInt<4>(0he)) node _sdq_enq_T_18 = eq(req.bits.uop.mem_cmd, UInt<4>(0hf)) node _sdq_enq_T_19 = or(_sdq_enq_T_14, _sdq_enq_T_15) node _sdq_enq_T_20 = or(_sdq_enq_T_19, _sdq_enq_T_16) node _sdq_enq_T_21 = or(_sdq_enq_T_20, _sdq_enq_T_17) node _sdq_enq_T_22 = or(_sdq_enq_T_21, _sdq_enq_T_18) node _sdq_enq_T_23 = or(_sdq_enq_T_13, _sdq_enq_T_22) node _sdq_enq_T_24 = or(_sdq_enq_T_6, _sdq_enq_T_23) node sdq_enq = and(_sdq_enq_T_1, _sdq_enq_T_24) cmem sdq : UInt<64> [17] when sdq_enq : infer mport MPORT = sdq[sdq_alloc_id], clock connect MPORT, req.bits.data reg lb : UInt<64>[8][2], clock wire idx_matches : UInt<1>[2][1] wire tag_matches : UInt<1>[2][1] wire way_matches : UInt<1>[2][1] node _tag_match_T = mux(idx_matches[0][0], tag_matches[0][0], UInt<1>(0h0)) node _tag_match_T_1 = mux(idx_matches[0][1], tag_matches[0][1], UInt<1>(0h0)) node _tag_match_T_2 = or(_tag_match_T, _tag_match_T_1) wire _tag_match_WIRE : UInt<1> connect _tag_match_WIRE, _tag_match_T_2 wire tag_match : UInt<1>[1] connect tag_match[0], _tag_match_WIRE node _idx_match_T = or(idx_matches[0][0], idx_matches[0][1]) wire idx_match : UInt<1>[1] connect idx_match[0], _idx_match_T node _way_match_T = mux(idx_matches[0][0], way_matches[0][0], UInt<1>(0h0)) node _way_match_T_1 = mux(idx_matches[0][1], way_matches[0][1], UInt<1>(0h0)) node _way_match_T_2 = or(_way_match_T, _way_match_T_1) wire _way_match_WIRE : UInt<1> connect _way_match_WIRE, _way_match_T_2 wire way_match : UInt<1>[1] connect way_match[0], _way_match_WIRE wire wb_tag_list : UInt<20>[2] inst meta_write_arb of Arbiter2_L1MetaWriteReq connect meta_write_arb.clock, clock connect meta_write_arb.reset, reset inst meta_read_arb of Arbiter2_L1MetaReadReq connect meta_read_arb.clock, clock connect meta_read_arb.reset, reset inst wb_req_arb of Arbiter2_WritebackReq connect wb_req_arb.clock, clock connect wb_req_arb.reset, reset inst replay_arb of Arbiter2_BoomDCacheReqInternal connect replay_arb.clock, clock connect replay_arb.reset, reset inst resp_arb of Arbiter3_BoomDCacheResp connect resp_arb.clock, clock connect resp_arb.reset, reset inst refill_arb of Arbiter2_L1DataWriteReq connect refill_arb.clock, clock connect refill_arb.reset, reset wire commit_vals : UInt<1>[2] wire commit_addrs : UInt<40>[2] wire commit_cohs : { state : UInt<2>}[2] connect io.fence_rdy, UInt<1>(0h1) connect io.probe_rdy, UInt<1>(0h1) connect io.mem_grant.ready, UInt<1>(0h0) wire mshr_alloc_idx : UInt wire pri_rdy : UInt<1> connect pri_rdy, UInt<1>(0h0) node _pri_val_T = and(req.valid, sdq_rdy) node _pri_val_T_1 = and(_pri_val_T, cacheable) node _pri_val_T_2 = eq(idx_match[0], UInt<1>(0h0)) node pri_val = and(_pri_val_T_1, _pri_val_T_2) inst mshrs_0 of BoomMSHR connect mshrs_0.clock, clock connect mshrs_0.reset, reset connect mshrs_0.io.id, UInt<1>(0h0) node _idx_matches_0_0_T = bits(io.req[0].bits.addr, 11, 6) node _idx_matches_0_0_T_1 = eq(mshrs_0.io.idx.bits, _idx_matches_0_0_T) node _idx_matches_0_0_T_2 = and(mshrs_0.io.idx.valid, _idx_matches_0_0_T_1) connect idx_matches[0][0], _idx_matches_0_0_T_2 node _tag_matches_0_0_T = shr(io.req[0].bits.addr, 12) node _tag_matches_0_0_T_1 = eq(mshrs_0.io.tag.bits, _tag_matches_0_0_T) node _tag_matches_0_0_T_2 = and(mshrs_0.io.tag.valid, _tag_matches_0_0_T_1) connect tag_matches[0][0], _tag_matches_0_0_T_2 node _way_matches_0_0_T = eq(mshrs_0.io.way.bits, io.req[0].bits.way_en) node _way_matches_0_0_T_1 = and(mshrs_0.io.way.valid, _way_matches_0_0_T) connect way_matches[0][0], _way_matches_0_0_T_1 connect wb_tag_list[0], mshrs_0.io.wb_req.bits.tag node _mshr_io_req_pri_val_T = eq(UInt<1>(0h0), mshr_alloc_idx) node _mshr_io_req_pri_val_T_1 = and(_mshr_io_req_pri_val_T, pri_val) connect mshrs_0.io.req_pri_val, _mshr_io_req_pri_val_T_1 node _T = eq(UInt<1>(0h0), mshr_alloc_idx) when _T : connect pri_rdy, mshrs_0.io.req_pri_rdy node _mshr_io_req_sec_val_T = and(req.valid, sdq_rdy) node _mshr_io_req_sec_val_T_1 = and(_mshr_io_req_sec_val_T, tag_match[0]) node _mshr_io_req_sec_val_T_2 = and(_mshr_io_req_sec_val_T_1, idx_matches[0][0]) node _mshr_io_req_sec_val_T_3 = and(_mshr_io_req_sec_val_T_2, cacheable) connect mshrs_0.io.req_sec_val, _mshr_io_req_sec_val_T_3 connect mshrs_0.io.req.sdq_id, req.bits.sdq_id connect mshrs_0.io.req.way_en, req.bits.way_en connect mshrs_0.io.req.old_meta.tag, req.bits.old_meta.tag connect mshrs_0.io.req.old_meta.coh.state, req.bits.old_meta.coh.state connect mshrs_0.io.req.tag_match, req.bits.tag_match connect mshrs_0.io.req.is_hella, req.bits.is_hella connect mshrs_0.io.req.data, req.bits.data connect mshrs_0.io.req.addr, req.bits.addr connect mshrs_0.io.req.uop.debug_tsrc, req.bits.uop.debug_tsrc connect mshrs_0.io.req.uop.debug_fsrc, req.bits.uop.debug_fsrc connect mshrs_0.io.req.uop.bp_xcpt_if, req.bits.uop.bp_xcpt_if connect mshrs_0.io.req.uop.bp_debug_if, req.bits.uop.bp_debug_if connect mshrs_0.io.req.uop.xcpt_ma_if, req.bits.uop.xcpt_ma_if connect mshrs_0.io.req.uop.xcpt_ae_if, req.bits.uop.xcpt_ae_if connect mshrs_0.io.req.uop.xcpt_pf_if, req.bits.uop.xcpt_pf_if connect mshrs_0.io.req.uop.fp_typ, req.bits.uop.fp_typ connect mshrs_0.io.req.uop.fp_rm, req.bits.uop.fp_rm connect mshrs_0.io.req.uop.fp_val, req.bits.uop.fp_val connect mshrs_0.io.req.uop.fcn_op, req.bits.uop.fcn_op connect mshrs_0.io.req.uop.fcn_dw, req.bits.uop.fcn_dw connect mshrs_0.io.req.uop.frs3_en, req.bits.uop.frs3_en connect mshrs_0.io.req.uop.lrs2_rtype, req.bits.uop.lrs2_rtype connect mshrs_0.io.req.uop.lrs1_rtype, req.bits.uop.lrs1_rtype connect mshrs_0.io.req.uop.dst_rtype, req.bits.uop.dst_rtype connect mshrs_0.io.req.uop.lrs3, req.bits.uop.lrs3 connect mshrs_0.io.req.uop.lrs2, req.bits.uop.lrs2 connect mshrs_0.io.req.uop.lrs1, req.bits.uop.lrs1 connect mshrs_0.io.req.uop.ldst, req.bits.uop.ldst connect mshrs_0.io.req.uop.ldst_is_rs1, req.bits.uop.ldst_is_rs1 connect mshrs_0.io.req.uop.csr_cmd, req.bits.uop.csr_cmd connect mshrs_0.io.req.uop.flush_on_commit, req.bits.uop.flush_on_commit connect mshrs_0.io.req.uop.is_unique, req.bits.uop.is_unique connect mshrs_0.io.req.uop.uses_stq, req.bits.uop.uses_stq connect mshrs_0.io.req.uop.uses_ldq, req.bits.uop.uses_ldq connect mshrs_0.io.req.uop.mem_signed, req.bits.uop.mem_signed connect mshrs_0.io.req.uop.mem_size, req.bits.uop.mem_size connect mshrs_0.io.req.uop.mem_cmd, req.bits.uop.mem_cmd connect mshrs_0.io.req.uop.exc_cause, req.bits.uop.exc_cause connect mshrs_0.io.req.uop.exception, req.bits.uop.exception connect mshrs_0.io.req.uop.stale_pdst, req.bits.uop.stale_pdst connect mshrs_0.io.req.uop.ppred_busy, req.bits.uop.ppred_busy connect mshrs_0.io.req.uop.prs3_busy, req.bits.uop.prs3_busy connect mshrs_0.io.req.uop.prs2_busy, req.bits.uop.prs2_busy connect mshrs_0.io.req.uop.prs1_busy, req.bits.uop.prs1_busy connect mshrs_0.io.req.uop.ppred, req.bits.uop.ppred connect mshrs_0.io.req.uop.prs3, req.bits.uop.prs3 connect mshrs_0.io.req.uop.prs2, req.bits.uop.prs2 connect mshrs_0.io.req.uop.prs1, req.bits.uop.prs1 connect mshrs_0.io.req.uop.pdst, req.bits.uop.pdst connect mshrs_0.io.req.uop.rxq_idx, req.bits.uop.rxq_idx connect mshrs_0.io.req.uop.stq_idx, req.bits.uop.stq_idx connect mshrs_0.io.req.uop.ldq_idx, req.bits.uop.ldq_idx connect mshrs_0.io.req.uop.rob_idx, req.bits.uop.rob_idx connect mshrs_0.io.req.uop.fp_ctrl.vec, req.bits.uop.fp_ctrl.vec connect mshrs_0.io.req.uop.fp_ctrl.wflags, req.bits.uop.fp_ctrl.wflags connect mshrs_0.io.req.uop.fp_ctrl.sqrt, req.bits.uop.fp_ctrl.sqrt connect mshrs_0.io.req.uop.fp_ctrl.div, req.bits.uop.fp_ctrl.div connect mshrs_0.io.req.uop.fp_ctrl.fma, req.bits.uop.fp_ctrl.fma connect mshrs_0.io.req.uop.fp_ctrl.fastpipe, req.bits.uop.fp_ctrl.fastpipe connect mshrs_0.io.req.uop.fp_ctrl.toint, req.bits.uop.fp_ctrl.toint connect mshrs_0.io.req.uop.fp_ctrl.fromint, req.bits.uop.fp_ctrl.fromint connect mshrs_0.io.req.uop.fp_ctrl.typeTagOut, req.bits.uop.fp_ctrl.typeTagOut connect mshrs_0.io.req.uop.fp_ctrl.typeTagIn, req.bits.uop.fp_ctrl.typeTagIn connect mshrs_0.io.req.uop.fp_ctrl.swap23, req.bits.uop.fp_ctrl.swap23 connect mshrs_0.io.req.uop.fp_ctrl.swap12, req.bits.uop.fp_ctrl.swap12 connect mshrs_0.io.req.uop.fp_ctrl.ren3, req.bits.uop.fp_ctrl.ren3 connect mshrs_0.io.req.uop.fp_ctrl.ren2, req.bits.uop.fp_ctrl.ren2 connect mshrs_0.io.req.uop.fp_ctrl.ren1, req.bits.uop.fp_ctrl.ren1 connect mshrs_0.io.req.uop.fp_ctrl.wen, req.bits.uop.fp_ctrl.wen connect mshrs_0.io.req.uop.fp_ctrl.ldst, req.bits.uop.fp_ctrl.ldst connect mshrs_0.io.req.uop.op2_sel, req.bits.uop.op2_sel connect mshrs_0.io.req.uop.op1_sel, req.bits.uop.op1_sel connect mshrs_0.io.req.uop.imm_packed, req.bits.uop.imm_packed connect mshrs_0.io.req.uop.pimm, req.bits.uop.pimm connect mshrs_0.io.req.uop.imm_sel, req.bits.uop.imm_sel connect mshrs_0.io.req.uop.imm_rename, req.bits.uop.imm_rename connect mshrs_0.io.req.uop.taken, req.bits.uop.taken connect mshrs_0.io.req.uop.pc_lob, req.bits.uop.pc_lob connect mshrs_0.io.req.uop.edge_inst, req.bits.uop.edge_inst connect mshrs_0.io.req.uop.ftq_idx, req.bits.uop.ftq_idx connect mshrs_0.io.req.uop.is_mov, req.bits.uop.is_mov connect mshrs_0.io.req.uop.is_rocc, req.bits.uop.is_rocc connect mshrs_0.io.req.uop.is_sys_pc2epc, req.bits.uop.is_sys_pc2epc connect mshrs_0.io.req.uop.is_eret, req.bits.uop.is_eret connect mshrs_0.io.req.uop.is_amo, req.bits.uop.is_amo connect mshrs_0.io.req.uop.is_sfence, req.bits.uop.is_sfence connect mshrs_0.io.req.uop.is_fencei, req.bits.uop.is_fencei connect mshrs_0.io.req.uop.is_fence, req.bits.uop.is_fence connect mshrs_0.io.req.uop.is_sfb, req.bits.uop.is_sfb connect mshrs_0.io.req.uop.br_type, req.bits.uop.br_type connect mshrs_0.io.req.uop.br_tag, req.bits.uop.br_tag connect mshrs_0.io.req.uop.br_mask, req.bits.uop.br_mask connect mshrs_0.io.req.uop.dis_col_sel, req.bits.uop.dis_col_sel connect mshrs_0.io.req.uop.iw_p3_bypass_hint, req.bits.uop.iw_p3_bypass_hint connect mshrs_0.io.req.uop.iw_p2_bypass_hint, req.bits.uop.iw_p2_bypass_hint connect mshrs_0.io.req.uop.iw_p1_bypass_hint, req.bits.uop.iw_p1_bypass_hint connect mshrs_0.io.req.uop.iw_p2_speculative_child, req.bits.uop.iw_p2_speculative_child connect mshrs_0.io.req.uop.iw_p1_speculative_child, req.bits.uop.iw_p1_speculative_child connect mshrs_0.io.req.uop.iw_issued_partial_dgen, req.bits.uop.iw_issued_partial_dgen connect mshrs_0.io.req.uop.iw_issued_partial_agen, req.bits.uop.iw_issued_partial_agen connect mshrs_0.io.req.uop.iw_issued, req.bits.uop.iw_issued connect mshrs_0.io.req.uop.fu_code[0], req.bits.uop.fu_code[0] connect mshrs_0.io.req.uop.fu_code[1], req.bits.uop.fu_code[1] connect mshrs_0.io.req.uop.fu_code[2], req.bits.uop.fu_code[2] connect mshrs_0.io.req.uop.fu_code[3], req.bits.uop.fu_code[3] connect mshrs_0.io.req.uop.fu_code[4], req.bits.uop.fu_code[4] connect mshrs_0.io.req.uop.fu_code[5], req.bits.uop.fu_code[5] connect mshrs_0.io.req.uop.fu_code[6], req.bits.uop.fu_code[6] connect mshrs_0.io.req.uop.fu_code[7], req.bits.uop.fu_code[7] connect mshrs_0.io.req.uop.fu_code[8], req.bits.uop.fu_code[8] connect mshrs_0.io.req.uop.fu_code[9], req.bits.uop.fu_code[9] connect mshrs_0.io.req.uop.iq_type[0], req.bits.uop.iq_type[0] connect mshrs_0.io.req.uop.iq_type[1], req.bits.uop.iq_type[1] connect mshrs_0.io.req.uop.iq_type[2], req.bits.uop.iq_type[2] connect mshrs_0.io.req.uop.iq_type[3], req.bits.uop.iq_type[3] connect mshrs_0.io.req.uop.debug_pc, req.bits.uop.debug_pc connect mshrs_0.io.req.uop.is_rvc, req.bits.uop.is_rvc connect mshrs_0.io.req.uop.debug_inst, req.bits.uop.debug_inst connect mshrs_0.io.req.uop.inst, req.bits.uop.inst connect mshrs_0.io.req_is_probe, io.req_is_probe[0] connect mshrs_0.io.req.sdq_id, sdq_alloc_id node _mshr_io_clear_prefetch_T = eq(req.valid, UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_1 = and(io.clear_all, _mshr_io_clear_prefetch_T) node _mshr_io_clear_prefetch_T_2 = and(req.valid, idx_matches[0][0]) node _mshr_io_clear_prefetch_T_3 = and(_mshr_io_clear_prefetch_T_2, cacheable) node _mshr_io_clear_prefetch_T_4 = eq(tag_match[0], UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_5 = and(_mshr_io_clear_prefetch_T_3, _mshr_io_clear_prefetch_T_4) node _mshr_io_clear_prefetch_T_6 = or(_mshr_io_clear_prefetch_T_1, _mshr_io_clear_prefetch_T_5) node _mshr_io_clear_prefetch_T_7 = and(io.req_is_probe[0], idx_matches[0][0]) node _mshr_io_clear_prefetch_T_8 = or(_mshr_io_clear_prefetch_T_6, _mshr_io_clear_prefetch_T_7) connect mshrs_0.io.clear_prefetch, _mshr_io_clear_prefetch_T_8 connect mshrs_0.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect mshrs_0.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect mshrs_0.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect mshrs_0.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect mshrs_0.io.brupdate.b2.taken, io.brupdate.b2.taken connect mshrs_0.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect mshrs_0.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect mshrs_0.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect mshrs_0.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect mshrs_0.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect mshrs_0.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect mshrs_0.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect mshrs_0.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect mshrs_0.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect mshrs_0.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect mshrs_0.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect mshrs_0.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect mshrs_0.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect mshrs_0.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect mshrs_0.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect mshrs_0.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect mshrs_0.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect mshrs_0.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect mshrs_0.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect mshrs_0.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect mshrs_0.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect mshrs_0.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect mshrs_0.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect mshrs_0.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect mshrs_0.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect mshrs_0.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect mshrs_0.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect mshrs_0.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect mshrs_0.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect mshrs_0.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect mshrs_0.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect mshrs_0.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect mshrs_0.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect mshrs_0.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect mshrs_0.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect mshrs_0.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect mshrs_0.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect mshrs_0.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect mshrs_0.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect mshrs_0.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect mshrs_0.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect mshrs_0.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect mshrs_0.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect mshrs_0.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect mshrs_0.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect mshrs_0.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect mshrs_0.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect mshrs_0.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect mshrs_0.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect mshrs_0.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect mshrs_0.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect mshrs_0.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect mshrs_0.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect mshrs_0.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect mshrs_0.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect mshrs_0.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect mshrs_0.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect mshrs_0.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect mshrs_0.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect mshrs_0.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect mshrs_0.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect mshrs_0.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect mshrs_0.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect mshrs_0.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect mshrs_0.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect mshrs_0.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect mshrs_0.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect mshrs_0.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect mshrs_0.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect mshrs_0.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect mshrs_0.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect mshrs_0.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect mshrs_0.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect mshrs_0.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect mshrs_0.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect mshrs_0.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect mshrs_0.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect mshrs_0.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect mshrs_0.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect mshrs_0.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect mshrs_0.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect mshrs_0.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect mshrs_0.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect mshrs_0.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect mshrs_0.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect mshrs_0.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect mshrs_0.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect mshrs_0.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect mshrs_0.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect mshrs_0.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect mshrs_0.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect mshrs_0.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect mshrs_0.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect mshrs_0.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect mshrs_0.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect mshrs_0.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect mshrs_0.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect mshrs_0.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect mshrs_0.io.exception, io.exception connect mshrs_0.io.rob_pnr_idx, io.rob_pnr_idx connect mshrs_0.io.rob_head_idx, io.rob_head_idx connect mshrs_0.io.prober_state.bits, io.prober_state.bits connect mshrs_0.io.prober_state.valid, io.prober_state.valid connect mshrs_0.io.wb_resp, io.wb_resp connect meta_write_arb.io.in[0], mshrs_0.io.meta_write connect meta_read_arb.io.in[0], mshrs_0.io.meta_read connect mshrs_0.io.meta_resp.bits.tag, io.meta_resp.bits.tag connect mshrs_0.io.meta_resp.bits.coh.state, io.meta_resp.bits.coh.state connect mshrs_0.io.meta_resp.valid, io.meta_resp.valid connect wb_req_arb.io.in[0], mshrs_0.io.wb_req connect replay_arb.io.in[0], mshrs_0.io.replay connect refill_arb.io.in[0], mshrs_0.io.refill connect mshrs_0.io.lb_resp, lb[0][mshrs_0.io.lb_read.offset] when mshrs_0.io.lb_write.valid : connect lb[0][mshrs_0.io.lb_write.bits.offset], mshrs_0.io.lb_write.bits.data connect commit_vals[0], mshrs_0.io.commit_val connect commit_addrs[0], mshrs_0.io.commit_addr connect commit_cohs[0], mshrs_0.io.commit_coh connect mshrs_0.io.mem_grant.valid, UInt<1>(0h0) invalidate mshrs_0.io.mem_grant.bits.corrupt invalidate mshrs_0.io.mem_grant.bits.data invalidate mshrs_0.io.mem_grant.bits.denied invalidate mshrs_0.io.mem_grant.bits.sink invalidate mshrs_0.io.mem_grant.bits.source invalidate mshrs_0.io.mem_grant.bits.size invalidate mshrs_0.io.mem_grant.bits.param invalidate mshrs_0.io.mem_grant.bits.opcode node _T_1 = eq(io.mem_grant.bits.source, UInt<1>(0h0)) when _T_1 : connect mshrs_0.io.mem_grant, io.mem_grant node _T_2 = and(mshrs_0.io.req_sec_rdy, mshrs_0.io.req_sec_val) node _T_3 = or(UInt<1>(0h0), _T_2) connect resp_arb.io.in[0], mshrs_0.io.resp node _T_4 = eq(mshrs_0.io.req_pri_rdy, UInt<1>(0h0)) when _T_4 : connect io.fence_rdy, UInt<1>(0h0) node _T_5 = eq(mshrs_0.io.probe_rdy, UInt<1>(0h0)) node _T_6 = and(_T_5, idx_matches[0][0]) node _T_7 = and(_T_6, io.req_is_probe[0]) when _T_7 : connect io.probe_rdy, UInt<1>(0h0) inst mshrs_1 of BoomMSHR_1 connect mshrs_1.clock, clock connect mshrs_1.reset, reset connect mshrs_1.io.id, UInt<1>(0h1) node _idx_matches_0_1_T = bits(io.req[0].bits.addr, 11, 6) node _idx_matches_0_1_T_1 = eq(mshrs_1.io.idx.bits, _idx_matches_0_1_T) node _idx_matches_0_1_T_2 = and(mshrs_1.io.idx.valid, _idx_matches_0_1_T_1) connect idx_matches[0][1], _idx_matches_0_1_T_2 node _tag_matches_0_1_T = shr(io.req[0].bits.addr, 12) node _tag_matches_0_1_T_1 = eq(mshrs_1.io.tag.bits, _tag_matches_0_1_T) node _tag_matches_0_1_T_2 = and(mshrs_1.io.tag.valid, _tag_matches_0_1_T_1) connect tag_matches[0][1], _tag_matches_0_1_T_2 node _way_matches_0_1_T = eq(mshrs_1.io.way.bits, io.req[0].bits.way_en) node _way_matches_0_1_T_1 = and(mshrs_1.io.way.valid, _way_matches_0_1_T) connect way_matches[0][1], _way_matches_0_1_T_1 connect wb_tag_list[1], mshrs_1.io.wb_req.bits.tag node _mshr_io_req_pri_val_T_2 = eq(UInt<1>(0h1), mshr_alloc_idx) node _mshr_io_req_pri_val_T_3 = and(_mshr_io_req_pri_val_T_2, pri_val) connect mshrs_1.io.req_pri_val, _mshr_io_req_pri_val_T_3 node _T_8 = eq(UInt<1>(0h1), mshr_alloc_idx) when _T_8 : connect pri_rdy, mshrs_1.io.req_pri_rdy node _mshr_io_req_sec_val_T_4 = and(req.valid, sdq_rdy) node _mshr_io_req_sec_val_T_5 = and(_mshr_io_req_sec_val_T_4, tag_match[0]) node _mshr_io_req_sec_val_T_6 = and(_mshr_io_req_sec_val_T_5, idx_matches[0][1]) node _mshr_io_req_sec_val_T_7 = and(_mshr_io_req_sec_val_T_6, cacheable) connect mshrs_1.io.req_sec_val, _mshr_io_req_sec_val_T_7 connect mshrs_1.io.req.sdq_id, req.bits.sdq_id connect mshrs_1.io.req.way_en, req.bits.way_en connect mshrs_1.io.req.old_meta.tag, req.bits.old_meta.tag connect mshrs_1.io.req.old_meta.coh.state, req.bits.old_meta.coh.state connect mshrs_1.io.req.tag_match, req.bits.tag_match connect mshrs_1.io.req.is_hella, req.bits.is_hella connect mshrs_1.io.req.data, req.bits.data connect mshrs_1.io.req.addr, req.bits.addr connect mshrs_1.io.req.uop.debug_tsrc, req.bits.uop.debug_tsrc connect mshrs_1.io.req.uop.debug_fsrc, req.bits.uop.debug_fsrc connect mshrs_1.io.req.uop.bp_xcpt_if, req.bits.uop.bp_xcpt_if connect mshrs_1.io.req.uop.bp_debug_if, req.bits.uop.bp_debug_if connect mshrs_1.io.req.uop.xcpt_ma_if, req.bits.uop.xcpt_ma_if connect mshrs_1.io.req.uop.xcpt_ae_if, req.bits.uop.xcpt_ae_if connect mshrs_1.io.req.uop.xcpt_pf_if, req.bits.uop.xcpt_pf_if connect mshrs_1.io.req.uop.fp_typ, req.bits.uop.fp_typ connect mshrs_1.io.req.uop.fp_rm, req.bits.uop.fp_rm connect mshrs_1.io.req.uop.fp_val, req.bits.uop.fp_val connect mshrs_1.io.req.uop.fcn_op, req.bits.uop.fcn_op connect mshrs_1.io.req.uop.fcn_dw, req.bits.uop.fcn_dw connect mshrs_1.io.req.uop.frs3_en, req.bits.uop.frs3_en connect mshrs_1.io.req.uop.lrs2_rtype, req.bits.uop.lrs2_rtype connect mshrs_1.io.req.uop.lrs1_rtype, req.bits.uop.lrs1_rtype connect mshrs_1.io.req.uop.dst_rtype, req.bits.uop.dst_rtype connect mshrs_1.io.req.uop.lrs3, req.bits.uop.lrs3 connect mshrs_1.io.req.uop.lrs2, req.bits.uop.lrs2 connect mshrs_1.io.req.uop.lrs1, req.bits.uop.lrs1 connect mshrs_1.io.req.uop.ldst, req.bits.uop.ldst connect mshrs_1.io.req.uop.ldst_is_rs1, req.bits.uop.ldst_is_rs1 connect mshrs_1.io.req.uop.csr_cmd, req.bits.uop.csr_cmd connect mshrs_1.io.req.uop.flush_on_commit, req.bits.uop.flush_on_commit connect mshrs_1.io.req.uop.is_unique, req.bits.uop.is_unique connect mshrs_1.io.req.uop.uses_stq, req.bits.uop.uses_stq connect mshrs_1.io.req.uop.uses_ldq, req.bits.uop.uses_ldq connect mshrs_1.io.req.uop.mem_signed, req.bits.uop.mem_signed connect mshrs_1.io.req.uop.mem_size, req.bits.uop.mem_size connect mshrs_1.io.req.uop.mem_cmd, req.bits.uop.mem_cmd connect mshrs_1.io.req.uop.exc_cause, req.bits.uop.exc_cause connect mshrs_1.io.req.uop.exception, req.bits.uop.exception connect mshrs_1.io.req.uop.stale_pdst, req.bits.uop.stale_pdst connect mshrs_1.io.req.uop.ppred_busy, req.bits.uop.ppred_busy connect mshrs_1.io.req.uop.prs3_busy, req.bits.uop.prs3_busy connect mshrs_1.io.req.uop.prs2_busy, req.bits.uop.prs2_busy connect mshrs_1.io.req.uop.prs1_busy, req.bits.uop.prs1_busy connect mshrs_1.io.req.uop.ppred, req.bits.uop.ppred connect mshrs_1.io.req.uop.prs3, req.bits.uop.prs3 connect mshrs_1.io.req.uop.prs2, req.bits.uop.prs2 connect mshrs_1.io.req.uop.prs1, req.bits.uop.prs1 connect mshrs_1.io.req.uop.pdst, req.bits.uop.pdst connect mshrs_1.io.req.uop.rxq_idx, req.bits.uop.rxq_idx connect mshrs_1.io.req.uop.stq_idx, req.bits.uop.stq_idx connect mshrs_1.io.req.uop.ldq_idx, req.bits.uop.ldq_idx connect mshrs_1.io.req.uop.rob_idx, req.bits.uop.rob_idx connect mshrs_1.io.req.uop.fp_ctrl.vec, req.bits.uop.fp_ctrl.vec connect mshrs_1.io.req.uop.fp_ctrl.wflags, req.bits.uop.fp_ctrl.wflags connect mshrs_1.io.req.uop.fp_ctrl.sqrt, req.bits.uop.fp_ctrl.sqrt connect mshrs_1.io.req.uop.fp_ctrl.div, req.bits.uop.fp_ctrl.div connect mshrs_1.io.req.uop.fp_ctrl.fma, req.bits.uop.fp_ctrl.fma connect mshrs_1.io.req.uop.fp_ctrl.fastpipe, req.bits.uop.fp_ctrl.fastpipe connect mshrs_1.io.req.uop.fp_ctrl.toint, req.bits.uop.fp_ctrl.toint connect mshrs_1.io.req.uop.fp_ctrl.fromint, req.bits.uop.fp_ctrl.fromint connect mshrs_1.io.req.uop.fp_ctrl.typeTagOut, req.bits.uop.fp_ctrl.typeTagOut connect mshrs_1.io.req.uop.fp_ctrl.typeTagIn, req.bits.uop.fp_ctrl.typeTagIn connect mshrs_1.io.req.uop.fp_ctrl.swap23, req.bits.uop.fp_ctrl.swap23 connect mshrs_1.io.req.uop.fp_ctrl.swap12, req.bits.uop.fp_ctrl.swap12 connect mshrs_1.io.req.uop.fp_ctrl.ren3, req.bits.uop.fp_ctrl.ren3 connect mshrs_1.io.req.uop.fp_ctrl.ren2, req.bits.uop.fp_ctrl.ren2 connect mshrs_1.io.req.uop.fp_ctrl.ren1, req.bits.uop.fp_ctrl.ren1 connect mshrs_1.io.req.uop.fp_ctrl.wen, req.bits.uop.fp_ctrl.wen connect mshrs_1.io.req.uop.fp_ctrl.ldst, req.bits.uop.fp_ctrl.ldst connect mshrs_1.io.req.uop.op2_sel, req.bits.uop.op2_sel connect mshrs_1.io.req.uop.op1_sel, req.bits.uop.op1_sel connect mshrs_1.io.req.uop.imm_packed, req.bits.uop.imm_packed connect mshrs_1.io.req.uop.pimm, req.bits.uop.pimm connect mshrs_1.io.req.uop.imm_sel, req.bits.uop.imm_sel connect mshrs_1.io.req.uop.imm_rename, req.bits.uop.imm_rename connect mshrs_1.io.req.uop.taken, req.bits.uop.taken connect mshrs_1.io.req.uop.pc_lob, req.bits.uop.pc_lob connect mshrs_1.io.req.uop.edge_inst, req.bits.uop.edge_inst connect mshrs_1.io.req.uop.ftq_idx, req.bits.uop.ftq_idx connect mshrs_1.io.req.uop.is_mov, req.bits.uop.is_mov connect mshrs_1.io.req.uop.is_rocc, req.bits.uop.is_rocc connect mshrs_1.io.req.uop.is_sys_pc2epc, req.bits.uop.is_sys_pc2epc connect mshrs_1.io.req.uop.is_eret, req.bits.uop.is_eret connect mshrs_1.io.req.uop.is_amo, req.bits.uop.is_amo connect mshrs_1.io.req.uop.is_sfence, req.bits.uop.is_sfence connect mshrs_1.io.req.uop.is_fencei, req.bits.uop.is_fencei connect mshrs_1.io.req.uop.is_fence, req.bits.uop.is_fence connect mshrs_1.io.req.uop.is_sfb, req.bits.uop.is_sfb connect mshrs_1.io.req.uop.br_type, req.bits.uop.br_type connect mshrs_1.io.req.uop.br_tag, req.bits.uop.br_tag connect mshrs_1.io.req.uop.br_mask, req.bits.uop.br_mask connect mshrs_1.io.req.uop.dis_col_sel, req.bits.uop.dis_col_sel connect mshrs_1.io.req.uop.iw_p3_bypass_hint, req.bits.uop.iw_p3_bypass_hint connect mshrs_1.io.req.uop.iw_p2_bypass_hint, req.bits.uop.iw_p2_bypass_hint connect mshrs_1.io.req.uop.iw_p1_bypass_hint, req.bits.uop.iw_p1_bypass_hint connect mshrs_1.io.req.uop.iw_p2_speculative_child, req.bits.uop.iw_p2_speculative_child connect mshrs_1.io.req.uop.iw_p1_speculative_child, req.bits.uop.iw_p1_speculative_child connect mshrs_1.io.req.uop.iw_issued_partial_dgen, req.bits.uop.iw_issued_partial_dgen connect mshrs_1.io.req.uop.iw_issued_partial_agen, req.bits.uop.iw_issued_partial_agen connect mshrs_1.io.req.uop.iw_issued, req.bits.uop.iw_issued connect mshrs_1.io.req.uop.fu_code[0], req.bits.uop.fu_code[0] connect mshrs_1.io.req.uop.fu_code[1], req.bits.uop.fu_code[1] connect mshrs_1.io.req.uop.fu_code[2], req.bits.uop.fu_code[2] connect mshrs_1.io.req.uop.fu_code[3], req.bits.uop.fu_code[3] connect mshrs_1.io.req.uop.fu_code[4], req.bits.uop.fu_code[4] connect mshrs_1.io.req.uop.fu_code[5], req.bits.uop.fu_code[5] connect mshrs_1.io.req.uop.fu_code[6], req.bits.uop.fu_code[6] connect mshrs_1.io.req.uop.fu_code[7], req.bits.uop.fu_code[7] connect mshrs_1.io.req.uop.fu_code[8], req.bits.uop.fu_code[8] connect mshrs_1.io.req.uop.fu_code[9], req.bits.uop.fu_code[9] connect mshrs_1.io.req.uop.iq_type[0], req.bits.uop.iq_type[0] connect mshrs_1.io.req.uop.iq_type[1], req.bits.uop.iq_type[1] connect mshrs_1.io.req.uop.iq_type[2], req.bits.uop.iq_type[2] connect mshrs_1.io.req.uop.iq_type[3], req.bits.uop.iq_type[3] connect mshrs_1.io.req.uop.debug_pc, req.bits.uop.debug_pc connect mshrs_1.io.req.uop.is_rvc, req.bits.uop.is_rvc connect mshrs_1.io.req.uop.debug_inst, req.bits.uop.debug_inst connect mshrs_1.io.req.uop.inst, req.bits.uop.inst connect mshrs_1.io.req_is_probe, io.req_is_probe[0] connect mshrs_1.io.req.sdq_id, sdq_alloc_id node _mshr_io_clear_prefetch_T_9 = eq(req.valid, UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_10 = and(io.clear_all, _mshr_io_clear_prefetch_T_9) node _mshr_io_clear_prefetch_T_11 = and(req.valid, idx_matches[0][1]) node _mshr_io_clear_prefetch_T_12 = and(_mshr_io_clear_prefetch_T_11, cacheable) node _mshr_io_clear_prefetch_T_13 = eq(tag_match[0], UInt<1>(0h0)) node _mshr_io_clear_prefetch_T_14 = and(_mshr_io_clear_prefetch_T_12, _mshr_io_clear_prefetch_T_13) node _mshr_io_clear_prefetch_T_15 = or(_mshr_io_clear_prefetch_T_10, _mshr_io_clear_prefetch_T_14) node _mshr_io_clear_prefetch_T_16 = and(io.req_is_probe[0], idx_matches[0][1]) node _mshr_io_clear_prefetch_T_17 = or(_mshr_io_clear_prefetch_T_15, _mshr_io_clear_prefetch_T_16) connect mshrs_1.io.clear_prefetch, _mshr_io_clear_prefetch_T_17 connect mshrs_1.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect mshrs_1.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect mshrs_1.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect mshrs_1.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect mshrs_1.io.brupdate.b2.taken, io.brupdate.b2.taken connect mshrs_1.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect mshrs_1.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect mshrs_1.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect mshrs_1.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect mshrs_1.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect mshrs_1.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect mshrs_1.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect mshrs_1.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect mshrs_1.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect mshrs_1.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect mshrs_1.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect mshrs_1.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect mshrs_1.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect mshrs_1.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect mshrs_1.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect mshrs_1.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect mshrs_1.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect mshrs_1.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect mshrs_1.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect mshrs_1.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect mshrs_1.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect mshrs_1.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect mshrs_1.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect mshrs_1.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect mshrs_1.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect mshrs_1.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect mshrs_1.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect mshrs_1.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect mshrs_1.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect mshrs_1.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect mshrs_1.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect mshrs_1.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect mshrs_1.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect mshrs_1.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect mshrs_1.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect mshrs_1.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect mshrs_1.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect mshrs_1.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect mshrs_1.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect mshrs_1.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect mshrs_1.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect mshrs_1.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect mshrs_1.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect mshrs_1.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect mshrs_1.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect mshrs_1.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect mshrs_1.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect mshrs_1.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect mshrs_1.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect mshrs_1.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect mshrs_1.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect mshrs_1.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect mshrs_1.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect mshrs_1.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect mshrs_1.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect mshrs_1.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect mshrs_1.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect mshrs_1.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect mshrs_1.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect mshrs_1.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect mshrs_1.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect mshrs_1.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect mshrs_1.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect mshrs_1.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect mshrs_1.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect mshrs_1.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect mshrs_1.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect mshrs_1.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect mshrs_1.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect mshrs_1.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect mshrs_1.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect mshrs_1.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect mshrs_1.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect mshrs_1.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect mshrs_1.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect mshrs_1.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect mshrs_1.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect mshrs_1.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect mshrs_1.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect mshrs_1.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect mshrs_1.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect mshrs_1.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect mshrs_1.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect mshrs_1.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect mshrs_1.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect mshrs_1.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect mshrs_1.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect mshrs_1.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect mshrs_1.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect mshrs_1.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect mshrs_1.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect mshrs_1.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect mshrs_1.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect mshrs_1.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect mshrs_1.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect mshrs_1.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect mshrs_1.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect mshrs_1.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect mshrs_1.io.exception, io.exception connect mshrs_1.io.rob_pnr_idx, io.rob_pnr_idx connect mshrs_1.io.rob_head_idx, io.rob_head_idx connect mshrs_1.io.prober_state.bits, io.prober_state.bits connect mshrs_1.io.prober_state.valid, io.prober_state.valid connect mshrs_1.io.wb_resp, io.wb_resp connect meta_write_arb.io.in[1], mshrs_1.io.meta_write connect meta_read_arb.io.in[1], mshrs_1.io.meta_read connect mshrs_1.io.meta_resp.bits.tag, io.meta_resp.bits.tag connect mshrs_1.io.meta_resp.bits.coh.state, io.meta_resp.bits.coh.state connect mshrs_1.io.meta_resp.valid, io.meta_resp.valid connect wb_req_arb.io.in[1], mshrs_1.io.wb_req connect replay_arb.io.in[1], mshrs_1.io.replay connect refill_arb.io.in[1], mshrs_1.io.refill connect mshrs_1.io.lb_resp, lb[1][mshrs_1.io.lb_read.offset] when mshrs_1.io.lb_write.valid : connect lb[1][mshrs_1.io.lb_write.bits.offset], mshrs_1.io.lb_write.bits.data connect commit_vals[1], mshrs_1.io.commit_val connect commit_addrs[1], mshrs_1.io.commit_addr connect commit_cohs[1], mshrs_1.io.commit_coh connect mshrs_1.io.mem_grant.valid, UInt<1>(0h0) invalidate mshrs_1.io.mem_grant.bits.corrupt invalidate mshrs_1.io.mem_grant.bits.data invalidate mshrs_1.io.mem_grant.bits.denied invalidate mshrs_1.io.mem_grant.bits.sink invalidate mshrs_1.io.mem_grant.bits.source invalidate mshrs_1.io.mem_grant.bits.size invalidate mshrs_1.io.mem_grant.bits.param invalidate mshrs_1.io.mem_grant.bits.opcode node _T_9 = eq(io.mem_grant.bits.source, UInt<1>(0h1)) when _T_9 : connect mshrs_1.io.mem_grant, io.mem_grant node _T_10 = and(mshrs_1.io.req_sec_rdy, mshrs_1.io.req_sec_val) node _T_11 = or(_T_3, _T_10) connect resp_arb.io.in[1], mshrs_1.io.resp node _T_12 = eq(mshrs_1.io.req_pri_rdy, UInt<1>(0h0)) when _T_12 : connect io.fence_rdy, UInt<1>(0h0) node _T_13 = eq(mshrs_1.io.probe_rdy, UInt<1>(0h0)) node _T_14 = and(_T_13, idx_matches[0][1]) node _T_15 = and(_T_14, io.req_is_probe[0]) when _T_15 : connect io.probe_rdy, UInt<1>(0h0) regreset mshr_head : UInt<1>, clock, reset, UInt<1>(0h0) node _mshr_alloc_idx_temp_vec_T = geq(UInt<1>(0h0), mshr_head) node mshr_alloc_idx_temp_vec_0 = and(mshrs_0.io.req_pri_rdy, _mshr_alloc_idx_temp_vec_T) node _mshr_alloc_idx_temp_vec_T_1 = geq(UInt<1>(0h1), mshr_head) node mshr_alloc_idx_temp_vec_1 = and(mshrs_1.io.req_pri_rdy, _mshr_alloc_idx_temp_vec_T_1) node _mshr_alloc_idx_idx_T = mux(mshrs_0.io.req_pri_rdy, UInt<2>(0h2), UInt<2>(0h3)) node _mshr_alloc_idx_idx_T_1 = mux(mshr_alloc_idx_temp_vec_1, UInt<1>(0h1), _mshr_alloc_idx_idx_T) node mshr_alloc_idx_idx = mux(mshr_alloc_idx_temp_vec_0, UInt<1>(0h0), _mshr_alloc_idx_idx_T_1) node _mshr_alloc_idx_T = bits(mshr_alloc_idx_idx, 0, 0) reg mshr_alloc_idx_REG : UInt, clock connect mshr_alloc_idx_REG, _mshr_alloc_idx_T connect mshr_alloc_idx, mshr_alloc_idx_REG node _T_16 = and(pri_rdy, pri_val) when _T_16 : node _mshr_head_T = add(mshr_head, UInt<1>(0h1)) node _mshr_head_T_1 = tail(_mshr_head_T, 1) node _mshr_head_T_2 = bits(_mshr_head_T_1, 0, 0) connect mshr_head, _mshr_head_T_2 connect io.meta_write.bits, meta_write_arb.io.out.bits connect io.meta_write.valid, meta_write_arb.io.out.valid connect meta_write_arb.io.out.ready, io.meta_write.ready connect io.meta_read.bits, meta_read_arb.io.out.bits connect io.meta_read.valid, meta_read_arb.io.out.valid connect meta_read_arb.io.out.ready, io.meta_read.ready connect io.wb_req.bits, wb_req_arb.io.out.bits connect io.wb_req.valid, wb_req_arb.io.out.valid connect wb_req_arb.io.out.ready, io.wb_req.ready inst mmio_alloc_arb of Arbiter1_Bool connect mmio_alloc_arb.clock, clock connect mmio_alloc_arb.reset, reset inst mmios_0 of BoomIOMSHR connect mmios_0.clock, clock connect mmios_0.reset, reset connect mmio_alloc_arb.io.in[0].valid, mmios_0.io.req.ready invalidate mmio_alloc_arb.io.in[0].bits connect mmios_0.io.req.valid, mmio_alloc_arb.io.in[0].ready connect mmios_0.io.req.bits.is_hella, req.bits.is_hella connect mmios_0.io.req.bits.data, req.bits.data connect mmios_0.io.req.bits.addr, req.bits.addr connect mmios_0.io.req.bits.uop.debug_tsrc, req.bits.uop.debug_tsrc connect mmios_0.io.req.bits.uop.debug_fsrc, req.bits.uop.debug_fsrc connect mmios_0.io.req.bits.uop.bp_xcpt_if, req.bits.uop.bp_xcpt_if connect mmios_0.io.req.bits.uop.bp_debug_if, req.bits.uop.bp_debug_if connect mmios_0.io.req.bits.uop.xcpt_ma_if, req.bits.uop.xcpt_ma_if connect mmios_0.io.req.bits.uop.xcpt_ae_if, req.bits.uop.xcpt_ae_if connect mmios_0.io.req.bits.uop.xcpt_pf_if, req.bits.uop.xcpt_pf_if connect mmios_0.io.req.bits.uop.fp_typ, req.bits.uop.fp_typ connect mmios_0.io.req.bits.uop.fp_rm, req.bits.uop.fp_rm connect mmios_0.io.req.bits.uop.fp_val, req.bits.uop.fp_val connect mmios_0.io.req.bits.uop.fcn_op, req.bits.uop.fcn_op connect mmios_0.io.req.bits.uop.fcn_dw, req.bits.uop.fcn_dw connect mmios_0.io.req.bits.uop.frs3_en, req.bits.uop.frs3_en connect mmios_0.io.req.bits.uop.lrs2_rtype, req.bits.uop.lrs2_rtype connect mmios_0.io.req.bits.uop.lrs1_rtype, req.bits.uop.lrs1_rtype connect mmios_0.io.req.bits.uop.dst_rtype, req.bits.uop.dst_rtype connect mmios_0.io.req.bits.uop.lrs3, req.bits.uop.lrs3 connect mmios_0.io.req.bits.uop.lrs2, req.bits.uop.lrs2 connect mmios_0.io.req.bits.uop.lrs1, req.bits.uop.lrs1 connect mmios_0.io.req.bits.uop.ldst, req.bits.uop.ldst connect mmios_0.io.req.bits.uop.ldst_is_rs1, req.bits.uop.ldst_is_rs1 connect mmios_0.io.req.bits.uop.csr_cmd, req.bits.uop.csr_cmd connect mmios_0.io.req.bits.uop.flush_on_commit, req.bits.uop.flush_on_commit connect mmios_0.io.req.bits.uop.is_unique, req.bits.uop.is_unique connect mmios_0.io.req.bits.uop.uses_stq, req.bits.uop.uses_stq connect mmios_0.io.req.bits.uop.uses_ldq, req.bits.uop.uses_ldq connect mmios_0.io.req.bits.uop.mem_signed, req.bits.uop.mem_signed connect mmios_0.io.req.bits.uop.mem_size, req.bits.uop.mem_size connect mmios_0.io.req.bits.uop.mem_cmd, req.bits.uop.mem_cmd connect mmios_0.io.req.bits.uop.exc_cause, req.bits.uop.exc_cause connect mmios_0.io.req.bits.uop.exception, req.bits.uop.exception connect mmios_0.io.req.bits.uop.stale_pdst, req.bits.uop.stale_pdst connect mmios_0.io.req.bits.uop.ppred_busy, req.bits.uop.ppred_busy connect mmios_0.io.req.bits.uop.prs3_busy, req.bits.uop.prs3_busy connect mmios_0.io.req.bits.uop.prs2_busy, req.bits.uop.prs2_busy connect mmios_0.io.req.bits.uop.prs1_busy, req.bits.uop.prs1_busy connect mmios_0.io.req.bits.uop.ppred, req.bits.uop.ppred connect mmios_0.io.req.bits.uop.prs3, req.bits.uop.prs3 connect mmios_0.io.req.bits.uop.prs2, req.bits.uop.prs2 connect mmios_0.io.req.bits.uop.prs1, req.bits.uop.prs1 connect mmios_0.io.req.bits.uop.pdst, req.bits.uop.pdst connect mmios_0.io.req.bits.uop.rxq_idx, req.bits.uop.rxq_idx connect mmios_0.io.req.bits.uop.stq_idx, req.bits.uop.stq_idx connect mmios_0.io.req.bits.uop.ldq_idx, req.bits.uop.ldq_idx connect mmios_0.io.req.bits.uop.rob_idx, req.bits.uop.rob_idx connect mmios_0.io.req.bits.uop.fp_ctrl.vec, req.bits.uop.fp_ctrl.vec connect mmios_0.io.req.bits.uop.fp_ctrl.wflags, req.bits.uop.fp_ctrl.wflags connect mmios_0.io.req.bits.uop.fp_ctrl.sqrt, req.bits.uop.fp_ctrl.sqrt connect mmios_0.io.req.bits.uop.fp_ctrl.div, req.bits.uop.fp_ctrl.div connect mmios_0.io.req.bits.uop.fp_ctrl.fma, req.bits.uop.fp_ctrl.fma connect mmios_0.io.req.bits.uop.fp_ctrl.fastpipe, req.bits.uop.fp_ctrl.fastpipe connect mmios_0.io.req.bits.uop.fp_ctrl.toint, req.bits.uop.fp_ctrl.toint connect mmios_0.io.req.bits.uop.fp_ctrl.fromint, req.bits.uop.fp_ctrl.fromint connect mmios_0.io.req.bits.uop.fp_ctrl.typeTagOut, req.bits.uop.fp_ctrl.typeTagOut connect mmios_0.io.req.bits.uop.fp_ctrl.typeTagIn, req.bits.uop.fp_ctrl.typeTagIn connect mmios_0.io.req.bits.uop.fp_ctrl.swap23, req.bits.uop.fp_ctrl.swap23 connect mmios_0.io.req.bits.uop.fp_ctrl.swap12, req.bits.uop.fp_ctrl.swap12 connect mmios_0.io.req.bits.uop.fp_ctrl.ren3, req.bits.uop.fp_ctrl.ren3 connect mmios_0.io.req.bits.uop.fp_ctrl.ren2, req.bits.uop.fp_ctrl.ren2 connect mmios_0.io.req.bits.uop.fp_ctrl.ren1, req.bits.uop.fp_ctrl.ren1 connect mmios_0.io.req.bits.uop.fp_ctrl.wen, req.bits.uop.fp_ctrl.wen connect mmios_0.io.req.bits.uop.fp_ctrl.ldst, req.bits.uop.fp_ctrl.ldst connect mmios_0.io.req.bits.uop.op2_sel, req.bits.uop.op2_sel connect mmios_0.io.req.bits.uop.op1_sel, req.bits.uop.op1_sel connect mmios_0.io.req.bits.uop.imm_packed, req.bits.uop.imm_packed connect mmios_0.io.req.bits.uop.pimm, req.bits.uop.pimm connect mmios_0.io.req.bits.uop.imm_sel, req.bits.uop.imm_sel connect mmios_0.io.req.bits.uop.imm_rename, req.bits.uop.imm_rename connect mmios_0.io.req.bits.uop.taken, req.bits.uop.taken connect mmios_0.io.req.bits.uop.pc_lob, req.bits.uop.pc_lob connect mmios_0.io.req.bits.uop.edge_inst, req.bits.uop.edge_inst connect mmios_0.io.req.bits.uop.ftq_idx, req.bits.uop.ftq_idx connect mmios_0.io.req.bits.uop.is_mov, req.bits.uop.is_mov connect mmios_0.io.req.bits.uop.is_rocc, req.bits.uop.is_rocc connect mmios_0.io.req.bits.uop.is_sys_pc2epc, req.bits.uop.is_sys_pc2epc connect mmios_0.io.req.bits.uop.is_eret, req.bits.uop.is_eret connect mmios_0.io.req.bits.uop.is_amo, req.bits.uop.is_amo connect mmios_0.io.req.bits.uop.is_sfence, req.bits.uop.is_sfence connect mmios_0.io.req.bits.uop.is_fencei, req.bits.uop.is_fencei connect mmios_0.io.req.bits.uop.is_fence, req.bits.uop.is_fence connect mmios_0.io.req.bits.uop.is_sfb, req.bits.uop.is_sfb connect mmios_0.io.req.bits.uop.br_type, req.bits.uop.br_type connect mmios_0.io.req.bits.uop.br_tag, req.bits.uop.br_tag connect mmios_0.io.req.bits.uop.br_mask, req.bits.uop.br_mask connect mmios_0.io.req.bits.uop.dis_col_sel, req.bits.uop.dis_col_sel connect mmios_0.io.req.bits.uop.iw_p3_bypass_hint, req.bits.uop.iw_p3_bypass_hint connect mmios_0.io.req.bits.uop.iw_p2_bypass_hint, req.bits.uop.iw_p2_bypass_hint connect mmios_0.io.req.bits.uop.iw_p1_bypass_hint, req.bits.uop.iw_p1_bypass_hint connect mmios_0.io.req.bits.uop.iw_p2_speculative_child, req.bits.uop.iw_p2_speculative_child connect mmios_0.io.req.bits.uop.iw_p1_speculative_child, req.bits.uop.iw_p1_speculative_child connect mmios_0.io.req.bits.uop.iw_issued_partial_dgen, req.bits.uop.iw_issued_partial_dgen connect mmios_0.io.req.bits.uop.iw_issued_partial_agen, req.bits.uop.iw_issued_partial_agen connect mmios_0.io.req.bits.uop.iw_issued, req.bits.uop.iw_issued connect mmios_0.io.req.bits.uop.fu_code[0], req.bits.uop.fu_code[0] connect mmios_0.io.req.bits.uop.fu_code[1], req.bits.uop.fu_code[1] connect mmios_0.io.req.bits.uop.fu_code[2], req.bits.uop.fu_code[2] connect mmios_0.io.req.bits.uop.fu_code[3], req.bits.uop.fu_code[3] connect mmios_0.io.req.bits.uop.fu_code[4], req.bits.uop.fu_code[4] connect mmios_0.io.req.bits.uop.fu_code[5], req.bits.uop.fu_code[5] connect mmios_0.io.req.bits.uop.fu_code[6], req.bits.uop.fu_code[6] connect mmios_0.io.req.bits.uop.fu_code[7], req.bits.uop.fu_code[7] connect mmios_0.io.req.bits.uop.fu_code[8], req.bits.uop.fu_code[8] connect mmios_0.io.req.bits.uop.fu_code[9], req.bits.uop.fu_code[9] connect mmios_0.io.req.bits.uop.iq_type[0], req.bits.uop.iq_type[0] connect mmios_0.io.req.bits.uop.iq_type[1], req.bits.uop.iq_type[1] connect mmios_0.io.req.bits.uop.iq_type[2], req.bits.uop.iq_type[2] connect mmios_0.io.req.bits.uop.iq_type[3], req.bits.uop.iq_type[3] connect mmios_0.io.req.bits.uop.debug_pc, req.bits.uop.debug_pc connect mmios_0.io.req.bits.uop.is_rvc, req.bits.uop.is_rvc connect mmios_0.io.req.bits.uop.debug_inst, req.bits.uop.debug_inst connect mmios_0.io.req.bits.uop.inst, req.bits.uop.inst node _T_17 = or(UInt<1>(0h0), mmios_0.io.req.ready) connect mmios_0.io.mem_ack.bits.corrupt, io.mem_grant.bits.corrupt connect mmios_0.io.mem_ack.bits.data, io.mem_grant.bits.data connect mmios_0.io.mem_ack.bits.denied, io.mem_grant.bits.denied connect mmios_0.io.mem_ack.bits.sink, io.mem_grant.bits.sink connect mmios_0.io.mem_ack.bits.source, io.mem_grant.bits.source connect mmios_0.io.mem_ack.bits.size, io.mem_grant.bits.size connect mmios_0.io.mem_ack.bits.param, io.mem_grant.bits.param connect mmios_0.io.mem_ack.bits.opcode, io.mem_grant.bits.opcode node _mshr_io_mem_ack_valid_T = eq(io.mem_grant.bits.source, UInt<2>(0h3)) node _mshr_io_mem_ack_valid_T_1 = and(io.mem_grant.valid, _mshr_io_mem_ack_valid_T) connect mmios_0.io.mem_ack.valid, _mshr_io_mem_ack_valid_T_1 node _T_18 = eq(io.mem_grant.bits.source, UInt<2>(0h3)) when _T_18 : connect io.mem_grant.ready, UInt<1>(0h1) connect resp_arb.io.in[2], mmios_0.io.resp node _T_19 = eq(mmios_0.io.req.ready, UInt<1>(0h0)) when _T_19 : connect io.fence_rdy, UInt<1>(0h0) node _mmio_alloc_arb_io_out_ready_T = eq(cacheable, UInt<1>(0h0)) node _mmio_alloc_arb_io_out_ready_T_1 = and(req.valid, _mmio_alloc_arb_io_out_ready_T) connect mmio_alloc_arb.io.out.ready, _mmio_alloc_arb_io_out_ready_T_1 node _decode_T = dshl(UInt<12>(0hfff), mshrs_0.io.mem_acquire.bits.size) node _decode_T_1 = bits(_decode_T, 11, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(mshrs_0.io.mem_acquire.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_20 = mux(opdata, decode, UInt<1>(0h0)) node _decode_T_3 = dshl(UInt<12>(0hfff), mshrs_1.io.mem_acquire.bits.size) node _decode_T_4 = bits(_decode_T_3, 11, 0) node _decode_T_5 = not(_decode_T_4) node decode_1 = shr(_decode_T_5, 3) node _opdata_T_1 = bits(mshrs_1.io.mem_acquire.bits.opcode, 2, 2) node opdata_1 = eq(_opdata_T_1, UInt<1>(0h0)) node _T_21 = mux(opdata_1, decode_1, UInt<1>(0h0)) node _decode_T_6 = dshl(UInt<12>(0hfff), mmios_0.io.mem_access.bits.size) node _decode_T_7 = bits(_decode_T_6, 11, 0) node _decode_T_8 = not(_decode_T_7) node decode_2 = shr(_decode_T_8, 3) node _opdata_T_2 = bits(mmios_0.io.mem_access.bits.opcode, 2, 2) node opdata_2 = eq(_opdata_T_2, UInt<1>(0h0)) node _T_22 = mux(opdata_2, decode_2, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, io.mem_acquire.ready) node readys_hi = cat(mmios_0.io.mem_access.valid, mshrs_1.io.mem_acquire.valid) node _readys_T = cat(readys_hi, mshrs_0.io.mem_acquire.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 2, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = shl(_readys_T_3, 2) node _readys_T_5 = bits(_readys_T_4, 2, 0) node _readys_T_6 = or(_readys_T_3, _readys_T_5) node _readys_T_7 = bits(_readys_T_6, 2, 0) node _readys_T_8 = shl(_readys_T_7, 1) node _readys_T_9 = bits(_readys_T_8, 2, 0) node _readys_T_10 = not(_readys_T_9) node _readys_T_11 = bits(_readys_T_10, 0, 0) node _readys_T_12 = bits(_readys_T_10, 1, 1) node _readys_T_13 = bits(_readys_T_10, 2, 2) wire readys : UInt<1>[3] connect readys[0], _readys_T_11 connect readys[1], _readys_T_12 connect readys[2], _readys_T_13 node _winner_T = and(readys[0], mshrs_0.io.mem_acquire.valid) node _winner_T_1 = and(readys[1], mshrs_1.io.mem_acquire.valid) node _winner_T_2 = and(readys[2], mmios_0.io.mem_access.valid) wire winner : UInt<1>[3] connect winner[0], _winner_T connect winner[1], _winner_T_1 connect winner[2], _winner_T_2 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node prefixOR_2 = or(prefixOR_1, winner[1]) node _prefixOR_T = or(prefixOR_2, winner[2]) node _T_23 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_24 = eq(winner[0], UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = eq(prefixOR_1, UInt<1>(0h0)) node _T_27 = eq(winner[1], UInt<1>(0h0)) node _T_28 = or(_T_26, _T_27) node _T_29 = eq(prefixOR_2, UInt<1>(0h0)) node _T_30 = eq(winner[2], UInt<1>(0h0)) node _T_31 = or(_T_29, _T_30) node _T_32 = and(_T_25, _T_28) node _T_33 = and(_T_32, _T_31) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_33, UInt<1>(0h1), "") : assert node _T_37 = or(mshrs_0.io.mem_acquire.valid, mshrs_1.io.mem_acquire.valid) node _T_38 = or(_T_37, mmios_0.io.mem_access.valid) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = or(winner[0], winner[1]) node _T_41 = or(_T_40, winner[2]) node _T_42 = or(_T_39, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_42, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], _T_20, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_21, UInt<1>(0h0)) node maskedBeats_2 = mux(winner[2], _T_22, UInt<1>(0h0)) node _initBeats_T = or(maskedBeats_0, maskedBeats_1) node initBeats = or(_initBeats_T, maskedBeats_2) node _beatsLeft_T = and(io.mem_acquire.ready, io.mem_acquire.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[3] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) connect _state_WIRE[2], UInt<1>(0h0) regreset state : UInt<1>[3], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _mshrs_0_io_mem_acquire_ready_T = and(io.mem_acquire.ready, allowed[0]) connect mshrs_0.io.mem_acquire.ready, _mshrs_0_io_mem_acquire_ready_T node _mshrs_1_io_mem_acquire_ready_T = and(io.mem_acquire.ready, allowed[1]) connect mshrs_1.io.mem_acquire.ready, _mshrs_1_io_mem_acquire_ready_T node _mmios_0_io_mem_access_ready_T = and(io.mem_acquire.ready, allowed[2]) connect mmios_0.io.mem_access.ready, _mmios_0_io_mem_access_ready_T node _io_mem_acquire_valid_T = or(mshrs_0.io.mem_acquire.valid, mshrs_1.io.mem_acquire.valid) node _io_mem_acquire_valid_T_1 = or(_io_mem_acquire_valid_T, mmios_0.io.mem_access.valid) node _io_mem_acquire_valid_T_2 = mux(state[0], mshrs_0.io.mem_acquire.valid, UInt<1>(0h0)) node _io_mem_acquire_valid_T_3 = mux(state[1], mshrs_1.io.mem_acquire.valid, UInt<1>(0h0)) node _io_mem_acquire_valid_T_4 = mux(state[2], mmios_0.io.mem_access.valid, UInt<1>(0h0)) node _io_mem_acquire_valid_T_5 = or(_io_mem_acquire_valid_T_2, _io_mem_acquire_valid_T_3) node _io_mem_acquire_valid_T_6 = or(_io_mem_acquire_valid_T_5, _io_mem_acquire_valid_T_4) wire _io_mem_acquire_valid_WIRE : UInt<1> connect _io_mem_acquire_valid_WIRE, _io_mem_acquire_valid_T_6 node _io_mem_acquire_valid_T_7 = mux(idle, _io_mem_acquire_valid_T_1, _io_mem_acquire_valid_WIRE) connect io.mem_acquire.valid, _io_mem_acquire_valid_T_7 wire _io_mem_acquire_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _io_mem_acquire_bits_T = mux(muxState[0], mshrs_0.io.mem_acquire.bits.corrupt, UInt<1>(0h0)) node _io_mem_acquire_bits_T_1 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.corrupt, UInt<1>(0h0)) node _io_mem_acquire_bits_T_2 = mux(muxState[2], mmios_0.io.mem_access.bits.corrupt, UInt<1>(0h0)) node _io_mem_acquire_bits_T_3 = or(_io_mem_acquire_bits_T, _io_mem_acquire_bits_T_1) node _io_mem_acquire_bits_T_4 = or(_io_mem_acquire_bits_T_3, _io_mem_acquire_bits_T_2) wire _io_mem_acquire_bits_WIRE_1 : UInt<1> connect _io_mem_acquire_bits_WIRE_1, _io_mem_acquire_bits_T_4 connect _io_mem_acquire_bits_WIRE.corrupt, _io_mem_acquire_bits_WIRE_1 node _io_mem_acquire_bits_T_5 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.data, UInt<1>(0h0)) node _io_mem_acquire_bits_T_6 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.data, UInt<1>(0h0)) node _io_mem_acquire_bits_T_7 = mux(muxState[2], mmios_0.io.mem_access.bits.data, UInt<1>(0h0)) node _io_mem_acquire_bits_T_8 = or(_io_mem_acquire_bits_T_5, _io_mem_acquire_bits_T_6) node _io_mem_acquire_bits_T_9 = or(_io_mem_acquire_bits_T_8, _io_mem_acquire_bits_T_7) wire _io_mem_acquire_bits_WIRE_2 : UInt<64> connect _io_mem_acquire_bits_WIRE_2, _io_mem_acquire_bits_T_9 connect _io_mem_acquire_bits_WIRE.data, _io_mem_acquire_bits_WIRE_2 node _io_mem_acquire_bits_T_10 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.mask, UInt<1>(0h0)) node _io_mem_acquire_bits_T_11 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.mask, UInt<1>(0h0)) node _io_mem_acquire_bits_T_12 = mux(muxState[2], mmios_0.io.mem_access.bits.mask, UInt<1>(0h0)) node _io_mem_acquire_bits_T_13 = or(_io_mem_acquire_bits_T_10, _io_mem_acquire_bits_T_11) node _io_mem_acquire_bits_T_14 = or(_io_mem_acquire_bits_T_13, _io_mem_acquire_bits_T_12) wire _io_mem_acquire_bits_WIRE_3 : UInt<8> connect _io_mem_acquire_bits_WIRE_3, _io_mem_acquire_bits_T_14 connect _io_mem_acquire_bits_WIRE.mask, _io_mem_acquire_bits_WIRE_3 wire _io_mem_acquire_bits_WIRE_4 : { } connect _io_mem_acquire_bits_WIRE.echo, _io_mem_acquire_bits_WIRE_4 wire _io_mem_acquire_bits_WIRE_5 : { } connect _io_mem_acquire_bits_WIRE.user, _io_mem_acquire_bits_WIRE_5 node _io_mem_acquire_bits_T_15 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.address, UInt<1>(0h0)) node _io_mem_acquire_bits_T_16 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.address, UInt<1>(0h0)) node _io_mem_acquire_bits_T_17 = mux(muxState[2], mmios_0.io.mem_access.bits.address, UInt<1>(0h0)) node _io_mem_acquire_bits_T_18 = or(_io_mem_acquire_bits_T_15, _io_mem_acquire_bits_T_16) node _io_mem_acquire_bits_T_19 = or(_io_mem_acquire_bits_T_18, _io_mem_acquire_bits_T_17) wire _io_mem_acquire_bits_WIRE_6 : UInt<32> connect _io_mem_acquire_bits_WIRE_6, _io_mem_acquire_bits_T_19 connect _io_mem_acquire_bits_WIRE.address, _io_mem_acquire_bits_WIRE_6 node _io_mem_acquire_bits_T_20 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.source, UInt<1>(0h0)) node _io_mem_acquire_bits_T_21 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.source, UInt<1>(0h0)) node _io_mem_acquire_bits_T_22 = mux(muxState[2], mmios_0.io.mem_access.bits.source, UInt<1>(0h0)) node _io_mem_acquire_bits_T_23 = or(_io_mem_acquire_bits_T_20, _io_mem_acquire_bits_T_21) node _io_mem_acquire_bits_T_24 = or(_io_mem_acquire_bits_T_23, _io_mem_acquire_bits_T_22) wire _io_mem_acquire_bits_WIRE_7 : UInt<2> connect _io_mem_acquire_bits_WIRE_7, _io_mem_acquire_bits_T_24 connect _io_mem_acquire_bits_WIRE.source, _io_mem_acquire_bits_WIRE_7 node _io_mem_acquire_bits_T_25 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.size, UInt<1>(0h0)) node _io_mem_acquire_bits_T_26 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.size, UInt<1>(0h0)) node _io_mem_acquire_bits_T_27 = mux(muxState[2], mmios_0.io.mem_access.bits.size, UInt<1>(0h0)) node _io_mem_acquire_bits_T_28 = or(_io_mem_acquire_bits_T_25, _io_mem_acquire_bits_T_26) node _io_mem_acquire_bits_T_29 = or(_io_mem_acquire_bits_T_28, _io_mem_acquire_bits_T_27) wire _io_mem_acquire_bits_WIRE_8 : UInt<4> connect _io_mem_acquire_bits_WIRE_8, _io_mem_acquire_bits_T_29 connect _io_mem_acquire_bits_WIRE.size, _io_mem_acquire_bits_WIRE_8 node _io_mem_acquire_bits_T_30 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.param, UInt<1>(0h0)) node _io_mem_acquire_bits_T_31 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.param, UInt<1>(0h0)) node _io_mem_acquire_bits_T_32 = mux(muxState[2], mmios_0.io.mem_access.bits.param, UInt<1>(0h0)) node _io_mem_acquire_bits_T_33 = or(_io_mem_acquire_bits_T_30, _io_mem_acquire_bits_T_31) node _io_mem_acquire_bits_T_34 = or(_io_mem_acquire_bits_T_33, _io_mem_acquire_bits_T_32) wire _io_mem_acquire_bits_WIRE_9 : UInt<3> connect _io_mem_acquire_bits_WIRE_9, _io_mem_acquire_bits_T_34 connect _io_mem_acquire_bits_WIRE.param, _io_mem_acquire_bits_WIRE_9 node _io_mem_acquire_bits_T_35 = mux(muxState[0], mshrs_0.io.mem_acquire.bits.opcode, UInt<1>(0h0)) node _io_mem_acquire_bits_T_36 = mux(muxState[1], mshrs_1.io.mem_acquire.bits.opcode, UInt<1>(0h0)) node _io_mem_acquire_bits_T_37 = mux(muxState[2], mmios_0.io.mem_access.bits.opcode, UInt<1>(0h0)) node _io_mem_acquire_bits_T_38 = or(_io_mem_acquire_bits_T_35, _io_mem_acquire_bits_T_36) node _io_mem_acquire_bits_T_39 = or(_io_mem_acquire_bits_T_38, _io_mem_acquire_bits_T_37) wire _io_mem_acquire_bits_WIRE_10 : UInt<3> connect _io_mem_acquire_bits_WIRE_10, _io_mem_acquire_bits_T_39 connect _io_mem_acquire_bits_WIRE.opcode, _io_mem_acquire_bits_WIRE_10 connect io.mem_acquire.bits.corrupt, _io_mem_acquire_bits_WIRE.corrupt connect io.mem_acquire.bits.data, _io_mem_acquire_bits_WIRE.data connect io.mem_acquire.bits.mask, _io_mem_acquire_bits_WIRE.mask connect io.mem_acquire.bits.address, _io_mem_acquire_bits_WIRE.address connect io.mem_acquire.bits.source, _io_mem_acquire_bits_WIRE.source connect io.mem_acquire.bits.size, _io_mem_acquire_bits_WIRE.size connect io.mem_acquire.bits.param, _io_mem_acquire_bits_WIRE.param connect io.mem_acquire.bits.opcode, _io_mem_acquire_bits_WIRE.opcode regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, io.mem_finish.ready) node _readys_T_14 = cat(mshrs_1.io.mem_finish.valid, mshrs_0.io.mem_finish.valid) node _readys_T_15 = shl(_readys_T_14, 1) node _readys_T_16 = bits(_readys_T_15, 1, 0) node _readys_T_17 = or(_readys_T_14, _readys_T_16) node _readys_T_18 = bits(_readys_T_17, 1, 0) node _readys_T_19 = shl(_readys_T_18, 1) node _readys_T_20 = bits(_readys_T_19, 1, 0) node _readys_T_21 = not(_readys_T_20) node _readys_T_22 = bits(_readys_T_21, 0, 0) node _readys_T_23 = bits(_readys_T_21, 1, 1) wire readys_1 : UInt<1>[2] connect readys_1[0], _readys_T_22 connect readys_1[1], _readys_T_23 node _winner_T_3 = and(readys_1[0], mshrs_0.io.mem_finish.valid) node _winner_T_4 = and(readys_1[1], mshrs_1.io.mem_finish.valid) wire winner_1 : UInt<1>[2] connect winner_1[0], _winner_T_3 connect winner_1[1], _winner_T_4 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node _prefixOR_T_1 = or(prefixOR_1_1, winner_1[1]) node _T_46 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_47 = eq(winner_1[0], UInt<1>(0h0)) node _T_48 = or(_T_46, _T_47) node _T_49 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_50 = eq(winner_1[1], UInt<1>(0h0)) node _T_51 = or(_T_49, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_52, UInt<1>(0h1), "") : assert_2 node _T_56 = or(mshrs_0.io.mem_finish.valid, mshrs_1.io.mem_finish.valid) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = or(winner_1[0], winner_1[1]) node _T_59 = or(_T_57, _T_58) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3 assert(clock, _T_59, UInt<1>(0h1), "") : assert_3 node maskedBeats_0_1 = mux(winner_1[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], UInt<1>(0h0), UInt<1>(0h0)) node initBeats_1 = or(maskedBeats_0_1, maskedBeats_1_1) node _beatsLeft_T_4 = and(io.mem_finish.ready, io.mem_finish.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[2] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) regreset state_1 : UInt<1>[2], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _mshrs_0_io_mem_finish_ready_T = and(io.mem_finish.ready, allowed_1[0]) connect mshrs_0.io.mem_finish.ready, _mshrs_0_io_mem_finish_ready_T node _mshrs_1_io_mem_finish_ready_T = and(io.mem_finish.ready, allowed_1[1]) connect mshrs_1.io.mem_finish.ready, _mshrs_1_io_mem_finish_ready_T node _io_mem_finish_valid_T = or(mshrs_0.io.mem_finish.valid, mshrs_1.io.mem_finish.valid) node _io_mem_finish_valid_T_1 = mux(state_1[0], mshrs_0.io.mem_finish.valid, UInt<1>(0h0)) node _io_mem_finish_valid_T_2 = mux(state_1[1], mshrs_1.io.mem_finish.valid, UInt<1>(0h0)) node _io_mem_finish_valid_T_3 = or(_io_mem_finish_valid_T_1, _io_mem_finish_valid_T_2) wire _io_mem_finish_valid_WIRE : UInt<1> connect _io_mem_finish_valid_WIRE, _io_mem_finish_valid_T_3 node _io_mem_finish_valid_T_4 = mux(idle_1, _io_mem_finish_valid_T, _io_mem_finish_valid_WIRE) connect io.mem_finish.valid, _io_mem_finish_valid_T_4 wire _io_mem_finish_bits_WIRE : { sink : UInt<3>} node _io_mem_finish_bits_T = mux(muxState_1[0], mshrs_0.io.mem_finish.bits.sink, UInt<1>(0h0)) node _io_mem_finish_bits_T_1 = mux(muxState_1[1], mshrs_1.io.mem_finish.bits.sink, UInt<1>(0h0)) node _io_mem_finish_bits_T_2 = or(_io_mem_finish_bits_T, _io_mem_finish_bits_T_1) wire _io_mem_finish_bits_WIRE_1 : UInt<3> connect _io_mem_finish_bits_WIRE_1, _io_mem_finish_bits_T_2 connect _io_mem_finish_bits_WIRE.sink, _io_mem_finish_bits_WIRE_1 connect io.mem_finish.bits.sink, _io_mem_finish_bits_WIRE.sink inst respq of BranchKillableQueue_4 connect respq.clock, clock connect respq.reset, reset connect respq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect respq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect respq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect respq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect respq.io.brupdate.b2.taken, io.brupdate.b2.taken connect respq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect respq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect respq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect respq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect respq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect respq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect respq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect respq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect respq.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect respq.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect respq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect respq.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect respq.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect respq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect respq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect respq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect respq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect respq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect respq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect respq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect respq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect respq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect respq.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect respq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect respq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect respq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect respq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect respq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect respq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect respq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect respq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect respq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect respq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect respq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect respq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect respq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect respq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect respq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect respq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect respq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect respq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect respq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect respq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect respq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect respq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect respq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect respq.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect respq.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect respq.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect respq.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect respq.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect respq.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect respq.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect respq.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect respq.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect respq.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect respq.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect respq.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect respq.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect respq.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect respq.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect respq.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect respq.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect respq.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect respq.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect respq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect respq.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect respq.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect respq.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect respq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect respq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect respq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect respq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect respq.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect respq.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect respq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect respq.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect respq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect respq.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect respq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect respq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect respq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect respq.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect respq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect respq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect respq.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect respq.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect respq.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect respq.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect respq.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect respq.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect respq.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect respq.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect respq.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect respq.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect respq.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect respq.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect respq.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect respq.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect respq.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect respq.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect respq.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect respq.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect respq.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect respq.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect respq.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect respq.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect respq.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect respq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect respq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect respq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect respq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect respq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect respq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect respq.io.flush, io.exception connect respq.io.enq, resp_arb.io.out connect io.resp.bits, respq.io.deq.bits connect io.resp.valid, respq.io.deq.valid connect respq.io.deq.ready, io.resp.ready node _io_req_0_ready_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _io_req_0_ready_T_1 = eq(cacheable, UInt<1>(0h0)) node _io_req_0_ready_T_2 = and(tag_match[0], _T_11) node _io_req_0_ready_T_3 = mux(idx_match[0], _io_req_0_ready_T_2, pri_rdy) node _io_req_0_ready_T_4 = and(sdq_rdy, _io_req_0_ready_T_3) node _io_req_0_ready_T_5 = mux(_io_req_0_ready_T_1, _T_17, _io_req_0_ready_T_4) node _io_req_0_ready_T_6 = and(_io_req_0_ready_T, _io_req_0_ready_T_5) connect io.req[0].ready, _io_req_0_ready_T_6 node _io_secondary_miss_0_T = and(idx_match[0], way_match[0]) node _io_secondary_miss_0_T_1 = eq(tag_match[0], UInt<1>(0h0)) node _io_secondary_miss_0_T_2 = and(_io_secondary_miss_0_T, _io_secondary_miss_0_T_1) connect io.secondary_miss[0], _io_secondary_miss_0_T_2 node _io_block_hit_0_T = and(idx_match[0], tag_match[0]) connect io.block_hit[0], _io_block_hit_0_T connect io.refill.bits, refill_arb.io.out.bits connect io.refill.valid, refill_arb.io.out.valid connect refill_arb.io.out.ready, io.refill.ready node _free_sdq_T = and(io.replay.ready, io.replay.valid) node _free_sdq_T_1 = eq(io.replay.bits.uop.mem_cmd, UInt<1>(0h1)) node _free_sdq_T_2 = eq(io.replay.bits.uop.mem_cmd, UInt<5>(0h11)) node _free_sdq_T_3 = or(_free_sdq_T_1, _free_sdq_T_2) node _free_sdq_T_4 = eq(io.replay.bits.uop.mem_cmd, UInt<3>(0h7)) node _free_sdq_T_5 = or(_free_sdq_T_3, _free_sdq_T_4) node _free_sdq_T_6 = eq(io.replay.bits.uop.mem_cmd, UInt<3>(0h4)) node _free_sdq_T_7 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0h9)) node _free_sdq_T_8 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0ha)) node _free_sdq_T_9 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hb)) node _free_sdq_T_10 = or(_free_sdq_T_6, _free_sdq_T_7) node _free_sdq_T_11 = or(_free_sdq_T_10, _free_sdq_T_8) node _free_sdq_T_12 = or(_free_sdq_T_11, _free_sdq_T_9) node _free_sdq_T_13 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0h8)) node _free_sdq_T_14 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hc)) node _free_sdq_T_15 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hd)) node _free_sdq_T_16 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0he)) node _free_sdq_T_17 = eq(io.replay.bits.uop.mem_cmd, UInt<4>(0hf)) node _free_sdq_T_18 = or(_free_sdq_T_13, _free_sdq_T_14) node _free_sdq_T_19 = or(_free_sdq_T_18, _free_sdq_T_15) node _free_sdq_T_20 = or(_free_sdq_T_19, _free_sdq_T_16) node _free_sdq_T_21 = or(_free_sdq_T_20, _free_sdq_T_17) node _free_sdq_T_22 = or(_free_sdq_T_12, _free_sdq_T_21) node _free_sdq_T_23 = or(_free_sdq_T_5, _free_sdq_T_22) node free_sdq = and(_free_sdq_T, _free_sdq_T_23) connect io.replay.bits, replay_arb.io.out.bits connect io.replay.valid, replay_arb.io.out.valid connect replay_arb.io.out.ready, io.replay.ready infer mport io_replay_bits_data_MPORT = sdq[replay_arb.io.out.bits.sdq_id], clock connect io.replay.bits.data, io_replay_bits_data_MPORT node _T_63 = or(io.replay.valid, sdq_enq) when _T_63 : node _sdq_val_T = dshl(UInt<1>(0h1), replay_arb.io.out.bits.sdq_id) node _sdq_val_T_1 = mux(free_sdq, UInt<17>(0h1ffff), UInt<17>(0h0)) node _sdq_val_T_2 = and(_sdq_val_T, _sdq_val_T_1) node _sdq_val_T_3 = not(_sdq_val_T_2) node _sdq_val_T_4 = and(sdq_val, _sdq_val_T_3) node _sdq_val_T_5 = bits(sdq_val, 16, 0) node _sdq_val_T_6 = not(_sdq_val_T_5) node _sdq_val_T_7 = bits(_sdq_val_T_6, 0, 0) node _sdq_val_T_8 = bits(_sdq_val_T_6, 1, 1) node _sdq_val_T_9 = bits(_sdq_val_T_6, 2, 2) node _sdq_val_T_10 = bits(_sdq_val_T_6, 3, 3) node _sdq_val_T_11 = bits(_sdq_val_T_6, 4, 4) node _sdq_val_T_12 = bits(_sdq_val_T_6, 5, 5) node _sdq_val_T_13 = bits(_sdq_val_T_6, 6, 6) node _sdq_val_T_14 = bits(_sdq_val_T_6, 7, 7) node _sdq_val_T_15 = bits(_sdq_val_T_6, 8, 8) node _sdq_val_T_16 = bits(_sdq_val_T_6, 9, 9) node _sdq_val_T_17 = bits(_sdq_val_T_6, 10, 10) node _sdq_val_T_18 = bits(_sdq_val_T_6, 11, 11) node _sdq_val_T_19 = bits(_sdq_val_T_6, 12, 12) node _sdq_val_T_20 = bits(_sdq_val_T_6, 13, 13) node _sdq_val_T_21 = bits(_sdq_val_T_6, 14, 14) node _sdq_val_T_22 = bits(_sdq_val_T_6, 15, 15) node _sdq_val_T_23 = bits(_sdq_val_T_6, 16, 16) node _sdq_val_T_24 = mux(_sdq_val_T_23, UInt<17>(0h10000), UInt<17>(0h0)) node _sdq_val_T_25 = mux(_sdq_val_T_22, UInt<17>(0h8000), _sdq_val_T_24) node _sdq_val_T_26 = mux(_sdq_val_T_21, UInt<17>(0h4000), _sdq_val_T_25) node _sdq_val_T_27 = mux(_sdq_val_T_20, UInt<17>(0h2000), _sdq_val_T_26) node _sdq_val_T_28 = mux(_sdq_val_T_19, UInt<17>(0h1000), _sdq_val_T_27) node _sdq_val_T_29 = mux(_sdq_val_T_18, UInt<17>(0h800), _sdq_val_T_28) node _sdq_val_T_30 = mux(_sdq_val_T_17, UInt<17>(0h400), _sdq_val_T_29) node _sdq_val_T_31 = mux(_sdq_val_T_16, UInt<17>(0h200), _sdq_val_T_30) node _sdq_val_T_32 = mux(_sdq_val_T_15, UInt<17>(0h100), _sdq_val_T_31) node _sdq_val_T_33 = mux(_sdq_val_T_14, UInt<17>(0h80), _sdq_val_T_32) node _sdq_val_T_34 = mux(_sdq_val_T_13, UInt<17>(0h40), _sdq_val_T_33) node _sdq_val_T_35 = mux(_sdq_val_T_12, UInt<17>(0h20), _sdq_val_T_34) node _sdq_val_T_36 = mux(_sdq_val_T_11, UInt<17>(0h10), _sdq_val_T_35) node _sdq_val_T_37 = mux(_sdq_val_T_10, UInt<17>(0h8), _sdq_val_T_36) node _sdq_val_T_38 = mux(_sdq_val_T_9, UInt<17>(0h4), _sdq_val_T_37) node _sdq_val_T_39 = mux(_sdq_val_T_8, UInt<17>(0h2), _sdq_val_T_38) node _sdq_val_T_40 = mux(_sdq_val_T_7, UInt<17>(0h1), _sdq_val_T_39) node _sdq_val_T_41 = mux(sdq_enq, UInt<17>(0h1ffff), UInt<17>(0h0)) node _sdq_val_T_42 = and(_sdq_val_T_40, _sdq_val_T_41) node _sdq_val_T_43 = or(_sdq_val_T_4, _sdq_val_T_42) connect sdq_val, _sdq_val_T_43 reg prefetcher_io_mshr_avail_REG : UInt<1>, clock connect prefetcher_io_mshr_avail_REG, pri_rdy connect prefetcher.io.mshr_avail, prefetcher_io_mshr_avail_REG node _prefetcher_io_req_val_T = or(commit_vals[0], commit_vals[1]) reg prefetcher_io_req_val_REG : UInt<1>, clock connect prefetcher_io_req_val_REG, _prefetcher_io_req_val_T connect prefetcher.io.req_val, prefetcher_io_req_val_REG node _prefetcher_io_req_addr_T = mux(commit_vals[0], commit_addrs[0], UInt<1>(0h0)) node _prefetcher_io_req_addr_T_1 = mux(commit_vals[1], commit_addrs[1], UInt<1>(0h0)) node _prefetcher_io_req_addr_T_2 = or(_prefetcher_io_req_addr_T, _prefetcher_io_req_addr_T_1) wire _prefetcher_io_req_addr_WIRE : UInt<40> connect _prefetcher_io_req_addr_WIRE, _prefetcher_io_req_addr_T_2 reg prefetcher_io_req_addr_REG : UInt, clock connect prefetcher_io_req_addr_REG, _prefetcher_io_req_addr_WIRE connect prefetcher.io.req_addr, prefetcher_io_req_addr_REG wire _prefetcher_io_req_coh_WIRE : { state : UInt<2>} node _prefetcher_io_req_coh_T = mux(commit_vals[0], commit_cohs[0].state, UInt<1>(0h0)) node _prefetcher_io_req_coh_T_1 = mux(commit_vals[1], commit_cohs[1].state, UInt<1>(0h0)) node _prefetcher_io_req_coh_T_2 = or(_prefetcher_io_req_coh_T, _prefetcher_io_req_coh_T_1) wire _prefetcher_io_req_coh_WIRE_1 : UInt<2> connect _prefetcher_io_req_coh_WIRE_1, _prefetcher_io_req_coh_T_2 connect _prefetcher_io_req_coh_WIRE.state, _prefetcher_io_req_coh_WIRE_1 reg prefetcher_io_req_coh_REG : { state : UInt<2>}, clock connect prefetcher_io_req_coh_REG, _prefetcher_io_req_coh_WIRE connect prefetcher.io.req_coh.state, prefetcher_io_req_coh_REG.state

module BoomMSHRFile( // @[mshrs.scala:498:7] input clock, // @[mshrs.scala:498:7] input reset, // @[mshrs.scala:498:7] output io_req_0_ready, // @[mshrs.scala:501:14] input io_req_0_valid, // @[mshrs.scala:501:14] input [31:0] io_req_0_bits_uop_inst, // @[mshrs.scala:501:14] input [31:0] io_req_0_bits_uop_debug_inst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_rvc, // @[mshrs.scala:501:14] input [39:0] io_req_0_bits_uop_debug_pc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_0, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_0, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_4, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_5, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_6, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_7, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_8, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_9, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] input [11:0] io_req_0_bits_uop_br_mask, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_br_tag, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_br_type, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sfb, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_fence, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_fencei, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sfence, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_amo, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_eret, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_rocc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_mov, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_ftq_idx, // @[mshrs.scala:501:14] input io_req_0_bits_uop_edge_inst, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_pc_lob, // @[mshrs.scala:501:14] input io_req_0_bits_uop_taken, // @[mshrs.scala:501:14] input io_req_0_bits_uop_imm_rename, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_imm_sel, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_pimm, // @[mshrs.scala:501:14] input [19:0] io_req_0_bits_uop_imm_packed, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_op1_sel, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_op2_sel, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_rob_idx, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_ldq_idx, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_stq_idx, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_rxq_idx, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_pdst, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs1, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs2, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs3, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_ppred, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs1_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs2_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs3_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_ppred_busy, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_stale_pdst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_exception, // @[mshrs.scala:501:14] input [63:0] io_req_0_bits_uop_exc_cause, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_mem_cmd, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_mem_size, // @[mshrs.scala:501:14] input io_req_0_bits_uop_mem_signed, // @[mshrs.scala:501:14] input io_req_0_bits_uop_uses_ldq, // @[mshrs.scala:501:14] input io_req_0_bits_uop_uses_stq, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_unique, // @[mshrs.scala:501:14] input io_req_0_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_csr_cmd, // @[mshrs.scala:501:14] input io_req_0_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_ldst, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs1, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs2, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs3, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_dst_rtype, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] input io_req_0_bits_uop_frs3_en, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fcn_dw, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_fcn_op, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_val, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_fp_rm, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_typ, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] input [39:0] io_req_0_bits_addr, // @[mshrs.scala:501:14] input [63:0] io_req_0_bits_data, // @[mshrs.scala:501:14] input io_req_0_bits_is_hella, // @[mshrs.scala:501:14] input io_req_0_bits_tag_match, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_old_meta_coh_state, // @[mshrs.scala:501:14] input [19:0] io_req_0_bits_old_meta_tag, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_way_en, // @[mshrs.scala:501:14] input io_req_is_probe_0, // @[mshrs.scala:501:14] input io_resp_ready, // @[mshrs.scala:501:14] output io_resp_valid, // @[mshrs.scala:501:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:501:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:501:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] output [11:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sfence, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_eret, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_rocc, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_mov, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:501:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:501:14] output io_resp_bits_uop_taken, // @[mshrs.scala:501:14] output io_resp_bits_uop_imm_rename, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:501:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:501:14] output io_resp_bits_uop_exception, // @[mshrs.scala:501:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:501:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:501:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:501:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:501:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:501:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:501:14] output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:501:14] output io_resp_bits_is_hella, // @[mshrs.scala:501:14] output io_secondary_miss_0, // @[mshrs.scala:501:14] output io_block_hit_0, // @[mshrs.scala:501:14] input [11:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:501:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:501:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:501:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:501:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_0, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_0, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_4, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_5, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_6, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_7, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_8, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_9, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[mshrs.scala:501:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_br_type, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sfence, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_eret, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_rocc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_mov, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_imm_rename, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_pimm, // @[mshrs.scala:501:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:501:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fcn_dw, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:501:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:501:14] input io_brupdate_b2_taken, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:501:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:501:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:501:14] input io_exception, // @[mshrs.scala:501:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:501:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:501:14] input io_mem_acquire_ready, // @[mshrs.scala:501:14] output io_mem_acquire_valid, // @[mshrs.scala:501:14] output [2:0] io_mem_acquire_bits_opcode, // @[mshrs.scala:501:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:501:14] output [3:0] io_mem_acquire_bits_size, // @[mshrs.scala:501:14] output [1:0] io_mem_acquire_bits_source, // @[mshrs.scala:501:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:501:14] output [7:0] io_mem_acquire_bits_mask, // @[mshrs.scala:501:14] output [63:0] io_mem_acquire_bits_data, // @[mshrs.scala:501:14] output io_mem_grant_ready, // @[mshrs.scala:501:14] input io_mem_grant_valid, // @[mshrs.scala:501:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:501:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:501:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:501:14] input [1:0] io_mem_grant_bits_source, // @[mshrs.scala:501:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:501:14] input io_mem_grant_bits_denied, // @[mshrs.scala:501:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:501:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:501:14] input io_mem_finish_ready, // @[mshrs.scala:501:14] output io_mem_finish_valid, // @[mshrs.scala:501:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:501:14] input io_refill_ready, // @[mshrs.scala:501:14] output io_refill_valid, // @[mshrs.scala:501:14] output [3:0] io_refill_bits_way_en, // @[mshrs.scala:501:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:501:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:501:14] input io_meta_write_ready, // @[mshrs.scala:501:14] output io_meta_write_valid, // @[mshrs.scala:501:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:501:14] output [3:0] io_meta_write_bits_way_en, // @[mshrs.scala:501:14] output [19:0] io_meta_write_bits_tag, // @[mshrs.scala:501:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:501:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:501:14] input io_meta_read_ready, // @[mshrs.scala:501:14] output io_meta_read_valid, // @[mshrs.scala:501:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:501:14] output [3:0] io_meta_read_bits_way_en, // @[mshrs.scala:501:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:501:14] input io_meta_resp_valid, // @[mshrs.scala:501:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:501:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:501:14] input io_replay_ready, // @[mshrs.scala:501:14] output io_replay_valid, // @[mshrs.scala:501:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:501:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:501:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] output [11:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sfence, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_eret, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_rocc, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_mov, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:501:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:501:14] output io_replay_bits_uop_taken, // @[mshrs.scala:501:14] output io_replay_bits_uop_imm_rename, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:501:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:501:14] output io_replay_bits_uop_exception, // @[mshrs.scala:501:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:501:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:501:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:501:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:501:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:501:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:501:14] output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:501:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:501:14] output io_replay_bits_is_hella, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_way_en, // @[mshrs.scala:501:14] input io_prefetch_ready, // @[mshrs.scala:501:14] input io_wb_req_ready, // @[mshrs.scala:501:14] output io_wb_req_valid, // @[mshrs.scala:501:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:501:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:501:14] output [1:0] io_wb_req_bits_source, // @[mshrs.scala:501:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:501:14] output [3:0] io_wb_req_bits_way_en, // @[mshrs.scala:501:14] input io_prober_state_valid, // @[mshrs.scala:501:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:501:14] input io_clear_all, // @[mshrs.scala:501:14] input io_wb_resp, // @[mshrs.scala:501:14] output io_fence_rdy, // @[mshrs.scala:501:14] output io_probe_rdy // @[mshrs.scala:501:14] ); wire io_req_0_ready_0; // @[mshrs.scala:498:7] wire _respq_io_enq_ready; // @[mshrs.scala:720:21] wire _mmios_0_io_req_ready; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_valid; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_resp_bits_uop_inst; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_resp_bits_uop_debug_inst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_rvc; // @[mshrs.scala:693:22] wire [39:0] _mmios_0_io_resp_bits_uop_debug_pc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:693:22] wire [11:0] _mmios_0_io_resp_bits_uop_br_mask; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_br_tag; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_br_type; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sfb; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_fence; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_fencei; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sfence; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_amo; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_eret; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_rocc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_mov; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_edge_inst; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_pc_lob; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_taken; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_imm_rename; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_imm_sel; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_pimm; // @[mshrs.scala:693:22] wire [19:0] _mmios_0_io_resp_bits_uop_imm_packed; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_op1_sel; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_op2_sel; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_rob_idx; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_stq_idx; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_pdst; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs1; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs2; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs3; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_ppred; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_exception; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_resp_bits_uop_exc_cause; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_mem_size; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_mem_signed; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_uses_stq; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_unique; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_ldst; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs1; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs2; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs3; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_frs3_en; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_fcn_op; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_val; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_fp_rm; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_typ; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_resp_bits_data; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_is_hella; // @[mshrs.scala:693:22] wire _mmios_0_io_mem_access_valid; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_mem_access_bits_opcode; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_mem_access_bits_param; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_mem_access_bits_size; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_mem_access_bits_source; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_mem_access_bits_address; // @[mshrs.scala:693:22] wire [7:0] _mmios_0_io_mem_access_bits_mask; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_mem_access_bits_data; // @[mshrs.scala:693:22] wire _mmio_alloc_arb_io_in_0_ready; // @[mshrs.scala:686:30] wire _mshrs_1_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_1_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_1_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_way_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_1_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_1_io_refill_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_1_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_1_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_1_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_1_io_lb_write_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_1_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_1_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_1_io_probe_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_way_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_0_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_0_io_refill_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_0_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_0_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_0_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_0_io_lb_write_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_0_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [11:0] _mshrs_0_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_0_io_probe_rdy; // @[mshrs.scala:602:22] wire _refill_arb_io_in_0_ready; // @[mshrs.scala:586:30] wire _refill_arb_io_in_1_ready; // @[mshrs.scala:586:30] wire _resp_arb_io_in_0_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_1_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_2_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_out_valid; // @[mshrs.scala:585:30] wire [31:0] _resp_arb_io_out_bits_uop_inst; // @[mshrs.scala:585:30] wire [31:0] _resp_arb_io_out_bits_uop_debug_inst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_rvc; // @[mshrs.scala:585:30] wire [39:0] _resp_arb_io_out_bits_uop_debug_pc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_0; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_0; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_4; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_5; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_6; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_7; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_8; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_9; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_dis_col_sel; // @[mshrs.scala:585:30] wire [11:0] _resp_arb_io_out_bits_uop_br_mask; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_br_tag; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_br_type; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sfb; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_fence; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_fencei; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sfence; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_amo; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_eret; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sys_pc2epc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_rocc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_mov; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_ftq_idx; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_edge_inst; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_pc_lob; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_taken; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_imm_rename; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_imm_sel; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_pimm; // @[mshrs.scala:585:30] wire [19:0] _resp_arb_io_out_bits_uop_imm_packed; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_op1_sel; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_op2_sel; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_wen; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_toint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fma; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_div; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_vec; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_rob_idx; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_ldq_idx; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_stq_idx; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_rxq_idx; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_pdst; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs1; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs2; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs3; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_ppred; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs1_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs2_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs3_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_ppred_busy; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_stale_pdst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_exception; // @[mshrs.scala:585:30] wire [63:0] _resp_arb_io_out_bits_uop_exc_cause; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_mem_cmd; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_mem_size; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_mem_signed; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_uses_ldq; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_uses_stq; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_unique; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_flush_on_commit; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_csr_cmd; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_ldst_is_rs1; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_ldst; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs1; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs2; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs3; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_dst_rtype; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_lrs1_rtype; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_lrs2_rtype; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_frs3_en; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fcn_dw; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_fcn_op; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_val; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_fp_rm; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_typ; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_pf_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_ae_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_ma_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_bp_debug_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_bp_xcpt_if; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_debug_fsrc; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_debug_tsrc; // @[mshrs.scala:585:30] wire [63:0] _resp_arb_io_out_bits_data; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_is_hella; // @[mshrs.scala:585:30] wire _replay_arb_io_in_0_ready; // @[mshrs.scala:584:30] wire _replay_arb_io_in_1_ready; // @[mshrs.scala:584:30] wire [4:0] _replay_arb_io_out_bits_sdq_id; // @[mshrs.scala:584:30] wire _wb_req_arb_io_in_0_ready; // @[mshrs.scala:583:30] wire _wb_req_arb_io_in_1_ready; // @[mshrs.scala:583:30] wire _meta_read_arb_io_in_0_ready; // @[mshrs.scala:582:30] wire _meta_read_arb_io_in_1_ready; // @[mshrs.scala:582:30] wire _meta_write_arb_io_in_0_ready; // @[mshrs.scala:581:30] wire _meta_write_arb_io_in_1_ready; // @[mshrs.scala:581:30] wire io_req_0_valid_0 = io_req_0_valid; // @[mshrs.scala:498:7] wire [31:0] io_req_0_bits_uop_inst_0 = io_req_0_bits_uop_inst; // @[mshrs.scala:498:7] wire [31:0] io_req_0_bits_uop_debug_inst_0 = io_req_0_bits_uop_debug_inst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_rvc_0 = io_req_0_bits_uop_is_rvc; // @[mshrs.scala:498:7] wire [39:0] io_req_0_bits_uop_debug_pc_0 = io_req_0_bits_uop_debug_pc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_0_0 = io_req_0_bits_uop_iq_type_0; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_1_0 = io_req_0_bits_uop_iq_type_1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_2_0 = io_req_0_bits_uop_iq_type_2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_3_0 = io_req_0_bits_uop_iq_type_3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_0_0 = io_req_0_bits_uop_fu_code_0; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_1_0 = io_req_0_bits_uop_fu_code_1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_2_0 = io_req_0_bits_uop_fu_code_2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_3_0 = io_req_0_bits_uop_fu_code_3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_4_0 = io_req_0_bits_uop_fu_code_4; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_5_0 = io_req_0_bits_uop_fu_code_5; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_6_0 = io_req_0_bits_uop_fu_code_6; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_7_0 = io_req_0_bits_uop_fu_code_7; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_8_0 = io_req_0_bits_uop_fu_code_8; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_9_0 = io_req_0_bits_uop_fu_code_9; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_0 = io_req_0_bits_uop_iw_issued; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_partial_agen_0 = io_req_0_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_partial_dgen_0 = io_req_0_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_iw_p1_speculative_child_0 = io_req_0_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_iw_p2_speculative_child_0 = io_req_0_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p1_bypass_hint_0 = io_req_0_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p2_bypass_hint_0 = io_req_0_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p3_bypass_hint_0 = io_req_0_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_dis_col_sel_0 = io_req_0_bits_uop_dis_col_sel; // @[mshrs.scala:498:7] wire [11:0] io_req_0_bits_uop_br_mask_0 = io_req_0_bits_uop_br_mask; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_br_tag_0 = io_req_0_bits_uop_br_tag; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_br_type_0 = io_req_0_bits_uop_br_type; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sfb_0 = io_req_0_bits_uop_is_sfb; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_fence_0 = io_req_0_bits_uop_is_fence; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_fencei_0 = io_req_0_bits_uop_is_fencei; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sfence_0 = io_req_0_bits_uop_is_sfence; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_amo_0 = io_req_0_bits_uop_is_amo; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_eret_0 = io_req_0_bits_uop_is_eret; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sys_pc2epc_0 = io_req_0_bits_uop_is_sys_pc2epc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_rocc_0 = io_req_0_bits_uop_is_rocc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_mov_0 = io_req_0_bits_uop_is_mov; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_ftq_idx_0 = io_req_0_bits_uop_ftq_idx; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_edge_inst_0 = io_req_0_bits_uop_edge_inst; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_pc_lob_0 = io_req_0_bits_uop_pc_lob; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_taken_0 = io_req_0_bits_uop_taken; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_imm_rename_0 = io_req_0_bits_uop_imm_rename; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_imm_sel_0 = io_req_0_bits_uop_imm_sel; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_pimm_0 = io_req_0_bits_uop_pimm; // @[mshrs.scala:498:7] wire [19:0] io_req_0_bits_uop_imm_packed_0 = io_req_0_bits_uop_imm_packed; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_op1_sel_0 = io_req_0_bits_uop_op1_sel; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_op2_sel_0 = io_req_0_bits_uop_op2_sel; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ldst_0 = io_req_0_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_wen_0 = io_req_0_bits_uop_fp_ctrl_wen; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren1_0 = io_req_0_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren2_0 = io_req_0_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren3_0 = io_req_0_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_swap12_0 = io_req_0_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_swap23_0 = io_req_0_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_ctrl_typeTagIn_0 = io_req_0_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_ctrl_typeTagOut_0 = io_req_0_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fromint_0 = io_req_0_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_toint_0 = io_req_0_bits_uop_fp_ctrl_toint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fastpipe_0 = io_req_0_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fma_0 = io_req_0_bits_uop_fp_ctrl_fma; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_div_0 = io_req_0_bits_uop_fp_ctrl_div; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_sqrt_0 = io_req_0_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_wflags_0 = io_req_0_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_vec_0 = io_req_0_bits_uop_fp_ctrl_vec; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_rob_idx_0 = io_req_0_bits_uop_rob_idx; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_ldq_idx_0 = io_req_0_bits_uop_ldq_idx; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_stq_idx_0 = io_req_0_bits_uop_stq_idx; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_rxq_idx_0 = io_req_0_bits_uop_rxq_idx; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_pdst_0 = io_req_0_bits_uop_pdst; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs1_0 = io_req_0_bits_uop_prs1; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs2_0 = io_req_0_bits_uop_prs2; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs3_0 = io_req_0_bits_uop_prs3; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_ppred_0 = io_req_0_bits_uop_ppred; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs1_busy_0 = io_req_0_bits_uop_prs1_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs2_busy_0 = io_req_0_bits_uop_prs2_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs3_busy_0 = io_req_0_bits_uop_prs3_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_ppred_busy_0 = io_req_0_bits_uop_ppred_busy; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_stale_pdst_0 = io_req_0_bits_uop_stale_pdst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_exception_0 = io_req_0_bits_uop_exception; // @[mshrs.scala:498:7] wire [63:0] io_req_0_bits_uop_exc_cause_0 = io_req_0_bits_uop_exc_cause; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_mem_cmd_0 = io_req_0_bits_uop_mem_cmd; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_mem_size_0 = io_req_0_bits_uop_mem_size; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_mem_signed_0 = io_req_0_bits_uop_mem_signed; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_uses_ldq_0 = io_req_0_bits_uop_uses_ldq; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_uses_stq_0 = io_req_0_bits_uop_uses_stq; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_unique_0 = io_req_0_bits_uop_is_unique; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_flush_on_commit_0 = io_req_0_bits_uop_flush_on_commit; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_csr_cmd_0 = io_req_0_bits_uop_csr_cmd; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_ldst_is_rs1_0 = io_req_0_bits_uop_ldst_is_rs1; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_ldst_0 = io_req_0_bits_uop_ldst; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs1_0 = io_req_0_bits_uop_lrs1; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs2_0 = io_req_0_bits_uop_lrs2; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs3_0 = io_req_0_bits_uop_lrs3; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_dst_rtype_0 = io_req_0_bits_uop_dst_rtype; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_lrs1_rtype_0 = io_req_0_bits_uop_lrs1_rtype; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_lrs2_rtype_0 = io_req_0_bits_uop_lrs2_rtype; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_frs3_en_0 = io_req_0_bits_uop_frs3_en; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fcn_dw_0 = io_req_0_bits_uop_fcn_dw; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_fcn_op_0 = io_req_0_bits_uop_fcn_op; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_val_0 = io_req_0_bits_uop_fp_val; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_fp_rm_0 = io_req_0_bits_uop_fp_rm; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_typ_0 = io_req_0_bits_uop_fp_typ; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_pf_if_0 = io_req_0_bits_uop_xcpt_pf_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_ae_if_0 = io_req_0_bits_uop_xcpt_ae_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_ma_if_0 = io_req_0_bits_uop_xcpt_ma_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_bp_debug_if_0 = io_req_0_bits_uop_bp_debug_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_bp_xcpt_if_0 = io_req_0_bits_uop_bp_xcpt_if; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_debug_fsrc_0 = io_req_0_bits_uop_debug_fsrc; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_debug_tsrc_0 = io_req_0_bits_uop_debug_tsrc; // @[mshrs.scala:498:7] wire [39:0] io_req_0_bits_addr_0 = io_req_0_bits_addr; // @[mshrs.scala:498:7] wire [63:0] io_req_0_bits_data_0 = io_req_0_bits_data; // @[mshrs.scala:498:7] wire io_req_0_bits_is_hella_0 = io_req_0_bits_is_hella; // @[mshrs.scala:498:7] wire io_req_0_bits_tag_match_0 = io_req_0_bits_tag_match; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_old_meta_coh_state_0 = io_req_0_bits_old_meta_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_req_0_bits_old_meta_tag_0 = io_req_0_bits_old_meta_tag; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_way_en_0 = io_req_0_bits_way_en; // @[mshrs.scala:498:7] wire io_req_is_probe_0_0 = io_req_is_probe_0; // @[mshrs.scala:498:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:498:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:498:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:498:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:498:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:498:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[mshrs.scala:498:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[mshrs.scala:498:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:498:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:498:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:498:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:498:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:498:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:498:7] wire io_exception_0 = io_exception; // @[mshrs.scala:498:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:498:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:498:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:498:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:498:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:498:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:498:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:498:7] wire [1:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:498:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:498:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:498:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:498:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:498:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:498:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:498:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:498:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:498:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:498:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:498:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:498:7] wire io_prefetch_ready_0 = io_prefetch_ready; // @[mshrs.scala:498:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:498:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:498:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:498:7] wire io_clear_all_0 = io_clear_all; // @[mshrs.scala:498:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:498:7] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:498:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:498:7] wire _cacheable_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _cacheable_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _mshr_alloc_idx_temp_vec_T_1 = 1'h1; // @[util.scala:352:72] wire _opdata_T = 1'h1; // @[Edges.scala:92:37] wire _opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _io_req_0_ready_T = 1'h1; // @[mshrs.scala:498:7, :727:34] wire [4:0] io_req_0_bits_sdq_id = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_ftq_idx = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_pimm = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_ppred = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_mem_cmd = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_fcn_op = 5'h0; // @[mshrs.scala:498:7] wire [4:0] req_bits_sdq_id = 5'h0; // @[mshrs.scala:536:25] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_valid = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_rvc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_0 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_0 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_4 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_5 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_6 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_7 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_8 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_9 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued_partial_agen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued_partial_dgen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p1_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p2_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p3_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sfb = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_fence = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_fencei = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sfence = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_amo = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_eret = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_rocc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_mov = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_edge_inst = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_taken = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_imm_rename = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ldst = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_wen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_swap12 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_swap23 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fromint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_toint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fma = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_div = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_sqrt = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_wflags = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_vec = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs1_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs2_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs3_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_ppred_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_exception = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_mem_signed = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_uses_ldq = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_uses_stq = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_unique = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_flush_on_commit = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_frs3_en = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fcn_dw = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_val = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_bp_debug_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_is_hella = 1'h0; // @[mshrs.scala:498:7] wire _cacheable_T = 1'h0; // @[Parameters.scala:684:29] wire _cacheable_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _cacheable_T_33 = 1'h0; // @[Parameters.scala:686:26] wire opdata = 1'h0; // @[Edges.scala:92:28] wire opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34] wire _io_mem_acquire_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_3 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_4 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire maskedBeats_0_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1_1 = 1'h0; // @[Arbiter.scala:82:69] wire initBeats_1 = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire [31:0] io_prefetch_bits_uop_inst = 32'h0; // @[mshrs.scala:498:7] wire [31:0] io_prefetch_bits_uop_debug_inst = 32'h0; // @[mshrs.scala:498:7] wire [39:0] io_prefetch_bits_uop_debug_pc = 40'h0; // @[mshrs.scala:498:7] wire [39:0] io_prefetch_bits_addr = 40'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_iw_p1_speculative_child = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_iw_p2_speculative_child = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_dis_col_sel = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_op1_sel = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_rxq_idx = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_mem_size = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_dst_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_typ = 2'h0; // @[mshrs.scala:498:7] wire [1:0] _io_mem_acquire_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [11:0] io_prefetch_bits_uop_br_mask = 12'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_br_tag = 4'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_br_type = 4'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_ldq_idx = 4'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_stq_idx = 4'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_pc_lob = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_rob_idx = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_ldst = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs1 = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs2 = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs3 = 6'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_imm_sel = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_op2_sel = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_csr_cmd = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_fp_rm = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_debug_fsrc = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_debug_tsrc = 3'h0; // @[mshrs.scala:498:7] wire [19:0] io_prefetch_bits_uop_imm_packed = 20'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_pdst = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs1 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs2 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs3 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_stale_pdst = 7'h0; // @[mshrs.scala:498:7] wire [63:0] io_prefetch_bits_uop_exc_cause = 64'h0; // @[mshrs.scala:498:7] wire [63:0] io_prefetch_bits_data = 64'h0; // @[mshrs.scala:498:7] wire [63:0] _io_mem_acquire_bits_T_5 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_6 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_8 = 64'h0; // @[Mux.scala:30:73] wire [8:0] maskedBeats_0 = 9'h0; // @[Arbiter.scala:82:69] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [8:0] _initBeats_T = 9'h0; // @[Arbiter.scala:84:44] wire [8:0] decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire _io_req_0_ready_T_6; // @[mshrs.scala:727:47] wire req_ready = io_req_0_ready_0; // @[mshrs.scala:498:7, :536:25] wire req_valid = io_req_0_valid_0; // @[mshrs.scala:498:7, :536:25] wire [31:0] req_bits_uop_inst = io_req_0_bits_uop_inst_0; // @[mshrs.scala:498:7, :536:25] wire [31:0] req_bits_uop_debug_inst = io_req_0_bits_uop_debug_inst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_rvc = io_req_0_bits_uop_is_rvc_0; // @[mshrs.scala:498:7, :536:25] wire [39:0] req_bits_uop_debug_pc = io_req_0_bits_uop_debug_pc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_0 = io_req_0_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_1 = io_req_0_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_2 = io_req_0_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_3 = io_req_0_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_0 = io_req_0_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_1 = io_req_0_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_2 = io_req_0_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_3 = io_req_0_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_4 = io_req_0_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_5 = io_req_0_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_6 = io_req_0_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_7 = io_req_0_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_8 = io_req_0_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_9 = io_req_0_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued = io_req_0_bits_uop_iw_issued_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued_partial_agen = io_req_0_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued_partial_dgen = io_req_0_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_iw_p1_speculative_child = io_req_0_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_iw_p2_speculative_child = io_req_0_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p1_bypass_hint = io_req_0_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p2_bypass_hint = io_req_0_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p3_bypass_hint = io_req_0_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_dis_col_sel = io_req_0_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7, :536:25] wire [11:0] req_bits_uop_br_mask = io_req_0_bits_uop_br_mask_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_br_tag = io_req_0_bits_uop_br_tag_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_br_type = io_req_0_bits_uop_br_type_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sfb = io_req_0_bits_uop_is_sfb_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_fence = io_req_0_bits_uop_is_fence_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_fencei = io_req_0_bits_uop_is_fencei_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sfence = io_req_0_bits_uop_is_sfence_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_amo = io_req_0_bits_uop_is_amo_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_eret = io_req_0_bits_uop_is_eret_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sys_pc2epc = io_req_0_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_rocc = io_req_0_bits_uop_is_rocc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_mov = io_req_0_bits_uop_is_mov_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_ftq_idx = io_req_0_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_edge_inst = io_req_0_bits_uop_edge_inst_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_pc_lob = io_req_0_bits_uop_pc_lob_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_taken = io_req_0_bits_uop_taken_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_imm_rename = io_req_0_bits_uop_imm_rename_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_imm_sel = io_req_0_bits_uop_imm_sel_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_pimm = io_req_0_bits_uop_pimm_0; // @[mshrs.scala:498:7, :536:25] wire [19:0] req_bits_uop_imm_packed = io_req_0_bits_uop_imm_packed_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_op1_sel = io_req_0_bits_uop_op1_sel_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_op2_sel = io_req_0_bits_uop_op2_sel_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ldst = io_req_0_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_wen = io_req_0_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren1 = io_req_0_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren2 = io_req_0_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren3 = io_req_0_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_swap12 = io_req_0_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_swap23 = io_req_0_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_ctrl_typeTagIn = io_req_0_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_ctrl_typeTagOut = io_req_0_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fromint = io_req_0_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_toint = io_req_0_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fastpipe = io_req_0_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fma = io_req_0_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_div = io_req_0_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_sqrt = io_req_0_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_wflags = io_req_0_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_vec = io_req_0_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_rob_idx = io_req_0_bits_uop_rob_idx_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_ldq_idx = io_req_0_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_stq_idx = io_req_0_bits_uop_stq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_rxq_idx = io_req_0_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_pdst = io_req_0_bits_uop_pdst_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs1 = io_req_0_bits_uop_prs1_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs2 = io_req_0_bits_uop_prs2_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs3 = io_req_0_bits_uop_prs3_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_ppred = io_req_0_bits_uop_ppred_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs1_busy = io_req_0_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs2_busy = io_req_0_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs3_busy = io_req_0_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_ppred_busy = io_req_0_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_stale_pdst = io_req_0_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_exception = io_req_0_bits_uop_exception_0; // @[mshrs.scala:498:7, :536:25] wire [63:0] req_bits_uop_exc_cause = io_req_0_bits_uop_exc_cause_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_mem_cmd = io_req_0_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_mem_size = io_req_0_bits_uop_mem_size_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_mem_signed = io_req_0_bits_uop_mem_signed_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_uses_ldq = io_req_0_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_uses_stq = io_req_0_bits_uop_uses_stq_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_unique = io_req_0_bits_uop_is_unique_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_flush_on_commit = io_req_0_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_csr_cmd = io_req_0_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_ldst_is_rs1 = io_req_0_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_ldst = io_req_0_bits_uop_ldst_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs1 = io_req_0_bits_uop_lrs1_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs2 = io_req_0_bits_uop_lrs2_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs3 = io_req_0_bits_uop_lrs3_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_dst_rtype = io_req_0_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_lrs1_rtype = io_req_0_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_lrs2_rtype = io_req_0_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_frs3_en = io_req_0_bits_uop_frs3_en_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fcn_dw = io_req_0_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_fcn_op = io_req_0_bits_uop_fcn_op_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_val = io_req_0_bits_uop_fp_val_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_fp_rm = io_req_0_bits_uop_fp_rm_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_typ = io_req_0_bits_uop_fp_typ_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_pf_if = io_req_0_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_ae_if = io_req_0_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_ma_if = io_req_0_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_bp_debug_if = io_req_0_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_bp_xcpt_if = io_req_0_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_debug_fsrc = io_req_0_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_debug_tsrc = io_req_0_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7, :536:25] wire [39:0] req_bits_addr = io_req_0_bits_addr_0; // @[mshrs.scala:498:7, :536:25] wire [63:0] req_bits_data = io_req_0_bits_data_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_is_hella = io_req_0_bits_is_hella_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_tag_match = io_req_0_bits_tag_match_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_old_meta_coh_state = io_req_0_bits_old_meta_coh_state_0; // @[mshrs.scala:498:7, :536:25] wire [19:0] req_bits_old_meta_tag = io_req_0_bits_old_meta_tag_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_way_en = io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :536:25] wire _io_secondary_miss_0_T_2; // @[mshrs.scala:729:58] wire _io_block_hit_0_T; // @[mshrs.scala:730:42] wire _io_mem_acquire_valid_T_7; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_acquire_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_WIRE_size; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_WIRE_data; // @[Mux.scala:30:73] wire _io_mem_finish_valid_T_4; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_finish_bits_WIRE_sink; // @[Mux.scala:30:73] wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:498:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:498:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7] wire [11:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:498:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:498:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:498:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:498:7] wire io_resp_valid_0; // @[mshrs.scala:498:7] wire io_secondary_miss_0_0; // @[mshrs.scala:498:7] wire io_block_hit_0_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_acquire_bits_opcode_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:498:7] wire [3:0] io_mem_acquire_bits_size_0; // @[mshrs.scala:498:7] wire [1:0] io_mem_acquire_bits_source_0; // @[mshrs.scala:498:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:498:7] wire [7:0] io_mem_acquire_bits_mask_0; // @[mshrs.scala:498:7] wire [63:0] io_mem_acquire_bits_data_0; // @[mshrs.scala:498:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:498:7] wire io_mem_grant_ready_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:498:7] wire io_mem_finish_valid_0; // @[mshrs.scala:498:7] wire [3:0] io_refill_bits_way_en_0; // @[mshrs.scala:498:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:498:7] wire [63:0] io_refill_bits_data_0; // @[mshrs.scala:498:7] wire io_refill_valid_0; // @[mshrs.scala:498:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:498:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_write_bits_tag_0; // @[mshrs.scala:498:7] wire io_meta_write_valid_0; // @[mshrs.scala:498:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:498:7] wire io_meta_read_valid_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:498:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:498:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7] wire [11:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:498:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:498:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_old_meta_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_replay_bits_old_meta_tag; // @[mshrs.scala:498:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:498:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:498:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:498:7] wire io_replay_bits_tag_match; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_way_en_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_sdq_id; // @[mshrs.scala:498:7] wire io_replay_valid_0; // @[mshrs.scala:498:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:498:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_wb_req_bits_source_0; // @[mshrs.scala:498:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:498:7] wire [3:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:498:7] wire io_wb_req_valid_0; // @[mshrs.scala:498:7] wire io_fence_rdy_0; // @[mshrs.scala:498:7] wire io_probe_rdy_0; // @[mshrs.scala:498:7] wire [39:0] _cacheable_T_1 = req_bits_addr; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_2 = {1'h0, _cacheable_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_3 = _cacheable_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_4 = _cacheable_T_3; // @[Parameters.scala:137:46] wire _cacheable_T_5 = _cacheable_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_6 = {req_bits_addr[39:17], req_bits_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_7 = {1'h0, _cacheable_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_8 = _cacheable_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_9 = _cacheable_T_8; // @[Parameters.scala:137:46] wire _cacheable_T_10 = _cacheable_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_11 = {req_bits_addr[39:28], req_bits_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_12 = {1'h0, _cacheable_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_13 = _cacheable_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_14 = _cacheable_T_13; // @[Parameters.scala:137:46] wire _cacheable_T_15 = _cacheable_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_16 = _cacheable_T_5 | _cacheable_T_10; // @[Parameters.scala:685:42] wire _cacheable_T_17 = _cacheable_T_16 | _cacheable_T_15; // @[Parameters.scala:685:42] wire [39:0] _cacheable_T_21 = {req_bits_addr[39:28], req_bits_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_22 = {1'h0, _cacheable_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_23 = _cacheable_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_24 = _cacheable_T_23; // @[Parameters.scala:137:46] wire _cacheable_T_25 = _cacheable_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_26 = {req_bits_addr[39:32], req_bits_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_27 = {1'h0, _cacheable_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_28 = _cacheable_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_29 = _cacheable_T_28; // @[Parameters.scala:137:46] wire _cacheable_T_30 = _cacheable_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_31 = _cacheable_T_25 | _cacheable_T_30; // @[Parameters.scala:685:42] wire _cacheable_T_32 = _cacheable_T_31; // @[Parameters.scala:684:54, :685:42] wire cacheable = _cacheable_T_32; // @[Parameters.scala:684:54, :686:26] reg [16:0] sdq_val; // @[mshrs.scala:552:29] wire [16:0] _sdq_alloc_id_T = sdq_val; // @[mshrs.scala:552:29, :553:46] wire [16:0] _sdq_val_T_5 = sdq_val; // @[mshrs.scala:552:29, :741:33] wire [16:0] _sdq_alloc_id_T_1 = ~_sdq_alloc_id_T; // @[mshrs.scala:553:{38,46}] wire _sdq_alloc_id_T_2 = _sdq_alloc_id_T_1[0]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_3 = _sdq_alloc_id_T_1[1]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_4 = _sdq_alloc_id_T_1[2]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_5 = _sdq_alloc_id_T_1[3]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_6 = _sdq_alloc_id_T_1[4]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_7 = _sdq_alloc_id_T_1[5]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_8 = _sdq_alloc_id_T_1[6]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_9 = _sdq_alloc_id_T_1[7]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_10 = _sdq_alloc_id_T_1[8]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_11 = _sdq_alloc_id_T_1[9]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_12 = _sdq_alloc_id_T_1[10]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_13 = _sdq_alloc_id_T_1[11]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_14 = _sdq_alloc_id_T_1[12]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_15 = _sdq_alloc_id_T_1[13]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_16 = _sdq_alloc_id_T_1[14]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_17 = _sdq_alloc_id_T_1[15]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_18 = _sdq_alloc_id_T_1[16]; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_19 = _sdq_alloc_id_T_17 ? 5'hF : 5'h10; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_20 = _sdq_alloc_id_T_16 ? 5'hE : _sdq_alloc_id_T_19; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_21 = _sdq_alloc_id_T_15 ? 5'hD : _sdq_alloc_id_T_20; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_22 = _sdq_alloc_id_T_14 ? 5'hC : _sdq_alloc_id_T_21; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_23 = _sdq_alloc_id_T_13 ? 5'hB : _sdq_alloc_id_T_22; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_24 = _sdq_alloc_id_T_12 ? 5'hA : _sdq_alloc_id_T_23; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_25 = _sdq_alloc_id_T_11 ? 5'h9 : _sdq_alloc_id_T_24; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_26 = _sdq_alloc_id_T_10 ? 5'h8 : _sdq_alloc_id_T_25; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_27 = _sdq_alloc_id_T_9 ? 5'h7 : _sdq_alloc_id_T_26; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_28 = _sdq_alloc_id_T_8 ? 5'h6 : _sdq_alloc_id_T_27; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_29 = _sdq_alloc_id_T_7 ? 5'h5 : _sdq_alloc_id_T_28; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_30 = _sdq_alloc_id_T_6 ? 5'h4 : _sdq_alloc_id_T_29; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_31 = _sdq_alloc_id_T_5 ? 5'h3 : _sdq_alloc_id_T_30; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_32 = _sdq_alloc_id_T_4 ? 5'h2 : _sdq_alloc_id_T_31; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_33 = _sdq_alloc_id_T_3 ? 5'h1 : _sdq_alloc_id_T_32; // @[OneHot.scala:48:45] wire [4:0] sdq_alloc_id = _sdq_alloc_id_T_2 ? 5'h0 : _sdq_alloc_id_T_33; // @[OneHot.scala:48:45] wire _sdq_rdy_T = &sdq_val; // @[mshrs.scala:552:29, :554:31] wire sdq_rdy = ~_sdq_rdy_T; // @[mshrs.scala:554:{22,31}] wire _sdq_enq_T = req_ready & req_valid; // @[Decoupled.scala:51:35] wire _sdq_enq_T_1 = _sdq_enq_T & cacheable; // @[Decoupled.scala:51:35] wire _sdq_enq_T_2 = req_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _sdq_enq_T_3 = req_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _sdq_enq_T_4 = _sdq_enq_T_2 | _sdq_enq_T_3; // @[Consts.scala:90:{32,42,49}] wire _sdq_enq_T_5 = req_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _sdq_enq_T_6 = _sdq_enq_T_4 | _sdq_enq_T_5; // @[Consts.scala:90:{42,59,66}] wire _sdq_enq_T_7 = req_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _sdq_enq_T_8 = req_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _sdq_enq_T_9 = req_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _sdq_enq_T_10 = req_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _sdq_enq_T_11 = _sdq_enq_T_7 | _sdq_enq_T_8; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_12 = _sdq_enq_T_11 | _sdq_enq_T_9; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_13 = _sdq_enq_T_12 | _sdq_enq_T_10; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_14 = req_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _sdq_enq_T_15 = req_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _sdq_enq_T_16 = req_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _sdq_enq_T_17 = req_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _sdq_enq_T_18 = req_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _sdq_enq_T_19 = _sdq_enq_T_14 | _sdq_enq_T_15; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_20 = _sdq_enq_T_19 | _sdq_enq_T_16; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_21 = _sdq_enq_T_20 | _sdq_enq_T_17; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_22 = _sdq_enq_T_21 | _sdq_enq_T_18; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_23 = _sdq_enq_T_13 | _sdq_enq_T_22; // @[package.scala:81:59] wire _sdq_enq_T_24 = _sdq_enq_T_6 | _sdq_enq_T_23; // @[Consts.scala:87:44, :90:{59,76}] wire sdq_enq = _sdq_enq_T_1 & _sdq_enq_T_24; // @[Consts.scala:90:76] reg [63:0] lb_0_0; // @[mshrs.scala:565:15] reg [63:0] lb_0_1; // @[mshrs.scala:565:15] reg [63:0] lb_0_2; // @[mshrs.scala:565:15] reg [63:0] lb_0_3; // @[mshrs.scala:565:15] reg [63:0] lb_0_4; // @[mshrs.scala:565:15] reg [63:0] lb_0_5; // @[mshrs.scala:565:15] reg [63:0] lb_0_6; // @[mshrs.scala:565:15] reg [63:0] lb_0_7; // @[mshrs.scala:565:15] reg [63:0] lb_1_0; // @[mshrs.scala:565:15] reg [63:0] lb_1_1; // @[mshrs.scala:565:15] reg [63:0] lb_1_2; // @[mshrs.scala:565:15] reg [63:0] lb_1_3; // @[mshrs.scala:565:15] reg [63:0] lb_1_4; // @[mshrs.scala:565:15] reg [63:0] lb_1_5; // @[mshrs.scala:565:15] reg [63:0] lb_1_6; // @[mshrs.scala:565:15] reg [63:0] lb_1_7; // @[mshrs.scala:565:15] wire _idx_matches_0_0_T_2; // @[mshrs.scala:606:46] wire _idx_matches_0_1_T_2; // @[mshrs.scala:606:46] wire idx_matches_0_0; // @[mshrs.scala:571:25] wire idx_matches_0_1; // @[mshrs.scala:571:25] wire _tag_matches_0_0_T_2; // @[mshrs.scala:607:46] wire _tag_matches_0_1_T_2; // @[mshrs.scala:607:46] wire tag_matches_0_0; // @[mshrs.scala:572:25] wire tag_matches_0_1; // @[mshrs.scala:572:25] wire _way_matches_0_0_T_1; // @[mshrs.scala:608:46] wire _way_matches_0_1_T_1; // @[mshrs.scala:608:46] wire way_matches_0_0; // @[mshrs.scala:573:25] wire way_matches_0_1; // @[mshrs.scala:573:25] wire _tag_match_T = idx_matches_0_0 & tag_matches_0_0; // @[Mux.scala:30:73] wire _tag_match_T_1 = idx_matches_0_1 & tag_matches_0_1; // @[Mux.scala:30:73] wire _tag_match_T_2 = _tag_match_T | _tag_match_T_1; // @[Mux.scala:30:73] wire _tag_match_WIRE = _tag_match_T_2; // @[Mux.scala:30:73] wire tag_match_0 = _tag_match_WIRE; // @[Mux.scala:30:73] wire _idx_match_T = idx_matches_0_0 | idx_matches_0_1; // @[mshrs.scala:571:25, :576:58] wire idx_match_0 = _idx_match_T; // @[mshrs.scala:566:49, :576:58] wire _way_match_T = idx_matches_0_0 & way_matches_0_0; // @[Mux.scala:30:73] wire _way_match_T_1 = idx_matches_0_1 & way_matches_0_1; // @[Mux.scala:30:73] wire _way_match_T_2 = _way_match_T | _way_match_T_1; // @[Mux.scala:30:73] wire _way_match_WIRE = _way_match_T_2; // @[Mux.scala:30:73] wire way_match_0 = _way_match_WIRE; // @[Mux.scala:30:73] wire [19:0] wb_tag_list_0; // @[mshrs.scala:579:25] wire [19:0] wb_tag_list_1; // @[mshrs.scala:579:25] wire commit_vals_0; // @[mshrs.scala:588:28] wire commit_vals_1; // @[mshrs.scala:588:28] wire [39:0] commit_addrs_0; // @[mshrs.scala:589:28] wire [39:0] commit_addrs_1; // @[mshrs.scala:589:28] wire [1:0] commit_cohs_0_state; // @[mshrs.scala:590:28] wire [1:0] commit_cohs_1_state; // @[mshrs.scala:590:28] wire mshr_alloc_idx; // @[mshrs.scala:598:28] wire _mshr_io_req_pri_val_T_2 = mshr_alloc_idx; // @[mshrs.scala:598:28, :614:34] wire pri_rdy; // @[mshrs.scala:599:25] wire _GEN = req_valid & sdq_rdy; // @[mshrs.scala:536:25, :554:22, :600:27] wire _pri_val_T; // @[mshrs.scala:600:27] assign _pri_val_T = _GEN; // @[mshrs.scala:600:27] wire _mshr_io_req_sec_val_T; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T = _GEN; // @[mshrs.scala:600:27, :619:39] wire _mshr_io_req_sec_val_T_4; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T_4 = _GEN; // @[mshrs.scala:600:27, :619:39] wire _pri_val_T_1 = _pri_val_T & cacheable; // @[Parameters.scala:686:26] wire _pri_val_T_2 = ~idx_match_0; // @[mshrs.scala:566:49, :600:54] wire pri_val = _pri_val_T_1 & _pri_val_T_2; // @[mshrs.scala:600:{38,51,54}] wire [5:0] _idx_matches_0_0_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire [5:0] _idx_matches_0_1_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire _idx_matches_0_0_T_1 = _mshrs_0_io_idx_bits == _idx_matches_0_0_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_0_T_2 = _mshrs_0_io_idx_valid & _idx_matches_0_0_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_0 = _idx_matches_0_0_T_2; // @[mshrs.scala:571:25, :606:46] wire [27:0] _tag_matches_0_0_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire [27:0] _tag_matches_0_1_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire _tag_matches_0_0_T_1 = _mshrs_0_io_tag_bits == _tag_matches_0_0_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_0_T_2 = _mshrs_0_io_tag_valid & _tag_matches_0_0_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_0 = _tag_matches_0_0_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_0_T = _mshrs_0_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_0_T_1 = _mshrs_0_io_way_valid & _way_matches_0_0_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_0 = _way_matches_0_0_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T = ~mshr_alloc_idx; // @[mshrs.scala:598:28, :614:34] wire _mshr_io_req_pri_val_T_1 = _mshr_io_req_pri_val_T & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] wire _mshr_io_req_sec_val_T_1 = _mshr_io_req_sec_val_T & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_2 = _mshr_io_req_sec_val_T_1 & idx_matches_0_0; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_3 = _mshr_io_req_sec_val_T_2 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_1 = io_clear_all_0 & _mshr_io_clear_prefetch_T; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_2 = req_valid & idx_matches_0_0; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_3 = _mshr_io_clear_prefetch_T_2 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_4 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_5 = _mshr_io_clear_prefetch_T_3 & _mshr_io_clear_prefetch_T_4; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_6 = _mshr_io_clear_prefetch_T_1 | _mshr_io_clear_prefetch_T_5; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_7 = io_req_is_probe_0_0 & idx_matches_0_0; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_8 = _mshr_io_clear_prefetch_T_6 | _mshr_io_clear_prefetch_T_7; // @[mshrs.scala:626:60, :627:82, :628:21] wire [7:0][63:0] _GEN_0 = {{lb_0_7}, {lb_0_6}, {lb_0_5}, {lb_0_4}, {lb_0_3}, {lb_0_2}, {lb_0_1}, {lb_0_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_1 = io_mem_grant_bits_source_0 == 2'h0; // @[mshrs.scala:498:7, :656:36] wire _idx_matches_0_1_T_1 = _mshrs_1_io_idx_bits == _idx_matches_0_1_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_1_T_2 = _mshrs_1_io_idx_valid & _idx_matches_0_1_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_1 = _idx_matches_0_1_T_2; // @[mshrs.scala:571:25, :606:46] wire _tag_matches_0_1_T_1 = _mshrs_1_io_tag_bits == _tag_matches_0_1_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_1_T_2 = _mshrs_1_io_tag_valid & _tag_matches_0_1_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_1 = _tag_matches_0_1_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_1_T = _mshrs_1_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_1_T_1 = _mshrs_1_io_way_valid & _way_matches_0_1_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_1 = _way_matches_0_1_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T_3 = _mshr_io_req_pri_val_T_2 & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] assign pri_rdy = mshr_alloc_idx ? _mshrs_1_io_req_pri_rdy : ~mshr_alloc_idx & _mshrs_0_io_req_pri_rdy; // @[mshrs.scala:598:28, :599:25, :602:22, :614:34, :615:35, :616:15] wire _mshr_io_req_sec_val_T_5 = _mshr_io_req_sec_val_T_4 & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_6 = _mshr_io_req_sec_val_T_5 & idx_matches_0_1; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_7 = _mshr_io_req_sec_val_T_6 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_9 = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_10 = io_clear_all_0 & _mshr_io_clear_prefetch_T_9; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_11 = req_valid & idx_matches_0_1; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_12 = _mshr_io_clear_prefetch_T_11 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_13 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_14 = _mshr_io_clear_prefetch_T_12 & _mshr_io_clear_prefetch_T_13; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_15 = _mshr_io_clear_prefetch_T_10 | _mshr_io_clear_prefetch_T_14; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_16 = io_req_is_probe_0_0 & idx_matches_0_1; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_17 = _mshr_io_clear_prefetch_T_15 | _mshr_io_clear_prefetch_T_16; // @[mshrs.scala:626:60, :627:82, :628:21] wire [7:0][63:0] _GEN_1 = {{lb_1_7}, {lb_1_6}, {lb_1_5}, {lb_1_4}, {lb_1_3}, {lb_1_2}, {lb_1_1}, {lb_1_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_9 = io_mem_grant_bits_source_0 == 2'h1; // @[mshrs.scala:498:7, :656:36] assign io_probe_rdy_0 = ~(~_mshrs_1_io_probe_rdy & idx_matches_0_1 & io_req_is_probe_0_0 | ~_mshrs_0_io_probe_rdy & idx_matches_0_0 & io_req_is_probe_0_0); // @[mshrs.scala:498:7, :571:25, :595:16, :602:22, :667:{13,32,53,76}, :668:22] reg mshr_head; // @[mshrs.scala:676:31] wire _mshr_alloc_idx_temp_vec_T = ~mshr_head; // @[util.scala:352:72] wire mshr_alloc_idx_temp_vec_0 = _mshrs_0_io_req_pri_rdy & _mshr_alloc_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire mshr_alloc_idx_temp_vec_1; // @[util.scala:352:65] wire [1:0] _mshr_alloc_idx_idx_T = {1'h1, ~_mshrs_0_io_req_pri_rdy}; // @[Mux.scala:50:70] wire [1:0] _mshr_alloc_idx_idx_T_1 = mshr_alloc_idx_temp_vec_1 ? 2'h1 : _mshr_alloc_idx_idx_T; // @[Mux.scala:50:70] wire [1:0] mshr_alloc_idx_idx = mshr_alloc_idx_temp_vec_0 ? 2'h0 : _mshr_alloc_idx_idx_T_1; // @[Mux.scala:50:70] wire _mshr_alloc_idx_T = mshr_alloc_idx_idx[0]; // @[Mux.scala:50:70] reg mshr_alloc_idx_REG; // @[mshrs.scala:677:31] assign mshr_alloc_idx = mshr_alloc_idx_REG; // @[mshrs.scala:598:28, :677:31] wire [1:0] _mshr_head_T = {1'h0, mshr_head} + 2'h1; // @[util.scala:211:14] wire _mshr_head_T_1 = _mshr_head_T[0]; // @[util.scala:211:14] wire _mshr_head_T_2 = _mshr_head_T_1; // @[util.scala:211:{14,20}] wire _mshr_io_mem_ack_valid_T = &io_mem_grant_bits_source_0; // @[mshrs.scala:498:7, :703:77] wire _mshr_io_mem_ack_valid_T_1 = io_mem_grant_valid_0 & _mshr_io_mem_ack_valid_T; // @[mshrs.scala:498:7, :703:{49,77}] assign io_mem_grant_ready_0 = (&io_mem_grant_bits_source_0) | (_T_9 ? _mshrs_1_io_mem_grant_ready : _T_1 & _mshrs_0_io_mem_grant_ready); // @[mshrs.scala:498:7, :596:22, :602:22, :656:{36,45}, :657:25, :703:77, :704:46, :705:26] assign io_fence_rdy_0 = ~(~_mmios_0_io_req_ready | ~_mshrs_1_io_req_pri_rdy | ~_mshrs_0_io_req_pri_rdy); // @[mshrs.scala:498:7, :594:16, :602:22, :663:{11,33}, :664:20, :693:22, :709:{11,31}, :710:20] wire _mmio_alloc_arb_io_out_ready_T = ~cacheable; // @[Parameters.scala:686:26] wire _mmio_alloc_arb_io_out_ready_T_1 = req_valid & _mmio_alloc_arb_io_out_ready_T; // @[mshrs.scala:536:25, :715:{44,47}] wire [26:0] _decode_T_6 = 27'hFFF << _mmios_0_io_mem_access_bits_size; // @[package.scala:243:71] wire [11:0] _decode_T_7 = _decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _decode_T_8 = ~_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] decode_2 = _decode_T_8[11:3]; // @[package.scala:243:46] wire _opdata_T_2 = _mmios_0_io_mem_access_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata_2 = ~_opdata_T_2; // @[Edges.scala:92:{28,37}] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & io_mem_acquire_ready_0; // @[Arbiter.scala:61:28, :62:24] wire [1:0] readys_hi = {_mmios_0_io_mem_access_valid, _mshrs_1_io_mem_acquire_valid}; // @[Arbiter.scala:68:51] wire [2:0] _readys_T = {readys_hi, _mshrs_0_io_mem_acquire_valid}; // @[Arbiter.scala:68:51] wire [3:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [2:0] _readys_T_2 = _readys_T_1[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [4:0] _readys_T_4 = {_readys_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [2:0] _readys_T_5 = _readys_T_4[2:0]; // @[package.scala:253:{48,53}] wire [2:0] _readys_T_6 = _readys_T_3 | _readys_T_5; // @[package.scala:253:{43,53}] wire [2:0] _readys_T_7 = _readys_T_6; // @[package.scala:253:43, :254:17] wire [3:0] _readys_T_8 = {_readys_T_7, 1'h0}; // @[package.scala:254:17] wire [2:0] _readys_T_9 = _readys_T_8[2:0]; // @[Arbiter.scala:16:{78,83}] wire [2:0] _readys_T_10 = ~_readys_T_9; // @[Arbiter.scala:16:{61,83}] wire _readys_T_11 = _readys_T_10[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_11; // @[Arbiter.scala:68:{27,76}] wire _readys_T_12 = _readys_T_10[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_12; // @[Arbiter.scala:68:{27,76}] wire _readys_T_13 = _readys_T_10[2]; // @[Arbiter.scala:16:61, :68:76] wire readys_2 = _readys_T_13; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & _mshrs_0_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & _mshrs_1_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire _winner_T_2 = readys_2 & _mmios_0_io_mem_access_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48] wire _io_mem_acquire_valid_T = _mshrs_0_io_mem_acquire_valid | _mshrs_1_io_mem_acquire_valid; // @[Arbiter.scala:79:31, :96:46] wire [8:0] maskedBeats_2 = winner_2 & opdata_2 ? decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [8:0] initBeats = maskedBeats_2; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = io_mem_acquire_ready_0 & io_mem_acquire_valid_0; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52] wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] reg state_2; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire _mshrs_0_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_0; // @[Arbiter.scala:92:24, :94:31] wire _mshrs_1_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_1; // @[Arbiter.scala:92:24, :94:31] wire _mmios_0_io_mem_access_ready_T = io_mem_acquire_ready_0 & allowed_2; // @[Arbiter.scala:92:24, :94:31] wire _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T | _mmios_0_io_mem_access_valid; // @[Arbiter.scala:96:46] wire _io_mem_acquire_valid_T_2 = state_0 & _mshrs_0_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_3 = state_1 & _mshrs_1_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_4 = state_2 & _mmios_0_io_mem_access_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_5 = _io_mem_acquire_valid_T_2 | _io_mem_acquire_valid_T_3; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_6 = _io_mem_acquire_valid_T_5 | _io_mem_acquire_valid_T_4; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_WIRE = _io_mem_acquire_valid_T_6; // @[Mux.scala:30:73] assign _io_mem_acquire_valid_T_7 = idle ? _io_mem_acquire_valid_T_1 : _io_mem_acquire_valid_WIRE; // @[Mux.scala:30:73] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_7; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_acquire_bits_WIRE_10; // @[Mux.scala:30:73] assign io_mem_acquire_bits_opcode_0 = _io_mem_acquire_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_9; // @[Mux.scala:30:73] assign io_mem_acquire_bits_param_0 = _io_mem_acquire_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_WIRE_8; // @[Mux.scala:30:73] assign io_mem_acquire_bits_size_0 = _io_mem_acquire_bits_WIRE_size; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_WIRE_7; // @[Mux.scala:30:73] assign io_mem_acquire_bits_source_0 = _io_mem_acquire_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_WIRE_6; // @[Mux.scala:30:73] assign io_mem_acquire_bits_address_0 = _io_mem_acquire_bits_WIRE_address; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_WIRE_3; // @[Mux.scala:30:73] assign io_mem_acquire_bits_mask_0 = _io_mem_acquire_bits_WIRE_mask; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_WIRE_2; // @[Mux.scala:30:73] assign io_mem_acquire_bits_data_0 = _io_mem_acquire_bits_WIRE_data; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_7 = muxState_2 ? _mmios_0_io_mem_access_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_mem_acquire_bits_T_9 = _io_mem_acquire_bits_T_7; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_2 = _io_mem_acquire_bits_T_9; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_data = _io_mem_acquire_bits_WIRE_2; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_10 = {8{muxState_0}}; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_11 = {8{muxState_1}}; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_12 = muxState_2 ? _mmios_0_io_mem_access_bits_mask : 8'h0; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_13 = _io_mem_acquire_bits_T_10 | _io_mem_acquire_bits_T_11; // @[Mux.scala:30:73] wire [7:0] _io_mem_acquire_bits_T_14 = _io_mem_acquire_bits_T_13 | _io_mem_acquire_bits_T_12; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_3 = _io_mem_acquire_bits_T_14; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_mask = _io_mem_acquire_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_15 = muxState_0 ? _mshrs_0_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_16 = muxState_1 ? _mshrs_1_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_17 = muxState_2 ? _mmios_0_io_mem_access_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_18 = _io_mem_acquire_bits_T_15 | _io_mem_acquire_bits_T_16; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_19 = _io_mem_acquire_bits_T_18 | _io_mem_acquire_bits_T_17; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_6 = _io_mem_acquire_bits_T_19; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_address = _io_mem_acquire_bits_WIRE_6; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_21 = {1'h0, muxState_1}; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_23 = _io_mem_acquire_bits_T_21; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_22 = muxState_2 ? _mmios_0_io_mem_access_bits_source : 2'h0; // @[Mux.scala:30:73] wire [1:0] _io_mem_acquire_bits_T_24 = _io_mem_acquire_bits_T_23 | _io_mem_acquire_bits_T_22; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_7 = _io_mem_acquire_bits_T_24; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_source = _io_mem_acquire_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_25 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_26 = muxState_1 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_27 = muxState_2 ? _mmios_0_io_mem_access_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_28 = _io_mem_acquire_bits_T_25 | _io_mem_acquire_bits_T_26; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_29 = _io_mem_acquire_bits_T_28 | _io_mem_acquire_bits_T_27; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_8 = _io_mem_acquire_bits_T_29; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_size = _io_mem_acquire_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_30 = muxState_0 ? _mshrs_0_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_31 = muxState_1 ? _mshrs_1_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_32 = muxState_2 ? _mmios_0_io_mem_access_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_33 = _io_mem_acquire_bits_T_30 | _io_mem_acquire_bits_T_31; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_34 = _io_mem_acquire_bits_T_33 | _io_mem_acquire_bits_T_32; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_9 = _io_mem_acquire_bits_T_34; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_param = _io_mem_acquire_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_35 = muxState_0 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_36 = muxState_1 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_37 = muxState_2 ? _mmios_0_io_mem_access_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_38 = _io_mem_acquire_bits_T_35 | _io_mem_acquire_bits_T_36; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_39 = _io_mem_acquire_bits_T_38 | _io_mem_acquire_bits_T_37; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_10 = _io_mem_acquire_bits_T_39; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_opcode = _io_mem_acquire_bits_WIRE_10; // @[Mux.scala:30:73] reg beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = ~beatsLeft_1; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & io_mem_finish_ready_0; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T_14 = {_mshrs_1_io_mem_finish_valid, _mshrs_0_io_mem_finish_valid}; // @[Arbiter.scala:68:51] wire [2:0] _readys_T_15 = {_readys_T_14, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_16 = _readys_T_15[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_17 = _readys_T_14 | _readys_T_16; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_18 = _readys_T_17; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_19 = {_readys_T_18, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_20 = _readys_T_19[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_21 = ~_readys_T_20; // @[Arbiter.scala:16:{61,83}] wire _readys_T_22 = _readys_T_21[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_0 = _readys_T_22; // @[Arbiter.scala:68:{27,76}] wire _readys_T_23 = _readys_T_21[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_1 = _readys_T_23; // @[Arbiter.scala:68:{27,76}] wire _winner_T_3 = readys_1_0 & _mshrs_0_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_0 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_1_1 & _mshrs_1_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_1 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _io_mem_finish_valid_T = _mshrs_0_io_mem_finish_valid | _mshrs_1_io_mem_finish_valid; // @[Arbiter.scala:79:31, :96:46]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_181 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_181( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_111 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_111( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_39 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_47 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_39( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_47 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncQueue_11 : output io : { flip enq_clock : Clock, flip enq_reset : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip deq_clock : Clock, flip deq_reset : UInt<1>, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}} inst source of AsyncQueueSource_Phit_11 connect source.clock, io.enq_clock connect source.reset, io.enq_reset inst sink of AsyncQueueSink_Phit_11 connect sink.clock, io.deq_clock connect sink.reset, io.deq_reset connect source.io.enq, io.enq connect io.deq.bits, sink.io.deq.bits connect io.deq.valid, sink.io.deq.valid connect sink.io.deq.ready, io.deq.ready connect sink.io.async, source.io.async

module AsyncQueue_11( // @[AsyncQueue.scala:226:7] input io_enq_clock, // @[AsyncQueue.scala:227:14] input io_enq_reset, // @[AsyncQueue.scala:227:14] output io_enq_ready, // @[AsyncQueue.scala:227:14] input io_enq_valid, // @[AsyncQueue.scala:227:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14] input io_deq_clock, // @[AsyncQueue.scala:227:14] input io_deq_reset, // @[AsyncQueue.scala:227:14] input io_deq_ready, // @[AsyncQueue.scala:227:14] output io_deq_valid, // @[AsyncQueue.scala:227:14] output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14] ); wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70] wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70] wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70] wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70] wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70] wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70] wire io_enq_clock_0 = io_enq_clock; // @[AsyncQueue.scala:226:7] wire io_enq_reset_0 = io_enq_reset; // @[AsyncQueue.scala:226:7] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:226:7] wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:226:7] wire io_deq_clock_0 = io_deq_clock; // @[AsyncQueue.scala:226:7] wire io_deq_reset_0 = io_deq_reset; // @[AsyncQueue.scala:226:7] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:226:7] wire io_enq_ready_0; // @[AsyncQueue.scala:226:7] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7] wire io_deq_valid_0; // @[AsyncQueue.scala:226:7] AsyncQueueSource_Phit_11 source ( // @[AsyncQueue.scala:228:70] .clock (io_enq_clock_0), // @[AsyncQueue.scala:226:7] .reset (io_enq_reset_0), // @[AsyncQueue.scala:226:7] .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[AsyncQueue.scala:226:7] .io_enq_bits_phit (io_enq_bits_phit_0), // @[AsyncQueue.scala:226:7] .io_async_mem_0_phit (_source_io_async_mem_0_phit), .io_async_mem_1_phit (_source_io_async_mem_1_phit), .io_async_mem_2_phit (_source_io_async_mem_2_phit), .io_async_mem_3_phit (_source_io_async_mem_3_phit), .io_async_mem_4_phit (_source_io_async_mem_4_phit), .io_async_mem_5_phit (_source_io_async_mem_5_phit), .io_async_mem_6_phit (_source_io_async_mem_6_phit), .io_async_mem_7_phit (_source_io_async_mem_7_phit), .io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70] .io_async_widx (_source_io_async_widx), .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70] .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70] ); // @[AsyncQueue.scala:228:70] AsyncQueueSink_Phit_11 sink ( // @[AsyncQueue.scala:229:70] .clock (io_deq_clock_0), // @[AsyncQueue.scala:226:7] .reset (io_deq_reset_0), // @[AsyncQueue.scala:226:7] .io_deq_ready (io_deq_ready_0), // @[AsyncQueue.scala:226:7] .io_deq_valid (io_deq_valid_0), .io_deq_bits_phit (io_deq_bits_phit_0), .io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70] .io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70] .io_async_ridx (_sink_io_async_ridx), .io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70] .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), .io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70] .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70] .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) ); // @[AsyncQueue.scala:229:70] assign io_enq_ready = io_enq_ready_0; // @[AsyncQueue.scala:226:7] assign io_deq_valid = io_deq_valid_0; // @[AsyncQueue.scala:226:7] assign io_deq_bits_phit = io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _T_1085 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1086 = orr(a_set_wo_ready) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) node _T_1088 = or(_T_1085, _T_1087) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_44 node _T_1092 = orr(inflight) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) node _T_1094 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1095 = or(_T_1093, _T_1094) node _T_1096 = lt(watchdog, plusarg_reader.out) node _T_1097 = or(_T_1095, _T_1096) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1101 = and(io.in.a.ready, io.in.a.valid) node _T_1102 = and(io.in.d.ready, io.in.d.valid) node _T_1103 = or(_T_1101, _T_1102) when _T_1103 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1104 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1105 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1106 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = and(_T_1104, _T_1107) when _T_1108 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1109 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1110 = and(_T_1109, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1111 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1112 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1113 = and(_T_1111, _T_1112) node _T_1114 = and(_T_1110, _T_1113) when _T_1114 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1115 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1116 = bits(_T_1115, 0, 0) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1124 = and(io.in.d.ready, io.in.d.valid) node _T_1125 = and(_T_1124, d_first_2) node _T_1126 = and(_T_1125, UInt<1>(0h1)) node _T_1127 = and(_T_1126, d_release_ack_1) when _T_1127 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1128 = and(io.in.d.valid, d_first_2) node _T_1129 = and(_T_1128, UInt<1>(0h1)) node _T_1130 = and(_T_1129, d_release_ack_1) when _T_1130 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1131 = dshr(inflight_1, io.in.d.bits.source) node _T_1132 = bits(_T_1131, 0, 0) node _T_1133 = or(_T_1132, same_cycle_resp_1) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1137 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_109 else : node _T_1141 = eq(io.in.d.bits.size, c_size_lookup) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_110 node _T_1145 = and(io.in.d.valid, d_first_2) node _T_1146 = and(_T_1145, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1147 = and(_T_1146, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1148 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = and(_T_1149, d_release_ack_1) node _T_1151 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1152 = and(_T_1150, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1154 = or(_T_1153, _WIRE_27.ready) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_111 node _T_1158 = orr(c_set_wo_ready) when _T_1158 : node _T_1159 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_45 node _T_1163 = orr(inflight_1) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) node _T_1165 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = lt(watchdog_1, plusarg_reader_1.out) node _T_1168 = or(_T_1166, _T_1167) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1172 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1173 = and(io.in.d.ready, io.in.d.valid) node _T_1174 = or(_T_1172, _T_1173) when _T_1174 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Tile_188 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_444 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_188( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_444 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_46 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_59 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_46( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_59 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_62 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_890 = orr(a_set_wo_ready) node _T_891 = eq(_T_890, UInt<1>(0h0)) node _T_892 = or(_T_889, _T_891) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_892, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_125 node _T_896 = orr(inflight) node _T_897 = eq(_T_896, UInt<1>(0h0)) node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_899 = or(_T_897, _T_898) node _T_900 = lt(watchdog, plusarg_reader.out) node _T_901 = or(_T_899, _T_900) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_901, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_905 = and(io.in.a.ready, io.in.a.valid) node _T_906 = and(io.in.d.ready, io.in.d.valid) node _T_907 = or(_T_905, _T_906) when _T_907 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_908 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_911 = and(_T_909, _T_910) node _T_912 = and(_T_908, _T_911) when _T_912 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_914 = and(_T_913, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_917 = and(_T_915, _T_916) node _T_918 = and(_T_914, _T_917) when _T_918 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_919 = dshr(inflight_1, _WIRE_15.bits.source) node _T_920 = bits(_T_919, 0, 0) node _T_921 = eq(_T_920, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_921, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_928 = and(io.in.d.ready, io.in.d.valid) node _T_929 = and(_T_928, d_first_2) node _T_930 = and(_T_929, UInt<1>(0h1)) node _T_931 = and(_T_930, d_release_ack_1) when _T_931 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_932 = and(io.in.d.valid, d_first_2) node _T_933 = and(_T_932, UInt<1>(0h1)) node _T_934 = and(_T_933, d_release_ack_1) when _T_934 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_935 = dshr(inflight_1, io.in.d.bits.source) node _T_936 = bits(_T_935, 0, 0) node _T_937 = or(_T_936, same_cycle_resp_1) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_937, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_941, UInt<1>(0h1), "") : assert_109 else : node _T_945 = eq(io.in.d.bits.size, c_size_lookup) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_945, UInt<1>(0h1), "") : assert_110 node _T_949 = and(io.in.d.valid, d_first_2) node _T_950 = and(_T_949, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_951 = and(_T_950, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_953 = and(_T_951, _T_952) node _T_954 = and(_T_953, d_release_ack_1) node _T_955 = eq(c_probe_ack, UInt<1>(0h0)) node _T_956 = and(_T_954, _T_955) when _T_956 : node _T_957 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_958 = or(_T_957, _WIRE_23.ready) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_958, UInt<1>(0h1), "") : assert_111 node _T_962 = orr(c_set_wo_ready) when _T_962 : node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_963, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_126 node _T_967 = orr(inflight_1) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_970 = or(_T_968, _T_969) node _T_971 = lt(watchdog_1, plusarg_reader_1.out) node _T_972 = or(_T_970, _T_971) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_972, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_977 = and(io.in.d.ready, io.in.d.valid) node _T_978 = or(_T_976, _T_977) when _T_978 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_62( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_905 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_905; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_905; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_978 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_978; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_905 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_978 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_949 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_949 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_931 = _T_978 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_931 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_931 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_931 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_77 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_77( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_pbus_to_bootaddressreg : input clock : Clock input reset : Reset output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_BootAddrReg connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect fragmenter.auto.anon_in, tlOut connect tlIn, auto.tl_in connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready extmodule plusarg_reader_24 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_25 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLInterconnectCoupler_pbus_to_bootaddressreg( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [12:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [12:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_BootAddrReg fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_138 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_138( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_84 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_85 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/ibex/src/main/scala/IbexTile.scala:162:43)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14] wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27] wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25] wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28] wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = |(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :673:46, :674:74, :678:{25,70}] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_2; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :783:46, :788:{25,70}] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module BoomFrontend_1 : input clock : Clock input reset : Reset output auto : { icache_master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip reset_vector_sink_in : UInt<32>} output io : { flip cpu : { flip fetchpacket : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[3]}}, flip get_pc : { flip ftq_idx : UInt<5>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}[2], debug_ftq_idx : UInt<5>[3], flip debug_fetch_pc : UInt<40>[3], status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], mcontext : UInt<0>, scontext : UInt<0>, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, redirect_flush : UInt<1>, redirect_val : UInt<1>, redirect_pc : UInt, redirect_ftq_idx : UInt, redirect_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, commit : { valid : UInt<1>, bits : UInt<32>}, flush_icache : UInt<1>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}} inst icache of ICache_3 connect icache.clock, clock connect icache.reset, reset wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn connect resetVectorSinkNodeIn, auto.reset_vector_sink_in connect icache.auto.master_out.d, auto.icache_master_out.d connect auto.icache_master_out.a.bits, icache.auto.master_out.a.bits connect auto.icache_master_out.a.valid, icache.auto.master_out.a.valid connect icache.auto.master_out.a.ready, auto.icache_master_out.a.ready inst bpd of BranchPredictor_1 connect bpd.clock, clock connect bpd.reset, reset connect bpd.io.f3_fire, UInt<1>(0h0) inst ras of BoomRAS_1 connect ras.clock, clock connect ras.reset, reset connect icache.io.invalidate, io.cpu.flush_icache inst tlb of ITLB_3 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T connect io.cpu.perf.acquire, icache.io.perf.acquire wire s0_vpc : UInt<40> connect s0_vpc, UInt<40>(0h0) wire _s0_ghist_WIRE : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _s0_ghist_WIRE.ras_idx, UInt<5>(0h0) connect _s0_ghist_WIRE.new_saw_branch_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.new_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.current_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.old_history, UInt<64>(0h0) wire s0_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect s0_ghist, _s0_ghist_WIRE wire s0_tsrc : UInt<2> connect s0_tsrc, UInt<2>(0h0) wire s0_valid : UInt<1> connect s0_valid, UInt<1>(0h0) wire s0_is_replay : UInt<1> connect s0_is_replay, UInt<1>(0h0) wire s0_is_sfence : UInt<1> connect s0_is_sfence, UInt<1>(0h0) wire s0_replay_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>} wire s0_replay_bpd_resp : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]} wire s0_replay_ppc : UInt wire s0_s1_use_f3_bpd_resp : UInt<1> connect s0_s1_use_f3_bpd_resp, UInt<1>(0h0) node _T = asUInt(reset) reg REG : UInt<1>, clock connect REG, _T node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = and(REG, _T_2) when _T_3 : connect s0_valid, UInt<1>(0h1) connect s0_vpc, resetVectorSinkNodeIn wire _s0_ghist_WIRE_1 : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _s0_ghist_WIRE_1.ras_idx, UInt<5>(0h0) connect _s0_ghist_WIRE_1.new_saw_branch_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.new_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.current_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.old_history, UInt<64>(0h0) connect s0_ghist, _s0_ghist_WIRE_1 connect s0_tsrc, UInt<2>(0h3) connect icache.io.req.valid, s0_valid connect icache.io.req.bits.addr, s0_vpc connect bpd.io.f0_req.valid, s0_valid connect bpd.io.f0_req.bits.pc, s0_vpc connect bpd.io.f0_req.bits.ghist.ras_idx, s0_ghist.ras_idx connect bpd.io.f0_req.bits.ghist.new_saw_branch_taken, s0_ghist.new_saw_branch_taken connect bpd.io.f0_req.bits.ghist.new_saw_branch_not_taken, s0_ghist.new_saw_branch_not_taken connect bpd.io.f0_req.bits.ghist.current_saw_branch_not_taken, s0_ghist.current_saw_branch_not_taken connect bpd.io.f0_req.bits.ghist.old_history, s0_ghist.old_history reg s1_vpc : UInt, clock connect s1_vpc, s0_vpc regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s1_valid, s0_valid reg s1_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, clock connect s1_ghist, s0_ghist reg s1_is_replay : UInt<1>, clock connect s1_is_replay, s0_is_replay reg s1_is_sfence : UInt<1>, clock connect s1_is_sfence, s0_is_sfence wire f1_clear : UInt<1> connect f1_clear, UInt<1>(0h0) reg s1_tsrc : UInt, clock connect s1_tsrc, s0_tsrc node _tlb_io_req_valid_T = eq(s1_is_replay, UInt<1>(0h0)) node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T) node _tlb_io_req_valid_T_2 = eq(f1_clear, UInt<1>(0h0)) node _tlb_io_req_valid_T_3 = and(_tlb_io_req_valid_T_1, _tlb_io_req_valid_T_2) node _tlb_io_req_valid_T_4 = or(_tlb_io_req_valid_T_3, s1_is_sfence) connect tlb.io.req.valid, _tlb_io_req_valid_T_4 invalidate tlb.io.req.bits.cmd connect tlb.io.req.bits.vaddr, s1_vpc connect tlb.io.req.bits.passthrough, UInt<1>(0h0) connect tlb.io.req.bits.size, UInt<3>(0h4) connect tlb.io.req.bits.v, io.ptw.status.v connect tlb.io.req.bits.prv, io.ptw.status.prv reg tlb_io_sfence_REG : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, clock connect tlb_io_sfence_REG, io.cpu.sfence connect tlb.io.sfence.bits.hg, tlb_io_sfence_REG.bits.hg connect tlb.io.sfence.bits.hv, tlb_io_sfence_REG.bits.hv connect tlb.io.sfence.bits.asid, tlb_io_sfence_REG.bits.asid connect tlb.io.sfence.bits.addr, tlb_io_sfence_REG.bits.addr connect tlb.io.sfence.bits.rs2, tlb_io_sfence_REG.bits.rs2 connect tlb.io.sfence.bits.rs1, tlb_io_sfence_REG.bits.rs1 connect tlb.io.sfence.valid, tlb_io_sfence_REG.valid connect tlb.io.kill, UInt<1>(0h0) node _s1_tlb_miss_T = eq(s1_is_replay, UInt<1>(0h0)) node s1_tlb_miss = and(_s1_tlb_miss_T, tlb.io.resp.miss) reg s1_tlb_resp_REG : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>}, clock connect s1_tlb_resp_REG, s0_replay_resp node s1_tlb_resp = mux(s1_is_replay, s1_tlb_resp_REG, tlb.io.resp) reg s1_ppc_REG : UInt, clock connect s1_ppc_REG, s0_replay_ppc node s1_ppc = mux(s1_is_replay, s1_ppc_REG, tlb.io.resp.paddr) connect icache.io.s1_paddr, s1_ppc node _icache_io_s1_kill_T = or(tlb.io.resp.miss, f1_clear) connect icache.io.s1_kill, _icache_io_s1_kill_T node f1_mask_idx = bits(s1_vpc, 3, 1) node f1_mask_shamt = bits(f1_mask_idx, 1, 0) node _f1_mask_end_mask_T = bits(s1_vpc, 5, 3) node _f1_mask_end_mask_T_1 = eq(_f1_mask_end_mask_T, UInt<3>(0h7)) node _f1_mask_end_mask_T_2 = and(UInt<1>(0h1), _f1_mask_end_mask_T_1) node _f1_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _f1_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node f1_mask_end_mask = mux(_f1_mask_end_mask_T_2, _f1_mask_end_mask_T_3, _f1_mask_end_mask_T_4) node _f1_mask_T = dshl(UInt<8>(0hff), f1_mask_shamt) node f1_mask = and(_f1_mask_T, f1_mask_end_mask) node _f1_redirects_T = bits(f1_mask, 0, 0) node _f1_redirects_T_1 = and(s1_valid, _f1_redirects_T) node _f1_redirects_T_2 = and(_f1_redirects_T_1, bpd.io.resp.f1.preds[0].predicted_pc.valid) node _f1_redirects_T_3 = and(bpd.io.resp.f1.preds[0].is_br, bpd.io.resp.f1.preds[0].taken) node _f1_redirects_T_4 = or(bpd.io.resp.f1.preds[0].is_jal, _f1_redirects_T_3) node f1_redirects_0 = and(_f1_redirects_T_2, _f1_redirects_T_4) node _f1_redirects_T_5 = bits(f1_mask, 1, 1) node _f1_redirects_T_6 = and(s1_valid, _f1_redirects_T_5) node _f1_redirects_T_7 = and(_f1_redirects_T_6, bpd.io.resp.f1.preds[1].predicted_pc.valid) node _f1_redirects_T_8 = and(bpd.io.resp.f1.preds[1].is_br, bpd.io.resp.f1.preds[1].taken) node _f1_redirects_T_9 = or(bpd.io.resp.f1.preds[1].is_jal, _f1_redirects_T_8) node f1_redirects_1 = and(_f1_redirects_T_7, _f1_redirects_T_9) node _f1_redirects_T_10 = bits(f1_mask, 2, 2) node _f1_redirects_T_11 = and(s1_valid, _f1_redirects_T_10) node _f1_redirects_T_12 = and(_f1_redirects_T_11, bpd.io.resp.f1.preds[2].predicted_pc.valid) node _f1_redirects_T_13 = and(bpd.io.resp.f1.preds[2].is_br, bpd.io.resp.f1.preds[2].taken) node _f1_redirects_T_14 = or(bpd.io.resp.f1.preds[2].is_jal, _f1_redirects_T_13) node f1_redirects_2 = and(_f1_redirects_T_12, _f1_redirects_T_14) node _f1_redirects_T_15 = bits(f1_mask, 3, 3) node _f1_redirects_T_16 = and(s1_valid, _f1_redirects_T_15) node _f1_redirects_T_17 = and(_f1_redirects_T_16, bpd.io.resp.f1.preds[3].predicted_pc.valid) node _f1_redirects_T_18 = and(bpd.io.resp.f1.preds[3].is_br, bpd.io.resp.f1.preds[3].taken) node _f1_redirects_T_19 = or(bpd.io.resp.f1.preds[3].is_jal, _f1_redirects_T_18) node f1_redirects_3 = and(_f1_redirects_T_17, _f1_redirects_T_19) node _f1_redirects_T_20 = bits(f1_mask, 4, 4) node _f1_redirects_T_21 = and(s1_valid, _f1_redirects_T_20) node _f1_redirects_T_22 = and(_f1_redirects_T_21, bpd.io.resp.f1.preds[4].predicted_pc.valid) node _f1_redirects_T_23 = and(bpd.io.resp.f1.preds[4].is_br, bpd.io.resp.f1.preds[4].taken) node _f1_redirects_T_24 = or(bpd.io.resp.f1.preds[4].is_jal, _f1_redirects_T_23) node f1_redirects_4 = and(_f1_redirects_T_22, _f1_redirects_T_24) node _f1_redirects_T_25 = bits(f1_mask, 5, 5) node _f1_redirects_T_26 = and(s1_valid, _f1_redirects_T_25) node _f1_redirects_T_27 = and(_f1_redirects_T_26, bpd.io.resp.f1.preds[5].predicted_pc.valid) node _f1_redirects_T_28 = and(bpd.io.resp.f1.preds[5].is_br, bpd.io.resp.f1.preds[5].taken) node _f1_redirects_T_29 = or(bpd.io.resp.f1.preds[5].is_jal, _f1_redirects_T_28) node f1_redirects_5 = and(_f1_redirects_T_27, _f1_redirects_T_29) node _f1_redirects_T_30 = bits(f1_mask, 6, 6) node _f1_redirects_T_31 = and(s1_valid, _f1_redirects_T_30) node _f1_redirects_T_32 = and(_f1_redirects_T_31, bpd.io.resp.f1.preds[6].predicted_pc.valid) node _f1_redirects_T_33 = and(bpd.io.resp.f1.preds[6].is_br, bpd.io.resp.f1.preds[6].taken) node _f1_redirects_T_34 = or(bpd.io.resp.f1.preds[6].is_jal, _f1_redirects_T_33) node f1_redirects_6 = and(_f1_redirects_T_32, _f1_redirects_T_34) node _f1_redirects_T_35 = bits(f1_mask, 7, 7) node _f1_redirects_T_36 = and(s1_valid, _f1_redirects_T_35) node _f1_redirects_T_37 = and(_f1_redirects_T_36, bpd.io.resp.f1.preds[7].predicted_pc.valid) node _f1_redirects_T_38 = and(bpd.io.resp.f1.preds[7].is_br, bpd.io.resp.f1.preds[7].taken) node _f1_redirects_T_39 = or(bpd.io.resp.f1.preds[7].is_jal, _f1_redirects_T_38) node f1_redirects_7 = and(_f1_redirects_T_37, _f1_redirects_T_39) node _f1_redirect_idx_T = mux(f1_redirects_6, UInt<3>(0h6), UInt<3>(0h7)) node _f1_redirect_idx_T_1 = mux(f1_redirects_5, UInt<3>(0h5), _f1_redirect_idx_T) node _f1_redirect_idx_T_2 = mux(f1_redirects_4, UInt<3>(0h4), _f1_redirect_idx_T_1) node _f1_redirect_idx_T_3 = mux(f1_redirects_3, UInt<2>(0h3), _f1_redirect_idx_T_2) node _f1_redirect_idx_T_4 = mux(f1_redirects_2, UInt<2>(0h2), _f1_redirect_idx_T_3) node _f1_redirect_idx_T_5 = mux(f1_redirects_1, UInt<1>(0h1), _f1_redirect_idx_T_4) node f1_redirect_idx = mux(f1_redirects_0, UInt<1>(0h0), _f1_redirect_idx_T_5) node _f1_do_redirect_T = or(f1_redirects_0, f1_redirects_1) node _f1_do_redirect_T_1 = or(_f1_do_redirect_T, f1_redirects_2) node _f1_do_redirect_T_2 = or(_f1_do_redirect_T_1, f1_redirects_3) node _f1_do_redirect_T_3 = or(_f1_do_redirect_T_2, f1_redirects_4) node _f1_do_redirect_T_4 = or(_f1_do_redirect_T_3, f1_redirects_5) node _f1_do_redirect_T_5 = or(_f1_do_redirect_T_4, f1_redirects_6) node _f1_do_redirect_T_6 = or(_f1_do_redirect_T_5, f1_redirects_7) node f1_do_redirect = and(_f1_do_redirect_T_6, UInt<1>(0h1)) node _f1_predicted_target_T = eq(f1_redirect_idx, UInt<1>(0h1)) node _f1_predicted_target_T_1 = mux(_f1_predicted_target_T, bpd.io.resp.f1.preds[1].predicted_pc.bits, bpd.io.resp.f1.preds[0].predicted_pc.bits) node _f1_predicted_target_T_2 = eq(f1_redirect_idx, UInt<2>(0h2)) node _f1_predicted_target_T_3 = mux(_f1_predicted_target_T_2, bpd.io.resp.f1.preds[2].predicted_pc.bits, _f1_predicted_target_T_1) node _f1_predicted_target_T_4 = eq(f1_redirect_idx, UInt<2>(0h3)) node _f1_predicted_target_T_5 = mux(_f1_predicted_target_T_4, bpd.io.resp.f1.preds[3].predicted_pc.bits, _f1_predicted_target_T_3) node _f1_predicted_target_T_6 = eq(f1_redirect_idx, UInt<3>(0h4)) node _f1_predicted_target_T_7 = mux(_f1_predicted_target_T_6, bpd.io.resp.f1.preds[4].predicted_pc.bits, _f1_predicted_target_T_5) node _f1_predicted_target_T_8 = eq(f1_redirect_idx, UInt<3>(0h5)) node _f1_predicted_target_T_9 = mux(_f1_predicted_target_T_8, bpd.io.resp.f1.preds[5].predicted_pc.bits, _f1_predicted_target_T_7) node _f1_predicted_target_T_10 = eq(f1_redirect_idx, UInt<3>(0h6)) node _f1_predicted_target_T_11 = mux(_f1_predicted_target_T_10, bpd.io.resp.f1.preds[6].predicted_pc.bits, _f1_predicted_target_T_9) node _f1_predicted_target_T_12 = eq(f1_redirect_idx, UInt<3>(0h7)) node _f1_predicted_target_T_13 = mux(_f1_predicted_target_T_12, bpd.io.resp.f1.preds[7].predicted_pc.bits, _f1_predicted_target_T_11) node _f1_predicted_target_T_14 = not(s1_vpc) node _f1_predicted_target_T_15 = or(_f1_predicted_target_T_14, UInt<3>(0h7)) node _f1_predicted_target_T_16 = not(_f1_predicted_target_T_15) node _f1_predicted_target_T_17 = bits(s1_vpc, 5, 3) node _f1_predicted_target_T_18 = eq(_f1_predicted_target_T_17, UInt<3>(0h7)) node _f1_predicted_target_T_19 = and(UInt<1>(0h1), _f1_predicted_target_T_18) node _f1_predicted_target_T_20 = mux(_f1_predicted_target_T_19, UInt<4>(0h8), UInt<5>(0h10)) node _f1_predicted_target_T_21 = add(_f1_predicted_target_T_16, _f1_predicted_target_T_20) node _f1_predicted_target_T_22 = tail(_f1_predicted_target_T_21, 1) node f1_predicted_target = mux(f1_do_redirect, _f1_predicted_target_T_13, _f1_predicted_target_T_22) node _f1_predicted_ghist_T = and(bpd.io.resp.f1.preds[0].is_br, bpd.io.resp.f1.preds[0].predicted_pc.valid) node _f1_predicted_ghist_T_1 = and(bpd.io.resp.f1.preds[1].is_br, bpd.io.resp.f1.preds[1].predicted_pc.valid) node _f1_predicted_ghist_T_2 = and(bpd.io.resp.f1.preds[2].is_br, bpd.io.resp.f1.preds[2].predicted_pc.valid) node _f1_predicted_ghist_T_3 = and(bpd.io.resp.f1.preds[3].is_br, bpd.io.resp.f1.preds[3].predicted_pc.valid) node _f1_predicted_ghist_T_4 = and(bpd.io.resp.f1.preds[4].is_br, bpd.io.resp.f1.preds[4].predicted_pc.valid) node _f1_predicted_ghist_T_5 = and(bpd.io.resp.f1.preds[5].is_br, bpd.io.resp.f1.preds[5].predicted_pc.valid) node _f1_predicted_ghist_T_6 = and(bpd.io.resp.f1.preds[6].is_br, bpd.io.resp.f1.preds[6].predicted_pc.valid) node _f1_predicted_ghist_T_7 = and(bpd.io.resp.f1.preds[7].is_br, bpd.io.resp.f1.preds[7].predicted_pc.valid) node f1_predicted_ghist_lo_lo = cat(_f1_predicted_ghist_T_1, _f1_predicted_ghist_T) node f1_predicted_ghist_lo_hi = cat(_f1_predicted_ghist_T_3, _f1_predicted_ghist_T_2) node f1_predicted_ghist_lo = cat(f1_predicted_ghist_lo_hi, f1_predicted_ghist_lo_lo) node f1_predicted_ghist_hi_lo = cat(_f1_predicted_ghist_T_5, _f1_predicted_ghist_T_4) node f1_predicted_ghist_hi_hi = cat(_f1_predicted_ghist_T_7, _f1_predicted_ghist_T_6) node f1_predicted_ghist_hi = cat(f1_predicted_ghist_hi_hi, f1_predicted_ghist_hi_lo) node _f1_predicted_ghist_T_8 = cat(f1_predicted_ghist_hi, f1_predicted_ghist_lo) node _f1_predicted_ghist_T_9 = and(_f1_predicted_ghist_T_8, f1_mask) node _f1_predicted_ghist_T_10 = and(bpd.io.resp.f1.preds[f1_redirect_idx].taken, f1_do_redirect) node f1_predicted_ghist_cfi_idx_fixed = bits(f1_redirect_idx, 2, 0) node f1_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f1_predicted_ghist_cfi_idx_fixed) wire f1_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f1_predicted_ghist_not_taken_branches_T = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_1 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f1_predicted_ghist_not_taken_branches_T_2 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f1_predicted_ghist_not_taken_branches_T_3 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f1_predicted_ghist_not_taken_branches_T_4 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h4)) node _f1_predicted_ghist_not_taken_branches_T_5 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h5)) node _f1_predicted_ghist_not_taken_branches_T_6 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h6)) node _f1_predicted_ghist_not_taken_branches_T_7 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<3>(0h7)) node _f1_predicted_ghist_not_taken_branches_T_8 = or(_f1_predicted_ghist_not_taken_branches_T, _f1_predicted_ghist_not_taken_branches_T_1) node _f1_predicted_ghist_not_taken_branches_T_9 = or(_f1_predicted_ghist_not_taken_branches_T_8, _f1_predicted_ghist_not_taken_branches_T_2) node _f1_predicted_ghist_not_taken_branches_T_10 = or(_f1_predicted_ghist_not_taken_branches_T_9, _f1_predicted_ghist_not_taken_branches_T_3) node _f1_predicted_ghist_not_taken_branches_T_11 = or(_f1_predicted_ghist_not_taken_branches_T_10, _f1_predicted_ghist_not_taken_branches_T_4) node _f1_predicted_ghist_not_taken_branches_T_12 = or(_f1_predicted_ghist_not_taken_branches_T_11, _f1_predicted_ghist_not_taken_branches_T_5) node _f1_predicted_ghist_not_taken_branches_T_13 = or(_f1_predicted_ghist_not_taken_branches_T_12, _f1_predicted_ghist_not_taken_branches_T_6) node _f1_predicted_ghist_not_taken_branches_T_14 = or(_f1_predicted_ghist_not_taken_branches_T_13, _f1_predicted_ghist_not_taken_branches_T_7) node _f1_predicted_ghist_not_taken_branches_T_15 = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, _f1_predicted_ghist_T_10) node _f1_predicted_ghist_not_taken_branches_T_16 = mux(_f1_predicted_ghist_not_taken_branches_T_15, f1_predicted_ghist_cfi_idx_oh, UInt<8>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_17 = not(_f1_predicted_ghist_not_taken_branches_T_16) node _f1_predicted_ghist_not_taken_branches_T_18 = and(_f1_predicted_ghist_not_taken_branches_T_14, _f1_predicted_ghist_not_taken_branches_T_17) node _f1_predicted_ghist_not_taken_branches_T_19 = not(UInt<8>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_20 = mux(f1_do_redirect, _f1_predicted_ghist_not_taken_branches_T_18, _f1_predicted_ghist_not_taken_branches_T_19) node f1_predicted_ghist_not_taken_branches = and(_f1_predicted_ghist_T_9, _f1_predicted_ghist_not_taken_branches_T_20) node _f1_predicted_ghist_base_T = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_base_T_1 = or(_f1_predicted_ghist_base_T, UInt<1>(0h1)) node _f1_predicted_ghist_base_T_2 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_base_T_3 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_base_T_2, s1_ghist.old_history) node f1_predicted_ghist_base = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_base_T_1, _f1_predicted_ghist_base_T_3) node _f1_predicted_ghist_cfi_in_bank_0_T = and(f1_do_redirect, _f1_predicted_ghist_T_10) node _f1_predicted_ghist_cfi_in_bank_0_T_1 = lt(f1_predicted_ghist_cfi_idx_fixed, UInt<3>(0h4)) node f1_predicted_ghist_cfi_in_bank_0 = and(_f1_predicted_ghist_cfi_in_bank_0_T, _f1_predicted_ghist_cfi_in_bank_0_T_1) node _f1_predicted_ghist_ignore_second_bank_T = bits(s1_vpc, 5, 3) node _f1_predicted_ghist_ignore_second_bank_T_1 = eq(_f1_predicted_ghist_ignore_second_bank_T, UInt<3>(0h7)) node _f1_predicted_ghist_ignore_second_bank_T_2 = and(UInt<1>(0h1), _f1_predicted_ghist_ignore_second_bank_T_1) node f1_predicted_ghist_ignore_second_bank = or(f1_predicted_ghist_cfi_in_bank_0, _f1_predicted_ghist_ignore_second_bank_T_2) node _f1_predicted_ghist_first_bank_saw_not_taken_T = bits(f1_predicted_ghist_not_taken_branches, 3, 0) node _f1_predicted_ghist_first_bank_saw_not_taken_T_1 = neq(_f1_predicted_ghist_first_bank_saw_not_taken_T, UInt<1>(0h0)) node f1_predicted_ghist_first_bank_saw_not_taken = or(_f1_predicted_ghist_first_bank_saw_not_taken_T_1, s1_ghist.current_saw_branch_not_taken) connect f1_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) when f1_predicted_ghist_ignore_second_bank : node _f1_predicted_ghist_new_history_old_history_T = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_1 = or(_f1_predicted_ghist_new_history_old_history_T, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_2 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_3 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_2, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_4 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_1, _f1_predicted_ghist_new_history_old_history_T_3) connect f1_predicted_ghist.old_history, _f1_predicted_ghist_new_history_old_history_T_4 connect f1_predicted_ghist.new_saw_branch_not_taken, f1_predicted_ghist_first_bank_saw_not_taken node _f1_predicted_ghist_new_history_new_saw_branch_taken_T = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, f1_predicted_ghist_cfi_in_bank_0) connect f1_predicted_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_new_saw_branch_taken_T else : node _f1_predicted_ghist_new_history_old_history_T_5 = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, f1_predicted_ghist_cfi_in_bank_0) node _f1_predicted_ghist_new_history_old_history_T_6 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_7 = or(_f1_predicted_ghist_new_history_old_history_T_6, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_8 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_9 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_8, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_10 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_7, _f1_predicted_ghist_new_history_old_history_T_9) node _f1_predicted_ghist_new_history_old_history_T_11 = shl(_f1_predicted_ghist_new_history_old_history_T_10, 1) node _f1_predicted_ghist_new_history_old_history_T_12 = or(_f1_predicted_ghist_new_history_old_history_T_11, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_13 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_14 = or(_f1_predicted_ghist_new_history_old_history_T_13, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_15 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_16 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_15, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_17 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_14, _f1_predicted_ghist_new_history_old_history_T_16) node _f1_predicted_ghist_new_history_old_history_T_18 = shl(_f1_predicted_ghist_new_history_old_history_T_17, 1) node _f1_predicted_ghist_new_history_old_history_T_19 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_20 = or(_f1_predicted_ghist_new_history_old_history_T_19, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_21 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_22 = mux(s1_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_old_history_T_21, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_23 = mux(s1_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_old_history_T_20, _f1_predicted_ghist_new_history_old_history_T_22) node _f1_predicted_ghist_new_history_old_history_T_24 = mux(f1_predicted_ghist_first_bank_saw_not_taken, _f1_predicted_ghist_new_history_old_history_T_18, _f1_predicted_ghist_new_history_old_history_T_23) node _f1_predicted_ghist_new_history_old_history_T_25 = mux(_f1_predicted_ghist_new_history_old_history_T_5, _f1_predicted_ghist_new_history_old_history_T_12, _f1_predicted_ghist_new_history_old_history_T_24) connect f1_predicted_ghist.old_history, _f1_predicted_ghist_new_history_old_history_T_25 node _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T = bits(f1_predicted_ghist_not_taken_branches, 7, 4) node _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = neq(_f1_predicted_ghist_new_history_new_saw_branch_not_taken_T, UInt<1>(0h0)) connect f1_predicted_ghist.new_saw_branch_not_taken, _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1 = and(f1_do_redirect, _f1_predicted_ghist_T_10) node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_2 = and(_f1_predicted_ghist_new_history_new_saw_branch_taken_T_1, bpd.io.resp.f1.preds[f1_redirect_idx].is_br) node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3 = eq(f1_predicted_ghist_cfi_in_bank_0, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4 = and(_f1_predicted_ghist_new_history_new_saw_branch_taken_T_2, _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3) connect f1_predicted_ghist.new_saw_branch_taken, _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4 node _f1_predicted_ghist_new_history_ras_idx_T = and(f1_do_redirect, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_ras_idx_T_1 = add(s1_ghist.ras_idx, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_ras_idx_T_2 = tail(_f1_predicted_ghist_new_history_ras_idx_T_1, 1) node _f1_predicted_ghist_new_history_ras_idx_T_3 = bits(_f1_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f1_predicted_ghist_new_history_ras_idx_T_4 = and(f1_do_redirect, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_ras_idx_T_5 = sub(s1_ghist.ras_idx, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_ras_idx_T_6 = tail(_f1_predicted_ghist_new_history_ras_idx_T_5, 1) node _f1_predicted_ghist_new_history_ras_idx_T_7 = bits(_f1_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f1_predicted_ghist_new_history_ras_idx_T_8 = mux(_f1_predicted_ghist_new_history_ras_idx_T_4, _f1_predicted_ghist_new_history_ras_idx_T_7, s1_ghist.ras_idx) node _f1_predicted_ghist_new_history_ras_idx_T_9 = mux(_f1_predicted_ghist_new_history_ras_idx_T, _f1_predicted_ghist_new_history_ras_idx_T_3, _f1_predicted_ghist_new_history_ras_idx_T_8) connect f1_predicted_ghist.ras_idx, _f1_predicted_ghist_new_history_ras_idx_T_9 node _T_4 = eq(s1_tlb_miss, UInt<1>(0h0)) node _T_5 = and(s1_valid, _T_4) when _T_5 : node _s0_valid_T = or(s1_tlb_resp.ae.inst, s1_tlb_resp.pf.inst) node _s0_valid_T_1 = eq(_s0_valid_T, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_1 connect s0_tsrc, UInt<2>(0h0) connect s0_vpc, f1_predicted_target connect s0_ghist, f1_predicted_ghist connect s0_is_replay, UInt<1>(0h0) node _s2_valid_T = eq(f1_clear, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_valid, _s2_valid_T_1 reg s2_vpc : UInt, clock connect s2_vpc, s1_vpc reg s2_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, clock connect s2_ghist, s1_ghist reg s2_ppc : UInt, clock connect s2_ppc, s1_ppc reg s2_tsrc : UInt, clock connect s2_tsrc, s1_tsrc wire s2_fsrc : UInt<2> connect s2_fsrc, UInt<2>(0h0) wire f2_clear : UInt<1> connect f2_clear, UInt<1>(0h0) reg s2_tlb_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>}, clock connect s2_tlb_resp, s1_tlb_resp reg s2_tlb_miss : UInt<1>, clock connect s2_tlb_miss, s1_tlb_miss reg s2_is_replay_REG : UInt<1>, clock connect s2_is_replay_REG, s1_is_replay node s2_is_replay = and(s2_is_replay_REG, s2_valid) node _s2_xcpt_T = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _s2_xcpt_T_1 = and(s2_valid, _s2_xcpt_T) node _s2_xcpt_T_2 = eq(s2_is_replay, UInt<1>(0h0)) node s2_xcpt = and(_s2_xcpt_T_1, _s2_xcpt_T_2) wire f3_ready : UInt<1> connect icache.io.s2_kill, s2_xcpt node f2_mask_idx = bits(s2_vpc, 3, 1) node f2_mask_shamt = bits(f2_mask_idx, 1, 0) node _f2_mask_end_mask_T = bits(s2_vpc, 5, 3) node _f2_mask_end_mask_T_1 = eq(_f2_mask_end_mask_T, UInt<3>(0h7)) node _f2_mask_end_mask_T_2 = and(UInt<1>(0h1), _f2_mask_end_mask_T_1) node _f2_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _f2_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node f2_mask_end_mask = mux(_f2_mask_end_mask_T_2, _f2_mask_end_mask_T_3, _f2_mask_end_mask_T_4) node _f2_mask_T = dshl(UInt<8>(0hff), f2_mask_shamt) node f2_mask = and(_f2_mask_T, f2_mask_end_mask) node _f2_redirects_T = bits(f2_mask, 0, 0) node _f2_redirects_T_1 = and(s2_valid, _f2_redirects_T) node _f2_redirects_T_2 = and(_f2_redirects_T_1, bpd.io.resp.f2.preds[0].predicted_pc.valid) node _f2_redirects_T_3 = and(bpd.io.resp.f2.preds[0].is_br, bpd.io.resp.f2.preds[0].taken) node _f2_redirects_T_4 = or(bpd.io.resp.f2.preds[0].is_jal, _f2_redirects_T_3) node f2_redirects_0 = and(_f2_redirects_T_2, _f2_redirects_T_4) node _f2_redirects_T_5 = bits(f2_mask, 1, 1) node _f2_redirects_T_6 = and(s2_valid, _f2_redirects_T_5) node _f2_redirects_T_7 = and(_f2_redirects_T_6, bpd.io.resp.f2.preds[1].predicted_pc.valid) node _f2_redirects_T_8 = and(bpd.io.resp.f2.preds[1].is_br, bpd.io.resp.f2.preds[1].taken) node _f2_redirects_T_9 = or(bpd.io.resp.f2.preds[1].is_jal, _f2_redirects_T_8) node f2_redirects_1 = and(_f2_redirects_T_7, _f2_redirects_T_9) node _f2_redirects_T_10 = bits(f2_mask, 2, 2) node _f2_redirects_T_11 = and(s2_valid, _f2_redirects_T_10) node _f2_redirects_T_12 = and(_f2_redirects_T_11, bpd.io.resp.f2.preds[2].predicted_pc.valid) node _f2_redirects_T_13 = and(bpd.io.resp.f2.preds[2].is_br, bpd.io.resp.f2.preds[2].taken) node _f2_redirects_T_14 = or(bpd.io.resp.f2.preds[2].is_jal, _f2_redirects_T_13) node f2_redirects_2 = and(_f2_redirects_T_12, _f2_redirects_T_14) node _f2_redirects_T_15 = bits(f2_mask, 3, 3) node _f2_redirects_T_16 = and(s2_valid, _f2_redirects_T_15) node _f2_redirects_T_17 = and(_f2_redirects_T_16, bpd.io.resp.f2.preds[3].predicted_pc.valid) node _f2_redirects_T_18 = and(bpd.io.resp.f2.preds[3].is_br, bpd.io.resp.f2.preds[3].taken) node _f2_redirects_T_19 = or(bpd.io.resp.f2.preds[3].is_jal, _f2_redirects_T_18) node f2_redirects_3 = and(_f2_redirects_T_17, _f2_redirects_T_19) node _f2_redirects_T_20 = bits(f2_mask, 4, 4) node _f2_redirects_T_21 = and(s2_valid, _f2_redirects_T_20) node _f2_redirects_T_22 = and(_f2_redirects_T_21, bpd.io.resp.f2.preds[4].predicted_pc.valid) node _f2_redirects_T_23 = and(bpd.io.resp.f2.preds[4].is_br, bpd.io.resp.f2.preds[4].taken) node _f2_redirects_T_24 = or(bpd.io.resp.f2.preds[4].is_jal, _f2_redirects_T_23) node f2_redirects_4 = and(_f2_redirects_T_22, _f2_redirects_T_24) node _f2_redirects_T_25 = bits(f2_mask, 5, 5) node _f2_redirects_T_26 = and(s2_valid, _f2_redirects_T_25) node _f2_redirects_T_27 = and(_f2_redirects_T_26, bpd.io.resp.f2.preds[5].predicted_pc.valid) node _f2_redirects_T_28 = and(bpd.io.resp.f2.preds[5].is_br, bpd.io.resp.f2.preds[5].taken) node _f2_redirects_T_29 = or(bpd.io.resp.f2.preds[5].is_jal, _f2_redirects_T_28) node f2_redirects_5 = and(_f2_redirects_T_27, _f2_redirects_T_29) node _f2_redirects_T_30 = bits(f2_mask, 6, 6) node _f2_redirects_T_31 = and(s2_valid, _f2_redirects_T_30) node _f2_redirects_T_32 = and(_f2_redirects_T_31, bpd.io.resp.f2.preds[6].predicted_pc.valid) node _f2_redirects_T_33 = and(bpd.io.resp.f2.preds[6].is_br, bpd.io.resp.f2.preds[6].taken) node _f2_redirects_T_34 = or(bpd.io.resp.f2.preds[6].is_jal, _f2_redirects_T_33) node f2_redirects_6 = and(_f2_redirects_T_32, _f2_redirects_T_34) node _f2_redirects_T_35 = bits(f2_mask, 7, 7) node _f2_redirects_T_36 = and(s2_valid, _f2_redirects_T_35) node _f2_redirects_T_37 = and(_f2_redirects_T_36, bpd.io.resp.f2.preds[7].predicted_pc.valid) node _f2_redirects_T_38 = and(bpd.io.resp.f2.preds[7].is_br, bpd.io.resp.f2.preds[7].taken) node _f2_redirects_T_39 = or(bpd.io.resp.f2.preds[7].is_jal, _f2_redirects_T_38) node f2_redirects_7 = and(_f2_redirects_T_37, _f2_redirects_T_39) node _f2_redirect_idx_T = mux(f2_redirects_6, UInt<3>(0h6), UInt<3>(0h7)) node _f2_redirect_idx_T_1 = mux(f2_redirects_5, UInt<3>(0h5), _f2_redirect_idx_T) node _f2_redirect_idx_T_2 = mux(f2_redirects_4, UInt<3>(0h4), _f2_redirect_idx_T_1) node _f2_redirect_idx_T_3 = mux(f2_redirects_3, UInt<2>(0h3), _f2_redirect_idx_T_2) node _f2_redirect_idx_T_4 = mux(f2_redirects_2, UInt<2>(0h2), _f2_redirect_idx_T_3) node _f2_redirect_idx_T_5 = mux(f2_redirects_1, UInt<1>(0h1), _f2_redirect_idx_T_4) node f2_redirect_idx = mux(f2_redirects_0, UInt<1>(0h0), _f2_redirect_idx_T_5) node _f2_do_redirect_T = or(f2_redirects_0, f2_redirects_1) node _f2_do_redirect_T_1 = or(_f2_do_redirect_T, f2_redirects_2) node _f2_do_redirect_T_2 = or(_f2_do_redirect_T_1, f2_redirects_3) node _f2_do_redirect_T_3 = or(_f2_do_redirect_T_2, f2_redirects_4) node _f2_do_redirect_T_4 = or(_f2_do_redirect_T_3, f2_redirects_5) node _f2_do_redirect_T_5 = or(_f2_do_redirect_T_4, f2_redirects_6) node _f2_do_redirect_T_6 = or(_f2_do_redirect_T_5, f2_redirects_7) node f2_do_redirect = and(_f2_do_redirect_T_6, UInt<1>(0h1)) node _f2_predicted_target_T = eq(f2_redirect_idx, UInt<1>(0h1)) node _f2_predicted_target_T_1 = mux(_f2_predicted_target_T, bpd.io.resp.f2.preds[1].predicted_pc.bits, bpd.io.resp.f2.preds[0].predicted_pc.bits) node _f2_predicted_target_T_2 = eq(f2_redirect_idx, UInt<2>(0h2)) node _f2_predicted_target_T_3 = mux(_f2_predicted_target_T_2, bpd.io.resp.f2.preds[2].predicted_pc.bits, _f2_predicted_target_T_1) node _f2_predicted_target_T_4 = eq(f2_redirect_idx, UInt<2>(0h3)) node _f2_predicted_target_T_5 = mux(_f2_predicted_target_T_4, bpd.io.resp.f2.preds[3].predicted_pc.bits, _f2_predicted_target_T_3) node _f2_predicted_target_T_6 = eq(f2_redirect_idx, UInt<3>(0h4)) node _f2_predicted_target_T_7 = mux(_f2_predicted_target_T_6, bpd.io.resp.f2.preds[4].predicted_pc.bits, _f2_predicted_target_T_5) node _f2_predicted_target_T_8 = eq(f2_redirect_idx, UInt<3>(0h5)) node _f2_predicted_target_T_9 = mux(_f2_predicted_target_T_8, bpd.io.resp.f2.preds[5].predicted_pc.bits, _f2_predicted_target_T_7) node _f2_predicted_target_T_10 = eq(f2_redirect_idx, UInt<3>(0h6)) node _f2_predicted_target_T_11 = mux(_f2_predicted_target_T_10, bpd.io.resp.f2.preds[6].predicted_pc.bits, _f2_predicted_target_T_9) node _f2_predicted_target_T_12 = eq(f2_redirect_idx, UInt<3>(0h7)) node _f2_predicted_target_T_13 = mux(_f2_predicted_target_T_12, bpd.io.resp.f2.preds[7].predicted_pc.bits, _f2_predicted_target_T_11) node _f2_predicted_target_T_14 = not(s2_vpc) node _f2_predicted_target_T_15 = or(_f2_predicted_target_T_14, UInt<3>(0h7)) node _f2_predicted_target_T_16 = not(_f2_predicted_target_T_15) node _f2_predicted_target_T_17 = bits(s2_vpc, 5, 3) node _f2_predicted_target_T_18 = eq(_f2_predicted_target_T_17, UInt<3>(0h7)) node _f2_predicted_target_T_19 = and(UInt<1>(0h1), _f2_predicted_target_T_18) node _f2_predicted_target_T_20 = mux(_f2_predicted_target_T_19, UInt<4>(0h8), UInt<5>(0h10)) node _f2_predicted_target_T_21 = add(_f2_predicted_target_T_16, _f2_predicted_target_T_20) node _f2_predicted_target_T_22 = tail(_f2_predicted_target_T_21, 1) node f2_predicted_target = mux(f2_do_redirect, _f2_predicted_target_T_13, _f2_predicted_target_T_22) node _f2_predicted_ghist_T = and(bpd.io.resp.f2.preds[0].is_br, bpd.io.resp.f2.preds[0].predicted_pc.valid) node _f2_predicted_ghist_T_1 = and(bpd.io.resp.f2.preds[1].is_br, bpd.io.resp.f2.preds[1].predicted_pc.valid) node _f2_predicted_ghist_T_2 = and(bpd.io.resp.f2.preds[2].is_br, bpd.io.resp.f2.preds[2].predicted_pc.valid) node _f2_predicted_ghist_T_3 = and(bpd.io.resp.f2.preds[3].is_br, bpd.io.resp.f2.preds[3].predicted_pc.valid) node _f2_predicted_ghist_T_4 = and(bpd.io.resp.f2.preds[4].is_br, bpd.io.resp.f2.preds[4].predicted_pc.valid) node _f2_predicted_ghist_T_5 = and(bpd.io.resp.f2.preds[5].is_br, bpd.io.resp.f2.preds[5].predicted_pc.valid) node _f2_predicted_ghist_T_6 = and(bpd.io.resp.f2.preds[6].is_br, bpd.io.resp.f2.preds[6].predicted_pc.valid) node _f2_predicted_ghist_T_7 = and(bpd.io.resp.f2.preds[7].is_br, bpd.io.resp.f2.preds[7].predicted_pc.valid) node f2_predicted_ghist_lo_lo = cat(_f2_predicted_ghist_T_1, _f2_predicted_ghist_T) node f2_predicted_ghist_lo_hi = cat(_f2_predicted_ghist_T_3, _f2_predicted_ghist_T_2) node f2_predicted_ghist_lo = cat(f2_predicted_ghist_lo_hi, f2_predicted_ghist_lo_lo) node f2_predicted_ghist_hi_lo = cat(_f2_predicted_ghist_T_5, _f2_predicted_ghist_T_4) node f2_predicted_ghist_hi_hi = cat(_f2_predicted_ghist_T_7, _f2_predicted_ghist_T_6) node f2_predicted_ghist_hi = cat(f2_predicted_ghist_hi_hi, f2_predicted_ghist_hi_lo) node _f2_predicted_ghist_T_8 = cat(f2_predicted_ghist_hi, f2_predicted_ghist_lo) node _f2_predicted_ghist_T_9 = and(_f2_predicted_ghist_T_8, f2_mask) node _f2_predicted_ghist_T_10 = and(bpd.io.resp.f2.preds[f2_redirect_idx].taken, f2_do_redirect) node f2_predicted_ghist_cfi_idx_fixed = bits(f2_redirect_idx, 2, 0) node f2_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f2_predicted_ghist_cfi_idx_fixed) wire f2_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f2_predicted_ghist_not_taken_branches_T = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_1 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f2_predicted_ghist_not_taken_branches_T_2 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f2_predicted_ghist_not_taken_branches_T_3 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f2_predicted_ghist_not_taken_branches_T_4 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h4)) node _f2_predicted_ghist_not_taken_branches_T_5 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h5)) node _f2_predicted_ghist_not_taken_branches_T_6 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h6)) node _f2_predicted_ghist_not_taken_branches_T_7 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<3>(0h7)) node _f2_predicted_ghist_not_taken_branches_T_8 = or(_f2_predicted_ghist_not_taken_branches_T, _f2_predicted_ghist_not_taken_branches_T_1) node _f2_predicted_ghist_not_taken_branches_T_9 = or(_f2_predicted_ghist_not_taken_branches_T_8, _f2_predicted_ghist_not_taken_branches_T_2) node _f2_predicted_ghist_not_taken_branches_T_10 = or(_f2_predicted_ghist_not_taken_branches_T_9, _f2_predicted_ghist_not_taken_branches_T_3) node _f2_predicted_ghist_not_taken_branches_T_11 = or(_f2_predicted_ghist_not_taken_branches_T_10, _f2_predicted_ghist_not_taken_branches_T_4) node _f2_predicted_ghist_not_taken_branches_T_12 = or(_f2_predicted_ghist_not_taken_branches_T_11, _f2_predicted_ghist_not_taken_branches_T_5) node _f2_predicted_ghist_not_taken_branches_T_13 = or(_f2_predicted_ghist_not_taken_branches_T_12, _f2_predicted_ghist_not_taken_branches_T_6) node _f2_predicted_ghist_not_taken_branches_T_14 = or(_f2_predicted_ghist_not_taken_branches_T_13, _f2_predicted_ghist_not_taken_branches_T_7) node _f2_predicted_ghist_not_taken_branches_T_15 = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, _f2_predicted_ghist_T_10) node _f2_predicted_ghist_not_taken_branches_T_16 = mux(_f2_predicted_ghist_not_taken_branches_T_15, f2_predicted_ghist_cfi_idx_oh, UInt<8>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_17 = not(_f2_predicted_ghist_not_taken_branches_T_16) node _f2_predicted_ghist_not_taken_branches_T_18 = and(_f2_predicted_ghist_not_taken_branches_T_14, _f2_predicted_ghist_not_taken_branches_T_17) node _f2_predicted_ghist_not_taken_branches_T_19 = not(UInt<8>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_20 = mux(f2_do_redirect, _f2_predicted_ghist_not_taken_branches_T_18, _f2_predicted_ghist_not_taken_branches_T_19) node f2_predicted_ghist_not_taken_branches = and(_f2_predicted_ghist_T_9, _f2_predicted_ghist_not_taken_branches_T_20) node _f2_predicted_ghist_base_T = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_base_T_1 = or(_f2_predicted_ghist_base_T, UInt<1>(0h1)) node _f2_predicted_ghist_base_T_2 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_base_T_3 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_base_T_2, s2_ghist.old_history) node f2_predicted_ghist_base = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_base_T_1, _f2_predicted_ghist_base_T_3) node _f2_predicted_ghist_cfi_in_bank_0_T = and(f2_do_redirect, _f2_predicted_ghist_T_10) node _f2_predicted_ghist_cfi_in_bank_0_T_1 = lt(f2_predicted_ghist_cfi_idx_fixed, UInt<3>(0h4)) node f2_predicted_ghist_cfi_in_bank_0 = and(_f2_predicted_ghist_cfi_in_bank_0_T, _f2_predicted_ghist_cfi_in_bank_0_T_1) node _f2_predicted_ghist_ignore_second_bank_T = bits(s2_vpc, 5, 3) node _f2_predicted_ghist_ignore_second_bank_T_1 = eq(_f2_predicted_ghist_ignore_second_bank_T, UInt<3>(0h7)) node _f2_predicted_ghist_ignore_second_bank_T_2 = and(UInt<1>(0h1), _f2_predicted_ghist_ignore_second_bank_T_1) node f2_predicted_ghist_ignore_second_bank = or(f2_predicted_ghist_cfi_in_bank_0, _f2_predicted_ghist_ignore_second_bank_T_2) node _f2_predicted_ghist_first_bank_saw_not_taken_T = bits(f2_predicted_ghist_not_taken_branches, 3, 0) node _f2_predicted_ghist_first_bank_saw_not_taken_T_1 = neq(_f2_predicted_ghist_first_bank_saw_not_taken_T, UInt<1>(0h0)) node f2_predicted_ghist_first_bank_saw_not_taken = or(_f2_predicted_ghist_first_bank_saw_not_taken_T_1, s2_ghist.current_saw_branch_not_taken) connect f2_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) when f2_predicted_ghist_ignore_second_bank : node _f2_predicted_ghist_new_history_old_history_T = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_1 = or(_f2_predicted_ghist_new_history_old_history_T, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_2 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_3 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_2, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_4 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_1, _f2_predicted_ghist_new_history_old_history_T_3) connect f2_predicted_ghist.old_history, _f2_predicted_ghist_new_history_old_history_T_4 connect f2_predicted_ghist.new_saw_branch_not_taken, f2_predicted_ghist_first_bank_saw_not_taken node _f2_predicted_ghist_new_history_new_saw_branch_taken_T = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, f2_predicted_ghist_cfi_in_bank_0) connect f2_predicted_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_new_saw_branch_taken_T else : node _f2_predicted_ghist_new_history_old_history_T_5 = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, f2_predicted_ghist_cfi_in_bank_0) node _f2_predicted_ghist_new_history_old_history_T_6 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_7 = or(_f2_predicted_ghist_new_history_old_history_T_6, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_8 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_9 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_8, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_10 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_7, _f2_predicted_ghist_new_history_old_history_T_9) node _f2_predicted_ghist_new_history_old_history_T_11 = shl(_f2_predicted_ghist_new_history_old_history_T_10, 1) node _f2_predicted_ghist_new_history_old_history_T_12 = or(_f2_predicted_ghist_new_history_old_history_T_11, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_13 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_14 = or(_f2_predicted_ghist_new_history_old_history_T_13, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_15 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_16 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_15, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_17 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_14, _f2_predicted_ghist_new_history_old_history_T_16) node _f2_predicted_ghist_new_history_old_history_T_18 = shl(_f2_predicted_ghist_new_history_old_history_T_17, 1) node _f2_predicted_ghist_new_history_old_history_T_19 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_20 = or(_f2_predicted_ghist_new_history_old_history_T_19, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_21 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_22 = mux(s2_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_old_history_T_21, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_23 = mux(s2_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_old_history_T_20, _f2_predicted_ghist_new_history_old_history_T_22) node _f2_predicted_ghist_new_history_old_history_T_24 = mux(f2_predicted_ghist_first_bank_saw_not_taken, _f2_predicted_ghist_new_history_old_history_T_18, _f2_predicted_ghist_new_history_old_history_T_23) node _f2_predicted_ghist_new_history_old_history_T_25 = mux(_f2_predicted_ghist_new_history_old_history_T_5, _f2_predicted_ghist_new_history_old_history_T_12, _f2_predicted_ghist_new_history_old_history_T_24) connect f2_predicted_ghist.old_history, _f2_predicted_ghist_new_history_old_history_T_25 node _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T = bits(f2_predicted_ghist_not_taken_branches, 7, 4) node _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = neq(_f2_predicted_ghist_new_history_new_saw_branch_not_taken_T, UInt<1>(0h0)) connect f2_predicted_ghist.new_saw_branch_not_taken, _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1 = and(f2_do_redirect, _f2_predicted_ghist_T_10) node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_2 = and(_f2_predicted_ghist_new_history_new_saw_branch_taken_T_1, bpd.io.resp.f2.preds[f2_redirect_idx].is_br) node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3 = eq(f2_predicted_ghist_cfi_in_bank_0, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4 = and(_f2_predicted_ghist_new_history_new_saw_branch_taken_T_2, _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3) connect f2_predicted_ghist.new_saw_branch_taken, _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4 node _f2_predicted_ghist_new_history_ras_idx_T = and(f2_do_redirect, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_ras_idx_T_1 = add(s2_ghist.ras_idx, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_ras_idx_T_2 = tail(_f2_predicted_ghist_new_history_ras_idx_T_1, 1) node _f2_predicted_ghist_new_history_ras_idx_T_3 = bits(_f2_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f2_predicted_ghist_new_history_ras_idx_T_4 = and(f2_do_redirect, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_ras_idx_T_5 = sub(s2_ghist.ras_idx, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_ras_idx_T_6 = tail(_f2_predicted_ghist_new_history_ras_idx_T_5, 1) node _f2_predicted_ghist_new_history_ras_idx_T_7 = bits(_f2_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f2_predicted_ghist_new_history_ras_idx_T_8 = mux(_f2_predicted_ghist_new_history_ras_idx_T_4, _f2_predicted_ghist_new_history_ras_idx_T_7, s2_ghist.ras_idx) node _f2_predicted_ghist_new_history_ras_idx_T_9 = mux(_f2_predicted_ghist_new_history_ras_idx_T, _f2_predicted_ghist_new_history_ras_idx_T_3, _f2_predicted_ghist_new_history_ras_idx_T_8) connect f2_predicted_ghist.ras_idx, _f2_predicted_ghist_new_history_ras_idx_T_9 node _f2_correct_f1_ghist_T = eq(s1_ghist.old_history, f2_predicted_ghist.old_history) node _f2_correct_f1_ghist_T_1 = eq(s1_ghist.new_saw_branch_not_taken, f2_predicted_ghist.new_saw_branch_not_taken) node _f2_correct_f1_ghist_T_2 = and(_f2_correct_f1_ghist_T, _f2_correct_f1_ghist_T_1) node _f2_correct_f1_ghist_T_3 = eq(s1_ghist.new_saw_branch_taken, f2_predicted_ghist.new_saw_branch_taken) node _f2_correct_f1_ghist_T_4 = and(_f2_correct_f1_ghist_T_2, _f2_correct_f1_ghist_T_3) node _f2_correct_f1_ghist_T_5 = eq(_f2_correct_f1_ghist_T_4, UInt<1>(0h0)) node f2_correct_f1_ghist = and(_f2_correct_f1_ghist_T_5, UInt<1>(0h1)) node _T_6 = eq(icache.io.resp.valid, UInt<1>(0h0)) node _T_7 = and(s2_valid, _T_6) node _T_8 = and(s2_valid, icache.io.resp.valid) node _T_9 = eq(f3_ready, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = or(_T_7, _T_10) when _T_11 : node _s0_valid_T_2 = eq(s2_tlb_resp.ae.inst, UInt<1>(0h0)) node _s0_valid_T_3 = eq(s2_tlb_resp.pf.inst, UInt<1>(0h0)) node _s0_valid_T_4 = and(_s0_valid_T_2, _s0_valid_T_3) node _s0_valid_T_5 = or(_s0_valid_T_4, s2_is_replay) node _s0_valid_T_6 = or(_s0_valid_T_5, s2_tlb_miss) connect s0_valid, _s0_valid_T_6 connect s0_vpc, s2_vpc node _s0_is_replay_T = and(s2_valid, icache.io.resp.valid) connect s0_is_replay, _s0_is_replay_T node _s0_s1_use_f3_bpd_resp_T = eq(s2_is_replay, UInt<1>(0h0)) connect s0_s1_use_f3_bpd_resp, _s0_s1_use_f3_bpd_resp_T connect s0_ghist, s2_ghist connect s0_tsrc, s2_tsrc connect f1_clear, UInt<1>(0h1) else : node _T_12 = and(s2_valid, f3_ready) when _T_12 : node _T_13 = eq(s1_vpc, f2_predicted_target) node _T_14 = and(s1_valid, _T_13) node _T_15 = eq(f2_correct_f1_ghist, UInt<1>(0h0)) node _T_16 = and(_T_14, _T_15) when _T_16 : connect s2_ghist, f2_predicted_ghist node _T_17 = neq(s1_vpc, f2_predicted_target) node _T_18 = or(_T_17, f2_correct_f1_ghist) node _T_19 = and(s1_valid, _T_18) node _T_20 = eq(s1_valid, UInt<1>(0h0)) node _T_21 = or(_T_19, _T_20) when _T_21 : connect f1_clear, UInt<1>(0h1) node _s0_valid_T_7 = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _s0_valid_T_8 = eq(s2_is_replay, UInt<1>(0h0)) node _s0_valid_T_9 = and(_s0_valid_T_7, _s0_valid_T_8) node _s0_valid_T_10 = eq(_s0_valid_T_9, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_10 connect s0_vpc, f2_predicted_target connect s0_is_replay, UInt<1>(0h0) connect s0_ghist, f2_predicted_ghist connect s2_fsrc, UInt<2>(0h1) connect s0_tsrc, UInt<2>(0h1) connect s0_replay_bpd_resp.lhist, bpd.io.resp.f2.lhist connect s0_replay_bpd_resp.meta, bpd.io.resp.f2.meta connect s0_replay_bpd_resp.preds[0].predicted_pc, bpd.io.resp.f2.preds[0].predicted_pc connect s0_replay_bpd_resp.preds[0].is_jal, bpd.io.resp.f2.preds[0].is_jal connect s0_replay_bpd_resp.preds[0].is_br, bpd.io.resp.f2.preds[0].is_br connect s0_replay_bpd_resp.preds[0].taken, bpd.io.resp.f2.preds[0].taken connect s0_replay_bpd_resp.preds[1].predicted_pc, bpd.io.resp.f2.preds[1].predicted_pc connect s0_replay_bpd_resp.preds[1].is_jal, bpd.io.resp.f2.preds[1].is_jal connect s0_replay_bpd_resp.preds[1].is_br, bpd.io.resp.f2.preds[1].is_br connect s0_replay_bpd_resp.preds[1].taken, bpd.io.resp.f2.preds[1].taken connect s0_replay_bpd_resp.preds[2].predicted_pc, bpd.io.resp.f2.preds[2].predicted_pc connect s0_replay_bpd_resp.preds[2].is_jal, bpd.io.resp.f2.preds[2].is_jal connect s0_replay_bpd_resp.preds[2].is_br, bpd.io.resp.f2.preds[2].is_br connect s0_replay_bpd_resp.preds[2].taken, bpd.io.resp.f2.preds[2].taken connect s0_replay_bpd_resp.preds[3].predicted_pc, bpd.io.resp.f2.preds[3].predicted_pc connect s0_replay_bpd_resp.preds[3].is_jal, bpd.io.resp.f2.preds[3].is_jal connect s0_replay_bpd_resp.preds[3].is_br, bpd.io.resp.f2.preds[3].is_br connect s0_replay_bpd_resp.preds[3].taken, bpd.io.resp.f2.preds[3].taken connect s0_replay_bpd_resp.preds[4].predicted_pc, bpd.io.resp.f2.preds[4].predicted_pc connect s0_replay_bpd_resp.preds[4].is_jal, bpd.io.resp.f2.preds[4].is_jal connect s0_replay_bpd_resp.preds[4].is_br, bpd.io.resp.f2.preds[4].is_br connect s0_replay_bpd_resp.preds[4].taken, bpd.io.resp.f2.preds[4].taken connect s0_replay_bpd_resp.preds[5].predicted_pc, bpd.io.resp.f2.preds[5].predicted_pc connect s0_replay_bpd_resp.preds[5].is_jal, bpd.io.resp.f2.preds[5].is_jal connect s0_replay_bpd_resp.preds[5].is_br, bpd.io.resp.f2.preds[5].is_br connect s0_replay_bpd_resp.preds[5].taken, bpd.io.resp.f2.preds[5].taken connect s0_replay_bpd_resp.preds[6].predicted_pc, bpd.io.resp.f2.preds[6].predicted_pc connect s0_replay_bpd_resp.preds[6].is_jal, bpd.io.resp.f2.preds[6].is_jal connect s0_replay_bpd_resp.preds[6].is_br, bpd.io.resp.f2.preds[6].is_br connect s0_replay_bpd_resp.preds[6].taken, bpd.io.resp.f2.preds[6].taken connect s0_replay_bpd_resp.preds[7].predicted_pc, bpd.io.resp.f2.preds[7].predicted_pc connect s0_replay_bpd_resp.preds[7].is_jal, bpd.io.resp.f2.preds[7].is_jal connect s0_replay_bpd_resp.preds[7].is_br, bpd.io.resp.f2.preds[7].is_br connect s0_replay_bpd_resp.preds[7].taken, bpd.io.resp.f2.preds[7].taken connect s0_replay_bpd_resp.pc, bpd.io.resp.f2.pc connect s0_replay_resp, s2_tlb_resp connect s0_replay_ppc, s2_ppc wire f3_clear : UInt<1> connect f3_clear, UInt<1>(0h0) node _T_22 = asUInt(reset) node _T_23 = or(_T_22, f3_clear) inst f3 of Queue1_FrontendResp_1 connect f3.clock, clock connect f3.reset, _T_23 node _T_24 = asUInt(reset) node _T_25 = or(_T_24, f3_clear) inst f3_bpd_resp of Queue1_BranchPredictionBundle_1 connect f3_bpd_resp.clock, clock connect f3_bpd_resp.reset, _T_25 wire f4_ready : UInt<1> connect f3_ready, f3.io.enq.ready node _f3_io_enq_valid_T = eq(f2_clear, UInt<1>(0h0)) node _f3_io_enq_valid_T_1 = and(s2_valid, _f3_io_enq_valid_T) node _f3_io_enq_valid_T_2 = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _f3_io_enq_valid_T_3 = eq(s2_tlb_miss, UInt<1>(0h0)) node _f3_io_enq_valid_T_4 = and(_f3_io_enq_valid_T_2, _f3_io_enq_valid_T_3) node _f3_io_enq_valid_T_5 = or(icache.io.resp.valid, _f3_io_enq_valid_T_4) node _f3_io_enq_valid_T_6 = and(_f3_io_enq_valid_T_1, _f3_io_enq_valid_T_5) connect f3.io.enq.valid, _f3_io_enq_valid_T_6 connect f3.io.enq.bits.pc, s2_vpc node _f3_io_enq_bits_data_T = mux(s2_xcpt, UInt<1>(0h0), icache.io.resp.bits.data) connect f3.io.enq.bits.data, _f3_io_enq_bits_data_T connect f3.io.enq.bits.ghist.ras_idx, s2_ghist.ras_idx connect f3.io.enq.bits.ghist.new_saw_branch_taken, s2_ghist.new_saw_branch_taken connect f3.io.enq.bits.ghist.new_saw_branch_not_taken, s2_ghist.new_saw_branch_not_taken connect f3.io.enq.bits.ghist.current_saw_branch_not_taken, s2_ghist.current_saw_branch_not_taken connect f3.io.enq.bits.ghist.old_history, s2_ghist.old_history node f3_io_enq_bits_mask_idx = bits(s2_vpc, 3, 1) node f3_io_enq_bits_mask_shamt = bits(f3_io_enq_bits_mask_idx, 1, 0) node _f3_io_enq_bits_mask_end_mask_T = bits(s2_vpc, 5, 3) node _f3_io_enq_bits_mask_end_mask_T_1 = eq(_f3_io_enq_bits_mask_end_mask_T, UInt<3>(0h7)) node _f3_io_enq_bits_mask_end_mask_T_2 = and(UInt<1>(0h1), _f3_io_enq_bits_mask_end_mask_T_1) node _f3_io_enq_bits_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _f3_io_enq_bits_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node f3_io_enq_bits_mask_end_mask = mux(_f3_io_enq_bits_mask_end_mask_T_2, _f3_io_enq_bits_mask_end_mask_T_3, _f3_io_enq_bits_mask_end_mask_T_4) node _f3_io_enq_bits_mask_T = dshl(UInt<8>(0hff), f3_io_enq_bits_mask_shamt) node _f3_io_enq_bits_mask_T_1 = and(_f3_io_enq_bits_mask_T, f3_io_enq_bits_mask_end_mask) connect f3.io.enq.bits.mask, _f3_io_enq_bits_mask_T_1 connect f3.io.enq.bits.xcpt.ae.inst, s2_tlb_resp.ae.inst connect f3.io.enq.bits.xcpt.gf.inst, s2_tlb_resp.gf.inst connect f3.io.enq.bits.xcpt.pf.inst, s2_tlb_resp.pf.inst connect f3.io.enq.bits.fsrc, s2_fsrc connect f3.io.enq.bits.tsrc, s2_tsrc regreset ras_read_idx : UInt<5>, clock, reset, UInt<5>(0h0) connect ras.io.read_idx, ras_read_idx node _T_26 = and(f3.io.enq.ready, f3.io.enq.valid) when _T_26 : connect ras_read_idx, f3.io.enq.bits.ghist.ras_idx connect ras.io.read_idx, f3.io.enq.bits.ghist.ras_idx reg f3_bpd_resp_io_enq_valid_REG : UInt<1>, clock connect f3_bpd_resp_io_enq_valid_REG, f3.io.enq.ready node _f3_bpd_resp_io_enq_valid_T = and(f3.io.deq.valid, f3_bpd_resp_io_enq_valid_REG) connect f3_bpd_resp.io.enq.valid, _f3_bpd_resp_io_enq_valid_T connect f3_bpd_resp.io.enq.bits.lhist[0], bpd.io.resp.f3.lhist[0] connect f3_bpd_resp.io.enq.bits.lhist[1], bpd.io.resp.f3.lhist[1] connect f3_bpd_resp.io.enq.bits.meta[0], bpd.io.resp.f3.meta[0] connect f3_bpd_resp.io.enq.bits.meta[1], bpd.io.resp.f3.meta[1] connect f3_bpd_resp.io.enq.bits.preds[0].predicted_pc.bits, bpd.io.resp.f3.preds[0].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[0].predicted_pc.valid, bpd.io.resp.f3.preds[0].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[0].is_jal, bpd.io.resp.f3.preds[0].is_jal connect f3_bpd_resp.io.enq.bits.preds[0].is_br, bpd.io.resp.f3.preds[0].is_br connect f3_bpd_resp.io.enq.bits.preds[0].taken, bpd.io.resp.f3.preds[0].taken connect f3_bpd_resp.io.enq.bits.preds[1].predicted_pc.bits, bpd.io.resp.f3.preds[1].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[1].predicted_pc.valid, bpd.io.resp.f3.preds[1].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[1].is_jal, bpd.io.resp.f3.preds[1].is_jal connect f3_bpd_resp.io.enq.bits.preds[1].is_br, bpd.io.resp.f3.preds[1].is_br connect f3_bpd_resp.io.enq.bits.preds[1].taken, bpd.io.resp.f3.preds[1].taken connect f3_bpd_resp.io.enq.bits.preds[2].predicted_pc.bits, bpd.io.resp.f3.preds[2].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[2].predicted_pc.valid, bpd.io.resp.f3.preds[2].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[2].is_jal, bpd.io.resp.f3.preds[2].is_jal connect f3_bpd_resp.io.enq.bits.preds[2].is_br, bpd.io.resp.f3.preds[2].is_br connect f3_bpd_resp.io.enq.bits.preds[2].taken, bpd.io.resp.f3.preds[2].taken connect f3_bpd_resp.io.enq.bits.preds[3].predicted_pc.bits, bpd.io.resp.f3.preds[3].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[3].predicted_pc.valid, bpd.io.resp.f3.preds[3].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[3].is_jal, bpd.io.resp.f3.preds[3].is_jal connect f3_bpd_resp.io.enq.bits.preds[3].is_br, bpd.io.resp.f3.preds[3].is_br connect f3_bpd_resp.io.enq.bits.preds[3].taken, bpd.io.resp.f3.preds[3].taken connect f3_bpd_resp.io.enq.bits.preds[4].predicted_pc.bits, bpd.io.resp.f3.preds[4].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[4].predicted_pc.valid, bpd.io.resp.f3.preds[4].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[4].is_jal, bpd.io.resp.f3.preds[4].is_jal connect f3_bpd_resp.io.enq.bits.preds[4].is_br, bpd.io.resp.f3.preds[4].is_br connect f3_bpd_resp.io.enq.bits.preds[4].taken, bpd.io.resp.f3.preds[4].taken connect f3_bpd_resp.io.enq.bits.preds[5].predicted_pc.bits, bpd.io.resp.f3.preds[5].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[5].predicted_pc.valid, bpd.io.resp.f3.preds[5].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[5].is_jal, bpd.io.resp.f3.preds[5].is_jal connect f3_bpd_resp.io.enq.bits.preds[5].is_br, bpd.io.resp.f3.preds[5].is_br connect f3_bpd_resp.io.enq.bits.preds[5].taken, bpd.io.resp.f3.preds[5].taken connect f3_bpd_resp.io.enq.bits.preds[6].predicted_pc.bits, bpd.io.resp.f3.preds[6].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[6].predicted_pc.valid, bpd.io.resp.f3.preds[6].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[6].is_jal, bpd.io.resp.f3.preds[6].is_jal connect f3_bpd_resp.io.enq.bits.preds[6].is_br, bpd.io.resp.f3.preds[6].is_br connect f3_bpd_resp.io.enq.bits.preds[6].taken, bpd.io.resp.f3.preds[6].taken connect f3_bpd_resp.io.enq.bits.preds[7].predicted_pc.bits, bpd.io.resp.f3.preds[7].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[7].predicted_pc.valid, bpd.io.resp.f3.preds[7].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[7].is_jal, bpd.io.resp.f3.preds[7].is_jal connect f3_bpd_resp.io.enq.bits.preds[7].is_br, bpd.io.resp.f3.preds[7].is_br connect f3_bpd_resp.io.enq.bits.preds[7].taken, bpd.io.resp.f3.preds[7].taken connect f3_bpd_resp.io.enq.bits.pc, bpd.io.resp.f3.pc node _T_27 = and(f3_bpd_resp.io.enq.ready, f3_bpd_resp.io.enq.valid) when _T_27 : connect bpd.io.f3_fire, UInt<1>(0h1) connect f3.io.deq.ready, f4_ready connect f3_bpd_resp.io.deq.ready, f4_ready node f3_bank_mask_idx = bits(f3.io.deq.bits.pc, 3, 1) node _f3_bank_mask_T = bits(f3.io.deq.bits.pc, 5, 3) node _f3_bank_mask_T_1 = eq(_f3_bank_mask_T, UInt<3>(0h7)) node _f3_bank_mask_T_2 = and(UInt<1>(0h1), _f3_bank_mask_T_1) node f3_bank_mask = mux(_f3_bank_mask_T_2, UInt<2>(0h1), UInt<2>(0h3)) node _f3_aligned_pc_T = not(f3.io.deq.bits.pc) node _f3_aligned_pc_T_1 = or(_f3_aligned_pc_T, UInt<3>(0h7)) node f3_aligned_pc = not(_f3_aligned_pc_T_1) node _f3_is_last_bank_in_block_T = bits(f3_aligned_pc, 5, 3) node _f3_is_last_bank_in_block_T_1 = eq(_f3_is_last_bank_in_block_T, UInt<3>(0h7)) node f3_is_last_bank_in_block = and(UInt<1>(0h1), _f3_is_last_bank_in_block_T_1) wire f3_is_rvc : UInt<1>[8] wire f3_redirects : UInt<1>[8] wire f3_targs : UInt<40>[8] wire f3_cfi_types : UInt<3>[8] wire f3_shadowed_mask : UInt<1>[8] wire f3_fetch_bundle : { pc : UInt<40>, next_pc : UInt<40>, edge_inst : UInt<1>[2], insts : UInt<32>[8], exp_insts : UInt<32>[8], sfbs : UInt<1>[8], sfb_masks : UInt<16>[8], sfb_dests : UInt<5>[8], shadowable_mask : UInt<1>[8], shadowed_mask : UInt<1>[8], cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_type : UInt<3>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ftq_idx : UInt<5>, mask : UInt<8>, br_mask : UInt<8>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[2], xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, bp_debug_if_oh : UInt<1>[8], bp_xcpt_if_oh : UInt<1>[8], end_half : { valid : UInt<1>, bits : UInt<16>}, bpd_meta : UInt[2], fsrc : UInt<2>, tsrc : UInt<2>} wire f3_mask : UInt<1>[8] wire f3_br_mask : UInt<1>[8] wire f3_call_mask : UInt<1>[8] wire f3_ret_mask : UInt<1>[8] wire f3_npc_plus4_mask : UInt<1>[8] wire f3_btb_mispredicts : UInt<1>[8] node f3_fetch_bundle_mask_lo_lo = cat(f3_mask[1], f3_mask[0]) node f3_fetch_bundle_mask_lo_hi = cat(f3_mask[3], f3_mask[2]) node f3_fetch_bundle_mask_lo = cat(f3_fetch_bundle_mask_lo_hi, f3_fetch_bundle_mask_lo_lo) node f3_fetch_bundle_mask_hi_lo = cat(f3_mask[5], f3_mask[4]) node f3_fetch_bundle_mask_hi_hi = cat(f3_mask[7], f3_mask[6]) node f3_fetch_bundle_mask_hi = cat(f3_fetch_bundle_mask_hi_hi, f3_fetch_bundle_mask_hi_lo) node _f3_fetch_bundle_mask_T = cat(f3_fetch_bundle_mask_hi, f3_fetch_bundle_mask_lo) connect f3_fetch_bundle.mask, _f3_fetch_bundle_mask_T node f3_fetch_bundle_br_mask_lo_lo = cat(f3_br_mask[1], f3_br_mask[0]) node f3_fetch_bundle_br_mask_lo_hi = cat(f3_br_mask[3], f3_br_mask[2]) node f3_fetch_bundle_br_mask_lo = cat(f3_fetch_bundle_br_mask_lo_hi, f3_fetch_bundle_br_mask_lo_lo) node f3_fetch_bundle_br_mask_hi_lo = cat(f3_br_mask[5], f3_br_mask[4]) node f3_fetch_bundle_br_mask_hi_hi = cat(f3_br_mask[7], f3_br_mask[6]) node f3_fetch_bundle_br_mask_hi = cat(f3_fetch_bundle_br_mask_hi_hi, f3_fetch_bundle_br_mask_hi_lo) node _f3_fetch_bundle_br_mask_T = cat(f3_fetch_bundle_br_mask_hi, f3_fetch_bundle_br_mask_lo) connect f3_fetch_bundle.br_mask, _f3_fetch_bundle_br_mask_T connect f3_fetch_bundle.pc, f3.io.deq.bits.pc connect f3_fetch_bundle.ftq_idx, UInt<1>(0h0) connect f3_fetch_bundle.xcpt_pf_if, f3.io.deq.bits.xcpt.pf.inst connect f3_fetch_bundle.xcpt_ae_if, f3.io.deq.bits.xcpt.ae.inst connect f3_fetch_bundle.fsrc, f3.io.deq.bits.fsrc connect f3_fetch_bundle.tsrc, f3.io.deq.bits.tsrc connect f3_fetch_bundle.shadowed_mask, f3_shadowed_mask reg f3_prev_half : UInt<16>, clock regreset f3_prev_is_half : UInt<1>, clock, reset, UInt<1>(0h0) node bank_data = bits(f3.io.deq.bits.data, 63, 0) wire bank_mask : UInt<1>[4] wire bank_insts : UInt<32>[4] wire valid : UInt<1> inst bpu of BreakpointUnit_11 connect bpu.clock, clock connect bpu.reset, reset connect bpu.io.status.uie, io.cpu.status.uie connect bpu.io.status.sie, io.cpu.status.sie connect bpu.io.status.hie, io.cpu.status.hie connect bpu.io.status.mie, io.cpu.status.mie connect bpu.io.status.upie, io.cpu.status.upie connect bpu.io.status.spie, io.cpu.status.spie connect bpu.io.status.ube, io.cpu.status.ube connect bpu.io.status.mpie, io.cpu.status.mpie connect bpu.io.status.spp, io.cpu.status.spp connect bpu.io.status.vs, io.cpu.status.vs connect bpu.io.status.mpp, io.cpu.status.mpp connect bpu.io.status.fs, io.cpu.status.fs connect bpu.io.status.xs, io.cpu.status.xs connect bpu.io.status.mprv, io.cpu.status.mprv connect bpu.io.status.sum, io.cpu.status.sum connect bpu.io.status.mxr, io.cpu.status.mxr connect bpu.io.status.tvm, io.cpu.status.tvm connect bpu.io.status.tw, io.cpu.status.tw connect bpu.io.status.tsr, io.cpu.status.tsr connect bpu.io.status.zero1, io.cpu.status.zero1 connect bpu.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu.io.status.uxl, io.cpu.status.uxl connect bpu.io.status.sxl, io.cpu.status.sxl connect bpu.io.status.sbe, io.cpu.status.sbe connect bpu.io.status.mbe, io.cpu.status.mbe connect bpu.io.status.gva, io.cpu.status.gva connect bpu.io.status.mpv, io.cpu.status.mpv connect bpu.io.status.zero2, io.cpu.status.zero2 connect bpu.io.status.sd, io.cpu.status.sd connect bpu.io.status.v, io.cpu.status.v connect bpu.io.status.prv, io.cpu.status.prv connect bpu.io.status.dv, io.cpu.status.dv connect bpu.io.status.dprv, io.cpu.status.dprv connect bpu.io.status.isa, io.cpu.status.isa connect bpu.io.status.wfi, io.cpu.status.wfi connect bpu.io.status.cease, io.cpu.status.cease connect bpu.io.status.debug, io.cpu.status.debug invalidate bpu.io.ea connect bpu.io.mcontext, io.cpu.mcontext connect bpu.io.scontext, io.cpu.scontext wire brsigs : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} node _inst0_T = bits(bank_data, 15, 0) node inst0 = cat(_inst0_T, f3_prev_half) node inst1 = bits(bank_data, 31, 0) inst exp_inst0_rvc_exp of RVCExpander_13 connect exp_inst0_rvc_exp.clock, clock connect exp_inst0_rvc_exp.reset, reset connect exp_inst0_rvc_exp.io.in, inst0 node exp_inst0 = mux(exp_inst0_rvc_exp.io.rvc, exp_inst0_rvc_exp.io.out.bits, inst0) inst exp_inst1_rvc_exp of RVCExpander_14 connect exp_inst1_rvc_exp.clock, clock connect exp_inst1_rvc_exp.reset, reset connect exp_inst1_rvc_exp.io.in, inst1 node exp_inst1 = mux(exp_inst1_rvc_exp.io.rvc, exp_inst1_rvc_exp.io.out.bits, inst1) node _pc0_T = add(f3_aligned_pc, UInt<1>(0h0)) node _pc0_T_1 = tail(_pc0_T, 1) node _pc0_T_2 = sub(_pc0_T_1, UInt<2>(0h2)) node pc0 = tail(_pc0_T_2, 1) node _pc1_T = add(f3_aligned_pc, UInt<1>(0h0)) node pc1 = tail(_pc1_T, 1) inst bpd_decoder0 of BranchDecode_11 connect bpd_decoder0.clock, clock connect bpd_decoder0.reset, reset connect bpd_decoder0.io.inst, exp_inst0 connect bpd_decoder0.io.pc, pc0 inst bpd_decoder1 of BranchDecode_12 connect bpd_decoder1.clock, clock connect bpd_decoder1.reset, reset connect bpd_decoder1.io.inst, exp_inst1 connect bpd_decoder1.io.pc, pc1 when f3_prev_is_half : connect bank_insts[0], inst0 connect f3_fetch_bundle.insts[0], inst0 connect f3_fetch_bundle.exp_insts[0], exp_inst0 connect bpu.io.pc, pc0 connect brsigs.shadowable, bpd_decoder0.io.out.shadowable connect brsigs.sfb_offset, bpd_decoder0.io.out.sfb_offset connect brsigs.cfi_type, bpd_decoder0.io.out.cfi_type connect brsigs.target, bpd_decoder0.io.out.target connect brsigs.is_call, bpd_decoder0.io.out.is_call connect brsigs.is_ret, bpd_decoder0.io.out.is_ret connect f3_fetch_bundle.edge_inst[0], UInt<1>(0h1) else : connect bank_insts[0], inst1 connect f3_fetch_bundle.insts[0], inst1 connect f3_fetch_bundle.exp_insts[0], exp_inst1 connect bpu.io.pc, pc1 connect brsigs.shadowable, bpd_decoder1.io.out.shadowable connect brsigs.sfb_offset, bpd_decoder1.io.out.sfb_offset connect brsigs.cfi_type, bpd_decoder1.io.out.cfi_type connect brsigs.target, bpd_decoder1.io.out.target connect brsigs.is_call, bpd_decoder1.io.out.is_call connect brsigs.is_ret, bpd_decoder1.io.out.is_ret connect f3_fetch_bundle.edge_inst[0], UInt<1>(0h0) connect valid, UInt<1>(0h1) node _f3_is_rvc_0_T = bits(bank_insts[0], 1, 0) node _f3_is_rvc_0_T_1 = neq(_f3_is_rvc_0_T, UInt<2>(0h3)) connect f3_is_rvc[0], _f3_is_rvc_0_T_1 node _bank_mask_0_T = bits(f3.io.deq.bits.mask, 0, 0) node _bank_mask_0_T_1 = and(f3.io.deq.valid, _bank_mask_0_T) node _bank_mask_0_T_2 = and(_bank_mask_0_T_1, valid) node _bank_mask_0_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bank_mask_0_T_4 = and(_bank_mask_0_T_2, _bank_mask_0_T_3) connect bank_mask[0], _bank_mask_0_T_4 node _f3_mask_0_T = bits(f3.io.deq.bits.mask, 0, 0) node _f3_mask_0_T_1 = and(f3.io.deq.valid, _f3_mask_0_T) node _f3_mask_0_T_2 = and(_f3_mask_0_T_1, valid) node _f3_mask_0_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _f3_mask_0_T_4 = and(_f3_mask_0_T_2, _f3_mask_0_T_3) connect f3_mask[0], _f3_mask_0_T_4 node _f3_targs_0_T = eq(brsigs.cfi_type, UInt<3>(0h3)) node _f3_targs_0_T_1 = mux(_f3_targs_0_T, f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.bits, brsigs.target) connect f3_targs[0], _f3_targs_0_T_1 node _f3_btb_mispredicts_0_T = eq(brsigs.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_0_T_1 = and(_f3_btb_mispredicts_0_T, valid) node _f3_btb_mispredicts_0_T_2 = and(_f3_btb_mispredicts_0_T_1, f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.valid) node _f3_btb_mispredicts_0_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.bits, brsigs.target) node _f3_btb_mispredicts_0_T_4 = and(_f3_btb_mispredicts_0_T_2, _f3_btb_mispredicts_0_T_3) connect f3_btb_mispredicts[0], _f3_btb_mispredicts_0_T_4 node _f3_npc_plus4_mask_0_T = eq(f3_is_rvc[0], UInt<1>(0h0)) node _f3_npc_plus4_mask_0_T_1 = eq(f3_prev_is_half, UInt<1>(0h0)) node _f3_npc_plus4_mask_0_T_2 = and(_f3_npc_plus4_mask_0_T, _f3_npc_plus4_mask_0_T_1) connect f3_npc_plus4_mask[0], _f3_npc_plus4_mask_0_T_2 node _offset_from_aligned_pc_T = add(UInt<7>(0h0), brsigs.sfb_offset.bits) node _offset_from_aligned_pc_T_1 = tail(_offset_from_aligned_pc_T, 1) node _offset_from_aligned_pc_T_2 = and(f3_prev_is_half, UInt<1>(0h1)) node _offset_from_aligned_pc_T_3 = mux(_offset_from_aligned_pc_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_4 = sub(_offset_from_aligned_pc_T_1, _offset_from_aligned_pc_T_3) node offset_from_aligned_pc = tail(_offset_from_aligned_pc_T_4, 1) wire lower_mask : UInt<16> wire upper_mask : UInt<16> node _lower_mask_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) connect lower_mask, _lower_mask_T node _upper_mask_T = bits(offset_from_aligned_pc, 5, 1) node _upper_mask_T_1 = dshl(UInt<1>(0h1), _upper_mask_T) node _upper_mask_T_2 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_3 = dshl(_upper_mask_T_1, _upper_mask_T_2) connect upper_mask, _upper_mask_T_3 node _f3_fetch_bundle_sfbs_0_T = and(f3_mask[0], brsigs.sfb_offset.valid) node _f3_fetch_bundle_sfbs_0_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_0_T_2 = leq(offset_from_aligned_pc, _f3_fetch_bundle_sfbs_0_T_1) node _f3_fetch_bundle_sfbs_0_T_3 = and(_f3_fetch_bundle_sfbs_0_T, _f3_fetch_bundle_sfbs_0_T_2) connect f3_fetch_bundle.sfbs[0], _f3_fetch_bundle_sfbs_0_T_3 node _f3_fetch_bundle_sfb_masks_0_T = dshr(lower_mask, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_0_T_1 = dshr(lower_mask, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_0_T_2 = dshr(lower_mask, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_0_T_3 = dshr(lower_mask, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_0_T_4 = dshr(lower_mask, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_0_T_5 = dshr(lower_mask, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_0_T_6 = dshr(lower_mask, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_0_T_7 = dshr(lower_mask, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_0_T_8 = dshr(lower_mask, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_0_T_9 = dshr(lower_mask, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_0_T_10 = dshr(lower_mask, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_0_T_11 = dshr(lower_mask, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_0_T_12 = dshr(lower_mask, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_0_T_13 = dshr(lower_mask, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_0_T_14 = dshr(lower_mask, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_0_T_15 = dshr(lower_mask, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_0_T_16 = or(_f3_fetch_bundle_sfb_masks_0_T, _f3_fetch_bundle_sfb_masks_0_T_1) node _f3_fetch_bundle_sfb_masks_0_T_17 = or(_f3_fetch_bundle_sfb_masks_0_T_16, _f3_fetch_bundle_sfb_masks_0_T_2) node _f3_fetch_bundle_sfb_masks_0_T_18 = or(_f3_fetch_bundle_sfb_masks_0_T_17, _f3_fetch_bundle_sfb_masks_0_T_3) node _f3_fetch_bundle_sfb_masks_0_T_19 = or(_f3_fetch_bundle_sfb_masks_0_T_18, _f3_fetch_bundle_sfb_masks_0_T_4) node _f3_fetch_bundle_sfb_masks_0_T_20 = or(_f3_fetch_bundle_sfb_masks_0_T_19, _f3_fetch_bundle_sfb_masks_0_T_5) node _f3_fetch_bundle_sfb_masks_0_T_21 = or(_f3_fetch_bundle_sfb_masks_0_T_20, _f3_fetch_bundle_sfb_masks_0_T_6) node _f3_fetch_bundle_sfb_masks_0_T_22 = or(_f3_fetch_bundle_sfb_masks_0_T_21, _f3_fetch_bundle_sfb_masks_0_T_7) node _f3_fetch_bundle_sfb_masks_0_T_23 = or(_f3_fetch_bundle_sfb_masks_0_T_22, _f3_fetch_bundle_sfb_masks_0_T_8) node _f3_fetch_bundle_sfb_masks_0_T_24 = or(_f3_fetch_bundle_sfb_masks_0_T_23, _f3_fetch_bundle_sfb_masks_0_T_9) node _f3_fetch_bundle_sfb_masks_0_T_25 = or(_f3_fetch_bundle_sfb_masks_0_T_24, _f3_fetch_bundle_sfb_masks_0_T_10) node _f3_fetch_bundle_sfb_masks_0_T_26 = or(_f3_fetch_bundle_sfb_masks_0_T_25, _f3_fetch_bundle_sfb_masks_0_T_11) node _f3_fetch_bundle_sfb_masks_0_T_27 = or(_f3_fetch_bundle_sfb_masks_0_T_26, _f3_fetch_bundle_sfb_masks_0_T_12) node _f3_fetch_bundle_sfb_masks_0_T_28 = or(_f3_fetch_bundle_sfb_masks_0_T_27, _f3_fetch_bundle_sfb_masks_0_T_13) node _f3_fetch_bundle_sfb_masks_0_T_29 = or(_f3_fetch_bundle_sfb_masks_0_T_28, _f3_fetch_bundle_sfb_masks_0_T_14) node _f3_fetch_bundle_sfb_masks_0_T_30 = or(_f3_fetch_bundle_sfb_masks_0_T_29, _f3_fetch_bundle_sfb_masks_0_T_15) node _f3_fetch_bundle_sfb_masks_0_T_31 = not(_f3_fetch_bundle_sfb_masks_0_T_30) node _f3_fetch_bundle_sfb_masks_0_T_32 = dshl(upper_mask, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_0_T_33 = bits(_f3_fetch_bundle_sfb_masks_0_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_34 = dshl(upper_mask, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_0_T_35 = bits(_f3_fetch_bundle_sfb_masks_0_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_36 = dshl(upper_mask, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_0_T_37 = bits(_f3_fetch_bundle_sfb_masks_0_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_38 = dshl(upper_mask, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_0_T_39 = bits(_f3_fetch_bundle_sfb_masks_0_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_40 = dshl(upper_mask, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_0_T_41 = bits(_f3_fetch_bundle_sfb_masks_0_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_42 = dshl(upper_mask, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_0_T_43 = bits(_f3_fetch_bundle_sfb_masks_0_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_44 = dshl(upper_mask, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_0_T_45 = bits(_f3_fetch_bundle_sfb_masks_0_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_46 = dshl(upper_mask, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_0_T_47 = bits(_f3_fetch_bundle_sfb_masks_0_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_48 = dshl(upper_mask, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_0_T_49 = bits(_f3_fetch_bundle_sfb_masks_0_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_50 = dshl(upper_mask, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_0_T_51 = bits(_f3_fetch_bundle_sfb_masks_0_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_52 = dshl(upper_mask, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_0_T_53 = bits(_f3_fetch_bundle_sfb_masks_0_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_54 = dshl(upper_mask, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_0_T_55 = bits(_f3_fetch_bundle_sfb_masks_0_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_56 = dshl(upper_mask, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_0_T_57 = bits(_f3_fetch_bundle_sfb_masks_0_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_58 = dshl(upper_mask, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_0_T_59 = bits(_f3_fetch_bundle_sfb_masks_0_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_60 = dshl(upper_mask, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_0_T_61 = bits(_f3_fetch_bundle_sfb_masks_0_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_62 = dshl(upper_mask, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_0_T_63 = bits(_f3_fetch_bundle_sfb_masks_0_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_0_T_64 = or(_f3_fetch_bundle_sfb_masks_0_T_33, _f3_fetch_bundle_sfb_masks_0_T_35) node _f3_fetch_bundle_sfb_masks_0_T_65 = or(_f3_fetch_bundle_sfb_masks_0_T_64, _f3_fetch_bundle_sfb_masks_0_T_37) node _f3_fetch_bundle_sfb_masks_0_T_66 = or(_f3_fetch_bundle_sfb_masks_0_T_65, _f3_fetch_bundle_sfb_masks_0_T_39) node _f3_fetch_bundle_sfb_masks_0_T_67 = or(_f3_fetch_bundle_sfb_masks_0_T_66, _f3_fetch_bundle_sfb_masks_0_T_41) node _f3_fetch_bundle_sfb_masks_0_T_68 = or(_f3_fetch_bundle_sfb_masks_0_T_67, _f3_fetch_bundle_sfb_masks_0_T_43) node _f3_fetch_bundle_sfb_masks_0_T_69 = or(_f3_fetch_bundle_sfb_masks_0_T_68, _f3_fetch_bundle_sfb_masks_0_T_45) node _f3_fetch_bundle_sfb_masks_0_T_70 = or(_f3_fetch_bundle_sfb_masks_0_T_69, _f3_fetch_bundle_sfb_masks_0_T_47) node _f3_fetch_bundle_sfb_masks_0_T_71 = or(_f3_fetch_bundle_sfb_masks_0_T_70, _f3_fetch_bundle_sfb_masks_0_T_49) node _f3_fetch_bundle_sfb_masks_0_T_72 = or(_f3_fetch_bundle_sfb_masks_0_T_71, _f3_fetch_bundle_sfb_masks_0_T_51) node _f3_fetch_bundle_sfb_masks_0_T_73 = or(_f3_fetch_bundle_sfb_masks_0_T_72, _f3_fetch_bundle_sfb_masks_0_T_53) node _f3_fetch_bundle_sfb_masks_0_T_74 = or(_f3_fetch_bundle_sfb_masks_0_T_73, _f3_fetch_bundle_sfb_masks_0_T_55) node _f3_fetch_bundle_sfb_masks_0_T_75 = or(_f3_fetch_bundle_sfb_masks_0_T_74, _f3_fetch_bundle_sfb_masks_0_T_57) node _f3_fetch_bundle_sfb_masks_0_T_76 = or(_f3_fetch_bundle_sfb_masks_0_T_75, _f3_fetch_bundle_sfb_masks_0_T_59) node _f3_fetch_bundle_sfb_masks_0_T_77 = or(_f3_fetch_bundle_sfb_masks_0_T_76, _f3_fetch_bundle_sfb_masks_0_T_61) node _f3_fetch_bundle_sfb_masks_0_T_78 = or(_f3_fetch_bundle_sfb_masks_0_T_77, _f3_fetch_bundle_sfb_masks_0_T_63) node _f3_fetch_bundle_sfb_masks_0_T_79 = not(_f3_fetch_bundle_sfb_masks_0_T_78) node _f3_fetch_bundle_sfb_masks_0_T_80 = and(_f3_fetch_bundle_sfb_masks_0_T_31, _f3_fetch_bundle_sfb_masks_0_T_79) connect f3_fetch_bundle.sfb_masks[0], _f3_fetch_bundle_sfb_masks_0_T_80 node _f3_fetch_bundle_shadowable_mask_0_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_0_T_1 = or(_f3_fetch_bundle_shadowable_mask_0_T, bpu.io.debug_if) node _f3_fetch_bundle_shadowable_mask_0_T_2 = or(_f3_fetch_bundle_shadowable_mask_0_T_1, bpu.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_0_T_3 = eq(_f3_fetch_bundle_shadowable_mask_0_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_0_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_0_T_5 = and(_f3_fetch_bundle_shadowable_mask_0_T_3, _f3_fetch_bundle_shadowable_mask_0_T_4) node _f3_fetch_bundle_shadowable_mask_0_T_6 = eq(f3_mask[0], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_0_T_7 = or(brsigs.shadowable, _f3_fetch_bundle_shadowable_mask_0_T_6) node _f3_fetch_bundle_shadowable_mask_0_T_8 = and(_f3_fetch_bundle_shadowable_mask_0_T_5, _f3_fetch_bundle_shadowable_mask_0_T_7) connect f3_fetch_bundle.shadowable_mask[0], _f3_fetch_bundle_shadowable_mask_0_T_8 connect f3_fetch_bundle.sfb_dests[0], offset_from_aligned_pc node _f3_redirects_0_T = eq(brsigs.cfi_type, UInt<3>(0h2)) node _f3_redirects_0_T_1 = eq(brsigs.cfi_type, UInt<3>(0h3)) node _f3_redirects_0_T_2 = or(_f3_redirects_0_T, _f3_redirects_0_T_1) node _f3_redirects_0_T_3 = eq(brsigs.cfi_type, UInt<3>(0h1)) node _f3_redirects_0_T_4 = and(_f3_redirects_0_T_3, f3_bpd_resp.io.deq.bits.preds[0].taken) node _f3_redirects_0_T_5 = and(_f3_redirects_0_T_4, UInt<1>(0h1)) node _f3_redirects_0_T_6 = or(_f3_redirects_0_T_2, _f3_redirects_0_T_5) node _f3_redirects_0_T_7 = and(f3_mask[0], _f3_redirects_0_T_6) connect f3_redirects[0], _f3_redirects_0_T_7 node _f3_br_mask_0_T = eq(brsigs.cfi_type, UInt<3>(0h1)) node _f3_br_mask_0_T_1 = and(f3_mask[0], _f3_br_mask_0_T) connect f3_br_mask[0], _f3_br_mask_0_T_1 connect f3_cfi_types[0], brsigs.cfi_type connect f3_call_mask[0], brsigs.is_call connect f3_ret_mask[0], brsigs.is_ret connect f3_fetch_bundle.bp_debug_if_oh[0], bpu.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[0], bpu.io.xcpt_if node _T_28 = or(UInt<1>(0h0), f3_redirects[0]) wire valid_1 : UInt<1> inst bpu_1 of BreakpointUnit_12 connect bpu_1.clock, clock connect bpu_1.reset, reset connect bpu_1.io.status.uie, io.cpu.status.uie connect bpu_1.io.status.sie, io.cpu.status.sie connect bpu_1.io.status.hie, io.cpu.status.hie connect bpu_1.io.status.mie, io.cpu.status.mie connect bpu_1.io.status.upie, io.cpu.status.upie connect bpu_1.io.status.spie, io.cpu.status.spie connect bpu_1.io.status.ube, io.cpu.status.ube connect bpu_1.io.status.mpie, io.cpu.status.mpie connect bpu_1.io.status.spp, io.cpu.status.spp connect bpu_1.io.status.vs, io.cpu.status.vs connect bpu_1.io.status.mpp, io.cpu.status.mpp connect bpu_1.io.status.fs, io.cpu.status.fs connect bpu_1.io.status.xs, io.cpu.status.xs connect bpu_1.io.status.mprv, io.cpu.status.mprv connect bpu_1.io.status.sum, io.cpu.status.sum connect bpu_1.io.status.mxr, io.cpu.status.mxr connect bpu_1.io.status.tvm, io.cpu.status.tvm connect bpu_1.io.status.tw, io.cpu.status.tw connect bpu_1.io.status.tsr, io.cpu.status.tsr connect bpu_1.io.status.zero1, io.cpu.status.zero1 connect bpu_1.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_1.io.status.uxl, io.cpu.status.uxl connect bpu_1.io.status.sxl, io.cpu.status.sxl connect bpu_1.io.status.sbe, io.cpu.status.sbe connect bpu_1.io.status.mbe, io.cpu.status.mbe connect bpu_1.io.status.gva, io.cpu.status.gva connect bpu_1.io.status.mpv, io.cpu.status.mpv connect bpu_1.io.status.zero2, io.cpu.status.zero2 connect bpu_1.io.status.sd, io.cpu.status.sd connect bpu_1.io.status.v, io.cpu.status.v connect bpu_1.io.status.prv, io.cpu.status.prv connect bpu_1.io.status.dv, io.cpu.status.dv connect bpu_1.io.status.dprv, io.cpu.status.dprv connect bpu_1.io.status.isa, io.cpu.status.isa connect bpu_1.io.status.wfi, io.cpu.status.wfi connect bpu_1.io.status.cease, io.cpu.status.cease connect bpu_1.io.status.debug, io.cpu.status.debug invalidate bpu_1.io.ea connect bpu_1.io.mcontext, io.cpu.mcontext connect bpu_1.io.scontext, io.cpu.scontext wire brsigs_1 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst : UInt<32> inst exp_inst_rvc_exp of RVCExpander_15 connect exp_inst_rvc_exp.clock, clock connect exp_inst_rvc_exp.reset, reset connect exp_inst_rvc_exp.io.in, inst node exp_inst = mux(exp_inst_rvc_exp.io.rvc, exp_inst_rvc_exp.io.out.bits, inst) node _pc_T = add(f3_aligned_pc, UInt<2>(0h2)) node pc = tail(_pc_T, 1) inst bpd_decoder of BranchDecode_13 connect bpd_decoder.clock, clock connect bpd_decoder.reset, reset connect bpd_decoder.io.inst, exp_inst connect bpd_decoder.io.pc, pc connect bank_insts[1], inst connect f3_fetch_bundle.insts[1], inst connect f3_fetch_bundle.exp_insts[1], exp_inst connect bpu_1.io.pc, pc connect brsigs_1.shadowable, bpd_decoder.io.out.shadowable connect brsigs_1.sfb_offset, bpd_decoder.io.out.sfb_offset connect brsigs_1.cfi_type, bpd_decoder.io.out.cfi_type connect brsigs_1.target, bpd_decoder.io.out.target connect brsigs_1.is_call, bpd_decoder.io.out.is_call connect brsigs_1.is_ret, bpd_decoder.io.out.is_ret node _inst_T = bits(bank_data, 47, 16) connect inst, _inst_T node _valid_T = bits(bank_insts[0], 1, 0) node _valid_T_1 = neq(_valid_T, UInt<2>(0h3)) node _valid_T_2 = eq(_valid_T_1, UInt<1>(0h0)) node _valid_T_3 = and(bank_mask[0], _valid_T_2) node _valid_T_4 = eq(_valid_T_3, UInt<1>(0h0)) node _valid_T_5 = or(f3_prev_is_half, _valid_T_4) connect valid_1, _valid_T_5 node _f3_is_rvc_1_T = bits(bank_insts[1], 1, 0) node _f3_is_rvc_1_T_1 = neq(_f3_is_rvc_1_T, UInt<2>(0h3)) connect f3_is_rvc[1], _f3_is_rvc_1_T_1 node _bank_mask_1_T = bits(f3.io.deq.bits.mask, 1, 1) node _bank_mask_1_T_1 = and(f3.io.deq.valid, _bank_mask_1_T) node _bank_mask_1_T_2 = and(_bank_mask_1_T_1, valid_1) node _bank_mask_1_T_3 = eq(_T_28, UInt<1>(0h0)) node _bank_mask_1_T_4 = and(_bank_mask_1_T_2, _bank_mask_1_T_3) connect bank_mask[1], _bank_mask_1_T_4 node _f3_mask_1_T = bits(f3.io.deq.bits.mask, 1, 1) node _f3_mask_1_T_1 = and(f3.io.deq.valid, _f3_mask_1_T) node _f3_mask_1_T_2 = and(_f3_mask_1_T_1, valid_1) node _f3_mask_1_T_3 = eq(_T_28, UInt<1>(0h0)) node _f3_mask_1_T_4 = and(_f3_mask_1_T_2, _f3_mask_1_T_3) connect f3_mask[1], _f3_mask_1_T_4 node _f3_targs_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h3)) node _f3_targs_1_T_1 = mux(_f3_targs_1_T, f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.bits, brsigs_1.target) connect f3_targs[1], _f3_targs_1_T_1 node _f3_btb_mispredicts_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_1_T_1 = and(_f3_btb_mispredicts_1_T, valid_1) node _f3_btb_mispredicts_1_T_2 = and(_f3_btb_mispredicts_1_T_1, f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.valid) node _f3_btb_mispredicts_1_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.bits, brsigs_1.target) node _f3_btb_mispredicts_1_T_4 = and(_f3_btb_mispredicts_1_T_2, _f3_btb_mispredicts_1_T_3) connect f3_btb_mispredicts[1], _f3_btb_mispredicts_1_T_4 node _f3_npc_plus4_mask_1_T = eq(f3_is_rvc[1], UInt<1>(0h0)) connect f3_npc_plus4_mask[1], _f3_npc_plus4_mask_1_T node _offset_from_aligned_pc_T_5 = add(UInt<7>(0h2), brsigs_1.sfb_offset.bits) node _offset_from_aligned_pc_T_6 = tail(_offset_from_aligned_pc_T_5, 1) node _offset_from_aligned_pc_T_7 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_8 = mux(_offset_from_aligned_pc_T_7, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_9 = sub(_offset_from_aligned_pc_T_6, _offset_from_aligned_pc_T_8) node offset_from_aligned_pc_1 = tail(_offset_from_aligned_pc_T_9, 1) wire lower_mask_1 : UInt<16> wire upper_mask_1 : UInt<16> node _lower_mask_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1)) connect lower_mask_1, _lower_mask_T_1 node _upper_mask_T_4 = bits(offset_from_aligned_pc_1, 5, 1) node _upper_mask_T_5 = dshl(UInt<1>(0h1), _upper_mask_T_4) node _upper_mask_T_6 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_7 = dshl(_upper_mask_T_5, _upper_mask_T_6) connect upper_mask_1, _upper_mask_T_7 node _f3_fetch_bundle_sfbs_1_T = and(f3_mask[1], brsigs_1.sfb_offset.valid) node _f3_fetch_bundle_sfbs_1_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_1_T_2 = leq(offset_from_aligned_pc_1, _f3_fetch_bundle_sfbs_1_T_1) node _f3_fetch_bundle_sfbs_1_T_3 = and(_f3_fetch_bundle_sfbs_1_T, _f3_fetch_bundle_sfbs_1_T_2) connect f3_fetch_bundle.sfbs[1], _f3_fetch_bundle_sfbs_1_T_3 node _f3_fetch_bundle_sfb_masks_1_T = dshr(lower_mask_1, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_1_T_1 = dshr(lower_mask_1, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_1_T_2 = dshr(lower_mask_1, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_1_T_3 = dshr(lower_mask_1, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_1_T_4 = dshr(lower_mask_1, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_1_T_5 = dshr(lower_mask_1, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_1_T_6 = dshr(lower_mask_1, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_1_T_7 = dshr(lower_mask_1, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_1_T_8 = dshr(lower_mask_1, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_1_T_9 = dshr(lower_mask_1, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_1_T_10 = dshr(lower_mask_1, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_1_T_11 = dshr(lower_mask_1, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_1_T_12 = dshr(lower_mask_1, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_1_T_13 = dshr(lower_mask_1, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_1_T_14 = dshr(lower_mask_1, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_1_T_15 = dshr(lower_mask_1, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_1_T_16 = or(_f3_fetch_bundle_sfb_masks_1_T, _f3_fetch_bundle_sfb_masks_1_T_1) node _f3_fetch_bundle_sfb_masks_1_T_17 = or(_f3_fetch_bundle_sfb_masks_1_T_16, _f3_fetch_bundle_sfb_masks_1_T_2) node _f3_fetch_bundle_sfb_masks_1_T_18 = or(_f3_fetch_bundle_sfb_masks_1_T_17, _f3_fetch_bundle_sfb_masks_1_T_3) node _f3_fetch_bundle_sfb_masks_1_T_19 = or(_f3_fetch_bundle_sfb_masks_1_T_18, _f3_fetch_bundle_sfb_masks_1_T_4) node _f3_fetch_bundle_sfb_masks_1_T_20 = or(_f3_fetch_bundle_sfb_masks_1_T_19, _f3_fetch_bundle_sfb_masks_1_T_5) node _f3_fetch_bundle_sfb_masks_1_T_21 = or(_f3_fetch_bundle_sfb_masks_1_T_20, _f3_fetch_bundle_sfb_masks_1_T_6) node _f3_fetch_bundle_sfb_masks_1_T_22 = or(_f3_fetch_bundle_sfb_masks_1_T_21, _f3_fetch_bundle_sfb_masks_1_T_7) node _f3_fetch_bundle_sfb_masks_1_T_23 = or(_f3_fetch_bundle_sfb_masks_1_T_22, _f3_fetch_bundle_sfb_masks_1_T_8) node _f3_fetch_bundle_sfb_masks_1_T_24 = or(_f3_fetch_bundle_sfb_masks_1_T_23, _f3_fetch_bundle_sfb_masks_1_T_9) node _f3_fetch_bundle_sfb_masks_1_T_25 = or(_f3_fetch_bundle_sfb_masks_1_T_24, _f3_fetch_bundle_sfb_masks_1_T_10) node _f3_fetch_bundle_sfb_masks_1_T_26 = or(_f3_fetch_bundle_sfb_masks_1_T_25, _f3_fetch_bundle_sfb_masks_1_T_11) node _f3_fetch_bundle_sfb_masks_1_T_27 = or(_f3_fetch_bundle_sfb_masks_1_T_26, _f3_fetch_bundle_sfb_masks_1_T_12) node _f3_fetch_bundle_sfb_masks_1_T_28 = or(_f3_fetch_bundle_sfb_masks_1_T_27, _f3_fetch_bundle_sfb_masks_1_T_13) node _f3_fetch_bundle_sfb_masks_1_T_29 = or(_f3_fetch_bundle_sfb_masks_1_T_28, _f3_fetch_bundle_sfb_masks_1_T_14) node _f3_fetch_bundle_sfb_masks_1_T_30 = or(_f3_fetch_bundle_sfb_masks_1_T_29, _f3_fetch_bundle_sfb_masks_1_T_15) node _f3_fetch_bundle_sfb_masks_1_T_31 = not(_f3_fetch_bundle_sfb_masks_1_T_30) node _f3_fetch_bundle_sfb_masks_1_T_32 = dshl(upper_mask_1, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_1_T_33 = bits(_f3_fetch_bundle_sfb_masks_1_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_34 = dshl(upper_mask_1, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_1_T_35 = bits(_f3_fetch_bundle_sfb_masks_1_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_36 = dshl(upper_mask_1, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_1_T_37 = bits(_f3_fetch_bundle_sfb_masks_1_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_38 = dshl(upper_mask_1, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_1_T_39 = bits(_f3_fetch_bundle_sfb_masks_1_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_40 = dshl(upper_mask_1, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_1_T_41 = bits(_f3_fetch_bundle_sfb_masks_1_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_42 = dshl(upper_mask_1, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_1_T_43 = bits(_f3_fetch_bundle_sfb_masks_1_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_44 = dshl(upper_mask_1, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_1_T_45 = bits(_f3_fetch_bundle_sfb_masks_1_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_46 = dshl(upper_mask_1, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_1_T_47 = bits(_f3_fetch_bundle_sfb_masks_1_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_48 = dshl(upper_mask_1, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_1_T_49 = bits(_f3_fetch_bundle_sfb_masks_1_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_50 = dshl(upper_mask_1, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_1_T_51 = bits(_f3_fetch_bundle_sfb_masks_1_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_52 = dshl(upper_mask_1, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_1_T_53 = bits(_f3_fetch_bundle_sfb_masks_1_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_54 = dshl(upper_mask_1, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_1_T_55 = bits(_f3_fetch_bundle_sfb_masks_1_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_56 = dshl(upper_mask_1, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_1_T_57 = bits(_f3_fetch_bundle_sfb_masks_1_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_58 = dshl(upper_mask_1, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_1_T_59 = bits(_f3_fetch_bundle_sfb_masks_1_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_60 = dshl(upper_mask_1, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_1_T_61 = bits(_f3_fetch_bundle_sfb_masks_1_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_62 = dshl(upper_mask_1, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_1_T_63 = bits(_f3_fetch_bundle_sfb_masks_1_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_1_T_64 = or(_f3_fetch_bundle_sfb_masks_1_T_33, _f3_fetch_bundle_sfb_masks_1_T_35) node _f3_fetch_bundle_sfb_masks_1_T_65 = or(_f3_fetch_bundle_sfb_masks_1_T_64, _f3_fetch_bundle_sfb_masks_1_T_37) node _f3_fetch_bundle_sfb_masks_1_T_66 = or(_f3_fetch_bundle_sfb_masks_1_T_65, _f3_fetch_bundle_sfb_masks_1_T_39) node _f3_fetch_bundle_sfb_masks_1_T_67 = or(_f3_fetch_bundle_sfb_masks_1_T_66, _f3_fetch_bundle_sfb_masks_1_T_41) node _f3_fetch_bundle_sfb_masks_1_T_68 = or(_f3_fetch_bundle_sfb_masks_1_T_67, _f3_fetch_bundle_sfb_masks_1_T_43) node _f3_fetch_bundle_sfb_masks_1_T_69 = or(_f3_fetch_bundle_sfb_masks_1_T_68, _f3_fetch_bundle_sfb_masks_1_T_45) node _f3_fetch_bundle_sfb_masks_1_T_70 = or(_f3_fetch_bundle_sfb_masks_1_T_69, _f3_fetch_bundle_sfb_masks_1_T_47) node _f3_fetch_bundle_sfb_masks_1_T_71 = or(_f3_fetch_bundle_sfb_masks_1_T_70, _f3_fetch_bundle_sfb_masks_1_T_49) node _f3_fetch_bundle_sfb_masks_1_T_72 = or(_f3_fetch_bundle_sfb_masks_1_T_71, _f3_fetch_bundle_sfb_masks_1_T_51) node _f3_fetch_bundle_sfb_masks_1_T_73 = or(_f3_fetch_bundle_sfb_masks_1_T_72, _f3_fetch_bundle_sfb_masks_1_T_53) node _f3_fetch_bundle_sfb_masks_1_T_74 = or(_f3_fetch_bundle_sfb_masks_1_T_73, _f3_fetch_bundle_sfb_masks_1_T_55) node _f3_fetch_bundle_sfb_masks_1_T_75 = or(_f3_fetch_bundle_sfb_masks_1_T_74, _f3_fetch_bundle_sfb_masks_1_T_57) node _f3_fetch_bundle_sfb_masks_1_T_76 = or(_f3_fetch_bundle_sfb_masks_1_T_75, _f3_fetch_bundle_sfb_masks_1_T_59) node _f3_fetch_bundle_sfb_masks_1_T_77 = or(_f3_fetch_bundle_sfb_masks_1_T_76, _f3_fetch_bundle_sfb_masks_1_T_61) node _f3_fetch_bundle_sfb_masks_1_T_78 = or(_f3_fetch_bundle_sfb_masks_1_T_77, _f3_fetch_bundle_sfb_masks_1_T_63) node _f3_fetch_bundle_sfb_masks_1_T_79 = not(_f3_fetch_bundle_sfb_masks_1_T_78) node _f3_fetch_bundle_sfb_masks_1_T_80 = and(_f3_fetch_bundle_sfb_masks_1_T_31, _f3_fetch_bundle_sfb_masks_1_T_79) connect f3_fetch_bundle.sfb_masks[1], _f3_fetch_bundle_sfb_masks_1_T_80 node _f3_fetch_bundle_shadowable_mask_1_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_1_T_1 = or(_f3_fetch_bundle_shadowable_mask_1_T, bpu_1.io.debug_if) node _f3_fetch_bundle_shadowable_mask_1_T_2 = or(_f3_fetch_bundle_shadowable_mask_1_T_1, bpu_1.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_1_T_3 = eq(_f3_fetch_bundle_shadowable_mask_1_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_1_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_1_T_5 = and(_f3_fetch_bundle_shadowable_mask_1_T_3, _f3_fetch_bundle_shadowable_mask_1_T_4) node _f3_fetch_bundle_shadowable_mask_1_T_6 = eq(f3_mask[1], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_1_T_7 = or(brsigs_1.shadowable, _f3_fetch_bundle_shadowable_mask_1_T_6) node _f3_fetch_bundle_shadowable_mask_1_T_8 = and(_f3_fetch_bundle_shadowable_mask_1_T_5, _f3_fetch_bundle_shadowable_mask_1_T_7) connect f3_fetch_bundle.shadowable_mask[1], _f3_fetch_bundle_shadowable_mask_1_T_8 connect f3_fetch_bundle.sfb_dests[1], offset_from_aligned_pc_1 node _f3_redirects_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h2)) node _f3_redirects_1_T_1 = eq(brsigs_1.cfi_type, UInt<3>(0h3)) node _f3_redirects_1_T_2 = or(_f3_redirects_1_T, _f3_redirects_1_T_1) node _f3_redirects_1_T_3 = eq(brsigs_1.cfi_type, UInt<3>(0h1)) node _f3_redirects_1_T_4 = and(_f3_redirects_1_T_3, f3_bpd_resp.io.deq.bits.preds[1].taken) node _f3_redirects_1_T_5 = and(_f3_redirects_1_T_4, UInt<1>(0h1)) node _f3_redirects_1_T_6 = or(_f3_redirects_1_T_2, _f3_redirects_1_T_5) node _f3_redirects_1_T_7 = and(f3_mask[1], _f3_redirects_1_T_6) connect f3_redirects[1], _f3_redirects_1_T_7 node _f3_br_mask_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h1)) node _f3_br_mask_1_T_1 = and(f3_mask[1], _f3_br_mask_1_T) connect f3_br_mask[1], _f3_br_mask_1_T_1 connect f3_cfi_types[1], brsigs_1.cfi_type connect f3_call_mask[1], brsigs_1.is_call connect f3_ret_mask[1], brsigs_1.is_ret connect f3_fetch_bundle.bp_debug_if_oh[1], bpu_1.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[1], bpu_1.io.xcpt_if node _T_29 = or(_T_28, f3_redirects[1]) wire valid_2 : UInt<1> inst bpu_2 of BreakpointUnit_13 connect bpu_2.clock, clock connect bpu_2.reset, reset connect bpu_2.io.status.uie, io.cpu.status.uie connect bpu_2.io.status.sie, io.cpu.status.sie connect bpu_2.io.status.hie, io.cpu.status.hie connect bpu_2.io.status.mie, io.cpu.status.mie connect bpu_2.io.status.upie, io.cpu.status.upie connect bpu_2.io.status.spie, io.cpu.status.spie connect bpu_2.io.status.ube, io.cpu.status.ube connect bpu_2.io.status.mpie, io.cpu.status.mpie connect bpu_2.io.status.spp, io.cpu.status.spp connect bpu_2.io.status.vs, io.cpu.status.vs connect bpu_2.io.status.mpp, io.cpu.status.mpp connect bpu_2.io.status.fs, io.cpu.status.fs connect bpu_2.io.status.xs, io.cpu.status.xs connect bpu_2.io.status.mprv, io.cpu.status.mprv connect bpu_2.io.status.sum, io.cpu.status.sum connect bpu_2.io.status.mxr, io.cpu.status.mxr connect bpu_2.io.status.tvm, io.cpu.status.tvm connect bpu_2.io.status.tw, io.cpu.status.tw connect bpu_2.io.status.tsr, io.cpu.status.tsr connect bpu_2.io.status.zero1, io.cpu.status.zero1 connect bpu_2.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_2.io.status.uxl, io.cpu.status.uxl connect bpu_2.io.status.sxl, io.cpu.status.sxl connect bpu_2.io.status.sbe, io.cpu.status.sbe connect bpu_2.io.status.mbe, io.cpu.status.mbe connect bpu_2.io.status.gva, io.cpu.status.gva connect bpu_2.io.status.mpv, io.cpu.status.mpv connect bpu_2.io.status.zero2, io.cpu.status.zero2 connect bpu_2.io.status.sd, io.cpu.status.sd connect bpu_2.io.status.v, io.cpu.status.v connect bpu_2.io.status.prv, io.cpu.status.prv connect bpu_2.io.status.dv, io.cpu.status.dv connect bpu_2.io.status.dprv, io.cpu.status.dprv connect bpu_2.io.status.isa, io.cpu.status.isa connect bpu_2.io.status.wfi, io.cpu.status.wfi connect bpu_2.io.status.cease, io.cpu.status.cease connect bpu_2.io.status.debug, io.cpu.status.debug invalidate bpu_2.io.ea connect bpu_2.io.mcontext, io.cpu.mcontext connect bpu_2.io.scontext, io.cpu.scontext wire brsigs_2 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_1 : UInt<32> inst exp_inst_rvc_exp_1 of RVCExpander_16 connect exp_inst_rvc_exp_1.clock, clock connect exp_inst_rvc_exp_1.reset, reset connect exp_inst_rvc_exp_1.io.in, inst_1 node exp_inst_1 = mux(exp_inst_rvc_exp_1.io.rvc, exp_inst_rvc_exp_1.io.out.bits, inst_1) node _pc_T_1 = add(f3_aligned_pc, UInt<3>(0h4)) node pc_1 = tail(_pc_T_1, 1) inst bpd_decoder_1 of BranchDecode_14 connect bpd_decoder_1.clock, clock connect bpd_decoder_1.reset, reset connect bpd_decoder_1.io.inst, exp_inst_1 connect bpd_decoder_1.io.pc, pc_1 connect bank_insts[2], inst_1 connect f3_fetch_bundle.insts[2], inst_1 connect f3_fetch_bundle.exp_insts[2], exp_inst_1 connect bpu_2.io.pc, pc_1 connect brsigs_2.shadowable, bpd_decoder_1.io.out.shadowable connect brsigs_2.sfb_offset, bpd_decoder_1.io.out.sfb_offset connect brsigs_2.cfi_type, bpd_decoder_1.io.out.cfi_type connect brsigs_2.target, bpd_decoder_1.io.out.target connect brsigs_2.is_call, bpd_decoder_1.io.out.is_call connect brsigs_2.is_ret, bpd_decoder_1.io.out.is_ret node _inst_T_1 = bits(bank_data, 63, 32) connect inst_1, _inst_T_1 node _valid_T_6 = bits(bank_insts[1], 1, 0) node _valid_T_7 = neq(_valid_T_6, UInt<2>(0h3)) node _valid_T_8 = eq(_valid_T_7, UInt<1>(0h0)) node _valid_T_9 = and(bank_mask[1], _valid_T_8) node _valid_T_10 = eq(_valid_T_9, UInt<1>(0h0)) connect valid_2, _valid_T_10 node _f3_is_rvc_2_T = bits(bank_insts[2], 1, 0) node _f3_is_rvc_2_T_1 = neq(_f3_is_rvc_2_T, UInt<2>(0h3)) connect f3_is_rvc[2], _f3_is_rvc_2_T_1 node _bank_mask_2_T = bits(f3.io.deq.bits.mask, 2, 2) node _bank_mask_2_T_1 = and(f3.io.deq.valid, _bank_mask_2_T) node _bank_mask_2_T_2 = and(_bank_mask_2_T_1, valid_2) node _bank_mask_2_T_3 = eq(_T_29, UInt<1>(0h0)) node _bank_mask_2_T_4 = and(_bank_mask_2_T_2, _bank_mask_2_T_3) connect bank_mask[2], _bank_mask_2_T_4 node _f3_mask_2_T = bits(f3.io.deq.bits.mask, 2, 2) node _f3_mask_2_T_1 = and(f3.io.deq.valid, _f3_mask_2_T) node _f3_mask_2_T_2 = and(_f3_mask_2_T_1, valid_2) node _f3_mask_2_T_3 = eq(_T_29, UInt<1>(0h0)) node _f3_mask_2_T_4 = and(_f3_mask_2_T_2, _f3_mask_2_T_3) connect f3_mask[2], _f3_mask_2_T_4 node _f3_targs_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h3)) node _f3_targs_2_T_1 = mux(_f3_targs_2_T, f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.bits, brsigs_2.target) connect f3_targs[2], _f3_targs_2_T_1 node _f3_btb_mispredicts_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_2_T_1 = and(_f3_btb_mispredicts_2_T, valid_2) node _f3_btb_mispredicts_2_T_2 = and(_f3_btb_mispredicts_2_T_1, f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.valid) node _f3_btb_mispredicts_2_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.bits, brsigs_2.target) node _f3_btb_mispredicts_2_T_4 = and(_f3_btb_mispredicts_2_T_2, _f3_btb_mispredicts_2_T_3) connect f3_btb_mispredicts[2], _f3_btb_mispredicts_2_T_4 node _f3_npc_plus4_mask_2_T = eq(f3_is_rvc[2], UInt<1>(0h0)) connect f3_npc_plus4_mask[2], _f3_npc_plus4_mask_2_T node _offset_from_aligned_pc_T_10 = add(UInt<7>(0h4), brsigs_2.sfb_offset.bits) node _offset_from_aligned_pc_T_11 = tail(_offset_from_aligned_pc_T_10, 1) node _offset_from_aligned_pc_T_12 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_13 = mux(_offset_from_aligned_pc_T_12, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_14 = sub(_offset_from_aligned_pc_T_11, _offset_from_aligned_pc_T_13) node offset_from_aligned_pc_2 = tail(_offset_from_aligned_pc_T_14, 1) wire lower_mask_2 : UInt<16> wire upper_mask_2 : UInt<16> node _lower_mask_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) connect lower_mask_2, _lower_mask_T_2 node _upper_mask_T_8 = bits(offset_from_aligned_pc_2, 5, 1) node _upper_mask_T_9 = dshl(UInt<1>(0h1), _upper_mask_T_8) node _upper_mask_T_10 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_11 = dshl(_upper_mask_T_9, _upper_mask_T_10) connect upper_mask_2, _upper_mask_T_11 node _f3_fetch_bundle_sfbs_2_T = and(f3_mask[2], brsigs_2.sfb_offset.valid) node _f3_fetch_bundle_sfbs_2_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_2_T_2 = leq(offset_from_aligned_pc_2, _f3_fetch_bundle_sfbs_2_T_1) node _f3_fetch_bundle_sfbs_2_T_3 = and(_f3_fetch_bundle_sfbs_2_T, _f3_fetch_bundle_sfbs_2_T_2) connect f3_fetch_bundle.sfbs[2], _f3_fetch_bundle_sfbs_2_T_3 node _f3_fetch_bundle_sfb_masks_2_T = dshr(lower_mask_2, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_2_T_1 = dshr(lower_mask_2, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_2_T_2 = dshr(lower_mask_2, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_2_T_3 = dshr(lower_mask_2, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_2_T_4 = dshr(lower_mask_2, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_2_T_5 = dshr(lower_mask_2, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_2_T_6 = dshr(lower_mask_2, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_2_T_7 = dshr(lower_mask_2, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_2_T_8 = dshr(lower_mask_2, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_2_T_9 = dshr(lower_mask_2, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_2_T_10 = dshr(lower_mask_2, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_2_T_11 = dshr(lower_mask_2, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_2_T_12 = dshr(lower_mask_2, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_2_T_13 = dshr(lower_mask_2, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_2_T_14 = dshr(lower_mask_2, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_2_T_15 = dshr(lower_mask_2, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_2_T_16 = or(_f3_fetch_bundle_sfb_masks_2_T, _f3_fetch_bundle_sfb_masks_2_T_1) node _f3_fetch_bundle_sfb_masks_2_T_17 = or(_f3_fetch_bundle_sfb_masks_2_T_16, _f3_fetch_bundle_sfb_masks_2_T_2) node _f3_fetch_bundle_sfb_masks_2_T_18 = or(_f3_fetch_bundle_sfb_masks_2_T_17, _f3_fetch_bundle_sfb_masks_2_T_3) node _f3_fetch_bundle_sfb_masks_2_T_19 = or(_f3_fetch_bundle_sfb_masks_2_T_18, _f3_fetch_bundle_sfb_masks_2_T_4) node _f3_fetch_bundle_sfb_masks_2_T_20 = or(_f3_fetch_bundle_sfb_masks_2_T_19, _f3_fetch_bundle_sfb_masks_2_T_5) node _f3_fetch_bundle_sfb_masks_2_T_21 = or(_f3_fetch_bundle_sfb_masks_2_T_20, _f3_fetch_bundle_sfb_masks_2_T_6) node _f3_fetch_bundle_sfb_masks_2_T_22 = or(_f3_fetch_bundle_sfb_masks_2_T_21, _f3_fetch_bundle_sfb_masks_2_T_7) node _f3_fetch_bundle_sfb_masks_2_T_23 = or(_f3_fetch_bundle_sfb_masks_2_T_22, _f3_fetch_bundle_sfb_masks_2_T_8) node _f3_fetch_bundle_sfb_masks_2_T_24 = or(_f3_fetch_bundle_sfb_masks_2_T_23, _f3_fetch_bundle_sfb_masks_2_T_9) node _f3_fetch_bundle_sfb_masks_2_T_25 = or(_f3_fetch_bundle_sfb_masks_2_T_24, _f3_fetch_bundle_sfb_masks_2_T_10) node _f3_fetch_bundle_sfb_masks_2_T_26 = or(_f3_fetch_bundle_sfb_masks_2_T_25, _f3_fetch_bundle_sfb_masks_2_T_11) node _f3_fetch_bundle_sfb_masks_2_T_27 = or(_f3_fetch_bundle_sfb_masks_2_T_26, _f3_fetch_bundle_sfb_masks_2_T_12) node _f3_fetch_bundle_sfb_masks_2_T_28 = or(_f3_fetch_bundle_sfb_masks_2_T_27, _f3_fetch_bundle_sfb_masks_2_T_13) node _f3_fetch_bundle_sfb_masks_2_T_29 = or(_f3_fetch_bundle_sfb_masks_2_T_28, _f3_fetch_bundle_sfb_masks_2_T_14) node _f3_fetch_bundle_sfb_masks_2_T_30 = or(_f3_fetch_bundle_sfb_masks_2_T_29, _f3_fetch_bundle_sfb_masks_2_T_15) node _f3_fetch_bundle_sfb_masks_2_T_31 = not(_f3_fetch_bundle_sfb_masks_2_T_30) node _f3_fetch_bundle_sfb_masks_2_T_32 = dshl(upper_mask_2, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_2_T_33 = bits(_f3_fetch_bundle_sfb_masks_2_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_34 = dshl(upper_mask_2, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_2_T_35 = bits(_f3_fetch_bundle_sfb_masks_2_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_36 = dshl(upper_mask_2, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_2_T_37 = bits(_f3_fetch_bundle_sfb_masks_2_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_38 = dshl(upper_mask_2, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_2_T_39 = bits(_f3_fetch_bundle_sfb_masks_2_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_40 = dshl(upper_mask_2, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_2_T_41 = bits(_f3_fetch_bundle_sfb_masks_2_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_42 = dshl(upper_mask_2, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_2_T_43 = bits(_f3_fetch_bundle_sfb_masks_2_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_44 = dshl(upper_mask_2, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_2_T_45 = bits(_f3_fetch_bundle_sfb_masks_2_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_46 = dshl(upper_mask_2, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_2_T_47 = bits(_f3_fetch_bundle_sfb_masks_2_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_48 = dshl(upper_mask_2, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_2_T_49 = bits(_f3_fetch_bundle_sfb_masks_2_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_50 = dshl(upper_mask_2, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_2_T_51 = bits(_f3_fetch_bundle_sfb_masks_2_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_52 = dshl(upper_mask_2, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_2_T_53 = bits(_f3_fetch_bundle_sfb_masks_2_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_54 = dshl(upper_mask_2, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_2_T_55 = bits(_f3_fetch_bundle_sfb_masks_2_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_56 = dshl(upper_mask_2, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_2_T_57 = bits(_f3_fetch_bundle_sfb_masks_2_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_58 = dshl(upper_mask_2, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_2_T_59 = bits(_f3_fetch_bundle_sfb_masks_2_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_60 = dshl(upper_mask_2, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_2_T_61 = bits(_f3_fetch_bundle_sfb_masks_2_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_62 = dshl(upper_mask_2, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_2_T_63 = bits(_f3_fetch_bundle_sfb_masks_2_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_2_T_64 = or(_f3_fetch_bundle_sfb_masks_2_T_33, _f3_fetch_bundle_sfb_masks_2_T_35) node _f3_fetch_bundle_sfb_masks_2_T_65 = or(_f3_fetch_bundle_sfb_masks_2_T_64, _f3_fetch_bundle_sfb_masks_2_T_37) node _f3_fetch_bundle_sfb_masks_2_T_66 = or(_f3_fetch_bundle_sfb_masks_2_T_65, _f3_fetch_bundle_sfb_masks_2_T_39) node _f3_fetch_bundle_sfb_masks_2_T_67 = or(_f3_fetch_bundle_sfb_masks_2_T_66, _f3_fetch_bundle_sfb_masks_2_T_41) node _f3_fetch_bundle_sfb_masks_2_T_68 = or(_f3_fetch_bundle_sfb_masks_2_T_67, _f3_fetch_bundle_sfb_masks_2_T_43) node _f3_fetch_bundle_sfb_masks_2_T_69 = or(_f3_fetch_bundle_sfb_masks_2_T_68, _f3_fetch_bundle_sfb_masks_2_T_45) node _f3_fetch_bundle_sfb_masks_2_T_70 = or(_f3_fetch_bundle_sfb_masks_2_T_69, _f3_fetch_bundle_sfb_masks_2_T_47) node _f3_fetch_bundle_sfb_masks_2_T_71 = or(_f3_fetch_bundle_sfb_masks_2_T_70, _f3_fetch_bundle_sfb_masks_2_T_49) node _f3_fetch_bundle_sfb_masks_2_T_72 = or(_f3_fetch_bundle_sfb_masks_2_T_71, _f3_fetch_bundle_sfb_masks_2_T_51) node _f3_fetch_bundle_sfb_masks_2_T_73 = or(_f3_fetch_bundle_sfb_masks_2_T_72, _f3_fetch_bundle_sfb_masks_2_T_53) node _f3_fetch_bundle_sfb_masks_2_T_74 = or(_f3_fetch_bundle_sfb_masks_2_T_73, _f3_fetch_bundle_sfb_masks_2_T_55) node _f3_fetch_bundle_sfb_masks_2_T_75 = or(_f3_fetch_bundle_sfb_masks_2_T_74, _f3_fetch_bundle_sfb_masks_2_T_57) node _f3_fetch_bundle_sfb_masks_2_T_76 = or(_f3_fetch_bundle_sfb_masks_2_T_75, _f3_fetch_bundle_sfb_masks_2_T_59) node _f3_fetch_bundle_sfb_masks_2_T_77 = or(_f3_fetch_bundle_sfb_masks_2_T_76, _f3_fetch_bundle_sfb_masks_2_T_61) node _f3_fetch_bundle_sfb_masks_2_T_78 = or(_f3_fetch_bundle_sfb_masks_2_T_77, _f3_fetch_bundle_sfb_masks_2_T_63) node _f3_fetch_bundle_sfb_masks_2_T_79 = not(_f3_fetch_bundle_sfb_masks_2_T_78) node _f3_fetch_bundle_sfb_masks_2_T_80 = and(_f3_fetch_bundle_sfb_masks_2_T_31, _f3_fetch_bundle_sfb_masks_2_T_79) connect f3_fetch_bundle.sfb_masks[2], _f3_fetch_bundle_sfb_masks_2_T_80 node _f3_fetch_bundle_shadowable_mask_2_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_2_T_1 = or(_f3_fetch_bundle_shadowable_mask_2_T, bpu_2.io.debug_if) node _f3_fetch_bundle_shadowable_mask_2_T_2 = or(_f3_fetch_bundle_shadowable_mask_2_T_1, bpu_2.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_2_T_3 = eq(_f3_fetch_bundle_shadowable_mask_2_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_2_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_2_T_5 = and(_f3_fetch_bundle_shadowable_mask_2_T_3, _f3_fetch_bundle_shadowable_mask_2_T_4) node _f3_fetch_bundle_shadowable_mask_2_T_6 = eq(f3_mask[2], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_2_T_7 = or(brsigs_2.shadowable, _f3_fetch_bundle_shadowable_mask_2_T_6) node _f3_fetch_bundle_shadowable_mask_2_T_8 = and(_f3_fetch_bundle_shadowable_mask_2_T_5, _f3_fetch_bundle_shadowable_mask_2_T_7) connect f3_fetch_bundle.shadowable_mask[2], _f3_fetch_bundle_shadowable_mask_2_T_8 connect f3_fetch_bundle.sfb_dests[2], offset_from_aligned_pc_2 node _f3_redirects_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h2)) node _f3_redirects_2_T_1 = eq(brsigs_2.cfi_type, UInt<3>(0h3)) node _f3_redirects_2_T_2 = or(_f3_redirects_2_T, _f3_redirects_2_T_1) node _f3_redirects_2_T_3 = eq(brsigs_2.cfi_type, UInt<3>(0h1)) node _f3_redirects_2_T_4 = and(_f3_redirects_2_T_3, f3_bpd_resp.io.deq.bits.preds[2].taken) node _f3_redirects_2_T_5 = and(_f3_redirects_2_T_4, UInt<1>(0h1)) node _f3_redirects_2_T_6 = or(_f3_redirects_2_T_2, _f3_redirects_2_T_5) node _f3_redirects_2_T_7 = and(f3_mask[2], _f3_redirects_2_T_6) connect f3_redirects[2], _f3_redirects_2_T_7 node _f3_br_mask_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h1)) node _f3_br_mask_2_T_1 = and(f3_mask[2], _f3_br_mask_2_T) connect f3_br_mask[2], _f3_br_mask_2_T_1 connect f3_cfi_types[2], brsigs_2.cfi_type connect f3_call_mask[2], brsigs_2.is_call connect f3_ret_mask[2], brsigs_2.is_ret connect f3_fetch_bundle.bp_debug_if_oh[2], bpu_2.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[2], bpu_2.io.xcpt_if node _T_30 = or(_T_29, f3_redirects[2]) wire valid_3 : UInt<1> inst bpu_3 of BreakpointUnit_14 connect bpu_3.clock, clock connect bpu_3.reset, reset connect bpu_3.io.status.uie, io.cpu.status.uie connect bpu_3.io.status.sie, io.cpu.status.sie connect bpu_3.io.status.hie, io.cpu.status.hie connect bpu_3.io.status.mie, io.cpu.status.mie connect bpu_3.io.status.upie, io.cpu.status.upie connect bpu_3.io.status.spie, io.cpu.status.spie connect bpu_3.io.status.ube, io.cpu.status.ube connect bpu_3.io.status.mpie, io.cpu.status.mpie connect bpu_3.io.status.spp, io.cpu.status.spp connect bpu_3.io.status.vs, io.cpu.status.vs connect bpu_3.io.status.mpp, io.cpu.status.mpp connect bpu_3.io.status.fs, io.cpu.status.fs connect bpu_3.io.status.xs, io.cpu.status.xs connect bpu_3.io.status.mprv, io.cpu.status.mprv connect bpu_3.io.status.sum, io.cpu.status.sum connect bpu_3.io.status.mxr, io.cpu.status.mxr connect bpu_3.io.status.tvm, io.cpu.status.tvm connect bpu_3.io.status.tw, io.cpu.status.tw connect bpu_3.io.status.tsr, io.cpu.status.tsr connect bpu_3.io.status.zero1, io.cpu.status.zero1 connect bpu_3.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_3.io.status.uxl, io.cpu.status.uxl connect bpu_3.io.status.sxl, io.cpu.status.sxl connect bpu_3.io.status.sbe, io.cpu.status.sbe connect bpu_3.io.status.mbe, io.cpu.status.mbe connect bpu_3.io.status.gva, io.cpu.status.gva connect bpu_3.io.status.mpv, io.cpu.status.mpv connect bpu_3.io.status.zero2, io.cpu.status.zero2 connect bpu_3.io.status.sd, io.cpu.status.sd connect bpu_3.io.status.v, io.cpu.status.v connect bpu_3.io.status.prv, io.cpu.status.prv connect bpu_3.io.status.dv, io.cpu.status.dv connect bpu_3.io.status.dprv, io.cpu.status.dprv connect bpu_3.io.status.isa, io.cpu.status.isa connect bpu_3.io.status.wfi, io.cpu.status.wfi connect bpu_3.io.status.cease, io.cpu.status.cease connect bpu_3.io.status.debug, io.cpu.status.debug invalidate bpu_3.io.ea connect bpu_3.io.mcontext, io.cpu.mcontext connect bpu_3.io.scontext, io.cpu.scontext wire brsigs_3 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_2 : UInt<32> inst exp_inst_rvc_exp_2 of RVCExpander_17 connect exp_inst_rvc_exp_2.clock, clock connect exp_inst_rvc_exp_2.reset, reset connect exp_inst_rvc_exp_2.io.in, inst_2 node exp_inst_2 = mux(exp_inst_rvc_exp_2.io.rvc, exp_inst_rvc_exp_2.io.out.bits, inst_2) node _pc_T_2 = add(f3_aligned_pc, UInt<3>(0h6)) node pc_2 = tail(_pc_T_2, 1) inst bpd_decoder_2 of BranchDecode_15 connect bpd_decoder_2.clock, clock connect bpd_decoder_2.reset, reset connect bpd_decoder_2.io.inst, exp_inst_2 connect bpd_decoder_2.io.pc, pc_2 connect bank_insts[3], inst_2 connect f3_fetch_bundle.insts[3], inst_2 connect f3_fetch_bundle.exp_insts[3], exp_inst_2 connect bpu_3.io.pc, pc_2 connect brsigs_3.shadowable, bpd_decoder_2.io.out.shadowable connect brsigs_3.sfb_offset, bpd_decoder_2.io.out.sfb_offset connect brsigs_3.cfi_type, bpd_decoder_2.io.out.cfi_type connect brsigs_3.target, bpd_decoder_2.io.out.target connect brsigs_3.is_call, bpd_decoder_2.io.out.is_call connect brsigs_3.is_ret, bpd_decoder_2.io.out.is_ret node _inst_T_2 = bits(bank_data, 63, 48) node _inst_T_3 = cat(UInt<16>(0h0), _inst_T_2) connect inst_2, _inst_T_3 node _valid_T_11 = bits(bank_insts[2], 1, 0) node _valid_T_12 = neq(_valid_T_11, UInt<2>(0h3)) node _valid_T_13 = eq(_valid_T_12, UInt<1>(0h0)) node _valid_T_14 = and(bank_mask[2], _valid_T_13) node _valid_T_15 = bits(inst_2, 1, 0) node _valid_T_16 = neq(_valid_T_15, UInt<2>(0h3)) node _valid_T_17 = eq(_valid_T_16, UInt<1>(0h0)) node _valid_T_18 = or(_valid_T_14, _valid_T_17) node _valid_T_19 = eq(_valid_T_18, UInt<1>(0h0)) connect valid_3, _valid_T_19 node _f3_is_rvc_3_T = bits(bank_insts[3], 1, 0) node _f3_is_rvc_3_T_1 = neq(_f3_is_rvc_3_T, UInt<2>(0h3)) connect f3_is_rvc[3], _f3_is_rvc_3_T_1 node _bank_mask_3_T = bits(f3.io.deq.bits.mask, 3, 3) node _bank_mask_3_T_1 = and(f3.io.deq.valid, _bank_mask_3_T) node _bank_mask_3_T_2 = and(_bank_mask_3_T_1, valid_3) node _bank_mask_3_T_3 = eq(_T_30, UInt<1>(0h0)) node _bank_mask_3_T_4 = and(_bank_mask_3_T_2, _bank_mask_3_T_3) connect bank_mask[3], _bank_mask_3_T_4 node _f3_mask_3_T = bits(f3.io.deq.bits.mask, 3, 3) node _f3_mask_3_T_1 = and(f3.io.deq.valid, _f3_mask_3_T) node _f3_mask_3_T_2 = and(_f3_mask_3_T_1, valid_3) node _f3_mask_3_T_3 = eq(_T_30, UInt<1>(0h0)) node _f3_mask_3_T_4 = and(_f3_mask_3_T_2, _f3_mask_3_T_3) connect f3_mask[3], _f3_mask_3_T_4 node _f3_targs_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h3)) node _f3_targs_3_T_1 = mux(_f3_targs_3_T, f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.bits, brsigs_3.target) connect f3_targs[3], _f3_targs_3_T_1 node _f3_btb_mispredicts_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_3_T_1 = and(_f3_btb_mispredicts_3_T, valid_3) node _f3_btb_mispredicts_3_T_2 = and(_f3_btb_mispredicts_3_T_1, f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.valid) node _f3_btb_mispredicts_3_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.bits, brsigs_3.target) node _f3_btb_mispredicts_3_T_4 = and(_f3_btb_mispredicts_3_T_2, _f3_btb_mispredicts_3_T_3) connect f3_btb_mispredicts[3], _f3_btb_mispredicts_3_T_4 node _f3_npc_plus4_mask_3_T = eq(f3_is_rvc[3], UInt<1>(0h0)) connect f3_npc_plus4_mask[3], _f3_npc_plus4_mask_3_T node _offset_from_aligned_pc_T_15 = add(UInt<7>(0h6), brsigs_3.sfb_offset.bits) node _offset_from_aligned_pc_T_16 = tail(_offset_from_aligned_pc_T_15, 1) node _offset_from_aligned_pc_T_17 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_18 = mux(_offset_from_aligned_pc_T_17, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_19 = sub(_offset_from_aligned_pc_T_16, _offset_from_aligned_pc_T_18) node offset_from_aligned_pc_3 = tail(_offset_from_aligned_pc_T_19, 1) wire lower_mask_3 : UInt<16> wire upper_mask_3 : UInt<16> node _lower_mask_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3)) connect lower_mask_3, _lower_mask_T_3 node _upper_mask_T_12 = bits(offset_from_aligned_pc_3, 5, 1) node _upper_mask_T_13 = dshl(UInt<1>(0h1), _upper_mask_T_12) node _upper_mask_T_14 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_15 = dshl(_upper_mask_T_13, _upper_mask_T_14) connect upper_mask_3, _upper_mask_T_15 node _f3_fetch_bundle_sfbs_3_T = and(f3_mask[3], brsigs_3.sfb_offset.valid) node _f3_fetch_bundle_sfbs_3_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_3_T_2 = leq(offset_from_aligned_pc_3, _f3_fetch_bundle_sfbs_3_T_1) node _f3_fetch_bundle_sfbs_3_T_3 = and(_f3_fetch_bundle_sfbs_3_T, _f3_fetch_bundle_sfbs_3_T_2) connect f3_fetch_bundle.sfbs[3], _f3_fetch_bundle_sfbs_3_T_3 node _f3_fetch_bundle_sfb_masks_3_T = dshr(lower_mask_3, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_3_T_1 = dshr(lower_mask_3, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_3_T_2 = dshr(lower_mask_3, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_3_T_3 = dshr(lower_mask_3, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_3_T_4 = dshr(lower_mask_3, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_3_T_5 = dshr(lower_mask_3, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_3_T_6 = dshr(lower_mask_3, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_3_T_7 = dshr(lower_mask_3, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_3_T_8 = dshr(lower_mask_3, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_3_T_9 = dshr(lower_mask_3, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_3_T_10 = dshr(lower_mask_3, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_3_T_11 = dshr(lower_mask_3, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_3_T_12 = dshr(lower_mask_3, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_3_T_13 = dshr(lower_mask_3, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_3_T_14 = dshr(lower_mask_3, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_3_T_15 = dshr(lower_mask_3, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_3_T_16 = or(_f3_fetch_bundle_sfb_masks_3_T, _f3_fetch_bundle_sfb_masks_3_T_1) node _f3_fetch_bundle_sfb_masks_3_T_17 = or(_f3_fetch_bundle_sfb_masks_3_T_16, _f3_fetch_bundle_sfb_masks_3_T_2) node _f3_fetch_bundle_sfb_masks_3_T_18 = or(_f3_fetch_bundle_sfb_masks_3_T_17, _f3_fetch_bundle_sfb_masks_3_T_3) node _f3_fetch_bundle_sfb_masks_3_T_19 = or(_f3_fetch_bundle_sfb_masks_3_T_18, _f3_fetch_bundle_sfb_masks_3_T_4) node _f3_fetch_bundle_sfb_masks_3_T_20 = or(_f3_fetch_bundle_sfb_masks_3_T_19, _f3_fetch_bundle_sfb_masks_3_T_5) node _f3_fetch_bundle_sfb_masks_3_T_21 = or(_f3_fetch_bundle_sfb_masks_3_T_20, _f3_fetch_bundle_sfb_masks_3_T_6) node _f3_fetch_bundle_sfb_masks_3_T_22 = or(_f3_fetch_bundle_sfb_masks_3_T_21, _f3_fetch_bundle_sfb_masks_3_T_7) node _f3_fetch_bundle_sfb_masks_3_T_23 = or(_f3_fetch_bundle_sfb_masks_3_T_22, _f3_fetch_bundle_sfb_masks_3_T_8) node _f3_fetch_bundle_sfb_masks_3_T_24 = or(_f3_fetch_bundle_sfb_masks_3_T_23, _f3_fetch_bundle_sfb_masks_3_T_9) node _f3_fetch_bundle_sfb_masks_3_T_25 = or(_f3_fetch_bundle_sfb_masks_3_T_24, _f3_fetch_bundle_sfb_masks_3_T_10) node _f3_fetch_bundle_sfb_masks_3_T_26 = or(_f3_fetch_bundle_sfb_masks_3_T_25, _f3_fetch_bundle_sfb_masks_3_T_11) node _f3_fetch_bundle_sfb_masks_3_T_27 = or(_f3_fetch_bundle_sfb_masks_3_T_26, _f3_fetch_bundle_sfb_masks_3_T_12) node _f3_fetch_bundle_sfb_masks_3_T_28 = or(_f3_fetch_bundle_sfb_masks_3_T_27, _f3_fetch_bundle_sfb_masks_3_T_13) node _f3_fetch_bundle_sfb_masks_3_T_29 = or(_f3_fetch_bundle_sfb_masks_3_T_28, _f3_fetch_bundle_sfb_masks_3_T_14) node _f3_fetch_bundle_sfb_masks_3_T_30 = or(_f3_fetch_bundle_sfb_masks_3_T_29, _f3_fetch_bundle_sfb_masks_3_T_15) node _f3_fetch_bundle_sfb_masks_3_T_31 = not(_f3_fetch_bundle_sfb_masks_3_T_30) node _f3_fetch_bundle_sfb_masks_3_T_32 = dshl(upper_mask_3, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_3_T_33 = bits(_f3_fetch_bundle_sfb_masks_3_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_34 = dshl(upper_mask_3, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_3_T_35 = bits(_f3_fetch_bundle_sfb_masks_3_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_36 = dshl(upper_mask_3, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_3_T_37 = bits(_f3_fetch_bundle_sfb_masks_3_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_38 = dshl(upper_mask_3, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_3_T_39 = bits(_f3_fetch_bundle_sfb_masks_3_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_40 = dshl(upper_mask_3, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_3_T_41 = bits(_f3_fetch_bundle_sfb_masks_3_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_42 = dshl(upper_mask_3, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_3_T_43 = bits(_f3_fetch_bundle_sfb_masks_3_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_44 = dshl(upper_mask_3, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_3_T_45 = bits(_f3_fetch_bundle_sfb_masks_3_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_46 = dshl(upper_mask_3, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_3_T_47 = bits(_f3_fetch_bundle_sfb_masks_3_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_48 = dshl(upper_mask_3, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_3_T_49 = bits(_f3_fetch_bundle_sfb_masks_3_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_50 = dshl(upper_mask_3, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_3_T_51 = bits(_f3_fetch_bundle_sfb_masks_3_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_52 = dshl(upper_mask_3, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_3_T_53 = bits(_f3_fetch_bundle_sfb_masks_3_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_54 = dshl(upper_mask_3, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_3_T_55 = bits(_f3_fetch_bundle_sfb_masks_3_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_56 = dshl(upper_mask_3, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_3_T_57 = bits(_f3_fetch_bundle_sfb_masks_3_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_58 = dshl(upper_mask_3, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_3_T_59 = bits(_f3_fetch_bundle_sfb_masks_3_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_60 = dshl(upper_mask_3, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_3_T_61 = bits(_f3_fetch_bundle_sfb_masks_3_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_62 = dshl(upper_mask_3, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_3_T_63 = bits(_f3_fetch_bundle_sfb_masks_3_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_3_T_64 = or(_f3_fetch_bundle_sfb_masks_3_T_33, _f3_fetch_bundle_sfb_masks_3_T_35) node _f3_fetch_bundle_sfb_masks_3_T_65 = or(_f3_fetch_bundle_sfb_masks_3_T_64, _f3_fetch_bundle_sfb_masks_3_T_37) node _f3_fetch_bundle_sfb_masks_3_T_66 = or(_f3_fetch_bundle_sfb_masks_3_T_65, _f3_fetch_bundle_sfb_masks_3_T_39) node _f3_fetch_bundle_sfb_masks_3_T_67 = or(_f3_fetch_bundle_sfb_masks_3_T_66, _f3_fetch_bundle_sfb_masks_3_T_41) node _f3_fetch_bundle_sfb_masks_3_T_68 = or(_f3_fetch_bundle_sfb_masks_3_T_67, _f3_fetch_bundle_sfb_masks_3_T_43) node _f3_fetch_bundle_sfb_masks_3_T_69 = or(_f3_fetch_bundle_sfb_masks_3_T_68, _f3_fetch_bundle_sfb_masks_3_T_45) node _f3_fetch_bundle_sfb_masks_3_T_70 = or(_f3_fetch_bundle_sfb_masks_3_T_69, _f3_fetch_bundle_sfb_masks_3_T_47) node _f3_fetch_bundle_sfb_masks_3_T_71 = or(_f3_fetch_bundle_sfb_masks_3_T_70, _f3_fetch_bundle_sfb_masks_3_T_49) node _f3_fetch_bundle_sfb_masks_3_T_72 = or(_f3_fetch_bundle_sfb_masks_3_T_71, _f3_fetch_bundle_sfb_masks_3_T_51) node _f3_fetch_bundle_sfb_masks_3_T_73 = or(_f3_fetch_bundle_sfb_masks_3_T_72, _f3_fetch_bundle_sfb_masks_3_T_53) node _f3_fetch_bundle_sfb_masks_3_T_74 = or(_f3_fetch_bundle_sfb_masks_3_T_73, _f3_fetch_bundle_sfb_masks_3_T_55) node _f3_fetch_bundle_sfb_masks_3_T_75 = or(_f3_fetch_bundle_sfb_masks_3_T_74, _f3_fetch_bundle_sfb_masks_3_T_57) node _f3_fetch_bundle_sfb_masks_3_T_76 = or(_f3_fetch_bundle_sfb_masks_3_T_75, _f3_fetch_bundle_sfb_masks_3_T_59) node _f3_fetch_bundle_sfb_masks_3_T_77 = or(_f3_fetch_bundle_sfb_masks_3_T_76, _f3_fetch_bundle_sfb_masks_3_T_61) node _f3_fetch_bundle_sfb_masks_3_T_78 = or(_f3_fetch_bundle_sfb_masks_3_T_77, _f3_fetch_bundle_sfb_masks_3_T_63) node _f3_fetch_bundle_sfb_masks_3_T_79 = not(_f3_fetch_bundle_sfb_masks_3_T_78) node _f3_fetch_bundle_sfb_masks_3_T_80 = and(_f3_fetch_bundle_sfb_masks_3_T_31, _f3_fetch_bundle_sfb_masks_3_T_79) connect f3_fetch_bundle.sfb_masks[3], _f3_fetch_bundle_sfb_masks_3_T_80 node _f3_fetch_bundle_shadowable_mask_3_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_3_T_1 = or(_f3_fetch_bundle_shadowable_mask_3_T, bpu_3.io.debug_if) node _f3_fetch_bundle_shadowable_mask_3_T_2 = or(_f3_fetch_bundle_shadowable_mask_3_T_1, bpu_3.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_3_T_3 = eq(_f3_fetch_bundle_shadowable_mask_3_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_3_T_4 = bits(f3_bank_mask, 0, 0) node _f3_fetch_bundle_shadowable_mask_3_T_5 = and(_f3_fetch_bundle_shadowable_mask_3_T_3, _f3_fetch_bundle_shadowable_mask_3_T_4) node _f3_fetch_bundle_shadowable_mask_3_T_6 = eq(f3_mask[3], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_3_T_7 = or(brsigs_3.shadowable, _f3_fetch_bundle_shadowable_mask_3_T_6) node _f3_fetch_bundle_shadowable_mask_3_T_8 = and(_f3_fetch_bundle_shadowable_mask_3_T_5, _f3_fetch_bundle_shadowable_mask_3_T_7) connect f3_fetch_bundle.shadowable_mask[3], _f3_fetch_bundle_shadowable_mask_3_T_8 connect f3_fetch_bundle.sfb_dests[3], offset_from_aligned_pc_3 node _f3_redirects_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h2)) node _f3_redirects_3_T_1 = eq(brsigs_3.cfi_type, UInt<3>(0h3)) node _f3_redirects_3_T_2 = or(_f3_redirects_3_T, _f3_redirects_3_T_1) node _f3_redirects_3_T_3 = eq(brsigs_3.cfi_type, UInt<3>(0h1)) node _f3_redirects_3_T_4 = and(_f3_redirects_3_T_3, f3_bpd_resp.io.deq.bits.preds[3].taken) node _f3_redirects_3_T_5 = and(_f3_redirects_3_T_4, UInt<1>(0h1)) node _f3_redirects_3_T_6 = or(_f3_redirects_3_T_2, _f3_redirects_3_T_5) node _f3_redirects_3_T_7 = and(f3_mask[3], _f3_redirects_3_T_6) connect f3_redirects[3], _f3_redirects_3_T_7 node _f3_br_mask_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h1)) node _f3_br_mask_3_T_1 = and(f3_mask[3], _f3_br_mask_3_T) connect f3_br_mask[3], _f3_br_mask_3_T_1 connect f3_cfi_types[3], brsigs_3.cfi_type connect f3_call_mask[3], brsigs_3.is_call connect f3_ret_mask[3], brsigs_3.is_ret connect f3_fetch_bundle.bp_debug_if_oh[3], bpu_3.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[3], bpu_3.io.xcpt_if node _T_31 = or(_T_30, f3_redirects[3]) node _T_32 = bits(bank_insts[3], 15, 0) node _T_33 = bits(f3_bank_mask, 0, 0) node _T_34 = bits(bank_insts[2], 1, 0) node _T_35 = neq(_T_34, UInt<2>(0h3)) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = and(bank_mask[2], _T_36) node _T_38 = eq(_T_37, UInt<1>(0h0)) node _T_39 = bits(_T_32, 1, 0) node _T_40 = neq(_T_39, UInt<2>(0h3)) node _T_41 = eq(_T_40, UInt<1>(0h0)) node _T_42 = and(_T_38, _T_41) node _T_43 = mux(_T_33, _T_42, f3_prev_is_half) node _T_44 = bits(f3_bank_mask, 0, 0) node _T_45 = bits(_T_32, 15, 0) node _T_46 = mux(_T_44, _T_45, f3_prev_half) node bank_data_1 = bits(f3.io.deq.bits.data, 127, 64) wire bank_mask_1 : UInt<1>[4] wire bank_insts_1 : UInt<32>[4] wire valid_4 : UInt<1> inst bpu_4 of BreakpointUnit_15 connect bpu_4.clock, clock connect bpu_4.reset, reset connect bpu_4.io.status.uie, io.cpu.status.uie connect bpu_4.io.status.sie, io.cpu.status.sie connect bpu_4.io.status.hie, io.cpu.status.hie connect bpu_4.io.status.mie, io.cpu.status.mie connect bpu_4.io.status.upie, io.cpu.status.upie connect bpu_4.io.status.spie, io.cpu.status.spie connect bpu_4.io.status.ube, io.cpu.status.ube connect bpu_4.io.status.mpie, io.cpu.status.mpie connect bpu_4.io.status.spp, io.cpu.status.spp connect bpu_4.io.status.vs, io.cpu.status.vs connect bpu_4.io.status.mpp, io.cpu.status.mpp connect bpu_4.io.status.fs, io.cpu.status.fs connect bpu_4.io.status.xs, io.cpu.status.xs connect bpu_4.io.status.mprv, io.cpu.status.mprv connect bpu_4.io.status.sum, io.cpu.status.sum connect bpu_4.io.status.mxr, io.cpu.status.mxr connect bpu_4.io.status.tvm, io.cpu.status.tvm connect bpu_4.io.status.tw, io.cpu.status.tw connect bpu_4.io.status.tsr, io.cpu.status.tsr connect bpu_4.io.status.zero1, io.cpu.status.zero1 connect bpu_4.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_4.io.status.uxl, io.cpu.status.uxl connect bpu_4.io.status.sxl, io.cpu.status.sxl connect bpu_4.io.status.sbe, io.cpu.status.sbe connect bpu_4.io.status.mbe, io.cpu.status.mbe connect bpu_4.io.status.gva, io.cpu.status.gva connect bpu_4.io.status.mpv, io.cpu.status.mpv connect bpu_4.io.status.zero2, io.cpu.status.zero2 connect bpu_4.io.status.sd, io.cpu.status.sd connect bpu_4.io.status.v, io.cpu.status.v connect bpu_4.io.status.prv, io.cpu.status.prv connect bpu_4.io.status.dv, io.cpu.status.dv connect bpu_4.io.status.dprv, io.cpu.status.dprv connect bpu_4.io.status.isa, io.cpu.status.isa connect bpu_4.io.status.wfi, io.cpu.status.wfi connect bpu_4.io.status.cease, io.cpu.status.cease connect bpu_4.io.status.debug, io.cpu.status.debug invalidate bpu_4.io.ea connect bpu_4.io.mcontext, io.cpu.mcontext connect bpu_4.io.scontext, io.cpu.scontext wire brsigs_4 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} node _inst0_T_1 = bits(bank_data_1, 15, 0) node inst0_1 = cat(_inst0_T_1, f3_prev_half) node inst1_1 = bits(bank_data_1, 31, 0) inst exp_inst0_rvc_exp_1 of RVCExpander_18 connect exp_inst0_rvc_exp_1.clock, clock connect exp_inst0_rvc_exp_1.reset, reset connect exp_inst0_rvc_exp_1.io.in, inst0_1 node exp_inst0_1 = mux(exp_inst0_rvc_exp_1.io.rvc, exp_inst0_rvc_exp_1.io.out.bits, inst0_1) inst exp_inst1_rvc_exp_1 of RVCExpander_19 connect exp_inst1_rvc_exp_1.clock, clock connect exp_inst1_rvc_exp_1.reset, reset connect exp_inst1_rvc_exp_1.io.in, inst1_1 node exp_inst1_1 = mux(exp_inst1_rvc_exp_1.io.rvc, exp_inst1_rvc_exp_1.io.out.bits, inst1_1) node _pc0_T_3 = add(f3_aligned_pc, UInt<4>(0h8)) node _pc0_T_4 = tail(_pc0_T_3, 1) node _pc0_T_5 = sub(_pc0_T_4, UInt<2>(0h2)) node pc0_1 = tail(_pc0_T_5, 1) node _pc1_T_1 = add(f3_aligned_pc, UInt<4>(0h8)) node pc1_1 = tail(_pc1_T_1, 1) inst bpd_decoder0_1 of BranchDecode_16 connect bpd_decoder0_1.clock, clock connect bpd_decoder0_1.reset, reset connect bpd_decoder0_1.io.inst, exp_inst0_1 connect bpd_decoder0_1.io.pc, pc0_1 inst bpd_decoder1_1 of BranchDecode_17 connect bpd_decoder1_1.clock, clock connect bpd_decoder1_1.reset, reset connect bpd_decoder1_1.io.inst, exp_inst1_1 connect bpd_decoder1_1.io.pc, pc1_1 when _T_43 : connect bank_insts_1[0], inst0_1 connect f3_fetch_bundle.insts[4], inst0_1 connect f3_fetch_bundle.exp_insts[4], exp_inst0_1 connect bpu_4.io.pc, pc0_1 connect brsigs_4.shadowable, bpd_decoder0_1.io.out.shadowable connect brsigs_4.sfb_offset, bpd_decoder0_1.io.out.sfb_offset connect brsigs_4.cfi_type, bpd_decoder0_1.io.out.cfi_type connect brsigs_4.target, bpd_decoder0_1.io.out.target connect brsigs_4.is_call, bpd_decoder0_1.io.out.is_call connect brsigs_4.is_ret, bpd_decoder0_1.io.out.is_ret connect f3_fetch_bundle.edge_inst[1], UInt<1>(0h1) node _inst0b_T = bits(bank_data_1, 15, 0) node inst0b = cat(_inst0b_T, _T_32) inst exp_inst0b_rvc_exp of RVCExpander_20 connect exp_inst0b_rvc_exp.clock, clock connect exp_inst0b_rvc_exp.reset, reset connect exp_inst0b_rvc_exp.io.in, inst0b node exp_inst0b = mux(exp_inst0b_rvc_exp.io.rvc, exp_inst0b_rvc_exp.io.out.bits, inst0b) inst bpd_decoder0b of BranchDecode_18 connect bpd_decoder0b.clock, clock connect bpd_decoder0b.reset, reset connect bpd_decoder0b.io.inst, exp_inst0b connect bpd_decoder0b.io.pc, pc0_1 node _T_47 = bits(f3_bank_mask, 0, 0) when _T_47 : connect bank_insts_1[0], inst0b connect f3_fetch_bundle.insts[4], inst0b connect f3_fetch_bundle.exp_insts[4], exp_inst0b connect brsigs_4.shadowable, bpd_decoder0b.io.out.shadowable connect brsigs_4.sfb_offset, bpd_decoder0b.io.out.sfb_offset connect brsigs_4.cfi_type, bpd_decoder0b.io.out.cfi_type connect brsigs_4.target, bpd_decoder0b.io.out.target connect brsigs_4.is_call, bpd_decoder0b.io.out.is_call connect brsigs_4.is_ret, bpd_decoder0b.io.out.is_ret else : connect bank_insts_1[0], inst1_1 connect f3_fetch_bundle.insts[4], inst1_1 connect f3_fetch_bundle.exp_insts[4], exp_inst1_1 connect bpu_4.io.pc, pc1_1 connect brsigs_4.shadowable, bpd_decoder1_1.io.out.shadowable connect brsigs_4.sfb_offset, bpd_decoder1_1.io.out.sfb_offset connect brsigs_4.cfi_type, bpd_decoder1_1.io.out.cfi_type connect brsigs_4.target, bpd_decoder1_1.io.out.target connect brsigs_4.is_call, bpd_decoder1_1.io.out.is_call connect brsigs_4.is_ret, bpd_decoder1_1.io.out.is_ret connect f3_fetch_bundle.edge_inst[1], UInt<1>(0h0) connect valid_4, UInt<1>(0h1) node _f3_is_rvc_4_T = bits(bank_insts_1[0], 1, 0) node _f3_is_rvc_4_T_1 = neq(_f3_is_rvc_4_T, UInt<2>(0h3)) connect f3_is_rvc[4], _f3_is_rvc_4_T_1 node _bank_mask_0_T_5 = bits(f3.io.deq.bits.mask, 4, 4) node _bank_mask_0_T_6 = and(f3.io.deq.valid, _bank_mask_0_T_5) node _bank_mask_0_T_7 = and(_bank_mask_0_T_6, valid_4) node _bank_mask_0_T_8 = eq(_T_31, UInt<1>(0h0)) node _bank_mask_0_T_9 = and(_bank_mask_0_T_7, _bank_mask_0_T_8) connect bank_mask_1[0], _bank_mask_0_T_9 node _f3_mask_4_T = bits(f3.io.deq.bits.mask, 4, 4) node _f3_mask_4_T_1 = and(f3.io.deq.valid, _f3_mask_4_T) node _f3_mask_4_T_2 = and(_f3_mask_4_T_1, valid_4) node _f3_mask_4_T_3 = eq(_T_31, UInt<1>(0h0)) node _f3_mask_4_T_4 = and(_f3_mask_4_T_2, _f3_mask_4_T_3) connect f3_mask[4], _f3_mask_4_T_4 node _f3_targs_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h3)) node _f3_targs_4_T_1 = mux(_f3_targs_4_T, f3_bpd_resp.io.deq.bits.preds[4].predicted_pc.bits, brsigs_4.target) connect f3_targs[4], _f3_targs_4_T_1 node _f3_btb_mispredicts_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_4_T_1 = and(_f3_btb_mispredicts_4_T, valid_4) node _f3_btb_mispredicts_4_T_2 = and(_f3_btb_mispredicts_4_T_1, f3_bpd_resp.io.deq.bits.preds[4].predicted_pc.valid) node _f3_btb_mispredicts_4_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[4].predicted_pc.bits, brsigs_4.target) node _f3_btb_mispredicts_4_T_4 = and(_f3_btb_mispredicts_4_T_2, _f3_btb_mispredicts_4_T_3) connect f3_btb_mispredicts[4], _f3_btb_mispredicts_4_T_4 node _f3_npc_plus4_mask_4_T = eq(f3_is_rvc[4], UInt<1>(0h0)) node _f3_npc_plus4_mask_4_T_1 = eq(_T_43, UInt<1>(0h0)) node _f3_npc_plus4_mask_4_T_2 = and(_f3_npc_plus4_mask_4_T, _f3_npc_plus4_mask_4_T_1) connect f3_npc_plus4_mask[4], _f3_npc_plus4_mask_4_T_2 node _offset_from_aligned_pc_T_20 = add(UInt<7>(0h8), brsigs_4.sfb_offset.bits) node _offset_from_aligned_pc_T_21 = tail(_offset_from_aligned_pc_T_20, 1) node _offset_from_aligned_pc_T_22 = and(_T_43, UInt<1>(0h1)) node _offset_from_aligned_pc_T_23 = mux(_offset_from_aligned_pc_T_22, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_24 = sub(_offset_from_aligned_pc_T_21, _offset_from_aligned_pc_T_23) node offset_from_aligned_pc_4 = tail(_offset_from_aligned_pc_T_24, 1) wire lower_mask_4 : UInt<16> wire upper_mask_4 : UInt<16> node _lower_mask_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4)) connect lower_mask_4, _lower_mask_T_4 node _upper_mask_T_16 = bits(offset_from_aligned_pc_4, 5, 1) node _upper_mask_T_17 = dshl(UInt<1>(0h1), _upper_mask_T_16) node _upper_mask_T_18 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_19 = dshl(_upper_mask_T_17, _upper_mask_T_18) connect upper_mask_4, _upper_mask_T_19 node _f3_fetch_bundle_sfbs_4_T = and(f3_mask[4], brsigs_4.sfb_offset.valid) node _f3_fetch_bundle_sfbs_4_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_4_T_2 = leq(offset_from_aligned_pc_4, _f3_fetch_bundle_sfbs_4_T_1) node _f3_fetch_bundle_sfbs_4_T_3 = and(_f3_fetch_bundle_sfbs_4_T, _f3_fetch_bundle_sfbs_4_T_2) connect f3_fetch_bundle.sfbs[4], _f3_fetch_bundle_sfbs_4_T_3 node _f3_fetch_bundle_sfb_masks_4_T = dshr(lower_mask_4, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_4_T_1 = dshr(lower_mask_4, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_4_T_2 = dshr(lower_mask_4, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_4_T_3 = dshr(lower_mask_4, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_4_T_4 = dshr(lower_mask_4, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_4_T_5 = dshr(lower_mask_4, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_4_T_6 = dshr(lower_mask_4, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_4_T_7 = dshr(lower_mask_4, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_4_T_8 = dshr(lower_mask_4, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_4_T_9 = dshr(lower_mask_4, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_4_T_10 = dshr(lower_mask_4, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_4_T_11 = dshr(lower_mask_4, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_4_T_12 = dshr(lower_mask_4, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_4_T_13 = dshr(lower_mask_4, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_4_T_14 = dshr(lower_mask_4, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_4_T_15 = dshr(lower_mask_4, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_4_T_16 = or(_f3_fetch_bundle_sfb_masks_4_T, _f3_fetch_bundle_sfb_masks_4_T_1) node _f3_fetch_bundle_sfb_masks_4_T_17 = or(_f3_fetch_bundle_sfb_masks_4_T_16, _f3_fetch_bundle_sfb_masks_4_T_2) node _f3_fetch_bundle_sfb_masks_4_T_18 = or(_f3_fetch_bundle_sfb_masks_4_T_17, _f3_fetch_bundle_sfb_masks_4_T_3) node _f3_fetch_bundle_sfb_masks_4_T_19 = or(_f3_fetch_bundle_sfb_masks_4_T_18, _f3_fetch_bundle_sfb_masks_4_T_4) node _f3_fetch_bundle_sfb_masks_4_T_20 = or(_f3_fetch_bundle_sfb_masks_4_T_19, _f3_fetch_bundle_sfb_masks_4_T_5) node _f3_fetch_bundle_sfb_masks_4_T_21 = or(_f3_fetch_bundle_sfb_masks_4_T_20, _f3_fetch_bundle_sfb_masks_4_T_6) node _f3_fetch_bundle_sfb_masks_4_T_22 = or(_f3_fetch_bundle_sfb_masks_4_T_21, _f3_fetch_bundle_sfb_masks_4_T_7) node _f3_fetch_bundle_sfb_masks_4_T_23 = or(_f3_fetch_bundle_sfb_masks_4_T_22, _f3_fetch_bundle_sfb_masks_4_T_8) node _f3_fetch_bundle_sfb_masks_4_T_24 = or(_f3_fetch_bundle_sfb_masks_4_T_23, _f3_fetch_bundle_sfb_masks_4_T_9) node _f3_fetch_bundle_sfb_masks_4_T_25 = or(_f3_fetch_bundle_sfb_masks_4_T_24, _f3_fetch_bundle_sfb_masks_4_T_10) node _f3_fetch_bundle_sfb_masks_4_T_26 = or(_f3_fetch_bundle_sfb_masks_4_T_25, _f3_fetch_bundle_sfb_masks_4_T_11) node _f3_fetch_bundle_sfb_masks_4_T_27 = or(_f3_fetch_bundle_sfb_masks_4_T_26, _f3_fetch_bundle_sfb_masks_4_T_12) node _f3_fetch_bundle_sfb_masks_4_T_28 = or(_f3_fetch_bundle_sfb_masks_4_T_27, _f3_fetch_bundle_sfb_masks_4_T_13) node _f3_fetch_bundle_sfb_masks_4_T_29 = or(_f3_fetch_bundle_sfb_masks_4_T_28, _f3_fetch_bundle_sfb_masks_4_T_14) node _f3_fetch_bundle_sfb_masks_4_T_30 = or(_f3_fetch_bundle_sfb_masks_4_T_29, _f3_fetch_bundle_sfb_masks_4_T_15) node _f3_fetch_bundle_sfb_masks_4_T_31 = not(_f3_fetch_bundle_sfb_masks_4_T_30) node _f3_fetch_bundle_sfb_masks_4_T_32 = dshl(upper_mask_4, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_4_T_33 = bits(_f3_fetch_bundle_sfb_masks_4_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_34 = dshl(upper_mask_4, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_4_T_35 = bits(_f3_fetch_bundle_sfb_masks_4_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_36 = dshl(upper_mask_4, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_4_T_37 = bits(_f3_fetch_bundle_sfb_masks_4_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_38 = dshl(upper_mask_4, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_4_T_39 = bits(_f3_fetch_bundle_sfb_masks_4_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_40 = dshl(upper_mask_4, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_4_T_41 = bits(_f3_fetch_bundle_sfb_masks_4_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_42 = dshl(upper_mask_4, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_4_T_43 = bits(_f3_fetch_bundle_sfb_masks_4_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_44 = dshl(upper_mask_4, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_4_T_45 = bits(_f3_fetch_bundle_sfb_masks_4_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_46 = dshl(upper_mask_4, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_4_T_47 = bits(_f3_fetch_bundle_sfb_masks_4_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_48 = dshl(upper_mask_4, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_4_T_49 = bits(_f3_fetch_bundle_sfb_masks_4_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_50 = dshl(upper_mask_4, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_4_T_51 = bits(_f3_fetch_bundle_sfb_masks_4_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_52 = dshl(upper_mask_4, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_4_T_53 = bits(_f3_fetch_bundle_sfb_masks_4_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_54 = dshl(upper_mask_4, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_4_T_55 = bits(_f3_fetch_bundle_sfb_masks_4_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_56 = dshl(upper_mask_4, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_4_T_57 = bits(_f3_fetch_bundle_sfb_masks_4_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_58 = dshl(upper_mask_4, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_4_T_59 = bits(_f3_fetch_bundle_sfb_masks_4_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_60 = dshl(upper_mask_4, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_4_T_61 = bits(_f3_fetch_bundle_sfb_masks_4_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_62 = dshl(upper_mask_4, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_4_T_63 = bits(_f3_fetch_bundle_sfb_masks_4_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_4_T_64 = or(_f3_fetch_bundle_sfb_masks_4_T_33, _f3_fetch_bundle_sfb_masks_4_T_35) node _f3_fetch_bundle_sfb_masks_4_T_65 = or(_f3_fetch_bundle_sfb_masks_4_T_64, _f3_fetch_bundle_sfb_masks_4_T_37) node _f3_fetch_bundle_sfb_masks_4_T_66 = or(_f3_fetch_bundle_sfb_masks_4_T_65, _f3_fetch_bundle_sfb_masks_4_T_39) node _f3_fetch_bundle_sfb_masks_4_T_67 = or(_f3_fetch_bundle_sfb_masks_4_T_66, _f3_fetch_bundle_sfb_masks_4_T_41) node _f3_fetch_bundle_sfb_masks_4_T_68 = or(_f3_fetch_bundle_sfb_masks_4_T_67, _f3_fetch_bundle_sfb_masks_4_T_43) node _f3_fetch_bundle_sfb_masks_4_T_69 = or(_f3_fetch_bundle_sfb_masks_4_T_68, _f3_fetch_bundle_sfb_masks_4_T_45) node _f3_fetch_bundle_sfb_masks_4_T_70 = or(_f3_fetch_bundle_sfb_masks_4_T_69, _f3_fetch_bundle_sfb_masks_4_T_47) node _f3_fetch_bundle_sfb_masks_4_T_71 = or(_f3_fetch_bundle_sfb_masks_4_T_70, _f3_fetch_bundle_sfb_masks_4_T_49) node _f3_fetch_bundle_sfb_masks_4_T_72 = or(_f3_fetch_bundle_sfb_masks_4_T_71, _f3_fetch_bundle_sfb_masks_4_T_51) node _f3_fetch_bundle_sfb_masks_4_T_73 = or(_f3_fetch_bundle_sfb_masks_4_T_72, _f3_fetch_bundle_sfb_masks_4_T_53) node _f3_fetch_bundle_sfb_masks_4_T_74 = or(_f3_fetch_bundle_sfb_masks_4_T_73, _f3_fetch_bundle_sfb_masks_4_T_55) node _f3_fetch_bundle_sfb_masks_4_T_75 = or(_f3_fetch_bundle_sfb_masks_4_T_74, _f3_fetch_bundle_sfb_masks_4_T_57) node _f3_fetch_bundle_sfb_masks_4_T_76 = or(_f3_fetch_bundle_sfb_masks_4_T_75, _f3_fetch_bundle_sfb_masks_4_T_59) node _f3_fetch_bundle_sfb_masks_4_T_77 = or(_f3_fetch_bundle_sfb_masks_4_T_76, _f3_fetch_bundle_sfb_masks_4_T_61) node _f3_fetch_bundle_sfb_masks_4_T_78 = or(_f3_fetch_bundle_sfb_masks_4_T_77, _f3_fetch_bundle_sfb_masks_4_T_63) node _f3_fetch_bundle_sfb_masks_4_T_79 = not(_f3_fetch_bundle_sfb_masks_4_T_78) node _f3_fetch_bundle_sfb_masks_4_T_80 = and(_f3_fetch_bundle_sfb_masks_4_T_31, _f3_fetch_bundle_sfb_masks_4_T_79) connect f3_fetch_bundle.sfb_masks[4], _f3_fetch_bundle_sfb_masks_4_T_80 node _f3_fetch_bundle_shadowable_mask_4_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_4_T_1 = or(_f3_fetch_bundle_shadowable_mask_4_T, bpu_4.io.debug_if) node _f3_fetch_bundle_shadowable_mask_4_T_2 = or(_f3_fetch_bundle_shadowable_mask_4_T_1, bpu_4.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_4_T_3 = eq(_f3_fetch_bundle_shadowable_mask_4_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_4_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_4_T_5 = and(_f3_fetch_bundle_shadowable_mask_4_T_3, _f3_fetch_bundle_shadowable_mask_4_T_4) node _f3_fetch_bundle_shadowable_mask_4_T_6 = eq(f3_mask[4], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_4_T_7 = or(brsigs_4.shadowable, _f3_fetch_bundle_shadowable_mask_4_T_6) node _f3_fetch_bundle_shadowable_mask_4_T_8 = and(_f3_fetch_bundle_shadowable_mask_4_T_5, _f3_fetch_bundle_shadowable_mask_4_T_7) connect f3_fetch_bundle.shadowable_mask[4], _f3_fetch_bundle_shadowable_mask_4_T_8 connect f3_fetch_bundle.sfb_dests[4], offset_from_aligned_pc_4 node _f3_redirects_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h2)) node _f3_redirects_4_T_1 = eq(brsigs_4.cfi_type, UInt<3>(0h3)) node _f3_redirects_4_T_2 = or(_f3_redirects_4_T, _f3_redirects_4_T_1) node _f3_redirects_4_T_3 = eq(brsigs_4.cfi_type, UInt<3>(0h1)) node _f3_redirects_4_T_4 = and(_f3_redirects_4_T_3, f3_bpd_resp.io.deq.bits.preds[4].taken) node _f3_redirects_4_T_5 = and(_f3_redirects_4_T_4, UInt<1>(0h1)) node _f3_redirects_4_T_6 = or(_f3_redirects_4_T_2, _f3_redirects_4_T_5) node _f3_redirects_4_T_7 = and(f3_mask[4], _f3_redirects_4_T_6) connect f3_redirects[4], _f3_redirects_4_T_7 node _f3_br_mask_4_T = eq(brsigs_4.cfi_type, UInt<3>(0h1)) node _f3_br_mask_4_T_1 = and(f3_mask[4], _f3_br_mask_4_T) connect f3_br_mask[4], _f3_br_mask_4_T_1 connect f3_cfi_types[4], brsigs_4.cfi_type connect f3_call_mask[4], brsigs_4.is_call connect f3_ret_mask[4], brsigs_4.is_ret connect f3_fetch_bundle.bp_debug_if_oh[4], bpu_4.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[4], bpu_4.io.xcpt_if node _T_48 = or(_T_31, f3_redirects[4]) wire valid_5 : UInt<1> inst bpu_5 of BreakpointUnit_16 connect bpu_5.clock, clock connect bpu_5.reset, reset connect bpu_5.io.status.uie, io.cpu.status.uie connect bpu_5.io.status.sie, io.cpu.status.sie connect bpu_5.io.status.hie, io.cpu.status.hie connect bpu_5.io.status.mie, io.cpu.status.mie connect bpu_5.io.status.upie, io.cpu.status.upie connect bpu_5.io.status.spie, io.cpu.status.spie connect bpu_5.io.status.ube, io.cpu.status.ube connect bpu_5.io.status.mpie, io.cpu.status.mpie connect bpu_5.io.status.spp, io.cpu.status.spp connect bpu_5.io.status.vs, io.cpu.status.vs connect bpu_5.io.status.mpp, io.cpu.status.mpp connect bpu_5.io.status.fs, io.cpu.status.fs connect bpu_5.io.status.xs, io.cpu.status.xs connect bpu_5.io.status.mprv, io.cpu.status.mprv connect bpu_5.io.status.sum, io.cpu.status.sum connect bpu_5.io.status.mxr, io.cpu.status.mxr connect bpu_5.io.status.tvm, io.cpu.status.tvm connect bpu_5.io.status.tw, io.cpu.status.tw connect bpu_5.io.status.tsr, io.cpu.status.tsr connect bpu_5.io.status.zero1, io.cpu.status.zero1 connect bpu_5.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_5.io.status.uxl, io.cpu.status.uxl connect bpu_5.io.status.sxl, io.cpu.status.sxl connect bpu_5.io.status.sbe, io.cpu.status.sbe connect bpu_5.io.status.mbe, io.cpu.status.mbe connect bpu_5.io.status.gva, io.cpu.status.gva connect bpu_5.io.status.mpv, io.cpu.status.mpv connect bpu_5.io.status.zero2, io.cpu.status.zero2 connect bpu_5.io.status.sd, io.cpu.status.sd connect bpu_5.io.status.v, io.cpu.status.v connect bpu_5.io.status.prv, io.cpu.status.prv connect bpu_5.io.status.dv, io.cpu.status.dv connect bpu_5.io.status.dprv, io.cpu.status.dprv connect bpu_5.io.status.isa, io.cpu.status.isa connect bpu_5.io.status.wfi, io.cpu.status.wfi connect bpu_5.io.status.cease, io.cpu.status.cease connect bpu_5.io.status.debug, io.cpu.status.debug invalidate bpu_5.io.ea connect bpu_5.io.mcontext, io.cpu.mcontext connect bpu_5.io.scontext, io.cpu.scontext wire brsigs_5 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_3 : UInt<32> inst exp_inst_rvc_exp_3 of RVCExpander_21 connect exp_inst_rvc_exp_3.clock, clock connect exp_inst_rvc_exp_3.reset, reset connect exp_inst_rvc_exp_3.io.in, inst_3 node exp_inst_3 = mux(exp_inst_rvc_exp_3.io.rvc, exp_inst_rvc_exp_3.io.out.bits, inst_3) node _pc_T_3 = add(f3_aligned_pc, UInt<4>(0ha)) node pc_3 = tail(_pc_T_3, 1) inst bpd_decoder_3 of BranchDecode_19 connect bpd_decoder_3.clock, clock connect bpd_decoder_3.reset, reset connect bpd_decoder_3.io.inst, exp_inst_3 connect bpd_decoder_3.io.pc, pc_3 connect bank_insts_1[1], inst_3 connect f3_fetch_bundle.insts[5], inst_3 connect f3_fetch_bundle.exp_insts[5], exp_inst_3 connect bpu_5.io.pc, pc_3 connect brsigs_5.shadowable, bpd_decoder_3.io.out.shadowable connect brsigs_5.sfb_offset, bpd_decoder_3.io.out.sfb_offset connect brsigs_5.cfi_type, bpd_decoder_3.io.out.cfi_type connect brsigs_5.target, bpd_decoder_3.io.out.target connect brsigs_5.is_call, bpd_decoder_3.io.out.is_call connect brsigs_5.is_ret, bpd_decoder_3.io.out.is_ret node _inst_T_4 = bits(bank_data_1, 47, 16) connect inst_3, _inst_T_4 node _valid_T_20 = bits(bank_insts_1[0], 1, 0) node _valid_T_21 = neq(_valid_T_20, UInt<2>(0h3)) node _valid_T_22 = eq(_valid_T_21, UInt<1>(0h0)) node _valid_T_23 = and(bank_mask_1[0], _valid_T_22) node _valid_T_24 = eq(_valid_T_23, UInt<1>(0h0)) node _valid_T_25 = or(_T_43, _valid_T_24) connect valid_5, _valid_T_25 node _f3_is_rvc_5_T = bits(bank_insts_1[1], 1, 0) node _f3_is_rvc_5_T_1 = neq(_f3_is_rvc_5_T, UInt<2>(0h3)) connect f3_is_rvc[5], _f3_is_rvc_5_T_1 node _bank_mask_1_T_5 = bits(f3.io.deq.bits.mask, 5, 5) node _bank_mask_1_T_6 = and(f3.io.deq.valid, _bank_mask_1_T_5) node _bank_mask_1_T_7 = and(_bank_mask_1_T_6, valid_5) node _bank_mask_1_T_8 = eq(_T_48, UInt<1>(0h0)) node _bank_mask_1_T_9 = and(_bank_mask_1_T_7, _bank_mask_1_T_8) connect bank_mask_1[1], _bank_mask_1_T_9 node _f3_mask_5_T = bits(f3.io.deq.bits.mask, 5, 5) node _f3_mask_5_T_1 = and(f3.io.deq.valid, _f3_mask_5_T) node _f3_mask_5_T_2 = and(_f3_mask_5_T_1, valid_5) node _f3_mask_5_T_3 = eq(_T_48, UInt<1>(0h0)) node _f3_mask_5_T_4 = and(_f3_mask_5_T_2, _f3_mask_5_T_3) connect f3_mask[5], _f3_mask_5_T_4 node _f3_targs_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h3)) node _f3_targs_5_T_1 = mux(_f3_targs_5_T, f3_bpd_resp.io.deq.bits.preds[5].predicted_pc.bits, brsigs_5.target) connect f3_targs[5], _f3_targs_5_T_1 node _f3_btb_mispredicts_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_5_T_1 = and(_f3_btb_mispredicts_5_T, valid_5) node _f3_btb_mispredicts_5_T_2 = and(_f3_btb_mispredicts_5_T_1, f3_bpd_resp.io.deq.bits.preds[5].predicted_pc.valid) node _f3_btb_mispredicts_5_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[5].predicted_pc.bits, brsigs_5.target) node _f3_btb_mispredicts_5_T_4 = and(_f3_btb_mispredicts_5_T_2, _f3_btb_mispredicts_5_T_3) connect f3_btb_mispredicts[5], _f3_btb_mispredicts_5_T_4 node _f3_npc_plus4_mask_5_T = eq(f3_is_rvc[5], UInt<1>(0h0)) connect f3_npc_plus4_mask[5], _f3_npc_plus4_mask_5_T node _offset_from_aligned_pc_T_25 = add(UInt<7>(0ha), brsigs_5.sfb_offset.bits) node _offset_from_aligned_pc_T_26 = tail(_offset_from_aligned_pc_T_25, 1) node _offset_from_aligned_pc_T_27 = and(_T_43, UInt<1>(0h0)) node _offset_from_aligned_pc_T_28 = mux(_offset_from_aligned_pc_T_27, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_29 = sub(_offset_from_aligned_pc_T_26, _offset_from_aligned_pc_T_28) node offset_from_aligned_pc_5 = tail(_offset_from_aligned_pc_T_29, 1) wire lower_mask_5 : UInt<16> wire upper_mask_5 : UInt<16> node _lower_mask_T_5 = dshl(UInt<1>(0h1), UInt<3>(0h5)) connect lower_mask_5, _lower_mask_T_5 node _upper_mask_T_20 = bits(offset_from_aligned_pc_5, 5, 1) node _upper_mask_T_21 = dshl(UInt<1>(0h1), _upper_mask_T_20) node _upper_mask_T_22 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_23 = dshl(_upper_mask_T_21, _upper_mask_T_22) connect upper_mask_5, _upper_mask_T_23 node _f3_fetch_bundle_sfbs_5_T = and(f3_mask[5], brsigs_5.sfb_offset.valid) node _f3_fetch_bundle_sfbs_5_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_5_T_2 = leq(offset_from_aligned_pc_5, _f3_fetch_bundle_sfbs_5_T_1) node _f3_fetch_bundle_sfbs_5_T_3 = and(_f3_fetch_bundle_sfbs_5_T, _f3_fetch_bundle_sfbs_5_T_2) connect f3_fetch_bundle.sfbs[5], _f3_fetch_bundle_sfbs_5_T_3 node _f3_fetch_bundle_sfb_masks_5_T = dshr(lower_mask_5, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_5_T_1 = dshr(lower_mask_5, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_5_T_2 = dshr(lower_mask_5, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_5_T_3 = dshr(lower_mask_5, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_5_T_4 = dshr(lower_mask_5, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_5_T_5 = dshr(lower_mask_5, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_5_T_6 = dshr(lower_mask_5, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_5_T_7 = dshr(lower_mask_5, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_5_T_8 = dshr(lower_mask_5, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_5_T_9 = dshr(lower_mask_5, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_5_T_10 = dshr(lower_mask_5, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_5_T_11 = dshr(lower_mask_5, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_5_T_12 = dshr(lower_mask_5, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_5_T_13 = dshr(lower_mask_5, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_5_T_14 = dshr(lower_mask_5, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_5_T_15 = dshr(lower_mask_5, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_5_T_16 = or(_f3_fetch_bundle_sfb_masks_5_T, _f3_fetch_bundle_sfb_masks_5_T_1) node _f3_fetch_bundle_sfb_masks_5_T_17 = or(_f3_fetch_bundle_sfb_masks_5_T_16, _f3_fetch_bundle_sfb_masks_5_T_2) node _f3_fetch_bundle_sfb_masks_5_T_18 = or(_f3_fetch_bundle_sfb_masks_5_T_17, _f3_fetch_bundle_sfb_masks_5_T_3) node _f3_fetch_bundle_sfb_masks_5_T_19 = or(_f3_fetch_bundle_sfb_masks_5_T_18, _f3_fetch_bundle_sfb_masks_5_T_4) node _f3_fetch_bundle_sfb_masks_5_T_20 = or(_f3_fetch_bundle_sfb_masks_5_T_19, _f3_fetch_bundle_sfb_masks_5_T_5) node _f3_fetch_bundle_sfb_masks_5_T_21 = or(_f3_fetch_bundle_sfb_masks_5_T_20, _f3_fetch_bundle_sfb_masks_5_T_6) node _f3_fetch_bundle_sfb_masks_5_T_22 = or(_f3_fetch_bundle_sfb_masks_5_T_21, _f3_fetch_bundle_sfb_masks_5_T_7) node _f3_fetch_bundle_sfb_masks_5_T_23 = or(_f3_fetch_bundle_sfb_masks_5_T_22, _f3_fetch_bundle_sfb_masks_5_T_8) node _f3_fetch_bundle_sfb_masks_5_T_24 = or(_f3_fetch_bundle_sfb_masks_5_T_23, _f3_fetch_bundle_sfb_masks_5_T_9) node _f3_fetch_bundle_sfb_masks_5_T_25 = or(_f3_fetch_bundle_sfb_masks_5_T_24, _f3_fetch_bundle_sfb_masks_5_T_10) node _f3_fetch_bundle_sfb_masks_5_T_26 = or(_f3_fetch_bundle_sfb_masks_5_T_25, _f3_fetch_bundle_sfb_masks_5_T_11) node _f3_fetch_bundle_sfb_masks_5_T_27 = or(_f3_fetch_bundle_sfb_masks_5_T_26, _f3_fetch_bundle_sfb_masks_5_T_12) node _f3_fetch_bundle_sfb_masks_5_T_28 = or(_f3_fetch_bundle_sfb_masks_5_T_27, _f3_fetch_bundle_sfb_masks_5_T_13) node _f3_fetch_bundle_sfb_masks_5_T_29 = or(_f3_fetch_bundle_sfb_masks_5_T_28, _f3_fetch_bundle_sfb_masks_5_T_14) node _f3_fetch_bundle_sfb_masks_5_T_30 = or(_f3_fetch_bundle_sfb_masks_5_T_29, _f3_fetch_bundle_sfb_masks_5_T_15) node _f3_fetch_bundle_sfb_masks_5_T_31 = not(_f3_fetch_bundle_sfb_masks_5_T_30) node _f3_fetch_bundle_sfb_masks_5_T_32 = dshl(upper_mask_5, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_5_T_33 = bits(_f3_fetch_bundle_sfb_masks_5_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_34 = dshl(upper_mask_5, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_5_T_35 = bits(_f3_fetch_bundle_sfb_masks_5_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_36 = dshl(upper_mask_5, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_5_T_37 = bits(_f3_fetch_bundle_sfb_masks_5_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_38 = dshl(upper_mask_5, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_5_T_39 = bits(_f3_fetch_bundle_sfb_masks_5_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_40 = dshl(upper_mask_5, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_5_T_41 = bits(_f3_fetch_bundle_sfb_masks_5_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_42 = dshl(upper_mask_5, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_5_T_43 = bits(_f3_fetch_bundle_sfb_masks_5_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_44 = dshl(upper_mask_5, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_5_T_45 = bits(_f3_fetch_bundle_sfb_masks_5_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_46 = dshl(upper_mask_5, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_5_T_47 = bits(_f3_fetch_bundle_sfb_masks_5_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_48 = dshl(upper_mask_5, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_5_T_49 = bits(_f3_fetch_bundle_sfb_masks_5_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_50 = dshl(upper_mask_5, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_5_T_51 = bits(_f3_fetch_bundle_sfb_masks_5_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_52 = dshl(upper_mask_5, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_5_T_53 = bits(_f3_fetch_bundle_sfb_masks_5_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_54 = dshl(upper_mask_5, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_5_T_55 = bits(_f3_fetch_bundle_sfb_masks_5_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_56 = dshl(upper_mask_5, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_5_T_57 = bits(_f3_fetch_bundle_sfb_masks_5_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_58 = dshl(upper_mask_5, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_5_T_59 = bits(_f3_fetch_bundle_sfb_masks_5_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_60 = dshl(upper_mask_5, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_5_T_61 = bits(_f3_fetch_bundle_sfb_masks_5_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_62 = dshl(upper_mask_5, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_5_T_63 = bits(_f3_fetch_bundle_sfb_masks_5_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_5_T_64 = or(_f3_fetch_bundle_sfb_masks_5_T_33, _f3_fetch_bundle_sfb_masks_5_T_35) node _f3_fetch_bundle_sfb_masks_5_T_65 = or(_f3_fetch_bundle_sfb_masks_5_T_64, _f3_fetch_bundle_sfb_masks_5_T_37) node _f3_fetch_bundle_sfb_masks_5_T_66 = or(_f3_fetch_bundle_sfb_masks_5_T_65, _f3_fetch_bundle_sfb_masks_5_T_39) node _f3_fetch_bundle_sfb_masks_5_T_67 = or(_f3_fetch_bundle_sfb_masks_5_T_66, _f3_fetch_bundle_sfb_masks_5_T_41) node _f3_fetch_bundle_sfb_masks_5_T_68 = or(_f3_fetch_bundle_sfb_masks_5_T_67, _f3_fetch_bundle_sfb_masks_5_T_43) node _f3_fetch_bundle_sfb_masks_5_T_69 = or(_f3_fetch_bundle_sfb_masks_5_T_68, _f3_fetch_bundle_sfb_masks_5_T_45) node _f3_fetch_bundle_sfb_masks_5_T_70 = or(_f3_fetch_bundle_sfb_masks_5_T_69, _f3_fetch_bundle_sfb_masks_5_T_47) node _f3_fetch_bundle_sfb_masks_5_T_71 = or(_f3_fetch_bundle_sfb_masks_5_T_70, _f3_fetch_bundle_sfb_masks_5_T_49) node _f3_fetch_bundle_sfb_masks_5_T_72 = or(_f3_fetch_bundle_sfb_masks_5_T_71, _f3_fetch_bundle_sfb_masks_5_T_51) node _f3_fetch_bundle_sfb_masks_5_T_73 = or(_f3_fetch_bundle_sfb_masks_5_T_72, _f3_fetch_bundle_sfb_masks_5_T_53) node _f3_fetch_bundle_sfb_masks_5_T_74 = or(_f3_fetch_bundle_sfb_masks_5_T_73, _f3_fetch_bundle_sfb_masks_5_T_55) node _f3_fetch_bundle_sfb_masks_5_T_75 = or(_f3_fetch_bundle_sfb_masks_5_T_74, _f3_fetch_bundle_sfb_masks_5_T_57) node _f3_fetch_bundle_sfb_masks_5_T_76 = or(_f3_fetch_bundle_sfb_masks_5_T_75, _f3_fetch_bundle_sfb_masks_5_T_59) node _f3_fetch_bundle_sfb_masks_5_T_77 = or(_f3_fetch_bundle_sfb_masks_5_T_76, _f3_fetch_bundle_sfb_masks_5_T_61) node _f3_fetch_bundle_sfb_masks_5_T_78 = or(_f3_fetch_bundle_sfb_masks_5_T_77, _f3_fetch_bundle_sfb_masks_5_T_63) node _f3_fetch_bundle_sfb_masks_5_T_79 = not(_f3_fetch_bundle_sfb_masks_5_T_78) node _f3_fetch_bundle_sfb_masks_5_T_80 = and(_f3_fetch_bundle_sfb_masks_5_T_31, _f3_fetch_bundle_sfb_masks_5_T_79) connect f3_fetch_bundle.sfb_masks[5], _f3_fetch_bundle_sfb_masks_5_T_80 node _f3_fetch_bundle_shadowable_mask_5_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_5_T_1 = or(_f3_fetch_bundle_shadowable_mask_5_T, bpu_5.io.debug_if) node _f3_fetch_bundle_shadowable_mask_5_T_2 = or(_f3_fetch_bundle_shadowable_mask_5_T_1, bpu_5.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_5_T_3 = eq(_f3_fetch_bundle_shadowable_mask_5_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_5_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_5_T_5 = and(_f3_fetch_bundle_shadowable_mask_5_T_3, _f3_fetch_bundle_shadowable_mask_5_T_4) node _f3_fetch_bundle_shadowable_mask_5_T_6 = eq(f3_mask[5], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_5_T_7 = or(brsigs_5.shadowable, _f3_fetch_bundle_shadowable_mask_5_T_6) node _f3_fetch_bundle_shadowable_mask_5_T_8 = and(_f3_fetch_bundle_shadowable_mask_5_T_5, _f3_fetch_bundle_shadowable_mask_5_T_7) connect f3_fetch_bundle.shadowable_mask[5], _f3_fetch_bundle_shadowable_mask_5_T_8 connect f3_fetch_bundle.sfb_dests[5], offset_from_aligned_pc_5 node _f3_redirects_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h2)) node _f3_redirects_5_T_1 = eq(brsigs_5.cfi_type, UInt<3>(0h3)) node _f3_redirects_5_T_2 = or(_f3_redirects_5_T, _f3_redirects_5_T_1) node _f3_redirects_5_T_3 = eq(brsigs_5.cfi_type, UInt<3>(0h1)) node _f3_redirects_5_T_4 = and(_f3_redirects_5_T_3, f3_bpd_resp.io.deq.bits.preds[5].taken) node _f3_redirects_5_T_5 = and(_f3_redirects_5_T_4, UInt<1>(0h1)) node _f3_redirects_5_T_6 = or(_f3_redirects_5_T_2, _f3_redirects_5_T_5) node _f3_redirects_5_T_7 = and(f3_mask[5], _f3_redirects_5_T_6) connect f3_redirects[5], _f3_redirects_5_T_7 node _f3_br_mask_5_T = eq(brsigs_5.cfi_type, UInt<3>(0h1)) node _f3_br_mask_5_T_1 = and(f3_mask[5], _f3_br_mask_5_T) connect f3_br_mask[5], _f3_br_mask_5_T_1 connect f3_cfi_types[5], brsigs_5.cfi_type connect f3_call_mask[5], brsigs_5.is_call connect f3_ret_mask[5], brsigs_5.is_ret connect f3_fetch_bundle.bp_debug_if_oh[5], bpu_5.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[5], bpu_5.io.xcpt_if node _T_49 = or(_T_48, f3_redirects[5]) wire valid_6 : UInt<1> inst bpu_6 of BreakpointUnit_17 connect bpu_6.clock, clock connect bpu_6.reset, reset connect bpu_6.io.status.uie, io.cpu.status.uie connect bpu_6.io.status.sie, io.cpu.status.sie connect bpu_6.io.status.hie, io.cpu.status.hie connect bpu_6.io.status.mie, io.cpu.status.mie connect bpu_6.io.status.upie, io.cpu.status.upie connect bpu_6.io.status.spie, io.cpu.status.spie connect bpu_6.io.status.ube, io.cpu.status.ube connect bpu_6.io.status.mpie, io.cpu.status.mpie connect bpu_6.io.status.spp, io.cpu.status.spp connect bpu_6.io.status.vs, io.cpu.status.vs connect bpu_6.io.status.mpp, io.cpu.status.mpp connect bpu_6.io.status.fs, io.cpu.status.fs connect bpu_6.io.status.xs, io.cpu.status.xs connect bpu_6.io.status.mprv, io.cpu.status.mprv connect bpu_6.io.status.sum, io.cpu.status.sum connect bpu_6.io.status.mxr, io.cpu.status.mxr connect bpu_6.io.status.tvm, io.cpu.status.tvm connect bpu_6.io.status.tw, io.cpu.status.tw connect bpu_6.io.status.tsr, io.cpu.status.tsr connect bpu_6.io.status.zero1, io.cpu.status.zero1 connect bpu_6.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_6.io.status.uxl, io.cpu.status.uxl connect bpu_6.io.status.sxl, io.cpu.status.sxl connect bpu_6.io.status.sbe, io.cpu.status.sbe connect bpu_6.io.status.mbe, io.cpu.status.mbe connect bpu_6.io.status.gva, io.cpu.status.gva connect bpu_6.io.status.mpv, io.cpu.status.mpv connect bpu_6.io.status.zero2, io.cpu.status.zero2 connect bpu_6.io.status.sd, io.cpu.status.sd connect bpu_6.io.status.v, io.cpu.status.v connect bpu_6.io.status.prv, io.cpu.status.prv connect bpu_6.io.status.dv, io.cpu.status.dv connect bpu_6.io.status.dprv, io.cpu.status.dprv connect bpu_6.io.status.isa, io.cpu.status.isa connect bpu_6.io.status.wfi, io.cpu.status.wfi connect bpu_6.io.status.cease, io.cpu.status.cease connect bpu_6.io.status.debug, io.cpu.status.debug invalidate bpu_6.io.ea connect bpu_6.io.mcontext, io.cpu.mcontext connect bpu_6.io.scontext, io.cpu.scontext wire brsigs_6 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_4 : UInt<32> inst exp_inst_rvc_exp_4 of RVCExpander_22 connect exp_inst_rvc_exp_4.clock, clock connect exp_inst_rvc_exp_4.reset, reset connect exp_inst_rvc_exp_4.io.in, inst_4 node exp_inst_4 = mux(exp_inst_rvc_exp_4.io.rvc, exp_inst_rvc_exp_4.io.out.bits, inst_4) node _pc_T_4 = add(f3_aligned_pc, UInt<4>(0hc)) node pc_4 = tail(_pc_T_4, 1) inst bpd_decoder_4 of BranchDecode_20 connect bpd_decoder_4.clock, clock connect bpd_decoder_4.reset, reset connect bpd_decoder_4.io.inst, exp_inst_4 connect bpd_decoder_4.io.pc, pc_4 connect bank_insts_1[2], inst_4 connect f3_fetch_bundle.insts[6], inst_4 connect f3_fetch_bundle.exp_insts[6], exp_inst_4 connect bpu_6.io.pc, pc_4 connect brsigs_6.shadowable, bpd_decoder_4.io.out.shadowable connect brsigs_6.sfb_offset, bpd_decoder_4.io.out.sfb_offset connect brsigs_6.cfi_type, bpd_decoder_4.io.out.cfi_type connect brsigs_6.target, bpd_decoder_4.io.out.target connect brsigs_6.is_call, bpd_decoder_4.io.out.is_call connect brsigs_6.is_ret, bpd_decoder_4.io.out.is_ret node _inst_T_5 = bits(bank_data_1, 63, 32) connect inst_4, _inst_T_5 node _valid_T_26 = bits(bank_insts_1[1], 1, 0) node _valid_T_27 = neq(_valid_T_26, UInt<2>(0h3)) node _valid_T_28 = eq(_valid_T_27, UInt<1>(0h0)) node _valid_T_29 = and(bank_mask_1[1], _valid_T_28) node _valid_T_30 = eq(_valid_T_29, UInt<1>(0h0)) connect valid_6, _valid_T_30 node _f3_is_rvc_6_T = bits(bank_insts_1[2], 1, 0) node _f3_is_rvc_6_T_1 = neq(_f3_is_rvc_6_T, UInt<2>(0h3)) connect f3_is_rvc[6], _f3_is_rvc_6_T_1 node _bank_mask_2_T_5 = bits(f3.io.deq.bits.mask, 6, 6) node _bank_mask_2_T_6 = and(f3.io.deq.valid, _bank_mask_2_T_5) node _bank_mask_2_T_7 = and(_bank_mask_2_T_6, valid_6) node _bank_mask_2_T_8 = eq(_T_49, UInt<1>(0h0)) node _bank_mask_2_T_9 = and(_bank_mask_2_T_7, _bank_mask_2_T_8) connect bank_mask_1[2], _bank_mask_2_T_9 node _f3_mask_6_T = bits(f3.io.deq.bits.mask, 6, 6) node _f3_mask_6_T_1 = and(f3.io.deq.valid, _f3_mask_6_T) node _f3_mask_6_T_2 = and(_f3_mask_6_T_1, valid_6) node _f3_mask_6_T_3 = eq(_T_49, UInt<1>(0h0)) node _f3_mask_6_T_4 = and(_f3_mask_6_T_2, _f3_mask_6_T_3) connect f3_mask[6], _f3_mask_6_T_4 node _f3_targs_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h3)) node _f3_targs_6_T_1 = mux(_f3_targs_6_T, f3_bpd_resp.io.deq.bits.preds[6].predicted_pc.bits, brsigs_6.target) connect f3_targs[6], _f3_targs_6_T_1 node _f3_btb_mispredicts_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_6_T_1 = and(_f3_btb_mispredicts_6_T, valid_6) node _f3_btb_mispredicts_6_T_2 = and(_f3_btb_mispredicts_6_T_1, f3_bpd_resp.io.deq.bits.preds[6].predicted_pc.valid) node _f3_btb_mispredicts_6_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[6].predicted_pc.bits, brsigs_6.target) node _f3_btb_mispredicts_6_T_4 = and(_f3_btb_mispredicts_6_T_2, _f3_btb_mispredicts_6_T_3) connect f3_btb_mispredicts[6], _f3_btb_mispredicts_6_T_4 node _f3_npc_plus4_mask_6_T = eq(f3_is_rvc[6], UInt<1>(0h0)) connect f3_npc_plus4_mask[6], _f3_npc_plus4_mask_6_T node _offset_from_aligned_pc_T_30 = add(UInt<7>(0hc), brsigs_6.sfb_offset.bits) node _offset_from_aligned_pc_T_31 = tail(_offset_from_aligned_pc_T_30, 1) node _offset_from_aligned_pc_T_32 = and(_T_43, UInt<1>(0h0)) node _offset_from_aligned_pc_T_33 = mux(_offset_from_aligned_pc_T_32, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_34 = sub(_offset_from_aligned_pc_T_31, _offset_from_aligned_pc_T_33) node offset_from_aligned_pc_6 = tail(_offset_from_aligned_pc_T_34, 1) wire lower_mask_6 : UInt<16> wire upper_mask_6 : UInt<16> node _lower_mask_T_6 = dshl(UInt<1>(0h1), UInt<3>(0h6)) connect lower_mask_6, _lower_mask_T_6 node _upper_mask_T_24 = bits(offset_from_aligned_pc_6, 5, 1) node _upper_mask_T_25 = dshl(UInt<1>(0h1), _upper_mask_T_24) node _upper_mask_T_26 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_27 = dshl(_upper_mask_T_25, _upper_mask_T_26) connect upper_mask_6, _upper_mask_T_27 node _f3_fetch_bundle_sfbs_6_T = and(f3_mask[6], brsigs_6.sfb_offset.valid) node _f3_fetch_bundle_sfbs_6_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_6_T_2 = leq(offset_from_aligned_pc_6, _f3_fetch_bundle_sfbs_6_T_1) node _f3_fetch_bundle_sfbs_6_T_3 = and(_f3_fetch_bundle_sfbs_6_T, _f3_fetch_bundle_sfbs_6_T_2) connect f3_fetch_bundle.sfbs[6], _f3_fetch_bundle_sfbs_6_T_3 node _f3_fetch_bundle_sfb_masks_6_T = dshr(lower_mask_6, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_6_T_1 = dshr(lower_mask_6, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_6_T_2 = dshr(lower_mask_6, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_6_T_3 = dshr(lower_mask_6, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_6_T_4 = dshr(lower_mask_6, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_6_T_5 = dshr(lower_mask_6, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_6_T_6 = dshr(lower_mask_6, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_6_T_7 = dshr(lower_mask_6, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_6_T_8 = dshr(lower_mask_6, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_6_T_9 = dshr(lower_mask_6, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_6_T_10 = dshr(lower_mask_6, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_6_T_11 = dshr(lower_mask_6, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_6_T_12 = dshr(lower_mask_6, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_6_T_13 = dshr(lower_mask_6, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_6_T_14 = dshr(lower_mask_6, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_6_T_15 = dshr(lower_mask_6, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_6_T_16 = or(_f3_fetch_bundle_sfb_masks_6_T, _f3_fetch_bundle_sfb_masks_6_T_1) node _f3_fetch_bundle_sfb_masks_6_T_17 = or(_f3_fetch_bundle_sfb_masks_6_T_16, _f3_fetch_bundle_sfb_masks_6_T_2) node _f3_fetch_bundle_sfb_masks_6_T_18 = or(_f3_fetch_bundle_sfb_masks_6_T_17, _f3_fetch_bundle_sfb_masks_6_T_3) node _f3_fetch_bundle_sfb_masks_6_T_19 = or(_f3_fetch_bundle_sfb_masks_6_T_18, _f3_fetch_bundle_sfb_masks_6_T_4) node _f3_fetch_bundle_sfb_masks_6_T_20 = or(_f3_fetch_bundle_sfb_masks_6_T_19, _f3_fetch_bundle_sfb_masks_6_T_5) node _f3_fetch_bundle_sfb_masks_6_T_21 = or(_f3_fetch_bundle_sfb_masks_6_T_20, _f3_fetch_bundle_sfb_masks_6_T_6) node _f3_fetch_bundle_sfb_masks_6_T_22 = or(_f3_fetch_bundle_sfb_masks_6_T_21, _f3_fetch_bundle_sfb_masks_6_T_7) node _f3_fetch_bundle_sfb_masks_6_T_23 = or(_f3_fetch_bundle_sfb_masks_6_T_22, _f3_fetch_bundle_sfb_masks_6_T_8) node _f3_fetch_bundle_sfb_masks_6_T_24 = or(_f3_fetch_bundle_sfb_masks_6_T_23, _f3_fetch_bundle_sfb_masks_6_T_9) node _f3_fetch_bundle_sfb_masks_6_T_25 = or(_f3_fetch_bundle_sfb_masks_6_T_24, _f3_fetch_bundle_sfb_masks_6_T_10) node _f3_fetch_bundle_sfb_masks_6_T_26 = or(_f3_fetch_bundle_sfb_masks_6_T_25, _f3_fetch_bundle_sfb_masks_6_T_11) node _f3_fetch_bundle_sfb_masks_6_T_27 = or(_f3_fetch_bundle_sfb_masks_6_T_26, _f3_fetch_bundle_sfb_masks_6_T_12) node _f3_fetch_bundle_sfb_masks_6_T_28 = or(_f3_fetch_bundle_sfb_masks_6_T_27, _f3_fetch_bundle_sfb_masks_6_T_13) node _f3_fetch_bundle_sfb_masks_6_T_29 = or(_f3_fetch_bundle_sfb_masks_6_T_28, _f3_fetch_bundle_sfb_masks_6_T_14) node _f3_fetch_bundle_sfb_masks_6_T_30 = or(_f3_fetch_bundle_sfb_masks_6_T_29, _f3_fetch_bundle_sfb_masks_6_T_15) node _f3_fetch_bundle_sfb_masks_6_T_31 = not(_f3_fetch_bundle_sfb_masks_6_T_30) node _f3_fetch_bundle_sfb_masks_6_T_32 = dshl(upper_mask_6, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_6_T_33 = bits(_f3_fetch_bundle_sfb_masks_6_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_34 = dshl(upper_mask_6, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_6_T_35 = bits(_f3_fetch_bundle_sfb_masks_6_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_36 = dshl(upper_mask_6, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_6_T_37 = bits(_f3_fetch_bundle_sfb_masks_6_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_38 = dshl(upper_mask_6, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_6_T_39 = bits(_f3_fetch_bundle_sfb_masks_6_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_40 = dshl(upper_mask_6, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_6_T_41 = bits(_f3_fetch_bundle_sfb_masks_6_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_42 = dshl(upper_mask_6, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_6_T_43 = bits(_f3_fetch_bundle_sfb_masks_6_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_44 = dshl(upper_mask_6, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_6_T_45 = bits(_f3_fetch_bundle_sfb_masks_6_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_46 = dshl(upper_mask_6, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_6_T_47 = bits(_f3_fetch_bundle_sfb_masks_6_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_48 = dshl(upper_mask_6, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_6_T_49 = bits(_f3_fetch_bundle_sfb_masks_6_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_50 = dshl(upper_mask_6, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_6_T_51 = bits(_f3_fetch_bundle_sfb_masks_6_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_52 = dshl(upper_mask_6, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_6_T_53 = bits(_f3_fetch_bundle_sfb_masks_6_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_54 = dshl(upper_mask_6, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_6_T_55 = bits(_f3_fetch_bundle_sfb_masks_6_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_56 = dshl(upper_mask_6, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_6_T_57 = bits(_f3_fetch_bundle_sfb_masks_6_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_58 = dshl(upper_mask_6, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_6_T_59 = bits(_f3_fetch_bundle_sfb_masks_6_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_60 = dshl(upper_mask_6, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_6_T_61 = bits(_f3_fetch_bundle_sfb_masks_6_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_62 = dshl(upper_mask_6, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_6_T_63 = bits(_f3_fetch_bundle_sfb_masks_6_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_6_T_64 = or(_f3_fetch_bundle_sfb_masks_6_T_33, _f3_fetch_bundle_sfb_masks_6_T_35) node _f3_fetch_bundle_sfb_masks_6_T_65 = or(_f3_fetch_bundle_sfb_masks_6_T_64, _f3_fetch_bundle_sfb_masks_6_T_37) node _f3_fetch_bundle_sfb_masks_6_T_66 = or(_f3_fetch_bundle_sfb_masks_6_T_65, _f3_fetch_bundle_sfb_masks_6_T_39) node _f3_fetch_bundle_sfb_masks_6_T_67 = or(_f3_fetch_bundle_sfb_masks_6_T_66, _f3_fetch_bundle_sfb_masks_6_T_41) node _f3_fetch_bundle_sfb_masks_6_T_68 = or(_f3_fetch_bundle_sfb_masks_6_T_67, _f3_fetch_bundle_sfb_masks_6_T_43) node _f3_fetch_bundle_sfb_masks_6_T_69 = or(_f3_fetch_bundle_sfb_masks_6_T_68, _f3_fetch_bundle_sfb_masks_6_T_45) node _f3_fetch_bundle_sfb_masks_6_T_70 = or(_f3_fetch_bundle_sfb_masks_6_T_69, _f3_fetch_bundle_sfb_masks_6_T_47) node _f3_fetch_bundle_sfb_masks_6_T_71 = or(_f3_fetch_bundle_sfb_masks_6_T_70, _f3_fetch_bundle_sfb_masks_6_T_49) node _f3_fetch_bundle_sfb_masks_6_T_72 = or(_f3_fetch_bundle_sfb_masks_6_T_71, _f3_fetch_bundle_sfb_masks_6_T_51) node _f3_fetch_bundle_sfb_masks_6_T_73 = or(_f3_fetch_bundle_sfb_masks_6_T_72, _f3_fetch_bundle_sfb_masks_6_T_53) node _f3_fetch_bundle_sfb_masks_6_T_74 = or(_f3_fetch_bundle_sfb_masks_6_T_73, _f3_fetch_bundle_sfb_masks_6_T_55) node _f3_fetch_bundle_sfb_masks_6_T_75 = or(_f3_fetch_bundle_sfb_masks_6_T_74, _f3_fetch_bundle_sfb_masks_6_T_57) node _f3_fetch_bundle_sfb_masks_6_T_76 = or(_f3_fetch_bundle_sfb_masks_6_T_75, _f3_fetch_bundle_sfb_masks_6_T_59) node _f3_fetch_bundle_sfb_masks_6_T_77 = or(_f3_fetch_bundle_sfb_masks_6_T_76, _f3_fetch_bundle_sfb_masks_6_T_61) node _f3_fetch_bundle_sfb_masks_6_T_78 = or(_f3_fetch_bundle_sfb_masks_6_T_77, _f3_fetch_bundle_sfb_masks_6_T_63) node _f3_fetch_bundle_sfb_masks_6_T_79 = not(_f3_fetch_bundle_sfb_masks_6_T_78) node _f3_fetch_bundle_sfb_masks_6_T_80 = and(_f3_fetch_bundle_sfb_masks_6_T_31, _f3_fetch_bundle_sfb_masks_6_T_79) connect f3_fetch_bundle.sfb_masks[6], _f3_fetch_bundle_sfb_masks_6_T_80 node _f3_fetch_bundle_shadowable_mask_6_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_6_T_1 = or(_f3_fetch_bundle_shadowable_mask_6_T, bpu_6.io.debug_if) node _f3_fetch_bundle_shadowable_mask_6_T_2 = or(_f3_fetch_bundle_shadowable_mask_6_T_1, bpu_6.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_6_T_3 = eq(_f3_fetch_bundle_shadowable_mask_6_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_6_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_6_T_5 = and(_f3_fetch_bundle_shadowable_mask_6_T_3, _f3_fetch_bundle_shadowable_mask_6_T_4) node _f3_fetch_bundle_shadowable_mask_6_T_6 = eq(f3_mask[6], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_6_T_7 = or(brsigs_6.shadowable, _f3_fetch_bundle_shadowable_mask_6_T_6) node _f3_fetch_bundle_shadowable_mask_6_T_8 = and(_f3_fetch_bundle_shadowable_mask_6_T_5, _f3_fetch_bundle_shadowable_mask_6_T_7) connect f3_fetch_bundle.shadowable_mask[6], _f3_fetch_bundle_shadowable_mask_6_T_8 connect f3_fetch_bundle.sfb_dests[6], offset_from_aligned_pc_6 node _f3_redirects_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h2)) node _f3_redirects_6_T_1 = eq(brsigs_6.cfi_type, UInt<3>(0h3)) node _f3_redirects_6_T_2 = or(_f3_redirects_6_T, _f3_redirects_6_T_1) node _f3_redirects_6_T_3 = eq(brsigs_6.cfi_type, UInt<3>(0h1)) node _f3_redirects_6_T_4 = and(_f3_redirects_6_T_3, f3_bpd_resp.io.deq.bits.preds[6].taken) node _f3_redirects_6_T_5 = and(_f3_redirects_6_T_4, UInt<1>(0h1)) node _f3_redirects_6_T_6 = or(_f3_redirects_6_T_2, _f3_redirects_6_T_5) node _f3_redirects_6_T_7 = and(f3_mask[6], _f3_redirects_6_T_6) connect f3_redirects[6], _f3_redirects_6_T_7 node _f3_br_mask_6_T = eq(brsigs_6.cfi_type, UInt<3>(0h1)) node _f3_br_mask_6_T_1 = and(f3_mask[6], _f3_br_mask_6_T) connect f3_br_mask[6], _f3_br_mask_6_T_1 connect f3_cfi_types[6], brsigs_6.cfi_type connect f3_call_mask[6], brsigs_6.is_call connect f3_ret_mask[6], brsigs_6.is_ret connect f3_fetch_bundle.bp_debug_if_oh[6], bpu_6.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[6], bpu_6.io.xcpt_if node _T_50 = or(_T_49, f3_redirects[6]) wire valid_7 : UInt<1> inst bpu_7 of BreakpointUnit_18 connect bpu_7.clock, clock connect bpu_7.reset, reset connect bpu_7.io.status.uie, io.cpu.status.uie connect bpu_7.io.status.sie, io.cpu.status.sie connect bpu_7.io.status.hie, io.cpu.status.hie connect bpu_7.io.status.mie, io.cpu.status.mie connect bpu_7.io.status.upie, io.cpu.status.upie connect bpu_7.io.status.spie, io.cpu.status.spie connect bpu_7.io.status.ube, io.cpu.status.ube connect bpu_7.io.status.mpie, io.cpu.status.mpie connect bpu_7.io.status.spp, io.cpu.status.spp connect bpu_7.io.status.vs, io.cpu.status.vs connect bpu_7.io.status.mpp, io.cpu.status.mpp connect bpu_7.io.status.fs, io.cpu.status.fs connect bpu_7.io.status.xs, io.cpu.status.xs connect bpu_7.io.status.mprv, io.cpu.status.mprv connect bpu_7.io.status.sum, io.cpu.status.sum connect bpu_7.io.status.mxr, io.cpu.status.mxr connect bpu_7.io.status.tvm, io.cpu.status.tvm connect bpu_7.io.status.tw, io.cpu.status.tw connect bpu_7.io.status.tsr, io.cpu.status.tsr connect bpu_7.io.status.zero1, io.cpu.status.zero1 connect bpu_7.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_7.io.status.uxl, io.cpu.status.uxl connect bpu_7.io.status.sxl, io.cpu.status.sxl connect bpu_7.io.status.sbe, io.cpu.status.sbe connect bpu_7.io.status.mbe, io.cpu.status.mbe connect bpu_7.io.status.gva, io.cpu.status.gva connect bpu_7.io.status.mpv, io.cpu.status.mpv connect bpu_7.io.status.zero2, io.cpu.status.zero2 connect bpu_7.io.status.sd, io.cpu.status.sd connect bpu_7.io.status.v, io.cpu.status.v connect bpu_7.io.status.prv, io.cpu.status.prv connect bpu_7.io.status.dv, io.cpu.status.dv connect bpu_7.io.status.dprv, io.cpu.status.dprv connect bpu_7.io.status.isa, io.cpu.status.isa connect bpu_7.io.status.wfi, io.cpu.status.wfi connect bpu_7.io.status.cease, io.cpu.status.cease connect bpu_7.io.status.debug, io.cpu.status.debug invalidate bpu_7.io.ea connect bpu_7.io.mcontext, io.cpu.mcontext connect bpu_7.io.scontext, io.cpu.scontext wire brsigs_7 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_5 : UInt<32> inst exp_inst_rvc_exp_5 of RVCExpander_23 connect exp_inst_rvc_exp_5.clock, clock connect exp_inst_rvc_exp_5.reset, reset connect exp_inst_rvc_exp_5.io.in, inst_5 node exp_inst_5 = mux(exp_inst_rvc_exp_5.io.rvc, exp_inst_rvc_exp_5.io.out.bits, inst_5) node _pc_T_5 = add(f3_aligned_pc, UInt<4>(0he)) node pc_5 = tail(_pc_T_5, 1) inst bpd_decoder_5 of BranchDecode_21 connect bpd_decoder_5.clock, clock connect bpd_decoder_5.reset, reset connect bpd_decoder_5.io.inst, exp_inst_5 connect bpd_decoder_5.io.pc, pc_5 connect bank_insts_1[3], inst_5 connect f3_fetch_bundle.insts[7], inst_5 connect f3_fetch_bundle.exp_insts[7], exp_inst_5 connect bpu_7.io.pc, pc_5 connect brsigs_7.shadowable, bpd_decoder_5.io.out.shadowable connect brsigs_7.sfb_offset, bpd_decoder_5.io.out.sfb_offset connect brsigs_7.cfi_type, bpd_decoder_5.io.out.cfi_type connect brsigs_7.target, bpd_decoder_5.io.out.target connect brsigs_7.is_call, bpd_decoder_5.io.out.is_call connect brsigs_7.is_ret, bpd_decoder_5.io.out.is_ret node _inst_T_6 = bits(bank_data_1, 63, 48) node _inst_T_7 = cat(UInt<16>(0h0), _inst_T_6) connect inst_5, _inst_T_7 node _valid_T_31 = bits(bank_insts_1[2], 1, 0) node _valid_T_32 = neq(_valid_T_31, UInt<2>(0h3)) node _valid_T_33 = eq(_valid_T_32, UInt<1>(0h0)) node _valid_T_34 = and(bank_mask_1[2], _valid_T_33) node _valid_T_35 = bits(inst_5, 1, 0) node _valid_T_36 = neq(_valid_T_35, UInt<2>(0h3)) node _valid_T_37 = eq(_valid_T_36, UInt<1>(0h0)) node _valid_T_38 = or(_valid_T_34, _valid_T_37) node _valid_T_39 = eq(_valid_T_38, UInt<1>(0h0)) connect valid_7, _valid_T_39 node _f3_is_rvc_7_T = bits(bank_insts_1[3], 1, 0) node _f3_is_rvc_7_T_1 = neq(_f3_is_rvc_7_T, UInt<2>(0h3)) connect f3_is_rvc[7], _f3_is_rvc_7_T_1 node _bank_mask_3_T_5 = bits(f3.io.deq.bits.mask, 7, 7) node _bank_mask_3_T_6 = and(f3.io.deq.valid, _bank_mask_3_T_5) node _bank_mask_3_T_7 = and(_bank_mask_3_T_6, valid_7) node _bank_mask_3_T_8 = eq(_T_50, UInt<1>(0h0)) node _bank_mask_3_T_9 = and(_bank_mask_3_T_7, _bank_mask_3_T_8) connect bank_mask_1[3], _bank_mask_3_T_9 node _f3_mask_7_T = bits(f3.io.deq.bits.mask, 7, 7) node _f3_mask_7_T_1 = and(f3.io.deq.valid, _f3_mask_7_T) node _f3_mask_7_T_2 = and(_f3_mask_7_T_1, valid_7) node _f3_mask_7_T_3 = eq(_T_50, UInt<1>(0h0)) node _f3_mask_7_T_4 = and(_f3_mask_7_T_2, _f3_mask_7_T_3) connect f3_mask[7], _f3_mask_7_T_4 node _f3_targs_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h3)) node _f3_targs_7_T_1 = mux(_f3_targs_7_T, f3_bpd_resp.io.deq.bits.preds[7].predicted_pc.bits, brsigs_7.target) connect f3_targs[7], _f3_targs_7_T_1 node _f3_btb_mispredicts_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_7_T_1 = and(_f3_btb_mispredicts_7_T, valid_7) node _f3_btb_mispredicts_7_T_2 = and(_f3_btb_mispredicts_7_T_1, f3_bpd_resp.io.deq.bits.preds[7].predicted_pc.valid) node _f3_btb_mispredicts_7_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[7].predicted_pc.bits, brsigs_7.target) node _f3_btb_mispredicts_7_T_4 = and(_f3_btb_mispredicts_7_T_2, _f3_btb_mispredicts_7_T_3) connect f3_btb_mispredicts[7], _f3_btb_mispredicts_7_T_4 node _f3_npc_plus4_mask_7_T = eq(f3_is_rvc[7], UInt<1>(0h0)) connect f3_npc_plus4_mask[7], _f3_npc_plus4_mask_7_T node _offset_from_aligned_pc_T_35 = add(UInt<7>(0he), brsigs_7.sfb_offset.bits) node _offset_from_aligned_pc_T_36 = tail(_offset_from_aligned_pc_T_35, 1) node _offset_from_aligned_pc_T_37 = and(_T_43, UInt<1>(0h0)) node _offset_from_aligned_pc_T_38 = mux(_offset_from_aligned_pc_T_37, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_39 = sub(_offset_from_aligned_pc_T_36, _offset_from_aligned_pc_T_38) node offset_from_aligned_pc_7 = tail(_offset_from_aligned_pc_T_39, 1) wire lower_mask_7 : UInt<16> wire upper_mask_7 : UInt<16> node _lower_mask_T_7 = dshl(UInt<1>(0h1), UInt<3>(0h7)) connect lower_mask_7, _lower_mask_T_7 node _upper_mask_T_28 = bits(offset_from_aligned_pc_7, 5, 1) node _upper_mask_T_29 = dshl(UInt<1>(0h1), _upper_mask_T_28) node _upper_mask_T_30 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_31 = dshl(_upper_mask_T_29, _upper_mask_T_30) connect upper_mask_7, _upper_mask_T_31 node _f3_fetch_bundle_sfbs_7_T = and(f3_mask[7], brsigs_7.sfb_offset.valid) node _f3_fetch_bundle_sfbs_7_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h18), UInt<6>(0h20)) node _f3_fetch_bundle_sfbs_7_T_2 = leq(offset_from_aligned_pc_7, _f3_fetch_bundle_sfbs_7_T_1) node _f3_fetch_bundle_sfbs_7_T_3 = and(_f3_fetch_bundle_sfbs_7_T, _f3_fetch_bundle_sfbs_7_T_2) connect f3_fetch_bundle.sfbs[7], _f3_fetch_bundle_sfbs_7_T_3 node _f3_fetch_bundle_sfb_masks_7_T = dshr(lower_mask_7, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_7_T_1 = dshr(lower_mask_7, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_7_T_2 = dshr(lower_mask_7, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_7_T_3 = dshr(lower_mask_7, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_7_T_4 = dshr(lower_mask_7, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_7_T_5 = dshr(lower_mask_7, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_7_T_6 = dshr(lower_mask_7, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_7_T_7 = dshr(lower_mask_7, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_7_T_8 = dshr(lower_mask_7, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_7_T_9 = dshr(lower_mask_7, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_7_T_10 = dshr(lower_mask_7, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_7_T_11 = dshr(lower_mask_7, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_7_T_12 = dshr(lower_mask_7, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_7_T_13 = dshr(lower_mask_7, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_7_T_14 = dshr(lower_mask_7, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_7_T_15 = dshr(lower_mask_7, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_7_T_16 = or(_f3_fetch_bundle_sfb_masks_7_T, _f3_fetch_bundle_sfb_masks_7_T_1) node _f3_fetch_bundle_sfb_masks_7_T_17 = or(_f3_fetch_bundle_sfb_masks_7_T_16, _f3_fetch_bundle_sfb_masks_7_T_2) node _f3_fetch_bundle_sfb_masks_7_T_18 = or(_f3_fetch_bundle_sfb_masks_7_T_17, _f3_fetch_bundle_sfb_masks_7_T_3) node _f3_fetch_bundle_sfb_masks_7_T_19 = or(_f3_fetch_bundle_sfb_masks_7_T_18, _f3_fetch_bundle_sfb_masks_7_T_4) node _f3_fetch_bundle_sfb_masks_7_T_20 = or(_f3_fetch_bundle_sfb_masks_7_T_19, _f3_fetch_bundle_sfb_masks_7_T_5) node _f3_fetch_bundle_sfb_masks_7_T_21 = or(_f3_fetch_bundle_sfb_masks_7_T_20, _f3_fetch_bundle_sfb_masks_7_T_6) node _f3_fetch_bundle_sfb_masks_7_T_22 = or(_f3_fetch_bundle_sfb_masks_7_T_21, _f3_fetch_bundle_sfb_masks_7_T_7) node _f3_fetch_bundle_sfb_masks_7_T_23 = or(_f3_fetch_bundle_sfb_masks_7_T_22, _f3_fetch_bundle_sfb_masks_7_T_8) node _f3_fetch_bundle_sfb_masks_7_T_24 = or(_f3_fetch_bundle_sfb_masks_7_T_23, _f3_fetch_bundle_sfb_masks_7_T_9) node _f3_fetch_bundle_sfb_masks_7_T_25 = or(_f3_fetch_bundle_sfb_masks_7_T_24, _f3_fetch_bundle_sfb_masks_7_T_10) node _f3_fetch_bundle_sfb_masks_7_T_26 = or(_f3_fetch_bundle_sfb_masks_7_T_25, _f3_fetch_bundle_sfb_masks_7_T_11) node _f3_fetch_bundle_sfb_masks_7_T_27 = or(_f3_fetch_bundle_sfb_masks_7_T_26, _f3_fetch_bundle_sfb_masks_7_T_12) node _f3_fetch_bundle_sfb_masks_7_T_28 = or(_f3_fetch_bundle_sfb_masks_7_T_27, _f3_fetch_bundle_sfb_masks_7_T_13) node _f3_fetch_bundle_sfb_masks_7_T_29 = or(_f3_fetch_bundle_sfb_masks_7_T_28, _f3_fetch_bundle_sfb_masks_7_T_14) node _f3_fetch_bundle_sfb_masks_7_T_30 = or(_f3_fetch_bundle_sfb_masks_7_T_29, _f3_fetch_bundle_sfb_masks_7_T_15) node _f3_fetch_bundle_sfb_masks_7_T_31 = not(_f3_fetch_bundle_sfb_masks_7_T_30) node _f3_fetch_bundle_sfb_masks_7_T_32 = dshl(upper_mask_7, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_7_T_33 = bits(_f3_fetch_bundle_sfb_masks_7_T_32, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_34 = dshl(upper_mask_7, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_7_T_35 = bits(_f3_fetch_bundle_sfb_masks_7_T_34, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_36 = dshl(upper_mask_7, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_7_T_37 = bits(_f3_fetch_bundle_sfb_masks_7_T_36, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_38 = dshl(upper_mask_7, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_7_T_39 = bits(_f3_fetch_bundle_sfb_masks_7_T_38, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_40 = dshl(upper_mask_7, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_7_T_41 = bits(_f3_fetch_bundle_sfb_masks_7_T_40, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_42 = dshl(upper_mask_7, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_7_T_43 = bits(_f3_fetch_bundle_sfb_masks_7_T_42, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_44 = dshl(upper_mask_7, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_7_T_45 = bits(_f3_fetch_bundle_sfb_masks_7_T_44, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_46 = dshl(upper_mask_7, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_7_T_47 = bits(_f3_fetch_bundle_sfb_masks_7_T_46, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_48 = dshl(upper_mask_7, UInt<4>(0h8)) node _f3_fetch_bundle_sfb_masks_7_T_49 = bits(_f3_fetch_bundle_sfb_masks_7_T_48, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_50 = dshl(upper_mask_7, UInt<4>(0h9)) node _f3_fetch_bundle_sfb_masks_7_T_51 = bits(_f3_fetch_bundle_sfb_masks_7_T_50, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_52 = dshl(upper_mask_7, UInt<4>(0ha)) node _f3_fetch_bundle_sfb_masks_7_T_53 = bits(_f3_fetch_bundle_sfb_masks_7_T_52, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_54 = dshl(upper_mask_7, UInt<4>(0hb)) node _f3_fetch_bundle_sfb_masks_7_T_55 = bits(_f3_fetch_bundle_sfb_masks_7_T_54, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_56 = dshl(upper_mask_7, UInt<4>(0hc)) node _f3_fetch_bundle_sfb_masks_7_T_57 = bits(_f3_fetch_bundle_sfb_masks_7_T_56, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_58 = dshl(upper_mask_7, UInt<4>(0hd)) node _f3_fetch_bundle_sfb_masks_7_T_59 = bits(_f3_fetch_bundle_sfb_masks_7_T_58, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_60 = dshl(upper_mask_7, UInt<4>(0he)) node _f3_fetch_bundle_sfb_masks_7_T_61 = bits(_f3_fetch_bundle_sfb_masks_7_T_60, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_62 = dshl(upper_mask_7, UInt<4>(0hf)) node _f3_fetch_bundle_sfb_masks_7_T_63 = bits(_f3_fetch_bundle_sfb_masks_7_T_62, 15, 0) node _f3_fetch_bundle_sfb_masks_7_T_64 = or(_f3_fetch_bundle_sfb_masks_7_T_33, _f3_fetch_bundle_sfb_masks_7_T_35) node _f3_fetch_bundle_sfb_masks_7_T_65 = or(_f3_fetch_bundle_sfb_masks_7_T_64, _f3_fetch_bundle_sfb_masks_7_T_37) node _f3_fetch_bundle_sfb_masks_7_T_66 = or(_f3_fetch_bundle_sfb_masks_7_T_65, _f3_fetch_bundle_sfb_masks_7_T_39) node _f3_fetch_bundle_sfb_masks_7_T_67 = or(_f3_fetch_bundle_sfb_masks_7_T_66, _f3_fetch_bundle_sfb_masks_7_T_41) node _f3_fetch_bundle_sfb_masks_7_T_68 = or(_f3_fetch_bundle_sfb_masks_7_T_67, _f3_fetch_bundle_sfb_masks_7_T_43) node _f3_fetch_bundle_sfb_masks_7_T_69 = or(_f3_fetch_bundle_sfb_masks_7_T_68, _f3_fetch_bundle_sfb_masks_7_T_45) node _f3_fetch_bundle_sfb_masks_7_T_70 = or(_f3_fetch_bundle_sfb_masks_7_T_69, _f3_fetch_bundle_sfb_masks_7_T_47) node _f3_fetch_bundle_sfb_masks_7_T_71 = or(_f3_fetch_bundle_sfb_masks_7_T_70, _f3_fetch_bundle_sfb_masks_7_T_49) node _f3_fetch_bundle_sfb_masks_7_T_72 = or(_f3_fetch_bundle_sfb_masks_7_T_71, _f3_fetch_bundle_sfb_masks_7_T_51) node _f3_fetch_bundle_sfb_masks_7_T_73 = or(_f3_fetch_bundle_sfb_masks_7_T_72, _f3_fetch_bundle_sfb_masks_7_T_53) node _f3_fetch_bundle_sfb_masks_7_T_74 = or(_f3_fetch_bundle_sfb_masks_7_T_73, _f3_fetch_bundle_sfb_masks_7_T_55) node _f3_fetch_bundle_sfb_masks_7_T_75 = or(_f3_fetch_bundle_sfb_masks_7_T_74, _f3_fetch_bundle_sfb_masks_7_T_57) node _f3_fetch_bundle_sfb_masks_7_T_76 = or(_f3_fetch_bundle_sfb_masks_7_T_75, _f3_fetch_bundle_sfb_masks_7_T_59) node _f3_fetch_bundle_sfb_masks_7_T_77 = or(_f3_fetch_bundle_sfb_masks_7_T_76, _f3_fetch_bundle_sfb_masks_7_T_61) node _f3_fetch_bundle_sfb_masks_7_T_78 = or(_f3_fetch_bundle_sfb_masks_7_T_77, _f3_fetch_bundle_sfb_masks_7_T_63) node _f3_fetch_bundle_sfb_masks_7_T_79 = not(_f3_fetch_bundle_sfb_masks_7_T_78) node _f3_fetch_bundle_sfb_masks_7_T_80 = and(_f3_fetch_bundle_sfb_masks_7_T_31, _f3_fetch_bundle_sfb_masks_7_T_79) connect f3_fetch_bundle.sfb_masks[7], _f3_fetch_bundle_sfb_masks_7_T_80 node _f3_fetch_bundle_shadowable_mask_7_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_7_T_1 = or(_f3_fetch_bundle_shadowable_mask_7_T, bpu_7.io.debug_if) node _f3_fetch_bundle_shadowable_mask_7_T_2 = or(_f3_fetch_bundle_shadowable_mask_7_T_1, bpu_7.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_7_T_3 = eq(_f3_fetch_bundle_shadowable_mask_7_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_7_T_4 = bits(f3_bank_mask, 1, 1) node _f3_fetch_bundle_shadowable_mask_7_T_5 = and(_f3_fetch_bundle_shadowable_mask_7_T_3, _f3_fetch_bundle_shadowable_mask_7_T_4) node _f3_fetch_bundle_shadowable_mask_7_T_6 = eq(f3_mask[7], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_7_T_7 = or(brsigs_7.shadowable, _f3_fetch_bundle_shadowable_mask_7_T_6) node _f3_fetch_bundle_shadowable_mask_7_T_8 = and(_f3_fetch_bundle_shadowable_mask_7_T_5, _f3_fetch_bundle_shadowable_mask_7_T_7) connect f3_fetch_bundle.shadowable_mask[7], _f3_fetch_bundle_shadowable_mask_7_T_8 connect f3_fetch_bundle.sfb_dests[7], offset_from_aligned_pc_7 node _f3_redirects_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h2)) node _f3_redirects_7_T_1 = eq(brsigs_7.cfi_type, UInt<3>(0h3)) node _f3_redirects_7_T_2 = or(_f3_redirects_7_T, _f3_redirects_7_T_1) node _f3_redirects_7_T_3 = eq(brsigs_7.cfi_type, UInt<3>(0h1)) node _f3_redirects_7_T_4 = and(_f3_redirects_7_T_3, f3_bpd_resp.io.deq.bits.preds[7].taken) node _f3_redirects_7_T_5 = and(_f3_redirects_7_T_4, UInt<1>(0h1)) node _f3_redirects_7_T_6 = or(_f3_redirects_7_T_2, _f3_redirects_7_T_5) node _f3_redirects_7_T_7 = and(f3_mask[7], _f3_redirects_7_T_6) connect f3_redirects[7], _f3_redirects_7_T_7 node _f3_br_mask_7_T = eq(brsigs_7.cfi_type, UInt<3>(0h1)) node _f3_br_mask_7_T_1 = and(f3_mask[7], _f3_br_mask_7_T) connect f3_br_mask[7], _f3_br_mask_7_T_1 connect f3_cfi_types[7], brsigs_7.cfi_type connect f3_call_mask[7], brsigs_7.is_call connect f3_ret_mask[7], brsigs_7.is_ret connect f3_fetch_bundle.bp_debug_if_oh[7], bpu_7.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[7], bpu_7.io.xcpt_if node _T_51 = or(_T_50, f3_redirects[7]) node _T_52 = bits(bank_insts_1[3], 15, 0) node _T_53 = bits(f3_bank_mask, 1, 1) node _T_54 = bits(bank_insts_1[2], 1, 0) node _T_55 = neq(_T_54, UInt<2>(0h3)) node _T_56 = eq(_T_55, UInt<1>(0h0)) node _T_57 = and(bank_mask_1[2], _T_56) node _T_58 = eq(_T_57, UInt<1>(0h0)) node _T_59 = bits(_T_52, 1, 0) node _T_60 = neq(_T_59, UInt<2>(0h3)) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(_T_58, _T_61) node _T_63 = mux(_T_53, _T_62, _T_43) node _T_64 = bits(f3_bank_mask, 1, 1) node _T_65 = bits(_T_52, 15, 0) node _T_66 = mux(_T_64, _T_65, _T_46) connect f3_fetch_bundle.cfi_type, f3_cfi_types[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_is_call, f3_call_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_is_ret, f3_ret_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_npc_plus4, f3_npc_plus4_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.ghist, f3.io.deq.bits.ghist connect f3_fetch_bundle.lhist, f3_bpd_resp.io.deq.bits.lhist connect f3_fetch_bundle.bpd_meta, f3_bpd_resp.io.deq.bits.meta connect f3_fetch_bundle.end_half.valid, _T_63 connect f3_fetch_bundle.end_half.bits, _T_66 node _T_67 = and(f3.io.deq.ready, f3.io.deq.valid) when _T_67 : connect f3_prev_is_half, _T_63 connect f3_prev_half, _T_66 node _T_68 = eq(f3_bpd_resp.io.deq.bits.pc, f3_fetch_bundle.pc) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed\n at frontend.scala:770 assert(f3_bpd_resp.io.deq.bits.pc === f3_fetch_bundle.pc)\n") : printf assert(clock, _T_68, UInt<1>(0h1), "") : assert when f3_clear : connect f3_prev_is_half, UInt<1>(0h0) node _f3_fetch_bundle_cfi_idx_valid_T = or(f3_redirects[0], f3_redirects[1]) node _f3_fetch_bundle_cfi_idx_valid_T_1 = or(_f3_fetch_bundle_cfi_idx_valid_T, f3_redirects[2]) node _f3_fetch_bundle_cfi_idx_valid_T_2 = or(_f3_fetch_bundle_cfi_idx_valid_T_1, f3_redirects[3]) node _f3_fetch_bundle_cfi_idx_valid_T_3 = or(_f3_fetch_bundle_cfi_idx_valid_T_2, f3_redirects[4]) node _f3_fetch_bundle_cfi_idx_valid_T_4 = or(_f3_fetch_bundle_cfi_idx_valid_T_3, f3_redirects[5]) node _f3_fetch_bundle_cfi_idx_valid_T_5 = or(_f3_fetch_bundle_cfi_idx_valid_T_4, f3_redirects[6]) node _f3_fetch_bundle_cfi_idx_valid_T_6 = or(_f3_fetch_bundle_cfi_idx_valid_T_5, f3_redirects[7]) connect f3_fetch_bundle.cfi_idx.valid, _f3_fetch_bundle_cfi_idx_valid_T_6 node _f3_fetch_bundle_cfi_idx_bits_T = mux(f3_redirects[6], UInt<3>(0h6), UInt<3>(0h7)) node _f3_fetch_bundle_cfi_idx_bits_T_1 = mux(f3_redirects[5], UInt<3>(0h5), _f3_fetch_bundle_cfi_idx_bits_T) node _f3_fetch_bundle_cfi_idx_bits_T_2 = mux(f3_redirects[4], UInt<3>(0h4), _f3_fetch_bundle_cfi_idx_bits_T_1) node _f3_fetch_bundle_cfi_idx_bits_T_3 = mux(f3_redirects[3], UInt<2>(0h3), _f3_fetch_bundle_cfi_idx_bits_T_2) node _f3_fetch_bundle_cfi_idx_bits_T_4 = mux(f3_redirects[2], UInt<2>(0h2), _f3_fetch_bundle_cfi_idx_bits_T_3) node _f3_fetch_bundle_cfi_idx_bits_T_5 = mux(f3_redirects[1], UInt<1>(0h1), _f3_fetch_bundle_cfi_idx_bits_T_4) node _f3_fetch_bundle_cfi_idx_bits_T_6 = mux(f3_redirects[0], UInt<1>(0h0), _f3_fetch_bundle_cfi_idx_bits_T_5) connect f3_fetch_bundle.cfi_idx.bits, _f3_fetch_bundle_cfi_idx_bits_T_6 connect f3_fetch_bundle.ras_top, ras.io.read_addr node _f3_predicted_target_T = or(f3_redirects[0], f3_redirects[1]) node _f3_predicted_target_T_1 = or(_f3_predicted_target_T, f3_redirects[2]) node _f3_predicted_target_T_2 = or(_f3_predicted_target_T_1, f3_redirects[3]) node _f3_predicted_target_T_3 = or(_f3_predicted_target_T_2, f3_redirects[4]) node _f3_predicted_target_T_4 = or(_f3_predicted_target_T_3, f3_redirects[5]) node _f3_predicted_target_T_5 = or(_f3_predicted_target_T_4, f3_redirects[6]) node _f3_predicted_target_T_6 = or(_f3_predicted_target_T_5, f3_redirects[7]) node _f3_predicted_target_T_7 = and(f3_fetch_bundle.cfi_is_ret, UInt<1>(0h1)) node _f3_predicted_target_T_8 = and(_f3_predicted_target_T_7, UInt<1>(0h1)) node _f3_predicted_target_T_9 = mux(f3_redirects[6], UInt<3>(0h6), UInt<3>(0h7)) node _f3_predicted_target_T_10 = mux(f3_redirects[5], UInt<3>(0h5), _f3_predicted_target_T_9) node _f3_predicted_target_T_11 = mux(f3_redirects[4], UInt<3>(0h4), _f3_predicted_target_T_10) node _f3_predicted_target_T_12 = mux(f3_redirects[3], UInt<2>(0h3), _f3_predicted_target_T_11) node _f3_predicted_target_T_13 = mux(f3_redirects[2], UInt<2>(0h2), _f3_predicted_target_T_12) node _f3_predicted_target_T_14 = mux(f3_redirects[1], UInt<1>(0h1), _f3_predicted_target_T_13) node _f3_predicted_target_T_15 = mux(f3_redirects[0], UInt<1>(0h0), _f3_predicted_target_T_14) node _f3_predicted_target_T_16 = mux(_f3_predicted_target_T_8, ras.io.read_addr, f3_targs[_f3_predicted_target_T_15]) node _f3_predicted_target_T_17 = not(f3_fetch_bundle.pc) node _f3_predicted_target_T_18 = or(_f3_predicted_target_T_17, UInt<3>(0h7)) node _f3_predicted_target_T_19 = not(_f3_predicted_target_T_18) node _f3_predicted_target_T_20 = bits(f3_fetch_bundle.pc, 5, 3) node _f3_predicted_target_T_21 = eq(_f3_predicted_target_T_20, UInt<3>(0h7)) node _f3_predicted_target_T_22 = and(UInt<1>(0h1), _f3_predicted_target_T_21) node _f3_predicted_target_T_23 = mux(_f3_predicted_target_T_22, UInt<4>(0h8), UInt<5>(0h10)) node _f3_predicted_target_T_24 = add(_f3_predicted_target_T_19, _f3_predicted_target_T_23) node _f3_predicted_target_T_25 = tail(_f3_predicted_target_T_24, 1) node f3_predicted_target = mux(_f3_predicted_target_T_6, _f3_predicted_target_T_16, _f3_predicted_target_T_25) connect f3_fetch_bundle.next_pc, f3_predicted_target node _f3_predicted_ghist_T = dshr(f3_fetch_bundle.br_mask, f3_fetch_bundle.cfi_idx.bits) node _f3_predicted_ghist_T_1 = bits(_f3_predicted_ghist_T, 0, 0) node f3_predicted_ghist_cfi_idx_fixed = bits(f3_fetch_bundle.cfi_idx.bits, 2, 0) node f3_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f3_predicted_ghist_cfi_idx_fixed) wire f3_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f3_predicted_ghist_not_taken_branches_T = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_1 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f3_predicted_ghist_not_taken_branches_T_2 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f3_predicted_ghist_not_taken_branches_T_3 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f3_predicted_ghist_not_taken_branches_T_4 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h4)) node _f3_predicted_ghist_not_taken_branches_T_5 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h5)) node _f3_predicted_ghist_not_taken_branches_T_6 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h6)) node _f3_predicted_ghist_not_taken_branches_T_7 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<3>(0h7)) node _f3_predicted_ghist_not_taken_branches_T_8 = or(_f3_predicted_ghist_not_taken_branches_T, _f3_predicted_ghist_not_taken_branches_T_1) node _f3_predicted_ghist_not_taken_branches_T_9 = or(_f3_predicted_ghist_not_taken_branches_T_8, _f3_predicted_ghist_not_taken_branches_T_2) node _f3_predicted_ghist_not_taken_branches_T_10 = or(_f3_predicted_ghist_not_taken_branches_T_9, _f3_predicted_ghist_not_taken_branches_T_3) node _f3_predicted_ghist_not_taken_branches_T_11 = or(_f3_predicted_ghist_not_taken_branches_T_10, _f3_predicted_ghist_not_taken_branches_T_4) node _f3_predicted_ghist_not_taken_branches_T_12 = or(_f3_predicted_ghist_not_taken_branches_T_11, _f3_predicted_ghist_not_taken_branches_T_5) node _f3_predicted_ghist_not_taken_branches_T_13 = or(_f3_predicted_ghist_not_taken_branches_T_12, _f3_predicted_ghist_not_taken_branches_T_6) node _f3_predicted_ghist_not_taken_branches_T_14 = or(_f3_predicted_ghist_not_taken_branches_T_13, _f3_predicted_ghist_not_taken_branches_T_7) node _f3_predicted_ghist_not_taken_branches_T_15 = and(_f3_predicted_ghist_T_1, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_not_taken_branches_T_16 = mux(_f3_predicted_ghist_not_taken_branches_T_15, f3_predicted_ghist_cfi_idx_oh, UInt<8>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_17 = not(_f3_predicted_ghist_not_taken_branches_T_16) node _f3_predicted_ghist_not_taken_branches_T_18 = and(_f3_predicted_ghist_not_taken_branches_T_14, _f3_predicted_ghist_not_taken_branches_T_17) node _f3_predicted_ghist_not_taken_branches_T_19 = not(UInt<8>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_20 = mux(f3_fetch_bundle.cfi_idx.valid, _f3_predicted_ghist_not_taken_branches_T_18, _f3_predicted_ghist_not_taken_branches_T_19) node f3_predicted_ghist_not_taken_branches = and(f3_fetch_bundle.br_mask, _f3_predicted_ghist_not_taken_branches_T_20) node _f3_predicted_ghist_base_T = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_base_T_1 = or(_f3_predicted_ghist_base_T, UInt<1>(0h1)) node _f3_predicted_ghist_base_T_2 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_base_T_3 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_base_T_2, f3_fetch_bundle.ghist.old_history) node f3_predicted_ghist_base = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_base_T_1, _f3_predicted_ghist_base_T_3) node _f3_predicted_ghist_cfi_in_bank_0_T = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_cfi_in_bank_0_T_1 = lt(f3_predicted_ghist_cfi_idx_fixed, UInt<3>(0h4)) node f3_predicted_ghist_cfi_in_bank_0 = and(_f3_predicted_ghist_cfi_in_bank_0_T, _f3_predicted_ghist_cfi_in_bank_0_T_1) node _f3_predicted_ghist_ignore_second_bank_T = bits(f3_fetch_bundle.pc, 5, 3) node _f3_predicted_ghist_ignore_second_bank_T_1 = eq(_f3_predicted_ghist_ignore_second_bank_T, UInt<3>(0h7)) node _f3_predicted_ghist_ignore_second_bank_T_2 = and(UInt<1>(0h1), _f3_predicted_ghist_ignore_second_bank_T_1) node f3_predicted_ghist_ignore_second_bank = or(f3_predicted_ghist_cfi_in_bank_0, _f3_predicted_ghist_ignore_second_bank_T_2) node _f3_predicted_ghist_first_bank_saw_not_taken_T = bits(f3_predicted_ghist_not_taken_branches, 3, 0) node _f3_predicted_ghist_first_bank_saw_not_taken_T_1 = neq(_f3_predicted_ghist_first_bank_saw_not_taken_T, UInt<1>(0h0)) node f3_predicted_ghist_first_bank_saw_not_taken = or(_f3_predicted_ghist_first_bank_saw_not_taken_T_1, f3_fetch_bundle.ghist.current_saw_branch_not_taken) connect f3_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) when f3_predicted_ghist_ignore_second_bank : node _f3_predicted_ghist_new_history_old_history_T = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_1 = or(_f3_predicted_ghist_new_history_old_history_T, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_2 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_3 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_2, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_4 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_1, _f3_predicted_ghist_new_history_old_history_T_3) connect f3_predicted_ghist.old_history, _f3_predicted_ghist_new_history_old_history_T_4 connect f3_predicted_ghist.new_saw_branch_not_taken, f3_predicted_ghist_first_bank_saw_not_taken node _f3_predicted_ghist_new_history_new_saw_branch_taken_T = and(_f3_predicted_ghist_T_1, f3_predicted_ghist_cfi_in_bank_0) connect f3_predicted_ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_new_saw_branch_taken_T else : node _f3_predicted_ghist_new_history_old_history_T_5 = and(_f3_predicted_ghist_T_1, f3_predicted_ghist_cfi_in_bank_0) node _f3_predicted_ghist_new_history_old_history_T_6 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_7 = or(_f3_predicted_ghist_new_history_old_history_T_6, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_8 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_9 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_8, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_10 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_7, _f3_predicted_ghist_new_history_old_history_T_9) node _f3_predicted_ghist_new_history_old_history_T_11 = shl(_f3_predicted_ghist_new_history_old_history_T_10, 1) node _f3_predicted_ghist_new_history_old_history_T_12 = or(_f3_predicted_ghist_new_history_old_history_T_11, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_13 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_14 = or(_f3_predicted_ghist_new_history_old_history_T_13, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_15 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_16 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_15, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_17 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_14, _f3_predicted_ghist_new_history_old_history_T_16) node _f3_predicted_ghist_new_history_old_history_T_18 = shl(_f3_predicted_ghist_new_history_old_history_T_17, 1) node _f3_predicted_ghist_new_history_old_history_T_19 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_20 = or(_f3_predicted_ghist_new_history_old_history_T_19, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_21 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_22 = mux(f3_fetch_bundle.ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_old_history_T_21, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_23 = mux(f3_fetch_bundle.ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_old_history_T_20, _f3_predicted_ghist_new_history_old_history_T_22) node _f3_predicted_ghist_new_history_old_history_T_24 = mux(f3_predicted_ghist_first_bank_saw_not_taken, _f3_predicted_ghist_new_history_old_history_T_18, _f3_predicted_ghist_new_history_old_history_T_23) node _f3_predicted_ghist_new_history_old_history_T_25 = mux(_f3_predicted_ghist_new_history_old_history_T_5, _f3_predicted_ghist_new_history_old_history_T_12, _f3_predicted_ghist_new_history_old_history_T_24) connect f3_predicted_ghist.old_history, _f3_predicted_ghist_new_history_old_history_T_25 node _f3_predicted_ghist_new_history_new_saw_branch_not_taken_T = bits(f3_predicted_ghist_not_taken_branches, 7, 4) node _f3_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = neq(_f3_predicted_ghist_new_history_new_saw_branch_not_taken_T, UInt<1>(0h0)) connect f3_predicted_ghist.new_saw_branch_not_taken, _f3_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_1 = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_2 = and(_f3_predicted_ghist_new_history_new_saw_branch_taken_T_1, _f3_predicted_ghist_T_1) node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_3 = eq(f3_predicted_ghist_cfi_in_bank_0, UInt<1>(0h0)) node _f3_predicted_ghist_new_history_new_saw_branch_taken_T_4 = and(_f3_predicted_ghist_new_history_new_saw_branch_taken_T_2, _f3_predicted_ghist_new_history_new_saw_branch_taken_T_3) connect f3_predicted_ghist.new_saw_branch_taken, _f3_predicted_ghist_new_history_new_saw_branch_taken_T_4 node _f3_predicted_ghist_new_history_ras_idx_T = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_is_call) node _f3_predicted_ghist_new_history_ras_idx_T_1 = add(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_ras_idx_T_2 = tail(_f3_predicted_ghist_new_history_ras_idx_T_1, 1) node _f3_predicted_ghist_new_history_ras_idx_T_3 = bits(_f3_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f3_predicted_ghist_new_history_ras_idx_T_4 = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_is_ret) node _f3_predicted_ghist_new_history_ras_idx_T_5 = sub(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_ras_idx_T_6 = tail(_f3_predicted_ghist_new_history_ras_idx_T_5, 1) node _f3_predicted_ghist_new_history_ras_idx_T_7 = bits(_f3_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f3_predicted_ghist_new_history_ras_idx_T_8 = mux(_f3_predicted_ghist_new_history_ras_idx_T_4, _f3_predicted_ghist_new_history_ras_idx_T_7, f3_fetch_bundle.ghist.ras_idx) node _f3_predicted_ghist_new_history_ras_idx_T_9 = mux(_f3_predicted_ghist_new_history_ras_idx_T, _f3_predicted_ghist_new_history_ras_idx_T_3, _f3_predicted_ghist_new_history_ras_idx_T_8) connect f3_predicted_ghist.ras_idx, _f3_predicted_ghist_new_history_ras_idx_T_9 connect ras.io.write_valid, UInt<1>(0h0) node _ras_io_write_addr_T = shl(f3_fetch_bundle.cfi_idx.bits, 1) node _ras_io_write_addr_T_1 = add(f3_aligned_pc, _ras_io_write_addr_T) node _ras_io_write_addr_T_2 = tail(_ras_io_write_addr_T_1, 1) node _ras_io_write_addr_T_3 = mux(f3_fetch_bundle.cfi_npc_plus4, UInt<3>(0h4), UInt<2>(0h2)) node _ras_io_write_addr_T_4 = add(_ras_io_write_addr_T_2, _ras_io_write_addr_T_3) node _ras_io_write_addr_T_5 = tail(_ras_io_write_addr_T_4, 1) connect ras.io.write_addr, _ras_io_write_addr_T_5 node _ras_io_write_idx_T = add(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _ras_io_write_idx_T_1 = tail(_ras_io_write_idx_T, 1) node _ras_io_write_idx_T_2 = bits(_ras_io_write_idx_T_1, 4, 0) connect ras.io.write_idx, _ras_io_write_idx_T_2 node _f3_correct_f1_ghist_T = eq(s1_ghist.old_history, f3_predicted_ghist.old_history) node _f3_correct_f1_ghist_T_1 = eq(s1_ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken) node _f3_correct_f1_ghist_T_2 = and(_f3_correct_f1_ghist_T, _f3_correct_f1_ghist_T_1) node _f3_correct_f1_ghist_T_3 = eq(s1_ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken) node _f3_correct_f1_ghist_T_4 = and(_f3_correct_f1_ghist_T_2, _f3_correct_f1_ghist_T_3) node _f3_correct_f1_ghist_T_5 = eq(_f3_correct_f1_ghist_T_4, UInt<1>(0h0)) node f3_correct_f1_ghist = and(_f3_correct_f1_ghist_T_5, UInt<1>(0h1)) node _f3_correct_f2_ghist_T = eq(s2_ghist.old_history, f3_predicted_ghist.old_history) node _f3_correct_f2_ghist_T_1 = eq(s2_ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken) node _f3_correct_f2_ghist_T_2 = and(_f3_correct_f2_ghist_T, _f3_correct_f2_ghist_T_1) node _f3_correct_f2_ghist_T_3 = eq(s2_ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken) node _f3_correct_f2_ghist_T_4 = and(_f3_correct_f2_ghist_T_2, _f3_correct_f2_ghist_T_3) node _f3_correct_f2_ghist_T_5 = eq(_f3_correct_f2_ghist_T_4, UInt<1>(0h0)) node f3_correct_f2_ghist = and(_f3_correct_f2_ghist_T_5, UInt<1>(0h1)) node _T_72 = and(f3.io.deq.valid, f4_ready) when _T_72 : node _T_73 = and(f3_fetch_bundle.cfi_is_call, f3_fetch_bundle.cfi_idx.valid) when _T_73 : connect ras.io.write_valid, UInt<1>(0h1) node _T_74 = or(f3_redirects[0], f3_redirects[1]) node _T_75 = or(_T_74, f3_redirects[2]) node _T_76 = or(_T_75, f3_redirects[3]) node _T_77 = or(_T_76, f3_redirects[4]) node _T_78 = or(_T_77, f3_redirects[5]) node _T_79 = or(_T_78, f3_redirects[6]) node _T_80 = or(_T_79, f3_redirects[7]) when _T_80 : connect f3_prev_is_half, UInt<1>(0h0) node _T_81 = eq(s2_vpc, f3_predicted_target) node _T_82 = and(s2_valid, _T_81) node _T_83 = eq(f3_correct_f2_ghist, UInt<1>(0h0)) node _T_84 = and(_T_82, _T_83) when _T_84 : connect f3.io.enq.bits.ghist.ras_idx, f3_predicted_ghist.ras_idx connect f3.io.enq.bits.ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken connect f3.io.enq.bits.ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken connect f3.io.enq.bits.ghist.current_saw_branch_not_taken, f3_predicted_ghist.current_saw_branch_not_taken connect f3.io.enq.bits.ghist.old_history, f3_predicted_ghist.old_history else : node _T_85 = eq(s2_valid, UInt<1>(0h0)) node _T_86 = and(_T_85, s1_valid) node _T_87 = eq(s1_vpc, f3_predicted_target) node _T_88 = and(_T_86, _T_87) node _T_89 = eq(f3_correct_f1_ghist, UInt<1>(0h0)) node _T_90 = and(_T_88, _T_89) when _T_90 : connect s2_ghist, f3_predicted_ghist else : node _T_91 = neq(s2_vpc, f3_predicted_target) node _T_92 = or(_T_91, f3_correct_f2_ghist) node _T_93 = and(s2_valid, _T_92) node _T_94 = eq(s2_valid, UInt<1>(0h0)) node _T_95 = and(_T_94, s1_valid) node _T_96 = neq(s1_vpc, f3_predicted_target) node _T_97 = or(_T_96, f3_correct_f1_ghist) node _T_98 = and(_T_95, _T_97) node _T_99 = or(_T_93, _T_98) node _T_100 = eq(s2_valid, UInt<1>(0h0)) node _T_101 = eq(s1_valid, UInt<1>(0h0)) node _T_102 = and(_T_100, _T_101) node _T_103 = or(_T_99, _T_102) when _T_103 : connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) node _s0_valid_T_11 = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _s0_valid_T_12 = eq(_s0_valid_T_11, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_12 connect s0_vpc, f3_predicted_target connect s0_is_replay, UInt<1>(0h0) connect s0_ghist, f3_predicted_ghist connect s0_tsrc, UInt<2>(0h2) connect f3_fetch_bundle.fsrc, UInt<2>(0h2) inst f4_btb_corrections of Queue2_BranchPredictionUpdate_1 connect f4_btb_corrections.clock, clock connect f4_btb_corrections.reset, reset node _f4_btb_corrections_io_enq_valid_T = and(f3.io.deq.ready, f3.io.deq.valid) node _f4_btb_corrections_io_enq_valid_T_1 = or(f3_btb_mispredicts[0], f3_btb_mispredicts[1]) node _f4_btb_corrections_io_enq_valid_T_2 = or(_f4_btb_corrections_io_enq_valid_T_1, f3_btb_mispredicts[2]) node _f4_btb_corrections_io_enq_valid_T_3 = or(_f4_btb_corrections_io_enq_valid_T_2, f3_btb_mispredicts[3]) node _f4_btb_corrections_io_enq_valid_T_4 = or(_f4_btb_corrections_io_enq_valid_T_3, f3_btb_mispredicts[4]) node _f4_btb_corrections_io_enq_valid_T_5 = or(_f4_btb_corrections_io_enq_valid_T_4, f3_btb_mispredicts[5]) node _f4_btb_corrections_io_enq_valid_T_6 = or(_f4_btb_corrections_io_enq_valid_T_5, f3_btb_mispredicts[6]) node _f4_btb_corrections_io_enq_valid_T_7 = or(_f4_btb_corrections_io_enq_valid_T_6, f3_btb_mispredicts[7]) node _f4_btb_corrections_io_enq_valid_T_8 = and(_f4_btb_corrections_io_enq_valid_T, _f4_btb_corrections_io_enq_valid_T_7) node _f4_btb_corrections_io_enq_valid_T_9 = and(_f4_btb_corrections_io_enq_valid_T_8, UInt<1>(0h1)) connect f4_btb_corrections.io.enq.valid, _f4_btb_corrections_io_enq_valid_T_9 invalidate f4_btb_corrections.io.enq.bits.meta[0] invalidate f4_btb_corrections.io.enq.bits.meta[1] invalidate f4_btb_corrections.io.enq.bits.target invalidate f4_btb_corrections.io.enq.bits.lhist[0] invalidate f4_btb_corrections.io.enq.bits.lhist[1] invalidate f4_btb_corrections.io.enq.bits.ghist.ras_idx invalidate f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_taken invalidate f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_not_taken invalidate f4_btb_corrections.io.enq.bits.ghist.current_saw_branch_not_taken invalidate f4_btb_corrections.io.enq.bits.ghist.old_history invalidate f4_btb_corrections.io.enq.bits.cfi_is_jalr invalidate f4_btb_corrections.io.enq.bits.cfi_is_jal invalidate f4_btb_corrections.io.enq.bits.cfi_is_br invalidate f4_btb_corrections.io.enq.bits.cfi_mispredicted invalidate f4_btb_corrections.io.enq.bits.cfi_taken invalidate f4_btb_corrections.io.enq.bits.cfi_idx.bits invalidate f4_btb_corrections.io.enq.bits.cfi_idx.valid invalidate f4_btb_corrections.io.enq.bits.br_mask invalidate f4_btb_corrections.io.enq.bits.pc invalidate f4_btb_corrections.io.enq.bits.btb_mispredicts invalidate f4_btb_corrections.io.enq.bits.is_repair_update invalidate f4_btb_corrections.io.enq.bits.is_mispredict_update connect f4_btb_corrections.io.enq.bits.is_mispredict_update, UInt<1>(0h0) connect f4_btb_corrections.io.enq.bits.is_repair_update, UInt<1>(0h0) node f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_lo = cat(f3_btb_mispredicts[1], f3_btb_mispredicts[0]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_hi = cat(f3_btb_mispredicts[3], f3_btb_mispredicts[2]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_lo = cat(f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_hi, f4_btb_corrections_io_enq_bits_btb_mispredicts_lo_lo) node f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_lo = cat(f3_btb_mispredicts[5], f3_btb_mispredicts[4]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_hi = cat(f3_btb_mispredicts[7], f3_btb_mispredicts[6]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_hi = cat(f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_hi, f4_btb_corrections_io_enq_bits_btb_mispredicts_hi_lo) node _f4_btb_corrections_io_enq_bits_btb_mispredicts_T = cat(f4_btb_corrections_io_enq_bits_btb_mispredicts_hi, f4_btb_corrections_io_enq_bits_btb_mispredicts_lo) connect f4_btb_corrections.io.enq.bits.btb_mispredicts, _f4_btb_corrections_io_enq_bits_btb_mispredicts_T connect f4_btb_corrections.io.enq.bits.pc, f3_fetch_bundle.pc connect f4_btb_corrections.io.enq.bits.ghist.ras_idx, f3_fetch_bundle.ghist.ras_idx connect f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_taken, f3_fetch_bundle.ghist.new_saw_branch_taken connect f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_not_taken, f3_fetch_bundle.ghist.new_saw_branch_not_taken connect f4_btb_corrections.io.enq.bits.ghist.current_saw_branch_not_taken, f3_fetch_bundle.ghist.current_saw_branch_not_taken connect f4_btb_corrections.io.enq.bits.ghist.old_history, f3_fetch_bundle.ghist.old_history connect f4_btb_corrections.io.enq.bits.lhist[0], f3_fetch_bundle.lhist[0] connect f4_btb_corrections.io.enq.bits.lhist[1], f3_fetch_bundle.lhist[1] connect f4_btb_corrections.io.enq.bits.meta[0], f3_fetch_bundle.bpd_meta[0] connect f4_btb_corrections.io.enq.bits.meta[1], f3_fetch_bundle.bpd_meta[1] wire f4_clear : UInt<1> connect f4_clear, UInt<1>(0h0) node _T_104 = asUInt(reset) node _T_105 = or(_T_104, f4_clear) inst f4 of Queue1_FetchBundle_1 connect f4.clock, clock connect f4.reset, _T_105 inst fb of FetchBuffer_1 connect fb.clock, clock connect fb.reset, reset inst ftq of FetchTargetQueue_1 connect ftq.clock, clock connect ftq.reset, reset node f4_shadowable_masks_lo_lo = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo = cat(f4_shadowable_masks_lo_hi, f4_shadowable_masks_lo_lo) node f4_shadowable_masks_hi_lo = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi = cat(f4_shadowable_masks_hi_hi, f4_shadowable_masks_hi_lo) node _f4_shadowable_masks_T = cat(f4_shadowable_masks_hi, f4_shadowable_masks_lo) node _f4_shadowable_masks_T_1 = bits(f4.io.deq.bits.sfb_masks[0], 7, 0) node _f4_shadowable_masks_T_2 = not(_f4_shadowable_masks_T_1) node _f4_shadowable_masks_T_3 = or(_f4_shadowable_masks_T, _f4_shadowable_masks_T_2) node f4_shadowable_masks_lo_lo_1 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_1 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_1 = cat(f4_shadowable_masks_lo_hi_1, f4_shadowable_masks_lo_lo_1) node f4_shadowable_masks_hi_lo_1 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_1 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_1 = cat(f4_shadowable_masks_hi_hi_1, f4_shadowable_masks_hi_lo_1) node _f4_shadowable_masks_T_4 = cat(f4_shadowable_masks_hi_1, f4_shadowable_masks_lo_1) node _f4_shadowable_masks_T_5 = bits(f4.io.deq.bits.sfb_masks[1], 7, 0) node _f4_shadowable_masks_T_6 = not(_f4_shadowable_masks_T_5) node _f4_shadowable_masks_T_7 = or(_f4_shadowable_masks_T_4, _f4_shadowable_masks_T_6) node f4_shadowable_masks_lo_lo_2 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_2 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_2 = cat(f4_shadowable_masks_lo_hi_2, f4_shadowable_masks_lo_lo_2) node f4_shadowable_masks_hi_lo_2 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_2 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_2 = cat(f4_shadowable_masks_hi_hi_2, f4_shadowable_masks_hi_lo_2) node _f4_shadowable_masks_T_8 = cat(f4_shadowable_masks_hi_2, f4_shadowable_masks_lo_2) node _f4_shadowable_masks_T_9 = bits(f4.io.deq.bits.sfb_masks[2], 7, 0) node _f4_shadowable_masks_T_10 = not(_f4_shadowable_masks_T_9) node _f4_shadowable_masks_T_11 = or(_f4_shadowable_masks_T_8, _f4_shadowable_masks_T_10) node f4_shadowable_masks_lo_lo_3 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_3 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_3 = cat(f4_shadowable_masks_lo_hi_3, f4_shadowable_masks_lo_lo_3) node f4_shadowable_masks_hi_lo_3 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_3 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_3 = cat(f4_shadowable_masks_hi_hi_3, f4_shadowable_masks_hi_lo_3) node _f4_shadowable_masks_T_12 = cat(f4_shadowable_masks_hi_3, f4_shadowable_masks_lo_3) node _f4_shadowable_masks_T_13 = bits(f4.io.deq.bits.sfb_masks[3], 7, 0) node _f4_shadowable_masks_T_14 = not(_f4_shadowable_masks_T_13) node _f4_shadowable_masks_T_15 = or(_f4_shadowable_masks_T_12, _f4_shadowable_masks_T_14) node f4_shadowable_masks_lo_lo_4 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_4 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_4 = cat(f4_shadowable_masks_lo_hi_4, f4_shadowable_masks_lo_lo_4) node f4_shadowable_masks_hi_lo_4 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_4 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_4 = cat(f4_shadowable_masks_hi_hi_4, f4_shadowable_masks_hi_lo_4) node _f4_shadowable_masks_T_16 = cat(f4_shadowable_masks_hi_4, f4_shadowable_masks_lo_4) node _f4_shadowable_masks_T_17 = bits(f4.io.deq.bits.sfb_masks[4], 7, 0) node _f4_shadowable_masks_T_18 = not(_f4_shadowable_masks_T_17) node _f4_shadowable_masks_T_19 = or(_f4_shadowable_masks_T_16, _f4_shadowable_masks_T_18) node f4_shadowable_masks_lo_lo_5 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_5 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_5 = cat(f4_shadowable_masks_lo_hi_5, f4_shadowable_masks_lo_lo_5) node f4_shadowable_masks_hi_lo_5 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_5 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_5 = cat(f4_shadowable_masks_hi_hi_5, f4_shadowable_masks_hi_lo_5) node _f4_shadowable_masks_T_20 = cat(f4_shadowable_masks_hi_5, f4_shadowable_masks_lo_5) node _f4_shadowable_masks_T_21 = bits(f4.io.deq.bits.sfb_masks[5], 7, 0) node _f4_shadowable_masks_T_22 = not(_f4_shadowable_masks_T_21) node _f4_shadowable_masks_T_23 = or(_f4_shadowable_masks_T_20, _f4_shadowable_masks_T_22) node f4_shadowable_masks_lo_lo_6 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_6 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_6 = cat(f4_shadowable_masks_lo_hi_6, f4_shadowable_masks_lo_lo_6) node f4_shadowable_masks_hi_lo_6 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_6 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_6 = cat(f4_shadowable_masks_hi_hi_6, f4_shadowable_masks_hi_lo_6) node _f4_shadowable_masks_T_24 = cat(f4_shadowable_masks_hi_6, f4_shadowable_masks_lo_6) node _f4_shadowable_masks_T_25 = bits(f4.io.deq.bits.sfb_masks[6], 7, 0) node _f4_shadowable_masks_T_26 = not(_f4_shadowable_masks_T_25) node _f4_shadowable_masks_T_27 = or(_f4_shadowable_masks_T_24, _f4_shadowable_masks_T_26) node f4_shadowable_masks_lo_lo_7 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_lo_hi_7 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node f4_shadowable_masks_lo_7 = cat(f4_shadowable_masks_lo_hi_7, f4_shadowable_masks_lo_lo_7) node f4_shadowable_masks_hi_lo_7 = cat(f4.io.deq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[4]) node f4_shadowable_masks_hi_hi_7 = cat(f4.io.deq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[6]) node f4_shadowable_masks_hi_7 = cat(f4_shadowable_masks_hi_hi_7, f4_shadowable_masks_hi_lo_7) node _f4_shadowable_masks_T_28 = cat(f4_shadowable_masks_hi_7, f4_shadowable_masks_lo_7) node _f4_shadowable_masks_T_29 = bits(f4.io.deq.bits.sfb_masks[7], 7, 0) node _f4_shadowable_masks_T_30 = not(_f4_shadowable_masks_T_29) node _f4_shadowable_masks_T_31 = or(_f4_shadowable_masks_T_28, _f4_shadowable_masks_T_30) wire f4_shadowable_masks : UInt<8>[8] connect f4_shadowable_masks[0], _f4_shadowable_masks_T_3 connect f4_shadowable_masks[1], _f4_shadowable_masks_T_7 connect f4_shadowable_masks[2], _f4_shadowable_masks_T_11 connect f4_shadowable_masks[3], _f4_shadowable_masks_T_15 connect f4_shadowable_masks[4], _f4_shadowable_masks_T_19 connect f4_shadowable_masks[5], _f4_shadowable_masks_T_23 connect f4_shadowable_masks[6], _f4_shadowable_masks_T_27 connect f4_shadowable_masks[7], _f4_shadowable_masks_T_31 node f3_shadowable_masks_lo_lo = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo = cat(f3_shadowable_masks_lo_hi, f3_shadowable_masks_lo_lo) node f3_shadowable_masks_hi_lo = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi = cat(f3_shadowable_masks_hi_hi, f3_shadowable_masks_hi_lo) node _f3_shadowable_masks_T = cat(f3_shadowable_masks_hi, f3_shadowable_masks_lo) node _f3_shadowable_masks_T_1 = mux(f4.io.enq.valid, _f3_shadowable_masks_T, UInt<1>(0h0)) node _f3_shadowable_masks_T_2 = bits(f4.io.deq.bits.sfb_masks[0], 15, 8) node _f3_shadowable_masks_T_3 = not(_f3_shadowable_masks_T_2) node _f3_shadowable_masks_T_4 = or(_f3_shadowable_masks_T_1, _f3_shadowable_masks_T_3) node f3_shadowable_masks_lo_lo_1 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_1 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_1 = cat(f3_shadowable_masks_lo_hi_1, f3_shadowable_masks_lo_lo_1) node f3_shadowable_masks_hi_lo_1 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_1 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_1 = cat(f3_shadowable_masks_hi_hi_1, f3_shadowable_masks_hi_lo_1) node _f3_shadowable_masks_T_5 = cat(f3_shadowable_masks_hi_1, f3_shadowable_masks_lo_1) node _f3_shadowable_masks_T_6 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_5, UInt<1>(0h0)) node _f3_shadowable_masks_T_7 = bits(f4.io.deq.bits.sfb_masks[1], 15, 8) node _f3_shadowable_masks_T_8 = not(_f3_shadowable_masks_T_7) node _f3_shadowable_masks_T_9 = or(_f3_shadowable_masks_T_6, _f3_shadowable_masks_T_8) node f3_shadowable_masks_lo_lo_2 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_2 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_2 = cat(f3_shadowable_masks_lo_hi_2, f3_shadowable_masks_lo_lo_2) node f3_shadowable_masks_hi_lo_2 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_2 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_2 = cat(f3_shadowable_masks_hi_hi_2, f3_shadowable_masks_hi_lo_2) node _f3_shadowable_masks_T_10 = cat(f3_shadowable_masks_hi_2, f3_shadowable_masks_lo_2) node _f3_shadowable_masks_T_11 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_10, UInt<1>(0h0)) node _f3_shadowable_masks_T_12 = bits(f4.io.deq.bits.sfb_masks[2], 15, 8) node _f3_shadowable_masks_T_13 = not(_f3_shadowable_masks_T_12) node _f3_shadowable_masks_T_14 = or(_f3_shadowable_masks_T_11, _f3_shadowable_masks_T_13) node f3_shadowable_masks_lo_lo_3 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_3 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_3 = cat(f3_shadowable_masks_lo_hi_3, f3_shadowable_masks_lo_lo_3) node f3_shadowable_masks_hi_lo_3 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_3 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_3 = cat(f3_shadowable_masks_hi_hi_3, f3_shadowable_masks_hi_lo_3) node _f3_shadowable_masks_T_15 = cat(f3_shadowable_masks_hi_3, f3_shadowable_masks_lo_3) node _f3_shadowable_masks_T_16 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_15, UInt<1>(0h0)) node _f3_shadowable_masks_T_17 = bits(f4.io.deq.bits.sfb_masks[3], 15, 8) node _f3_shadowable_masks_T_18 = not(_f3_shadowable_masks_T_17) node _f3_shadowable_masks_T_19 = or(_f3_shadowable_masks_T_16, _f3_shadowable_masks_T_18) node f3_shadowable_masks_lo_lo_4 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_4 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_4 = cat(f3_shadowable_masks_lo_hi_4, f3_shadowable_masks_lo_lo_4) node f3_shadowable_masks_hi_lo_4 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_4 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_4 = cat(f3_shadowable_masks_hi_hi_4, f3_shadowable_masks_hi_lo_4) node _f3_shadowable_masks_T_20 = cat(f3_shadowable_masks_hi_4, f3_shadowable_masks_lo_4) node _f3_shadowable_masks_T_21 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_20, UInt<1>(0h0)) node _f3_shadowable_masks_T_22 = bits(f4.io.deq.bits.sfb_masks[4], 15, 8) node _f3_shadowable_masks_T_23 = not(_f3_shadowable_masks_T_22) node _f3_shadowable_masks_T_24 = or(_f3_shadowable_masks_T_21, _f3_shadowable_masks_T_23) node f3_shadowable_masks_lo_lo_5 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_5 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_5 = cat(f3_shadowable_masks_lo_hi_5, f3_shadowable_masks_lo_lo_5) node f3_shadowable_masks_hi_lo_5 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_5 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_5 = cat(f3_shadowable_masks_hi_hi_5, f3_shadowable_masks_hi_lo_5) node _f3_shadowable_masks_T_25 = cat(f3_shadowable_masks_hi_5, f3_shadowable_masks_lo_5) node _f3_shadowable_masks_T_26 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_25, UInt<1>(0h0)) node _f3_shadowable_masks_T_27 = bits(f4.io.deq.bits.sfb_masks[5], 15, 8) node _f3_shadowable_masks_T_28 = not(_f3_shadowable_masks_T_27) node _f3_shadowable_masks_T_29 = or(_f3_shadowable_masks_T_26, _f3_shadowable_masks_T_28) node f3_shadowable_masks_lo_lo_6 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_6 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_6 = cat(f3_shadowable_masks_lo_hi_6, f3_shadowable_masks_lo_lo_6) node f3_shadowable_masks_hi_lo_6 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_6 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_6 = cat(f3_shadowable_masks_hi_hi_6, f3_shadowable_masks_hi_lo_6) node _f3_shadowable_masks_T_30 = cat(f3_shadowable_masks_hi_6, f3_shadowable_masks_lo_6) node _f3_shadowable_masks_T_31 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_30, UInt<1>(0h0)) node _f3_shadowable_masks_T_32 = bits(f4.io.deq.bits.sfb_masks[6], 15, 8) node _f3_shadowable_masks_T_33 = not(_f3_shadowable_masks_T_32) node _f3_shadowable_masks_T_34 = or(_f3_shadowable_masks_T_31, _f3_shadowable_masks_T_33) node f3_shadowable_masks_lo_lo_7 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_lo_hi_7 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node f3_shadowable_masks_lo_7 = cat(f3_shadowable_masks_lo_hi_7, f3_shadowable_masks_lo_lo_7) node f3_shadowable_masks_hi_lo_7 = cat(f4.io.enq.bits.shadowable_mask[5], f4.io.enq.bits.shadowable_mask[4]) node f3_shadowable_masks_hi_hi_7 = cat(f4.io.enq.bits.shadowable_mask[7], f4.io.enq.bits.shadowable_mask[6]) node f3_shadowable_masks_hi_7 = cat(f3_shadowable_masks_hi_hi_7, f3_shadowable_masks_hi_lo_7) node _f3_shadowable_masks_T_35 = cat(f3_shadowable_masks_hi_7, f3_shadowable_masks_lo_7) node _f3_shadowable_masks_T_36 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_35, UInt<1>(0h0)) node _f3_shadowable_masks_T_37 = bits(f4.io.deq.bits.sfb_masks[7], 15, 8) node _f3_shadowable_masks_T_38 = not(_f3_shadowable_masks_T_37) node _f3_shadowable_masks_T_39 = or(_f3_shadowable_masks_T_36, _f3_shadowable_masks_T_38) wire f3_shadowable_masks : UInt<8>[8] connect f3_shadowable_masks[0], _f3_shadowable_masks_T_4 connect f3_shadowable_masks[1], _f3_shadowable_masks_T_9 connect f3_shadowable_masks[2], _f3_shadowable_masks_T_14 connect f3_shadowable_masks[3], _f3_shadowable_masks_T_19 connect f3_shadowable_masks[4], _f3_shadowable_masks_T_24 connect f3_shadowable_masks[5], _f3_shadowable_masks_T_29 connect f3_shadowable_masks[6], _f3_shadowable_masks_T_34 connect f3_shadowable_masks[7], _f3_shadowable_masks_T_39 node _f4_sfbs_T = not(f4_shadowable_masks[0]) node _f4_sfbs_T_1 = eq(_f4_sfbs_T, UInt<1>(0h0)) node _f4_sfbs_T_2 = not(f3_shadowable_masks[0]) node _f4_sfbs_T_3 = eq(_f4_sfbs_T_2, UInt<1>(0h0)) node _f4_sfbs_T_4 = and(_f4_sfbs_T_1, _f4_sfbs_T_3) node _f4_sfbs_T_5 = and(_f4_sfbs_T_4, f4.io.deq.bits.sfbs[0]) node _f4_sfbs_T_6 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<1>(0h0)) node _f4_sfbs_T_7 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_6) node _f4_sfbs_T_8 = eq(_f4_sfbs_T_7, UInt<1>(0h0)) node _f4_sfbs_T_9 = and(_f4_sfbs_T_5, _f4_sfbs_T_8) node _f4_sfbs_T_10 = eq(f4.io.deq.bits.sfb_dests[0], UInt<1>(0h0)) node _f4_sfbs_T_11 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_12 = eq(f4.io.deq.bits.sfb_dests[0], UInt<5>(0h10)) node _f4_sfbs_T_13 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_14 = mux(_f4_sfbs_T_12, _f4_sfbs_T_13, UInt<1>(0h1)) node _f4_sfbs_T_15 = mux(_f4_sfbs_T_10, _f4_sfbs_T_11, _f4_sfbs_T_14) node _f4_sfbs_T_16 = and(_f4_sfbs_T_9, _f4_sfbs_T_15) node _f4_sfbs_T_17 = and(UInt<1>(0h0), _f4_sfbs_T_16) node _f4_sfbs_T_18 = not(f4_shadowable_masks[1]) node _f4_sfbs_T_19 = eq(_f4_sfbs_T_18, UInt<1>(0h0)) node _f4_sfbs_T_20 = not(f3_shadowable_masks[1]) node _f4_sfbs_T_21 = eq(_f4_sfbs_T_20, UInt<1>(0h0)) node _f4_sfbs_T_22 = and(_f4_sfbs_T_19, _f4_sfbs_T_21) node _f4_sfbs_T_23 = and(_f4_sfbs_T_22, f4.io.deq.bits.sfbs[1]) node _f4_sfbs_T_24 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<1>(0h1)) node _f4_sfbs_T_25 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_24) node _f4_sfbs_T_26 = eq(_f4_sfbs_T_25, UInt<1>(0h0)) node _f4_sfbs_T_27 = and(_f4_sfbs_T_23, _f4_sfbs_T_26) node _f4_sfbs_T_28 = eq(f4.io.deq.bits.sfb_dests[1], UInt<1>(0h0)) node _f4_sfbs_T_29 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_30 = eq(f4.io.deq.bits.sfb_dests[1], UInt<5>(0h10)) node _f4_sfbs_T_31 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_32 = mux(_f4_sfbs_T_30, _f4_sfbs_T_31, UInt<1>(0h1)) node _f4_sfbs_T_33 = mux(_f4_sfbs_T_28, _f4_sfbs_T_29, _f4_sfbs_T_32) node _f4_sfbs_T_34 = and(_f4_sfbs_T_27, _f4_sfbs_T_33) node _f4_sfbs_T_35 = and(UInt<1>(0h0), _f4_sfbs_T_34) node _f4_sfbs_T_36 = not(f4_shadowable_masks[2]) node _f4_sfbs_T_37 = eq(_f4_sfbs_T_36, UInt<1>(0h0)) node _f4_sfbs_T_38 = not(f3_shadowable_masks[2]) node _f4_sfbs_T_39 = eq(_f4_sfbs_T_38, UInt<1>(0h0)) node _f4_sfbs_T_40 = and(_f4_sfbs_T_37, _f4_sfbs_T_39) node _f4_sfbs_T_41 = and(_f4_sfbs_T_40, f4.io.deq.bits.sfbs[2]) node _f4_sfbs_T_42 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<2>(0h2)) node _f4_sfbs_T_43 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_42) node _f4_sfbs_T_44 = eq(_f4_sfbs_T_43, UInt<1>(0h0)) node _f4_sfbs_T_45 = and(_f4_sfbs_T_41, _f4_sfbs_T_44) node _f4_sfbs_T_46 = eq(f4.io.deq.bits.sfb_dests[2], UInt<1>(0h0)) node _f4_sfbs_T_47 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_48 = eq(f4.io.deq.bits.sfb_dests[2], UInt<5>(0h10)) node _f4_sfbs_T_49 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_50 = mux(_f4_sfbs_T_48, _f4_sfbs_T_49, UInt<1>(0h1)) node _f4_sfbs_T_51 = mux(_f4_sfbs_T_46, _f4_sfbs_T_47, _f4_sfbs_T_50) node _f4_sfbs_T_52 = and(_f4_sfbs_T_45, _f4_sfbs_T_51) node _f4_sfbs_T_53 = and(UInt<1>(0h0), _f4_sfbs_T_52) node _f4_sfbs_T_54 = not(f4_shadowable_masks[3]) node _f4_sfbs_T_55 = eq(_f4_sfbs_T_54, UInt<1>(0h0)) node _f4_sfbs_T_56 = not(f3_shadowable_masks[3]) node _f4_sfbs_T_57 = eq(_f4_sfbs_T_56, UInt<1>(0h0)) node _f4_sfbs_T_58 = and(_f4_sfbs_T_55, _f4_sfbs_T_57) node _f4_sfbs_T_59 = and(_f4_sfbs_T_58, f4.io.deq.bits.sfbs[3]) node _f4_sfbs_T_60 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<2>(0h3)) node _f4_sfbs_T_61 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_60) node _f4_sfbs_T_62 = eq(_f4_sfbs_T_61, UInt<1>(0h0)) node _f4_sfbs_T_63 = and(_f4_sfbs_T_59, _f4_sfbs_T_62) node _f4_sfbs_T_64 = eq(f4.io.deq.bits.sfb_dests[3], UInt<1>(0h0)) node _f4_sfbs_T_65 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_66 = eq(f4.io.deq.bits.sfb_dests[3], UInt<5>(0h10)) node _f4_sfbs_T_67 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_68 = mux(_f4_sfbs_T_66, _f4_sfbs_T_67, UInt<1>(0h1)) node _f4_sfbs_T_69 = mux(_f4_sfbs_T_64, _f4_sfbs_T_65, _f4_sfbs_T_68) node _f4_sfbs_T_70 = and(_f4_sfbs_T_63, _f4_sfbs_T_69) node _f4_sfbs_T_71 = and(UInt<1>(0h0), _f4_sfbs_T_70) node _f4_sfbs_T_72 = not(f4_shadowable_masks[4]) node _f4_sfbs_T_73 = eq(_f4_sfbs_T_72, UInt<1>(0h0)) node _f4_sfbs_T_74 = not(f3_shadowable_masks[4]) node _f4_sfbs_T_75 = eq(_f4_sfbs_T_74, UInt<1>(0h0)) node _f4_sfbs_T_76 = and(_f4_sfbs_T_73, _f4_sfbs_T_75) node _f4_sfbs_T_77 = and(_f4_sfbs_T_76, f4.io.deq.bits.sfbs[4]) node _f4_sfbs_T_78 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h4)) node _f4_sfbs_T_79 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_78) node _f4_sfbs_T_80 = eq(_f4_sfbs_T_79, UInt<1>(0h0)) node _f4_sfbs_T_81 = and(_f4_sfbs_T_77, _f4_sfbs_T_80) node _f4_sfbs_T_82 = eq(f4.io.deq.bits.sfb_dests[4], UInt<1>(0h0)) node _f4_sfbs_T_83 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_84 = eq(f4.io.deq.bits.sfb_dests[4], UInt<5>(0h10)) node _f4_sfbs_T_85 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_86 = mux(_f4_sfbs_T_84, _f4_sfbs_T_85, UInt<1>(0h1)) node _f4_sfbs_T_87 = mux(_f4_sfbs_T_82, _f4_sfbs_T_83, _f4_sfbs_T_86) node _f4_sfbs_T_88 = and(_f4_sfbs_T_81, _f4_sfbs_T_87) node _f4_sfbs_T_89 = and(UInt<1>(0h0), _f4_sfbs_T_88) node _f4_sfbs_T_90 = not(f4_shadowable_masks[5]) node _f4_sfbs_T_91 = eq(_f4_sfbs_T_90, UInt<1>(0h0)) node _f4_sfbs_T_92 = not(f3_shadowable_masks[5]) node _f4_sfbs_T_93 = eq(_f4_sfbs_T_92, UInt<1>(0h0)) node _f4_sfbs_T_94 = and(_f4_sfbs_T_91, _f4_sfbs_T_93) node _f4_sfbs_T_95 = and(_f4_sfbs_T_94, f4.io.deq.bits.sfbs[5]) node _f4_sfbs_T_96 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h5)) node _f4_sfbs_T_97 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_96) node _f4_sfbs_T_98 = eq(_f4_sfbs_T_97, UInt<1>(0h0)) node _f4_sfbs_T_99 = and(_f4_sfbs_T_95, _f4_sfbs_T_98) node _f4_sfbs_T_100 = eq(f4.io.deq.bits.sfb_dests[5], UInt<1>(0h0)) node _f4_sfbs_T_101 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_102 = eq(f4.io.deq.bits.sfb_dests[5], UInt<5>(0h10)) node _f4_sfbs_T_103 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_104 = mux(_f4_sfbs_T_102, _f4_sfbs_T_103, UInt<1>(0h1)) node _f4_sfbs_T_105 = mux(_f4_sfbs_T_100, _f4_sfbs_T_101, _f4_sfbs_T_104) node _f4_sfbs_T_106 = and(_f4_sfbs_T_99, _f4_sfbs_T_105) node _f4_sfbs_T_107 = and(UInt<1>(0h0), _f4_sfbs_T_106) node _f4_sfbs_T_108 = not(f4_shadowable_masks[6]) node _f4_sfbs_T_109 = eq(_f4_sfbs_T_108, UInt<1>(0h0)) node _f4_sfbs_T_110 = not(f3_shadowable_masks[6]) node _f4_sfbs_T_111 = eq(_f4_sfbs_T_110, UInt<1>(0h0)) node _f4_sfbs_T_112 = and(_f4_sfbs_T_109, _f4_sfbs_T_111) node _f4_sfbs_T_113 = and(_f4_sfbs_T_112, f4.io.deq.bits.sfbs[6]) node _f4_sfbs_T_114 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h6)) node _f4_sfbs_T_115 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_114) node _f4_sfbs_T_116 = eq(_f4_sfbs_T_115, UInt<1>(0h0)) node _f4_sfbs_T_117 = and(_f4_sfbs_T_113, _f4_sfbs_T_116) node _f4_sfbs_T_118 = eq(f4.io.deq.bits.sfb_dests[6], UInt<1>(0h0)) node _f4_sfbs_T_119 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_120 = eq(f4.io.deq.bits.sfb_dests[6], UInt<5>(0h10)) node _f4_sfbs_T_121 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_122 = mux(_f4_sfbs_T_120, _f4_sfbs_T_121, UInt<1>(0h1)) node _f4_sfbs_T_123 = mux(_f4_sfbs_T_118, _f4_sfbs_T_119, _f4_sfbs_T_122) node _f4_sfbs_T_124 = and(_f4_sfbs_T_117, _f4_sfbs_T_123) node _f4_sfbs_T_125 = and(UInt<1>(0h0), _f4_sfbs_T_124) node _f4_sfbs_T_126 = not(f4_shadowable_masks[7]) node _f4_sfbs_T_127 = eq(_f4_sfbs_T_126, UInt<1>(0h0)) node _f4_sfbs_T_128 = not(f3_shadowable_masks[7]) node _f4_sfbs_T_129 = eq(_f4_sfbs_T_128, UInt<1>(0h0)) node _f4_sfbs_T_130 = and(_f4_sfbs_T_127, _f4_sfbs_T_129) node _f4_sfbs_T_131 = and(_f4_sfbs_T_130, f4.io.deq.bits.sfbs[7]) node _f4_sfbs_T_132 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<3>(0h7)) node _f4_sfbs_T_133 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_132) node _f4_sfbs_T_134 = eq(_f4_sfbs_T_133, UInt<1>(0h0)) node _f4_sfbs_T_135 = and(_f4_sfbs_T_131, _f4_sfbs_T_134) node _f4_sfbs_T_136 = eq(f4.io.deq.bits.sfb_dests[7], UInt<1>(0h0)) node _f4_sfbs_T_137 = eq(_T_63, UInt<1>(0h0)) node _f4_sfbs_T_138 = eq(f4.io.deq.bits.sfb_dests[7], UInt<5>(0h10)) node _f4_sfbs_T_139 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_140 = mux(_f4_sfbs_T_138, _f4_sfbs_T_139, UInt<1>(0h1)) node _f4_sfbs_T_141 = mux(_f4_sfbs_T_136, _f4_sfbs_T_137, _f4_sfbs_T_140) node _f4_sfbs_T_142 = and(_f4_sfbs_T_135, _f4_sfbs_T_141) node _f4_sfbs_T_143 = and(UInt<1>(0h0), _f4_sfbs_T_142) wire f4_sfbs : UInt<1>[8] connect f4_sfbs[0], _f4_sfbs_T_17 connect f4_sfbs[1], _f4_sfbs_T_35 connect f4_sfbs[2], _f4_sfbs_T_53 connect f4_sfbs[3], _f4_sfbs_T_71 connect f4_sfbs[4], _f4_sfbs_T_89 connect f4_sfbs[5], _f4_sfbs_T_107 connect f4_sfbs[6], _f4_sfbs_T_125 connect f4_sfbs[7], _f4_sfbs_T_143 node _f4_sfb_valid_T = or(f4_sfbs[0], f4_sfbs[1]) node _f4_sfb_valid_T_1 = or(_f4_sfb_valid_T, f4_sfbs[2]) node _f4_sfb_valid_T_2 = or(_f4_sfb_valid_T_1, f4_sfbs[3]) node _f4_sfb_valid_T_3 = or(_f4_sfb_valid_T_2, f4_sfbs[4]) node _f4_sfb_valid_T_4 = or(_f4_sfb_valid_T_3, f4_sfbs[5]) node _f4_sfb_valid_T_5 = or(_f4_sfb_valid_T_4, f4_sfbs[6]) node _f4_sfb_valid_T_6 = or(_f4_sfb_valid_T_5, f4_sfbs[7]) node f4_sfb_valid = and(_f4_sfb_valid_T_6, f4.io.deq.valid) node _f4_sfb_idx_T = mux(f4_sfbs[6], UInt<3>(0h6), UInt<3>(0h7)) node _f4_sfb_idx_T_1 = mux(f4_sfbs[5], UInt<3>(0h5), _f4_sfb_idx_T) node _f4_sfb_idx_T_2 = mux(f4_sfbs[4], UInt<3>(0h4), _f4_sfb_idx_T_1) node _f4_sfb_idx_T_3 = mux(f4_sfbs[3], UInt<2>(0h3), _f4_sfb_idx_T_2) node _f4_sfb_idx_T_4 = mux(f4_sfbs[2], UInt<2>(0h2), _f4_sfb_idx_T_3) node _f4_sfb_idx_T_5 = mux(f4_sfbs[1], UInt<1>(0h1), _f4_sfb_idx_T_4) node f4_sfb_idx = mux(f4_sfbs[0], UInt<1>(0h0), _f4_sfb_idx_T_5) node _f4_delay_T = or(f4.io.deq.bits.sfbs[0], f4.io.deq.bits.sfbs[1]) node _f4_delay_T_1 = or(_f4_delay_T, f4.io.deq.bits.sfbs[2]) node _f4_delay_T_2 = or(_f4_delay_T_1, f4.io.deq.bits.sfbs[3]) node _f4_delay_T_3 = or(_f4_delay_T_2, f4.io.deq.bits.sfbs[4]) node _f4_delay_T_4 = or(_f4_delay_T_3, f4.io.deq.bits.sfbs[5]) node _f4_delay_T_5 = or(_f4_delay_T_4, f4.io.deq.bits.sfbs[6]) node _f4_delay_T_6 = or(_f4_delay_T_5, f4.io.deq.bits.sfbs[7]) node _f4_delay_T_7 = eq(f4.io.deq.bits.cfi_idx.valid, UInt<1>(0h0)) node _f4_delay_T_8 = and(_f4_delay_T_6, _f4_delay_T_7) node _f4_delay_T_9 = eq(f4.io.enq.valid, UInt<1>(0h0)) node _f4_delay_T_10 = and(_f4_delay_T_8, _f4_delay_T_9) node _f4_delay_T_11 = eq(f4.io.deq.bits.xcpt_pf_if, UInt<1>(0h0)) node _f4_delay_T_12 = and(_f4_delay_T_10, _f4_delay_T_11) node _f4_delay_T_13 = eq(f4.io.deq.bits.xcpt_ae_if, UInt<1>(0h0)) node f4_delay = and(_f4_delay_T_12, _f4_delay_T_13) when f4_sfb_valid : node _T_106 = bits(f4.io.deq.bits.sfb_masks[f4_sfb_idx], 15, 8) node _T_107 = bits(_T_106, 0, 0) node _T_108 = bits(_T_106, 1, 1) node _T_109 = bits(_T_106, 2, 2) node _T_110 = bits(_T_106, 3, 3) node _T_111 = bits(_T_106, 4, 4) node _T_112 = bits(_T_106, 5, 5) node _T_113 = bits(_T_106, 6, 6) node _T_114 = bits(_T_106, 7, 7) connect f3_shadowed_mask[0], _T_107 connect f3_shadowed_mask[1], _T_108 connect f3_shadowed_mask[2], _T_109 connect f3_shadowed_mask[3], _T_110 connect f3_shadowed_mask[4], _T_111 connect f3_shadowed_mask[5], _T_112 connect f3_shadowed_mask[6], _T_113 connect f3_shadowed_mask[7], _T_114 else : wire _WIRE : UInt<1>[8] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect f3_shadowed_mask, _WIRE connect f4_ready, f4.io.enq.ready node _f4_io_enq_valid_T = eq(f3_clear, UInt<1>(0h0)) node _f4_io_enq_valid_T_1 = and(f3.io.deq.valid, _f4_io_enq_valid_T) connect f4.io.enq.valid, _f4_io_enq_valid_T_1 connect f4.io.enq.bits.tsrc, f3_fetch_bundle.tsrc connect f4.io.enq.bits.fsrc, f3_fetch_bundle.fsrc connect f4.io.enq.bits.bpd_meta[0], f3_fetch_bundle.bpd_meta[0] connect f4.io.enq.bits.bpd_meta[1], f3_fetch_bundle.bpd_meta[1] connect f4.io.enq.bits.end_half.bits, f3_fetch_bundle.end_half.bits connect f4.io.enq.bits.end_half.valid, f3_fetch_bundle.end_half.valid connect f4.io.enq.bits.bp_xcpt_if_oh[0], f3_fetch_bundle.bp_xcpt_if_oh[0] connect f4.io.enq.bits.bp_xcpt_if_oh[1], f3_fetch_bundle.bp_xcpt_if_oh[1] connect f4.io.enq.bits.bp_xcpt_if_oh[2], f3_fetch_bundle.bp_xcpt_if_oh[2] connect f4.io.enq.bits.bp_xcpt_if_oh[3], f3_fetch_bundle.bp_xcpt_if_oh[3] connect f4.io.enq.bits.bp_xcpt_if_oh[4], f3_fetch_bundle.bp_xcpt_if_oh[4] connect f4.io.enq.bits.bp_xcpt_if_oh[5], f3_fetch_bundle.bp_xcpt_if_oh[5] connect f4.io.enq.bits.bp_xcpt_if_oh[6], f3_fetch_bundle.bp_xcpt_if_oh[6] connect f4.io.enq.bits.bp_xcpt_if_oh[7], f3_fetch_bundle.bp_xcpt_if_oh[7] connect f4.io.enq.bits.bp_debug_if_oh[0], f3_fetch_bundle.bp_debug_if_oh[0] connect f4.io.enq.bits.bp_debug_if_oh[1], f3_fetch_bundle.bp_debug_if_oh[1] connect f4.io.enq.bits.bp_debug_if_oh[2], f3_fetch_bundle.bp_debug_if_oh[2] connect f4.io.enq.bits.bp_debug_if_oh[3], f3_fetch_bundle.bp_debug_if_oh[3] connect f4.io.enq.bits.bp_debug_if_oh[4], f3_fetch_bundle.bp_debug_if_oh[4] connect f4.io.enq.bits.bp_debug_if_oh[5], f3_fetch_bundle.bp_debug_if_oh[5] connect f4.io.enq.bits.bp_debug_if_oh[6], f3_fetch_bundle.bp_debug_if_oh[6] connect f4.io.enq.bits.bp_debug_if_oh[7], f3_fetch_bundle.bp_debug_if_oh[7] connect f4.io.enq.bits.xcpt_ae_if, f3_fetch_bundle.xcpt_ae_if connect f4.io.enq.bits.xcpt_pf_if, f3_fetch_bundle.xcpt_pf_if connect f4.io.enq.bits.lhist[0], f3_fetch_bundle.lhist[0] connect f4.io.enq.bits.lhist[1], f3_fetch_bundle.lhist[1] connect f4.io.enq.bits.ghist.ras_idx, f3_fetch_bundle.ghist.ras_idx connect f4.io.enq.bits.ghist.new_saw_branch_taken, f3_fetch_bundle.ghist.new_saw_branch_taken connect f4.io.enq.bits.ghist.new_saw_branch_not_taken, f3_fetch_bundle.ghist.new_saw_branch_not_taken connect f4.io.enq.bits.ghist.current_saw_branch_not_taken, f3_fetch_bundle.ghist.current_saw_branch_not_taken connect f4.io.enq.bits.ghist.old_history, f3_fetch_bundle.ghist.old_history connect f4.io.enq.bits.br_mask, f3_fetch_bundle.br_mask connect f4.io.enq.bits.mask, f3_fetch_bundle.mask connect f4.io.enq.bits.ftq_idx, f3_fetch_bundle.ftq_idx connect f4.io.enq.bits.ras_top, f3_fetch_bundle.ras_top connect f4.io.enq.bits.cfi_npc_plus4, f3_fetch_bundle.cfi_npc_plus4 connect f4.io.enq.bits.cfi_is_ret, f3_fetch_bundle.cfi_is_ret connect f4.io.enq.bits.cfi_is_call, f3_fetch_bundle.cfi_is_call connect f4.io.enq.bits.cfi_type, f3_fetch_bundle.cfi_type connect f4.io.enq.bits.cfi_idx.bits, f3_fetch_bundle.cfi_idx.bits connect f4.io.enq.bits.cfi_idx.valid, f3_fetch_bundle.cfi_idx.valid connect f4.io.enq.bits.shadowed_mask[0], f3_fetch_bundle.shadowed_mask[0] connect f4.io.enq.bits.shadowed_mask[1], f3_fetch_bundle.shadowed_mask[1] connect f4.io.enq.bits.shadowed_mask[2], f3_fetch_bundle.shadowed_mask[2] connect f4.io.enq.bits.shadowed_mask[3], f3_fetch_bundle.shadowed_mask[3] connect f4.io.enq.bits.shadowed_mask[4], f3_fetch_bundle.shadowed_mask[4] connect f4.io.enq.bits.shadowed_mask[5], f3_fetch_bundle.shadowed_mask[5] connect f4.io.enq.bits.shadowed_mask[6], f3_fetch_bundle.shadowed_mask[6] connect f4.io.enq.bits.shadowed_mask[7], f3_fetch_bundle.shadowed_mask[7] connect f4.io.enq.bits.shadowable_mask[0], f3_fetch_bundle.shadowable_mask[0] connect f4.io.enq.bits.shadowable_mask[1], f3_fetch_bundle.shadowable_mask[1] connect f4.io.enq.bits.shadowable_mask[2], f3_fetch_bundle.shadowable_mask[2] connect f4.io.enq.bits.shadowable_mask[3], f3_fetch_bundle.shadowable_mask[3] connect f4.io.enq.bits.shadowable_mask[4], f3_fetch_bundle.shadowable_mask[4] connect f4.io.enq.bits.shadowable_mask[5], f3_fetch_bundle.shadowable_mask[5] connect f4.io.enq.bits.shadowable_mask[6], f3_fetch_bundle.shadowable_mask[6] connect f4.io.enq.bits.shadowable_mask[7], f3_fetch_bundle.shadowable_mask[7] connect f4.io.enq.bits.sfb_dests[0], f3_fetch_bundle.sfb_dests[0] connect f4.io.enq.bits.sfb_dests[1], f3_fetch_bundle.sfb_dests[1] connect f4.io.enq.bits.sfb_dests[2], f3_fetch_bundle.sfb_dests[2] connect f4.io.enq.bits.sfb_dests[3], f3_fetch_bundle.sfb_dests[3] connect f4.io.enq.bits.sfb_dests[4], f3_fetch_bundle.sfb_dests[4] connect f4.io.enq.bits.sfb_dests[5], f3_fetch_bundle.sfb_dests[5] connect f4.io.enq.bits.sfb_dests[6], f3_fetch_bundle.sfb_dests[6] connect f4.io.enq.bits.sfb_dests[7], f3_fetch_bundle.sfb_dests[7] connect f4.io.enq.bits.sfb_masks[0], f3_fetch_bundle.sfb_masks[0] connect f4.io.enq.bits.sfb_masks[1], f3_fetch_bundle.sfb_masks[1] connect f4.io.enq.bits.sfb_masks[2], f3_fetch_bundle.sfb_masks[2] connect f4.io.enq.bits.sfb_masks[3], f3_fetch_bundle.sfb_masks[3] connect f4.io.enq.bits.sfb_masks[4], f3_fetch_bundle.sfb_masks[4] connect f4.io.enq.bits.sfb_masks[5], f3_fetch_bundle.sfb_masks[5] connect f4.io.enq.bits.sfb_masks[6], f3_fetch_bundle.sfb_masks[6] connect f4.io.enq.bits.sfb_masks[7], f3_fetch_bundle.sfb_masks[7] connect f4.io.enq.bits.sfbs[0], f3_fetch_bundle.sfbs[0] connect f4.io.enq.bits.sfbs[1], f3_fetch_bundle.sfbs[1] connect f4.io.enq.bits.sfbs[2], f3_fetch_bundle.sfbs[2] connect f4.io.enq.bits.sfbs[3], f3_fetch_bundle.sfbs[3] connect f4.io.enq.bits.sfbs[4], f3_fetch_bundle.sfbs[4] connect f4.io.enq.bits.sfbs[5], f3_fetch_bundle.sfbs[5] connect f4.io.enq.bits.sfbs[6], f3_fetch_bundle.sfbs[6] connect f4.io.enq.bits.sfbs[7], f3_fetch_bundle.sfbs[7] connect f4.io.enq.bits.exp_insts[0], f3_fetch_bundle.exp_insts[0] connect f4.io.enq.bits.exp_insts[1], f3_fetch_bundle.exp_insts[1] connect f4.io.enq.bits.exp_insts[2], f3_fetch_bundle.exp_insts[2] connect f4.io.enq.bits.exp_insts[3], f3_fetch_bundle.exp_insts[3] connect f4.io.enq.bits.exp_insts[4], f3_fetch_bundle.exp_insts[4] connect f4.io.enq.bits.exp_insts[5], f3_fetch_bundle.exp_insts[5] connect f4.io.enq.bits.exp_insts[6], f3_fetch_bundle.exp_insts[6] connect f4.io.enq.bits.exp_insts[7], f3_fetch_bundle.exp_insts[7] connect f4.io.enq.bits.insts[0], f3_fetch_bundle.insts[0] connect f4.io.enq.bits.insts[1], f3_fetch_bundle.insts[1] connect f4.io.enq.bits.insts[2], f3_fetch_bundle.insts[2] connect f4.io.enq.bits.insts[3], f3_fetch_bundle.insts[3] connect f4.io.enq.bits.insts[4], f3_fetch_bundle.insts[4] connect f4.io.enq.bits.insts[5], f3_fetch_bundle.insts[5] connect f4.io.enq.bits.insts[6], f3_fetch_bundle.insts[6] connect f4.io.enq.bits.insts[7], f3_fetch_bundle.insts[7] connect f4.io.enq.bits.edge_inst[0], f3_fetch_bundle.edge_inst[0] connect f4.io.enq.bits.edge_inst[1], f3_fetch_bundle.edge_inst[1] connect f4.io.enq.bits.next_pc, f3_fetch_bundle.next_pc connect f4.io.enq.bits.pc, f3_fetch_bundle.pc node _f4_io_deq_ready_T = and(fb.io.enq.ready, ftq.io.enq.ready) node _f4_io_deq_ready_T_1 = eq(f4_delay, UInt<1>(0h0)) node _f4_io_deq_ready_T_2 = and(_f4_io_deq_ready_T, _f4_io_deq_ready_T_1) connect f4.io.deq.ready, _f4_io_deq_ready_T_2 node _fb_io_enq_valid_T = and(f4.io.deq.valid, ftq.io.enq.ready) node _fb_io_enq_valid_T_1 = eq(f4_delay, UInt<1>(0h0)) node _fb_io_enq_valid_T_2 = and(_fb_io_enq_valid_T, _fb_io_enq_valid_T_1) connect fb.io.enq.valid, _fb_io_enq_valid_T_2 connect fb.io.enq.bits.tsrc, f4.io.deq.bits.tsrc connect fb.io.enq.bits.fsrc, f4.io.deq.bits.fsrc connect fb.io.enq.bits.bpd_meta[0], f4.io.deq.bits.bpd_meta[0] connect fb.io.enq.bits.bpd_meta[1], f4.io.deq.bits.bpd_meta[1] connect fb.io.enq.bits.end_half.bits, f4.io.deq.bits.end_half.bits connect fb.io.enq.bits.end_half.valid, f4.io.deq.bits.end_half.valid connect fb.io.enq.bits.bp_xcpt_if_oh[0], f4.io.deq.bits.bp_xcpt_if_oh[0] connect fb.io.enq.bits.bp_xcpt_if_oh[1], f4.io.deq.bits.bp_xcpt_if_oh[1] connect fb.io.enq.bits.bp_xcpt_if_oh[2], f4.io.deq.bits.bp_xcpt_if_oh[2] connect fb.io.enq.bits.bp_xcpt_if_oh[3], f4.io.deq.bits.bp_xcpt_if_oh[3] connect fb.io.enq.bits.bp_xcpt_if_oh[4], f4.io.deq.bits.bp_xcpt_if_oh[4] connect fb.io.enq.bits.bp_xcpt_if_oh[5], f4.io.deq.bits.bp_xcpt_if_oh[5] connect fb.io.enq.bits.bp_xcpt_if_oh[6], f4.io.deq.bits.bp_xcpt_if_oh[6] connect fb.io.enq.bits.bp_xcpt_if_oh[7], f4.io.deq.bits.bp_xcpt_if_oh[7] connect fb.io.enq.bits.bp_debug_if_oh[0], f4.io.deq.bits.bp_debug_if_oh[0] connect fb.io.enq.bits.bp_debug_if_oh[1], f4.io.deq.bits.bp_debug_if_oh[1] connect fb.io.enq.bits.bp_debug_if_oh[2], f4.io.deq.bits.bp_debug_if_oh[2] connect fb.io.enq.bits.bp_debug_if_oh[3], f4.io.deq.bits.bp_debug_if_oh[3] connect fb.io.enq.bits.bp_debug_if_oh[4], f4.io.deq.bits.bp_debug_if_oh[4] connect fb.io.enq.bits.bp_debug_if_oh[5], f4.io.deq.bits.bp_debug_if_oh[5] connect fb.io.enq.bits.bp_debug_if_oh[6], f4.io.deq.bits.bp_debug_if_oh[6] connect fb.io.enq.bits.bp_debug_if_oh[7], f4.io.deq.bits.bp_debug_if_oh[7] connect fb.io.enq.bits.xcpt_ae_if, f4.io.deq.bits.xcpt_ae_if connect fb.io.enq.bits.xcpt_pf_if, f4.io.deq.bits.xcpt_pf_if connect fb.io.enq.bits.lhist[0], f4.io.deq.bits.lhist[0] connect fb.io.enq.bits.lhist[1], f4.io.deq.bits.lhist[1] connect fb.io.enq.bits.ghist.ras_idx, f4.io.deq.bits.ghist.ras_idx connect fb.io.enq.bits.ghist.new_saw_branch_taken, f4.io.deq.bits.ghist.new_saw_branch_taken connect fb.io.enq.bits.ghist.new_saw_branch_not_taken, f4.io.deq.bits.ghist.new_saw_branch_not_taken connect fb.io.enq.bits.ghist.current_saw_branch_not_taken, f4.io.deq.bits.ghist.current_saw_branch_not_taken connect fb.io.enq.bits.ghist.old_history, f4.io.deq.bits.ghist.old_history connect fb.io.enq.bits.br_mask, f4.io.deq.bits.br_mask connect fb.io.enq.bits.mask, f4.io.deq.bits.mask connect fb.io.enq.bits.ftq_idx, f4.io.deq.bits.ftq_idx connect fb.io.enq.bits.ras_top, f4.io.deq.bits.ras_top connect fb.io.enq.bits.cfi_npc_plus4, f4.io.deq.bits.cfi_npc_plus4 connect fb.io.enq.bits.cfi_is_ret, f4.io.deq.bits.cfi_is_ret connect fb.io.enq.bits.cfi_is_call, f4.io.deq.bits.cfi_is_call connect fb.io.enq.bits.cfi_type, f4.io.deq.bits.cfi_type connect fb.io.enq.bits.cfi_idx.bits, f4.io.deq.bits.cfi_idx.bits connect fb.io.enq.bits.cfi_idx.valid, f4.io.deq.bits.cfi_idx.valid connect fb.io.enq.bits.shadowed_mask[0], f4.io.deq.bits.shadowed_mask[0] connect fb.io.enq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[1] connect fb.io.enq.bits.shadowed_mask[2], f4.io.deq.bits.shadowed_mask[2] connect fb.io.enq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[3] connect fb.io.enq.bits.shadowed_mask[4], f4.io.deq.bits.shadowed_mask[4] connect fb.io.enq.bits.shadowed_mask[5], f4.io.deq.bits.shadowed_mask[5] connect fb.io.enq.bits.shadowed_mask[6], f4.io.deq.bits.shadowed_mask[6] connect fb.io.enq.bits.shadowed_mask[7], f4.io.deq.bits.shadowed_mask[7] connect fb.io.enq.bits.shadowable_mask[0], f4.io.deq.bits.shadowable_mask[0] connect fb.io.enq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[1] connect fb.io.enq.bits.shadowable_mask[2], f4.io.deq.bits.shadowable_mask[2] connect fb.io.enq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[3] connect fb.io.enq.bits.shadowable_mask[4], f4.io.deq.bits.shadowable_mask[4] connect fb.io.enq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[5] connect fb.io.enq.bits.shadowable_mask[6], f4.io.deq.bits.shadowable_mask[6] connect fb.io.enq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[7] connect fb.io.enq.bits.sfb_dests[0], f4.io.deq.bits.sfb_dests[0] connect fb.io.enq.bits.sfb_dests[1], f4.io.deq.bits.sfb_dests[1] connect fb.io.enq.bits.sfb_dests[2], f4.io.deq.bits.sfb_dests[2] connect fb.io.enq.bits.sfb_dests[3], f4.io.deq.bits.sfb_dests[3] connect fb.io.enq.bits.sfb_dests[4], f4.io.deq.bits.sfb_dests[4] connect fb.io.enq.bits.sfb_dests[5], f4.io.deq.bits.sfb_dests[5] connect fb.io.enq.bits.sfb_dests[6], f4.io.deq.bits.sfb_dests[6] connect fb.io.enq.bits.sfb_dests[7], f4.io.deq.bits.sfb_dests[7] connect fb.io.enq.bits.sfb_masks[0], f4.io.deq.bits.sfb_masks[0] connect fb.io.enq.bits.sfb_masks[1], f4.io.deq.bits.sfb_masks[1] connect fb.io.enq.bits.sfb_masks[2], f4.io.deq.bits.sfb_masks[2] connect fb.io.enq.bits.sfb_masks[3], f4.io.deq.bits.sfb_masks[3] connect fb.io.enq.bits.sfb_masks[4], f4.io.deq.bits.sfb_masks[4] connect fb.io.enq.bits.sfb_masks[5], f4.io.deq.bits.sfb_masks[5] connect fb.io.enq.bits.sfb_masks[6], f4.io.deq.bits.sfb_masks[6] connect fb.io.enq.bits.sfb_masks[7], f4.io.deq.bits.sfb_masks[7] connect fb.io.enq.bits.sfbs[0], f4.io.deq.bits.sfbs[0] connect fb.io.enq.bits.sfbs[1], f4.io.deq.bits.sfbs[1] connect fb.io.enq.bits.sfbs[2], f4.io.deq.bits.sfbs[2] connect fb.io.enq.bits.sfbs[3], f4.io.deq.bits.sfbs[3] connect fb.io.enq.bits.sfbs[4], f4.io.deq.bits.sfbs[4] connect fb.io.enq.bits.sfbs[5], f4.io.deq.bits.sfbs[5] connect fb.io.enq.bits.sfbs[6], f4.io.deq.bits.sfbs[6] connect fb.io.enq.bits.sfbs[7], f4.io.deq.bits.sfbs[7] connect fb.io.enq.bits.exp_insts[0], f4.io.deq.bits.exp_insts[0] connect fb.io.enq.bits.exp_insts[1], f4.io.deq.bits.exp_insts[1] connect fb.io.enq.bits.exp_insts[2], f4.io.deq.bits.exp_insts[2] connect fb.io.enq.bits.exp_insts[3], f4.io.deq.bits.exp_insts[3] connect fb.io.enq.bits.exp_insts[4], f4.io.deq.bits.exp_insts[4] connect fb.io.enq.bits.exp_insts[5], f4.io.deq.bits.exp_insts[5] connect fb.io.enq.bits.exp_insts[6], f4.io.deq.bits.exp_insts[6] connect fb.io.enq.bits.exp_insts[7], f4.io.deq.bits.exp_insts[7] connect fb.io.enq.bits.insts[0], f4.io.deq.bits.insts[0] connect fb.io.enq.bits.insts[1], f4.io.deq.bits.insts[1] connect fb.io.enq.bits.insts[2], f4.io.deq.bits.insts[2] connect fb.io.enq.bits.insts[3], f4.io.deq.bits.insts[3] connect fb.io.enq.bits.insts[4], f4.io.deq.bits.insts[4] connect fb.io.enq.bits.insts[5], f4.io.deq.bits.insts[5] connect fb.io.enq.bits.insts[6], f4.io.deq.bits.insts[6] connect fb.io.enq.bits.insts[7], f4.io.deq.bits.insts[7] connect fb.io.enq.bits.edge_inst[0], f4.io.deq.bits.edge_inst[0] connect fb.io.enq.bits.edge_inst[1], f4.io.deq.bits.edge_inst[1] connect fb.io.enq.bits.next_pc, f4.io.deq.bits.next_pc connect fb.io.enq.bits.pc, f4.io.deq.bits.pc connect fb.io.enq.bits.ftq_idx, ftq.io.enq_idx node _T_115 = dshl(UInt<1>(0h1), f4_sfb_idx) node _T_116 = mux(f4_sfb_valid, _T_115, UInt<8>(0h0)) node _T_117 = bits(_T_116, 0, 0) node _T_118 = bits(_T_116, 1, 1) node _T_119 = bits(_T_116, 2, 2) node _T_120 = bits(_T_116, 3, 3) node _T_121 = bits(_T_116, 4, 4) node _T_122 = bits(_T_116, 5, 5) node _T_123 = bits(_T_116, 6, 6) node _T_124 = bits(_T_116, 7, 7) connect fb.io.enq.bits.sfbs[0], _T_117 connect fb.io.enq.bits.sfbs[1], _T_118 connect fb.io.enq.bits.sfbs[2], _T_119 connect fb.io.enq.bits.sfbs[3], _T_120 connect fb.io.enq.bits.sfbs[4], _T_121 connect fb.io.enq.bits.sfbs[5], _T_122 connect fb.io.enq.bits.sfbs[6], _T_123 connect fb.io.enq.bits.sfbs[7], _T_124 node _T_125 = bits(f4.io.deq.bits.sfb_masks[f4_sfb_idx], 7, 0) node _T_126 = mux(f4_sfb_valid, _T_125, UInt<8>(0h0)) node lo_lo = cat(f4.io.deq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[0]) node lo_hi = cat(f4.io.deq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[2]) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(f4.io.deq.bits.shadowed_mask[5], f4.io.deq.bits.shadowed_mask[4]) node hi_hi = cat(f4.io.deq.bits.shadowed_mask[7], f4.io.deq.bits.shadowed_mask[6]) node hi = cat(hi_hi, hi_lo) node _T_127 = cat(hi, lo) node _T_128 = or(_T_126, _T_127) node _T_129 = bits(_T_128, 0, 0) node _T_130 = bits(_T_128, 1, 1) node _T_131 = bits(_T_128, 2, 2) node _T_132 = bits(_T_128, 3, 3) node _T_133 = bits(_T_128, 4, 4) node _T_134 = bits(_T_128, 5, 5) node _T_135 = bits(_T_128, 6, 6) node _T_136 = bits(_T_128, 7, 7) connect fb.io.enq.bits.shadowed_mask[0], _T_129 connect fb.io.enq.bits.shadowed_mask[1], _T_130 connect fb.io.enq.bits.shadowed_mask[2], _T_131 connect fb.io.enq.bits.shadowed_mask[3], _T_132 connect fb.io.enq.bits.shadowed_mask[4], _T_133 connect fb.io.enq.bits.shadowed_mask[5], _T_134 connect fb.io.enq.bits.shadowed_mask[6], _T_135 connect fb.io.enq.bits.shadowed_mask[7], _T_136 node _ftq_io_enq_valid_T = and(f4.io.deq.valid, fb.io.enq.ready) node _ftq_io_enq_valid_T_1 = eq(f4_delay, UInt<1>(0h0)) node _ftq_io_enq_valid_T_2 = and(_ftq_io_enq_valid_T, _ftq_io_enq_valid_T_1) connect ftq.io.enq.valid, _ftq_io_enq_valid_T_2 connect ftq.io.enq.bits.tsrc, f4.io.deq.bits.tsrc connect ftq.io.enq.bits.fsrc, f4.io.deq.bits.fsrc connect ftq.io.enq.bits.bpd_meta[0], f4.io.deq.bits.bpd_meta[0] connect ftq.io.enq.bits.bpd_meta[1], f4.io.deq.bits.bpd_meta[1] connect ftq.io.enq.bits.end_half.bits, f4.io.deq.bits.end_half.bits connect ftq.io.enq.bits.end_half.valid, f4.io.deq.bits.end_half.valid connect ftq.io.enq.bits.bp_xcpt_if_oh[0], f4.io.deq.bits.bp_xcpt_if_oh[0] connect ftq.io.enq.bits.bp_xcpt_if_oh[1], f4.io.deq.bits.bp_xcpt_if_oh[1] connect ftq.io.enq.bits.bp_xcpt_if_oh[2], f4.io.deq.bits.bp_xcpt_if_oh[2] connect ftq.io.enq.bits.bp_xcpt_if_oh[3], f4.io.deq.bits.bp_xcpt_if_oh[3] connect ftq.io.enq.bits.bp_xcpt_if_oh[4], f4.io.deq.bits.bp_xcpt_if_oh[4] connect ftq.io.enq.bits.bp_xcpt_if_oh[5], f4.io.deq.bits.bp_xcpt_if_oh[5] connect ftq.io.enq.bits.bp_xcpt_if_oh[6], f4.io.deq.bits.bp_xcpt_if_oh[6] connect ftq.io.enq.bits.bp_xcpt_if_oh[7], f4.io.deq.bits.bp_xcpt_if_oh[7] connect ftq.io.enq.bits.bp_debug_if_oh[0], f4.io.deq.bits.bp_debug_if_oh[0] connect ftq.io.enq.bits.bp_debug_if_oh[1], f4.io.deq.bits.bp_debug_if_oh[1] connect ftq.io.enq.bits.bp_debug_if_oh[2], f4.io.deq.bits.bp_debug_if_oh[2] connect ftq.io.enq.bits.bp_debug_if_oh[3], f4.io.deq.bits.bp_debug_if_oh[3] connect ftq.io.enq.bits.bp_debug_if_oh[4], f4.io.deq.bits.bp_debug_if_oh[4] connect ftq.io.enq.bits.bp_debug_if_oh[5], f4.io.deq.bits.bp_debug_if_oh[5] connect ftq.io.enq.bits.bp_debug_if_oh[6], f4.io.deq.bits.bp_debug_if_oh[6] connect ftq.io.enq.bits.bp_debug_if_oh[7], f4.io.deq.bits.bp_debug_if_oh[7] connect ftq.io.enq.bits.xcpt_ae_if, f4.io.deq.bits.xcpt_ae_if connect ftq.io.enq.bits.xcpt_pf_if, f4.io.deq.bits.xcpt_pf_if connect ftq.io.enq.bits.lhist[0], f4.io.deq.bits.lhist[0] connect ftq.io.enq.bits.lhist[1], f4.io.deq.bits.lhist[1] connect ftq.io.enq.bits.ghist.ras_idx, f4.io.deq.bits.ghist.ras_idx connect ftq.io.enq.bits.ghist.new_saw_branch_taken, f4.io.deq.bits.ghist.new_saw_branch_taken connect ftq.io.enq.bits.ghist.new_saw_branch_not_taken, f4.io.deq.bits.ghist.new_saw_branch_not_taken connect ftq.io.enq.bits.ghist.current_saw_branch_not_taken, f4.io.deq.bits.ghist.current_saw_branch_not_taken connect ftq.io.enq.bits.ghist.old_history, f4.io.deq.bits.ghist.old_history connect ftq.io.enq.bits.br_mask, f4.io.deq.bits.br_mask connect ftq.io.enq.bits.mask, f4.io.deq.bits.mask connect ftq.io.enq.bits.ftq_idx, f4.io.deq.bits.ftq_idx connect ftq.io.enq.bits.ras_top, f4.io.deq.bits.ras_top connect ftq.io.enq.bits.cfi_npc_plus4, f4.io.deq.bits.cfi_npc_plus4 connect ftq.io.enq.bits.cfi_is_ret, f4.io.deq.bits.cfi_is_ret connect ftq.io.enq.bits.cfi_is_call, f4.io.deq.bits.cfi_is_call connect ftq.io.enq.bits.cfi_type, f4.io.deq.bits.cfi_type connect ftq.io.enq.bits.cfi_idx.bits, f4.io.deq.bits.cfi_idx.bits connect ftq.io.enq.bits.cfi_idx.valid, f4.io.deq.bits.cfi_idx.valid connect ftq.io.enq.bits.shadowed_mask[0], f4.io.deq.bits.shadowed_mask[0] connect ftq.io.enq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[1] connect ftq.io.enq.bits.shadowed_mask[2], f4.io.deq.bits.shadowed_mask[2] connect ftq.io.enq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[3] connect ftq.io.enq.bits.shadowed_mask[4], f4.io.deq.bits.shadowed_mask[4] connect ftq.io.enq.bits.shadowed_mask[5], f4.io.deq.bits.shadowed_mask[5] connect ftq.io.enq.bits.shadowed_mask[6], f4.io.deq.bits.shadowed_mask[6] connect ftq.io.enq.bits.shadowed_mask[7], f4.io.deq.bits.shadowed_mask[7] connect ftq.io.enq.bits.shadowable_mask[0], f4.io.deq.bits.shadowable_mask[0] connect ftq.io.enq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[1] connect ftq.io.enq.bits.shadowable_mask[2], f4.io.deq.bits.shadowable_mask[2] connect ftq.io.enq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[3] connect ftq.io.enq.bits.shadowable_mask[4], f4.io.deq.bits.shadowable_mask[4] connect ftq.io.enq.bits.shadowable_mask[5], f4.io.deq.bits.shadowable_mask[5] connect ftq.io.enq.bits.shadowable_mask[6], f4.io.deq.bits.shadowable_mask[6] connect ftq.io.enq.bits.shadowable_mask[7], f4.io.deq.bits.shadowable_mask[7] connect ftq.io.enq.bits.sfb_dests[0], f4.io.deq.bits.sfb_dests[0] connect ftq.io.enq.bits.sfb_dests[1], f4.io.deq.bits.sfb_dests[1] connect ftq.io.enq.bits.sfb_dests[2], f4.io.deq.bits.sfb_dests[2] connect ftq.io.enq.bits.sfb_dests[3], f4.io.deq.bits.sfb_dests[3] connect ftq.io.enq.bits.sfb_dests[4], f4.io.deq.bits.sfb_dests[4] connect ftq.io.enq.bits.sfb_dests[5], f4.io.deq.bits.sfb_dests[5] connect ftq.io.enq.bits.sfb_dests[6], f4.io.deq.bits.sfb_dests[6] connect ftq.io.enq.bits.sfb_dests[7], f4.io.deq.bits.sfb_dests[7] connect ftq.io.enq.bits.sfb_masks[0], f4.io.deq.bits.sfb_masks[0] connect ftq.io.enq.bits.sfb_masks[1], f4.io.deq.bits.sfb_masks[1] connect ftq.io.enq.bits.sfb_masks[2], f4.io.deq.bits.sfb_masks[2] connect ftq.io.enq.bits.sfb_masks[3], f4.io.deq.bits.sfb_masks[3] connect ftq.io.enq.bits.sfb_masks[4], f4.io.deq.bits.sfb_masks[4] connect ftq.io.enq.bits.sfb_masks[5], f4.io.deq.bits.sfb_masks[5] connect ftq.io.enq.bits.sfb_masks[6], f4.io.deq.bits.sfb_masks[6] connect ftq.io.enq.bits.sfb_masks[7], f4.io.deq.bits.sfb_masks[7] connect ftq.io.enq.bits.sfbs[0], f4.io.deq.bits.sfbs[0] connect ftq.io.enq.bits.sfbs[1], f4.io.deq.bits.sfbs[1] connect ftq.io.enq.bits.sfbs[2], f4.io.deq.bits.sfbs[2] connect ftq.io.enq.bits.sfbs[3], f4.io.deq.bits.sfbs[3] connect ftq.io.enq.bits.sfbs[4], f4.io.deq.bits.sfbs[4] connect ftq.io.enq.bits.sfbs[5], f4.io.deq.bits.sfbs[5] connect ftq.io.enq.bits.sfbs[6], f4.io.deq.bits.sfbs[6] connect ftq.io.enq.bits.sfbs[7], f4.io.deq.bits.sfbs[7] connect ftq.io.enq.bits.exp_insts[0], f4.io.deq.bits.exp_insts[0] connect ftq.io.enq.bits.exp_insts[1], f4.io.deq.bits.exp_insts[1] connect ftq.io.enq.bits.exp_insts[2], f4.io.deq.bits.exp_insts[2] connect ftq.io.enq.bits.exp_insts[3], f4.io.deq.bits.exp_insts[3] connect ftq.io.enq.bits.exp_insts[4], f4.io.deq.bits.exp_insts[4] connect ftq.io.enq.bits.exp_insts[5], f4.io.deq.bits.exp_insts[5] connect ftq.io.enq.bits.exp_insts[6], f4.io.deq.bits.exp_insts[6] connect ftq.io.enq.bits.exp_insts[7], f4.io.deq.bits.exp_insts[7] connect ftq.io.enq.bits.insts[0], f4.io.deq.bits.insts[0] connect ftq.io.enq.bits.insts[1], f4.io.deq.bits.insts[1] connect ftq.io.enq.bits.insts[2], f4.io.deq.bits.insts[2] connect ftq.io.enq.bits.insts[3], f4.io.deq.bits.insts[3] connect ftq.io.enq.bits.insts[4], f4.io.deq.bits.insts[4] connect ftq.io.enq.bits.insts[5], f4.io.deq.bits.insts[5] connect ftq.io.enq.bits.insts[6], f4.io.deq.bits.insts[6] connect ftq.io.enq.bits.insts[7], f4.io.deq.bits.insts[7] connect ftq.io.enq.bits.edge_inst[0], f4.io.deq.bits.edge_inst[0] connect ftq.io.enq.bits.edge_inst[1], f4.io.deq.bits.edge_inst[1] connect ftq.io.enq.bits.next_pc, f4.io.deq.bits.next_pc connect ftq.io.enq.bits.pc, f4.io.deq.bits.pc inst bpd_update_arbiter of Arbiter2_BranchPredictionUpdate_1 connect bpd_update_arbiter.clock, clock connect bpd_update_arbiter.reset, reset connect bpd_update_arbiter.io.in[0].valid, ftq.io.bpdupdate.valid connect bpd_update_arbiter.io.in[0].bits.meta[0], ftq.io.bpdupdate.bits.meta[0] connect bpd_update_arbiter.io.in[0].bits.meta[1], ftq.io.bpdupdate.bits.meta[1] connect bpd_update_arbiter.io.in[0].bits.target, ftq.io.bpdupdate.bits.target connect bpd_update_arbiter.io.in[0].bits.lhist[0], ftq.io.bpdupdate.bits.lhist[0] connect bpd_update_arbiter.io.in[0].bits.lhist[1], ftq.io.bpdupdate.bits.lhist[1] connect bpd_update_arbiter.io.in[0].bits.ghist.ras_idx, ftq.io.bpdupdate.bits.ghist.ras_idx connect bpd_update_arbiter.io.in[0].bits.ghist.new_saw_branch_taken, ftq.io.bpdupdate.bits.ghist.new_saw_branch_taken connect bpd_update_arbiter.io.in[0].bits.ghist.new_saw_branch_not_taken, ftq.io.bpdupdate.bits.ghist.new_saw_branch_not_taken connect bpd_update_arbiter.io.in[0].bits.ghist.current_saw_branch_not_taken, ftq.io.bpdupdate.bits.ghist.current_saw_branch_not_taken connect bpd_update_arbiter.io.in[0].bits.ghist.old_history, ftq.io.bpdupdate.bits.ghist.old_history connect bpd_update_arbiter.io.in[0].bits.cfi_is_jalr, ftq.io.bpdupdate.bits.cfi_is_jalr connect bpd_update_arbiter.io.in[0].bits.cfi_is_jal, ftq.io.bpdupdate.bits.cfi_is_jal connect bpd_update_arbiter.io.in[0].bits.cfi_is_br, ftq.io.bpdupdate.bits.cfi_is_br connect bpd_update_arbiter.io.in[0].bits.cfi_mispredicted, ftq.io.bpdupdate.bits.cfi_mispredicted connect bpd_update_arbiter.io.in[0].bits.cfi_taken, ftq.io.bpdupdate.bits.cfi_taken connect bpd_update_arbiter.io.in[0].bits.cfi_idx.bits, ftq.io.bpdupdate.bits.cfi_idx.bits connect bpd_update_arbiter.io.in[0].bits.cfi_idx.valid, ftq.io.bpdupdate.bits.cfi_idx.valid connect bpd_update_arbiter.io.in[0].bits.br_mask, ftq.io.bpdupdate.bits.br_mask connect bpd_update_arbiter.io.in[0].bits.pc, ftq.io.bpdupdate.bits.pc connect bpd_update_arbiter.io.in[0].bits.btb_mispredicts, ftq.io.bpdupdate.bits.btb_mispredicts connect bpd_update_arbiter.io.in[0].bits.is_repair_update, ftq.io.bpdupdate.bits.is_repair_update connect bpd_update_arbiter.io.in[0].bits.is_mispredict_update, ftq.io.bpdupdate.bits.is_mispredict_update node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(bpd_update_arbiter.io.in[0].ready, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed\n at frontend.scala:928 assert(bpd_update_arbiter.io.in(0).ready)\n") : printf_1 assert(clock, bpd_update_arbiter.io.in[0].ready, UInt<1>(0h1), "") : assert_1 connect bpd_update_arbiter.io.in[1], f4_btb_corrections.io.deq connect bpd.io.update.bits.meta[0], bpd_update_arbiter.io.out.bits.meta[0] connect bpd.io.update.bits.meta[1], bpd_update_arbiter.io.out.bits.meta[1] connect bpd.io.update.bits.target, bpd_update_arbiter.io.out.bits.target connect bpd.io.update.bits.lhist[0], bpd_update_arbiter.io.out.bits.lhist[0] connect bpd.io.update.bits.lhist[1], bpd_update_arbiter.io.out.bits.lhist[1] connect bpd.io.update.bits.ghist.ras_idx, bpd_update_arbiter.io.out.bits.ghist.ras_idx connect bpd.io.update.bits.ghist.new_saw_branch_taken, bpd_update_arbiter.io.out.bits.ghist.new_saw_branch_taken connect bpd.io.update.bits.ghist.new_saw_branch_not_taken, bpd_update_arbiter.io.out.bits.ghist.new_saw_branch_not_taken connect bpd.io.update.bits.ghist.current_saw_branch_not_taken, bpd_update_arbiter.io.out.bits.ghist.current_saw_branch_not_taken connect bpd.io.update.bits.ghist.old_history, bpd_update_arbiter.io.out.bits.ghist.old_history connect bpd.io.update.bits.cfi_is_jalr, bpd_update_arbiter.io.out.bits.cfi_is_jalr connect bpd.io.update.bits.cfi_is_jal, bpd_update_arbiter.io.out.bits.cfi_is_jal connect bpd.io.update.bits.cfi_is_br, bpd_update_arbiter.io.out.bits.cfi_is_br connect bpd.io.update.bits.cfi_mispredicted, bpd_update_arbiter.io.out.bits.cfi_mispredicted connect bpd.io.update.bits.cfi_taken, bpd_update_arbiter.io.out.bits.cfi_taken connect bpd.io.update.bits.cfi_idx.bits, bpd_update_arbiter.io.out.bits.cfi_idx.bits connect bpd.io.update.bits.cfi_idx.valid, bpd_update_arbiter.io.out.bits.cfi_idx.valid connect bpd.io.update.bits.br_mask, bpd_update_arbiter.io.out.bits.br_mask connect bpd.io.update.bits.pc, bpd_update_arbiter.io.out.bits.pc connect bpd.io.update.bits.btb_mispredicts, bpd_update_arbiter.io.out.bits.btb_mispredicts connect bpd.io.update.bits.is_repair_update, bpd_update_arbiter.io.out.bits.is_repair_update connect bpd.io.update.bits.is_mispredict_update, bpd_update_arbiter.io.out.bits.is_mispredict_update connect bpd.io.update.valid, bpd_update_arbiter.io.out.valid connect bpd_update_arbiter.io.out.ready, UInt<1>(0h1) node _T_140 = and(ftq.io.ras_update, UInt<1>(0h1)) when _T_140 : connect ras.io.write_valid, UInt<1>(0h1) connect ras.io.write_idx, ftq.io.ras_update_idx connect ras.io.write_addr, ftq.io.ras_update_pc connect io.cpu.fetchpacket.bits, fb.io.deq.bits connect io.cpu.fetchpacket.valid, fb.io.deq.valid connect fb.io.deq.ready, io.cpu.fetchpacket.ready connect io.cpu.get_pc[0].next_pc, ftq.io.get_ftq_pc[0].next_pc connect io.cpu.get_pc[0].next_val, ftq.io.get_ftq_pc[0].next_val connect io.cpu.get_pc[0].com_pc, ftq.io.get_ftq_pc[0].com_pc connect io.cpu.get_pc[0].pc, ftq.io.get_ftq_pc[0].pc connect io.cpu.get_pc[0].ghist, ftq.io.get_ftq_pc[0].ghist connect io.cpu.get_pc[0].entry, ftq.io.get_ftq_pc[0].entry connect ftq.io.get_ftq_pc[0].ftq_idx, io.cpu.get_pc[0].ftq_idx connect io.cpu.get_pc[1].next_pc, ftq.io.get_ftq_pc[1].next_pc connect io.cpu.get_pc[1].next_val, ftq.io.get_ftq_pc[1].next_val connect io.cpu.get_pc[1].com_pc, ftq.io.get_ftq_pc[1].com_pc connect io.cpu.get_pc[1].pc, ftq.io.get_ftq_pc[1].pc connect io.cpu.get_pc[1].ghist, ftq.io.get_ftq_pc[1].ghist connect io.cpu.get_pc[1].entry, ftq.io.get_ftq_pc[1].entry connect ftq.io.get_ftq_pc[1].ftq_idx, io.cpu.get_pc[1].ftq_idx connect ftq.io.deq.bits, io.cpu.commit.bits connect ftq.io.deq.valid, io.cpu.commit.valid connect ftq.io.brupdate.b2.target_offset, io.cpu.brupdate.b2.target_offset connect ftq.io.brupdate.b2.jalr_target, io.cpu.brupdate.b2.jalr_target connect ftq.io.brupdate.b2.pc_sel, io.cpu.brupdate.b2.pc_sel connect ftq.io.brupdate.b2.cfi_type, io.cpu.brupdate.b2.cfi_type connect ftq.io.brupdate.b2.taken, io.cpu.brupdate.b2.taken connect ftq.io.brupdate.b2.mispredict, io.cpu.brupdate.b2.mispredict connect ftq.io.brupdate.b2.valid, io.cpu.brupdate.b2.valid connect ftq.io.brupdate.b2.uop.debug_tsrc, io.cpu.brupdate.b2.uop.debug_tsrc connect ftq.io.brupdate.b2.uop.debug_fsrc, io.cpu.brupdate.b2.uop.debug_fsrc connect ftq.io.brupdate.b2.uop.bp_xcpt_if, io.cpu.brupdate.b2.uop.bp_xcpt_if connect ftq.io.brupdate.b2.uop.bp_debug_if, io.cpu.brupdate.b2.uop.bp_debug_if connect ftq.io.brupdate.b2.uop.xcpt_ma_if, io.cpu.brupdate.b2.uop.xcpt_ma_if connect ftq.io.brupdate.b2.uop.xcpt_ae_if, io.cpu.brupdate.b2.uop.xcpt_ae_if connect ftq.io.brupdate.b2.uop.xcpt_pf_if, io.cpu.brupdate.b2.uop.xcpt_pf_if connect ftq.io.brupdate.b2.uop.fp_single, io.cpu.brupdate.b2.uop.fp_single connect ftq.io.brupdate.b2.uop.fp_val, io.cpu.brupdate.b2.uop.fp_val connect ftq.io.brupdate.b2.uop.frs3_en, io.cpu.brupdate.b2.uop.frs3_en connect ftq.io.brupdate.b2.uop.lrs2_rtype, io.cpu.brupdate.b2.uop.lrs2_rtype connect ftq.io.brupdate.b2.uop.lrs1_rtype, io.cpu.brupdate.b2.uop.lrs1_rtype connect ftq.io.brupdate.b2.uop.dst_rtype, io.cpu.brupdate.b2.uop.dst_rtype connect ftq.io.brupdate.b2.uop.ldst_val, io.cpu.brupdate.b2.uop.ldst_val connect ftq.io.brupdate.b2.uop.lrs3, io.cpu.brupdate.b2.uop.lrs3 connect ftq.io.brupdate.b2.uop.lrs2, io.cpu.brupdate.b2.uop.lrs2 connect ftq.io.brupdate.b2.uop.lrs1, io.cpu.brupdate.b2.uop.lrs1 connect ftq.io.brupdate.b2.uop.ldst, io.cpu.brupdate.b2.uop.ldst connect ftq.io.brupdate.b2.uop.ldst_is_rs1, io.cpu.brupdate.b2.uop.ldst_is_rs1 connect ftq.io.brupdate.b2.uop.flush_on_commit, io.cpu.brupdate.b2.uop.flush_on_commit connect ftq.io.brupdate.b2.uop.is_unique, io.cpu.brupdate.b2.uop.is_unique connect ftq.io.brupdate.b2.uop.is_sys_pc2epc, io.cpu.brupdate.b2.uop.is_sys_pc2epc connect ftq.io.brupdate.b2.uop.uses_stq, io.cpu.brupdate.b2.uop.uses_stq connect ftq.io.brupdate.b2.uop.uses_ldq, io.cpu.brupdate.b2.uop.uses_ldq connect ftq.io.brupdate.b2.uop.is_amo, io.cpu.brupdate.b2.uop.is_amo connect ftq.io.brupdate.b2.uop.is_fencei, io.cpu.brupdate.b2.uop.is_fencei connect ftq.io.brupdate.b2.uop.is_fence, io.cpu.brupdate.b2.uop.is_fence connect ftq.io.brupdate.b2.uop.mem_signed, io.cpu.brupdate.b2.uop.mem_signed connect ftq.io.brupdate.b2.uop.mem_size, io.cpu.brupdate.b2.uop.mem_size connect ftq.io.brupdate.b2.uop.mem_cmd, io.cpu.brupdate.b2.uop.mem_cmd connect ftq.io.brupdate.b2.uop.bypassable, io.cpu.brupdate.b2.uop.bypassable connect ftq.io.brupdate.b2.uop.exc_cause, io.cpu.brupdate.b2.uop.exc_cause connect ftq.io.brupdate.b2.uop.exception, io.cpu.brupdate.b2.uop.exception connect ftq.io.brupdate.b2.uop.stale_pdst, io.cpu.brupdate.b2.uop.stale_pdst connect ftq.io.brupdate.b2.uop.ppred_busy, io.cpu.brupdate.b2.uop.ppred_busy connect ftq.io.brupdate.b2.uop.prs3_busy, io.cpu.brupdate.b2.uop.prs3_busy connect ftq.io.brupdate.b2.uop.prs2_busy, io.cpu.brupdate.b2.uop.prs2_busy connect ftq.io.brupdate.b2.uop.prs1_busy, io.cpu.brupdate.b2.uop.prs1_busy connect ftq.io.brupdate.b2.uop.ppred, io.cpu.brupdate.b2.uop.ppred connect ftq.io.brupdate.b2.uop.prs3, io.cpu.brupdate.b2.uop.prs3 connect ftq.io.brupdate.b2.uop.prs2, io.cpu.brupdate.b2.uop.prs2 connect ftq.io.brupdate.b2.uop.prs1, io.cpu.brupdate.b2.uop.prs1 connect ftq.io.brupdate.b2.uop.pdst, io.cpu.brupdate.b2.uop.pdst connect ftq.io.brupdate.b2.uop.rxq_idx, io.cpu.brupdate.b2.uop.rxq_idx connect ftq.io.brupdate.b2.uop.stq_idx, io.cpu.brupdate.b2.uop.stq_idx connect ftq.io.brupdate.b2.uop.ldq_idx, io.cpu.brupdate.b2.uop.ldq_idx connect ftq.io.brupdate.b2.uop.rob_idx, io.cpu.brupdate.b2.uop.rob_idx connect ftq.io.brupdate.b2.uop.csr_addr, io.cpu.brupdate.b2.uop.csr_addr connect ftq.io.brupdate.b2.uop.imm_packed, io.cpu.brupdate.b2.uop.imm_packed connect ftq.io.brupdate.b2.uop.taken, io.cpu.brupdate.b2.uop.taken connect ftq.io.brupdate.b2.uop.pc_lob, io.cpu.brupdate.b2.uop.pc_lob connect ftq.io.brupdate.b2.uop.edge_inst, io.cpu.brupdate.b2.uop.edge_inst connect ftq.io.brupdate.b2.uop.ftq_idx, io.cpu.brupdate.b2.uop.ftq_idx connect ftq.io.brupdate.b2.uop.br_tag, io.cpu.brupdate.b2.uop.br_tag connect ftq.io.brupdate.b2.uop.br_mask, io.cpu.brupdate.b2.uop.br_mask connect ftq.io.brupdate.b2.uop.is_sfb, io.cpu.brupdate.b2.uop.is_sfb connect ftq.io.brupdate.b2.uop.is_jal, io.cpu.brupdate.b2.uop.is_jal connect ftq.io.brupdate.b2.uop.is_jalr, io.cpu.brupdate.b2.uop.is_jalr connect ftq.io.brupdate.b2.uop.is_br, io.cpu.brupdate.b2.uop.is_br connect ftq.io.brupdate.b2.uop.iw_p2_poisoned, io.cpu.brupdate.b2.uop.iw_p2_poisoned connect ftq.io.brupdate.b2.uop.iw_p1_poisoned, io.cpu.brupdate.b2.uop.iw_p1_poisoned connect ftq.io.brupdate.b2.uop.iw_state, io.cpu.brupdate.b2.uop.iw_state connect ftq.io.brupdate.b2.uop.ctrl.is_std, io.cpu.brupdate.b2.uop.ctrl.is_std connect ftq.io.brupdate.b2.uop.ctrl.is_sta, io.cpu.brupdate.b2.uop.ctrl.is_sta connect ftq.io.brupdate.b2.uop.ctrl.is_load, io.cpu.brupdate.b2.uop.ctrl.is_load connect ftq.io.brupdate.b2.uop.ctrl.csr_cmd, io.cpu.brupdate.b2.uop.ctrl.csr_cmd connect ftq.io.brupdate.b2.uop.ctrl.fcn_dw, io.cpu.brupdate.b2.uop.ctrl.fcn_dw connect ftq.io.brupdate.b2.uop.ctrl.op_fcn, io.cpu.brupdate.b2.uop.ctrl.op_fcn connect ftq.io.brupdate.b2.uop.ctrl.imm_sel, io.cpu.brupdate.b2.uop.ctrl.imm_sel connect ftq.io.brupdate.b2.uop.ctrl.op2_sel, io.cpu.brupdate.b2.uop.ctrl.op2_sel connect ftq.io.brupdate.b2.uop.ctrl.op1_sel, io.cpu.brupdate.b2.uop.ctrl.op1_sel connect ftq.io.brupdate.b2.uop.ctrl.br_type, io.cpu.brupdate.b2.uop.ctrl.br_type connect ftq.io.brupdate.b2.uop.fu_code, io.cpu.brupdate.b2.uop.fu_code connect ftq.io.brupdate.b2.uop.iq_type, io.cpu.brupdate.b2.uop.iq_type connect ftq.io.brupdate.b2.uop.debug_pc, io.cpu.brupdate.b2.uop.debug_pc connect ftq.io.brupdate.b2.uop.is_rvc, io.cpu.brupdate.b2.uop.is_rvc connect ftq.io.brupdate.b2.uop.debug_inst, io.cpu.brupdate.b2.uop.debug_inst connect ftq.io.brupdate.b2.uop.inst, io.cpu.brupdate.b2.uop.inst connect ftq.io.brupdate.b2.uop.uopc, io.cpu.brupdate.b2.uop.uopc connect ftq.io.brupdate.b1.mispredict_mask, io.cpu.brupdate.b1.mispredict_mask connect ftq.io.brupdate.b1.resolve_mask, io.cpu.brupdate.b1.resolve_mask connect ftq.io.redirect.valid, io.cpu.redirect_val connect ftq.io.redirect.bits, io.cpu.redirect_ftq_idx connect fb.io.clear, UInt<1>(0h0) when io.cpu.sfence.valid : connect fb.io.clear, UInt<1>(0h1) connect f4_clear, UInt<1>(0h1) connect f3_clear, UInt<1>(0h1) connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) connect s0_valid, UInt<1>(0h0) connect s0_vpc, io.cpu.sfence.bits.addr connect s0_is_replay, UInt<1>(0h0) connect s0_is_sfence, UInt<1>(0h1) else : when io.cpu.redirect_flush : connect fb.io.clear, UInt<1>(0h1) connect f4_clear, UInt<1>(0h1) connect f3_clear, UInt<1>(0h1) connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) connect f3_prev_is_half, UInt<1>(0h0) connect s0_valid, io.cpu.redirect_val connect s0_vpc, io.cpu.redirect_pc connect s0_ghist, io.cpu.redirect_ghist connect s0_tsrc, UInt<2>(0h3) connect s0_is_replay, UInt<1>(0h0) connect ftq.io.redirect.valid, io.cpu.redirect_val connect ftq.io.redirect.bits, io.cpu.redirect_ftq_idx connect ftq.io.debug_ftq_idx[0], io.cpu.debug_ftq_idx[0] connect ftq.io.debug_ftq_idx[1], io.cpu.debug_ftq_idx[1] connect ftq.io.debug_ftq_idx[2], io.cpu.debug_ftq_idx[2] connect io.cpu.debug_fetch_pc, ftq.io.debug_fetch_pc

module BoomFrontend_1( // @[frontend.scala:322:7] input clock, // @[frontend.scala:322:7] input reset, // @[frontend.scala:322:7] input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_cpu_fetchpacket_ready, // @[frontend.scala:326:14] output io_cpu_fetchpacket_valid, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_valid, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_0_bits_inst, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_inst, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_is_rvc, // @[frontend.scala:326:14] output [39:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_pc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_is_sfb, // @[frontend.scala:326:14] output [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_edge_inst, // @[frontend.scala:326:14] output [5:0] io_cpu_fetchpacket_bits_uops_0_bits_pc_lob, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_taken, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[frontend.scala:326:14] output [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_valid, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_1_bits_inst, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_inst, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_is_rvc, // @[frontend.scala:326:14] output [39:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_pc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_is_sfb, // @[frontend.scala:326:14] output [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_edge_inst, // @[frontend.scala:326:14] output [5:0] io_cpu_fetchpacket_bits_uops_1_bits_pc_lob, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_taken, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if, // @[frontend.scala:326:14] output [1:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_valid, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_2_bits_inst, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_inst, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_is_rvc, // @[frontend.scala:326:14] output [39:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_pc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_is_sfb, // @[frontend.scala:326:14] output [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_edge_inst, // @[frontend.scala:326:14] output [5:0] io_cpu_fetchpacket_bits_uops_2_bits_pc_lob, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_taken, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if, // @[frontend.scala:326:14] output [1:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc, // @[frontend.scala:326:14] input [4:0] io_cpu_get_pc_0_ftq_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_idx_valid, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_0_entry_cfi_idx_bits, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_mispredicted, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_0_entry_cfi_type, // @[frontend.scala:326:14] output [7:0] io_cpu_get_pc_0_entry_br_mask, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_is_call, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_is_ret, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_npc_plus4, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_entry_ras_top, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_0_entry_ras_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_start_bank, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_com_pc, // @[frontend.scala:326:14] output io_cpu_get_pc_0_next_val, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_next_pc, // @[frontend.scala:326:14] input [4:0] io_cpu_get_pc_1_ftq_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_idx_valid, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_1_entry_cfi_idx_bits, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_mispredicted, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_1_entry_cfi_type, // @[frontend.scala:326:14] output [7:0] io_cpu_get_pc_1_entry_br_mask, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_is_call, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_is_ret, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_npc_plus4, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_entry_ras_top, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_1_entry_ras_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_start_bank, // @[frontend.scala:326:14] output [63:0] io_cpu_get_pc_1_ghist_old_history, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_current_saw_branch_not_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_new_saw_branch_not_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_new_saw_branch_taken, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_1_ghist_ras_idx, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_com_pc, // @[frontend.scala:326:14] output io_cpu_get_pc_1_next_val, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_next_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_debug_fetch_pc_0, // @[frontend.scala:326:14] output [39:0] io_cpu_debug_fetch_pc_1, // @[frontend.scala:326:14] output [39:0] io_cpu_debug_fetch_pc_2, // @[frontend.scala:326:14] input io_cpu_status_debug, // @[frontend.scala:326:14] input io_cpu_status_cease, // @[frontend.scala:326:14] input io_cpu_status_wfi, // @[frontend.scala:326:14] input [1:0] io_cpu_status_dprv, // @[frontend.scala:326:14] input io_cpu_status_dv, // @[frontend.scala:326:14] input [1:0] io_cpu_status_prv, // @[frontend.scala:326:14] input io_cpu_status_v, // @[frontend.scala:326:14] input io_cpu_status_sd, // @[frontend.scala:326:14] input io_cpu_status_mpv, // @[frontend.scala:326:14] input io_cpu_status_gva, // @[frontend.scala:326:14] input io_cpu_status_tsr, // @[frontend.scala:326:14] input io_cpu_status_tw, // @[frontend.scala:326:14] input io_cpu_status_tvm, // @[frontend.scala:326:14] input io_cpu_status_mxr, // @[frontend.scala:326:14] input io_cpu_status_sum, // @[frontend.scala:326:14] input io_cpu_status_mprv, // @[frontend.scala:326:14] input [1:0] io_cpu_status_fs, // @[frontend.scala:326:14] input [1:0] io_cpu_status_mpp, // @[frontend.scala:326:14] input io_cpu_status_spp, // @[frontend.scala:326:14] input io_cpu_status_mpie, // @[frontend.scala:326:14] input io_cpu_status_spie, // @[frontend.scala:326:14] input io_cpu_status_mie, // @[frontend.scala:326:14] input io_cpu_status_sie, // @[frontend.scala:326:14] input io_cpu_sfence_valid, // @[frontend.scala:326:14] input io_cpu_sfence_bits_rs1, // @[frontend.scala:326:14] input io_cpu_sfence_bits_rs2, // @[frontend.scala:326:14] input [38:0] io_cpu_sfence_bits_addr, // @[frontend.scala:326:14] input io_cpu_sfence_bits_asid, // @[frontend.scala:326:14] input [15:0] io_cpu_brupdate_b1_resolve_mask, // @[frontend.scala:326:14] input [15:0] io_cpu_brupdate_b1_mispredict_mask, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_uopc, // @[frontend.scala:326:14] input [31:0] io_cpu_brupdate_b2_uop_inst, // @[frontend.scala:326:14] input [31:0] io_cpu_brupdate_b2_uop_debug_inst, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_rvc, // @[frontend.scala:326:14] input [39:0] io_cpu_brupdate_b2_uop_debug_pc, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_iq_type, // @[frontend.scala:326:14] input [9:0] io_cpu_brupdate_b2_uop_fu_code, // @[frontend.scala:326:14] input [3:0] io_cpu_brupdate_b2_uop_ctrl_br_type, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_ctrl_op1_sel, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_op2_sel, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_imm_sel, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ctrl_op_fcn, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_fcn_dw, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_csr_cmd, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_load, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_sta, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_std, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_iw_state, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_iw_p1_poisoned, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_iw_p2_poisoned, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_br, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_jalr, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_jal, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_sfb, // @[frontend.scala:326:14] input [15:0] io_cpu_brupdate_b2_uop_br_mask, // @[frontend.scala:326:14] input [3:0] io_cpu_brupdate_b2_uop_br_tag, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ftq_idx, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_edge_inst, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_pc_lob, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_taken, // @[frontend.scala:326:14] input [19:0] io_cpu_brupdate_b2_uop_imm_packed, // @[frontend.scala:326:14] input [11:0] io_cpu_brupdate_b2_uop_csr_addr, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_rob_idx, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ldq_idx, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_stq_idx, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_rxq_idx, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_pdst, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_prs1, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_prs2, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_prs3, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ppred, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs1_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs2_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs3_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ppred_busy, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_stale_pdst, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_exception, // @[frontend.scala:326:14] input [63:0] io_cpu_brupdate_b2_uop_exc_cause, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bypassable, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_mem_cmd, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_mem_size, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_mem_signed, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_fence, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_fencei, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_amo, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_uses_ldq, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_uses_stq, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_sys_pc2epc, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_unique, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_flush_on_commit, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ldst_is_rs1, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_ldst, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs1, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs2, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs3, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ldst_val, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_dst_rtype, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_lrs1_rtype, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_lrs2_rtype, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_frs3_en, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_fp_val, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_fp_single, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_pf_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_ae_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_ma_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bp_debug_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bp_xcpt_if, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_debug_fsrc, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_debug_tsrc, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_valid, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_mispredict, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_taken, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_cfi_type, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_pc_sel, // @[frontend.scala:326:14] input [39:0] io_cpu_brupdate_b2_jalr_target, // @[frontend.scala:326:14] input [20:0] io_cpu_brupdate_b2_target_offset, // @[frontend.scala:326:14] input io_cpu_redirect_flush, // @[frontend.scala:326:14] input io_cpu_redirect_val, // @[frontend.scala:326:14] input [39:0] io_cpu_redirect_pc, // @[frontend.scala:326:14] input [4:0] io_cpu_redirect_ftq_idx, // @[frontend.scala:326:14] input [63:0] io_cpu_redirect_ghist_old_history, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_current_saw_branch_not_taken, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_new_saw_branch_not_taken, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_new_saw_branch_taken, // @[frontend.scala:326:14] input [4:0] io_cpu_redirect_ghist_ras_idx, // @[frontend.scala:326:14] input io_cpu_commit_valid, // @[frontend.scala:326:14] input [31:0] io_cpu_commit_bits, // @[frontend.scala:326:14] input io_cpu_flush_icache, // @[frontend.scala:326:14] output io_cpu_perf_acquire, // @[frontend.scala:326:14] output io_cpu_perf_tlbMiss, // @[frontend.scala:326:14] input io_ptw_req_ready, // @[frontend.scala:326:14] output io_ptw_req_valid, // @[frontend.scala:326:14] output [26:0] io_ptw_req_bits_bits_addr, // @[frontend.scala:326:14] output io_ptw_req_bits_bits_need_gpa, // @[frontend.scala:326:14] input io_ptw_resp_valid, // @[frontend.scala:326:14] input io_ptw_resp_bits_ae_ptw, // @[frontend.scala:326:14] input io_ptw_resp_bits_ae_final, // @[frontend.scala:326:14] input io_ptw_resp_bits_pf, // @[frontend.scala:326:14] input io_ptw_resp_bits_gf, // @[frontend.scala:326:14] input io_ptw_resp_bits_hr, // @[frontend.scala:326:14] input io_ptw_resp_bits_hw, // @[frontend.scala:326:14] input io_ptw_resp_bits_hx, // @[frontend.scala:326:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[frontend.scala:326:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[frontend.scala:326:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_d, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_a, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_g, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_u, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_x, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_w, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_r, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_v, // @[frontend.scala:326:14] input [1:0] io_ptw_resp_bits_level, // @[frontend.scala:326:14] input io_ptw_resp_bits_homogeneous, // @[frontend.scala:326:14] input io_ptw_resp_bits_gpa_valid, // @[frontend.scala:326:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[frontend.scala:326:14] input io_ptw_resp_bits_gpa_is_pte, // @[frontend.scala:326:14] input [3:0] io_ptw_ptbr_mode, // @[frontend.scala:326:14] input [43:0] io_ptw_ptbr_ppn, // @[frontend.scala:326:14] input io_ptw_status_debug, // @[frontend.scala:326:14] input io_ptw_status_cease, // @[frontend.scala:326:14] input io_ptw_status_wfi, // @[frontend.scala:326:14] input [1:0] io_ptw_status_dprv, // @[frontend.scala:326:14] input io_ptw_status_dv, // @[frontend.scala:326:14] input [1:0] io_ptw_status_prv, // @[frontend.scala:326:14] input io_ptw_status_v, // @[frontend.scala:326:14] input io_ptw_status_sd, // @[frontend.scala:326:14] input io_ptw_status_mpv, // @[frontend.scala:326:14] input io_ptw_status_gva, // @[frontend.scala:326:14] input io_ptw_status_tsr, // @[frontend.scala:326:14] input io_ptw_status_tw, // @[frontend.scala:326:14] input io_ptw_status_tvm, // @[frontend.scala:326:14] input io_ptw_status_mxr, // @[frontend.scala:326:14] input io_ptw_status_sum, // @[frontend.scala:326:14] input io_ptw_status_mprv, // @[frontend.scala:326:14] input [1:0] io_ptw_status_fs, // @[frontend.scala:326:14] input [1:0] io_ptw_status_mpp, // @[frontend.scala:326:14] input io_ptw_status_spp, // @[frontend.scala:326:14] input io_ptw_status_mpie, // @[frontend.scala:326:14] input io_ptw_status_spie, // @[frontend.scala:326:14] input io_ptw_status_mie, // @[frontend.scala:326:14] input io_ptw_status_sie, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_0_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_0_mask, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_1_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_1_mask, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_2_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_2_mask, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_3_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_3_mask, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_4_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_4_mask, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_5_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_5_mask, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_6_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_6_mask, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_7_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_7_mask // @[frontend.scala:326:14] ); wire [4:0] f3_io_enq_bits_ghist_ras_idx; // @[frontend.scala:533:24, :814:38, :821:79, :822:28] wire f3_fetch_bundle_cfi_is_ret; // @[frontend.scala:569:29] wire [2:0] f3_fetch_bundle_cfi_idx_bits; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_idx_valid; // @[frontend.scala:569:29] wire _bpd_update_arbiter_io_in_1_ready; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_valid; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_is_mispredict_update; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_is_repair_update; // @[frontend.scala:925:34] wire [7:0] _bpd_update_arbiter_io_out_bits_btb_mispredicts; // @[frontend.scala:925:34] wire [39:0] _bpd_update_arbiter_io_out_bits_pc; // @[frontend.scala:925:34] wire [7:0] _bpd_update_arbiter_io_out_bits_br_mask; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_idx_valid; // @[frontend.scala:925:34] wire [2:0] _bpd_update_arbiter_io_out_bits_cfi_idx_bits; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_mispredicted; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_br; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_jal; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_jalr; // @[frontend.scala:925:34] wire [63:0] _bpd_update_arbiter_io_out_bits_ghist_old_history; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_new_saw_branch_taken; // @[frontend.scala:925:34] wire [4:0] _bpd_update_arbiter_io_out_bits_ghist_ras_idx; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_lhist_0; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_lhist_1; // @[frontend.scala:925:34] wire [39:0] _bpd_update_arbiter_io_out_bits_target; // @[frontend.scala:925:34] wire [119:0] _bpd_update_arbiter_io_out_bits_meta_0; // @[frontend.scala:925:34] wire [119:0] _bpd_update_arbiter_io_out_bits_meta_1; // @[frontend.scala:925:34] wire _ftq_io_enq_ready; // @[frontend.scala:862:19] wire [4:0] _ftq_io_enq_idx; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_valid; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_is_mispredict_update; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_is_repair_update; // @[frontend.scala:862:19] wire [39:0] _ftq_io_bpdupdate_bits_pc; // @[frontend.scala:862:19] wire [7:0] _ftq_io_bpdupdate_bits_br_mask; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_idx_valid; // @[frontend.scala:862:19] wire [2:0] _ftq_io_bpdupdate_bits_cfi_idx_bits; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_mispredicted; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_is_br; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_is_jal; // @[frontend.scala:862:19] wire [63:0] _ftq_io_bpdupdate_bits_ghist_old_history; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_new_saw_branch_taken; // @[frontend.scala:862:19] wire [4:0] _ftq_io_bpdupdate_bits_ghist_ras_idx; // @[frontend.scala:862:19] wire [39:0] _ftq_io_bpdupdate_bits_target; // @[frontend.scala:862:19] wire [119:0] _ftq_io_bpdupdate_bits_meta_0; // @[frontend.scala:862:19] wire [119:0] _ftq_io_bpdupdate_bits_meta_1; // @[frontend.scala:862:19] wire _ftq_io_ras_update; // @[frontend.scala:862:19] wire [4:0] _ftq_io_ras_update_idx; // @[frontend.scala:862:19] wire [39:0] _ftq_io_ras_update_pc; // @[frontend.scala:862:19] wire _fb_io_enq_ready; // @[frontend.scala:861:19] wire _f4_io_deq_valid; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_pc; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_next_pc; // @[frontend.scala:859:11] wire _f4_io_deq_bits_edge_inst_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_edge_inst_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_0; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_2; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_3; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_4; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_5; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_6; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_7; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_0; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_2; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_3; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_4; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_5; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_6; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_7; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_0; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_1; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_2; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_3; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_4; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_5; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_6; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_sfb_masks_7; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_0; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_1; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_2; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_3; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_4; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_5; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_6; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_sfb_dests_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_idx_valid; // @[frontend.scala:859:11] wire [2:0] _f4_io_deq_bits_cfi_idx_bits; // @[frontend.scala:859:11] wire [2:0] _f4_io_deq_bits_cfi_type; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_is_call; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_is_ret; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_npc_plus4; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_ras_top; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_ftq_idx; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_mask; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_br_mask; // @[frontend.scala:859:11] wire [63:0] _f4_io_deq_bits_ghist_old_history; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_new_saw_branch_taken; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_ghist_ras_idx; // @[frontend.scala:859:11] wire _f4_io_deq_bits_lhist_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_lhist_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_xcpt_pf_if; // @[frontend.scala:859:11] wire _f4_io_deq_bits_xcpt_ae_if; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_4; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_5; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_6; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_7; // @[frontend.scala:859:11] wire _f4_io_deq_bits_end_half_valid; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_end_half_bits; // @[frontend.scala:859:11] wire [119:0] _f4_io_deq_bits_bpd_meta_0; // @[frontend.scala:859:11] wire [119:0] _f4_io_deq_bits_bpd_meta_1; // @[frontend.scala:859:11] wire [1:0] _f4_io_deq_bits_fsrc; // @[frontend.scala:859:11] wire [1:0] _f4_io_deq_bits_tsrc; // @[frontend.scala:859:11] wire _f4_btb_corrections_io_deq_valid; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_is_mispredict_update; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_is_repair_update; // @[frontend.scala:842:34] wire [7:0] _f4_btb_corrections_io_deq_bits_btb_mispredicts; // @[frontend.scala:842:34] wire [39:0] _f4_btb_corrections_io_deq_bits_pc; // @[frontend.scala:842:34] wire [7:0] _f4_btb_corrections_io_deq_bits_br_mask; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_idx_valid; // @[frontend.scala:842:34] wire [2:0] _f4_btb_corrections_io_deq_bits_cfi_idx_bits; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_mispredicted; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_br; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_jal; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_jalr; // @[frontend.scala:842:34] wire [63:0] _f4_btb_corrections_io_deq_bits_ghist_old_history; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_new_saw_branch_taken; // @[frontend.scala:842:34] wire [4:0] _f4_btb_corrections_io_deq_bits_ghist_ras_idx; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_lhist_0; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_lhist_1; // @[frontend.scala:842:34] wire [39:0] _f4_btb_corrections_io_deq_bits_target; // @[frontend.scala:842:34] wire [119:0] _f4_btb_corrections_io_deq_bits_meta_0; // @[frontend.scala:842:34] wire [119:0] _f4_btb_corrections_io_deq_bits_meta_1; // @[frontend.scala:842:34] wire [31:0] _exp_inst_rvc_exp_5_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_5_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_4_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_4_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_3_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_3_io_rvc; // @[consts.scala:330:25] wire _bpd_decoder0b_io_out_is_ret; // @[frontend.scala:639:39] wire _bpd_decoder0b_io_out_is_call; // @[frontend.scala:639:39] wire [39:0] _bpd_decoder0b_io_out_target; // @[frontend.scala:639:39] wire [2:0] _bpd_decoder0b_io_out_cfi_type; // @[frontend.scala:639:39] wire _bpd_decoder0b_io_out_sfb_offset_valid; // @[frontend.scala:639:39] wire [5:0] _bpd_decoder0b_io_out_sfb_offset_bits; // @[frontend.scala:639:39] wire _bpd_decoder0b_io_out_shadowable; // @[frontend.scala:639:39] wire [31:0] _exp_inst0b_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst0b_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _bpd_decoder1_1_io_out_is_ret; // @[frontend.scala:625:34] wire _bpd_decoder1_1_io_out_is_call; // @[frontend.scala:625:34] wire [39:0] _bpd_decoder1_1_io_out_target; // @[frontend.scala:625:34] wire [2:0] _bpd_decoder1_1_io_out_cfi_type; // @[frontend.scala:625:34] wire _bpd_decoder1_1_io_out_sfb_offset_valid; // @[frontend.scala:625:34] wire [5:0] _bpd_decoder1_1_io_out_sfb_offset_bits; // @[frontend.scala:625:34] wire _bpd_decoder1_1_io_out_shadowable; // @[frontend.scala:625:34] wire _bpd_decoder0_1_io_out_is_ret; // @[frontend.scala:622:34] wire _bpd_decoder0_1_io_out_is_call; // @[frontend.scala:622:34] wire [39:0] _bpd_decoder0_1_io_out_target; // @[frontend.scala:622:34] wire [2:0] _bpd_decoder0_1_io_out_cfi_type; // @[frontend.scala:622:34] wire _bpd_decoder0_1_io_out_sfb_offset_valid; // @[frontend.scala:622:34] wire [5:0] _bpd_decoder0_1_io_out_sfb_offset_bits; // @[frontend.scala:622:34] wire _bpd_decoder0_1_io_out_shadowable; // @[frontend.scala:622:34] wire [31:0] _exp_inst1_rvc_exp_1_io_out_bits; // @[consts.scala:330:25] wire _exp_inst1_rvc_exp_1_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst0_rvc_exp_1_io_out_bits; // @[consts.scala:330:25] wire _exp_inst0_rvc_exp_1_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_2_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_2_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_1_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_1_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _bpd_decoder1_io_out_is_ret; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_is_call; // @[frontend.scala:625:34] wire [39:0] _bpd_decoder1_io_out_target; // @[frontend.scala:625:34] wire [2:0] _bpd_decoder1_io_out_cfi_type; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_sfb_offset_valid; // @[frontend.scala:625:34] wire [5:0] _bpd_decoder1_io_out_sfb_offset_bits; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_shadowable; // @[frontend.scala:625:34] wire _bpd_decoder0_io_out_is_ret; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_is_call; // @[frontend.scala:622:34] wire [39:0] _bpd_decoder0_io_out_target; // @[frontend.scala:622:34] wire [2:0] _bpd_decoder0_io_out_cfi_type; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_sfb_offset_valid; // @[frontend.scala:622:34] wire [5:0] _bpd_decoder0_io_out_sfb_offset_bits; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_shadowable; // @[frontend.scala:622:34] wire [31:0] _exp_inst1_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst1_rvc_exp_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst0_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst0_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _f3_bpd_resp_io_enq_ready; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_pc; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_0_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_1_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_2_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_3_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_4_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_5_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_6_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_7_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_io_enq_ready; // @[frontend.scala:516:11] wire _f3_io_deq_valid; // @[frontend.scala:516:11] wire [39:0] _f3_io_deq_bits_pc; // @[frontend.scala:516:11] wire [127:0] _f3_io_deq_bits_data; // @[frontend.scala:516:11] wire [7:0] _f3_io_deq_bits_mask; // @[frontend.scala:516:11] wire [1:0] _f3_io_deq_bits_fsrc; // @[frontend.scala:516:11] wire _tlb_io_resp_miss; // @[frontend.scala:337:19] wire [31:0] _tlb_io_resp_paddr; // @[frontend.scala:337:19] wire [39:0] _tlb_io_resp_gpa; // @[frontend.scala:337:19] wire _tlb_io_resp_pf_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_pf_inst; // @[frontend.scala:337:19] wire _tlb_io_resp_ae_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_ae_inst; // @[frontend.scala:337:19] wire _tlb_io_resp_ma_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_cacheable; // @[frontend.scala:337:19] wire _tlb_io_resp_prefetchable; // @[frontend.scala:337:19] wire [39:0] _ras_io_read_addr; // @[frontend.scala:333:19] wire _bpd_io_resp_f1_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_4_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_4_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_5_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_5_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_6_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_6_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_7_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_7_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_4_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_4_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_5_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_5_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_6_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_6_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_7_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_7_predicted_pc_bits; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_pc; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_4_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_4_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_5_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_5_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_6_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_6_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_7_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_7_predicted_pc_bits; // @[frontend.scala:331:19] wire [119:0] _bpd_io_resp_f3_meta_0; // @[frontend.scala:331:19] wire [119:0] _bpd_io_resp_f3_meta_1; // @[frontend.scala:331:19] wire _icache_io_resp_valid; // @[frontend.scala:299:26] wire [127:0] _icache_io_resp_bits_data; // @[frontend.scala:299:26] wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[frontend.scala:322:7] wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[frontend.scala:322:7] wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[frontend.scala:322:7] wire [127:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_ready_0 = io_cpu_fetchpacket_ready; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_ftq_idx_0 = io_cpu_get_pc_0_ftq_idx; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_ftq_idx_0 = io_cpu_get_pc_1_ftq_idx; // @[frontend.scala:322:7] wire io_cpu_status_debug_0 = io_cpu_status_debug; // @[frontend.scala:322:7] wire io_cpu_status_cease_0 = io_cpu_status_cease; // @[frontend.scala:322:7] wire io_cpu_status_wfi_0 = io_cpu_status_wfi; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_dprv_0 = io_cpu_status_dprv; // @[frontend.scala:322:7] wire io_cpu_status_dv_0 = io_cpu_status_dv; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_prv_0 = io_cpu_status_prv; // @[frontend.scala:322:7] wire io_cpu_status_v_0 = io_cpu_status_v; // @[frontend.scala:322:7] wire io_cpu_status_sd_0 = io_cpu_status_sd; // @[frontend.scala:322:7] wire io_cpu_status_mpv_0 = io_cpu_status_mpv; // @[frontend.scala:322:7] wire io_cpu_status_gva_0 = io_cpu_status_gva; // @[frontend.scala:322:7] wire io_cpu_status_tsr_0 = io_cpu_status_tsr; // @[frontend.scala:322:7] wire io_cpu_status_tw_0 = io_cpu_status_tw; // @[frontend.scala:322:7] wire io_cpu_status_tvm_0 = io_cpu_status_tvm; // @[frontend.scala:322:7] wire io_cpu_status_mxr_0 = io_cpu_status_mxr; // @[frontend.scala:322:7] wire io_cpu_status_sum_0 = io_cpu_status_sum; // @[frontend.scala:322:7] wire io_cpu_status_mprv_0 = io_cpu_status_mprv; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_fs_0 = io_cpu_status_fs; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_mpp_0 = io_cpu_status_mpp; // @[frontend.scala:322:7] wire io_cpu_status_spp_0 = io_cpu_status_spp; // @[frontend.scala:322:7] wire io_cpu_status_mpie_0 = io_cpu_status_mpie; // @[frontend.scala:322:7] wire io_cpu_status_spie_0 = io_cpu_status_spie; // @[frontend.scala:322:7] wire io_cpu_status_mie_0 = io_cpu_status_mie; // @[frontend.scala:322:7] wire io_cpu_status_sie_0 = io_cpu_status_sie; // @[frontend.scala:322:7] wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[frontend.scala:322:7] wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[frontend.scala:322:7] wire [15:0] io_cpu_brupdate_b1_resolve_mask_0 = io_cpu_brupdate_b1_resolve_mask; // @[frontend.scala:322:7] wire [15:0] io_cpu_brupdate_b1_mispredict_mask_0 = io_cpu_brupdate_b1_mispredict_mask; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_uopc_0 = io_cpu_brupdate_b2_uop_uopc; // @[frontend.scala:322:7] wire [31:0] io_cpu_brupdate_b2_uop_inst_0 = io_cpu_brupdate_b2_uop_inst; // @[frontend.scala:322:7] wire [31:0] io_cpu_brupdate_b2_uop_debug_inst_0 = io_cpu_brupdate_b2_uop_debug_inst; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_rvc_0 = io_cpu_brupdate_b2_uop_is_rvc; // @[frontend.scala:322:7] wire [39:0] io_cpu_brupdate_b2_uop_debug_pc_0 = io_cpu_brupdate_b2_uop_debug_pc; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_iq_type_0 = io_cpu_brupdate_b2_uop_iq_type; // @[frontend.scala:322:7] wire [9:0] io_cpu_brupdate_b2_uop_fu_code_0 = io_cpu_brupdate_b2_uop_fu_code; // @[frontend.scala:322:7] wire [3:0] io_cpu_brupdate_b2_uop_ctrl_br_type_0 = io_cpu_brupdate_b2_uop_ctrl_br_type; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_ctrl_op1_sel_0 = io_cpu_brupdate_b2_uop_ctrl_op1_sel; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_op2_sel_0 = io_cpu_brupdate_b2_uop_ctrl_op2_sel; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_imm_sel_0 = io_cpu_brupdate_b2_uop_ctrl_imm_sel; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ctrl_op_fcn_0 = io_cpu_brupdate_b2_uop_ctrl_op_fcn; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_fcn_dw_0 = io_cpu_brupdate_b2_uop_ctrl_fcn_dw; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_csr_cmd_0 = io_cpu_brupdate_b2_uop_ctrl_csr_cmd; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_load_0 = io_cpu_brupdate_b2_uop_ctrl_is_load; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_sta_0 = io_cpu_brupdate_b2_uop_ctrl_is_sta; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_std_0 = io_cpu_brupdate_b2_uop_ctrl_is_std; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_iw_state_0 = io_cpu_brupdate_b2_uop_iw_state; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_iw_p1_poisoned_0 = io_cpu_brupdate_b2_uop_iw_p1_poisoned; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_iw_p2_poisoned_0 = io_cpu_brupdate_b2_uop_iw_p2_poisoned; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_br_0 = io_cpu_brupdate_b2_uop_is_br; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_jalr_0 = io_cpu_brupdate_b2_uop_is_jalr; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_jal_0 = io_cpu_brupdate_b2_uop_is_jal; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_sfb_0 = io_cpu_brupdate_b2_uop_is_sfb; // @[frontend.scala:322:7] wire [15:0] io_cpu_brupdate_b2_uop_br_mask_0 = io_cpu_brupdate_b2_uop_br_mask; // @[frontend.scala:322:7] wire [3:0] io_cpu_brupdate_b2_uop_br_tag_0 = io_cpu_brupdate_b2_uop_br_tag; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ftq_idx_0 = io_cpu_brupdate_b2_uop_ftq_idx; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_edge_inst_0 = io_cpu_brupdate_b2_uop_edge_inst; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_pc_lob_0 = io_cpu_brupdate_b2_uop_pc_lob; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_taken_0 = io_cpu_brupdate_b2_uop_taken; // @[frontend.scala:322:7] wire [19:0] io_cpu_brupdate_b2_uop_imm_packed_0 = io_cpu_brupdate_b2_uop_imm_packed; // @[frontend.scala:322:7] wire [11:0] io_cpu_brupdate_b2_uop_csr_addr_0 = io_cpu_brupdate_b2_uop_csr_addr; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_rob_idx_0 = io_cpu_brupdate_b2_uop_rob_idx; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ldq_idx_0 = io_cpu_brupdate_b2_uop_ldq_idx; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_stq_idx_0 = io_cpu_brupdate_b2_uop_stq_idx; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_rxq_idx_0 = io_cpu_brupdate_b2_uop_rxq_idx; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_pdst_0 = io_cpu_brupdate_b2_uop_pdst; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_prs1_0 = io_cpu_brupdate_b2_uop_prs1; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_prs2_0 = io_cpu_brupdate_b2_uop_prs2; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_prs3_0 = io_cpu_brupdate_b2_uop_prs3; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ppred_0 = io_cpu_brupdate_b2_uop_ppred; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs1_busy_0 = io_cpu_brupdate_b2_uop_prs1_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs2_busy_0 = io_cpu_brupdate_b2_uop_prs2_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs3_busy_0 = io_cpu_brupdate_b2_uop_prs3_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ppred_busy_0 = io_cpu_brupdate_b2_uop_ppred_busy; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_stale_pdst_0 = io_cpu_brupdate_b2_uop_stale_pdst; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_exception_0 = io_cpu_brupdate_b2_uop_exception; // @[frontend.scala:322:7] wire [63:0] io_cpu_brupdate_b2_uop_exc_cause_0 = io_cpu_brupdate_b2_uop_exc_cause; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bypassable_0 = io_cpu_brupdate_b2_uop_bypassable; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_mem_cmd_0 = io_cpu_brupdate_b2_uop_mem_cmd; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_mem_size_0 = io_cpu_brupdate_b2_uop_mem_size; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_mem_signed_0 = io_cpu_brupdate_b2_uop_mem_signed; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_fence_0 = io_cpu_brupdate_b2_uop_is_fence; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_fencei_0 = io_cpu_brupdate_b2_uop_is_fencei; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_amo_0 = io_cpu_brupdate_b2_uop_is_amo; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_uses_ldq_0 = io_cpu_brupdate_b2_uop_uses_ldq; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_uses_stq_0 = io_cpu_brupdate_b2_uop_uses_stq; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_sys_pc2epc_0 = io_cpu_brupdate_b2_uop_is_sys_pc2epc; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_unique_0 = io_cpu_brupdate_b2_uop_is_unique; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_flush_on_commit_0 = io_cpu_brupdate_b2_uop_flush_on_commit; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ldst_is_rs1_0 = io_cpu_brupdate_b2_uop_ldst_is_rs1; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_ldst_0 = io_cpu_brupdate_b2_uop_ldst; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs1_0 = io_cpu_brupdate_b2_uop_lrs1; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs2_0 = io_cpu_brupdate_b2_uop_lrs2; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs3_0 = io_cpu_brupdate_b2_uop_lrs3; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ldst_val_0 = io_cpu_brupdate_b2_uop_ldst_val; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_dst_rtype_0 = io_cpu_brupdate_b2_uop_dst_rtype; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_lrs1_rtype_0 = io_cpu_brupdate_b2_uop_lrs1_rtype; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_lrs2_rtype_0 = io_cpu_brupdate_b2_uop_lrs2_rtype; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_frs3_en_0 = io_cpu_brupdate_b2_uop_frs3_en; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_fp_val_0 = io_cpu_brupdate_b2_uop_fp_val; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_fp_single_0 = io_cpu_brupdate_b2_uop_fp_single; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_pf_if_0 = io_cpu_brupdate_b2_uop_xcpt_pf_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_ae_if_0 = io_cpu_brupdate_b2_uop_xcpt_ae_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_ma_if_0 = io_cpu_brupdate_b2_uop_xcpt_ma_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bp_debug_if_0 = io_cpu_brupdate_b2_uop_bp_debug_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bp_xcpt_if_0 = io_cpu_brupdate_b2_uop_bp_xcpt_if; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_debug_fsrc_0 = io_cpu_brupdate_b2_uop_debug_fsrc; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_debug_tsrc_0 = io_cpu_brupdate_b2_uop_debug_tsrc; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_valid_0 = io_cpu_brupdate_b2_valid; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_mispredict_0 = io_cpu_brupdate_b2_mispredict; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_taken_0 = io_cpu_brupdate_b2_taken; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_cfi_type_0 = io_cpu_brupdate_b2_cfi_type; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_pc_sel_0 = io_cpu_brupdate_b2_pc_sel; // @[frontend.scala:322:7] wire [39:0] io_cpu_brupdate_b2_jalr_target_0 = io_cpu_brupdate_b2_jalr_target; // @[frontend.scala:322:7] wire [20:0] io_cpu_brupdate_b2_target_offset_0 = io_cpu_brupdate_b2_target_offset; // @[frontend.scala:322:7] wire io_cpu_redirect_flush_0 = io_cpu_redirect_flush; // @[frontend.scala:322:7] wire io_cpu_redirect_val_0 = io_cpu_redirect_val; // @[frontend.scala:322:7] wire [39:0] io_cpu_redirect_pc_0 = io_cpu_redirect_pc; // @[frontend.scala:322:7] wire [4:0] io_cpu_redirect_ftq_idx_0 = io_cpu_redirect_ftq_idx; // @[frontend.scala:322:7] wire [63:0] io_cpu_redirect_ghist_old_history_0 = io_cpu_redirect_ghist_old_history; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_current_saw_branch_not_taken_0 = io_cpu_redirect_ghist_current_saw_branch_not_taken; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_new_saw_branch_not_taken_0 = io_cpu_redirect_ghist_new_saw_branch_not_taken; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_new_saw_branch_taken_0 = io_cpu_redirect_ghist_new_saw_branch_taken; // @[frontend.scala:322:7] wire [4:0] io_cpu_redirect_ghist_ras_idx_0 = io_cpu_redirect_ghist_ras_idx; // @[frontend.scala:322:7] wire io_cpu_commit_valid_0 = io_cpu_commit_valid; // @[frontend.scala:322:7] wire [31:0] io_cpu_commit_bits_0 = io_cpu_commit_bits; // @[frontend.scala:322:7] wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[frontend.scala:322:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[frontend.scala:322:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[frontend.scala:322:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[frontend.scala:322:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[frontend.scala:322:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[frontend.scala:322:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[frontend.scala:322:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[frontend.scala:322:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[frontend.scala:322:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[frontend.scala:322:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[frontend.scala:322:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[frontend.scala:322:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[frontend.scala:322:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[frontend.scala:322:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[frontend.scala:322:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[frontend.scala:322:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[frontend.scala:322:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[frontend.scala:322:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[frontend.scala:322:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[frontend.scala:322:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[frontend.scala:322:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[frontend.scala:322:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[frontend.scala:322:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[frontend.scala:322:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[frontend.scala:322:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[frontend.scala:322:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[frontend.scala:322:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[frontend.scala:322:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[frontend.scala:322:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[frontend.scala:322:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[frontend.scala:322:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_uopc = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_rob_idx = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_prs1 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_prs2 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_prs3 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_stale_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_uopc = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_rob_idx = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_prs1 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_prs2 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_prs3 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_1_bits_stale_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_uopc = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_rob_idx = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_pdst = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_prs1 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_prs2 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_prs3 = 7'h0; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_2_bits_stale_pdst = 7'h0; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_iq_type = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_op2_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_imm_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_csr_cmd = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_iq_type = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_op2_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_imm_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_csr_cmd = 3'h0; // @[frontend.scala:322:7] wire [9:0] io_cpu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0; // @[frontend.scala:322:7] wire [9:0] io_cpu_fetchpacket_bits_uops_1_bits_fu_code = 10'h0; // @[frontend.scala:322:7] wire [9:0] io_cpu_fetchpacket_bits_uops_2_bits_fu_code = 10'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_0_bits_br_tag = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_br_type = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_1_bits_br_tag = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_br_type = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_2_bits_br_tag = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_op1_sel = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_iw_state = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_rxq_idx = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_mem_size = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_dst_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_tsrc = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_op1_sel = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_iw_state = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_rxq_idx = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_mem_size = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_dst_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs1_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs2_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_tsrc = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] _offset_from_aligned_pc_T_8 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_13 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_18 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_28 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_33 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_38 = 2'h0; // @[frontend.scala:710:12] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ldq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_stq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ppred = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ctrl_op_fcn = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ldq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_stq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ppred = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_mem_cmd = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ctrl_op_fcn = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ldq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_stq_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ppred = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_mem_cmd = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_ghist_ras_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_debug_ftq_idx_0 = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_debug_ftq_idx_1 = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_debug_ftq_idx_2 = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[frontend.scala:322:7] wire [4:0] _s0_ghist_WIRE_ras_idx = 5'h0; // @[frontend.scala:348:45] wire [4:0] _s0_ghist_WIRE_1_ras_idx = 5'h0; // @[frontend.scala:364:33] wire [4:0] f3_fetch_bundle_ftq_idx = 5'h0; // @[frontend.scala:569:29] wire auto_icache_master_out_a_bits_source = 1'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_source = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_br = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_fcn_dw = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_is_load = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_is_sta = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ctrl_is_std = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_iw_p1_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_iw_p2_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_br = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_jalr = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_jal = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_prs1_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_prs2_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_prs3_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ppred_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_exception = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_bypassable = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_mem_signed = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_fence = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_fencei = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_amo = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_uses_ldq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_uses_stq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_unique = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_flush_on_commit = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_ldst_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_frs3_en = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_fp_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_fp_single = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_fcn_dw = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_is_load = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_is_sta = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ctrl_is_std = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_iw_p1_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_iw_p2_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_br = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_jalr = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_jal = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_prs1_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_prs2_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_prs3_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ppred_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_exception = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_bypassable = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_mem_signed = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_fence = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_fencei = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_amo = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_uses_ldq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_uses_stq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_sys_pc2epc = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_unique = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_flush_on_commit = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ldst_is_rs1 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_ldst_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_frs3_en = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_fp_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_fp_single = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ma_if = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_mbe = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_sbe = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_ube = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_upie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_hie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_uie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_hv = 1'h0; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_hg = 1'h0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_mbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_sbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_ube = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_upie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_hie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_uie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtw = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_hu = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_spvp = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_spv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_gva = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_debug = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_cease = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_wfi = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_dv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_v = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sd = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mpv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_gva = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tsr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tw = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tvm = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mxr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sum = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mprv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_spp = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mpie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_ube = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_spie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_upie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_hie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_uie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[frontend.scala:322:7] wire _s0_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:348:45] wire _s0_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:348:45] wire _s0_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[frontend.scala:348:45] wire s0_replay_bpd_resp_lhist_0 = 1'h0; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_lhist_1 = 1'h0; // @[frontend.scala:354:32] wire _s0_ghist_WIRE_1_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:364:33] wire _s0_ghist_WIRE_1_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:364:33] wire _s0_ghist_WIRE_1_new_saw_branch_taken = 1'h0; // @[frontend.scala:364:33] wire f1_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire _f1_predicted_ghist_new_history_ras_idx_T = 1'h0; // @[frontend.scala:123:42] wire _f1_predicted_ghist_new_history_ras_idx_T_4 = 1'h0; // @[frontend.scala:124:42] wire f2_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire _f2_predicted_ghist_new_history_ras_idx_T = 1'h0; // @[frontend.scala:123:42] wire _f2_predicted_ghist_new_history_ras_idx_T_4 = 1'h0; // @[frontend.scala:124:42] wire f3_shadowed_mask_0 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_1 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_2 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_3 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_4 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_5 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_6 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_7 = 1'h0; // @[frontend.scala:568:30] wire f3_fetch_bundle_shadowed_mask_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_4 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_5 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_6 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_7 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_4 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_5 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_6 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_7 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_4 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_5 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_6 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_7 = 1'h0; // @[frontend.scala:569:29] wire _offset_from_aligned_pc_T_7 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_12 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_17 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_27 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_32 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_37 = 1'h0; // @[frontend.scala:710:31] wire f3_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire _f4_sfbs_T_17 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_35 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_53 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_71 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_89 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_107 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_125 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_143 = 1'h0; // @[frontend.scala:876:20] wire f4_sfbs_0 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_1 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_2 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_3 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_4 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_5 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_6 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_7 = 1'h0; // @[frontend.scala:875:24] wire _f4_sfb_valid_T = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_1 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_2 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_3 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_4 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_5 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_6 = 1'h0; // @[frontend.scala:890:38] wire f4_sfb_valid = 1'h0; // @[frontend.scala:890:43] wire [15:0] io_cpu_fetchpacket_bits_uops_0_bits_br_mask = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_cpu_fetchpacket_bits_uops_1_bits_br_mask = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_cpu_fetchpacket_bits_uops_2_bits_br_mask = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_1 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_2 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_3 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_2 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_3 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_3 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_4 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_5 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_6 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_7 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_15 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_8 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_9 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_10 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_11 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_12 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_13 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_14 = 16'h0; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_15 = 16'h0; // @[util.scala:373:29] wire [19:0] io_cpu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[frontend.scala:322:7] wire [19:0] io_cpu_fetchpacket_bits_uops_1_bits_imm_packed = 20'h0; // @[frontend.scala:322:7] wire [19:0] io_cpu_fetchpacket_bits_uops_2_bits_imm_packed = 20'h0; // @[frontend.scala:322:7] wire [11:0] io_cpu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0; // @[frontend.scala:322:7] wire [11:0] io_cpu_fetchpacket_bits_uops_1_bits_csr_addr = 12'h0; // @[frontend.scala:322:7] wire [11:0] io_cpu_fetchpacket_bits_uops_2_bits_csr_addr = 12'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_fetchpacket_bits_uops_1_bits_exc_cause = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_fetchpacket_bits_uops_2_bits_exc_cause = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_get_pc_0_ghist_old_history = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] _s0_ghist_WIRE_old_history = 64'h0; // @[frontend.scala:348:45] wire [63:0] _s0_ghist_WIRE_1_old_history = 64'h0; // @[frontend.scala:364:33] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_ldst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_lrs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_ldst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_lrs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[frontend.scala:322:7] wire [31:0] io_cpu_status_isa = 32'h14112D; // @[frontend.scala:322:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[frontend.scala:322:7] wire [22:0] io_cpu_status_zero2 = 23'h0; // @[frontend.scala:322:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[frontend.scala:322:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[frontend.scala:322:7] wire [7:0] io_cpu_status_zero1 = 8'h0; // @[frontend.scala:322:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[frontend.scala:322:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[frontend.scala:322:7] wire [15:0] auto_icache_master_out_a_bits_mask = 16'hFFFF; // @[frontend.scala:322:7] wire [127:0] auto_icache_master_out_a_bits_data = 128'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_d_ready = 1'h1; // @[frontend.scala:322:7] wire io_ptw_req_bits_valid = 1'h1; // @[frontend.scala:322:7] wire valid = 1'h1; // @[frontend.scala:605:23] wire _bank_mask_0_T_3 = 1'h1; // @[frontend.scala:689:74] wire _f3_mask_0_T_3 = 1'h1; // @[frontend.scala:690:74] wire valid_4 = 1'h1; // @[frontend.scala:605:23] wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[frontend.scala:322:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [1:0] io_cpu_status_sxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_uxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] _lower_mask_T_1 = 2'h2; // @[OneHot.scala:58:35] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[frontend.scala:322:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[frontend.scala:322:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[frontend.scala:322:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[frontend.scala:322:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[frontend.scala:322:7] wire [2:0] _f4_sfb_idx_T = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_1 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_2 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_3 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_4 = 3'h7; // @[Mux.scala:50:70] wire [2:0] _f4_sfb_idx_T_5 = 3'h7; // @[Mux.scala:50:70] wire [2:0] f4_sfb_idx = 3'h7; // @[Mux.scala:50:70] wire [7:0] _f1_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:180:81] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire [7:0] _f2_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:180:81] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire [7:0] _f3_io_enq_bits_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:180:81] wire [7:0] _f3_predicted_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_31 = 16'hFF00; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_22 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_23 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_24 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_25 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_26 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_27 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_28 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_29 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_30 = 16'hFF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_21 = 16'hFE; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_20 = 16'hFC; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_19 = 16'hF8; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_18 = 16'hF0; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_17 = 16'hE0; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_16 = 16'hC0; // @[util.scala:373:45] wire [15:0] lower_mask = 16'h1; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_16 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_17 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_18 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_19 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_20 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_21 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_22 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_23 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_24 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_25 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_26 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_27 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_28 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_29 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_30 = 16'h1; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_1 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_2 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_3 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_4 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_5 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_6 = 16'h1; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_7 = 16'h1; // @[util.scala:373:29] wire [15:0] lower_mask_1 = 16'h2; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_1 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_2 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_3 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_4 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_5 = 16'h2; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_6 = 16'h2; // @[util.scala:373:29] wire [15:0] lower_mask_2 = 16'h4; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_1 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_2 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_3 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_4 = 16'h4; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_5 = 16'h4; // @[util.scala:373:29] wire [15:0] lower_mask_3 = 16'h8; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_1 = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_2 = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_3 = 16'h8; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_4 = 16'h8; // @[util.scala:373:29] wire [15:0] lower_mask_4 = 16'h10; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T = 16'h10; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_1 = 16'h10; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_2 = 16'h10; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_3 = 16'h10; // @[util.scala:373:29] wire [15:0] lower_mask_5 = 16'h20; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T = 16'h20; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_1 = 16'h20; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_2 = 16'h20; // @[util.scala:373:29] wire [15:0] lower_mask_6 = 16'h40; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T = 16'h40; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_1 = 16'h40; // @[util.scala:373:29] wire [15:0] lower_mask_7 = 16'h80; // @[frontend.scala:712:28] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T = 16'h80; // @[util.scala:373:29] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_31 = 16'hFF80; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_21 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_22 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_23 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_24 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_25 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_26 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_27 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_28 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_29 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_30 = 16'h7F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_20 = 16'h7E; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_19 = 16'h7C; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_18 = 16'h78; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_17 = 16'h70; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_16 = 16'h60; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_31 = 16'hFFC0; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_20 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_21 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_22 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_23 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_24 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_25 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_26 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_27 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_28 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_29 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_30 = 16'h3F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_19 = 16'h3E; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_18 = 16'h3C; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_17 = 16'h38; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_16 = 16'h30; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_31 = 16'hFFE0; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_19 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_20 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_21 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_22 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_23 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_24 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_25 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_26 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_27 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_28 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_29 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_30 = 16'h1F; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_18 = 16'h1E; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_17 = 16'h1C; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_16 = 16'h18; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_31 = 16'hFFF0; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_18 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_19 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_20 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_21 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_22 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_23 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_24 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_25 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_26 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_27 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_28 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_29 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_30 = 16'hF; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_17 = 16'hE; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_16 = 16'hC; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_31 = 16'hFFF8; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_17 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_18 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_19 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_20 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_21 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_22 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_23 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_24 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_25 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_26 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_27 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_28 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_29 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_30 = 16'h7; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_16 = 16'h6; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_31 = 16'hFFFC; // @[frontend.scala:722:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_16 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_17 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_18 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_19 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_20 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_21 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_22 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_23 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_24 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_25 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_26 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_27 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_28 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_29 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_30 = 16'h3; // @[util.scala:373:45] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_31 = 16'hFFFE; // @[frontend.scala:722:45] wire [119:0] s0_replay_bpd_resp_meta_0 = 120'h0; // @[frontend.scala:354:32] wire [119:0] s0_replay_bpd_resp_meta_1 = 120'h0; // @[frontend.scala:354:32] wire [7:0] _lower_mask_T_7 = 8'h80; // @[OneHot.scala:58:35] wire [7:0] _lower_mask_T_6 = 8'h40; // @[OneHot.scala:58:35] wire [7:0] _lower_mask_T_5 = 8'h20; // @[OneHot.scala:58:35] wire [7:0] _lower_mask_T_4 = 8'h10; // @[OneHot.scala:58:35] wire [3:0] _lower_mask_T_2 = 4'h4; // @[OneHot.scala:58:35] wire [1:0] _lower_mask_T = 2'h1; // @[OneHot.scala:58:35] wire [3:0] _lower_mask_T_3 = 4'h8; // @[OneHot.scala:58:35] wire [3:0] _f1_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:180:56] wire [3:0] _f2_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:180:56] wire [3:0] _f3_io_enq_bits_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:180:56] wire s0_is_sfence = io_cpu_sfence_valid_0; // @[frontend.scala:322:7, :352:30] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire [31:0] auto_icache_master_out_a_bits_address_0; // @[frontend.scala:322:7] wire auto_icache_master_out_a_valid_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_0_bits_inst_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_inst_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_rvc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_pc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_sfb_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_edge_inst_0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_pc_lob_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_taken_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_valid_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_1_bits_inst_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_inst_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_rvc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_pc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_is_sfb_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_edge_inst_0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_1_bits_pc_lob_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_taken_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_1_valid_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_2_bits_inst_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_inst_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_rvc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_pc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_is_sfb_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_edge_inst_0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_2_bits_pc_lob_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_taken_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_2_valid_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_valid_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_idx_valid_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_0_entry_cfi_idx_bits_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_mispredicted_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_0_entry_cfi_type_0; // @[frontend.scala:322:7] wire [7:0] io_cpu_get_pc_0_entry_br_mask_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_is_call_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_is_ret_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_npc_plus4_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_entry_ras_top_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_entry_ras_idx_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_start_bank_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_com_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_next_val_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_next_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_idx_valid_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_1_entry_cfi_idx_bits_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_mispredicted_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_1_entry_cfi_type_0; // @[frontend.scala:322:7] wire [7:0] io_cpu_get_pc_1_entry_br_mask_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_is_call_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_is_ret_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_npc_plus4_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_entry_ras_top_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_entry_ras_idx_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_start_bank_0; // @[frontend.scala:322:7] wire [63:0] io_cpu_get_pc_1_ghist_old_history_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_new_saw_branch_not_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_new_saw_branch_taken_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_ghist_ras_idx_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_com_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_next_val_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_next_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_debug_fetch_pc_0_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_debug_fetch_pc_1_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_debug_fetch_pc_2_0; // @[frontend.scala:322:7] wire io_cpu_perf_acquire_0; // @[frontend.scala:322:7] wire io_cpu_perf_tlbMiss_0; // @[frontend.scala:322:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[frontend.scala:322:7] wire io_ptw_req_valid_0; // @[frontend.scala:322:7] assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_cpu_perf_tlbMiss_0 = _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire [39:0] s0_vpc; // @[frontend.scala:347:30] wire [63:0] s0_ghist_old_history; // @[frontend.scala:348:30] wire s0_ghist_current_saw_branch_not_taken; // @[frontend.scala:348:30] wire s0_ghist_new_saw_branch_not_taken; // @[frontend.scala:348:30] wire s0_ghist_new_saw_branch_taken; // @[frontend.scala:348:30] wire [4:0] s0_ghist_ras_idx; // @[frontend.scala:348:30] wire [1:0] s0_tsrc; // @[frontend.scala:349:30] wire s0_valid; // @[frontend.scala:350:30] wire s0_is_replay; // @[frontend.scala:351:30] wire s0_replay_resp_pf_ld; // @[frontend.scala:353:28] wire s0_replay_resp_pf_st; // @[frontend.scala:353:28] wire s0_replay_resp_pf_inst; // @[frontend.scala:353:28] wire s0_replay_resp_gf_ld; // @[frontend.scala:353:28] wire s0_replay_resp_gf_st; // @[frontend.scala:353:28] wire s0_replay_resp_gf_inst; // @[frontend.scala:353:28] wire s0_replay_resp_ae_ld; // @[frontend.scala:353:28] wire s0_replay_resp_ae_st; // @[frontend.scala:353:28] wire s0_replay_resp_ae_inst; // @[frontend.scala:353:28] wire s0_replay_resp_ma_ld; // @[frontend.scala:353:28] wire s0_replay_resp_ma_st; // @[frontend.scala:353:28] wire s0_replay_resp_ma_inst; // @[frontend.scala:353:28] wire s0_replay_resp_miss; // @[frontend.scala:353:28] wire [31:0] s0_replay_resp_paddr; // @[frontend.scala:353:28] wire [39:0] s0_replay_resp_gpa; // @[frontend.scala:353:28] wire s0_replay_resp_gpa_is_pte; // @[frontend.scala:353:28] wire s0_replay_resp_cacheable; // @[frontend.scala:353:28] wire s0_replay_resp_must_alloc; // @[frontend.scala:353:28] wire s0_replay_resp_prefetchable; // @[frontend.scala:353:28] wire [2:0] s0_replay_resp_size; // @[frontend.scala:353:28] wire [4:0] s0_replay_resp_cmd; // @[frontend.scala:353:28] wire s0_replay_bpd_resp_preds_0_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_0_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_1_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_2_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_3_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_4_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_4_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_5_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_5_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_6_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_6_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_7_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_7_is_jal; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_pc; // @[frontend.scala:354:32] wire [31:0] s0_replay_ppc; // @[frontend.scala:355:28] wire s0_s1_use_f3_bpd_resp; // @[frontend.scala:356:39] reg REG; // @[frontend.scala:361:16] wire _T_3 = REG & ~reset; // @[frontend.scala:361:{16,31,34}] reg [39:0] s1_vpc; // @[frontend.scala:379:29] reg s1_valid; // @[frontend.scala:380:29] reg [63:0] s1_ghist_old_history; // @[frontend.scala:381:29] reg s1_ghist_current_saw_branch_not_taken; // @[frontend.scala:381:29] reg s1_ghist_new_saw_branch_not_taken; // @[frontend.scala:381:29] reg s1_ghist_new_saw_branch_taken; // @[frontend.scala:381:29] reg [4:0] s1_ghist_ras_idx; // @[frontend.scala:381:29] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_8 = s1_ghist_ras_idx; // @[frontend.scala:124:31, :381:29] reg s1_is_replay; // @[frontend.scala:382:29] reg s1_is_sfence; // @[frontend.scala:383:29] wire f1_clear; // @[frontend.scala:384:30] reg [1:0] s1_tsrc; // @[frontend.scala:385:29] wire _tlb_io_req_valid_T = ~s1_is_replay; // @[frontend.scala:382:29, :386:41] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[frontend.scala:380:29, :386:{38,41}] wire _tlb_io_req_valid_T_2 = ~f1_clear; // @[frontend.scala:384:30, :386:58] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_1 & _tlb_io_req_valid_T_2; // @[frontend.scala:386:{38,55,58}] wire _tlb_io_req_valid_T_4 = _tlb_io_req_valid_T_3 | s1_is_sfence; // @[frontend.scala:383:29, :386:{55,69}] reg tlb_io_sfence_REG_valid; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_rs1; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_rs2; // @[frontend.scala:393:35] reg [38:0] tlb_io_sfence_REG_bits_addr; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_asid; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_hv; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_hg; // @[frontend.scala:393:35] wire _s1_tlb_miss_T = ~s1_is_replay; // @[frontend.scala:382:29, :386:41, :396:21] wire s1_tlb_miss = _s1_tlb_miss_T & _tlb_io_resp_miss; // @[frontend.scala:337:19, :396:{21,35}] reg s1_tlb_resp_REG_miss; // @[frontend.scala:397:46] reg [31:0] s1_tlb_resp_REG_paddr; // @[frontend.scala:397:46] reg [39:0] s1_tlb_resp_REG_gpa; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gpa_is_pte; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_cacheable; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_must_alloc; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_prefetchable; // @[frontend.scala:397:46] reg [2:0] s1_tlb_resp_REG_size; // @[frontend.scala:397:46] reg [4:0] s1_tlb_resp_REG_cmd; // @[frontend.scala:397:46] wire s1_tlb_resp_miss = s1_is_replay ? s1_tlb_resp_REG_miss : _tlb_io_resp_miss; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [31:0] s1_tlb_resp_paddr = s1_is_replay ? s1_tlb_resp_REG_paddr : _tlb_io_resp_paddr; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [39:0] s1_tlb_resp_gpa = s1_is_replay ? s1_tlb_resp_REG_gpa : _tlb_io_resp_gpa; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_gpa_is_pte = s1_is_replay & s1_tlb_resp_REG_gpa_is_pte; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_pf_ld = s1_is_replay ? s1_tlb_resp_REG_pf_ld : _tlb_io_resp_pf_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_pf_st = s1_is_replay & s1_tlb_resp_REG_pf_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_pf_inst = s1_is_replay ? s1_tlb_resp_REG_pf_inst : _tlb_io_resp_pf_inst; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_gf_ld = s1_is_replay & s1_tlb_resp_REG_gf_ld; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_gf_st = s1_is_replay & s1_tlb_resp_REG_gf_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_gf_inst = s1_is_replay & s1_tlb_resp_REG_gf_inst; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ae_ld = s1_is_replay ? s1_tlb_resp_REG_ae_ld : _tlb_io_resp_ae_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ae_st = s1_is_replay & s1_tlb_resp_REG_ae_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ae_inst = s1_is_replay ? s1_tlb_resp_REG_ae_inst : _tlb_io_resp_ae_inst; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ma_ld = s1_is_replay ? s1_tlb_resp_REG_ma_ld : _tlb_io_resp_ma_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ma_st = s1_is_replay & s1_tlb_resp_REG_ma_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ma_inst = s1_is_replay & s1_tlb_resp_REG_ma_inst; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_cacheable = s1_is_replay ? s1_tlb_resp_REG_cacheable : _tlb_io_resp_cacheable; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_must_alloc = s1_is_replay & s1_tlb_resp_REG_must_alloc; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_prefetchable = s1_is_replay ? s1_tlb_resp_REG_prefetchable : _tlb_io_resp_prefetchable; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [2:0] s1_tlb_resp_size = s1_is_replay ? s1_tlb_resp_REG_size : 3'h4; // @[frontend.scala:382:29, :397:{24,46}] wire [4:0] s1_tlb_resp_cmd = s1_is_replay ? s1_tlb_resp_REG_cmd : 5'h0; // @[frontend.scala:382:29, :397:{24,46}] reg [31:0] s1_ppc_REG; // @[frontend.scala:398:42] wire [31:0] s1_ppc = s1_is_replay ? s1_ppc_REG : _tlb_io_resp_paddr; // @[frontend.scala:337:19, :382:29, :398:{20,42}] wire _icache_io_s1_kill_T = _tlb_io_resp_miss | f1_clear; // @[frontend.scala:337:19, :384:30, :402:42] wire [2:0] f1_mask_idx = s1_vpc[3:1]; // @[package.scala:163:13] wire [1:0] f1_mask_shamt = f1_mask_idx[1:0]; // @[package.scala:163:13] wire [2:0] _f1_mask_end_mask_T = s1_vpc[5:3]; // @[frontend.scala:152:28, :379:29] wire [2:0] _f1_predicted_target_T_17 = s1_vpc[5:3]; // @[frontend.scala:152:28, :379:29] wire [2:0] _f1_predicted_ghist_ignore_second_bank_T = s1_vpc[5:3]; // @[frontend.scala:152:28, :379:29] wire _f1_mask_end_mask_T_1 = &_f1_mask_end_mask_T; // @[frontend.scala:152:{28,66}] wire _f1_mask_end_mask_T_2 = _f1_mask_end_mask_T_1; // @[frontend.scala:152:{21,66}] wire [7:0] f1_mask_end_mask = _f1_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:152:21, :180:25] wire [10:0] _f1_mask_T = 11'hFF << f1_mask_shamt; // @[package.scala:163:13] wire [10:0] f1_mask = {3'h0, _f1_mask_T[7:0] & f1_mask_end_mask}; // @[frontend.scala:180:25, :181:{31,40}] wire _f1_redirects_T = f1_mask[0]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_1 = s1_valid & _f1_redirects_T; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_2 = _f1_redirects_T_1 & _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_3 = _bpd_io_resp_f1_preds_0_is_br & _bpd_io_resp_f1_preds_0_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_4 = _bpd_io_resp_f1_preds_0_is_jal | _f1_redirects_T_3; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_0 = _f1_redirects_T_2 & _f1_redirects_T_4; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_5 = f1_mask[1]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_6 = s1_valid & _f1_redirects_T_5; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_7 = _f1_redirects_T_6 & _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_8 = _bpd_io_resp_f1_preds_1_is_br & _bpd_io_resp_f1_preds_1_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_9 = _bpd_io_resp_f1_preds_1_is_jal | _f1_redirects_T_8; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_1 = _f1_redirects_T_7 & _f1_redirects_T_9; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_10 = f1_mask[2]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_11 = s1_valid & _f1_redirects_T_10; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_12 = _f1_redirects_T_11 & _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_13 = _bpd_io_resp_f1_preds_2_is_br & _bpd_io_resp_f1_preds_2_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_14 = _bpd_io_resp_f1_preds_2_is_jal | _f1_redirects_T_13; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_2 = _f1_redirects_T_12 & _f1_redirects_T_14; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_15 = f1_mask[3]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_16 = s1_valid & _f1_redirects_T_15; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_17 = _f1_redirects_T_16 & _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_18 = _bpd_io_resp_f1_preds_3_is_br & _bpd_io_resp_f1_preds_3_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_19 = _bpd_io_resp_f1_preds_3_is_jal | _f1_redirects_T_18; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_3 = _f1_redirects_T_17 & _f1_redirects_T_19; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_20 = f1_mask[4]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_21 = s1_valid & _f1_redirects_T_20; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_22 = _f1_redirects_T_21 & _bpd_io_resp_f1_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_23 = _bpd_io_resp_f1_preds_4_is_br & _bpd_io_resp_f1_preds_4_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_24 = _bpd_io_resp_f1_preds_4_is_jal | _f1_redirects_T_23; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_4 = _f1_redirects_T_22 & _f1_redirects_T_24; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_25 = f1_mask[5]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_26 = s1_valid & _f1_redirects_T_25; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_27 = _f1_redirects_T_26 & _bpd_io_resp_f1_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_28 = _bpd_io_resp_f1_preds_5_is_br & _bpd_io_resp_f1_preds_5_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_29 = _bpd_io_resp_f1_preds_5_is_jal | _f1_redirects_T_28; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_5 = _f1_redirects_T_27 & _f1_redirects_T_29; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_30 = f1_mask[6]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_31 = s1_valid & _f1_redirects_T_30; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_32 = _f1_redirects_T_31 & _bpd_io_resp_f1_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_33 = _bpd_io_resp_f1_preds_6_is_br & _bpd_io_resp_f1_preds_6_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_34 = _bpd_io_resp_f1_preds_6_is_jal | _f1_redirects_T_33; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_6 = _f1_redirects_T_32 & _f1_redirects_T_34; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_35 = f1_mask[7]; // @[frontend.scala:181:40, :406:24] wire _f1_redirects_T_36 = s1_valid & _f1_redirects_T_35; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_37 = _f1_redirects_T_36 & _bpd_io_resp_f1_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_38 = _bpd_io_resp_f1_preds_7_is_br & _bpd_io_resp_f1_preds_7_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_39 = _bpd_io_resp_f1_preds_7_is_jal | _f1_redirects_T_38; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_7 = _f1_redirects_T_37 & _f1_redirects_T_39; // @[frontend.scala:406:{28,71}, :407:34] wire [2:0] _f1_redirect_idx_T = {2'h3, ~f1_redirects_6}; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_1 = f1_redirects_5 ? 3'h5 : _f1_redirect_idx_T; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_2 = f1_redirects_4 ? 3'h4 : _f1_redirect_idx_T_1; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_3 = f1_redirects_3 ? 3'h3 : _f1_redirect_idx_T_2; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_4 = f1_redirects_2 ? 3'h2 : _f1_redirect_idx_T_3; // @[Mux.scala:50:70] wire [2:0] _f1_redirect_idx_T_5 = f1_redirects_1 ? 3'h1 : _f1_redirect_idx_T_4; // @[Mux.scala:50:70] wire [2:0] f1_redirect_idx = f1_redirects_0 ? 3'h0 : _f1_redirect_idx_T_5; // @[Mux.scala:50:70] wire [2:0] f1_predicted_ghist_cfi_idx_fixed = f1_redirect_idx; // @[Mux.scala:50:70] wire _f1_do_redirect_T = f1_redirects_0 | f1_redirects_1; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_1 = _f1_do_redirect_T | f1_redirects_2; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_2 = _f1_do_redirect_T_1 | f1_redirects_3; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_3 = _f1_do_redirect_T_2 | f1_redirects_4; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_4 = _f1_do_redirect_T_3 | f1_redirects_5; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_5 = _f1_do_redirect_T_4 | f1_redirects_6; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_6 = _f1_do_redirect_T_5 | f1_redirects_7; // @[frontend.scala:406:71, :411:45] wire f1_do_redirect = _f1_do_redirect_T_6; // @[frontend.scala:411:{45,50}] wire _f1_predicted_target_T = f1_redirect_idx == 3'h1; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_1 = _f1_predicted_target_T ? _bpd_io_resp_f1_preds_1_predicted_pc_bits : _bpd_io_resp_f1_preds_0_predicted_pc_bits; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_2 = f1_redirect_idx == 3'h2; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_3 = _f1_predicted_target_T_2 ? _bpd_io_resp_f1_preds_2_predicted_pc_bits : _f1_predicted_target_T_1; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_4 = f1_redirect_idx == 3'h3; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_5 = _f1_predicted_target_T_4 ? _bpd_io_resp_f1_preds_3_predicted_pc_bits : _f1_predicted_target_T_3; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_6 = f1_redirect_idx == 3'h4; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_7 = _f1_predicted_target_T_6 ? _bpd_io_resp_f1_preds_4_predicted_pc_bits : _f1_predicted_target_T_5; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_8 = f1_redirect_idx == 3'h5; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_9 = _f1_predicted_target_T_8 ? _bpd_io_resp_f1_preds_5_predicted_pc_bits : _f1_predicted_target_T_7; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_10 = f1_redirect_idx == 3'h6; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_11 = _f1_predicted_target_T_10 ? _bpd_io_resp_f1_preds_6_predicted_pc_bits : _f1_predicted_target_T_9; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_12 = &f1_redirect_idx; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_13 = _f1_predicted_target_T_12 ? _bpd_io_resp_f1_preds_7_predicted_pc_bits : _f1_predicted_target_T_11; // @[package.scala:39:{76,86}] wire [39:0] _f1_predicted_target_T_14 = ~s1_vpc; // @[frontend.scala:160:33, :379:29] wire [39:0] _f1_predicted_target_T_15 = {_f1_predicted_target_T_14[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _f1_predicted_target_T_16 = ~_f1_predicted_target_T_15; // @[frontend.scala:160:{31,39}] wire _f1_predicted_target_T_18 = &_f1_predicted_target_T_17; // @[frontend.scala:152:{28,66}] wire _f1_predicted_target_T_19 = _f1_predicted_target_T_18; // @[frontend.scala:152:{21,66}] wire [4:0] _f1_predicted_target_T_20 = _f1_predicted_target_T_19 ? 5'h8 : 5'h10; // @[frontend.scala:152:21, :170:28] wire [40:0] _f1_predicted_target_T_21 = {1'h0, _f1_predicted_target_T_16} + {36'h0, _f1_predicted_target_T_20}; // @[frontend.scala:160:31, :170:{23,28}] wire [39:0] _f1_predicted_target_T_22 = _f1_predicted_target_T_21[39:0]; // @[frontend.scala:170:23] wire [39:0] f1_predicted_target = f1_do_redirect ? _f1_predicted_target_T_13 : _f1_predicted_target_T_22; // @[package.scala:39:76] wire _f1_predicted_ghist_T = _bpd_io_resp_f1_preds_0_is_br & _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_1 = _bpd_io_resp_f1_preds_1_is_br & _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_2 = _bpd_io_resp_f1_preds_2_is_br & _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_3 = _bpd_io_resp_f1_preds_3_is_br & _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_4 = _bpd_io_resp_f1_preds_4_is_br & _bpd_io_resp_f1_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_5 = _bpd_io_resp_f1_preds_5_is_br & _bpd_io_resp_f1_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_6 = _bpd_io_resp_f1_preds_6_is_br & _bpd_io_resp_f1_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_7 = _bpd_io_resp_f1_preds_7_is_br & _bpd_io_resp_f1_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire [1:0] f1_predicted_ghist_lo_lo = {_f1_predicted_ghist_T_1, _f1_predicted_ghist_T}; // @[package.scala:45:27] wire [1:0] f1_predicted_ghist_lo_hi = {_f1_predicted_ghist_T_3, _f1_predicted_ghist_T_2}; // @[package.scala:45:27] wire [3:0] f1_predicted_ghist_lo = {f1_predicted_ghist_lo_hi, f1_predicted_ghist_lo_lo}; // @[package.scala:45:27] wire [1:0] f1_predicted_ghist_hi_lo = {_f1_predicted_ghist_T_5, _f1_predicted_ghist_T_4}; // @[package.scala:45:27] wire [1:0] f1_predicted_ghist_hi_hi = {_f1_predicted_ghist_T_7, _f1_predicted_ghist_T_6}; // @[package.scala:45:27] wire [3:0] f1_predicted_ghist_hi = {f1_predicted_ghist_hi_hi, f1_predicted_ghist_hi_lo}; // @[package.scala:45:27] wire [7:0] _f1_predicted_ghist_T_8 = {f1_predicted_ghist_hi, f1_predicted_ghist_lo}; // @[package.scala:45:27] wire [10:0] _f1_predicted_ghist_T_9 = {3'h0, f1_mask[7:0] & _f1_predicted_ghist_T_8}; // @[package.scala:45:27] wire [7:0] _GEN = {{_bpd_io_resp_f1_preds_7_taken}, {_bpd_io_resp_f1_preds_6_taken}, {_bpd_io_resp_f1_preds_5_taken}, {_bpd_io_resp_f1_preds_4_taken}, {_bpd_io_resp_f1_preds_3_taken}, {_bpd_io_resp_f1_preds_2_taken}, {_bpd_io_resp_f1_preds_1_taken}, {_bpd_io_resp_f1_preds_0_taken}}; // @[frontend.scala:331:19, :419:46] wire [7:0] _GEN_0 = {{_bpd_io_resp_f1_preds_7_is_br}, {_bpd_io_resp_f1_preds_6_is_br}, {_bpd_io_resp_f1_preds_5_is_br}, {_bpd_io_resp_f1_preds_4_is_br}, {_bpd_io_resp_f1_preds_3_is_br}, {_bpd_io_resp_f1_preds_2_is_br}, {_bpd_io_resp_f1_preds_1_is_br}, {_bpd_io_resp_f1_preds_0_is_br}}; // @[frontend.scala:331:19, :419:46] wire _f1_predicted_ghist_T_10 = _GEN[f1_redirect_idx] & f1_do_redirect; // @[Mux.scala:50:70] wire [7:0] f1_predicted_ghist_cfi_idx_oh = 8'h1 << f1_predicted_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T = f1_predicted_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] f1_predicted_ghist_old_history; // @[frontend.scala:87:27] wire f1_predicted_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire f1_predicted_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] f1_predicted_ghist_ras_idx; // @[frontend.scala:87:27] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_1 = {1'h0, f1_predicted_ghist_cfi_idx_oh[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_2 = {2'h0, f1_predicted_ghist_cfi_idx_oh[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_3 = {3'h0, f1_predicted_ghist_cfi_idx_oh[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_4 = {4'h0, f1_predicted_ghist_cfi_idx_oh[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_5 = {5'h0, f1_predicted_ghist_cfi_idx_oh[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_6 = {6'h0, f1_predicted_ghist_cfi_idx_oh[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_7 = {7'h0, f1_predicted_ghist_cfi_idx_oh[7]}; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_8 = _f1_predicted_ghist_not_taken_branches_T | _f1_predicted_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_9 = _f1_predicted_ghist_not_taken_branches_T_8 | _f1_predicted_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_10 = _f1_predicted_ghist_not_taken_branches_T_9 | _f1_predicted_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_11 = _f1_predicted_ghist_not_taken_branches_T_10 | _f1_predicted_ghist_not_taken_branches_T_4; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_12 = _f1_predicted_ghist_not_taken_branches_T_11 | _f1_predicted_ghist_not_taken_branches_T_5; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_13 = _f1_predicted_ghist_not_taken_branches_T_12 | _f1_predicted_ghist_not_taken_branches_T_6; // @[util.scala:373:{29,45}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_14 = _f1_predicted_ghist_not_taken_branches_T_13 | _f1_predicted_ghist_not_taken_branches_T_7; // @[util.scala:373:{29,45}] wire _f1_predicted_ghist_not_taken_branches_T_15 = _GEN_0[f1_redirect_idx] & _f1_predicted_ghist_T_10; // @[Mux.scala:50:70] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_16 = _f1_predicted_ghist_not_taken_branches_T_15 ? f1_predicted_ghist_cfi_idx_oh : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_17 = ~_f1_predicted_ghist_not_taken_branches_T_16; // @[frontend.scala:90:{69,73}] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_18 = _f1_predicted_ghist_not_taken_branches_T_14 & _f1_predicted_ghist_not_taken_branches_T_17; // @[util.scala:373:45] wire [7:0] _f1_predicted_ghist_not_taken_branches_T_20 = f1_do_redirect ? _f1_predicted_ghist_not_taken_branches_T_18 : 8'hFF; // @[frontend.scala:89:44, :90:67, :411:50] wire [10:0] f1_predicted_ghist_not_taken_branches = {3'h0, _f1_predicted_ghist_T_9[7:0] & _f1_predicted_ghist_not_taken_branches_T_20}; // @[frontend.scala:89:{39,44}, :418:72] wire [64:0] _GEN_1 = {s1_ghist_old_history, 1'h0}; // @[frontend.scala:67:75, :381:29] wire [64:0] _f1_predicted_ghist_base_T; // @[frontend.scala:67:75] assign _f1_predicted_ghist_base_T = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_base_T_2; // @[frontend.scala:68:75] assign _f1_predicted_ghist_base_T_2 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_2; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_2 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_6; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T_6 = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_8; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_8 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_13; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T_13 = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_15; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_15 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_19; // @[frontend.scala:67:75] assign _f1_predicted_ghist_new_history_old_history_T_19 = _GEN_1; // @[frontend.scala:67:75] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_21; // @[frontend.scala:68:75] assign _f1_predicted_ghist_new_history_old_history_T_21 = _GEN_1; // @[frontend.scala:67:75, :68:75] wire [64:0] _f1_predicted_ghist_base_T_1 = {_f1_predicted_ghist_base_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _GEN_2 = {1'h0, s1_ghist_old_history}; // @[frontend.scala:68:12, :381:29] wire [64:0] _f1_predicted_ghist_base_T_3 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_base_T_2 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] f1_predicted_ghist_base = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_base_T_1 : _f1_predicted_ghist_base_T_3; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire _GEN_3 = f1_do_redirect & _f1_predicted_ghist_T_10; // @[frontend.scala:104:37, :411:50, :419:46] wire _f1_predicted_ghist_cfi_in_bank_0_T; // @[frontend.scala:104:37] assign _f1_predicted_ghist_cfi_in_bank_0_T = _GEN_3; // @[frontend.scala:104:37] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1; // @[frontend.scala:119:59] assign _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1 = _GEN_3; // @[frontend.scala:104:37, :119:59] wire _f1_predicted_ghist_cfi_in_bank_0_T_1 = ~(f1_predicted_ghist_cfi_idx_fixed[2]); // @[frontend.scala:85:32, :104:67] wire f1_predicted_ghist_cfi_in_bank_0 = _f1_predicted_ghist_cfi_in_bank_0_T & _f1_predicted_ghist_cfi_in_bank_0_T_1; // @[frontend.scala:104:{37,50,67}] wire _f1_predicted_ghist_ignore_second_bank_T_1 = &_f1_predicted_ghist_ignore_second_bank_T; // @[frontend.scala:152:{28,66}] wire _f1_predicted_ghist_ignore_second_bank_T_2 = _f1_predicted_ghist_ignore_second_bank_T_1; // @[frontend.scala:152:{21,66}] wire f1_predicted_ghist_ignore_second_bank = f1_predicted_ghist_cfi_in_bank_0 | _f1_predicted_ghist_ignore_second_bank_T_2; // @[frontend.scala:104:50, :105:46, :152:21] wire [3:0] _f1_predicted_ghist_first_bank_saw_not_taken_T = f1_predicted_ghist_not_taken_branches[3:0]; // @[frontend.scala:89:39, :107:56] wire _f1_predicted_ghist_first_bank_saw_not_taken_T_1 = |_f1_predicted_ghist_first_bank_saw_not_taken_T; // @[frontend.scala:107:{56,72}] wire f1_predicted_ghist_first_bank_saw_not_taken = _f1_predicted_ghist_first_bank_saw_not_taken_T_1 | s1_ghist_current_saw_branch_not_taken; // @[frontend.scala:107:{72,80}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_1 = {_f1_predicted_ghist_new_history_old_history_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_3 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_2 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_4 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_1 : _f1_predicted_ghist_new_history_old_history_T_3; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire _GEN_4 = _GEN_0[f1_redirect_idx] & f1_predicted_ghist_cfi_in_bank_0; // @[Mux.scala:50:70] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T; // @[frontend.scala:112:59] assign _f1_predicted_ghist_new_history_new_saw_branch_taken_T = _GEN_4; // @[frontend.scala:112:59] wire _f1_predicted_ghist_new_history_old_history_T_5; // @[frontend.scala:114:50] assign _f1_predicted_ghist_new_history_old_history_T_5 = _GEN_4; // @[frontend.scala:112:59, :114:50] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_7 = {_f1_predicted_ghist_new_history_old_history_T_6[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_9 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_8 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_10 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_7 : _f1_predicted_ghist_new_history_old_history_T_9; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_11 = {_f1_predicted_ghist_new_history_old_history_T_10, 1'h0}; // @[frontend.scala:67:12, :114:110] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_12 = {_f1_predicted_ghist_new_history_old_history_T_11[65:1], 1'h1}; // @[frontend.scala:114:{110,115}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_14 = {_f1_predicted_ghist_new_history_old_history_T_13[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_16 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_15 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_17 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_14 : _f1_predicted_ghist_new_history_old_history_T_16; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_18 = {_f1_predicted_ghist_new_history_old_history_T_17, 1'h0}; // @[frontend.scala:67:12, :115:110] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_20 = {_f1_predicted_ghist_new_history_old_history_T_19[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_22 = s1_ghist_new_saw_branch_not_taken ? _f1_predicted_ghist_new_history_old_history_T_21 : _GEN_2; // @[frontend.scala:68:{12,75}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_23 = s1_ghist_new_saw_branch_taken ? _f1_predicted_ghist_new_history_old_history_T_20 : _f1_predicted_ghist_new_history_old_history_T_22; // @[frontend.scala:67:{12,80}, :68:12, :381:29] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_24 = f1_predicted_ghist_first_bank_saw_not_taken ? _f1_predicted_ghist_new_history_old_history_T_18 : {1'h0, _f1_predicted_ghist_new_history_old_history_T_23}; // @[frontend.scala:67:12, :107:80, :115:{39,110}] wire [65:0] _f1_predicted_ghist_new_history_old_history_T_25 = _f1_predicted_ghist_new_history_old_history_T_5 ? _f1_predicted_ghist_new_history_old_history_T_12 : _f1_predicted_ghist_new_history_old_history_T_24; // @[frontend.scala:114:{39,50,115}, :115:39] assign f1_predicted_ghist_old_history = f1_predicted_ghist_ignore_second_bank ? _f1_predicted_ghist_new_history_old_history_T_4[63:0] : _f1_predicted_ghist_new_history_old_history_T_25[63:0]; // @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}] wire [3:0] _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T = f1_predicted_ghist_not_taken_branches[7:4]; // @[frontend.scala:89:39, :118:67] wire _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = |_f1_predicted_ghist_new_history_new_saw_branch_not_taken_T; // @[frontend.scala:118:{67,92}] assign f1_predicted_ghist_new_saw_branch_not_taken = f1_predicted_ghist_ignore_second_bank ? f1_predicted_ghist_first_bank_saw_not_taken : _f1_predicted_ghist_new_history_new_saw_branch_not_taken_T_1; // @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_2 = _f1_predicted_ghist_new_history_new_saw_branch_taken_T_1 & _GEN_0[f1_redirect_idx]; // @[Mux.scala:50:70] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3 = ~f1_predicted_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :119:88] wire _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4 = _f1_predicted_ghist_new_history_new_saw_branch_taken_T_2 & _f1_predicted_ghist_new_history_new_saw_branch_taken_T_3; // @[frontend.scala:119:{72,85,88}] assign f1_predicted_ghist_new_saw_branch_taken = f1_predicted_ghist_ignore_second_bank ? _f1_predicted_ghist_new_history_new_saw_branch_taken_T : _f1_predicted_ghist_new_history_new_saw_branch_taken_T_4; // @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}] wire [5:0] _GEN_5 = {1'h0, s1_ghist_ras_idx}; // @[util.scala:203:14] wire [5:0] _f1_predicted_ghist_new_history_ras_idx_T_1 = _GEN_5 + 6'h1; // @[util.scala:203:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_2 = _f1_predicted_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_3 = _f1_predicted_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _f1_predicted_ghist_new_history_ras_idx_T_5 = _GEN_5 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_6 = _f1_predicted_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_7 = _f1_predicted_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] assign _f1_predicted_ghist_new_history_ras_idx_T_9 = _f1_predicted_ghist_new_history_ras_idx_T_8; // @[frontend.scala:123:31, :124:31] assign f1_predicted_ghist_ras_idx = _f1_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire _T_5 = s1_valid & ~s1_tlb_miss; // @[frontend.scala:380:29, :396:35, :427:{18,21}] wire _s0_valid_T = s1_tlb_resp_ae_inst | s1_tlb_resp_pf_inst; // @[frontend.scala:397:24, :429:43] wire _s0_valid_T_1 = ~_s0_valid_T; // @[frontend.scala:429:{21,43}] wire _s2_valid_T = ~f1_clear; // @[frontend.scala:384:30, :386:58, :440:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[frontend.scala:380:29, :440:{35,38}] reg s2_valid; // @[frontend.scala:440:25] reg [39:0] s2_vpc; // @[frontend.scala:441:25] reg [63:0] s2_ghist_old_history; // @[frontend.scala:442:21] reg s2_ghist_current_saw_branch_not_taken; // @[frontend.scala:442:21] reg s2_ghist_new_saw_branch_not_taken; // @[frontend.scala:442:21] reg s2_ghist_new_saw_branch_taken; // @[frontend.scala:442:21] reg [4:0] s2_ghist_ras_idx; // @[frontend.scala:442:21] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_8 = s2_ghist_ras_idx; // @[frontend.scala:124:31, :442:21] reg [31:0] s2_ppc; // @[frontend.scala:444:24] assign s0_replay_ppc = s2_ppc; // @[frontend.scala:355:28, :444:24] reg [1:0] s2_tsrc; // @[frontend.scala:445:24] wire [1:0] s2_fsrc; // @[frontend.scala:446:25] wire f2_clear; // @[frontend.scala:447:26] reg s2_tlb_resp_miss; // @[frontend.scala:448:28] assign s0_replay_resp_miss = s2_tlb_resp_miss; // @[frontend.scala:353:28, :448:28] reg [31:0] s2_tlb_resp_paddr; // @[frontend.scala:448:28] assign s0_replay_resp_paddr = s2_tlb_resp_paddr; // @[frontend.scala:353:28, :448:28] reg [39:0] s2_tlb_resp_gpa; // @[frontend.scala:448:28] assign s0_replay_resp_gpa = s2_tlb_resp_gpa; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gpa_is_pte; // @[frontend.scala:448:28] assign s0_replay_resp_gpa_is_pte = s2_tlb_resp_gpa_is_pte; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_ld; // @[frontend.scala:448:28] assign s0_replay_resp_pf_ld = s2_tlb_resp_pf_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_st; // @[frontend.scala:448:28] assign s0_replay_resp_pf_st = s2_tlb_resp_pf_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_inst; // @[frontend.scala:448:28] assign s0_replay_resp_pf_inst = s2_tlb_resp_pf_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_ld; // @[frontend.scala:448:28] assign s0_replay_resp_gf_ld = s2_tlb_resp_gf_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_st; // @[frontend.scala:448:28] assign s0_replay_resp_gf_st = s2_tlb_resp_gf_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_inst; // @[frontend.scala:448:28] assign s0_replay_resp_gf_inst = s2_tlb_resp_gf_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_ld; // @[frontend.scala:448:28] assign s0_replay_resp_ae_ld = s2_tlb_resp_ae_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_st; // @[frontend.scala:448:28] assign s0_replay_resp_ae_st = s2_tlb_resp_ae_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_inst; // @[frontend.scala:448:28] assign s0_replay_resp_ae_inst = s2_tlb_resp_ae_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_ld; // @[frontend.scala:448:28] assign s0_replay_resp_ma_ld = s2_tlb_resp_ma_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_st; // @[frontend.scala:448:28] assign s0_replay_resp_ma_st = s2_tlb_resp_ma_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_inst; // @[frontend.scala:448:28] assign s0_replay_resp_ma_inst = s2_tlb_resp_ma_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_cacheable; // @[frontend.scala:448:28] assign s0_replay_resp_cacheable = s2_tlb_resp_cacheable; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_must_alloc; // @[frontend.scala:448:28] assign s0_replay_resp_must_alloc = s2_tlb_resp_must_alloc; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_prefetchable; // @[frontend.scala:448:28] assign s0_replay_resp_prefetchable = s2_tlb_resp_prefetchable; // @[frontend.scala:353:28, :448:28] reg [2:0] s2_tlb_resp_size; // @[frontend.scala:448:28] assign s0_replay_resp_size = s2_tlb_resp_size; // @[frontend.scala:353:28, :448:28] reg [4:0] s2_tlb_resp_cmd; // @[frontend.scala:448:28] assign s0_replay_resp_cmd = s2_tlb_resp_cmd; // @[frontend.scala:353:28, :448:28] reg s2_tlb_miss; // @[frontend.scala:449:28] reg s2_is_replay_REG; // @[frontend.scala:450:29] wire s2_is_replay = s2_is_replay_REG & s2_valid; // @[frontend.scala:440:25, :450:{29,44}] wire _GEN_6 = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[frontend.scala:448:28, :451:50] wire _s2_xcpt_T; // @[frontend.scala:451:50] assign _s2_xcpt_T = _GEN_6; // @[frontend.scala:451:50] wire _s0_valid_T_7; // @[frontend.scala:499:46] assign _s0_valid_T_7 = _GEN_6; // @[frontend.scala:451:50, :499:46] wire _f3_io_enq_valid_T_2; // @[frontend.scala:529:52] assign _f3_io_enq_valid_T_2 = _GEN_6; // @[frontend.scala:451:50, :529:52] wire _s2_xcpt_T_1 = s2_valid & _s2_xcpt_T; // @[frontend.scala:440:25, :451:{26,50}] wire _s2_xcpt_T_2 = ~s2_is_replay; // @[frontend.scala:450:44, :451:77] wire s2_xcpt = _s2_xcpt_T_1 & _s2_xcpt_T_2; // @[frontend.scala:451:{26,74,77}] wire f3_ready; // @[frontend.scala:452:22] wire [2:0] f2_mask_idx = s2_vpc[3:1]; // @[package.scala:163:13] wire [2:0] f3_io_enq_bits_mask_idx = s2_vpc[3:1]; // @[package.scala:163:13] wire [1:0] f2_mask_shamt = f2_mask_idx[1:0]; // @[package.scala:163:13] wire [2:0] _f2_mask_end_mask_T = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire [2:0] _f2_predicted_target_T_17 = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire [2:0] _f2_predicted_ghist_ignore_second_bank_T = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire [2:0] _f3_io_enq_bits_mask_end_mask_T = s2_vpc[5:3]; // @[frontend.scala:152:28, :441:25] wire _f2_mask_end_mask_T_1 = &_f2_mask_end_mask_T; // @[frontend.scala:152:{28,66}] wire _f2_mask_end_mask_T_2 = _f2_mask_end_mask_T_1; // @[frontend.scala:152:{21,66}] wire [7:0] f2_mask_end_mask = _f2_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:152:21, :180:25] wire [10:0] _f2_mask_T = 11'hFF << f2_mask_shamt; // @[package.scala:163:13] wire [10:0] f2_mask = {3'h0, _f2_mask_T[7:0] & f2_mask_end_mask}; // @[frontend.scala:180:25, :181:{31,40}] wire _f2_redirects_T = f2_mask[0]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_1 = s2_valid & _f2_redirects_T; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_2 = _f2_redirects_T_1 & _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_3 = _bpd_io_resp_f2_preds_0_is_br & _bpd_io_resp_f2_preds_0_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_4 = _bpd_io_resp_f2_preds_0_is_jal | _f2_redirects_T_3; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_0 = _f2_redirects_T_2 & _f2_redirects_T_4; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_5 = f2_mask[1]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_6 = s2_valid & _f2_redirects_T_5; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_7 = _f2_redirects_T_6 & _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_8 = _bpd_io_resp_f2_preds_1_is_br & _bpd_io_resp_f2_preds_1_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_9 = _bpd_io_resp_f2_preds_1_is_jal | _f2_redirects_T_8; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_1 = _f2_redirects_T_7 & _f2_redirects_T_9; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_10 = f2_mask[2]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_11 = s2_valid & _f2_redirects_T_10; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_12 = _f2_redirects_T_11 & _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_13 = _bpd_io_resp_f2_preds_2_is_br & _bpd_io_resp_f2_preds_2_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_14 = _bpd_io_resp_f2_preds_2_is_jal | _f2_redirects_T_13; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_2 = _f2_redirects_T_12 & _f2_redirects_T_14; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_15 = f2_mask[3]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_16 = s2_valid & _f2_redirects_T_15; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_17 = _f2_redirects_T_16 & _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_18 = _bpd_io_resp_f2_preds_3_is_br & _bpd_io_resp_f2_preds_3_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_19 = _bpd_io_resp_f2_preds_3_is_jal | _f2_redirects_T_18; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_3 = _f2_redirects_T_17 & _f2_redirects_T_19; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_20 = f2_mask[4]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_21 = s2_valid & _f2_redirects_T_20; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_22 = _f2_redirects_T_21 & _bpd_io_resp_f2_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_23 = _bpd_io_resp_f2_preds_4_is_br & _bpd_io_resp_f2_preds_4_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_24 = _bpd_io_resp_f2_preds_4_is_jal | _f2_redirects_T_23; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_4 = _f2_redirects_T_22 & _f2_redirects_T_24; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_25 = f2_mask[5]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_26 = s2_valid & _f2_redirects_T_25; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_27 = _f2_redirects_T_26 & _bpd_io_resp_f2_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_28 = _bpd_io_resp_f2_preds_5_is_br & _bpd_io_resp_f2_preds_5_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_29 = _bpd_io_resp_f2_preds_5_is_jal | _f2_redirects_T_28; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_5 = _f2_redirects_T_27 & _f2_redirects_T_29; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_30 = f2_mask[6]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_31 = s2_valid & _f2_redirects_T_30; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_32 = _f2_redirects_T_31 & _bpd_io_resp_f2_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_33 = _bpd_io_resp_f2_preds_6_is_br & _bpd_io_resp_f2_preds_6_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_34 = _bpd_io_resp_f2_preds_6_is_jal | _f2_redirects_T_33; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_6 = _f2_redirects_T_32 & _f2_redirects_T_34; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_35 = f2_mask[7]; // @[frontend.scala:181:40, :459:24] wire _f2_redirects_T_36 = s2_valid & _f2_redirects_T_35; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_37 = _f2_redirects_T_36 & _bpd_io_resp_f2_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_38 = _bpd_io_resp_f2_preds_7_is_br & _bpd_io_resp_f2_preds_7_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_39 = _bpd_io_resp_f2_preds_7_is_jal | _f2_redirects_T_38; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_7 = _f2_redirects_T_37 & _f2_redirects_T_39; // @[frontend.scala:459:{28,71}, :460:34] wire [2:0] _f2_redirect_idx_T = {2'h3, ~f2_redirects_6}; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_1 = f2_redirects_5 ? 3'h5 : _f2_redirect_idx_T; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_2 = f2_redirects_4 ? 3'h4 : _f2_redirect_idx_T_1; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_3 = f2_redirects_3 ? 3'h3 : _f2_redirect_idx_T_2; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_4 = f2_redirects_2 ? 3'h2 : _f2_redirect_idx_T_3; // @[Mux.scala:50:70] wire [2:0] _f2_redirect_idx_T_5 = f2_redirects_1 ? 3'h1 : _f2_redirect_idx_T_4; // @[Mux.scala:50:70] wire [2:0] f2_redirect_idx = f2_redirects_0 ? 3'h0 : _f2_redirect_idx_T_5; // @[Mux.scala:50:70] wire [2:0] f2_predicted_ghist_cfi_idx_fixed = f2_redirect_idx; // @[Mux.scala:50:70] wire _f2_do_redirect_T = f2_redirects_0 | f2_redirects_1; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_1 = _f2_do_redirect_T | f2_redirects_2; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_2 = _f2_do_redirect_T_1 | f2_redirects_3; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_3 = _f2_do_redirect_T_2 | f2_redirects_4; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_4 = _f2_do_redirect_T_3 | f2_redirects_5; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_5 = _f2_do_redirect_T_4 | f2_redirects_6; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_6 = _f2_do_redirect_T_5 | f2_redirects_7; // @[frontend.scala:459:71, :465:45] wire f2_do_redirect = _f2_do_redirect_T_6; // @[frontend.scala:465:{45,50}] wire _f2_predicted_target_T = f2_redirect_idx == 3'h1; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_1 = _f2_predicted_target_T ? _bpd_io_resp_f2_preds_1_predicted_pc_bits : _bpd_io_resp_f2_preds_0_predicted_pc_bits; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_2 = f2_redirect_idx == 3'h2; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_3 = _f2_predicted_target_T_2 ? _bpd_io_resp_f2_preds_2_predicted_pc_bits : _f2_predicted_target_T_1; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_4 = f2_redirect_idx == 3'h3; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_5 = _f2_predicted_target_T_4 ? _bpd_io_resp_f2_preds_3_predicted_pc_bits : _f2_predicted_target_T_3; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_6 = f2_redirect_idx == 3'h4; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_7 = _f2_predicted_target_T_6 ? _bpd_io_resp_f2_preds_4_predicted_pc_bits : _f2_predicted_target_T_5; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_8 = f2_redirect_idx == 3'h5; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_9 = _f2_predicted_target_T_8 ? _bpd_io_resp_f2_preds_5_predicted_pc_bits : _f2_predicted_target_T_7; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_10 = f2_redirect_idx == 3'h6; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_11 = _f2_predicted_target_T_10 ? _bpd_io_resp_f2_preds_6_predicted_pc_bits : _f2_predicted_target_T_9; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_12 = &f2_redirect_idx; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_13 = _f2_predicted_target_T_12 ? _bpd_io_resp_f2_preds_7_predicted_pc_bits : _f2_predicted_target_T_11; // @[package.scala:39:{76,86}] wire [39:0] _f2_predicted_target_T_14 = ~s2_vpc; // @[frontend.scala:160:33, :441:25] wire [39:0] _f2_predicted_target_T_15 = {_f2_predicted_target_T_14[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _f2_predicted_target_T_16 = ~_f2_predicted_target_T_15; // @[frontend.scala:160:{31,39}] wire _f2_predicted_target_T_18 = &_f2_predicted_target_T_17; // @[frontend.scala:152:{28,66}] wire _f2_predicted_target_T_19 = _f2_predicted_target_T_18; // @[frontend.scala:152:{21,66}] wire [4:0] _f2_predicted_target_T_20 = _f2_predicted_target_T_19 ? 5'h8 : 5'h10; // @[frontend.scala:152:21, :170:28] wire [40:0] _f2_predicted_target_T_21 = {1'h0, _f2_predicted_target_T_16} + {36'h0, _f2_predicted_target_T_20}; // @[frontend.scala:160:31, :170:{23,28}] wire [39:0] _f2_predicted_target_T_22 = _f2_predicted_target_T_21[39:0]; // @[frontend.scala:170:23] wire [39:0] f2_predicted_target = f2_do_redirect ? _f2_predicted_target_T_13 : _f2_predicted_target_T_22; // @[package.scala:39:76] wire _f2_predicted_ghist_T = _bpd_io_resp_f2_preds_0_is_br & _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_1 = _bpd_io_resp_f2_preds_1_is_br & _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_2 = _bpd_io_resp_f2_preds_2_is_br & _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_3 = _bpd_io_resp_f2_preds_3_is_br & _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_4 = _bpd_io_resp_f2_preds_4_is_br & _bpd_io_resp_f2_preds_4_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_5 = _bpd_io_resp_f2_preds_5_is_br & _bpd_io_resp_f2_preds_5_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_6 = _bpd_io_resp_f2_preds_6_is_br & _bpd_io_resp_f2_preds_6_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_7 = _bpd_io_resp_f2_preds_7_is_br & _bpd_io_resp_f2_preds_7_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire [1:0] f2_predicted_ghist_lo_lo = {_f2_predicted_ghist_T_1, _f2_predicted_ghist_T}; // @[package.scala:45:27] wire [1:0] f2_predicted_ghist_lo_hi = {_f2_predicted_ghist_T_3, _f2_predicted_ghist_T_2}; // @[package.scala:45:27] wire [3:0] f2_predicted_ghist_lo = {f2_predicted_ghist_lo_hi, f2_predicted_ghist_lo_lo}; // @[package.scala:45:27] wire [1:0] f2_predicted_ghist_hi_lo = {_f2_predicted_ghist_T_5, _f2_predicted_ghist_T_4}; // @[package.scala:45:27] wire [1:0] f2_predicted_ghist_hi_hi = {_f2_predicted_ghist_T_7, _f2_predicted_ghist_T_6}; // @[package.scala:45:27] wire [3:0] f2_predicted_ghist_hi = {f2_predicted_ghist_hi_hi, f2_predicted_ghist_hi_lo}; // @[package.scala:45:27] wire [7:0] _f2_predicted_ghist_T_8 = {f2_predicted_ghist_hi, f2_predicted_ghist_lo}; // @[package.scala:45:27] wire [10:0] _f2_predicted_ghist_T_9 = {3'h0, f2_mask[7:0] & _f2_predicted_ghist_T_8}; // @[package.scala:45:27] wire [7:0] _GEN_7 = {{_bpd_io_resp_f2_preds_7_taken}, {_bpd_io_resp_f2_preds_6_taken}, {_bpd_io_resp_f2_preds_5_taken}, {_bpd_io_resp_f2_preds_4_taken}, {_bpd_io_resp_f2_preds_3_taken}, {_bpd_io_resp_f2_preds_2_taken}, {_bpd_io_resp_f2_preds_1_taken}, {_bpd_io_resp_f2_preds_0_taken}}; // @[frontend.scala:331:19, :471:46] wire [7:0] _GEN_8 = {{_bpd_io_resp_f2_preds_7_is_br}, {_bpd_io_resp_f2_preds_6_is_br}, {_bpd_io_resp_f2_preds_5_is_br}, {_bpd_io_resp_f2_preds_4_is_br}, {_bpd_io_resp_f2_preds_3_is_br}, {_bpd_io_resp_f2_preds_2_is_br}, {_bpd_io_resp_f2_preds_1_is_br}, {_bpd_io_resp_f2_preds_0_is_br}}; // @[frontend.scala:331:19, :471:46] wire _f2_predicted_ghist_T_10 = _GEN_7[f2_redirect_idx] & f2_do_redirect; // @[Mux.scala:50:70] wire [7:0] f2_predicted_ghist_cfi_idx_oh = 8'h1 << f2_predicted_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T = f2_predicted_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] f2_predicted_ghist_old_history; // @[frontend.scala:87:27] wire f2_predicted_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire f2_predicted_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] f2_predicted_ghist_ras_idx; // @[frontend.scala:87:27] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_1 = {1'h0, f2_predicted_ghist_cfi_idx_oh[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_2 = {2'h0, f2_predicted_ghist_cfi_idx_oh[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_3 = {3'h0, f2_predicted_ghist_cfi_idx_oh[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_4 = {4'h0, f2_predicted_ghist_cfi_idx_oh[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_5 = {5'h0, f2_predicted_ghist_cfi_idx_oh[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_6 = {6'h0, f2_predicted_ghist_cfi_idx_oh[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_7 = {7'h0, f2_predicted_ghist_cfi_idx_oh[7]}; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_8 = _f2_predicted_ghist_not_taken_branches_T | _f2_predicted_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_9 = _f2_predicted_ghist_not_taken_branches_T_8 | _f2_predicted_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_10 = _f2_predicted_ghist_not_taken_branches_T_9 | _f2_predicted_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_11 = _f2_predicted_ghist_not_taken_branches_T_10 | _f2_predicted_ghist_not_taken_branches_T_4; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_12 = _f2_predicted_ghist_not_taken_branches_T_11 | _f2_predicted_ghist_not_taken_branches_T_5; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_13 = _f2_predicted_ghist_not_taken_branches_T_12 | _f2_predicted_ghist_not_taken_branches_T_6; // @[util.scala:373:{29,45}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_14 = _f2_predicted_ghist_not_taken_branches_T_13 | _f2_predicted_ghist_not_taken_branches_T_7; // @[util.scala:373:{29,45}] wire _f2_predicted_ghist_not_taken_branches_T_15 = _GEN_8[f2_redirect_idx] & _f2_predicted_ghist_T_10; // @[Mux.scala:50:70] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_16 = _f2_predicted_ghist_not_taken_branches_T_15 ? f2_predicted_ghist_cfi_idx_oh : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_17 = ~_f2_predicted_ghist_not_taken_branches_T_16; // @[frontend.scala:90:{69,73}] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_18 = _f2_predicted_ghist_not_taken_branches_T_14 & _f2_predicted_ghist_not_taken_branches_T_17; // @[util.scala:373:45] wire [7:0] _f2_predicted_ghist_not_taken_branches_T_20 = f2_do_redirect ? _f2_predicted_ghist_not_taken_branches_T_18 : 8'hFF; // @[frontend.scala:89:44, :90:67, :465:50] wire [10:0] f2_predicted_ghist_not_taken_branches = {3'h0, _f2_predicted_ghist_T_9[7:0] & _f2_predicted_ghist_not_taken_branches_T_20}; // @[frontend.scala:89:{39,44}, :470:72] wire [64:0] _GEN_9 = {s2_ghist_old_history, 1'h0}; // @[frontend.scala:67:75, :442:21] wire [64:0] _f2_predicted_ghist_base_T; // @[frontend.scala:67:75] assign _f2_predicted_ghist_base_T = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_base_T_2; // @[frontend.scala:68:75] assign _f2_predicted_ghist_base_T_2 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_2; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_2 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_6; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T_6 = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_8; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_8 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_13; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T_13 = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_15; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_15 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_19; // @[frontend.scala:67:75] assign _f2_predicted_ghist_new_history_old_history_T_19 = _GEN_9; // @[frontend.scala:67:75] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_21; // @[frontend.scala:68:75] assign _f2_predicted_ghist_new_history_old_history_T_21 = _GEN_9; // @[frontend.scala:67:75, :68:75] wire [64:0] _f2_predicted_ghist_base_T_1 = {_f2_predicted_ghist_base_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _GEN_10 = {1'h0, s2_ghist_old_history}; // @[frontend.scala:68:12, :442:21] wire [64:0] _f2_predicted_ghist_base_T_3 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_base_T_2 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] f2_predicted_ghist_base = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_base_T_1 : _f2_predicted_ghist_base_T_3; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire _GEN_11 = f2_do_redirect & _f2_predicted_ghist_T_10; // @[frontend.scala:104:37, :465:50, :471:46] wire _f2_predicted_ghist_cfi_in_bank_0_T; // @[frontend.scala:104:37] assign _f2_predicted_ghist_cfi_in_bank_0_T = _GEN_11; // @[frontend.scala:104:37] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1; // @[frontend.scala:119:59] assign _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1 = _GEN_11; // @[frontend.scala:104:37, :119:59] wire _f2_predicted_ghist_cfi_in_bank_0_T_1 = ~(f2_predicted_ghist_cfi_idx_fixed[2]); // @[frontend.scala:85:32, :104:67] wire f2_predicted_ghist_cfi_in_bank_0 = _f2_predicted_ghist_cfi_in_bank_0_T & _f2_predicted_ghist_cfi_in_bank_0_T_1; // @[frontend.scala:104:{37,50,67}] wire _f2_predicted_ghist_ignore_second_bank_T_1 = &_f2_predicted_ghist_ignore_second_bank_T; // @[frontend.scala:152:{28,66}] wire _f2_predicted_ghist_ignore_second_bank_T_2 = _f2_predicted_ghist_ignore_second_bank_T_1; // @[frontend.scala:152:{21,66}] wire f2_predicted_ghist_ignore_second_bank = f2_predicted_ghist_cfi_in_bank_0 | _f2_predicted_ghist_ignore_second_bank_T_2; // @[frontend.scala:104:50, :105:46, :152:21] wire [3:0] _f2_predicted_ghist_first_bank_saw_not_taken_T = f2_predicted_ghist_not_taken_branches[3:0]; // @[frontend.scala:89:39, :107:56] wire _f2_predicted_ghist_first_bank_saw_not_taken_T_1 = |_f2_predicted_ghist_first_bank_saw_not_taken_T; // @[frontend.scala:107:{56,72}] wire f2_predicted_ghist_first_bank_saw_not_taken = _f2_predicted_ghist_first_bank_saw_not_taken_T_1 | s2_ghist_current_saw_branch_not_taken; // @[frontend.scala:107:{72,80}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_1 = {_f2_predicted_ghist_new_history_old_history_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_3 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_2 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_4 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_1 : _f2_predicted_ghist_new_history_old_history_T_3; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire _GEN_12 = _GEN_8[f2_redirect_idx] & f2_predicted_ghist_cfi_in_bank_0; // @[Mux.scala:50:70] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T; // @[frontend.scala:112:59] assign _f2_predicted_ghist_new_history_new_saw_branch_taken_T = _GEN_12; // @[frontend.scala:112:59] wire _f2_predicted_ghist_new_history_old_history_T_5; // @[frontend.scala:114:50] assign _f2_predicted_ghist_new_history_old_history_T_5 = _GEN_12; // @[frontend.scala:112:59, :114:50] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_7 = {_f2_predicted_ghist_new_history_old_history_T_6[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_9 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_8 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_10 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_7 : _f2_predicted_ghist_new_history_old_history_T_9; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_11 = {_f2_predicted_ghist_new_history_old_history_T_10, 1'h0}; // @[frontend.scala:67:12, :114:110] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_12 = {_f2_predicted_ghist_new_history_old_history_T_11[65:1], 1'h1}; // @[frontend.scala:114:{110,115}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_14 = {_f2_predicted_ghist_new_history_old_history_T_13[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_16 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_15 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_17 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_14 : _f2_predicted_ghist_new_history_old_history_T_16; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_18 = {_f2_predicted_ghist_new_history_old_history_T_17, 1'h0}; // @[frontend.scala:67:12, :115:110] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_20 = {_f2_predicted_ghist_new_history_old_history_T_19[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_22 = s2_ghist_new_saw_branch_not_taken ? _f2_predicted_ghist_new_history_old_history_T_21 : _GEN_10; // @[frontend.scala:68:{12,75}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_23 = s2_ghist_new_saw_branch_taken ? _f2_predicted_ghist_new_history_old_history_T_20 : _f2_predicted_ghist_new_history_old_history_T_22; // @[frontend.scala:67:{12,80}, :68:12, :442:21] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_24 = f2_predicted_ghist_first_bank_saw_not_taken ? _f2_predicted_ghist_new_history_old_history_T_18 : {1'h0, _f2_predicted_ghist_new_history_old_history_T_23}; // @[frontend.scala:67:12, :107:80, :115:{39,110}] wire [65:0] _f2_predicted_ghist_new_history_old_history_T_25 = _f2_predicted_ghist_new_history_old_history_T_5 ? _f2_predicted_ghist_new_history_old_history_T_12 : _f2_predicted_ghist_new_history_old_history_T_24; // @[frontend.scala:114:{39,50,115}, :115:39] assign f2_predicted_ghist_old_history = f2_predicted_ghist_ignore_second_bank ? _f2_predicted_ghist_new_history_old_history_T_4[63:0] : _f2_predicted_ghist_new_history_old_history_T_25[63:0]; // @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}] wire [3:0] _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T = f2_predicted_ghist_not_taken_branches[7:4]; // @[frontend.scala:89:39, :118:67] wire _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1 = |_f2_predicted_ghist_new_history_new_saw_branch_not_taken_T; // @[frontend.scala:118:{67,92}] assign f2_predicted_ghist_new_saw_branch_not_taken = f2_predicted_ghist_ignore_second_bank ? f2_predicted_ghist_first_bank_saw_not_taken : _f2_predicted_ghist_new_history_new_saw_branch_not_taken_T_1; // @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_2 = _f2_predicted_ghist_new_history_new_saw_branch_taken_T_1 & _GEN_8[f2_redirect_idx]; // @[Mux.scala:50:70] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3 = ~f2_predicted_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :119:88] wire _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4 = _f2_predicted_ghist_new_history_new_saw_branch_taken_T_2 & _f2_predicted_ghist_new_history_new_saw_branch_taken_T_3; // @[frontend.scala:119:{72,85,88}] assign f2_predicted_ghist_new_saw_branch_taken = f2_predicted_ghist_ignore_second_bank ? _f2_predicted_ghist_new_history_new_saw_branch_taken_T : _f2_predicted_ghist_new_history_new_saw_branch_taken_T_4; // @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}] wire [5:0] _GEN_13 = {1'h0, s2_ghist_ras_idx}; // @[util.scala:203:14] wire [5:0] _f2_predicted_ghist_new_history_ras_idx_T_1 = _GEN_13 + 6'h1; // @[util.scala:203:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_2 = _f2_predicted_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_3 = _f2_predicted_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _f2_predicted_ghist_new_history_ras_idx_T_5 = _GEN_13 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_6 = _f2_predicted_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_7 = _f2_predicted_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] assign _f2_predicted_ghist_new_history_ras_idx_T_9 = _f2_predicted_ghist_new_history_ras_idx_T_8; // @[frontend.scala:123:31, :124:31] assign f2_predicted_ghist_ras_idx = _f2_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire _f2_correct_f1_ghist_T = s1_ghist_old_history == f2_predicted_ghist_old_history; // @[frontend.scala:75:19, :87:27, :381:29] wire _f2_correct_f1_ghist_T_1 = s1_ghist_new_saw_branch_not_taken == f2_predicted_ghist_new_saw_branch_not_taken; // @[frontend.scala:76:32, :87:27, :381:29] wire _f2_correct_f1_ghist_T_2 = _f2_correct_f1_ghist_T & _f2_correct_f1_ghist_T_1; // @[frontend.scala:75:{19,42}, :76:32] wire _f2_correct_f1_ghist_T_3 = s1_ghist_new_saw_branch_taken == f2_predicted_ghist_new_saw_branch_taken; // @[frontend.scala:77:28, :87:27, :381:29] wire _f2_correct_f1_ghist_T_4 = _f2_correct_f1_ghist_T_2 & _f2_correct_f1_ghist_T_3; // @[frontend.scala:75:42, :76:68, :77:28] wire _f2_correct_f1_ghist_T_5 = ~_f2_correct_f1_ghist_T_4; // @[frontend.scala:76:68, :80:41] wire f2_correct_f1_ghist = _f2_correct_f1_ghist_T_5; // @[frontend.scala:80:41, :479:61] wire _s0_is_replay_T = s2_valid & _icache_io_resp_valid; // @[frontend.scala:299:26, :440:25, :482:19, :485:30] wire _T_11 = s2_valid & ~_icache_io_resp_valid | _s0_is_replay_T & ~f3_ready; // @[frontend.scala:299:26, :440:25, :452:22, :481:{19,22,45}, :482:{43,46}, :485:30] wire _s0_valid_T_2 = ~s2_tlb_resp_ae_inst; // @[frontend.scala:448:28, :483:18] wire _s0_valid_T_3 = ~s2_tlb_resp_pf_inst; // @[frontend.scala:448:28, :483:42] wire _s0_valid_T_4 = _s0_valid_T_2 & _s0_valid_T_3; // @[frontend.scala:483:{18,39,42}] wire _s0_valid_T_5 = _s0_valid_T_4 | s2_is_replay; // @[frontend.scala:450:44, :483:{39,64}] wire _s0_valid_T_6 = _s0_valid_T_5 | s2_tlb_miss; // @[frontend.scala:449:28, :483:{64,80}] wire _s0_s1_use_f3_bpd_resp_T = ~s2_is_replay; // @[frontend.scala:450:44, :451:77, :487:30] assign s0_s1_use_f3_bpd_resp = _T_11 & _s0_s1_use_f3_bpd_resp_T; // @[frontend.scala:356:39, :481:45, :482:58, :487:{27,30}] wire _T_12 = s2_valid & f3_ready; // @[frontend.scala:440:25, :452:22, :491:25] wire _T_21 = s1_valid & (s1_vpc != f2_predicted_target | f2_correct_f1_ghist) | ~s1_valid; // @[frontend.scala:379:29, :380:29, :466:32, :479:61, :496:{21,32,56,81,84}] wire _GEN_14 = _T_12 & _T_21; // @[frontend.scala:384:30, :491:{25,38}, :496:{81,95}] wire _s0_valid_T_8 = ~s2_is_replay; // @[frontend.scala:450:44, :451:77, :499:73] wire _s0_valid_T_9 = _s0_valid_T_7 & _s0_valid_T_8; // @[frontend.scala:499:{46,70,73}] wire _s0_valid_T_10 = ~_s0_valid_T_9; // @[frontend.scala:499:{23,70}] wire _GEN_15 = _T_12 & _T_21; // @[frontend.scala:427:35, :491:{25,38}, :496:{81,95}, :499:20] assign s2_fsrc = _T_11 ? 2'h0 : {1'h0, _GEN_15}; // @[frontend.scala:427:35, :446:25, :481:45, :482:58, :491:38, :496:95, :499:20, :503:20] wire f3_clear; // @[frontend.scala:514:26] wire f4_ready; // @[frontend.scala:526:22] wire _f3_io_enq_valid_T = ~f2_clear; // @[frontend.scala:447:26, :528:37] wire _f3_io_enq_valid_T_1 = s2_valid & _f3_io_enq_valid_T; // @[frontend.scala:440:25, :528:{34,37}] wire _f3_io_enq_valid_T_3 = ~s2_tlb_miss; // @[frontend.scala:449:28, :529:79] wire _f3_io_enq_valid_T_4 = _f3_io_enq_valid_T_2 & _f3_io_enq_valid_T_3; // @[frontend.scala:529:{52,76,79}] wire _f3_io_enq_valid_T_5 = _icache_io_resp_valid | _f3_io_enq_valid_T_4; // @[frontend.scala:299:26, :529:{27,76}] wire _f3_io_enq_valid_T_6 = _f3_io_enq_valid_T_1 & _f3_io_enq_valid_T_5; // @[frontend.scala:528:{34,47}, :529:27] wire [127:0] _f3_io_enq_bits_data_T = s2_xcpt ? 128'h0 : _icache_io_resp_bits_data; // @[frontend.scala:299:26, :451:74, :532:30] wire [1:0] f3_io_enq_bits_mask_shamt = f3_io_enq_bits_mask_idx[1:0]; // @[package.scala:163:13] wire _f3_io_enq_bits_mask_end_mask_T_1 = &_f3_io_enq_bits_mask_end_mask_T; // @[frontend.scala:152:{28,66}] wire _f3_io_enq_bits_mask_end_mask_T_2 = _f3_io_enq_bits_mask_end_mask_T_1; // @[frontend.scala:152:{21,66}] wire [7:0] f3_io_enq_bits_mask_end_mask = _f3_io_enq_bits_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:152:21, :180:25] wire [10:0] _f3_io_enq_bits_mask_T = 11'hFF << f3_io_enq_bits_mask_shamt; // @[package.scala:163:13] wire [10:0] _f3_io_enq_bits_mask_T_1 = {3'h0, _f3_io_enq_bits_mask_T[7:0] & f3_io_enq_bits_mask_end_mask}; // @[frontend.scala:180:25, :181:{31,40}] reg [4:0] ras_read_idx; // @[frontend.scala:540:29] wire _T_26 = _f3_io_enq_ready & _f3_io_enq_valid_T_6; // @[Decoupled.scala:51:35] reg f3_bpd_resp_io_enq_valid_REG; // @[frontend.scala:549:57] wire _f3_bpd_resp_io_enq_valid_T = _f3_io_deq_valid & f3_bpd_resp_io_enq_valid_REG; // @[frontend.scala:516:11, :549:{47,57}] wire [2:0] f3_bank_mask_idx = _f3_io_deq_bits_pc[3:1]; // @[package.scala:163:13] wire [2:0] _f3_bank_mask_T = _f3_io_deq_bits_pc[5:3]; // @[frontend.scala:152:28, :516:11] wire _f3_bank_mask_T_1 = &_f3_bank_mask_T; // @[frontend.scala:152:{28,66}] wire _f3_bank_mask_T_2 = _f3_bank_mask_T_1; // @[frontend.scala:152:{21,66}] wire [1:0] f3_bank_mask = {~_f3_bank_mask_T_2, 1'h1}; // @[frontend.scala:152:21, :190:10] wire [39:0] _f3_aligned_pc_T = ~_f3_io_deq_bits_pc; // @[frontend.scala:160:33, :516:11] wire [39:0] _f3_aligned_pc_T_1 = {_f3_aligned_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] f3_aligned_pc = ~_f3_aligned_pc_T_1; // @[frontend.scala:160:{31,39}] wire [2:0] _f3_is_last_bank_in_block_T = f3_aligned_pc[5:3]; // @[frontend.scala:152:28, :160:31] wire _f3_is_last_bank_in_block_T_1 = &_f3_is_last_bank_in_block_T; // @[frontend.scala:152:{28,66}] wire f3_is_last_bank_in_block = _f3_is_last_bank_in_block_T_1; // @[frontend.scala:152:{21,66}] wire _f3_is_rvc_0_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_1_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_2_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_3_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_4_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_5_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_6_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_7_T_1; // @[frontend.scala:592:38] wire f3_is_rvc_0; // @[frontend.scala:564:29] wire f3_is_rvc_1; // @[frontend.scala:564:29] wire f3_is_rvc_2; // @[frontend.scala:564:29] wire f3_is_rvc_3; // @[frontend.scala:564:29] wire f3_is_rvc_4; // @[frontend.scala:564:29] wire f3_is_rvc_5; // @[frontend.scala:564:29] wire f3_is_rvc_6; // @[frontend.scala:564:29] wire f3_is_rvc_7; // @[frontend.scala:564:29] wire _f3_redirects_0_T_7; // @[frontend.scala:731:40] wire _f3_redirects_1_T_7; // @[frontend.scala:731:40] wire _f3_redirects_2_T_7; // @[frontend.scala:731:40] wire _f3_redirects_3_T_7; // @[frontend.scala:731:40] wire _f3_redirects_4_T_7; // @[frontend.scala:731:40] wire _f3_redirects_5_T_7; // @[frontend.scala:731:40] wire _f3_redirects_6_T_7; // @[frontend.scala:731:40] wire _f3_redirects_7_T_7; // @[frontend.scala:731:40] wire f3_redirects_0; // @[frontend.scala:565:29] wire f3_redirects_1; // @[frontend.scala:565:29] wire f3_redirects_2; // @[frontend.scala:565:29] wire f3_redirects_3; // @[frontend.scala:565:29] wire f3_redirects_4; // @[frontend.scala:565:29] wire f3_redirects_5; // @[frontend.scala:565:29] wire f3_redirects_6; // @[frontend.scala:565:29] wire f3_redirects_7; // @[frontend.scala:565:29] wire [39:0] _f3_targs_0_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_1_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_2_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_3_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_4_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_5_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_6_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_7_T_1; // @[frontend.scala:691:26] wire [39:0] f3_targs_0; // @[frontend.scala:566:29] wire [39:0] f3_targs_1; // @[frontend.scala:566:29] wire [39:0] f3_targs_2; // @[frontend.scala:566:29] wire [39:0] f3_targs_3; // @[frontend.scala:566:29] wire [39:0] f3_targs_4; // @[frontend.scala:566:29] wire [39:0] f3_targs_5; // @[frontend.scala:566:29] wire [39:0] f3_targs_6; // @[frontend.scala:566:29] wire [39:0] f3_targs_7; // @[frontend.scala:566:29] wire [2:0] brsigs_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_1_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_2_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_3_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_4_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_5_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_6_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_7_cfi_type; // @[frontend.scala:613:24] wire [2:0] f3_cfi_types_0; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_1; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_2; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_3; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_4; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_5; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_6; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_7; // @[frontend.scala:567:29] wire [39:0] f3_predicted_target; // @[frontend.scala:784:32] wire [31:0] inst; // @[frontend.scala:660:24] wire [31:0] inst_1; // @[frontend.scala:660:24] wire [31:0] inst_2; // @[frontend.scala:660:24] wire [31:0] inst_3; // @[frontend.scala:660:24] wire [31:0] inst_4; // @[frontend.scala:660:24] wire [31:0] inst_5; // @[frontend.scala:660:24] wire [31:0] exp_inst; // @[consts.scala:332:8] wire [31:0] exp_inst_1; // @[consts.scala:332:8] wire [31:0] exp_inst_2; // @[consts.scala:332:8] wire [31:0] exp_inst_3; // @[consts.scala:332:8] wire [31:0] exp_inst_4; // @[consts.scala:332:8] wire [31:0] exp_inst_5; // @[consts.scala:332:8] wire _f3_fetch_bundle_sfbs_0_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_1_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_2_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_3_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_4_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_5_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_6_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_7_T_3; // @[frontend.scala:719:33] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_80; // @[frontend.scala:722:68] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_80; // @[frontend.scala:722:68] wire _f3_fetch_bundle_shadowable_mask_0_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_1_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_2_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_3_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_4_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_5_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_6_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_7_T_8; // @[frontend.scala:724:62] wire _f3_fetch_bundle_cfi_idx_valid_T_6; // @[frontend.scala:777:57] wire [2:0] _f3_fetch_bundle_cfi_idx_bits_T_6; // @[Mux.scala:50:70] wire _f3_predicted_ghist_cfi_in_bank_0_T = f3_fetch_bundle_cfi_idx_valid; // @[frontend.scala:104:37, :569:29] wire _f3_predicted_ghist_new_history_new_saw_branch_taken_T_1 = f3_fetch_bundle_cfi_idx_valid; // @[frontend.scala:119:59, :569:29] wire [2:0] f3_predicted_ghist_cfi_idx_fixed = f3_fetch_bundle_cfi_idx_bits; // @[frontend.scala:85:32, :569:29] wire _f3_predicted_target_T_7 = f3_fetch_bundle_cfi_is_ret; // @[frontend.scala:569:29, :785:36] wire [7:0] _f3_fetch_bundle_mask_T; // @[frontend.scala:576:35] wire [7:0] _f3_fetch_bundle_br_mask_T; // @[frontend.scala:577:41] wire f3_fetch_bundle_edge_inst_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_edge_inst_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_0; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_2; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_3; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_4; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_5; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_6; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_7; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_0; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_2; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_3; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_4; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_5; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_6; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_7; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_2; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_3; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_4; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_5; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_6; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_7; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_0; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_1; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_2; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_3; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_4; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_5; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_6; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_sfb_masks_7; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_0; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_1; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_2; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_3; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_4; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_5; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_6; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_sfb_dests_7; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_2; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_3; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_4; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_5; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_6; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_7; // @[frontend.scala:569:29] wire [63:0] f3_fetch_bundle_ghist_old_history; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_current_saw_branch_not_taken; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_new_saw_branch_not_taken; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_new_saw_branch_taken; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_ghist_ras_idx; // @[frontend.scala:569:29] wire f3_fetch_bundle_lhist_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_lhist_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_end_half_valid; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_end_half_bits; // @[frontend.scala:569:29] wire [119:0] f3_fetch_bundle_bpd_meta_0; // @[frontend.scala:569:29] wire [119:0] f3_fetch_bundle_bpd_meta_1; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_pc; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_next_pc; // @[frontend.scala:569:29] wire [2:0] f3_fetch_bundle_cfi_type; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_is_call; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_npc_plus4; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_ras_top; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_mask; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_br_mask; // @[frontend.scala:569:29] wire f3_fetch_bundle_xcpt_pf_if; // @[frontend.scala:569:29] wire f3_fetch_bundle_xcpt_ae_if; // @[frontend.scala:569:29] wire [1:0] f3_fetch_bundle_fsrc; // @[frontend.scala:569:29] wire [1:0] f3_fetch_bundle_tsrc; // @[frontend.scala:569:29] wire _f3_mask_0_T_4; // @[frontend.scala:690:71] wire _f3_mask_1_T_4; // @[frontend.scala:690:71] wire _f3_mask_2_T_4; // @[frontend.scala:690:71] wire _f3_mask_3_T_4; // @[frontend.scala:690:71] wire _f3_mask_4_T_4; // @[frontend.scala:690:71] wire _f3_mask_5_T_4; // @[frontend.scala:690:71] wire _f3_mask_6_T_4; // @[frontend.scala:690:71] wire _f3_mask_7_T_4; // @[frontend.scala:690:71] wire f3_mask_0; // @[frontend.scala:570:29] wire f3_mask_1; // @[frontend.scala:570:29] wire f3_mask_2; // @[frontend.scala:570:29] wire f3_mask_3; // @[frontend.scala:570:29] wire f3_mask_4; // @[frontend.scala:570:29] wire f3_mask_5; // @[frontend.scala:570:29] wire f3_mask_6; // @[frontend.scala:570:29] wire f3_mask_7; // @[frontend.scala:570:29] wire _f3_br_mask_0_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_1_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_2_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_3_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_4_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_5_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_6_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_7_T_1; // @[frontend.scala:736:37] wire f3_br_mask_0; // @[frontend.scala:571:29] wire f3_br_mask_1; // @[frontend.scala:571:29] wire f3_br_mask_2; // @[frontend.scala:571:29] wire f3_br_mask_3; // @[frontend.scala:571:29] wire f3_br_mask_4; // @[frontend.scala:571:29] wire f3_br_mask_5; // @[frontend.scala:571:29] wire f3_br_mask_6; // @[frontend.scala:571:29] wire f3_br_mask_7; // @[frontend.scala:571:29] wire brsigs_is_call; // @[frontend.scala:613:24] wire brsigs_1_is_call; // @[frontend.scala:613:24] wire brsigs_2_is_call; // @[frontend.scala:613:24] wire brsigs_3_is_call; // @[frontend.scala:613:24] wire brsigs_4_is_call; // @[frontend.scala:613:24] wire brsigs_5_is_call; // @[frontend.scala:613:24] wire brsigs_6_is_call; // @[frontend.scala:613:24] wire brsigs_7_is_call; // @[frontend.scala:613:24] wire f3_call_mask_0; // @[frontend.scala:572:29] wire f3_call_mask_1; // @[frontend.scala:572:29] wire f3_call_mask_2; // @[frontend.scala:572:29] wire f3_call_mask_3; // @[frontend.scala:572:29] wire f3_call_mask_4; // @[frontend.scala:572:29] wire f3_call_mask_5; // @[frontend.scala:572:29] wire f3_call_mask_6; // @[frontend.scala:572:29] wire f3_call_mask_7; // @[frontend.scala:572:29] wire brsigs_is_ret; // @[frontend.scala:613:24] wire brsigs_1_is_ret; // @[frontend.scala:613:24] wire brsigs_2_is_ret; // @[frontend.scala:613:24] wire brsigs_3_is_ret; // @[frontend.scala:613:24] wire brsigs_4_is_ret; // @[frontend.scala:613:24] wire brsigs_5_is_ret; // @[frontend.scala:613:24] wire brsigs_6_is_ret; // @[frontend.scala:613:24] wire brsigs_7_is_ret; // @[frontend.scala:613:24] wire f3_ret_mask_0; // @[frontend.scala:573:29] wire f3_ret_mask_1; // @[frontend.scala:573:29] wire f3_ret_mask_2; // @[frontend.scala:573:29] wire f3_ret_mask_3; // @[frontend.scala:573:29] wire f3_ret_mask_4; // @[frontend.scala:573:29] wire f3_ret_mask_5; // @[frontend.scala:573:29] wire f3_ret_mask_6; // @[frontend.scala:573:29] wire f3_ret_mask_7; // @[frontend.scala:573:29] wire _f3_npc_plus4_mask_0_T_2; // @[frontend.scala:703:23] wire _f3_npc_plus4_mask_1_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_2_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_3_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_4_T_2; // @[frontend.scala:703:23] wire _f3_npc_plus4_mask_5_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_6_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_7_T; // @[frontend.scala:705:9] wire f3_npc_plus4_mask_0; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_1; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_2; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_3; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_4; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_5; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_6; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_7; // @[frontend.scala:574:31] wire _f3_btb_mispredicts_0_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_1_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_2_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_3_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_4_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_5_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_6_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_7_T_4; // @[frontend.scala:697:61] wire f3_btb_mispredicts_0; // @[frontend.scala:575:32] wire f3_btb_mispredicts_1; // @[frontend.scala:575:32] wire f3_btb_mispredicts_2; // @[frontend.scala:575:32] wire f3_btb_mispredicts_3; // @[frontend.scala:575:32] wire f3_btb_mispredicts_4; // @[frontend.scala:575:32] wire f3_btb_mispredicts_5; // @[frontend.scala:575:32] wire f3_btb_mispredicts_6; // @[frontend.scala:575:32] wire f3_btb_mispredicts_7; // @[frontend.scala:575:32] wire [1:0] f3_fetch_bundle_mask_lo_lo = {f3_mask_1, f3_mask_0}; // @[frontend.scala:570:29, :576:35] wire [1:0] f3_fetch_bundle_mask_lo_hi = {f3_mask_3, f3_mask_2}; // @[frontend.scala:570:29, :576:35] wire [3:0] f3_fetch_bundle_mask_lo = {f3_fetch_bundle_mask_lo_hi, f3_fetch_bundle_mask_lo_lo}; // @[frontend.scala:576:35] wire [1:0] f3_fetch_bundle_mask_hi_lo = {f3_mask_5, f3_mask_4}; // @[frontend.scala:570:29, :576:35] wire [1:0] f3_fetch_bundle_mask_hi_hi = {f3_mask_7, f3_mask_6}; // @[frontend.scala:570:29, :576:35] wire [3:0] f3_fetch_bundle_mask_hi = {f3_fetch_bundle_mask_hi_hi, f3_fetch_bundle_mask_hi_lo}; // @[frontend.scala:576:35] assign _f3_fetch_bundle_mask_T = {f3_fetch_bundle_mask_hi, f3_fetch_bundle_mask_lo}; // @[frontend.scala:576:35] assign f3_fetch_bundle_mask = _f3_fetch_bundle_mask_T; // @[frontend.scala:569:29, :576:35] wire [1:0] f3_fetch_bundle_br_mask_lo_lo = {f3_br_mask_1, f3_br_mask_0}; // @[frontend.scala:571:29, :577:41] wire [1:0] f3_fetch_bundle_br_mask_lo_hi = {f3_br_mask_3, f3_br_mask_2}; // @[frontend.scala:571:29, :577:41] wire [3:0] f3_fetch_bundle_br_mask_lo = {f3_fetch_bundle_br_mask_lo_hi, f3_fetch_bundle_br_mask_lo_lo}; // @[frontend.scala:577:41] wire [1:0] f3_fetch_bundle_br_mask_hi_lo = {f3_br_mask_5, f3_br_mask_4}; // @[frontend.scala:571:29, :577:41] wire [1:0] f3_fetch_bundle_br_mask_hi_hi = {f3_br_mask_7, f3_br_mask_6}; // @[frontend.scala:571:29, :577:41] wire [3:0] f3_fetch_bundle_br_mask_hi = {f3_fetch_bundle_br_mask_hi_hi, f3_fetch_bundle_br_mask_hi_lo}; // @[frontend.scala:577:41] assign _f3_fetch_bundle_br_mask_T = {f3_fetch_bundle_br_mask_hi, f3_fetch_bundle_br_mask_lo}; // @[frontend.scala:577:41] assign f3_fetch_bundle_br_mask = _f3_fetch_bundle_br_mask_T; // @[frontend.scala:569:29, :577:41] reg [15:0] f3_prev_half; // @[frontend.scala:587:28] reg f3_prev_is_half; // @[frontend.scala:589:32] assign f3_fetch_bundle_edge_inst_0 = f3_prev_is_half; // @[frontend.scala:569:29, :589:32] wire _offset_from_aligned_pc_T_2 = f3_prev_is_half; // @[frontend.scala:589:32, :710:31] wire [63:0] bank_data = _f3_io_deq_bits_data[63:0]; // @[frontend.scala:516:11, :598:29] wire _bank_mask_0_T_4; // @[frontend.scala:689:71] wire _bank_mask_1_T_4; // @[frontend.scala:689:71] wire _bank_mask_2_T_4; // @[frontend.scala:689:71] wire _bank_mask_3_T_4; // @[frontend.scala:689:71] wire bank_mask_0; // @[frontend.scala:599:26] wire bank_mask_1; // @[frontend.scala:599:26] wire bank_mask_2; // @[frontend.scala:599:26] wire bank_mask_3; // @[frontend.scala:599:26] wire [31:0] bank_insts_0; // @[frontend.scala:600:26] wire [31:0] bank_insts_1; // @[frontend.scala:600:26] wire [31:0] bank_insts_2; // @[frontend.scala:600:26] wire [31:0] bank_insts_3; // @[frontend.scala:600:26] assign f3_ret_mask_0 = brsigs_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_0 = brsigs_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_0 = brsigs_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_target; // @[frontend.scala:613:24] wire brsigs_shadowable; // @[frontend.scala:613:24] wire [15:0] _inst0_T = bank_data[15:0]; // @[frontend.scala:598:29, :615:34] wire [31:0] inst0 = {_inst0_T, f3_prev_half}; // @[frontend.scala:587:28, :615:{24,34}] wire [31:0] inst1 = bank_data[31:0]; // @[frontend.scala:598:29, :616:30] wire [31:0] exp_inst0 = _exp_inst0_rvc_exp_io_rvc ? _exp_inst0_rvc_exp_io_out_bits : inst0; // @[frontend.scala:615:24] wire [31:0] exp_inst1 = _exp_inst1_rvc_exp_io_rvc ? _exp_inst1_rvc_exp_io_out_bits : inst1; // @[frontend.scala:616:30] wire [40:0] _GEN_16 = {1'h0, f3_aligned_pc}; // @[frontend.scala:160:31, :619:34] wire [40:0] _pc0_T; // @[frontend.scala:619:34] assign _pc0_T = _GEN_16; // @[frontend.scala:619:34] wire [40:0] _pc1_T; // @[frontend.scala:620:34] assign _pc1_T = _GEN_16; // @[frontend.scala:619:34, :620:34] wire [39:0] _pc0_T_1 = _pc0_T[39:0]; // @[frontend.scala:619:34] wire [40:0] _pc0_T_2 = {1'h0, _pc0_T_1} - 41'h2; // @[frontend.scala:619:{34,69}] wire [39:0] pc0 = _pc0_T_2[39:0]; // @[frontend.scala:619:69] wire [39:0] pc1 = _pc1_T[39:0]; // @[frontend.scala:620:34] wire [31:0] _GEN_17 = f3_prev_is_half ? inst0 : inst1; // @[frontend.scala:589:32, :615:24, :616:30, :629:34, :630:40, :651:40] assign f3_fetch_bundle_insts_0 = _GEN_17; // @[frontend.scala:569:29, :629:34, :630:40, :651:40] assign bank_insts_0 = _GEN_17; // @[frontend.scala:600:26, :629:34, :630:40, :651:40] assign f3_fetch_bundle_exp_insts_0 = f3_prev_is_half ? exp_inst0 : exp_inst1; // @[frontend.scala:569:29, :589:32, :629:34, :632:40, :653:40] assign brsigs_shadowable = f3_prev_is_half ? _bpd_decoder0_io_out_shadowable : _bpd_decoder1_io_out_shadowable; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_sfb_offset_valid = f3_prev_is_half ? _bpd_decoder0_io_out_sfb_offset_valid : _bpd_decoder1_io_out_sfb_offset_valid; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_sfb_offset_bits = f3_prev_is_half ? _bpd_decoder0_io_out_sfb_offset_bits : _bpd_decoder1_io_out_sfb_offset_bits; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_cfi_type = f3_prev_is_half ? _bpd_decoder0_io_out_cfi_type : _bpd_decoder1_io_out_cfi_type; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_target = f3_prev_is_half ? _bpd_decoder0_io_out_target : _bpd_decoder1_io_out_target; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_is_call = f3_prev_is_half ? _bpd_decoder0_io_out_is_call : _bpd_decoder1_io_out_is_call; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_is_ret = f3_prev_is_half ? _bpd_decoder0_io_out_is_ret : _bpd_decoder1_io_out_is_ret; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] wire [1:0] _f3_is_rvc_0_T = bank_insts_0[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T = bank_insts_0[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_0_T_1 = _f3_is_rvc_0_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_0 = _f3_is_rvc_0_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_0_T = _f3_io_deq_bits_mask[0]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_0_T = _f3_io_deq_bits_mask[0]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_0_T_1 = _f3_io_deq_valid & _bank_mask_0_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_0_T_2 = _bank_mask_0_T_1; // @[frontend.scala:689:{39,62}] assign _bank_mask_0_T_4 = _bank_mask_0_T_2; // @[frontend.scala:689:{62,71}] assign bank_mask_0 = _bank_mask_0_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_0_T_1 = _f3_io_deq_valid & _f3_mask_0_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_0_T_2 = _f3_mask_0_T_1; // @[frontend.scala:690:{39,62}] assign _f3_mask_0_T_4 = _f3_mask_0_T_2; // @[frontend.scala:690:{62,71}] assign f3_mask_0 = _f3_mask_0_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_18 = brsigs_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_0_T; // @[frontend.scala:691:43] assign _f3_targs_0_T = _GEN_18; // @[frontend.scala:691:43] wire _f3_redirects_0_T_1; // @[frontend.scala:732:56] assign _f3_redirects_0_T_1 = _GEN_18; // @[frontend.scala:691:43, :732:56] assign _f3_targs_0_T_1 = _f3_targs_0_T ? _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits : brsigs_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_0 = _f3_targs_0_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_19 = brsigs_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_0_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_0_T = _GEN_19; // @[frontend.scala:696:49] wire _f3_redirects_0_T; // @[frontend.scala:732:25] assign _f3_redirects_0_T = _GEN_19; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_0_T_1 = _f3_btb_mispredicts_0_T; // @[frontend.scala:696:{49,61}] wire _f3_btb_mispredicts_0_T_2 = _f3_btb_mispredicts_0_T_1 & _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_0_T_3 = _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits != brsigs_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_0_T_4 = _f3_btb_mispredicts_0_T_2 & _f3_btb_mispredicts_0_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_0 = _f3_btb_mispredicts_0_T_4; // @[frontend.scala:575:32, :697:61] wire _f3_npc_plus4_mask_0_T = ~f3_is_rvc_0; // @[frontend.scala:564:29, :703:9] wire _f3_npc_plus4_mask_0_T_1 = ~f3_prev_is_half; // @[frontend.scala:589:32, :703:26] assign _f3_npc_plus4_mask_0_T_2 = _f3_npc_plus4_mask_0_T & _f3_npc_plus4_mask_0_T_1; // @[frontend.scala:703:{9,23,26}] assign f3_npc_plus4_mask_0 = _f3_npc_plus4_mask_0_T_2; // @[frontend.scala:574:31, :703:23] wire [7:0] _offset_from_aligned_pc_T = {2'h0, brsigs_sfb_offset_bits}; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_1 = _offset_from_aligned_pc_T[6:0]; // @[frontend.scala:708:50] wire [1:0] _offset_from_aligned_pc_T_3 = {_offset_from_aligned_pc_T_2, 1'h0}; // @[frontend.scala:710:{12,31}] wire [7:0] _offset_from_aligned_pc_T_4 = {1'h0, _offset_from_aligned_pc_T_1} - {6'h0, _offset_from_aligned_pc_T_3}; // @[frontend.scala:708:50, :709:32, :710:12] wire [6:0] offset_from_aligned_pc = _offset_from_aligned_pc_T_4[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T = offset_from_aligned_pc[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_1 = 32'h1 << _upper_mask_T; // @[OneHot.scala:58:35] wire [2:0] _GEN_20 = {f3_is_last_bank_in_block, 2'h0}; // @[frontend.scala:152:21, :715:86] wire [2:0] _upper_mask_T_2; // @[frontend.scala:715:86] assign _upper_mask_T_2 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_6; // @[frontend.scala:715:86] assign _upper_mask_T_6 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_10; // @[frontend.scala:715:86] assign _upper_mask_T_10 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_14; // @[frontend.scala:715:86] assign _upper_mask_T_14 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_18; // @[frontend.scala:715:86] assign _upper_mask_T_18 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_22; // @[frontend.scala:715:86] assign _upper_mask_T_22 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_26; // @[frontend.scala:715:86] assign _upper_mask_T_26 = _GEN_20; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_30; // @[frontend.scala:715:86] assign _upper_mask_T_30 = _GEN_20; // @[frontend.scala:715:86] wire [38:0] _upper_mask_T_3 = {7'h0, _upper_mask_T_1} << _upper_mask_T_2; // @[OneHot.scala:58:35] assign upper_mask = _upper_mask_T_3[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_0_T = f3_mask_0 & brsigs_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire [5:0] _GEN_21 = f3_is_last_bank_in_block ? 6'h18 : 6'h20; // @[frontend.scala:152:21, :720:39] wire [5:0] _f3_fetch_bundle_sfbs_0_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_0_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_1_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_1_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_2_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_2_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_3_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_3_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_4_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_4_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_5_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_5_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_6_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_6_T_1 = _GEN_21; // @[frontend.scala:720:39] wire [5:0] _f3_fetch_bundle_sfbs_7_T_1; // @[frontend.scala:720:39] assign _f3_fetch_bundle_sfbs_7_T_1 = _GEN_21; // @[frontend.scala:720:39] wire _f3_fetch_bundle_sfbs_0_T_2 = offset_from_aligned_pc <= {1'h0, _f3_fetch_bundle_sfbs_0_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_0_T_3 = _f3_fetch_bundle_sfbs_0_T & _f3_fetch_bundle_sfbs_0_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_0 = _f3_fetch_bundle_sfbs_0_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_0_T_32 = {1'h0, upper_mask}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_33 = _f3_fetch_bundle_sfb_masks_0_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_0_T_34 = {upper_mask, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_35 = _f3_fetch_bundle_sfb_masks_0_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_0_T_36 = {1'h0, upper_mask, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_37 = _f3_fetch_bundle_sfb_masks_0_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_0_T_38 = {upper_mask, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_39 = _f3_fetch_bundle_sfb_masks_0_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_40 = {3'h0, upper_mask, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_41 = _f3_fetch_bundle_sfb_masks_0_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_42 = {2'h0, upper_mask, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_43 = _f3_fetch_bundle_sfb_masks_0_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_44 = {1'h0, upper_mask, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_45 = _f3_fetch_bundle_sfb_masks_0_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_0_T_46 = {upper_mask, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_47 = _f3_fetch_bundle_sfb_masks_0_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_48 = {7'h0, upper_mask, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_49 = _f3_fetch_bundle_sfb_masks_0_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_50 = {6'h0, upper_mask, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_51 = _f3_fetch_bundle_sfb_masks_0_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_52 = {5'h0, upper_mask, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_53 = _f3_fetch_bundle_sfb_masks_0_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_54 = {4'h0, upper_mask, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_55 = _f3_fetch_bundle_sfb_masks_0_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_56 = {3'h0, upper_mask, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_57 = _f3_fetch_bundle_sfb_masks_0_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_58 = {2'h0, upper_mask, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_59 = _f3_fetch_bundle_sfb_masks_0_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_60 = {1'h0, upper_mask, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_61 = _f3_fetch_bundle_sfb_masks_0_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_0_T_62 = {upper_mask, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_63 = _f3_fetch_bundle_sfb_masks_0_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_64 = _f3_fetch_bundle_sfb_masks_0_T_33 | _f3_fetch_bundle_sfb_masks_0_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_65 = _f3_fetch_bundle_sfb_masks_0_T_64 | _f3_fetch_bundle_sfb_masks_0_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_66 = _f3_fetch_bundle_sfb_masks_0_T_65 | _f3_fetch_bundle_sfb_masks_0_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_67 = _f3_fetch_bundle_sfb_masks_0_T_66 | _f3_fetch_bundle_sfb_masks_0_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_68 = _f3_fetch_bundle_sfb_masks_0_T_67 | _f3_fetch_bundle_sfb_masks_0_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_69 = _f3_fetch_bundle_sfb_masks_0_T_68 | _f3_fetch_bundle_sfb_masks_0_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_70 = _f3_fetch_bundle_sfb_masks_0_T_69 | _f3_fetch_bundle_sfb_masks_0_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_71 = _f3_fetch_bundle_sfb_masks_0_T_70 | _f3_fetch_bundle_sfb_masks_0_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_72 = _f3_fetch_bundle_sfb_masks_0_T_71 | _f3_fetch_bundle_sfb_masks_0_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_73 = _f3_fetch_bundle_sfb_masks_0_T_72 | _f3_fetch_bundle_sfb_masks_0_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_74 = _f3_fetch_bundle_sfb_masks_0_T_73 | _f3_fetch_bundle_sfb_masks_0_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_75 = _f3_fetch_bundle_sfb_masks_0_T_74 | _f3_fetch_bundle_sfb_masks_0_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_76 = _f3_fetch_bundle_sfb_masks_0_T_75 | _f3_fetch_bundle_sfb_masks_0_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_77 = _f3_fetch_bundle_sfb_masks_0_T_76 | _f3_fetch_bundle_sfb_masks_0_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_78 = _f3_fetch_bundle_sfb_masks_0_T_77 | _f3_fetch_bundle_sfb_masks_0_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_0_T_79 = ~_f3_fetch_bundle_sfb_masks_0_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_0_T_80 = _f3_fetch_bundle_sfb_masks_0_T_79 & 16'hFFFE; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_0 = _f3_fetch_bundle_sfb_masks_0_T_80; // @[frontend.scala:569:29, :722:68] wire _GEN_22 = f3_fetch_bundle_xcpt_pf_if | f3_fetch_bundle_xcpt_ae_if; // @[frontend.scala:569:29, :723:75] wire _f3_fetch_bundle_shadowable_mask_0_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_0_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_1_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_1_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_2_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_2_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_3_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_3_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_4_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_4_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_5_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_5_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_6_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_6_T = _GEN_22; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_7_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_7_T = _GEN_22; // @[frontend.scala:723:75] wire _s0_valid_T_11; // @[frontend.scala:831:52] assign _s0_valid_T_11 = _GEN_22; // @[frontend.scala:723:75, :831:52] wire _f3_fetch_bundle_shadowable_mask_0_T_1 = _f3_fetch_bundle_shadowable_mask_0_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_0_T_2 = _f3_fetch_bundle_shadowable_mask_0_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_0_T_3 = ~_f3_fetch_bundle_shadowable_mask_0_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_0_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_1_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_2_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_3_T_4 = f3_bank_mask[0]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_0_T_5 = _f3_fetch_bundle_shadowable_mask_0_T_3 & _f3_fetch_bundle_shadowable_mask_0_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_0_T_6 = ~f3_mask_0; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_0_T_7 = brsigs_shadowable | _f3_fetch_bundle_shadowable_mask_0_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_0_T_8 = _f3_fetch_bundle_shadowable_mask_0_T_5 & _f3_fetch_bundle_shadowable_mask_0_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_0 = _f3_fetch_bundle_shadowable_mask_0_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_0 = offset_from_aligned_pc[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_0_T_2 = _f3_redirects_0_T | _f3_redirects_0_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_23 = brsigs_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_0_T_3; // @[frontend.scala:733:26] assign _f3_redirects_0_T_3 = _GEN_23; // @[frontend.scala:733:26] wire _f3_br_mask_0_T; // @[frontend.scala:736:56] assign _f3_br_mask_0_T = _GEN_23; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_0_T_4 = _f3_redirects_0_T_3 & _f3_bpd_resp_io_deq_bits_preds_0_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_0_T_5 = _f3_redirects_0_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_0_T_6 = _f3_redirects_0_T_2 | _f3_redirects_0_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_0_T_7 = f3_mask_0 & _f3_redirects_0_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_0 = _f3_redirects_0_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_0_T_1 = f3_mask_0 & _f3_br_mask_0_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_0 = _f3_br_mask_0_T_1; // @[frontend.scala:571:29, :736:37] wire _valid_T_5; // @[frontend.scala:675:38] wire valid_1; // @[frontend.scala:605:23] assign f3_ret_mask_1 = brsigs_1_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_1 = brsigs_1_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_1 = brsigs_1_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_1_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_1_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_1_target; // @[frontend.scala:613:24] wire brsigs_1_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T; // @[frontend.scala:674:29] assign f3_fetch_bundle_insts_1 = inst; // @[frontend.scala:569:29, :660:24] assign bank_insts_1 = inst; // @[frontend.scala:600:26, :660:24] assign exp_inst = _exp_inst_rvc_exp_io_rvc ? _exp_inst_rvc_exp_io_out_bits : inst; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_1 = exp_inst; // @[frontend.scala:569:29] wire [40:0] _pc_T = _GEN_16 + 41'h2; // @[frontend.scala:619:34, :662:32] wire [39:0] pc = _pc_T[39:0]; // @[frontend.scala:662:32] assign _inst_T = bank_data[47:16]; // @[frontend.scala:598:29, :674:29] assign inst = _inst_T; // @[frontend.scala:660:24, :674:29] wire _valid_T_1 = _valid_T != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_2 = ~_valid_T_1; // @[frontend.scala:592:38, :675:59] wire _valid_T_3 = bank_mask_0 & _valid_T_2; // @[frontend.scala:599:26, :675:{56,59}] wire _valid_T_4 = ~_valid_T_3; // @[frontend.scala:675:{41,56}] assign _valid_T_5 = f3_prev_is_half | _valid_T_4; // @[frontend.scala:589:32, :675:{38,41}] assign valid_1 = _valid_T_5; // @[frontend.scala:605:23, :675:38] wire [1:0] _f3_is_rvc_1_T = bank_insts_1[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_6 = bank_insts_1[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_1_T_1 = _f3_is_rvc_1_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_1 = _f3_is_rvc_1_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_1_T = _f3_io_deq_bits_mask[1]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_1_T = _f3_io_deq_bits_mask[1]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_1_T_1 = _f3_io_deq_valid & _bank_mask_1_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_1_T_2 = _bank_mask_1_T_1 & valid_1; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_1_T_3 = ~f3_redirects_0; // @[frontend.scala:565:29, :689:74] assign _bank_mask_1_T_4 = _bank_mask_1_T_2 & _bank_mask_1_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1 = _bank_mask_1_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_1_T_1 = _f3_io_deq_valid & _f3_mask_1_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_1_T_2 = _f3_mask_1_T_1 & valid_1; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_1_T_3 = ~f3_redirects_0; // @[frontend.scala:565:29, :689:74, :690:74] assign _f3_mask_1_T_4 = _f3_mask_1_T_2 & _f3_mask_1_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_1 = _f3_mask_1_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_24 = brsigs_1_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_1_T; // @[frontend.scala:691:43] assign _f3_targs_1_T = _GEN_24; // @[frontend.scala:691:43] wire _f3_redirects_1_T_1; // @[frontend.scala:732:56] assign _f3_redirects_1_T_1 = _GEN_24; // @[frontend.scala:691:43, :732:56] assign _f3_targs_1_T_1 = _f3_targs_1_T ? _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits : brsigs_1_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_1 = _f3_targs_1_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_25 = brsigs_1_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_1_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_1_T = _GEN_25; // @[frontend.scala:696:49] wire _f3_redirects_1_T; // @[frontend.scala:732:25] assign _f3_redirects_1_T = _GEN_25; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_1_T_1 = _f3_btb_mispredicts_1_T & valid_1; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_1_T_2 = _f3_btb_mispredicts_1_T_1 & _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_1_T_3 = _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits != brsigs_1_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_1_T_4 = _f3_btb_mispredicts_1_T_2 & _f3_btb_mispredicts_1_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_1 = _f3_btb_mispredicts_1_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_1_T = ~f3_is_rvc_1; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_1 = _f3_npc_plus4_mask_1_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_5 = {2'h0, brsigs_1_sfb_offset_bits} + 8'h2; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_6 = _offset_from_aligned_pc_T_5[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_9 = {1'h0, _offset_from_aligned_pc_T_6}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_1 = _offset_from_aligned_pc_T_9[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_1; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_4 = offset_from_aligned_pc_1[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_5 = 32'h1 << _upper_mask_T_4; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_7 = {7'h0, _upper_mask_T_5} << _upper_mask_T_6; // @[OneHot.scala:58:35] assign upper_mask_1 = _upper_mask_T_7[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_1_T = f3_mask_1 & brsigs_1_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_1_T_2 = offset_from_aligned_pc_1 <= {1'h0, _f3_fetch_bundle_sfbs_1_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_1_T_3 = _f3_fetch_bundle_sfbs_1_T & _f3_fetch_bundle_sfbs_1_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_1 = _f3_fetch_bundle_sfbs_1_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_1_T_32 = {1'h0, upper_mask_1}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_33 = _f3_fetch_bundle_sfb_masks_1_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_1_T_34 = {upper_mask_1, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_35 = _f3_fetch_bundle_sfb_masks_1_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_1_T_36 = {1'h0, upper_mask_1, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_37 = _f3_fetch_bundle_sfb_masks_1_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_1_T_38 = {upper_mask_1, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_39 = _f3_fetch_bundle_sfb_masks_1_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_40 = {3'h0, upper_mask_1, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_41 = _f3_fetch_bundle_sfb_masks_1_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_42 = {2'h0, upper_mask_1, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_43 = _f3_fetch_bundle_sfb_masks_1_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_44 = {1'h0, upper_mask_1, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_45 = _f3_fetch_bundle_sfb_masks_1_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_1_T_46 = {upper_mask_1, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_47 = _f3_fetch_bundle_sfb_masks_1_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_48 = {7'h0, upper_mask_1, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_49 = _f3_fetch_bundle_sfb_masks_1_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_50 = {6'h0, upper_mask_1, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_51 = _f3_fetch_bundle_sfb_masks_1_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_52 = {5'h0, upper_mask_1, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_53 = _f3_fetch_bundle_sfb_masks_1_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_54 = {4'h0, upper_mask_1, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_55 = _f3_fetch_bundle_sfb_masks_1_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_56 = {3'h0, upper_mask_1, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_57 = _f3_fetch_bundle_sfb_masks_1_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_58 = {2'h0, upper_mask_1, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_59 = _f3_fetch_bundle_sfb_masks_1_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_60 = {1'h0, upper_mask_1, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_61 = _f3_fetch_bundle_sfb_masks_1_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_1_T_62 = {upper_mask_1, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_63 = _f3_fetch_bundle_sfb_masks_1_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_64 = _f3_fetch_bundle_sfb_masks_1_T_33 | _f3_fetch_bundle_sfb_masks_1_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_65 = _f3_fetch_bundle_sfb_masks_1_T_64 | _f3_fetch_bundle_sfb_masks_1_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_66 = _f3_fetch_bundle_sfb_masks_1_T_65 | _f3_fetch_bundle_sfb_masks_1_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_67 = _f3_fetch_bundle_sfb_masks_1_T_66 | _f3_fetch_bundle_sfb_masks_1_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_68 = _f3_fetch_bundle_sfb_masks_1_T_67 | _f3_fetch_bundle_sfb_masks_1_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_69 = _f3_fetch_bundle_sfb_masks_1_T_68 | _f3_fetch_bundle_sfb_masks_1_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_70 = _f3_fetch_bundle_sfb_masks_1_T_69 | _f3_fetch_bundle_sfb_masks_1_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_71 = _f3_fetch_bundle_sfb_masks_1_T_70 | _f3_fetch_bundle_sfb_masks_1_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_72 = _f3_fetch_bundle_sfb_masks_1_T_71 | _f3_fetch_bundle_sfb_masks_1_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_73 = _f3_fetch_bundle_sfb_masks_1_T_72 | _f3_fetch_bundle_sfb_masks_1_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_74 = _f3_fetch_bundle_sfb_masks_1_T_73 | _f3_fetch_bundle_sfb_masks_1_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_75 = _f3_fetch_bundle_sfb_masks_1_T_74 | _f3_fetch_bundle_sfb_masks_1_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_76 = _f3_fetch_bundle_sfb_masks_1_T_75 | _f3_fetch_bundle_sfb_masks_1_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_77 = _f3_fetch_bundle_sfb_masks_1_T_76 | _f3_fetch_bundle_sfb_masks_1_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_78 = _f3_fetch_bundle_sfb_masks_1_T_77 | _f3_fetch_bundle_sfb_masks_1_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_1_T_79 = ~_f3_fetch_bundle_sfb_masks_1_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_1_T_80 = _f3_fetch_bundle_sfb_masks_1_T_79 & 16'hFFFC; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_1 = _f3_fetch_bundle_sfb_masks_1_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_1_T_1 = _f3_fetch_bundle_shadowable_mask_1_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_1_T_2 = _f3_fetch_bundle_shadowable_mask_1_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_1_T_3 = ~_f3_fetch_bundle_shadowable_mask_1_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_1_T_5 = _f3_fetch_bundle_shadowable_mask_1_T_3 & _f3_fetch_bundle_shadowable_mask_1_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_1_T_6 = ~f3_mask_1; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_1_T_7 = brsigs_1_shadowable | _f3_fetch_bundle_shadowable_mask_1_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_1_T_8 = _f3_fetch_bundle_shadowable_mask_1_T_5 & _f3_fetch_bundle_shadowable_mask_1_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_1 = _f3_fetch_bundle_shadowable_mask_1_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_1 = offset_from_aligned_pc_1[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_1_T_2 = _f3_redirects_1_T | _f3_redirects_1_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_26 = brsigs_1_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_1_T_3; // @[frontend.scala:733:26] assign _f3_redirects_1_T_3 = _GEN_26; // @[frontend.scala:733:26] wire _f3_br_mask_1_T; // @[frontend.scala:736:56] assign _f3_br_mask_1_T = _GEN_26; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_1_T_4 = _f3_redirects_1_T_3 & _f3_bpd_resp_io_deq_bits_preds_1_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_1_T_5 = _f3_redirects_1_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_1_T_6 = _f3_redirects_1_T_2 | _f3_redirects_1_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_1_T_7 = f3_mask_1 & _f3_redirects_1_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_1 = _f3_redirects_1_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_1_T_1 = f3_mask_1 & _f3_br_mask_1_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_1 = _f3_br_mask_1_T_1; // @[frontend.scala:571:29, :736:37] wire _T_29 = f3_redirects_0 | f3_redirects_1; // @[frontend.scala:565:29, :744:39] wire _valid_T_10; // @[frontend.scala:682:20] wire valid_2; // @[frontend.scala:605:23] assign f3_ret_mask_2 = brsigs_2_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_2 = brsigs_2_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_2 = brsigs_2_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_2_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_2_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_2_target; // @[frontend.scala:613:24] wire brsigs_2_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_1; // @[frontend.scala:681:29] assign f3_fetch_bundle_insts_2 = inst_1; // @[frontend.scala:569:29, :660:24] assign bank_insts_2 = inst_1; // @[frontend.scala:600:26, :660:24] assign exp_inst_1 = _exp_inst_rvc_exp_1_io_rvc ? _exp_inst_rvc_exp_1_io_out_bits : inst_1; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_2 = exp_inst_1; // @[frontend.scala:569:29] wire [40:0] _pc_T_1 = _GEN_16 + 41'h4; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_1 = _pc_T_1[39:0]; // @[frontend.scala:662:32] assign _inst_T_1 = bank_data[63:32]; // @[frontend.scala:598:29, :681:29] assign inst_1 = _inst_T_1; // @[frontend.scala:660:24, :681:29] wire _valid_T_7 = _valid_T_6 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_8 = ~_valid_T_7; // @[frontend.scala:592:38, :682:40] wire _valid_T_9 = bank_mask_1 & _valid_T_8; // @[frontend.scala:599:26, :682:{37,40}] assign _valid_T_10 = ~_valid_T_9; // @[frontend.scala:682:{20,37}] assign valid_2 = _valid_T_10; // @[frontend.scala:605:23, :682:20] wire [1:0] _f3_is_rvc_2_T = bank_insts_2[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_11 = bank_insts_2[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_2_T_1 = _f3_is_rvc_2_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_2 = _f3_is_rvc_2_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_2_T = _f3_io_deq_bits_mask[2]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_2_T = _f3_io_deq_bits_mask[2]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_2_T_1 = _f3_io_deq_valid & _bank_mask_2_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_2_T_2 = _bank_mask_2_T_1 & valid_2; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_2_T_3 = ~_T_29; // @[frontend.scala:689:74, :744:39] assign _bank_mask_2_T_4 = _bank_mask_2_T_2 & _bank_mask_2_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_2 = _bank_mask_2_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_2_T_1 = _f3_io_deq_valid & _f3_mask_2_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_2_T_2 = _f3_mask_2_T_1 & valid_2; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_2_T_3 = ~_T_29; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_2_T_4 = _f3_mask_2_T_2 & _f3_mask_2_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_2 = _f3_mask_2_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_27 = brsigs_2_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_2_T; // @[frontend.scala:691:43] assign _f3_targs_2_T = _GEN_27; // @[frontend.scala:691:43] wire _f3_redirects_2_T_1; // @[frontend.scala:732:56] assign _f3_redirects_2_T_1 = _GEN_27; // @[frontend.scala:691:43, :732:56] assign _f3_targs_2_T_1 = _f3_targs_2_T ? _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits : brsigs_2_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_2 = _f3_targs_2_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_28 = brsigs_2_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_2_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_2_T = _GEN_28; // @[frontend.scala:696:49] wire _f3_redirects_2_T; // @[frontend.scala:732:25] assign _f3_redirects_2_T = _GEN_28; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_2_T_1 = _f3_btb_mispredicts_2_T & valid_2; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_2_T_2 = _f3_btb_mispredicts_2_T_1 & _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_2_T_3 = _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits != brsigs_2_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_2_T_4 = _f3_btb_mispredicts_2_T_2 & _f3_btb_mispredicts_2_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_2 = _f3_btb_mispredicts_2_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_2_T = ~f3_is_rvc_2; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_2 = _f3_npc_plus4_mask_2_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_10 = {2'h0, brsigs_2_sfb_offset_bits} + 8'h4; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_11 = _offset_from_aligned_pc_T_10[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_14 = {1'h0, _offset_from_aligned_pc_T_11}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_2 = _offset_from_aligned_pc_T_14[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_2; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_8 = offset_from_aligned_pc_2[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_9 = 32'h1 << _upper_mask_T_8; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_11 = {7'h0, _upper_mask_T_9} << _upper_mask_T_10; // @[OneHot.scala:58:35] assign upper_mask_2 = _upper_mask_T_11[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_2_T = f3_mask_2 & brsigs_2_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_2_T_2 = offset_from_aligned_pc_2 <= {1'h0, _f3_fetch_bundle_sfbs_2_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_2_T_3 = _f3_fetch_bundle_sfbs_2_T & _f3_fetch_bundle_sfbs_2_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_2 = _f3_fetch_bundle_sfbs_2_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_2_T_32 = {1'h0, upper_mask_2}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_33 = _f3_fetch_bundle_sfb_masks_2_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_2_T_34 = {upper_mask_2, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_35 = _f3_fetch_bundle_sfb_masks_2_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_2_T_36 = {1'h0, upper_mask_2, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_37 = _f3_fetch_bundle_sfb_masks_2_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_2_T_38 = {upper_mask_2, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_39 = _f3_fetch_bundle_sfb_masks_2_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_40 = {3'h0, upper_mask_2, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_41 = _f3_fetch_bundle_sfb_masks_2_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_42 = {2'h0, upper_mask_2, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_43 = _f3_fetch_bundle_sfb_masks_2_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_44 = {1'h0, upper_mask_2, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_45 = _f3_fetch_bundle_sfb_masks_2_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_2_T_46 = {upper_mask_2, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_47 = _f3_fetch_bundle_sfb_masks_2_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_48 = {7'h0, upper_mask_2, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_49 = _f3_fetch_bundle_sfb_masks_2_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_50 = {6'h0, upper_mask_2, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_51 = _f3_fetch_bundle_sfb_masks_2_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_52 = {5'h0, upper_mask_2, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_53 = _f3_fetch_bundle_sfb_masks_2_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_54 = {4'h0, upper_mask_2, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_55 = _f3_fetch_bundle_sfb_masks_2_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_56 = {3'h0, upper_mask_2, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_57 = _f3_fetch_bundle_sfb_masks_2_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_58 = {2'h0, upper_mask_2, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_59 = _f3_fetch_bundle_sfb_masks_2_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_60 = {1'h0, upper_mask_2, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_61 = _f3_fetch_bundle_sfb_masks_2_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_2_T_62 = {upper_mask_2, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_63 = _f3_fetch_bundle_sfb_masks_2_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_64 = _f3_fetch_bundle_sfb_masks_2_T_33 | _f3_fetch_bundle_sfb_masks_2_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_65 = _f3_fetch_bundle_sfb_masks_2_T_64 | _f3_fetch_bundle_sfb_masks_2_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_66 = _f3_fetch_bundle_sfb_masks_2_T_65 | _f3_fetch_bundle_sfb_masks_2_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_67 = _f3_fetch_bundle_sfb_masks_2_T_66 | _f3_fetch_bundle_sfb_masks_2_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_68 = _f3_fetch_bundle_sfb_masks_2_T_67 | _f3_fetch_bundle_sfb_masks_2_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_69 = _f3_fetch_bundle_sfb_masks_2_T_68 | _f3_fetch_bundle_sfb_masks_2_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_70 = _f3_fetch_bundle_sfb_masks_2_T_69 | _f3_fetch_bundle_sfb_masks_2_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_71 = _f3_fetch_bundle_sfb_masks_2_T_70 | _f3_fetch_bundle_sfb_masks_2_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_72 = _f3_fetch_bundle_sfb_masks_2_T_71 | _f3_fetch_bundle_sfb_masks_2_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_73 = _f3_fetch_bundle_sfb_masks_2_T_72 | _f3_fetch_bundle_sfb_masks_2_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_74 = _f3_fetch_bundle_sfb_masks_2_T_73 | _f3_fetch_bundle_sfb_masks_2_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_75 = _f3_fetch_bundle_sfb_masks_2_T_74 | _f3_fetch_bundle_sfb_masks_2_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_76 = _f3_fetch_bundle_sfb_masks_2_T_75 | _f3_fetch_bundle_sfb_masks_2_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_77 = _f3_fetch_bundle_sfb_masks_2_T_76 | _f3_fetch_bundle_sfb_masks_2_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_78 = _f3_fetch_bundle_sfb_masks_2_T_77 | _f3_fetch_bundle_sfb_masks_2_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_2_T_79 = ~_f3_fetch_bundle_sfb_masks_2_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_2_T_80 = _f3_fetch_bundle_sfb_masks_2_T_79 & 16'hFFF8; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_2 = _f3_fetch_bundle_sfb_masks_2_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_2_T_1 = _f3_fetch_bundle_shadowable_mask_2_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_2_T_2 = _f3_fetch_bundle_shadowable_mask_2_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_2_T_3 = ~_f3_fetch_bundle_shadowable_mask_2_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_2_T_5 = _f3_fetch_bundle_shadowable_mask_2_T_3 & _f3_fetch_bundle_shadowable_mask_2_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_2_T_6 = ~f3_mask_2; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_2_T_7 = brsigs_2_shadowable | _f3_fetch_bundle_shadowable_mask_2_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_2_T_8 = _f3_fetch_bundle_shadowable_mask_2_T_5 & _f3_fetch_bundle_shadowable_mask_2_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_2 = _f3_fetch_bundle_shadowable_mask_2_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_2 = offset_from_aligned_pc_2[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_2_T_2 = _f3_redirects_2_T | _f3_redirects_2_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_29 = brsigs_2_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_2_T_3; // @[frontend.scala:733:26] assign _f3_redirects_2_T_3 = _GEN_29; // @[frontend.scala:733:26] wire _f3_br_mask_2_T; // @[frontend.scala:736:56] assign _f3_br_mask_2_T = _GEN_29; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_2_T_4 = _f3_redirects_2_T_3 & _f3_bpd_resp_io_deq_bits_preds_2_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_2_T_5 = _f3_redirects_2_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_2_T_6 = _f3_redirects_2_T_2 | _f3_redirects_2_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_2_T_7 = f3_mask_2 & _f3_redirects_2_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_2 = _f3_redirects_2_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_2_T_1 = f3_mask_2 & _f3_br_mask_2_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_2 = _f3_br_mask_2_T_1; // @[frontend.scala:571:29, :736:37] wire _T_30 = _T_29 | f3_redirects_2; // @[frontend.scala:565:29, :744:39] wire _valid_T_19; // @[frontend.scala:678:20] wire valid_3; // @[frontend.scala:605:23] assign f3_ret_mask_3 = brsigs_3_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_3 = brsigs_3_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_3 = brsigs_3_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_3_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_3_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_3_target; // @[frontend.scala:613:24] wire brsigs_3_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_3; // @[frontend.scala:677:23] assign f3_fetch_bundle_insts_3 = inst_2; // @[frontend.scala:569:29, :660:24] assign bank_insts_3 = inst_2; // @[frontend.scala:600:26, :660:24] assign exp_inst_2 = _exp_inst_rvc_exp_2_io_rvc ? _exp_inst_rvc_exp_2_io_out_bits : inst_2; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_3 = exp_inst_2; // @[frontend.scala:569:29] wire [40:0] _pc_T_2 = _GEN_16 + 41'h6; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_2 = _pc_T_2[39:0]; // @[frontend.scala:662:32] wire [15:0] _inst_T_2 = bank_data[63:48]; // @[frontend.scala:598:29, :677:44] assign _inst_T_3 = {16'h0, _inst_T_2}; // @[frontend.scala:677:{23,44}] assign inst_2 = _inst_T_3; // @[frontend.scala:660:24, :677:23] wire _valid_T_12 = _valid_T_11 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_13 = ~_valid_T_12; // @[frontend.scala:592:38, :678:41] wire _valid_T_14 = bank_mask_2 & _valid_T_13; // @[frontend.scala:599:26, :678:{38,41}] wire [1:0] _valid_T_15 = inst_2[1:0]; // @[frontend.scala:592:32, :660:24] wire _valid_T_16 = _valid_T_15 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_17 = ~_valid_T_16; // @[frontend.scala:592:38, :679:13] wire _valid_T_18 = _valid_T_14 | _valid_T_17; // @[frontend.scala:678:{38,66}, :679:13] assign _valid_T_19 = ~_valid_T_18; // @[frontend.scala:678:{20,66}] assign valid_3 = _valid_T_19; // @[frontend.scala:605:23, :678:20] wire [1:0] _f3_is_rvc_3_T = bank_insts_3[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_3_T_1 = _f3_is_rvc_3_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_3 = _f3_is_rvc_3_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_3_T = _f3_io_deq_bits_mask[3]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_3_T = _f3_io_deq_bits_mask[3]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_3_T_1 = _f3_io_deq_valid & _bank_mask_3_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_3_T_2 = _bank_mask_3_T_1 & valid_3; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_3_T_3 = ~_T_30; // @[frontend.scala:689:74, :744:39] assign _bank_mask_3_T_4 = _bank_mask_3_T_2 & _bank_mask_3_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_3 = _bank_mask_3_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_3_T_1 = _f3_io_deq_valid & _f3_mask_3_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_3_T_2 = _f3_mask_3_T_1 & valid_3; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_3_T_3 = ~_T_30; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_3_T_4 = _f3_mask_3_T_2 & _f3_mask_3_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_3 = _f3_mask_3_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_30 = brsigs_3_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_3_T; // @[frontend.scala:691:43] assign _f3_targs_3_T = _GEN_30; // @[frontend.scala:691:43] wire _f3_redirects_3_T_1; // @[frontend.scala:732:56] assign _f3_redirects_3_T_1 = _GEN_30; // @[frontend.scala:691:43, :732:56] assign _f3_targs_3_T_1 = _f3_targs_3_T ? _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits : brsigs_3_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_3 = _f3_targs_3_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_31 = brsigs_3_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_3_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_3_T = _GEN_31; // @[frontend.scala:696:49] wire _f3_redirects_3_T; // @[frontend.scala:732:25] assign _f3_redirects_3_T = _GEN_31; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_3_T_1 = _f3_btb_mispredicts_3_T & valid_3; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_3_T_2 = _f3_btb_mispredicts_3_T_1 & _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_3_T_3 = _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits != brsigs_3_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_3_T_4 = _f3_btb_mispredicts_3_T_2 & _f3_btb_mispredicts_3_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_3 = _f3_btb_mispredicts_3_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_3_T = ~f3_is_rvc_3; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_3 = _f3_npc_plus4_mask_3_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_15 = {2'h0, brsigs_3_sfb_offset_bits} + 8'h6; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_16 = _offset_from_aligned_pc_T_15[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_19 = {1'h0, _offset_from_aligned_pc_T_16}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_3 = _offset_from_aligned_pc_T_19[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_3; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_12 = offset_from_aligned_pc_3[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_13 = 32'h1 << _upper_mask_T_12; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_15 = {7'h0, _upper_mask_T_13} << _upper_mask_T_14; // @[OneHot.scala:58:35] assign upper_mask_3 = _upper_mask_T_15[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_3_T = f3_mask_3 & brsigs_3_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_3_T_2 = offset_from_aligned_pc_3 <= {1'h0, _f3_fetch_bundle_sfbs_3_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_3_T_3 = _f3_fetch_bundle_sfbs_3_T & _f3_fetch_bundle_sfbs_3_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_3 = _f3_fetch_bundle_sfbs_3_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_3_T_32 = {1'h0, upper_mask_3}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_33 = _f3_fetch_bundle_sfb_masks_3_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_3_T_34 = {upper_mask_3, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_35 = _f3_fetch_bundle_sfb_masks_3_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_3_T_36 = {1'h0, upper_mask_3, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_37 = _f3_fetch_bundle_sfb_masks_3_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_3_T_38 = {upper_mask_3, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_39 = _f3_fetch_bundle_sfb_masks_3_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_40 = {3'h0, upper_mask_3, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_41 = _f3_fetch_bundle_sfb_masks_3_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_42 = {2'h0, upper_mask_3, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_43 = _f3_fetch_bundle_sfb_masks_3_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_44 = {1'h0, upper_mask_3, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_45 = _f3_fetch_bundle_sfb_masks_3_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_3_T_46 = {upper_mask_3, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_47 = _f3_fetch_bundle_sfb_masks_3_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_48 = {7'h0, upper_mask_3, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_49 = _f3_fetch_bundle_sfb_masks_3_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_50 = {6'h0, upper_mask_3, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_51 = _f3_fetch_bundle_sfb_masks_3_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_52 = {5'h0, upper_mask_3, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_53 = _f3_fetch_bundle_sfb_masks_3_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_54 = {4'h0, upper_mask_3, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_55 = _f3_fetch_bundle_sfb_masks_3_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_56 = {3'h0, upper_mask_3, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_57 = _f3_fetch_bundle_sfb_masks_3_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_58 = {2'h0, upper_mask_3, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_59 = _f3_fetch_bundle_sfb_masks_3_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_60 = {1'h0, upper_mask_3, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_61 = _f3_fetch_bundle_sfb_masks_3_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_3_T_62 = {upper_mask_3, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_63 = _f3_fetch_bundle_sfb_masks_3_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_64 = _f3_fetch_bundle_sfb_masks_3_T_33 | _f3_fetch_bundle_sfb_masks_3_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_65 = _f3_fetch_bundle_sfb_masks_3_T_64 | _f3_fetch_bundle_sfb_masks_3_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_66 = _f3_fetch_bundle_sfb_masks_3_T_65 | _f3_fetch_bundle_sfb_masks_3_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_67 = _f3_fetch_bundle_sfb_masks_3_T_66 | _f3_fetch_bundle_sfb_masks_3_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_68 = _f3_fetch_bundle_sfb_masks_3_T_67 | _f3_fetch_bundle_sfb_masks_3_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_69 = _f3_fetch_bundle_sfb_masks_3_T_68 | _f3_fetch_bundle_sfb_masks_3_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_70 = _f3_fetch_bundle_sfb_masks_3_T_69 | _f3_fetch_bundle_sfb_masks_3_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_71 = _f3_fetch_bundle_sfb_masks_3_T_70 | _f3_fetch_bundle_sfb_masks_3_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_72 = _f3_fetch_bundle_sfb_masks_3_T_71 | _f3_fetch_bundle_sfb_masks_3_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_73 = _f3_fetch_bundle_sfb_masks_3_T_72 | _f3_fetch_bundle_sfb_masks_3_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_74 = _f3_fetch_bundle_sfb_masks_3_T_73 | _f3_fetch_bundle_sfb_masks_3_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_75 = _f3_fetch_bundle_sfb_masks_3_T_74 | _f3_fetch_bundle_sfb_masks_3_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_76 = _f3_fetch_bundle_sfb_masks_3_T_75 | _f3_fetch_bundle_sfb_masks_3_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_77 = _f3_fetch_bundle_sfb_masks_3_T_76 | _f3_fetch_bundle_sfb_masks_3_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_78 = _f3_fetch_bundle_sfb_masks_3_T_77 | _f3_fetch_bundle_sfb_masks_3_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_3_T_79 = ~_f3_fetch_bundle_sfb_masks_3_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_3_T_80 = _f3_fetch_bundle_sfb_masks_3_T_79 & 16'hFFF0; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_3 = _f3_fetch_bundle_sfb_masks_3_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_3_T_1 = _f3_fetch_bundle_shadowable_mask_3_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_3_T_2 = _f3_fetch_bundle_shadowable_mask_3_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_3_T_3 = ~_f3_fetch_bundle_shadowable_mask_3_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_3_T_5 = _f3_fetch_bundle_shadowable_mask_3_T_3 & _f3_fetch_bundle_shadowable_mask_3_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_3_T_6 = ~f3_mask_3; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_3_T_7 = brsigs_3_shadowable | _f3_fetch_bundle_shadowable_mask_3_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_3_T_8 = _f3_fetch_bundle_shadowable_mask_3_T_5 & _f3_fetch_bundle_shadowable_mask_3_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_3 = _f3_fetch_bundle_shadowable_mask_3_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_3 = offset_from_aligned_pc_3[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_3_T_2 = _f3_redirects_3_T | _f3_redirects_3_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_32 = brsigs_3_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_3_T_3; // @[frontend.scala:733:26] assign _f3_redirects_3_T_3 = _GEN_32; // @[frontend.scala:733:26] wire _f3_br_mask_3_T; // @[frontend.scala:736:56] assign _f3_br_mask_3_T = _GEN_32; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_3_T_4 = _f3_redirects_3_T_3 & _f3_bpd_resp_io_deq_bits_preds_3_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_3_T_5 = _f3_redirects_3_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_3_T_6 = _f3_redirects_3_T_2 | _f3_redirects_3_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_3_T_7 = f3_mask_3 & _f3_redirects_3_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_3 = _f3_redirects_3_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_3_T_1 = f3_mask_3 & _f3_br_mask_3_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_3 = _f3_br_mask_3_T_1; // @[frontend.scala:571:29, :736:37] wire _T_31 = _T_30 | f3_redirects_3; // @[frontend.scala:565:29, :744:39] wire _T_43 = f3_bank_mask[0] ? ~(bank_mask_2 & (&(bank_insts_2[1:0]))) & (&(bank_insts_3[1:0])) : f3_prev_is_half; // @[frontend.scala:190:10, :589:32, :592:{32,38}, :599:26, :600:26, :724:58, :746:40, :747:28, :748:{8,33,69}] assign f3_fetch_bundle_edge_inst_1 = _T_43; // @[frontend.scala:569:29, :747:28] wire _offset_from_aligned_pc_T_22; // @[frontend.scala:710:31] assign _offset_from_aligned_pc_T_22 = _T_43; // @[frontend.scala:710:31, :747:28] wire [63:0] bank_data_1 = _f3_io_deq_bits_data[127:64]; // @[frontend.scala:516:11, :598:29] wire _bank_mask_0_T_9; // @[frontend.scala:689:71] wire _bank_mask_1_T_9; // @[frontend.scala:689:71] wire _bank_mask_2_T_9; // @[frontend.scala:689:71] wire _bank_mask_3_T_9; // @[frontend.scala:689:71] wire bank_mask_1_0; // @[frontend.scala:599:26] wire bank_mask_1_1; // @[frontend.scala:599:26] wire bank_mask_1_2; // @[frontend.scala:599:26] wire bank_mask_1_3; // @[frontend.scala:599:26] wire [31:0] bank_insts_1_0; // @[frontend.scala:600:26] wire [31:0] bank_insts_1_1; // @[frontend.scala:600:26] wire [31:0] bank_insts_1_2; // @[frontend.scala:600:26] wire [31:0] bank_insts_1_3; // @[frontend.scala:600:26] assign f3_ret_mask_4 = brsigs_4_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_4 = brsigs_4_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_4 = brsigs_4_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_4_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_4_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_4_target; // @[frontend.scala:613:24] wire brsigs_4_shadowable; // @[frontend.scala:613:24] wire [15:0] _inst0_T_1 = bank_data_1[15:0]; // @[frontend.scala:598:29, :615:34] wire [15:0] _inst0b_T = bank_data_1[15:0]; // @[frontend.scala:598:29, :615:34, :637:43] wire [31:0] inst0_1 = {_inst0_T_1, f3_prev_half}; // @[frontend.scala:587:28, :615:{24,34}] wire [31:0] inst1_1 = bank_data_1[31:0]; // @[frontend.scala:598:29, :616:30] wire [31:0] exp_inst0_1 = _exp_inst0_rvc_exp_1_io_rvc ? _exp_inst0_rvc_exp_1_io_out_bits : inst0_1; // @[frontend.scala:615:24] wire [31:0] exp_inst1_1 = _exp_inst1_rvc_exp_1_io_rvc ? _exp_inst1_rvc_exp_1_io_out_bits : inst1_1; // @[frontend.scala:616:30] wire [40:0] _GEN_33 = _GEN_16 + 41'h8; // @[frontend.scala:619:34] wire [40:0] _pc0_T_3; // @[frontend.scala:619:34] assign _pc0_T_3 = _GEN_33; // @[frontend.scala:619:34] wire [40:0] _pc1_T_1; // @[frontend.scala:620:34] assign _pc1_T_1 = _GEN_33; // @[frontend.scala:619:34, :620:34] wire [39:0] _pc0_T_4 = _pc0_T_3[39:0]; // @[frontend.scala:619:34] wire [40:0] _pc0_T_5 = {1'h0, _pc0_T_4} - 41'h2; // @[frontend.scala:619:{34,69}] wire [39:0] pc0_1 = _pc0_T_5[39:0]; // @[frontend.scala:619:69] wire [39:0] pc1_1 = _pc1_T_1[39:0]; // @[frontend.scala:620:34] wire [31:0] inst0b = {_inst0b_T, bank_insts_3[15:0]}; // @[frontend.scala:600:26, :637:{33,43}, :746:40] wire [31:0] exp_inst0b = _exp_inst0b_rvc_exp_io_rvc ? _exp_inst0b_rvc_exp_io_out_bits : inst0b; // @[frontend.scala:637:33] wire [31:0] _GEN_34 = _T_43 ? (f3_bank_mask[0] ? inst0b : inst0_1) : inst1_1; // @[frontend.scala:190:10, :615:24, :616:30, :629:34, :630:40, :637:33, :643:38, :644:44, :651:40, :724:58, :747:28] assign f3_fetch_bundle_insts_4 = _GEN_34; // @[frontend.scala:569:29, :629:34, :643:38, :651:40] assign bank_insts_1_0 = _GEN_34; // @[frontend.scala:600:26, :629:34, :643:38, :651:40] assign f3_fetch_bundle_exp_insts_4 = _T_43 ? (f3_bank_mask[0] ? exp_inst0b : exp_inst0_1) : exp_inst1_1; // @[frontend.scala:190:10, :569:29, :629:34, :632:40, :643:38, :646:44, :653:40, :724:58, :747:28] assign brsigs_4_shadowable = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_shadowable : _bpd_decoder0_1_io_out_shadowable) : _bpd_decoder1_1_io_out_shadowable; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_sfb_offset_valid = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_sfb_offset_valid : _bpd_decoder0_1_io_out_sfb_offset_valid) : _bpd_decoder1_1_io_out_sfb_offset_valid; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_sfb_offset_bits = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_sfb_offset_bits : _bpd_decoder0_1_io_out_sfb_offset_bits) : _bpd_decoder1_1_io_out_sfb_offset_bits; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_cfi_type = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_cfi_type : _bpd_decoder0_1_io_out_cfi_type) : _bpd_decoder1_1_io_out_cfi_type; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_target = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_target : _bpd_decoder0_1_io_out_target) : _bpd_decoder1_1_io_out_target; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_is_call = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_is_call : _bpd_decoder0_1_io_out_is_call) : _bpd_decoder1_1_io_out_is_call; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] assign brsigs_4_is_ret = _T_43 ? (f3_bank_mask[0] ? _bpd_decoder0b_io_out_is_ret : _bpd_decoder0_1_io_out_is_ret) : _bpd_decoder1_1_io_out_is_ret; // @[frontend.scala:190:10, :613:24, :622:34, :625:34, :629:34, :634:40, :639:39, :643:38, :647:44, :655:40, :724:58, :747:28] wire [1:0] _f3_is_rvc_4_T = bank_insts_1_0[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_20 = bank_insts_1_0[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_4_T_1 = _f3_is_rvc_4_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_4 = _f3_is_rvc_4_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_0_T_5 = _f3_io_deq_bits_mask[4]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_4_T = _f3_io_deq_bits_mask[4]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_0_T_6 = _f3_io_deq_valid & _bank_mask_0_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_0_T_7 = _bank_mask_0_T_6; // @[frontend.scala:689:{39,62}] wire _bank_mask_0_T_8 = ~_T_31; // @[frontend.scala:689:74, :744:39] assign _bank_mask_0_T_9 = _bank_mask_0_T_7 & _bank_mask_0_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_0 = _bank_mask_0_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_4_T_1 = _f3_io_deq_valid & _f3_mask_4_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_4_T_2 = _f3_mask_4_T_1; // @[frontend.scala:690:{39,62}] wire _f3_mask_4_T_3 = ~_T_31; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_4_T_4 = _f3_mask_4_T_2 & _f3_mask_4_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_4 = _f3_mask_4_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_35 = brsigs_4_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_4_T; // @[frontend.scala:691:43] assign _f3_targs_4_T = _GEN_35; // @[frontend.scala:691:43] wire _f3_redirects_4_T_1; // @[frontend.scala:732:56] assign _f3_redirects_4_T_1 = _GEN_35; // @[frontend.scala:691:43, :732:56] assign _f3_targs_4_T_1 = _f3_targs_4_T ? _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_bits : brsigs_4_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_4 = _f3_targs_4_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_36 = brsigs_4_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_4_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_4_T = _GEN_36; // @[frontend.scala:696:49] wire _f3_redirects_4_T; // @[frontend.scala:732:25] assign _f3_redirects_4_T = _GEN_36; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_4_T_1 = _f3_btb_mispredicts_4_T; // @[frontend.scala:696:{49,61}] wire _f3_btb_mispredicts_4_T_2 = _f3_btb_mispredicts_4_T_1 & _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_4_T_3 = _f3_bpd_resp_io_deq_bits_preds_4_predicted_pc_bits != brsigs_4_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_4_T_4 = _f3_btb_mispredicts_4_T_2 & _f3_btb_mispredicts_4_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_4 = _f3_btb_mispredicts_4_T_4; // @[frontend.scala:575:32, :697:61] wire _f3_npc_plus4_mask_4_T = ~f3_is_rvc_4; // @[frontend.scala:564:29, :703:9] wire _f3_npc_plus4_mask_4_T_1 = ~_T_43; // @[frontend.scala:703:26, :747:28] assign _f3_npc_plus4_mask_4_T_2 = _f3_npc_plus4_mask_4_T & _f3_npc_plus4_mask_4_T_1; // @[frontend.scala:703:{9,23,26}] assign f3_npc_plus4_mask_4 = _f3_npc_plus4_mask_4_T_2; // @[frontend.scala:574:31, :703:23] wire [7:0] _offset_from_aligned_pc_T_20 = {2'h0, brsigs_4_sfb_offset_bits} + 8'h8; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_21 = _offset_from_aligned_pc_T_20[6:0]; // @[frontend.scala:708:50] wire [1:0] _offset_from_aligned_pc_T_23 = {_offset_from_aligned_pc_T_22, 1'h0}; // @[frontend.scala:710:{12,31}] wire [7:0] _offset_from_aligned_pc_T_24 = {1'h0, _offset_from_aligned_pc_T_21} - {6'h0, _offset_from_aligned_pc_T_23}; // @[frontend.scala:708:50, :709:32, :710:12] wire [6:0] offset_from_aligned_pc_4 = _offset_from_aligned_pc_T_24[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_4; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_16 = offset_from_aligned_pc_4[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_17 = 32'h1 << _upper_mask_T_16; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_19 = {7'h0, _upper_mask_T_17} << _upper_mask_T_18; // @[OneHot.scala:58:35] assign upper_mask_4 = _upper_mask_T_19[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_4_T = f3_mask_4 & brsigs_4_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_4_T_2 = offset_from_aligned_pc_4 <= {1'h0, _f3_fetch_bundle_sfbs_4_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_4_T_3 = _f3_fetch_bundle_sfbs_4_T & _f3_fetch_bundle_sfbs_4_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_4 = _f3_fetch_bundle_sfbs_4_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_4_T_32 = {1'h0, upper_mask_4}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_33 = _f3_fetch_bundle_sfb_masks_4_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_4_T_34 = {upper_mask_4, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_35 = _f3_fetch_bundle_sfb_masks_4_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_4_T_36 = {1'h0, upper_mask_4, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_37 = _f3_fetch_bundle_sfb_masks_4_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_4_T_38 = {upper_mask_4, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_39 = _f3_fetch_bundle_sfb_masks_4_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_40 = {3'h0, upper_mask_4, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_41 = _f3_fetch_bundle_sfb_masks_4_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_42 = {2'h0, upper_mask_4, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_43 = _f3_fetch_bundle_sfb_masks_4_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_44 = {1'h0, upper_mask_4, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_45 = _f3_fetch_bundle_sfb_masks_4_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_4_T_46 = {upper_mask_4, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_47 = _f3_fetch_bundle_sfb_masks_4_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_48 = {7'h0, upper_mask_4, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_49 = _f3_fetch_bundle_sfb_masks_4_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_50 = {6'h0, upper_mask_4, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_51 = _f3_fetch_bundle_sfb_masks_4_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_52 = {5'h0, upper_mask_4, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_53 = _f3_fetch_bundle_sfb_masks_4_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_54 = {4'h0, upper_mask_4, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_55 = _f3_fetch_bundle_sfb_masks_4_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_56 = {3'h0, upper_mask_4, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_57 = _f3_fetch_bundle_sfb_masks_4_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_58 = {2'h0, upper_mask_4, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_59 = _f3_fetch_bundle_sfb_masks_4_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_60 = {1'h0, upper_mask_4, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_61 = _f3_fetch_bundle_sfb_masks_4_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_4_T_62 = {upper_mask_4, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_63 = _f3_fetch_bundle_sfb_masks_4_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_64 = _f3_fetch_bundle_sfb_masks_4_T_33 | _f3_fetch_bundle_sfb_masks_4_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_65 = _f3_fetch_bundle_sfb_masks_4_T_64 | _f3_fetch_bundle_sfb_masks_4_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_66 = _f3_fetch_bundle_sfb_masks_4_T_65 | _f3_fetch_bundle_sfb_masks_4_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_67 = _f3_fetch_bundle_sfb_masks_4_T_66 | _f3_fetch_bundle_sfb_masks_4_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_68 = _f3_fetch_bundle_sfb_masks_4_T_67 | _f3_fetch_bundle_sfb_masks_4_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_69 = _f3_fetch_bundle_sfb_masks_4_T_68 | _f3_fetch_bundle_sfb_masks_4_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_70 = _f3_fetch_bundle_sfb_masks_4_T_69 | _f3_fetch_bundle_sfb_masks_4_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_71 = _f3_fetch_bundle_sfb_masks_4_T_70 | _f3_fetch_bundle_sfb_masks_4_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_72 = _f3_fetch_bundle_sfb_masks_4_T_71 | _f3_fetch_bundle_sfb_masks_4_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_73 = _f3_fetch_bundle_sfb_masks_4_T_72 | _f3_fetch_bundle_sfb_masks_4_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_74 = _f3_fetch_bundle_sfb_masks_4_T_73 | _f3_fetch_bundle_sfb_masks_4_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_75 = _f3_fetch_bundle_sfb_masks_4_T_74 | _f3_fetch_bundle_sfb_masks_4_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_76 = _f3_fetch_bundle_sfb_masks_4_T_75 | _f3_fetch_bundle_sfb_masks_4_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_77 = _f3_fetch_bundle_sfb_masks_4_T_76 | _f3_fetch_bundle_sfb_masks_4_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_78 = _f3_fetch_bundle_sfb_masks_4_T_77 | _f3_fetch_bundle_sfb_masks_4_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_4_T_79 = ~_f3_fetch_bundle_sfb_masks_4_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_4_T_80 = _f3_fetch_bundle_sfb_masks_4_T_79 & 16'hFFE0; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_4 = _f3_fetch_bundle_sfb_masks_4_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_4_T_1 = _f3_fetch_bundle_shadowable_mask_4_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_4_T_2 = _f3_fetch_bundle_shadowable_mask_4_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_4_T_3 = ~_f3_fetch_bundle_shadowable_mask_4_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_4_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_5_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_6_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_7_T_4 = f3_bank_mask[1]; // @[frontend.scala:190:10, :724:58] wire _f3_fetch_bundle_shadowable_mask_4_T_5 = _f3_fetch_bundle_shadowable_mask_4_T_3 & _f3_fetch_bundle_shadowable_mask_4_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_4_T_6 = ~f3_mask_4; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_4_T_7 = brsigs_4_shadowable | _f3_fetch_bundle_shadowable_mask_4_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_4_T_8 = _f3_fetch_bundle_shadowable_mask_4_T_5 & _f3_fetch_bundle_shadowable_mask_4_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_4 = _f3_fetch_bundle_shadowable_mask_4_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_4 = offset_from_aligned_pc_4[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_4_T_2 = _f3_redirects_4_T | _f3_redirects_4_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_37 = brsigs_4_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_4_T_3; // @[frontend.scala:733:26] assign _f3_redirects_4_T_3 = _GEN_37; // @[frontend.scala:733:26] wire _f3_br_mask_4_T; // @[frontend.scala:736:56] assign _f3_br_mask_4_T = _GEN_37; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_4_T_4 = _f3_redirects_4_T_3 & _f3_bpd_resp_io_deq_bits_preds_4_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_4_T_5 = _f3_redirects_4_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_4_T_6 = _f3_redirects_4_T_2 | _f3_redirects_4_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_4_T_7 = f3_mask_4 & _f3_redirects_4_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_4 = _f3_redirects_4_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_4_T_1 = f3_mask_4 & _f3_br_mask_4_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_4 = _f3_br_mask_4_T_1; // @[frontend.scala:571:29, :736:37] wire _T_48 = _T_31 | f3_redirects_4; // @[frontend.scala:565:29, :744:39] wire _valid_T_25; // @[frontend.scala:675:38] wire valid_5; // @[frontend.scala:605:23] assign f3_ret_mask_5 = brsigs_5_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_5 = brsigs_5_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_5 = brsigs_5_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_5_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_5_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_5_target; // @[frontend.scala:613:24] wire brsigs_5_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_4; // @[frontend.scala:674:29] assign f3_fetch_bundle_insts_5 = inst_3; // @[frontend.scala:569:29, :660:24] assign bank_insts_1_1 = inst_3; // @[frontend.scala:600:26, :660:24] assign exp_inst_3 = _exp_inst_rvc_exp_3_io_rvc ? _exp_inst_rvc_exp_3_io_out_bits : inst_3; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_5 = exp_inst_3; // @[frontend.scala:569:29] wire [40:0] _pc_T_3 = _GEN_16 + 41'hA; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_3 = _pc_T_3[39:0]; // @[frontend.scala:662:32] assign _inst_T_4 = bank_data_1[47:16]; // @[frontend.scala:598:29, :674:29] assign inst_3 = _inst_T_4; // @[frontend.scala:660:24, :674:29] wire _valid_T_21 = _valid_T_20 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_22 = ~_valid_T_21; // @[frontend.scala:592:38, :675:59] wire _valid_T_23 = bank_mask_1_0 & _valid_T_22; // @[frontend.scala:599:26, :675:{56,59}] wire _valid_T_24 = ~_valid_T_23; // @[frontend.scala:675:{41,56}] assign _valid_T_25 = _T_43 | _valid_T_24; // @[frontend.scala:675:{38,41}, :747:28] assign valid_5 = _valid_T_25; // @[frontend.scala:605:23, :675:38] wire [1:0] _f3_is_rvc_5_T = bank_insts_1_1[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_26 = bank_insts_1_1[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_5_T_1 = _f3_is_rvc_5_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_5 = _f3_is_rvc_5_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_1_T_5 = _f3_io_deq_bits_mask[5]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_5_T = _f3_io_deq_bits_mask[5]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_1_T_6 = _f3_io_deq_valid & _bank_mask_1_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_1_T_7 = _bank_mask_1_T_6 & valid_5; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_1_T_8 = ~_T_48; // @[frontend.scala:689:74, :744:39] assign _bank_mask_1_T_9 = _bank_mask_1_T_7 & _bank_mask_1_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_1 = _bank_mask_1_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_5_T_1 = _f3_io_deq_valid & _f3_mask_5_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_5_T_2 = _f3_mask_5_T_1 & valid_5; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_5_T_3 = ~_T_48; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_5_T_4 = _f3_mask_5_T_2 & _f3_mask_5_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_5 = _f3_mask_5_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_38 = brsigs_5_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_5_T; // @[frontend.scala:691:43] assign _f3_targs_5_T = _GEN_38; // @[frontend.scala:691:43] wire _f3_redirects_5_T_1; // @[frontend.scala:732:56] assign _f3_redirects_5_T_1 = _GEN_38; // @[frontend.scala:691:43, :732:56] assign _f3_targs_5_T_1 = _f3_targs_5_T ? _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_bits : brsigs_5_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_5 = _f3_targs_5_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_39 = brsigs_5_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_5_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_5_T = _GEN_39; // @[frontend.scala:696:49] wire _f3_redirects_5_T; // @[frontend.scala:732:25] assign _f3_redirects_5_T = _GEN_39; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_5_T_1 = _f3_btb_mispredicts_5_T & valid_5; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_5_T_2 = _f3_btb_mispredicts_5_T_1 & _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_5_T_3 = _f3_bpd_resp_io_deq_bits_preds_5_predicted_pc_bits != brsigs_5_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_5_T_4 = _f3_btb_mispredicts_5_T_2 & _f3_btb_mispredicts_5_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_5 = _f3_btb_mispredicts_5_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_5_T = ~f3_is_rvc_5; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_5 = _f3_npc_plus4_mask_5_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_25 = {2'h0, brsigs_5_sfb_offset_bits} + 8'hA; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_26 = _offset_from_aligned_pc_T_25[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_29 = {1'h0, _offset_from_aligned_pc_T_26}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_5 = _offset_from_aligned_pc_T_29[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_5; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_20 = offset_from_aligned_pc_5[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_21 = 32'h1 << _upper_mask_T_20; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_23 = {7'h0, _upper_mask_T_21} << _upper_mask_T_22; // @[OneHot.scala:58:35] assign upper_mask_5 = _upper_mask_T_23[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_5_T = f3_mask_5 & brsigs_5_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_5_T_2 = offset_from_aligned_pc_5 <= {1'h0, _f3_fetch_bundle_sfbs_5_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_5_T_3 = _f3_fetch_bundle_sfbs_5_T & _f3_fetch_bundle_sfbs_5_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_5 = _f3_fetch_bundle_sfbs_5_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_5_T_32 = {1'h0, upper_mask_5}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_33 = _f3_fetch_bundle_sfb_masks_5_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_5_T_34 = {upper_mask_5, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_35 = _f3_fetch_bundle_sfb_masks_5_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_5_T_36 = {1'h0, upper_mask_5, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_37 = _f3_fetch_bundle_sfb_masks_5_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_5_T_38 = {upper_mask_5, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_39 = _f3_fetch_bundle_sfb_masks_5_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_40 = {3'h0, upper_mask_5, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_41 = _f3_fetch_bundle_sfb_masks_5_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_42 = {2'h0, upper_mask_5, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_43 = _f3_fetch_bundle_sfb_masks_5_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_44 = {1'h0, upper_mask_5, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_45 = _f3_fetch_bundle_sfb_masks_5_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_5_T_46 = {upper_mask_5, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_47 = _f3_fetch_bundle_sfb_masks_5_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_48 = {7'h0, upper_mask_5, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_49 = _f3_fetch_bundle_sfb_masks_5_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_50 = {6'h0, upper_mask_5, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_51 = _f3_fetch_bundle_sfb_masks_5_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_52 = {5'h0, upper_mask_5, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_53 = _f3_fetch_bundle_sfb_masks_5_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_54 = {4'h0, upper_mask_5, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_55 = _f3_fetch_bundle_sfb_masks_5_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_56 = {3'h0, upper_mask_5, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_57 = _f3_fetch_bundle_sfb_masks_5_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_58 = {2'h0, upper_mask_5, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_59 = _f3_fetch_bundle_sfb_masks_5_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_60 = {1'h0, upper_mask_5, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_61 = _f3_fetch_bundle_sfb_masks_5_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_5_T_62 = {upper_mask_5, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_63 = _f3_fetch_bundle_sfb_masks_5_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_64 = _f3_fetch_bundle_sfb_masks_5_T_33 | _f3_fetch_bundle_sfb_masks_5_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_65 = _f3_fetch_bundle_sfb_masks_5_T_64 | _f3_fetch_bundle_sfb_masks_5_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_66 = _f3_fetch_bundle_sfb_masks_5_T_65 | _f3_fetch_bundle_sfb_masks_5_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_67 = _f3_fetch_bundle_sfb_masks_5_T_66 | _f3_fetch_bundle_sfb_masks_5_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_68 = _f3_fetch_bundle_sfb_masks_5_T_67 | _f3_fetch_bundle_sfb_masks_5_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_69 = _f3_fetch_bundle_sfb_masks_5_T_68 | _f3_fetch_bundle_sfb_masks_5_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_70 = _f3_fetch_bundle_sfb_masks_5_T_69 | _f3_fetch_bundle_sfb_masks_5_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_71 = _f3_fetch_bundle_sfb_masks_5_T_70 | _f3_fetch_bundle_sfb_masks_5_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_72 = _f3_fetch_bundle_sfb_masks_5_T_71 | _f3_fetch_bundle_sfb_masks_5_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_73 = _f3_fetch_bundle_sfb_masks_5_T_72 | _f3_fetch_bundle_sfb_masks_5_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_74 = _f3_fetch_bundle_sfb_masks_5_T_73 | _f3_fetch_bundle_sfb_masks_5_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_75 = _f3_fetch_bundle_sfb_masks_5_T_74 | _f3_fetch_bundle_sfb_masks_5_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_76 = _f3_fetch_bundle_sfb_masks_5_T_75 | _f3_fetch_bundle_sfb_masks_5_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_77 = _f3_fetch_bundle_sfb_masks_5_T_76 | _f3_fetch_bundle_sfb_masks_5_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_78 = _f3_fetch_bundle_sfb_masks_5_T_77 | _f3_fetch_bundle_sfb_masks_5_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_5_T_79 = ~_f3_fetch_bundle_sfb_masks_5_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_5_T_80 = _f3_fetch_bundle_sfb_masks_5_T_79 & 16'hFFC0; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_5 = _f3_fetch_bundle_sfb_masks_5_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_5_T_1 = _f3_fetch_bundle_shadowable_mask_5_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_5_T_2 = _f3_fetch_bundle_shadowable_mask_5_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_5_T_3 = ~_f3_fetch_bundle_shadowable_mask_5_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_5_T_5 = _f3_fetch_bundle_shadowable_mask_5_T_3 & _f3_fetch_bundle_shadowable_mask_5_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_5_T_6 = ~f3_mask_5; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_5_T_7 = brsigs_5_shadowable | _f3_fetch_bundle_shadowable_mask_5_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_5_T_8 = _f3_fetch_bundle_shadowable_mask_5_T_5 & _f3_fetch_bundle_shadowable_mask_5_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_5 = _f3_fetch_bundle_shadowable_mask_5_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_5 = offset_from_aligned_pc_5[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_5_T_2 = _f3_redirects_5_T | _f3_redirects_5_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_40 = brsigs_5_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_5_T_3; // @[frontend.scala:733:26] assign _f3_redirects_5_T_3 = _GEN_40; // @[frontend.scala:733:26] wire _f3_br_mask_5_T; // @[frontend.scala:736:56] assign _f3_br_mask_5_T = _GEN_40; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_5_T_4 = _f3_redirects_5_T_3 & _f3_bpd_resp_io_deq_bits_preds_5_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_5_T_5 = _f3_redirects_5_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_5_T_6 = _f3_redirects_5_T_2 | _f3_redirects_5_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_5_T_7 = f3_mask_5 & _f3_redirects_5_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_5 = _f3_redirects_5_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_5_T_1 = f3_mask_5 & _f3_br_mask_5_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_5 = _f3_br_mask_5_T_1; // @[frontend.scala:571:29, :736:37] wire _T_49 = _T_48 | f3_redirects_5; // @[frontend.scala:565:29, :744:39] wire _valid_T_30; // @[frontend.scala:682:20] wire valid_6; // @[frontend.scala:605:23] assign f3_ret_mask_6 = brsigs_6_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_6 = brsigs_6_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_6 = brsigs_6_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_6_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_6_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_6_target; // @[frontend.scala:613:24] wire brsigs_6_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_5; // @[frontend.scala:681:29] assign f3_fetch_bundle_insts_6 = inst_4; // @[frontend.scala:569:29, :660:24] assign bank_insts_1_2 = inst_4; // @[frontend.scala:600:26, :660:24] assign exp_inst_4 = _exp_inst_rvc_exp_4_io_rvc ? _exp_inst_rvc_exp_4_io_out_bits : inst_4; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_6 = exp_inst_4; // @[frontend.scala:569:29] wire [40:0] _pc_T_4 = _GEN_16 + 41'hC; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_4 = _pc_T_4[39:0]; // @[frontend.scala:662:32] assign _inst_T_5 = bank_data_1[63:32]; // @[frontend.scala:598:29, :681:29] assign inst_4 = _inst_T_5; // @[frontend.scala:660:24, :681:29] wire _valid_T_27 = _valid_T_26 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_28 = ~_valid_T_27; // @[frontend.scala:592:38, :682:40] wire _valid_T_29 = bank_mask_1_1 & _valid_T_28; // @[frontend.scala:599:26, :682:{37,40}] assign _valid_T_30 = ~_valid_T_29; // @[frontend.scala:682:{20,37}] assign valid_6 = _valid_T_30; // @[frontend.scala:605:23, :682:20] wire [1:0] _f3_is_rvc_6_T = bank_insts_1_2[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_31 = bank_insts_1_2[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_6_T_1 = _f3_is_rvc_6_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_6 = _f3_is_rvc_6_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_2_T_5 = _f3_io_deq_bits_mask[6]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_6_T = _f3_io_deq_bits_mask[6]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_2_T_6 = _f3_io_deq_valid & _bank_mask_2_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_2_T_7 = _bank_mask_2_T_6 & valid_6; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_2_T_8 = ~_T_49; // @[frontend.scala:689:74, :744:39] assign _bank_mask_2_T_9 = _bank_mask_2_T_7 & _bank_mask_2_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_2 = _bank_mask_2_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_6_T_1 = _f3_io_deq_valid & _f3_mask_6_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_6_T_2 = _f3_mask_6_T_1 & valid_6; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_6_T_3 = ~_T_49; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_6_T_4 = _f3_mask_6_T_2 & _f3_mask_6_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_6 = _f3_mask_6_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_41 = brsigs_6_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_6_T; // @[frontend.scala:691:43] assign _f3_targs_6_T = _GEN_41; // @[frontend.scala:691:43] wire _f3_redirects_6_T_1; // @[frontend.scala:732:56] assign _f3_redirects_6_T_1 = _GEN_41; // @[frontend.scala:691:43, :732:56] assign _f3_targs_6_T_1 = _f3_targs_6_T ? _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_bits : brsigs_6_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_6 = _f3_targs_6_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_42 = brsigs_6_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_6_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_6_T = _GEN_42; // @[frontend.scala:696:49] wire _f3_redirects_6_T; // @[frontend.scala:732:25] assign _f3_redirects_6_T = _GEN_42; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_6_T_1 = _f3_btb_mispredicts_6_T & valid_6; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_6_T_2 = _f3_btb_mispredicts_6_T_1 & _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_6_T_3 = _f3_bpd_resp_io_deq_bits_preds_6_predicted_pc_bits != brsigs_6_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_6_T_4 = _f3_btb_mispredicts_6_T_2 & _f3_btb_mispredicts_6_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_6 = _f3_btb_mispredicts_6_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_6_T = ~f3_is_rvc_6; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_6 = _f3_npc_plus4_mask_6_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_30 = {2'h0, brsigs_6_sfb_offset_bits} + 8'hC; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_31 = _offset_from_aligned_pc_T_30[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_34 = {1'h0, _offset_from_aligned_pc_T_31}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_6 = _offset_from_aligned_pc_T_34[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_6; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_24 = offset_from_aligned_pc_6[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_25 = 32'h1 << _upper_mask_T_24; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_27 = {7'h0, _upper_mask_T_25} << _upper_mask_T_26; // @[OneHot.scala:58:35] assign upper_mask_6 = _upper_mask_T_27[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_6_T = f3_mask_6 & brsigs_6_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_6_T_2 = offset_from_aligned_pc_6 <= {1'h0, _f3_fetch_bundle_sfbs_6_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_6_T_3 = _f3_fetch_bundle_sfbs_6_T & _f3_fetch_bundle_sfbs_6_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_6 = _f3_fetch_bundle_sfbs_6_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_6_T_32 = {1'h0, upper_mask_6}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_33 = _f3_fetch_bundle_sfb_masks_6_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_6_T_34 = {upper_mask_6, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_35 = _f3_fetch_bundle_sfb_masks_6_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_6_T_36 = {1'h0, upper_mask_6, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_37 = _f3_fetch_bundle_sfb_masks_6_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_6_T_38 = {upper_mask_6, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_39 = _f3_fetch_bundle_sfb_masks_6_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_40 = {3'h0, upper_mask_6, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_41 = _f3_fetch_bundle_sfb_masks_6_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_42 = {2'h0, upper_mask_6, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_43 = _f3_fetch_bundle_sfb_masks_6_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_44 = {1'h0, upper_mask_6, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_45 = _f3_fetch_bundle_sfb_masks_6_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_6_T_46 = {upper_mask_6, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_47 = _f3_fetch_bundle_sfb_masks_6_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_48 = {7'h0, upper_mask_6, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_49 = _f3_fetch_bundle_sfb_masks_6_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_50 = {6'h0, upper_mask_6, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_51 = _f3_fetch_bundle_sfb_masks_6_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_52 = {5'h0, upper_mask_6, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_53 = _f3_fetch_bundle_sfb_masks_6_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_54 = {4'h0, upper_mask_6, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_55 = _f3_fetch_bundle_sfb_masks_6_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_56 = {3'h0, upper_mask_6, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_57 = _f3_fetch_bundle_sfb_masks_6_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_58 = {2'h0, upper_mask_6, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_59 = _f3_fetch_bundle_sfb_masks_6_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_60 = {1'h0, upper_mask_6, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_61 = _f3_fetch_bundle_sfb_masks_6_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_6_T_62 = {upper_mask_6, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_63 = _f3_fetch_bundle_sfb_masks_6_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_64 = _f3_fetch_bundle_sfb_masks_6_T_33 | _f3_fetch_bundle_sfb_masks_6_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_65 = _f3_fetch_bundle_sfb_masks_6_T_64 | _f3_fetch_bundle_sfb_masks_6_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_66 = _f3_fetch_bundle_sfb_masks_6_T_65 | _f3_fetch_bundle_sfb_masks_6_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_67 = _f3_fetch_bundle_sfb_masks_6_T_66 | _f3_fetch_bundle_sfb_masks_6_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_68 = _f3_fetch_bundle_sfb_masks_6_T_67 | _f3_fetch_bundle_sfb_masks_6_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_69 = _f3_fetch_bundle_sfb_masks_6_T_68 | _f3_fetch_bundle_sfb_masks_6_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_70 = _f3_fetch_bundle_sfb_masks_6_T_69 | _f3_fetch_bundle_sfb_masks_6_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_71 = _f3_fetch_bundle_sfb_masks_6_T_70 | _f3_fetch_bundle_sfb_masks_6_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_72 = _f3_fetch_bundle_sfb_masks_6_T_71 | _f3_fetch_bundle_sfb_masks_6_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_73 = _f3_fetch_bundle_sfb_masks_6_T_72 | _f3_fetch_bundle_sfb_masks_6_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_74 = _f3_fetch_bundle_sfb_masks_6_T_73 | _f3_fetch_bundle_sfb_masks_6_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_75 = _f3_fetch_bundle_sfb_masks_6_T_74 | _f3_fetch_bundle_sfb_masks_6_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_76 = _f3_fetch_bundle_sfb_masks_6_T_75 | _f3_fetch_bundle_sfb_masks_6_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_77 = _f3_fetch_bundle_sfb_masks_6_T_76 | _f3_fetch_bundle_sfb_masks_6_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_78 = _f3_fetch_bundle_sfb_masks_6_T_77 | _f3_fetch_bundle_sfb_masks_6_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_6_T_79 = ~_f3_fetch_bundle_sfb_masks_6_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_6_T_80 = _f3_fetch_bundle_sfb_masks_6_T_79 & 16'hFF80; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_6 = _f3_fetch_bundle_sfb_masks_6_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_6_T_1 = _f3_fetch_bundle_shadowable_mask_6_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_6_T_2 = _f3_fetch_bundle_shadowable_mask_6_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_6_T_3 = ~_f3_fetch_bundle_shadowable_mask_6_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_6_T_5 = _f3_fetch_bundle_shadowable_mask_6_T_3 & _f3_fetch_bundle_shadowable_mask_6_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_6_T_6 = ~f3_mask_6; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_6_T_7 = brsigs_6_shadowable | _f3_fetch_bundle_shadowable_mask_6_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_6_T_8 = _f3_fetch_bundle_shadowable_mask_6_T_5 & _f3_fetch_bundle_shadowable_mask_6_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_6 = _f3_fetch_bundle_shadowable_mask_6_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_6 = offset_from_aligned_pc_6[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_6_T_2 = _f3_redirects_6_T | _f3_redirects_6_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_43 = brsigs_6_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_6_T_3; // @[frontend.scala:733:26] assign _f3_redirects_6_T_3 = _GEN_43; // @[frontend.scala:733:26] wire _f3_br_mask_6_T; // @[frontend.scala:736:56] assign _f3_br_mask_6_T = _GEN_43; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_6_T_4 = _f3_redirects_6_T_3 & _f3_bpd_resp_io_deq_bits_preds_6_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_6_T_5 = _f3_redirects_6_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_6_T_6 = _f3_redirects_6_T_2 | _f3_redirects_6_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_6_T_7 = f3_mask_6 & _f3_redirects_6_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_6 = _f3_redirects_6_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_6_T_1 = f3_mask_6 & _f3_br_mask_6_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_6 = _f3_br_mask_6_T_1; // @[frontend.scala:571:29, :736:37] wire _T_50 = _T_49 | f3_redirects_6; // @[frontend.scala:565:29, :744:39] wire _valid_T_39; // @[frontend.scala:678:20] wire valid_7; // @[frontend.scala:605:23] assign f3_ret_mask_7 = brsigs_7_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_7 = brsigs_7_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_7 = brsigs_7_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_7_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_7_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_7_target; // @[frontend.scala:613:24] wire brsigs_7_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_7; // @[frontend.scala:677:23] assign f3_fetch_bundle_insts_7 = inst_5; // @[frontend.scala:569:29, :660:24] assign bank_insts_1_3 = inst_5; // @[frontend.scala:600:26, :660:24] assign exp_inst_5 = _exp_inst_rvc_exp_5_io_rvc ? _exp_inst_rvc_exp_5_io_out_bits : inst_5; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_7 = exp_inst_5; // @[frontend.scala:569:29] wire [40:0] _pc_T_5 = _GEN_16 + 41'hE; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_5 = _pc_T_5[39:0]; // @[frontend.scala:662:32] wire [15:0] _inst_T_6 = bank_data_1[63:48]; // @[frontend.scala:598:29, :677:44] assign _inst_T_7 = {16'h0, _inst_T_6}; // @[frontend.scala:677:{23,44}] assign inst_5 = _inst_T_7; // @[frontend.scala:660:24, :677:23] wire _valid_T_32 = _valid_T_31 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_33 = ~_valid_T_32; // @[frontend.scala:592:38, :678:41] wire _valid_T_34 = bank_mask_1_2 & _valid_T_33; // @[frontend.scala:599:26, :678:{38,41}] wire [1:0] _valid_T_35 = inst_5[1:0]; // @[frontend.scala:592:32, :660:24] wire _valid_T_36 = _valid_T_35 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_37 = ~_valid_T_36; // @[frontend.scala:592:38, :679:13] wire _valid_T_38 = _valid_T_34 | _valid_T_37; // @[frontend.scala:678:{38,66}, :679:13] assign _valid_T_39 = ~_valid_T_38; // @[frontend.scala:678:{20,66}] assign valid_7 = _valid_T_39; // @[frontend.scala:605:23, :678:20] wire [1:0] _f3_is_rvc_7_T = bank_insts_1_3[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_7_T_1 = _f3_is_rvc_7_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_7 = _f3_is_rvc_7_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_3_T_5 = _f3_io_deq_bits_mask[7]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_7_T = _f3_io_deq_bits_mask[7]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_3_T_6 = _f3_io_deq_valid & _bank_mask_3_T_5; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_3_T_7 = _bank_mask_3_T_6 & valid_7; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_3_T_8 = ~_T_50; // @[frontend.scala:689:74, :744:39] assign _bank_mask_3_T_9 = _bank_mask_3_T_7 & _bank_mask_3_T_8; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1_3 = _bank_mask_3_T_9; // @[frontend.scala:599:26, :689:71] wire _f3_mask_7_T_1 = _f3_io_deq_valid & _f3_mask_7_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_7_T_2 = _f3_mask_7_T_1 & valid_7; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_7_T_3 = ~_T_50; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_7_T_4 = _f3_mask_7_T_2 & _f3_mask_7_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_7 = _f3_mask_7_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_44 = brsigs_7_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_7_T; // @[frontend.scala:691:43] assign _f3_targs_7_T = _GEN_44; // @[frontend.scala:691:43] wire _f3_redirects_7_T_1; // @[frontend.scala:732:56] assign _f3_redirects_7_T_1 = _GEN_44; // @[frontend.scala:691:43, :732:56] assign _f3_targs_7_T_1 = _f3_targs_7_T ? _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_bits : brsigs_7_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_7 = _f3_targs_7_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_45 = brsigs_7_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_7_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_7_T = _GEN_45; // @[frontend.scala:696:49] wire _f3_redirects_7_T; // @[frontend.scala:732:25] assign _f3_redirects_7_T = _GEN_45; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_7_T_1 = _f3_btb_mispredicts_7_T & valid_7; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_7_T_2 = _f3_btb_mispredicts_7_T_1 & _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_7_T_3 = _f3_bpd_resp_io_deq_bits_preds_7_predicted_pc_bits != brsigs_7_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_7_T_4 = _f3_btb_mispredicts_7_T_2 & _f3_btb_mispredicts_7_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_7 = _f3_btb_mispredicts_7_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_7_T = ~f3_is_rvc_7; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_7 = _f3_npc_plus4_mask_7_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_35 = {2'h0, brsigs_7_sfb_offset_bits} + 8'hE; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_36 = _offset_from_aligned_pc_T_35[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_39 = {1'h0, _offset_from_aligned_pc_T_36}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_7 = _offset_from_aligned_pc_T_39[6:0]; // @[frontend.scala:709:32] wire [15:0] upper_mask_7; // @[frontend.scala:713:28] wire [4:0] _upper_mask_T_28 = offset_from_aligned_pc_7[5:1]; // @[frontend.scala:709:32, :715:52] wire [31:0] _upper_mask_T_29 = 32'h1 << _upper_mask_T_28; // @[OneHot.scala:58:35] wire [38:0] _upper_mask_T_31 = {7'h0, _upper_mask_T_29} << _upper_mask_T_30; // @[OneHot.scala:58:35] assign upper_mask_7 = _upper_mask_T_31[15:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_7_T = f3_mask_7 & brsigs_7_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_7_T_2 = offset_from_aligned_pc_7 <= {1'h0, _f3_fetch_bundle_sfbs_7_T_1}; // @[frontend.scala:709:32, :720:{33,39}] assign _f3_fetch_bundle_sfbs_7_T_3 = _f3_fetch_bundle_sfbs_7_T & _f3_fetch_bundle_sfbs_7_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_7 = _f3_fetch_bundle_sfbs_7_T_3; // @[frontend.scala:569:29, :719:33] wire [16:0] _f3_fetch_bundle_sfb_masks_7_T_32 = {1'h0, upper_mask_7}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_33 = _f3_fetch_bundle_sfb_masks_7_T_32[15:0]; // @[util.scala:384:{30,37}] wire [16:0] _f3_fetch_bundle_sfb_masks_7_T_34 = {upper_mask_7, 1'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_35 = _f3_fetch_bundle_sfb_masks_7_T_34[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_7_T_36 = {1'h0, upper_mask_7, 2'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_37 = _f3_fetch_bundle_sfb_masks_7_T_36[15:0]; // @[util.scala:384:{30,37}] wire [18:0] _f3_fetch_bundle_sfb_masks_7_T_38 = {upper_mask_7, 3'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_39 = _f3_fetch_bundle_sfb_masks_7_T_38[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_40 = {3'h0, upper_mask_7, 4'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_41 = _f3_fetch_bundle_sfb_masks_7_T_40[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_42 = {2'h0, upper_mask_7, 5'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_43 = _f3_fetch_bundle_sfb_masks_7_T_42[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_44 = {1'h0, upper_mask_7, 6'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_45 = _f3_fetch_bundle_sfb_masks_7_T_44[15:0]; // @[util.scala:384:{30,37}] wire [22:0] _f3_fetch_bundle_sfb_masks_7_T_46 = {upper_mask_7, 7'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_47 = _f3_fetch_bundle_sfb_masks_7_T_46[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_48 = {7'h0, upper_mask_7, 8'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_49 = _f3_fetch_bundle_sfb_masks_7_T_48[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_50 = {6'h0, upper_mask_7, 9'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_51 = _f3_fetch_bundle_sfb_masks_7_T_50[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_52 = {5'h0, upper_mask_7, 10'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_53 = _f3_fetch_bundle_sfb_masks_7_T_52[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_54 = {4'h0, upper_mask_7, 11'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_55 = _f3_fetch_bundle_sfb_masks_7_T_54[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_56 = {3'h0, upper_mask_7, 12'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_57 = _f3_fetch_bundle_sfb_masks_7_T_56[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_58 = {2'h0, upper_mask_7, 13'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_59 = _f3_fetch_bundle_sfb_masks_7_T_58[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_60 = {1'h0, upper_mask_7, 14'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_61 = _f3_fetch_bundle_sfb_masks_7_T_60[15:0]; // @[util.scala:384:{30,37}] wire [30:0] _f3_fetch_bundle_sfb_masks_7_T_62 = {upper_mask_7, 15'h0}; // @[util.scala:384:30] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_63 = _f3_fetch_bundle_sfb_masks_7_T_62[15:0]; // @[util.scala:384:{30,37}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_64 = _f3_fetch_bundle_sfb_masks_7_T_33 | _f3_fetch_bundle_sfb_masks_7_T_35; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_65 = _f3_fetch_bundle_sfb_masks_7_T_64 | _f3_fetch_bundle_sfb_masks_7_T_37; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_66 = _f3_fetch_bundle_sfb_masks_7_T_65 | _f3_fetch_bundle_sfb_masks_7_T_39; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_67 = _f3_fetch_bundle_sfb_masks_7_T_66 | _f3_fetch_bundle_sfb_masks_7_T_41; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_68 = _f3_fetch_bundle_sfb_masks_7_T_67 | _f3_fetch_bundle_sfb_masks_7_T_43; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_69 = _f3_fetch_bundle_sfb_masks_7_T_68 | _f3_fetch_bundle_sfb_masks_7_T_45; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_70 = _f3_fetch_bundle_sfb_masks_7_T_69 | _f3_fetch_bundle_sfb_masks_7_T_47; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_71 = _f3_fetch_bundle_sfb_masks_7_T_70 | _f3_fetch_bundle_sfb_masks_7_T_49; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_72 = _f3_fetch_bundle_sfb_masks_7_T_71 | _f3_fetch_bundle_sfb_masks_7_T_51; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_73 = _f3_fetch_bundle_sfb_masks_7_T_72 | _f3_fetch_bundle_sfb_masks_7_T_53; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_74 = _f3_fetch_bundle_sfb_masks_7_T_73 | _f3_fetch_bundle_sfb_masks_7_T_55; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_75 = _f3_fetch_bundle_sfb_masks_7_T_74 | _f3_fetch_bundle_sfb_masks_7_T_57; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_76 = _f3_fetch_bundle_sfb_masks_7_T_75 | _f3_fetch_bundle_sfb_masks_7_T_59; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_77 = _f3_fetch_bundle_sfb_masks_7_T_76 | _f3_fetch_bundle_sfb_masks_7_T_61; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_78 = _f3_fetch_bundle_sfb_masks_7_T_77 | _f3_fetch_bundle_sfb_masks_7_T_63; // @[util.scala:384:{37,54}] wire [15:0] _f3_fetch_bundle_sfb_masks_7_T_79 = ~_f3_fetch_bundle_sfb_masks_7_T_78; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_7_T_80 = _f3_fetch_bundle_sfb_masks_7_T_79 & 16'hFF00; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_7 = _f3_fetch_bundle_sfb_masks_7_T_80; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_7_T_1 = _f3_fetch_bundle_shadowable_mask_7_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_7_T_2 = _f3_fetch_bundle_shadowable_mask_7_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_7_T_3 = ~_f3_fetch_bundle_shadowable_mask_7_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_7_T_5 = _f3_fetch_bundle_shadowable_mask_7_T_3 & _f3_fetch_bundle_shadowable_mask_7_T_4; // @[frontend.scala:723:{46,143}, :724:58] wire _f3_fetch_bundle_shadowable_mask_7_T_6 = ~f3_mask_7; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_7_T_7 = brsigs_7_shadowable | _f3_fetch_bundle_shadowable_mask_7_T_6; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_7_T_8 = _f3_fetch_bundle_shadowable_mask_7_T_5 & _f3_fetch_bundle_shadowable_mask_7_T_7; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_7 = _f3_fetch_bundle_shadowable_mask_7_T_8; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_7 = offset_from_aligned_pc_7[4:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_7_T_2 = _f3_redirects_7_T | _f3_redirects_7_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_46 = brsigs_7_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_7_T_3; // @[frontend.scala:733:26] assign _f3_redirects_7_T_3 = _GEN_46; // @[frontend.scala:733:26] wire _f3_br_mask_7_T; // @[frontend.scala:736:56] assign _f3_br_mask_7_T = _GEN_46; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_7_T_4 = _f3_redirects_7_T_3 & _f3_bpd_resp_io_deq_bits_preds_7_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_7_T_5 = _f3_redirects_7_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_7_T_6 = _f3_redirects_7_T_2 | _f3_redirects_7_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_7_T_7 = f3_mask_7 & _f3_redirects_7_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_7 = _f3_redirects_7_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_7_T_1 = f3_mask_7 & _f3_br_mask_7_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_7 = _f3_br_mask_7_T_1; // @[frontend.scala:571:29, :736:37] assign f3_fetch_bundle_end_half_valid = f3_bank_mask[1] ? ~(bank_mask_1_2 & (&(bank_insts_1_2[1:0]))) & (&(bank_insts_1_3[1:0])) : _T_43; // @[frontend.scala:190:10, :569:29, :592:{32,38}, :599:26, :600:26, :724:58, :746:40, :747:28, :748:{8,33,69}] assign f3_fetch_bundle_end_half_bits = f3_bank_mask[1] ? bank_insts_1_3[15:0] : f3_bank_mask[0] ? bank_insts_3[15:0] : f3_prev_half; // @[frontend.scala:190:10, :569:29, :587:28, :600:26, :724:58, :746:40, :750:28] wire [7:0][2:0] _GEN_47 = {{f3_cfi_types_7}, {f3_cfi_types_6}, {f3_cfi_types_5}, {f3_cfi_types_4}, {f3_cfi_types_3}, {f3_cfi_types_2}, {f3_cfi_types_1}, {f3_cfi_types_0}}; // @[frontend.scala:567:29, :755:33] assign f3_fetch_bundle_cfi_type = _GEN_47[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :755:33] wire [7:0] _GEN_48 = {{f3_call_mask_7}, {f3_call_mask_6}, {f3_call_mask_5}, {f3_call_mask_4}, {f3_call_mask_3}, {f3_call_mask_2}, {f3_call_mask_1}, {f3_call_mask_0}}; // @[frontend.scala:572:29, :756:33] assign f3_fetch_bundle_cfi_is_call = _GEN_48[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :756:33] wire [7:0] _GEN_49 = {{f3_ret_mask_7}, {f3_ret_mask_6}, {f3_ret_mask_5}, {f3_ret_mask_4}, {f3_ret_mask_3}, {f3_ret_mask_2}, {f3_ret_mask_1}, {f3_ret_mask_0}}; // @[frontend.scala:573:29, :757:33] assign f3_fetch_bundle_cfi_is_ret = _GEN_49[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :757:33] wire [7:0] _GEN_50 = {{f3_npc_plus4_mask_7}, {f3_npc_plus4_mask_6}, {f3_npc_plus4_mask_5}, {f3_npc_plus4_mask_4}, {f3_npc_plus4_mask_3}, {f3_npc_plus4_mask_2}, {f3_npc_plus4_mask_1}, {f3_npc_plus4_mask_0}}; // @[frontend.scala:574:31, :758:33] assign f3_fetch_bundle_cfi_npc_plus4 = _GEN_50[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :758:33] wire _f4_btb_corrections_io_enq_valid_T = f4_ready & _f3_io_deq_valid; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s7k4z3c : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_40 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a32d128s7k4z3c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a32d128s7k4z3c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready connect nodeIn.b, nodeOut.b connect nodeOut.c, nodeIn.c connect nodeOut.e, nodeIn.e

module TLBuffer_a32d128s7k4z3c( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [127:0] auto_in_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] nodeIn_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [15:0] auto_in_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] nodeIn_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [6:0] auto_in_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [6:0] auto_out_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [6:0] nodeIn_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [6:0] nodeOut_b_bits_source = 7'h40; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_out_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeOut_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign nodeOut_c_valid = nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_opcode = nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_param = nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_size = nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_source = nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_address = nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_data = nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_c_bits_corrupt = nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign nodeOut_e_valid = nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_e_bits_sink = nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_param = nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_address = nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_c_ready = nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a32d128s7k4z3c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a32d128s7k4z3c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NBDTLB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}[1], miss_rdy : UInt<1>, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} reg sectored_entries : { level : UInt<2>, tag : UInt<27>, data : UInt<34>[4], valid : UInt<1>[4]}[2], clock reg superpage_entries : { level : UInt<2>, tag : UInt<27>, data : UInt<34>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag : UInt<27>, data : UInt<34>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<1>, clock reg r_sectored_hit_addr : UInt<1>, clock reg r_sectored_hit : UInt<1>, clock node priv_s = bits(io.ptw.status.dprv, 0, 0) node priv_uses_vm = leq(io.ptw.status.dprv, UInt<1>(0h1)) node _vm_enabled_T = bits(io.ptw.ptbr.mode, 3, 3) node _vm_enabled_T_1 = and(UInt<1>(0h1), _vm_enabled_T) node _vm_enabled_T_2 = and(_vm_enabled_T_1, priv_uses_vm) node _vm_enabled_T_3 = eq(io.req[0].bits.passthrough, UInt<1>(0h0)) node _vm_enabled_T_4 = and(_vm_enabled_T_2, _vm_enabled_T_3) wire vm_enabled : UInt<1>[1] connect vm_enabled[0], _vm_enabled_T_4 node _vpn_T = bits(io.req[0].bits.vaddr, 38, 12) wire vpn : UInt<27>[1] connect vpn[0], _vpn_T node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled[0], UInt<1>(0h1)) wire _mpu_ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_data_WIRE_1 : UInt<34> connect _mpu_ppn_data_WIRE_1, special_entry.data[0] node _mpu_ppn_data_T = bits(_mpu_ppn_data_WIRE_1, 0, 0) connect _mpu_ppn_data_WIRE.fragmented_superpage, _mpu_ppn_data_T node _mpu_ppn_data_T_1 = bits(_mpu_ppn_data_WIRE_1, 1, 1) connect _mpu_ppn_data_WIRE.c, _mpu_ppn_data_T_1 node _mpu_ppn_data_T_2 = bits(_mpu_ppn_data_WIRE_1, 2, 2) connect _mpu_ppn_data_WIRE.eff, _mpu_ppn_data_T_2 node _mpu_ppn_data_T_3 = bits(_mpu_ppn_data_WIRE_1, 3, 3) connect _mpu_ppn_data_WIRE.paa, _mpu_ppn_data_T_3 node _mpu_ppn_data_T_4 = bits(_mpu_ppn_data_WIRE_1, 4, 4) connect _mpu_ppn_data_WIRE.pal, _mpu_ppn_data_T_4 node _mpu_ppn_data_T_5 = bits(_mpu_ppn_data_WIRE_1, 5, 5) connect _mpu_ppn_data_WIRE.pr, _mpu_ppn_data_T_5 node _mpu_ppn_data_T_6 = bits(_mpu_ppn_data_WIRE_1, 6, 6) connect _mpu_ppn_data_WIRE.px, _mpu_ppn_data_T_6 node _mpu_ppn_data_T_7 = bits(_mpu_ppn_data_WIRE_1, 7, 7) connect _mpu_ppn_data_WIRE.pw, _mpu_ppn_data_T_7 node _mpu_ppn_data_T_8 = bits(_mpu_ppn_data_WIRE_1, 8, 8) connect _mpu_ppn_data_WIRE.sr, _mpu_ppn_data_T_8 node _mpu_ppn_data_T_9 = bits(_mpu_ppn_data_WIRE_1, 9, 9) connect _mpu_ppn_data_WIRE.sx, _mpu_ppn_data_T_9 node _mpu_ppn_data_T_10 = bits(_mpu_ppn_data_WIRE_1, 10, 10) connect _mpu_ppn_data_WIRE.sw, _mpu_ppn_data_T_10 node _mpu_ppn_data_T_11 = bits(_mpu_ppn_data_WIRE_1, 11, 11) connect _mpu_ppn_data_WIRE.ae, _mpu_ppn_data_T_11 node _mpu_ppn_data_T_12 = bits(_mpu_ppn_data_WIRE_1, 12, 12) connect _mpu_ppn_data_WIRE.g, _mpu_ppn_data_T_12 node _mpu_ppn_data_T_13 = bits(_mpu_ppn_data_WIRE_1, 13, 13) connect _mpu_ppn_data_WIRE.u, _mpu_ppn_data_T_13 node _mpu_ppn_data_T_14 = bits(_mpu_ppn_data_WIRE_1, 33, 14) connect _mpu_ppn_data_WIRE.ppn, _mpu_ppn_data_T_14 inst mpu_ppn_data_barrier of OptimizationBarrier_EntryData connect mpu_ppn_data_barrier.clock, clock connect mpu_ppn_data_barrier.reset, reset connect mpu_ppn_data_barrier.io.x.fragmented_superpage, _mpu_ppn_data_WIRE.fragmented_superpage connect mpu_ppn_data_barrier.io.x.c, _mpu_ppn_data_WIRE.c connect mpu_ppn_data_barrier.io.x.eff, _mpu_ppn_data_WIRE.eff connect mpu_ppn_data_barrier.io.x.paa, _mpu_ppn_data_WIRE.paa connect mpu_ppn_data_barrier.io.x.pal, _mpu_ppn_data_WIRE.pal connect mpu_ppn_data_barrier.io.x.pr, _mpu_ppn_data_WIRE.pr connect mpu_ppn_data_barrier.io.x.px, _mpu_ppn_data_WIRE.px connect mpu_ppn_data_barrier.io.x.pw, _mpu_ppn_data_WIRE.pw connect mpu_ppn_data_barrier.io.x.sr, _mpu_ppn_data_WIRE.sr connect mpu_ppn_data_barrier.io.x.sx, _mpu_ppn_data_WIRE.sx connect mpu_ppn_data_barrier.io.x.sw, _mpu_ppn_data_WIRE.sw connect mpu_ppn_data_barrier.io.x.ae, _mpu_ppn_data_WIRE.ae connect mpu_ppn_data_barrier.io.x.g, _mpu_ppn_data_WIRE.g connect mpu_ppn_data_barrier.io.x.u, _mpu_ppn_data_WIRE.u connect mpu_ppn_data_barrier.io.x.ppn, _mpu_ppn_data_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_data_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_1 = mux(mpu_ppn_ignore, vpn[0], UInt<1>(0h0)) node _mpu_ppn_T_2 = or(_mpu_ppn_T_1, mpu_ppn_data_barrier.io.y.ppn) node _mpu_ppn_T_3 = bits(_mpu_ppn_T_2, 17, 9) node _mpu_ppn_T_4 = cat(mpu_ppn_res, _mpu_ppn_T_3) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_5 = mux(mpu_ppn_ignore_1, vpn[0], UInt<1>(0h0)) node _mpu_ppn_T_6 = or(_mpu_ppn_T_5, mpu_ppn_data_barrier.io.y.ppn) node _mpu_ppn_T_7 = bits(_mpu_ppn_T_6, 8, 0) node _mpu_ppn_T_8 = cat(_mpu_ppn_T_4, _mpu_ppn_T_7) node _mpu_ppn_T_9 = shr(io.req[0].bits.vaddr, 12) node _mpu_ppn_T_10 = mux(_mpu_ppn_T, _mpu_ppn_T_8, _mpu_ppn_T_9) node _mpu_ppn_T_11 = mux(do_refill, refill_ppn, _mpu_ppn_T_10) wire mpu_ppn : UInt<28>[1] connect mpu_ppn[0], _mpu_ppn_T_11 node _mpu_physaddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _mpu_physaddr_T_1 = cat(mpu_ppn[0], _mpu_physaddr_T) wire mpu_physaddr : UInt<40>[1] connect mpu_physaddr[0], _mpu_physaddr_T_1 inst pmp_0 of PMPChecker_s3_1 connect pmp_0.clock, clock connect pmp_0.reset, reset connect pmp_0.io.addr, mpu_physaddr[0] connect pmp_0.io.size, io.req[0].bits.size connect pmp_0.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp_0.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp_0.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp_0.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp_0.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp_0.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp_0.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp_0.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp_0.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp_0.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp_0.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp_0.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp_0.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp_0.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp_0.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp_0.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp_0.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp_0.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp_0.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp_0.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp_0.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp_0.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp_0.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp_0.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp_0.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp_0.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp_0.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp_0.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp_0.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp_0.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp_0.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp_0.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp_0.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp_0.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp_0.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp_0.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp_0.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp_0.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp_0.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp_0.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp_0.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp_0.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp_0.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp_0.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp_0.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp_0.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp_0.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp_0.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp_0.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp_0.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp_0.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp_0.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp_0.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp_0.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp_0.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp_0.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp_0.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp_0.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp_0.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp_0.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp_0.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp_0.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp_0.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp_0.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l node _pmp_0_io_prv_T = or(do_refill, io.req[0].bits.passthrough) node _pmp_0_io_prv_T_1 = and(UInt<1>(0h1), _pmp_0_io_prv_T) node _pmp_0_io_prv_T_2 = mux(_pmp_0_io_prv_T_1, UInt<1>(0h1), io.ptw.status.dprv) connect pmp_0.io.prv, _pmp_0_io_prv_T_2 node _legal_address_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(mpu_physaddr[0], UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(mpu_physaddr[0], UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(mpu_physaddr[0], UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node _legal_address_T_70 = or(_legal_address_T_69, _legal_address_WIRE[11]) wire legal_address : UInt<1>[1] connect legal_address[0], _legal_address_T_70 node _cacheable_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _cacheable_T_1 = cvt(_cacheable_T) node _cacheable_T_2 = and(_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_3 = asSInt(_cacheable_T_2) node _cacheable_T_4 = eq(_cacheable_T_3, asSInt(UInt<1>(0h0))) node _cacheable_T_5 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _cacheable_T_6 = cvt(_cacheable_T_5) node _cacheable_T_7 = and(_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _cacheable_T_8 = asSInt(_cacheable_T_7) node _cacheable_T_9 = eq(_cacheable_T_8, asSInt(UInt<1>(0h0))) node _cacheable_T_10 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _cacheable_T_11 = cvt(_cacheable_T_10) node _cacheable_T_12 = and(_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _cacheable_T_13 = asSInt(_cacheable_T_12) node _cacheable_T_14 = eq(_cacheable_T_13, asSInt(UInt<1>(0h0))) node _cacheable_T_15 = or(_cacheable_T_4, _cacheable_T_9) node _cacheable_T_16 = or(_cacheable_T_15, _cacheable_T_14) node _cacheable_T_17 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _cacheable_T_18 = cvt(_cacheable_T_17) node _cacheable_T_19 = and(_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _cacheable_T_20 = asSInt(_cacheable_T_19) node _cacheable_T_21 = eq(_cacheable_T_20, asSInt(UInt<1>(0h0))) node _cacheable_T_22 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _cacheable_T_23 = cvt(_cacheable_T_22) node _cacheable_T_24 = and(_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _cacheable_T_25 = asSInt(_cacheable_T_24) node _cacheable_T_26 = eq(_cacheable_T_25, asSInt(UInt<1>(0h0))) node _cacheable_T_27 = or(_cacheable_T_21, _cacheable_T_26) node _cacheable_T_28 = mux(_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _cacheable_T_29 = mux(_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _cacheable_T_30 = or(_cacheable_T_28, _cacheable_T_29) wire _cacheable_WIRE : UInt<1> connect _cacheable_WIRE, _cacheable_T_30 node _cacheable_T_31 = and(legal_address[0], _cacheable_WIRE) node _cacheable_T_32 = and(_cacheable_T_31, UInt<1>(0h1)) wire cacheable : UInt<1>[1] connect cacheable[0], _cacheable_T_32 node _homogeneous_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr[0], UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node _homogeneous_T_59 = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_60 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_61 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_62 = cvt(_homogeneous_T_61) node _homogeneous_T_63 = and(_homogeneous_T_62, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_64 = asSInt(_homogeneous_T_63) node _homogeneous_T_65 = eq(_homogeneous_T_64, asSInt(UInt<1>(0h0))) node _homogeneous_T_66 = or(UInt<1>(0h0), _homogeneous_T_65) node _homogeneous_T_67 = eq(_homogeneous_T_66, UInt<1>(0h0)) node _homogeneous_T_68 = xor(mpu_physaddr[0], UInt<1>(0h0)) node _homogeneous_T_69 = cvt(_homogeneous_T_68) node _homogeneous_T_70 = and(_homogeneous_T_69, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_71 = asSInt(_homogeneous_T_70) node _homogeneous_T_72 = eq(_homogeneous_T_71, asSInt(UInt<1>(0h0))) node _homogeneous_T_73 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _homogeneous_T_74 = cvt(_homogeneous_T_73) node _homogeneous_T_75 = and(_homogeneous_T_74, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_76 = asSInt(_homogeneous_T_75) node _homogeneous_T_77 = eq(_homogeneous_T_76, asSInt(UInt<1>(0h0))) node _homogeneous_T_78 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_79 = cvt(_homogeneous_T_78) node _homogeneous_T_80 = and(_homogeneous_T_79, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_81 = asSInt(_homogeneous_T_80) node _homogeneous_T_82 = eq(_homogeneous_T_81, asSInt(UInt<1>(0h0))) node _homogeneous_T_83 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _homogeneous_T_84 = cvt(_homogeneous_T_83) node _homogeneous_T_85 = and(_homogeneous_T_84, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_86 = asSInt(_homogeneous_T_85) node _homogeneous_T_87 = eq(_homogeneous_T_86, asSInt(UInt<1>(0h0))) node _homogeneous_T_88 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_89 = cvt(_homogeneous_T_88) node _homogeneous_T_90 = and(_homogeneous_T_89, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_91 = asSInt(_homogeneous_T_90) node _homogeneous_T_92 = eq(_homogeneous_T_91, asSInt(UInt<1>(0h0))) node _homogeneous_T_93 = or(UInt<1>(0h0), _homogeneous_T_72) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_77) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_82) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_87) node _homogeneous_T_97 = or(_homogeneous_T_96, _homogeneous_T_92) node _homogeneous_T_98 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _homogeneous_T_99 = cvt(_homogeneous_T_98) node _homogeneous_T_100 = and(_homogeneous_T_99, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_101 = asSInt(_homogeneous_T_100) node _homogeneous_T_102 = eq(_homogeneous_T_101, asSInt(UInt<1>(0h0))) node _homogeneous_T_103 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _homogeneous_T_104 = cvt(_homogeneous_T_103) node _homogeneous_T_105 = and(_homogeneous_T_104, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_106 = asSInt(_homogeneous_T_105) node _homogeneous_T_107 = eq(_homogeneous_T_106, asSInt(UInt<1>(0h0))) node _homogeneous_T_108 = or(UInt<1>(0h0), _homogeneous_T_102) node _homogeneous_T_109 = or(_homogeneous_T_108, _homogeneous_T_107) node _homogeneous_T_110 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_111 = cvt(_homogeneous_T_110) node _homogeneous_T_112 = and(_homogeneous_T_111, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_113 = asSInt(_homogeneous_T_112) node _homogeneous_T_114 = eq(_homogeneous_T_113, asSInt(UInt<1>(0h0))) node _homogeneous_T_115 = or(UInt<1>(0h0), _homogeneous_T_114) node _homogeneous_T_116 = eq(_homogeneous_T_115, UInt<1>(0h0)) node _homogeneous_T_117 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _homogeneous_T_118 = cvt(_homogeneous_T_117) node _homogeneous_T_119 = and(_homogeneous_T_118, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_120 = asSInt(_homogeneous_T_119) node _homogeneous_T_121 = eq(_homogeneous_T_120, asSInt(UInt<1>(0h0))) node _homogeneous_T_122 = or(UInt<1>(0h0), _homogeneous_T_121) node _homogeneous_T_123 = eq(_homogeneous_T_122, UInt<1>(0h0)) wire homogeneous : UInt<1>[1] connect homogeneous[0], _homogeneous_T_59 node _prot_r_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_r_T_1 = cvt(_prot_r_T) node _prot_r_T_2 = and(_prot_r_T_1, asSInt(UInt<1>(0h0))) node _prot_r_T_3 = asSInt(_prot_r_T_2) node _prot_r_T_4 = eq(_prot_r_T_3, asSInt(UInt<1>(0h0))) node _prot_r_T_5 = and(legal_address[0], UInt<1>(0h1)) node _prot_r_T_6 = and(_prot_r_T_5, pmp_0.io.r) wire prot_r : UInt<1>[1] connect prot_r[0], _prot_r_T_6 node _prot_w_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_w_T_1 = cvt(_prot_w_T) node _prot_w_T_2 = and(_prot_w_T_1, asSInt(UInt<33>(0h98110000))) node _prot_w_T_3 = asSInt(_prot_w_T_2) node _prot_w_T_4 = eq(_prot_w_T_3, asSInt(UInt<1>(0h0))) node _prot_w_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_w_T_6 = cvt(_prot_w_T_5) node _prot_w_T_7 = and(_prot_w_T_6, asSInt(UInt<33>(0h9a101000))) node _prot_w_T_8 = asSInt(_prot_w_T_7) node _prot_w_T_9 = eq(_prot_w_T_8, asSInt(UInt<1>(0h0))) node _prot_w_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_w_T_11 = cvt(_prot_w_T_10) node _prot_w_T_12 = and(_prot_w_T_11, asSInt(UInt<33>(0h9a111000))) node _prot_w_T_13 = asSInt(_prot_w_T_12) node _prot_w_T_14 = eq(_prot_w_T_13, asSInt(UInt<1>(0h0))) node _prot_w_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_w_T_16 = cvt(_prot_w_T_15) node _prot_w_T_17 = and(_prot_w_T_16, asSInt(UInt<33>(0h98000000))) node _prot_w_T_18 = asSInt(_prot_w_T_17) node _prot_w_T_19 = eq(_prot_w_T_18, asSInt(UInt<1>(0h0))) node _prot_w_T_20 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_w_T_21 = cvt(_prot_w_T_20) node _prot_w_T_22 = and(_prot_w_T_21, asSInt(UInt<33>(0h9a110000))) node _prot_w_T_23 = asSInt(_prot_w_T_22) node _prot_w_T_24 = eq(_prot_w_T_23, asSInt(UInt<1>(0h0))) node _prot_w_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_w_T_26 = cvt(_prot_w_T_25) node _prot_w_T_27 = and(_prot_w_T_26, asSInt(UInt<33>(0h9a111000))) node _prot_w_T_28 = asSInt(_prot_w_T_27) node _prot_w_T_29 = eq(_prot_w_T_28, asSInt(UInt<1>(0h0))) node _prot_w_T_30 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_w_T_31 = cvt(_prot_w_T_30) node _prot_w_T_32 = and(_prot_w_T_31, asSInt(UInt<33>(0h90000000))) node _prot_w_T_33 = asSInt(_prot_w_T_32) node _prot_w_T_34 = eq(_prot_w_T_33, asSInt(UInt<1>(0h0))) node _prot_w_T_35 = or(_prot_w_T_4, _prot_w_T_9) node _prot_w_T_36 = or(_prot_w_T_35, _prot_w_T_14) node _prot_w_T_37 = or(_prot_w_T_36, _prot_w_T_19) node _prot_w_T_38 = or(_prot_w_T_37, _prot_w_T_24) node _prot_w_T_39 = or(_prot_w_T_38, _prot_w_T_29) node _prot_w_T_40 = or(_prot_w_T_39, _prot_w_T_34) node _prot_w_T_41 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_w_T_42 = cvt(_prot_w_T_41) node _prot_w_T_43 = and(_prot_w_T_42, asSInt(UInt<33>(0h9a110000))) node _prot_w_T_44 = asSInt(_prot_w_T_43) node _prot_w_T_45 = eq(_prot_w_T_44, asSInt(UInt<1>(0h0))) node _prot_w_T_46 = mux(_prot_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _prot_w_T_47 = mux(_prot_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _prot_w_T_48 = or(_prot_w_T_46, _prot_w_T_47) wire _prot_w_WIRE : UInt<1> connect _prot_w_WIRE, _prot_w_T_48 node _prot_w_T_49 = and(legal_address[0], _prot_w_WIRE) node _prot_w_T_50 = and(_prot_w_T_49, pmp_0.io.w) wire prot_w : UInt<1>[1] connect prot_w[0], _prot_w_T_50 node _prot_al_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_al_T_1 = cvt(_prot_al_T) node _prot_al_T_2 = and(_prot_al_T_1, asSInt(UInt<33>(0h98110000))) node _prot_al_T_3 = asSInt(_prot_al_T_2) node _prot_al_T_4 = eq(_prot_al_T_3, asSInt(UInt<1>(0h0))) node _prot_al_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_al_T_6 = cvt(_prot_al_T_5) node _prot_al_T_7 = and(_prot_al_T_6, asSInt(UInt<33>(0h9a101000))) node _prot_al_T_8 = asSInt(_prot_al_T_7) node _prot_al_T_9 = eq(_prot_al_T_8, asSInt(UInt<1>(0h0))) node _prot_al_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_al_T_11 = cvt(_prot_al_T_10) node _prot_al_T_12 = and(_prot_al_T_11, asSInt(UInt<33>(0h9a111000))) node _prot_al_T_13 = asSInt(_prot_al_T_12) node _prot_al_T_14 = eq(_prot_al_T_13, asSInt(UInt<1>(0h0))) node _prot_al_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_al_T_16 = cvt(_prot_al_T_15) node _prot_al_T_17 = and(_prot_al_T_16, asSInt(UInt<33>(0h98000000))) node _prot_al_T_18 = asSInt(_prot_al_T_17) node _prot_al_T_19 = eq(_prot_al_T_18, asSInt(UInt<1>(0h0))) node _prot_al_T_20 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_al_T_21 = cvt(_prot_al_T_20) node _prot_al_T_22 = and(_prot_al_T_21, asSInt(UInt<33>(0h9a110000))) node _prot_al_T_23 = asSInt(_prot_al_T_22) node _prot_al_T_24 = eq(_prot_al_T_23, asSInt(UInt<1>(0h0))) node _prot_al_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_al_T_26 = cvt(_prot_al_T_25) node _prot_al_T_27 = and(_prot_al_T_26, asSInt(UInt<33>(0h9a111000))) node _prot_al_T_28 = asSInt(_prot_al_T_27) node _prot_al_T_29 = eq(_prot_al_T_28, asSInt(UInt<1>(0h0))) node _prot_al_T_30 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_al_T_31 = cvt(_prot_al_T_30) node _prot_al_T_32 = and(_prot_al_T_31, asSInt(UInt<33>(0h90000000))) node _prot_al_T_33 = asSInt(_prot_al_T_32) node _prot_al_T_34 = eq(_prot_al_T_33, asSInt(UInt<1>(0h0))) node _prot_al_T_35 = or(_prot_al_T_4, _prot_al_T_9) node _prot_al_T_36 = or(_prot_al_T_35, _prot_al_T_14) node _prot_al_T_37 = or(_prot_al_T_36, _prot_al_T_19) node _prot_al_T_38 = or(_prot_al_T_37, _prot_al_T_24) node _prot_al_T_39 = or(_prot_al_T_38, _prot_al_T_29) node _prot_al_T_40 = or(_prot_al_T_39, _prot_al_T_34) node _prot_al_T_41 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_al_T_42 = cvt(_prot_al_T_41) node _prot_al_T_43 = and(_prot_al_T_42, asSInt(UInt<33>(0h9a110000))) node _prot_al_T_44 = asSInt(_prot_al_T_43) node _prot_al_T_45 = eq(_prot_al_T_44, asSInt(UInt<1>(0h0))) node _prot_al_T_46 = mux(_prot_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _prot_al_T_47 = mux(_prot_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _prot_al_T_48 = or(_prot_al_T_46, _prot_al_T_47) wire _prot_al_WIRE : UInt<1> connect _prot_al_WIRE, _prot_al_T_48 node _prot_al_T_49 = and(legal_address[0], _prot_al_WIRE) wire prot_al : UInt<1>[1] connect prot_al[0], _prot_al_T_49 node _prot_aa_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_aa_T_1 = cvt(_prot_aa_T) node _prot_aa_T_2 = and(_prot_aa_T_1, asSInt(UInt<33>(0h98110000))) node _prot_aa_T_3 = asSInt(_prot_aa_T_2) node _prot_aa_T_4 = eq(_prot_aa_T_3, asSInt(UInt<1>(0h0))) node _prot_aa_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_aa_T_6 = cvt(_prot_aa_T_5) node _prot_aa_T_7 = and(_prot_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _prot_aa_T_8 = asSInt(_prot_aa_T_7) node _prot_aa_T_9 = eq(_prot_aa_T_8, asSInt(UInt<1>(0h0))) node _prot_aa_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_aa_T_11 = cvt(_prot_aa_T_10) node _prot_aa_T_12 = and(_prot_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _prot_aa_T_13 = asSInt(_prot_aa_T_12) node _prot_aa_T_14 = eq(_prot_aa_T_13, asSInt(UInt<1>(0h0))) node _prot_aa_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_aa_T_16 = cvt(_prot_aa_T_15) node _prot_aa_T_17 = and(_prot_aa_T_16, asSInt(UInt<33>(0h98000000))) node _prot_aa_T_18 = asSInt(_prot_aa_T_17) node _prot_aa_T_19 = eq(_prot_aa_T_18, asSInt(UInt<1>(0h0))) node _prot_aa_T_20 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_aa_T_21 = cvt(_prot_aa_T_20) node _prot_aa_T_22 = and(_prot_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _prot_aa_T_23 = asSInt(_prot_aa_T_22) node _prot_aa_T_24 = eq(_prot_aa_T_23, asSInt(UInt<1>(0h0))) node _prot_aa_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_aa_T_26 = cvt(_prot_aa_T_25) node _prot_aa_T_27 = and(_prot_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _prot_aa_T_28 = asSInt(_prot_aa_T_27) node _prot_aa_T_29 = eq(_prot_aa_T_28, asSInt(UInt<1>(0h0))) node _prot_aa_T_30 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_aa_T_31 = cvt(_prot_aa_T_30) node _prot_aa_T_32 = and(_prot_aa_T_31, asSInt(UInt<33>(0h90000000))) node _prot_aa_T_33 = asSInt(_prot_aa_T_32) node _prot_aa_T_34 = eq(_prot_aa_T_33, asSInt(UInt<1>(0h0))) node _prot_aa_T_35 = or(_prot_aa_T_4, _prot_aa_T_9) node _prot_aa_T_36 = or(_prot_aa_T_35, _prot_aa_T_14) node _prot_aa_T_37 = or(_prot_aa_T_36, _prot_aa_T_19) node _prot_aa_T_38 = or(_prot_aa_T_37, _prot_aa_T_24) node _prot_aa_T_39 = or(_prot_aa_T_38, _prot_aa_T_29) node _prot_aa_T_40 = or(_prot_aa_T_39, _prot_aa_T_34) node _prot_aa_T_41 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_aa_T_42 = cvt(_prot_aa_T_41) node _prot_aa_T_43 = and(_prot_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _prot_aa_T_44 = asSInt(_prot_aa_T_43) node _prot_aa_T_45 = eq(_prot_aa_T_44, asSInt(UInt<1>(0h0))) node _prot_aa_T_46 = mux(_prot_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _prot_aa_T_47 = mux(_prot_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _prot_aa_T_48 = or(_prot_aa_T_46, _prot_aa_T_47) wire _prot_aa_WIRE : UInt<1> connect _prot_aa_WIRE, _prot_aa_T_48 node _prot_aa_T_49 = and(legal_address[0], _prot_aa_WIRE) wire prot_aa : UInt<1>[1] connect prot_aa[0], _prot_aa_T_49 node _prot_x_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_x_T_1 = cvt(_prot_x_T) node _prot_x_T_2 = and(_prot_x_T_1, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_3 = asSInt(_prot_x_T_2) node _prot_x_T_4 = eq(_prot_x_T_3, asSInt(UInt<1>(0h0))) node _prot_x_T_5 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _prot_x_T_6 = cvt(_prot_x_T_5) node _prot_x_T_7 = and(_prot_x_T_6, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_8 = asSInt(_prot_x_T_7) node _prot_x_T_9 = eq(_prot_x_T_8, asSInt(UInt<1>(0h0))) node _prot_x_T_10 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_x_T_11 = cvt(_prot_x_T_10) node _prot_x_T_12 = and(_prot_x_T_11, asSInt(UInt<33>(0h9e110000))) node _prot_x_T_13 = asSInt(_prot_x_T_12) node _prot_x_T_14 = eq(_prot_x_T_13, asSInt(UInt<1>(0h0))) node _prot_x_T_15 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_x_T_16 = cvt(_prot_x_T_15) node _prot_x_T_17 = and(_prot_x_T_16, asSInt(UInt<33>(0h9e110000))) node _prot_x_T_18 = asSInt(_prot_x_T_17) node _prot_x_T_19 = eq(_prot_x_T_18, asSInt(UInt<1>(0h0))) node _prot_x_T_20 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_x_T_21 = cvt(_prot_x_T_20) node _prot_x_T_22 = and(_prot_x_T_21, asSInt(UInt<33>(0h90000000))) node _prot_x_T_23 = asSInt(_prot_x_T_22) node _prot_x_T_24 = eq(_prot_x_T_23, asSInt(UInt<1>(0h0))) node _prot_x_T_25 = or(_prot_x_T_4, _prot_x_T_9) node _prot_x_T_26 = or(_prot_x_T_25, _prot_x_T_14) node _prot_x_T_27 = or(_prot_x_T_26, _prot_x_T_19) node _prot_x_T_28 = or(_prot_x_T_27, _prot_x_T_24) node _prot_x_T_29 = xor(mpu_physaddr[0], UInt<13>(0h1000)) node _prot_x_T_30 = cvt(_prot_x_T_29) node _prot_x_T_31 = and(_prot_x_T_30, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_32 = asSInt(_prot_x_T_31) node _prot_x_T_33 = eq(_prot_x_T_32, asSInt(UInt<1>(0h0))) node _prot_x_T_34 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_x_T_35 = cvt(_prot_x_T_34) node _prot_x_T_36 = and(_prot_x_T_35, asSInt(UInt<33>(0h9e103000))) node _prot_x_T_37 = asSInt(_prot_x_T_36) node _prot_x_T_38 = eq(_prot_x_T_37, asSInt(UInt<1>(0h0))) node _prot_x_T_39 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _prot_x_T_40 = cvt(_prot_x_T_39) node _prot_x_T_41 = and(_prot_x_T_40, asSInt(UInt<33>(0h9e110000))) node _prot_x_T_42 = asSInt(_prot_x_T_41) node _prot_x_T_43 = eq(_prot_x_T_42, asSInt(UInt<1>(0h0))) node _prot_x_T_44 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_x_T_45 = cvt(_prot_x_T_44) node _prot_x_T_46 = and(_prot_x_T_45, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_47 = asSInt(_prot_x_T_46) node _prot_x_T_48 = eq(_prot_x_T_47, asSInt(UInt<1>(0h0))) node _prot_x_T_49 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _prot_x_T_50 = cvt(_prot_x_T_49) node _prot_x_T_51 = and(_prot_x_T_50, asSInt(UInt<33>(0h9c000000))) node _prot_x_T_52 = asSInt(_prot_x_T_51) node _prot_x_T_53 = eq(_prot_x_T_52, asSInt(UInt<1>(0h0))) node _prot_x_T_54 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_x_T_55 = cvt(_prot_x_T_54) node _prot_x_T_56 = and(_prot_x_T_55, asSInt(UInt<33>(0h9e113000))) node _prot_x_T_57 = asSInt(_prot_x_T_56) node _prot_x_T_58 = eq(_prot_x_T_57, asSInt(UInt<1>(0h0))) node _prot_x_T_59 = or(_prot_x_T_33, _prot_x_T_38) node _prot_x_T_60 = or(_prot_x_T_59, _prot_x_T_43) node _prot_x_T_61 = or(_prot_x_T_60, _prot_x_T_48) node _prot_x_T_62 = or(_prot_x_T_61, _prot_x_T_53) node _prot_x_T_63 = or(_prot_x_T_62, _prot_x_T_58) node _prot_x_T_64 = mux(_prot_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _prot_x_T_65 = mux(_prot_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _prot_x_T_66 = or(_prot_x_T_64, _prot_x_T_65) wire _prot_x_WIRE : UInt<1> connect _prot_x_WIRE, _prot_x_T_66 node _prot_x_T_67 = and(legal_address[0], _prot_x_WIRE) node _prot_x_T_68 = and(_prot_x_T_67, pmp_0.io.x) wire prot_x : UInt<1>[1] connect prot_x[0], _prot_x_T_68 node _prot_eff_T = xor(mpu_physaddr[0], UInt<1>(0h0)) node _prot_eff_T_1 = cvt(_prot_eff_T) node _prot_eff_T_2 = and(_prot_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _prot_eff_T_3 = asSInt(_prot_eff_T_2) node _prot_eff_T_4 = eq(_prot_eff_T_3, asSInt(UInt<1>(0h0))) node _prot_eff_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000)) node _prot_eff_T_6 = cvt(_prot_eff_T_5) node _prot_eff_T_7 = and(_prot_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _prot_eff_T_8 = asSInt(_prot_eff_T_7) node _prot_eff_T_9 = eq(_prot_eff_T_8, asSInt(UInt<1>(0h0))) node _prot_eff_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2000000)) node _prot_eff_T_11 = cvt(_prot_eff_T_10) node _prot_eff_T_12 = and(_prot_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _prot_eff_T_13 = asSInt(_prot_eff_T_12) node _prot_eff_T_14 = eq(_prot_eff_T_13, asSInt(UInt<1>(0h0))) node _prot_eff_T_15 = xor(mpu_physaddr[0], UInt<26>(0h2010000)) node _prot_eff_T_16 = cvt(_prot_eff_T_15) node _prot_eff_T_17 = and(_prot_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _prot_eff_T_18 = asSInt(_prot_eff_T_17) node _prot_eff_T_19 = eq(_prot_eff_T_18, asSInt(UInt<1>(0h0))) node _prot_eff_T_20 = xor(mpu_physaddr[0], UInt<28>(0hc000000)) node _prot_eff_T_21 = cvt(_prot_eff_T_20) node _prot_eff_T_22 = and(_prot_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _prot_eff_T_23 = asSInt(_prot_eff_T_22) node _prot_eff_T_24 = eq(_prot_eff_T_23, asSInt(UInt<1>(0h0))) node _prot_eff_T_25 = xor(mpu_physaddr[0], UInt<29>(0h10000000)) node _prot_eff_T_26 = cvt(_prot_eff_T_25) node _prot_eff_T_27 = and(_prot_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _prot_eff_T_28 = asSInt(_prot_eff_T_27) node _prot_eff_T_29 = eq(_prot_eff_T_28, asSInt(UInt<1>(0h0))) node _prot_eff_T_30 = or(_prot_eff_T_4, _prot_eff_T_9) node _prot_eff_T_31 = or(_prot_eff_T_30, _prot_eff_T_14) node _prot_eff_T_32 = or(_prot_eff_T_31, _prot_eff_T_19) node _prot_eff_T_33 = or(_prot_eff_T_32, _prot_eff_T_24) node _prot_eff_T_34 = or(_prot_eff_T_33, _prot_eff_T_29) node _prot_eff_T_35 = xor(mpu_physaddr[0], UInt<14>(0h3000)) node _prot_eff_T_36 = cvt(_prot_eff_T_35) node _prot_eff_T_37 = and(_prot_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _prot_eff_T_38 = asSInt(_prot_eff_T_37) node _prot_eff_T_39 = eq(_prot_eff_T_38, asSInt(UInt<1>(0h0))) node _prot_eff_T_40 = xor(mpu_physaddr[0], UInt<17>(0h10000)) node _prot_eff_T_41 = cvt(_prot_eff_T_40) node _prot_eff_T_42 = and(_prot_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _prot_eff_T_43 = asSInt(_prot_eff_T_42) node _prot_eff_T_44 = eq(_prot_eff_T_43, asSInt(UInt<1>(0h0))) node _prot_eff_T_45 = xor(mpu_physaddr[0], UInt<28>(0h8000000)) node _prot_eff_T_46 = cvt(_prot_eff_T_45) node _prot_eff_T_47 = and(_prot_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _prot_eff_T_48 = asSInt(_prot_eff_T_47) node _prot_eff_T_49 = eq(_prot_eff_T_48, asSInt(UInt<1>(0h0))) node _prot_eff_T_50 = xor(mpu_physaddr[0], UInt<32>(0h80000000)) node _prot_eff_T_51 = cvt(_prot_eff_T_50) node _prot_eff_T_52 = and(_prot_eff_T_51, asSInt(UInt<33>(0h90000000))) node _prot_eff_T_53 = asSInt(_prot_eff_T_52) node _prot_eff_T_54 = eq(_prot_eff_T_53, asSInt(UInt<1>(0h0))) node _prot_eff_T_55 = or(_prot_eff_T_39, _prot_eff_T_44) node _prot_eff_T_56 = or(_prot_eff_T_55, _prot_eff_T_49) node _prot_eff_T_57 = or(_prot_eff_T_56, _prot_eff_T_54) node _prot_eff_T_58 = mux(_prot_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _prot_eff_T_59 = mux(_prot_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _prot_eff_T_60 = or(_prot_eff_T_58, _prot_eff_T_59) wire _prot_eff_WIRE : UInt<1> connect _prot_eff_WIRE, _prot_eff_T_60 node _prot_eff_T_61 = and(legal_address[0], _prot_eff_WIRE) wire prot_eff : UInt<1>[1] connect prot_eff[0], _prot_eff_T_61 node _sector_hits_T = or(sectored_entries[0].valid[0], sectored_entries[0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0].tag, vpn[0]) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = and(_sector_hits_T_2, _sector_hits_T_5) node _sector_hits_T_7 = or(sectored_entries[1].valid[0], sectored_entries[1].valid[1]) node _sector_hits_T_8 = or(_sector_hits_T_7, sectored_entries[1].valid[2]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[1].valid[3]) node _sector_hits_T_10 = xor(sectored_entries[1].tag, vpn[0]) node _sector_hits_T_11 = shr(_sector_hits_T_10, 2) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = and(_sector_hits_T_9, _sector_hits_T_12) wire _sector_hits_WIRE : UInt<1>[2] connect _sector_hits_WIRE[0], _sector_hits_T_6 connect _sector_hits_WIRE[1], _sector_hits_T_13 wire sector_hits : UInt<1>[2][1] connect sector_hits[0], _sector_hits_WIRE node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = bits(superpage_entries[0].tag, 26, 18) node _superpage_hits_T_1 = bits(vpn[0], 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T, _superpage_hits_T_1) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_entries[0].valid[0], _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = bits(superpage_entries[0].tag, 17, 9) node _superpage_hits_T_6 = bits(vpn[0], 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_5, _superpage_hits_T_6) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = bits(superpage_entries[0].tag, 8, 0) node _superpage_hits_T_11 = bits(vpn[0], 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_10, _superpage_hits_T_11) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node _superpage_hits_T_14 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_15 = bits(superpage_entries[1].tag, 26, 18) node _superpage_hits_T_16 = bits(vpn[0], 26, 18) node _superpage_hits_T_17 = eq(_superpage_hits_T_15, _superpage_hits_T_16) node _superpage_hits_T_18 = or(superpage_hits_ignore_3, _superpage_hits_T_17) node _superpage_hits_T_19 = and(superpage_entries[1].valid[0], _superpage_hits_T_18) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_20 = bits(superpage_entries[1].tag, 17, 9) node _superpage_hits_T_21 = bits(vpn[0], 17, 9) node _superpage_hits_T_22 = eq(_superpage_hits_T_20, _superpage_hits_T_21) node _superpage_hits_T_23 = or(superpage_hits_ignore_4, _superpage_hits_T_22) node _superpage_hits_T_24 = and(_superpage_hits_T_19, _superpage_hits_T_23) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_25 = bits(superpage_entries[1].tag, 8, 0) node _superpage_hits_T_26 = bits(vpn[0], 8, 0) node _superpage_hits_T_27 = eq(_superpage_hits_T_25, _superpage_hits_T_26) node _superpage_hits_T_28 = or(superpage_hits_ignore_5, _superpage_hits_T_27) node _superpage_hits_T_29 = and(_superpage_hits_T_24, _superpage_hits_T_28) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_30 = bits(superpage_entries[2].tag, 26, 18) node _superpage_hits_T_31 = bits(vpn[0], 26, 18) node _superpage_hits_T_32 = eq(_superpage_hits_T_30, _superpage_hits_T_31) node _superpage_hits_T_33 = or(superpage_hits_ignore_6, _superpage_hits_T_32) node _superpage_hits_T_34 = and(superpage_entries[2].valid[0], _superpage_hits_T_33) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_35 = bits(superpage_entries[2].tag, 17, 9) node _superpage_hits_T_36 = bits(vpn[0], 17, 9) node _superpage_hits_T_37 = eq(_superpage_hits_T_35, _superpage_hits_T_36) node _superpage_hits_T_38 = or(superpage_hits_ignore_7, _superpage_hits_T_37) node _superpage_hits_T_39 = and(_superpage_hits_T_34, _superpage_hits_T_38) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_40 = bits(superpage_entries[2].tag, 8, 0) node _superpage_hits_T_41 = bits(vpn[0], 8, 0) node _superpage_hits_T_42 = eq(_superpage_hits_T_40, _superpage_hits_T_41) node _superpage_hits_T_43 = or(superpage_hits_ignore_8, _superpage_hits_T_42) node _superpage_hits_T_44 = and(_superpage_hits_T_39, _superpage_hits_T_43) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_45 = bits(superpage_entries[3].tag, 26, 18) node _superpage_hits_T_46 = bits(vpn[0], 26, 18) node _superpage_hits_T_47 = eq(_superpage_hits_T_45, _superpage_hits_T_46) node _superpage_hits_T_48 = or(superpage_hits_ignore_9, _superpage_hits_T_47) node _superpage_hits_T_49 = and(superpage_entries[3].valid[0], _superpage_hits_T_48) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_50 = bits(superpage_entries[3].tag, 17, 9) node _superpage_hits_T_51 = bits(vpn[0], 17, 9) node _superpage_hits_T_52 = eq(_superpage_hits_T_50, _superpage_hits_T_51) node _superpage_hits_T_53 = or(superpage_hits_ignore_10, _superpage_hits_T_52) node _superpage_hits_T_54 = and(_superpage_hits_T_49, _superpage_hits_T_53) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_55 = bits(superpage_entries[3].tag, 8, 0) node _superpage_hits_T_56 = bits(vpn[0], 8, 0) node _superpage_hits_T_57 = eq(_superpage_hits_T_55, _superpage_hits_T_56) node _superpage_hits_T_58 = or(superpage_hits_ignore_11, _superpage_hits_T_57) node _superpage_hits_T_59 = and(_superpage_hits_T_54, _superpage_hits_T_58) wire _superpage_hits_WIRE : UInt<1>[4] connect _superpage_hits_WIRE[0], _superpage_hits_T_14 connect _superpage_hits_WIRE[1], _superpage_hits_T_29 connect _superpage_hits_WIRE[2], _superpage_hits_T_44 connect _superpage_hits_WIRE[3], _superpage_hits_T_59 wire superpage_hits : UInt<1>[4][1] connect superpage_hits[0], _superpage_hits_WIRE node hitsVec_idx = bits(vpn[0], 1, 0) node _hitsVec_T = xor(sectored_entries[0].tag, vpn[0]) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = and(sectored_entries[0].valid[hitsVec_idx], _hitsVec_T_2) node _hitsVec_T_4 = and(vm_enabled[0], _hitsVec_T_3) node hitsVec_idx_1 = bits(vpn[0], 1, 0) node _hitsVec_T_5 = xor(sectored_entries[1].tag, vpn[0]) node _hitsVec_T_6 = shr(_hitsVec_T_5, 2) node _hitsVec_T_7 = eq(_hitsVec_T_6, UInt<1>(0h0)) node _hitsVec_T_8 = and(sectored_entries[1].valid[hitsVec_idx_1], _hitsVec_T_7) node _hitsVec_T_9 = and(vm_enabled[0], _hitsVec_T_8) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_10 = bits(superpage_entries[0].tag, 26, 18) node _hitsVec_T_11 = bits(vpn[0], 26, 18) node _hitsVec_T_12 = eq(_hitsVec_T_10, _hitsVec_T_11) node _hitsVec_T_13 = or(hitsVec_ignore, _hitsVec_T_12) node _hitsVec_T_14 = and(superpage_entries[0].valid[0], _hitsVec_T_13) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_15 = bits(superpage_entries[0].tag, 17, 9) node _hitsVec_T_16 = bits(vpn[0], 17, 9) node _hitsVec_T_17 = eq(_hitsVec_T_15, _hitsVec_T_16) node _hitsVec_T_18 = or(hitsVec_ignore_1, _hitsVec_T_17) node _hitsVec_T_19 = and(_hitsVec_T_14, _hitsVec_T_18) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_20 = bits(superpage_entries[0].tag, 8, 0) node _hitsVec_T_21 = bits(vpn[0], 8, 0) node _hitsVec_T_22 = eq(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = or(hitsVec_ignore_2, _hitsVec_T_22) node _hitsVec_T_24 = and(_hitsVec_T_19, _hitsVec_T_23) node _hitsVec_T_25 = and(vm_enabled[0], _hitsVec_T_24) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_26 = bits(superpage_entries[1].tag, 26, 18) node _hitsVec_T_27 = bits(vpn[0], 26, 18) node _hitsVec_T_28 = eq(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = or(hitsVec_ignore_3, _hitsVec_T_28) node _hitsVec_T_30 = and(superpage_entries[1].valid[0], _hitsVec_T_29) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_31 = bits(superpage_entries[1].tag, 17, 9) node _hitsVec_T_32 = bits(vpn[0], 17, 9) node _hitsVec_T_33 = eq(_hitsVec_T_31, _hitsVec_T_32) node _hitsVec_T_34 = or(hitsVec_ignore_4, _hitsVec_T_33) node _hitsVec_T_35 = and(_hitsVec_T_30, _hitsVec_T_34) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_36 = bits(superpage_entries[1].tag, 8, 0) node _hitsVec_T_37 = bits(vpn[0], 8, 0) node _hitsVec_T_38 = eq(_hitsVec_T_36, _hitsVec_T_37) node _hitsVec_T_39 = or(hitsVec_ignore_5, _hitsVec_T_38) node _hitsVec_T_40 = and(_hitsVec_T_35, _hitsVec_T_39) node _hitsVec_T_41 = and(vm_enabled[0], _hitsVec_T_40) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_42 = bits(superpage_entries[2].tag, 26, 18) node _hitsVec_T_43 = bits(vpn[0], 26, 18) node _hitsVec_T_44 = eq(_hitsVec_T_42, _hitsVec_T_43) node _hitsVec_T_45 = or(hitsVec_ignore_6, _hitsVec_T_44) node _hitsVec_T_46 = and(superpage_entries[2].valid[0], _hitsVec_T_45) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_47 = bits(superpage_entries[2].tag, 17, 9) node _hitsVec_T_48 = bits(vpn[0], 17, 9) node _hitsVec_T_49 = eq(_hitsVec_T_47, _hitsVec_T_48) node _hitsVec_T_50 = or(hitsVec_ignore_7, _hitsVec_T_49) node _hitsVec_T_51 = and(_hitsVec_T_46, _hitsVec_T_50) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_52 = bits(superpage_entries[2].tag, 8, 0) node _hitsVec_T_53 = bits(vpn[0], 8, 0) node _hitsVec_T_54 = eq(_hitsVec_T_52, _hitsVec_T_53) node _hitsVec_T_55 = or(hitsVec_ignore_8, _hitsVec_T_54) node _hitsVec_T_56 = and(_hitsVec_T_51, _hitsVec_T_55) node _hitsVec_T_57 = and(vm_enabled[0], _hitsVec_T_56) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_58 = bits(superpage_entries[3].tag, 26, 18) node _hitsVec_T_59 = bits(vpn[0], 26, 18) node _hitsVec_T_60 = eq(_hitsVec_T_58, _hitsVec_T_59) node _hitsVec_T_61 = or(hitsVec_ignore_9, _hitsVec_T_60) node _hitsVec_T_62 = and(superpage_entries[3].valid[0], _hitsVec_T_61) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_63 = bits(superpage_entries[3].tag, 17, 9) node _hitsVec_T_64 = bits(vpn[0], 17, 9) node _hitsVec_T_65 = eq(_hitsVec_T_63, _hitsVec_T_64) node _hitsVec_T_66 = or(hitsVec_ignore_10, _hitsVec_T_65) node _hitsVec_T_67 = and(_hitsVec_T_62, _hitsVec_T_66) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_68 = bits(superpage_entries[3].tag, 8, 0) node _hitsVec_T_69 = bits(vpn[0], 8, 0) node _hitsVec_T_70 = eq(_hitsVec_T_68, _hitsVec_T_69) node _hitsVec_T_71 = or(hitsVec_ignore_11, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_T_73 = and(vm_enabled[0], _hitsVec_T_72) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_74 = bits(special_entry.tag, 26, 18) node _hitsVec_T_75 = bits(vpn[0], 26, 18) node _hitsVec_T_76 = eq(_hitsVec_T_74, _hitsVec_T_75) node _hitsVec_T_77 = or(hitsVec_ignore_12, _hitsVec_T_76) node _hitsVec_T_78 = and(special_entry.valid[0], _hitsVec_T_77) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_79 = bits(special_entry.tag, 17, 9) node _hitsVec_T_80 = bits(vpn[0], 17, 9) node _hitsVec_T_81 = eq(_hitsVec_T_79, _hitsVec_T_80) node _hitsVec_T_82 = or(hitsVec_ignore_13, _hitsVec_T_81) node _hitsVec_T_83 = and(_hitsVec_T_78, _hitsVec_T_82) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_84 = bits(special_entry.tag, 8, 0) node _hitsVec_T_85 = bits(vpn[0], 8, 0) node _hitsVec_T_86 = eq(_hitsVec_T_84, _hitsVec_T_85) node _hitsVec_T_87 = or(hitsVec_ignore_14, _hitsVec_T_86) node _hitsVec_T_88 = and(_hitsVec_T_83, _hitsVec_T_87) node _hitsVec_T_89 = and(vm_enabled[0], _hitsVec_T_88) wire _hitsVec_WIRE : UInt<1>[7] connect _hitsVec_WIRE[0], _hitsVec_T_4 connect _hitsVec_WIRE[1], _hitsVec_T_9 connect _hitsVec_WIRE[2], _hitsVec_T_25 connect _hitsVec_WIRE[3], _hitsVec_T_41 connect _hitsVec_WIRE[4], _hitsVec_T_57 connect _hitsVec_WIRE[5], _hitsVec_T_73 connect _hitsVec_WIRE[6], _hitsVec_T_89 wire hitsVec : UInt<1>[7][1] connect hitsVec[0], _hitsVec_WIRE node real_hits_lo_hi = cat(hitsVec[0][2], hitsVec[0][1]) node real_hits_lo = cat(real_hits_lo_hi, hitsVec[0][0]) node real_hits_hi_lo = cat(hitsVec[0][4], hitsVec[0][3]) node real_hits_hi_hi = cat(hitsVec[0][6], hitsVec[0][5]) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node _real_hits_T = cat(real_hits_hi, real_hits_lo) wire real_hits : UInt<7>[1] connect real_hits[0], _real_hits_T node _hits_T = eq(vm_enabled[0], UInt<1>(0h0)) node _hits_T_1 = cat(_hits_T, real_hits[0]) wire hits : UInt<8>[1] connect hits[0], _hits_T_1 node _ppn_T = eq(vm_enabled[0], UInt<1>(0h0)) node _ppn_data_T = bits(vpn[0], 1, 0) wire _ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_1 : UInt<34> connect _ppn_data_WIRE_1, sectored_entries[0].data[_ppn_data_T] node _ppn_data_T_1 = bits(_ppn_data_WIRE_1, 0, 0) connect _ppn_data_WIRE.fragmented_superpage, _ppn_data_T_1 node _ppn_data_T_2 = bits(_ppn_data_WIRE_1, 1, 1) connect _ppn_data_WIRE.c, _ppn_data_T_2 node _ppn_data_T_3 = bits(_ppn_data_WIRE_1, 2, 2) connect _ppn_data_WIRE.eff, _ppn_data_T_3 node _ppn_data_T_4 = bits(_ppn_data_WIRE_1, 3, 3) connect _ppn_data_WIRE.paa, _ppn_data_T_4 node _ppn_data_T_5 = bits(_ppn_data_WIRE_1, 4, 4) connect _ppn_data_WIRE.pal, _ppn_data_T_5 node _ppn_data_T_6 = bits(_ppn_data_WIRE_1, 5, 5) connect _ppn_data_WIRE.pr, _ppn_data_T_6 node _ppn_data_T_7 = bits(_ppn_data_WIRE_1, 6, 6) connect _ppn_data_WIRE.px, _ppn_data_T_7 node _ppn_data_T_8 = bits(_ppn_data_WIRE_1, 7, 7) connect _ppn_data_WIRE.pw, _ppn_data_T_8 node _ppn_data_T_9 = bits(_ppn_data_WIRE_1, 8, 8) connect _ppn_data_WIRE.sr, _ppn_data_T_9 node _ppn_data_T_10 = bits(_ppn_data_WIRE_1, 9, 9) connect _ppn_data_WIRE.sx, _ppn_data_T_10 node _ppn_data_T_11 = bits(_ppn_data_WIRE_1, 10, 10) connect _ppn_data_WIRE.sw, _ppn_data_T_11 node _ppn_data_T_12 = bits(_ppn_data_WIRE_1, 11, 11) connect _ppn_data_WIRE.ae, _ppn_data_T_12 node _ppn_data_T_13 = bits(_ppn_data_WIRE_1, 12, 12) connect _ppn_data_WIRE.g, _ppn_data_T_13 node _ppn_data_T_14 = bits(_ppn_data_WIRE_1, 13, 13) connect _ppn_data_WIRE.u, _ppn_data_T_14 node _ppn_data_T_15 = bits(_ppn_data_WIRE_1, 33, 14) connect _ppn_data_WIRE.ppn, _ppn_data_T_15 inst ppn_data_barrier of OptimizationBarrier_EntryData_1 connect ppn_data_barrier.clock, clock connect ppn_data_barrier.reset, reset connect ppn_data_barrier.io.x.fragmented_superpage, _ppn_data_WIRE.fragmented_superpage connect ppn_data_barrier.io.x.c, _ppn_data_WIRE.c connect ppn_data_barrier.io.x.eff, _ppn_data_WIRE.eff connect ppn_data_barrier.io.x.paa, _ppn_data_WIRE.paa connect ppn_data_barrier.io.x.pal, _ppn_data_WIRE.pal connect ppn_data_barrier.io.x.pr, _ppn_data_WIRE.pr connect ppn_data_barrier.io.x.px, _ppn_data_WIRE.px connect ppn_data_barrier.io.x.pw, _ppn_data_WIRE.pw connect ppn_data_barrier.io.x.sr, _ppn_data_WIRE.sr connect ppn_data_barrier.io.x.sx, _ppn_data_WIRE.sx connect ppn_data_barrier.io.x.sw, _ppn_data_WIRE.sw connect ppn_data_barrier.io.x.ae, _ppn_data_WIRE.ae connect ppn_data_barrier.io.x.g, _ppn_data_WIRE.g connect ppn_data_barrier.io.x.u, _ppn_data_WIRE.u connect ppn_data_barrier.io.x.ppn, _ppn_data_WIRE.ppn node _ppn_data_T_16 = bits(vpn[0], 1, 0) wire _ppn_data_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_3 : UInt<34> connect _ppn_data_WIRE_3, sectored_entries[1].data[_ppn_data_T_16] node _ppn_data_T_17 = bits(_ppn_data_WIRE_3, 0, 0) connect _ppn_data_WIRE_2.fragmented_superpage, _ppn_data_T_17 node _ppn_data_T_18 = bits(_ppn_data_WIRE_3, 1, 1) connect _ppn_data_WIRE_2.c, _ppn_data_T_18 node _ppn_data_T_19 = bits(_ppn_data_WIRE_3, 2, 2) connect _ppn_data_WIRE_2.eff, _ppn_data_T_19 node _ppn_data_T_20 = bits(_ppn_data_WIRE_3, 3, 3) connect _ppn_data_WIRE_2.paa, _ppn_data_T_20 node _ppn_data_T_21 = bits(_ppn_data_WIRE_3, 4, 4) connect _ppn_data_WIRE_2.pal, _ppn_data_T_21 node _ppn_data_T_22 = bits(_ppn_data_WIRE_3, 5, 5) connect _ppn_data_WIRE_2.pr, _ppn_data_T_22 node _ppn_data_T_23 = bits(_ppn_data_WIRE_3, 6, 6) connect _ppn_data_WIRE_2.px, _ppn_data_T_23 node _ppn_data_T_24 = bits(_ppn_data_WIRE_3, 7, 7) connect _ppn_data_WIRE_2.pw, _ppn_data_T_24 node _ppn_data_T_25 = bits(_ppn_data_WIRE_3, 8, 8) connect _ppn_data_WIRE_2.sr, _ppn_data_T_25 node _ppn_data_T_26 = bits(_ppn_data_WIRE_3, 9, 9) connect _ppn_data_WIRE_2.sx, _ppn_data_T_26 node _ppn_data_T_27 = bits(_ppn_data_WIRE_3, 10, 10) connect _ppn_data_WIRE_2.sw, _ppn_data_T_27 node _ppn_data_T_28 = bits(_ppn_data_WIRE_3, 11, 11) connect _ppn_data_WIRE_2.ae, _ppn_data_T_28 node _ppn_data_T_29 = bits(_ppn_data_WIRE_3, 12, 12) connect _ppn_data_WIRE_2.g, _ppn_data_T_29 node _ppn_data_T_30 = bits(_ppn_data_WIRE_3, 13, 13) connect _ppn_data_WIRE_2.u, _ppn_data_T_30 node _ppn_data_T_31 = bits(_ppn_data_WIRE_3, 33, 14) connect _ppn_data_WIRE_2.ppn, _ppn_data_T_31 inst ppn_data_barrier_1 of OptimizationBarrier_EntryData_2 connect ppn_data_barrier_1.clock, clock connect ppn_data_barrier_1.reset, reset connect ppn_data_barrier_1.io.x.fragmented_superpage, _ppn_data_WIRE_2.fragmented_superpage connect ppn_data_barrier_1.io.x.c, _ppn_data_WIRE_2.c connect ppn_data_barrier_1.io.x.eff, _ppn_data_WIRE_2.eff connect ppn_data_barrier_1.io.x.paa, _ppn_data_WIRE_2.paa connect ppn_data_barrier_1.io.x.pal, _ppn_data_WIRE_2.pal connect ppn_data_barrier_1.io.x.pr, _ppn_data_WIRE_2.pr connect ppn_data_barrier_1.io.x.px, _ppn_data_WIRE_2.px connect ppn_data_barrier_1.io.x.pw, _ppn_data_WIRE_2.pw connect ppn_data_barrier_1.io.x.sr, _ppn_data_WIRE_2.sr connect ppn_data_barrier_1.io.x.sx, _ppn_data_WIRE_2.sx connect ppn_data_barrier_1.io.x.sw, _ppn_data_WIRE_2.sw connect ppn_data_barrier_1.io.x.ae, _ppn_data_WIRE_2.ae connect ppn_data_barrier_1.io.x.g, _ppn_data_WIRE_2.g connect ppn_data_barrier_1.io.x.u, _ppn_data_WIRE_2.u connect ppn_data_barrier_1.io.x.ppn, _ppn_data_WIRE_2.ppn wire _ppn_data_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_5 : UInt<34> connect _ppn_data_WIRE_5, superpage_entries[0].data[0] node _ppn_data_T_32 = bits(_ppn_data_WIRE_5, 0, 0) connect _ppn_data_WIRE_4.fragmented_superpage, _ppn_data_T_32 node _ppn_data_T_33 = bits(_ppn_data_WIRE_5, 1, 1) connect _ppn_data_WIRE_4.c, _ppn_data_T_33 node _ppn_data_T_34 = bits(_ppn_data_WIRE_5, 2, 2) connect _ppn_data_WIRE_4.eff, _ppn_data_T_34 node _ppn_data_T_35 = bits(_ppn_data_WIRE_5, 3, 3) connect _ppn_data_WIRE_4.paa, _ppn_data_T_35 node _ppn_data_T_36 = bits(_ppn_data_WIRE_5, 4, 4) connect _ppn_data_WIRE_4.pal, _ppn_data_T_36 node _ppn_data_T_37 = bits(_ppn_data_WIRE_5, 5, 5) connect _ppn_data_WIRE_4.pr, _ppn_data_T_37 node _ppn_data_T_38 = bits(_ppn_data_WIRE_5, 6, 6) connect _ppn_data_WIRE_4.px, _ppn_data_T_38 node _ppn_data_T_39 = bits(_ppn_data_WIRE_5, 7, 7) connect _ppn_data_WIRE_4.pw, _ppn_data_T_39 node _ppn_data_T_40 = bits(_ppn_data_WIRE_5, 8, 8) connect _ppn_data_WIRE_4.sr, _ppn_data_T_40 node _ppn_data_T_41 = bits(_ppn_data_WIRE_5, 9, 9) connect _ppn_data_WIRE_4.sx, _ppn_data_T_41 node _ppn_data_T_42 = bits(_ppn_data_WIRE_5, 10, 10) connect _ppn_data_WIRE_4.sw, _ppn_data_T_42 node _ppn_data_T_43 = bits(_ppn_data_WIRE_5, 11, 11) connect _ppn_data_WIRE_4.ae, _ppn_data_T_43 node _ppn_data_T_44 = bits(_ppn_data_WIRE_5, 12, 12) connect _ppn_data_WIRE_4.g, _ppn_data_T_44 node _ppn_data_T_45 = bits(_ppn_data_WIRE_5, 13, 13) connect _ppn_data_WIRE_4.u, _ppn_data_T_45 node _ppn_data_T_46 = bits(_ppn_data_WIRE_5, 33, 14) connect _ppn_data_WIRE_4.ppn, _ppn_data_T_46 inst ppn_data_barrier_2 of OptimizationBarrier_EntryData_3 connect ppn_data_barrier_2.clock, clock connect ppn_data_barrier_2.reset, reset connect ppn_data_barrier_2.io.x.fragmented_superpage, _ppn_data_WIRE_4.fragmented_superpage connect ppn_data_barrier_2.io.x.c, _ppn_data_WIRE_4.c connect ppn_data_barrier_2.io.x.eff, _ppn_data_WIRE_4.eff connect ppn_data_barrier_2.io.x.paa, _ppn_data_WIRE_4.paa connect ppn_data_barrier_2.io.x.pal, _ppn_data_WIRE_4.pal connect ppn_data_barrier_2.io.x.pr, _ppn_data_WIRE_4.pr connect ppn_data_barrier_2.io.x.px, _ppn_data_WIRE_4.px connect ppn_data_barrier_2.io.x.pw, _ppn_data_WIRE_4.pw connect ppn_data_barrier_2.io.x.sr, _ppn_data_WIRE_4.sr connect ppn_data_barrier_2.io.x.sx, _ppn_data_WIRE_4.sx connect ppn_data_barrier_2.io.x.sw, _ppn_data_WIRE_4.sw connect ppn_data_barrier_2.io.x.ae, _ppn_data_WIRE_4.ae connect ppn_data_barrier_2.io.x.g, _ppn_data_WIRE_4.g connect ppn_data_barrier_2.io.x.u, _ppn_data_WIRE_4.u connect ppn_data_barrier_2.io.x.ppn, _ppn_data_WIRE_4.ppn node ppn_res = shr(ppn_data_barrier_2.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn[0], UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, ppn_data_barrier_2.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn[0], UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, ppn_data_barrier_2.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) wire _ppn_data_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_7 : UInt<34> connect _ppn_data_WIRE_7, superpage_entries[1].data[0] node _ppn_data_T_47 = bits(_ppn_data_WIRE_7, 0, 0) connect _ppn_data_WIRE_6.fragmented_superpage, _ppn_data_T_47 node _ppn_data_T_48 = bits(_ppn_data_WIRE_7, 1, 1) connect _ppn_data_WIRE_6.c, _ppn_data_T_48 node _ppn_data_T_49 = bits(_ppn_data_WIRE_7, 2, 2) connect _ppn_data_WIRE_6.eff, _ppn_data_T_49 node _ppn_data_T_50 = bits(_ppn_data_WIRE_7, 3, 3) connect _ppn_data_WIRE_6.paa, _ppn_data_T_50 node _ppn_data_T_51 = bits(_ppn_data_WIRE_7, 4, 4) connect _ppn_data_WIRE_6.pal, _ppn_data_T_51 node _ppn_data_T_52 = bits(_ppn_data_WIRE_7, 5, 5) connect _ppn_data_WIRE_6.pr, _ppn_data_T_52 node _ppn_data_T_53 = bits(_ppn_data_WIRE_7, 6, 6) connect _ppn_data_WIRE_6.px, _ppn_data_T_53 node _ppn_data_T_54 = bits(_ppn_data_WIRE_7, 7, 7) connect _ppn_data_WIRE_6.pw, _ppn_data_T_54 node _ppn_data_T_55 = bits(_ppn_data_WIRE_7, 8, 8) connect _ppn_data_WIRE_6.sr, _ppn_data_T_55 node _ppn_data_T_56 = bits(_ppn_data_WIRE_7, 9, 9) connect _ppn_data_WIRE_6.sx, _ppn_data_T_56 node _ppn_data_T_57 = bits(_ppn_data_WIRE_7, 10, 10) connect _ppn_data_WIRE_6.sw, _ppn_data_T_57 node _ppn_data_T_58 = bits(_ppn_data_WIRE_7, 11, 11) connect _ppn_data_WIRE_6.ae, _ppn_data_T_58 node _ppn_data_T_59 = bits(_ppn_data_WIRE_7, 12, 12) connect _ppn_data_WIRE_6.g, _ppn_data_T_59 node _ppn_data_T_60 = bits(_ppn_data_WIRE_7, 13, 13) connect _ppn_data_WIRE_6.u, _ppn_data_T_60 node _ppn_data_T_61 = bits(_ppn_data_WIRE_7, 33, 14) connect _ppn_data_WIRE_6.ppn, _ppn_data_T_61 inst ppn_data_barrier_3 of OptimizationBarrier_EntryData_4 connect ppn_data_barrier_3.clock, clock connect ppn_data_barrier_3.reset, reset connect ppn_data_barrier_3.io.x.fragmented_superpage, _ppn_data_WIRE_6.fragmented_superpage connect ppn_data_barrier_3.io.x.c, _ppn_data_WIRE_6.c connect ppn_data_barrier_3.io.x.eff, _ppn_data_WIRE_6.eff connect ppn_data_barrier_3.io.x.paa, _ppn_data_WIRE_6.paa connect ppn_data_barrier_3.io.x.pal, _ppn_data_WIRE_6.pal connect ppn_data_barrier_3.io.x.pr, _ppn_data_WIRE_6.pr connect ppn_data_barrier_3.io.x.px, _ppn_data_WIRE_6.px connect ppn_data_barrier_3.io.x.pw, _ppn_data_WIRE_6.pw connect ppn_data_barrier_3.io.x.sr, _ppn_data_WIRE_6.sr connect ppn_data_barrier_3.io.x.sx, _ppn_data_WIRE_6.sx connect ppn_data_barrier_3.io.x.sw, _ppn_data_WIRE_6.sw connect ppn_data_barrier_3.io.x.ae, _ppn_data_WIRE_6.ae connect ppn_data_barrier_3.io.x.g, _ppn_data_WIRE_6.g connect ppn_data_barrier_3.io.x.u, _ppn_data_WIRE_6.u connect ppn_data_barrier_3.io.x.ppn, _ppn_data_WIRE_6.ppn node ppn_res_1 = shr(ppn_data_barrier_3.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn[0], UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, ppn_data_barrier_3.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn[0], UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, ppn_data_barrier_3.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) wire _ppn_data_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_9 : UInt<34> connect _ppn_data_WIRE_9, superpage_entries[2].data[0] node _ppn_data_T_62 = bits(_ppn_data_WIRE_9, 0, 0) connect _ppn_data_WIRE_8.fragmented_superpage, _ppn_data_T_62 node _ppn_data_T_63 = bits(_ppn_data_WIRE_9, 1, 1) connect _ppn_data_WIRE_8.c, _ppn_data_T_63 node _ppn_data_T_64 = bits(_ppn_data_WIRE_9, 2, 2) connect _ppn_data_WIRE_8.eff, _ppn_data_T_64 node _ppn_data_T_65 = bits(_ppn_data_WIRE_9, 3, 3) connect _ppn_data_WIRE_8.paa, _ppn_data_T_65 node _ppn_data_T_66 = bits(_ppn_data_WIRE_9, 4, 4) connect _ppn_data_WIRE_8.pal, _ppn_data_T_66 node _ppn_data_T_67 = bits(_ppn_data_WIRE_9, 5, 5) connect _ppn_data_WIRE_8.pr, _ppn_data_T_67 node _ppn_data_T_68 = bits(_ppn_data_WIRE_9, 6, 6) connect _ppn_data_WIRE_8.px, _ppn_data_T_68 node _ppn_data_T_69 = bits(_ppn_data_WIRE_9, 7, 7) connect _ppn_data_WIRE_8.pw, _ppn_data_T_69 node _ppn_data_T_70 = bits(_ppn_data_WIRE_9, 8, 8) connect _ppn_data_WIRE_8.sr, _ppn_data_T_70 node _ppn_data_T_71 = bits(_ppn_data_WIRE_9, 9, 9) connect _ppn_data_WIRE_8.sx, _ppn_data_T_71 node _ppn_data_T_72 = bits(_ppn_data_WIRE_9, 10, 10) connect _ppn_data_WIRE_8.sw, _ppn_data_T_72 node _ppn_data_T_73 = bits(_ppn_data_WIRE_9, 11, 11) connect _ppn_data_WIRE_8.ae, _ppn_data_T_73 node _ppn_data_T_74 = bits(_ppn_data_WIRE_9, 12, 12) connect _ppn_data_WIRE_8.g, _ppn_data_T_74 node _ppn_data_T_75 = bits(_ppn_data_WIRE_9, 13, 13) connect _ppn_data_WIRE_8.u, _ppn_data_T_75 node _ppn_data_T_76 = bits(_ppn_data_WIRE_9, 33, 14) connect _ppn_data_WIRE_8.ppn, _ppn_data_T_76 inst ppn_data_barrier_4 of OptimizationBarrier_EntryData_5 connect ppn_data_barrier_4.clock, clock connect ppn_data_barrier_4.reset, reset connect ppn_data_barrier_4.io.x.fragmented_superpage, _ppn_data_WIRE_8.fragmented_superpage connect ppn_data_barrier_4.io.x.c, _ppn_data_WIRE_8.c connect ppn_data_barrier_4.io.x.eff, _ppn_data_WIRE_8.eff connect ppn_data_barrier_4.io.x.paa, _ppn_data_WIRE_8.paa connect ppn_data_barrier_4.io.x.pal, _ppn_data_WIRE_8.pal connect ppn_data_barrier_4.io.x.pr, _ppn_data_WIRE_8.pr connect ppn_data_barrier_4.io.x.px, _ppn_data_WIRE_8.px connect ppn_data_barrier_4.io.x.pw, _ppn_data_WIRE_8.pw connect ppn_data_barrier_4.io.x.sr, _ppn_data_WIRE_8.sr connect ppn_data_barrier_4.io.x.sx, _ppn_data_WIRE_8.sx connect ppn_data_barrier_4.io.x.sw, _ppn_data_WIRE_8.sw connect ppn_data_barrier_4.io.x.ae, _ppn_data_WIRE_8.ae connect ppn_data_barrier_4.io.x.g, _ppn_data_WIRE_8.g connect ppn_data_barrier_4.io.x.u, _ppn_data_WIRE_8.u connect ppn_data_barrier_4.io.x.ppn, _ppn_data_WIRE_8.ppn node ppn_res_2 = shr(ppn_data_barrier_4.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn[0], UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, ppn_data_barrier_4.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn[0], UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, ppn_data_barrier_4.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) wire _ppn_data_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_11 : UInt<34> connect _ppn_data_WIRE_11, superpage_entries[3].data[0] node _ppn_data_T_77 = bits(_ppn_data_WIRE_11, 0, 0) connect _ppn_data_WIRE_10.fragmented_superpage, _ppn_data_T_77 node _ppn_data_T_78 = bits(_ppn_data_WIRE_11, 1, 1) connect _ppn_data_WIRE_10.c, _ppn_data_T_78 node _ppn_data_T_79 = bits(_ppn_data_WIRE_11, 2, 2) connect _ppn_data_WIRE_10.eff, _ppn_data_T_79 node _ppn_data_T_80 = bits(_ppn_data_WIRE_11, 3, 3) connect _ppn_data_WIRE_10.paa, _ppn_data_T_80 node _ppn_data_T_81 = bits(_ppn_data_WIRE_11, 4, 4) connect _ppn_data_WIRE_10.pal, _ppn_data_T_81 node _ppn_data_T_82 = bits(_ppn_data_WIRE_11, 5, 5) connect _ppn_data_WIRE_10.pr, _ppn_data_T_82 node _ppn_data_T_83 = bits(_ppn_data_WIRE_11, 6, 6) connect _ppn_data_WIRE_10.px, _ppn_data_T_83 node _ppn_data_T_84 = bits(_ppn_data_WIRE_11, 7, 7) connect _ppn_data_WIRE_10.pw, _ppn_data_T_84 node _ppn_data_T_85 = bits(_ppn_data_WIRE_11, 8, 8) connect _ppn_data_WIRE_10.sr, _ppn_data_T_85 node _ppn_data_T_86 = bits(_ppn_data_WIRE_11, 9, 9) connect _ppn_data_WIRE_10.sx, _ppn_data_T_86 node _ppn_data_T_87 = bits(_ppn_data_WIRE_11, 10, 10) connect _ppn_data_WIRE_10.sw, _ppn_data_T_87 node _ppn_data_T_88 = bits(_ppn_data_WIRE_11, 11, 11) connect _ppn_data_WIRE_10.ae, _ppn_data_T_88 node _ppn_data_T_89 = bits(_ppn_data_WIRE_11, 12, 12) connect _ppn_data_WIRE_10.g, _ppn_data_T_89 node _ppn_data_T_90 = bits(_ppn_data_WIRE_11, 13, 13) connect _ppn_data_WIRE_10.u, _ppn_data_T_90 node _ppn_data_T_91 = bits(_ppn_data_WIRE_11, 33, 14) connect _ppn_data_WIRE_10.ppn, _ppn_data_T_91 inst ppn_data_barrier_5 of OptimizationBarrier_EntryData_6 connect ppn_data_barrier_5.clock, clock connect ppn_data_barrier_5.reset, reset connect ppn_data_barrier_5.io.x.fragmented_superpage, _ppn_data_WIRE_10.fragmented_superpage connect ppn_data_barrier_5.io.x.c, _ppn_data_WIRE_10.c connect ppn_data_barrier_5.io.x.eff, _ppn_data_WIRE_10.eff connect ppn_data_barrier_5.io.x.paa, _ppn_data_WIRE_10.paa connect ppn_data_barrier_5.io.x.pal, _ppn_data_WIRE_10.pal connect ppn_data_barrier_5.io.x.pr, _ppn_data_WIRE_10.pr connect ppn_data_barrier_5.io.x.px, _ppn_data_WIRE_10.px connect ppn_data_barrier_5.io.x.pw, _ppn_data_WIRE_10.pw connect ppn_data_barrier_5.io.x.sr, _ppn_data_WIRE_10.sr connect ppn_data_barrier_5.io.x.sx, _ppn_data_WIRE_10.sx connect ppn_data_barrier_5.io.x.sw, _ppn_data_WIRE_10.sw connect ppn_data_barrier_5.io.x.ae, _ppn_data_WIRE_10.ae connect ppn_data_barrier_5.io.x.g, _ppn_data_WIRE_10.g connect ppn_data_barrier_5.io.x.u, _ppn_data_WIRE_10.u connect ppn_data_barrier_5.io.x.ppn, _ppn_data_WIRE_10.ppn node ppn_res_3 = shr(ppn_data_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn[0], UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, ppn_data_barrier_5.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn[0], UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, ppn_data_barrier_5.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) wire _ppn_data_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _ppn_data_WIRE_13 : UInt<34> connect _ppn_data_WIRE_13, special_entry.data[0] node _ppn_data_T_92 = bits(_ppn_data_WIRE_13, 0, 0) connect _ppn_data_WIRE_12.fragmented_superpage, _ppn_data_T_92 node _ppn_data_T_93 = bits(_ppn_data_WIRE_13, 1, 1) connect _ppn_data_WIRE_12.c, _ppn_data_T_93 node _ppn_data_T_94 = bits(_ppn_data_WIRE_13, 2, 2) connect _ppn_data_WIRE_12.eff, _ppn_data_T_94 node _ppn_data_T_95 = bits(_ppn_data_WIRE_13, 3, 3) connect _ppn_data_WIRE_12.paa, _ppn_data_T_95 node _ppn_data_T_96 = bits(_ppn_data_WIRE_13, 4, 4) connect _ppn_data_WIRE_12.pal, _ppn_data_T_96 node _ppn_data_T_97 = bits(_ppn_data_WIRE_13, 5, 5) connect _ppn_data_WIRE_12.pr, _ppn_data_T_97 node _ppn_data_T_98 = bits(_ppn_data_WIRE_13, 6, 6) connect _ppn_data_WIRE_12.px, _ppn_data_T_98 node _ppn_data_T_99 = bits(_ppn_data_WIRE_13, 7, 7) connect _ppn_data_WIRE_12.pw, _ppn_data_T_99 node _ppn_data_T_100 = bits(_ppn_data_WIRE_13, 8, 8) connect _ppn_data_WIRE_12.sr, _ppn_data_T_100 node _ppn_data_T_101 = bits(_ppn_data_WIRE_13, 9, 9) connect _ppn_data_WIRE_12.sx, _ppn_data_T_101 node _ppn_data_T_102 = bits(_ppn_data_WIRE_13, 10, 10) connect _ppn_data_WIRE_12.sw, _ppn_data_T_102 node _ppn_data_T_103 = bits(_ppn_data_WIRE_13, 11, 11) connect _ppn_data_WIRE_12.ae, _ppn_data_T_103 node _ppn_data_T_104 = bits(_ppn_data_WIRE_13, 12, 12) connect _ppn_data_WIRE_12.g, _ppn_data_T_104 node _ppn_data_T_105 = bits(_ppn_data_WIRE_13, 13, 13) connect _ppn_data_WIRE_12.u, _ppn_data_T_105 node _ppn_data_T_106 = bits(_ppn_data_WIRE_13, 33, 14) connect _ppn_data_WIRE_12.ppn, _ppn_data_T_106 inst ppn_data_barrier_6 of OptimizationBarrier_EntryData_7 connect ppn_data_barrier_6.clock, clock connect ppn_data_barrier_6.reset, reset connect ppn_data_barrier_6.io.x.fragmented_superpage, _ppn_data_WIRE_12.fragmented_superpage connect ppn_data_barrier_6.io.x.c, _ppn_data_WIRE_12.c connect ppn_data_barrier_6.io.x.eff, _ppn_data_WIRE_12.eff connect ppn_data_barrier_6.io.x.paa, _ppn_data_WIRE_12.paa connect ppn_data_barrier_6.io.x.pal, _ppn_data_WIRE_12.pal connect ppn_data_barrier_6.io.x.pr, _ppn_data_WIRE_12.pr connect ppn_data_barrier_6.io.x.px, _ppn_data_WIRE_12.px connect ppn_data_barrier_6.io.x.pw, _ppn_data_WIRE_12.pw connect ppn_data_barrier_6.io.x.sr, _ppn_data_WIRE_12.sr connect ppn_data_barrier_6.io.x.sx, _ppn_data_WIRE_12.sx connect ppn_data_barrier_6.io.x.sw, _ppn_data_WIRE_12.sw connect ppn_data_barrier_6.io.x.ae, _ppn_data_WIRE_12.ae connect ppn_data_barrier_6.io.x.g, _ppn_data_WIRE_12.g connect ppn_data_barrier_6.io.x.u, _ppn_data_WIRE_12.u connect ppn_data_barrier_6.io.x.ppn, _ppn_data_WIRE_12.ppn node ppn_res_4 = shr(ppn_data_barrier_6.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn[0], UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, ppn_data_barrier_6.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn[0], UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, ppn_data_barrier_6.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn[0], 19, 0) node _ppn_T_42 = mux(hitsVec[0][0], ppn_data_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec[0][1], ppn_data_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec[0][2], _ppn_T_8, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec[0][3], _ppn_T_16, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec[0][4], _ppn_T_24, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec[0][5], _ppn_T_32, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec[0][6], _ppn_T_40, UInt<1>(0h0)) node _ppn_T_49 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_50 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_51 = or(_ppn_T_50, _ppn_T_44) node _ppn_T_52 = or(_ppn_T_51, _ppn_T_45) node _ppn_T_53 = or(_ppn_T_52, _ppn_T_46) node _ppn_T_54 = or(_ppn_T_53, _ppn_T_47) node _ppn_T_55 = or(_ppn_T_54, _ppn_T_48) node _ppn_T_56 = or(_ppn_T_55, _ppn_T_49) wire _ppn_WIRE : UInt<20> connect _ppn_WIRE, _ppn_T_56 wire ppn : UInt<20>[1] connect ppn[0], _ppn_WIRE when do_refill : wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable[0] connect newEntry.u, io.ptw.resp.bits.pte.u connect newEntry.g, io.ptw.resp.bits.pte.g connect newEntry.ae, io.ptw.resp.bits.ae_final node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r[0] connect newEntry.pw, prot_w[0] connect newEntry.px, prot_x[0] connect newEntry.pal, prot_al[0] connect newEntry.paa, prot_aa[0] connect newEntry.eff, prot_eff[0] connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag, r_refill_tag node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, newEntry.fragmented_superpage) node special_entry_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node special_entry_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node special_entry_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag, r_refill_tag node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_0_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_0_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag, r_refill_tag node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_1_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_1_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag, r_refill_tag node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_2_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_2_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag, r_refill_tag node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node superpage_entries_3_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae) node superpage_entries_3_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T else : node waddr = mux(r_sectored_hit, r_sectored_hit_addr, r_sectored_repl_addr) node _T_7 = eq(waddr, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) connect sectored_entries[0].tag, r_refill_tag connect sectored_entries[0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0].valid[idx], UInt<1>(0h1) node sectored_entries_0_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_0_data_lo_lo = cat(sectored_entries_0_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_0_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_lo_hi = cat(sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo) node sectored_entries_0_data_lo = cat(sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo) node sectored_entries_0_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_0_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_0_data_hi_lo = cat(sectored_entries_0_data_hi_lo_hi, sectored_entries_0_data_hi_lo_lo) node sectored_entries_0_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_0_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_hi_hi = cat(sectored_entries_0_data_hi_hi_hi, sectored_entries_0_data_hi_hi_lo) node sectored_entries_0_data_hi = cat(sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo) node _sectored_entries_0_data_T = cat(sectored_entries_0_data_hi, sectored_entries_0_data_lo) connect sectored_entries[0].data[idx], _sectored_entries_0_data_T node _T_9 = eq(waddr, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit, UInt<1>(0h0)) when _T_10 : connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) connect sectored_entries[1].tag, r_refill_tag connect sectored_entries[1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[1].valid[idx_1], UInt<1>(0h1) node sectored_entries_1_data_lo_lo_hi = cat(newEntry.eff, newEntry.c) node sectored_entries_1_data_lo_lo = cat(sectored_entries_1_data_lo_lo_hi, newEntry.fragmented_superpage) node sectored_entries_1_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_lo_hi_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_lo_hi = cat(sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo) node sectored_entries_1_data_lo = cat(sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo) node sectored_entries_1_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw) node sectored_entries_1_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx) node sectored_entries_1_data_hi_lo = cat(sectored_entries_1_data_hi_lo_hi, sectored_entries_1_data_hi_lo_lo) node sectored_entries_1_data_hi_hi_lo = cat(newEntry.g, newEntry.ae) node sectored_entries_1_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_hi_hi = cat(sectored_entries_1_data_hi_hi_hi, sectored_entries_1_data_hi_hi_lo) node sectored_entries_1_data_hi = cat(sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo) node _sectored_entries_1_data_T = cat(sectored_entries_1_data_hi, sectored_entries_1_data_lo) connect sectored_entries[1].data[idx_1], _sectored_entries_1_data_T node _entries_T = bits(vpn[0], 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<34> connect _entries_WIRE_1, sectored_entries[0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.sr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.sx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.sw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.ae, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.g, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.u, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 33, 14) connect _entries_WIRE.ppn, _entries_T_15 inst entries_barrier of OptimizationBarrier_EntryData_8 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.ae, _entries_WIRE.ae connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_16 = bits(vpn[0], 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<34> connect _entries_WIRE_3, sectored_entries[1].data[_entries_T_16] node _entries_T_17 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.pr, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.px, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.pw, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.sr, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.sx, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.sw, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.ae, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.g, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.u, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 33, 14) connect _entries_WIRE_2.ppn, _entries_T_31 inst entries_barrier_1 of OptimizationBarrier_EntryData_9 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.ae, _entries_WIRE_2.ae connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<34> connect _entries_WIRE_5, superpage_entries[0].data[0] node _entries_T_32 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.pr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.px, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.pw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.sr, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.sx, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.sw, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.ae, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.g, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.u, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_5, 33, 14) connect _entries_WIRE_4.ppn, _entries_T_46 inst entries_barrier_2 of OptimizationBarrier_EntryData_10 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.ae, _entries_WIRE_4.ae connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<34> connect _entries_WIRE_7, superpage_entries[1].data[0] node _entries_T_47 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.pr, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.px, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.pw, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.sr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.sx, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.sw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.ae, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.g, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.u, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_7, 33, 14) connect _entries_WIRE_6.ppn, _entries_T_61 inst entries_barrier_3 of OptimizationBarrier_EntryData_11 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.ae, _entries_WIRE_6.ae connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<34> connect _entries_WIRE_9, superpage_entries[2].data[0] node _entries_T_62 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.pr, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.px, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.pw, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.sr, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.sx, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.sw, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.ae, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.g, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.u, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_9, 33, 14) connect _entries_WIRE_8.ppn, _entries_T_76 inst entries_barrier_4 of OptimizationBarrier_EntryData_12 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.ae, _entries_WIRE_8.ae connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<34> connect _entries_WIRE_11, superpage_entries[3].data[0] node _entries_T_77 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.pr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.px, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.pw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.ae, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.g, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.u, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_11, 33, 14) connect _entries_WIRE_10.ppn, _entries_T_91 inst entries_barrier_5 of OptimizationBarrier_EntryData_13 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.ae, _entries_WIRE_10.ae connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<34> connect _entries_WIRE_13, special_entry.data[0] node _entries_T_92 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.pr, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.px, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.pw, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.sr, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.sx, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.sw, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.ae, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.g, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.u, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_13, 33, 14) connect _entries_WIRE_12.ppn, _entries_T_106 inst entries_barrier_6 of OptimizationBarrier_EntryData_14 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.ae, _entries_WIRE_12.ae connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[7] connect _entries_WIRE_14[0], entries_barrier.io.y connect _entries_WIRE_14[1], entries_barrier_1.io.y connect _entries_WIRE_14[2], entries_barrier_2.io.y connect _entries_WIRE_14[3], entries_barrier_3.io.y connect _entries_WIRE_14[4], entries_barrier_4.io.y connect _entries_WIRE_14[5], entries_barrier_5.io.y connect _entries_WIRE_14[6], entries_barrier_6.io.y wire entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[7][1] connect entries[0], _entries_WIRE_14 node _normal_entries_T = bits(vpn[0], 1, 0) wire _normal_entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_1 : UInt<34> connect _normal_entries_WIRE_1, sectored_entries[0].data[_normal_entries_T] node _normal_entries_T_1 = bits(_normal_entries_WIRE_1, 0, 0) connect _normal_entries_WIRE.fragmented_superpage, _normal_entries_T_1 node _normal_entries_T_2 = bits(_normal_entries_WIRE_1, 1, 1) connect _normal_entries_WIRE.c, _normal_entries_T_2 node _normal_entries_T_3 = bits(_normal_entries_WIRE_1, 2, 2) connect _normal_entries_WIRE.eff, _normal_entries_T_3 node _normal_entries_T_4 = bits(_normal_entries_WIRE_1, 3, 3) connect _normal_entries_WIRE.paa, _normal_entries_T_4 node _normal_entries_T_5 = bits(_normal_entries_WIRE_1, 4, 4) connect _normal_entries_WIRE.pal, _normal_entries_T_5 node _normal_entries_T_6 = bits(_normal_entries_WIRE_1, 5, 5) connect _normal_entries_WIRE.pr, _normal_entries_T_6 node _normal_entries_T_7 = bits(_normal_entries_WIRE_1, 6, 6) connect _normal_entries_WIRE.px, _normal_entries_T_7 node _normal_entries_T_8 = bits(_normal_entries_WIRE_1, 7, 7) connect _normal_entries_WIRE.pw, _normal_entries_T_8 node _normal_entries_T_9 = bits(_normal_entries_WIRE_1, 8, 8) connect _normal_entries_WIRE.sr, _normal_entries_T_9 node _normal_entries_T_10 = bits(_normal_entries_WIRE_1, 9, 9) connect _normal_entries_WIRE.sx, _normal_entries_T_10 node _normal_entries_T_11 = bits(_normal_entries_WIRE_1, 10, 10) connect _normal_entries_WIRE.sw, _normal_entries_T_11 node _normal_entries_T_12 = bits(_normal_entries_WIRE_1, 11, 11) connect _normal_entries_WIRE.ae, _normal_entries_T_12 node _normal_entries_T_13 = bits(_normal_entries_WIRE_1, 12, 12) connect _normal_entries_WIRE.g, _normal_entries_T_13 node _normal_entries_T_14 = bits(_normal_entries_WIRE_1, 13, 13) connect _normal_entries_WIRE.u, _normal_entries_T_14 node _normal_entries_T_15 = bits(_normal_entries_WIRE_1, 33, 14) connect _normal_entries_WIRE.ppn, _normal_entries_T_15 inst normal_entries_barrier of OptimizationBarrier_EntryData_15 connect normal_entries_barrier.clock, clock connect normal_entries_barrier.reset, reset connect normal_entries_barrier.io.x.fragmented_superpage, _normal_entries_WIRE.fragmented_superpage connect normal_entries_barrier.io.x.c, _normal_entries_WIRE.c connect normal_entries_barrier.io.x.eff, _normal_entries_WIRE.eff connect normal_entries_barrier.io.x.paa, _normal_entries_WIRE.paa connect normal_entries_barrier.io.x.pal, _normal_entries_WIRE.pal connect normal_entries_barrier.io.x.pr, _normal_entries_WIRE.pr connect normal_entries_barrier.io.x.px, _normal_entries_WIRE.px connect normal_entries_barrier.io.x.pw, _normal_entries_WIRE.pw connect normal_entries_barrier.io.x.sr, _normal_entries_WIRE.sr connect normal_entries_barrier.io.x.sx, _normal_entries_WIRE.sx connect normal_entries_barrier.io.x.sw, _normal_entries_WIRE.sw connect normal_entries_barrier.io.x.ae, _normal_entries_WIRE.ae connect normal_entries_barrier.io.x.g, _normal_entries_WIRE.g connect normal_entries_barrier.io.x.u, _normal_entries_WIRE.u connect normal_entries_barrier.io.x.ppn, _normal_entries_WIRE.ppn node _normal_entries_T_16 = bits(vpn[0], 1, 0) wire _normal_entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_3 : UInt<34> connect _normal_entries_WIRE_3, sectored_entries[1].data[_normal_entries_T_16] node _normal_entries_T_17 = bits(_normal_entries_WIRE_3, 0, 0) connect _normal_entries_WIRE_2.fragmented_superpage, _normal_entries_T_17 node _normal_entries_T_18 = bits(_normal_entries_WIRE_3, 1, 1) connect _normal_entries_WIRE_2.c, _normal_entries_T_18 node _normal_entries_T_19 = bits(_normal_entries_WIRE_3, 2, 2) connect _normal_entries_WIRE_2.eff, _normal_entries_T_19 node _normal_entries_T_20 = bits(_normal_entries_WIRE_3, 3, 3) connect _normal_entries_WIRE_2.paa, _normal_entries_T_20 node _normal_entries_T_21 = bits(_normal_entries_WIRE_3, 4, 4) connect _normal_entries_WIRE_2.pal, _normal_entries_T_21 node _normal_entries_T_22 = bits(_normal_entries_WIRE_3, 5, 5) connect _normal_entries_WIRE_2.pr, _normal_entries_T_22 node _normal_entries_T_23 = bits(_normal_entries_WIRE_3, 6, 6) connect _normal_entries_WIRE_2.px, _normal_entries_T_23 node _normal_entries_T_24 = bits(_normal_entries_WIRE_3, 7, 7) connect _normal_entries_WIRE_2.pw, _normal_entries_T_24 node _normal_entries_T_25 = bits(_normal_entries_WIRE_3, 8, 8) connect _normal_entries_WIRE_2.sr, _normal_entries_T_25 node _normal_entries_T_26 = bits(_normal_entries_WIRE_3, 9, 9) connect _normal_entries_WIRE_2.sx, _normal_entries_T_26 node _normal_entries_T_27 = bits(_normal_entries_WIRE_3, 10, 10) connect _normal_entries_WIRE_2.sw, _normal_entries_T_27 node _normal_entries_T_28 = bits(_normal_entries_WIRE_3, 11, 11) connect _normal_entries_WIRE_2.ae, _normal_entries_T_28 node _normal_entries_T_29 = bits(_normal_entries_WIRE_3, 12, 12) connect _normal_entries_WIRE_2.g, _normal_entries_T_29 node _normal_entries_T_30 = bits(_normal_entries_WIRE_3, 13, 13) connect _normal_entries_WIRE_2.u, _normal_entries_T_30 node _normal_entries_T_31 = bits(_normal_entries_WIRE_3, 33, 14) connect _normal_entries_WIRE_2.ppn, _normal_entries_T_31 inst normal_entries_barrier_1 of OptimizationBarrier_EntryData_16 connect normal_entries_barrier_1.clock, clock connect normal_entries_barrier_1.reset, reset connect normal_entries_barrier_1.io.x.fragmented_superpage, _normal_entries_WIRE_2.fragmented_superpage connect normal_entries_barrier_1.io.x.c, _normal_entries_WIRE_2.c connect normal_entries_barrier_1.io.x.eff, _normal_entries_WIRE_2.eff connect normal_entries_barrier_1.io.x.paa, _normal_entries_WIRE_2.paa connect normal_entries_barrier_1.io.x.pal, _normal_entries_WIRE_2.pal connect normal_entries_barrier_1.io.x.pr, _normal_entries_WIRE_2.pr connect normal_entries_barrier_1.io.x.px, _normal_entries_WIRE_2.px connect normal_entries_barrier_1.io.x.pw, _normal_entries_WIRE_2.pw connect normal_entries_barrier_1.io.x.sr, _normal_entries_WIRE_2.sr connect normal_entries_barrier_1.io.x.sx, _normal_entries_WIRE_2.sx connect normal_entries_barrier_1.io.x.sw, _normal_entries_WIRE_2.sw connect normal_entries_barrier_1.io.x.ae, _normal_entries_WIRE_2.ae connect normal_entries_barrier_1.io.x.g, _normal_entries_WIRE_2.g connect normal_entries_barrier_1.io.x.u, _normal_entries_WIRE_2.u connect normal_entries_barrier_1.io.x.ppn, _normal_entries_WIRE_2.ppn wire _normal_entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_5 : UInt<34> connect _normal_entries_WIRE_5, superpage_entries[0].data[0] node _normal_entries_T_32 = bits(_normal_entries_WIRE_5, 0, 0) connect _normal_entries_WIRE_4.fragmented_superpage, _normal_entries_T_32 node _normal_entries_T_33 = bits(_normal_entries_WIRE_5, 1, 1) connect _normal_entries_WIRE_4.c, _normal_entries_T_33 node _normal_entries_T_34 = bits(_normal_entries_WIRE_5, 2, 2) connect _normal_entries_WIRE_4.eff, _normal_entries_T_34 node _normal_entries_T_35 = bits(_normal_entries_WIRE_5, 3, 3) connect _normal_entries_WIRE_4.paa, _normal_entries_T_35 node _normal_entries_T_36 = bits(_normal_entries_WIRE_5, 4, 4) connect _normal_entries_WIRE_4.pal, _normal_entries_T_36 node _normal_entries_T_37 = bits(_normal_entries_WIRE_5, 5, 5) connect _normal_entries_WIRE_4.pr, _normal_entries_T_37 node _normal_entries_T_38 = bits(_normal_entries_WIRE_5, 6, 6) connect _normal_entries_WIRE_4.px, _normal_entries_T_38 node _normal_entries_T_39 = bits(_normal_entries_WIRE_5, 7, 7) connect _normal_entries_WIRE_4.pw, _normal_entries_T_39 node _normal_entries_T_40 = bits(_normal_entries_WIRE_5, 8, 8) connect _normal_entries_WIRE_4.sr, _normal_entries_T_40 node _normal_entries_T_41 = bits(_normal_entries_WIRE_5, 9, 9) connect _normal_entries_WIRE_4.sx, _normal_entries_T_41 node _normal_entries_T_42 = bits(_normal_entries_WIRE_5, 10, 10) connect _normal_entries_WIRE_4.sw, _normal_entries_T_42 node _normal_entries_T_43 = bits(_normal_entries_WIRE_5, 11, 11) connect _normal_entries_WIRE_4.ae, _normal_entries_T_43 node _normal_entries_T_44 = bits(_normal_entries_WIRE_5, 12, 12) connect _normal_entries_WIRE_4.g, _normal_entries_T_44 node _normal_entries_T_45 = bits(_normal_entries_WIRE_5, 13, 13) connect _normal_entries_WIRE_4.u, _normal_entries_T_45 node _normal_entries_T_46 = bits(_normal_entries_WIRE_5, 33, 14) connect _normal_entries_WIRE_4.ppn, _normal_entries_T_46 inst normal_entries_barrier_2 of OptimizationBarrier_EntryData_17 connect normal_entries_barrier_2.clock, clock connect normal_entries_barrier_2.reset, reset connect normal_entries_barrier_2.io.x.fragmented_superpage, _normal_entries_WIRE_4.fragmented_superpage connect normal_entries_barrier_2.io.x.c, _normal_entries_WIRE_4.c connect normal_entries_barrier_2.io.x.eff, _normal_entries_WIRE_4.eff connect normal_entries_barrier_2.io.x.paa, _normal_entries_WIRE_4.paa connect normal_entries_barrier_2.io.x.pal, _normal_entries_WIRE_4.pal connect normal_entries_barrier_2.io.x.pr, _normal_entries_WIRE_4.pr connect normal_entries_barrier_2.io.x.px, _normal_entries_WIRE_4.px connect normal_entries_barrier_2.io.x.pw, _normal_entries_WIRE_4.pw connect normal_entries_barrier_2.io.x.sr, _normal_entries_WIRE_4.sr connect normal_entries_barrier_2.io.x.sx, _normal_entries_WIRE_4.sx connect normal_entries_barrier_2.io.x.sw, _normal_entries_WIRE_4.sw connect normal_entries_barrier_2.io.x.ae, _normal_entries_WIRE_4.ae connect normal_entries_barrier_2.io.x.g, _normal_entries_WIRE_4.g connect normal_entries_barrier_2.io.x.u, _normal_entries_WIRE_4.u connect normal_entries_barrier_2.io.x.ppn, _normal_entries_WIRE_4.ppn wire _normal_entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_7 : UInt<34> connect _normal_entries_WIRE_7, superpage_entries[1].data[0] node _normal_entries_T_47 = bits(_normal_entries_WIRE_7, 0, 0) connect _normal_entries_WIRE_6.fragmented_superpage, _normal_entries_T_47 node _normal_entries_T_48 = bits(_normal_entries_WIRE_7, 1, 1) connect _normal_entries_WIRE_6.c, _normal_entries_T_48 node _normal_entries_T_49 = bits(_normal_entries_WIRE_7, 2, 2) connect _normal_entries_WIRE_6.eff, _normal_entries_T_49 node _normal_entries_T_50 = bits(_normal_entries_WIRE_7, 3, 3) connect _normal_entries_WIRE_6.paa, _normal_entries_T_50 node _normal_entries_T_51 = bits(_normal_entries_WIRE_7, 4, 4) connect _normal_entries_WIRE_6.pal, _normal_entries_T_51 node _normal_entries_T_52 = bits(_normal_entries_WIRE_7, 5, 5) connect _normal_entries_WIRE_6.pr, _normal_entries_T_52 node _normal_entries_T_53 = bits(_normal_entries_WIRE_7, 6, 6) connect _normal_entries_WIRE_6.px, _normal_entries_T_53 node _normal_entries_T_54 = bits(_normal_entries_WIRE_7, 7, 7) connect _normal_entries_WIRE_6.pw, _normal_entries_T_54 node _normal_entries_T_55 = bits(_normal_entries_WIRE_7, 8, 8) connect _normal_entries_WIRE_6.sr, _normal_entries_T_55 node _normal_entries_T_56 = bits(_normal_entries_WIRE_7, 9, 9) connect _normal_entries_WIRE_6.sx, _normal_entries_T_56 node _normal_entries_T_57 = bits(_normal_entries_WIRE_7, 10, 10) connect _normal_entries_WIRE_6.sw, _normal_entries_T_57 node _normal_entries_T_58 = bits(_normal_entries_WIRE_7, 11, 11) connect _normal_entries_WIRE_6.ae, _normal_entries_T_58 node _normal_entries_T_59 = bits(_normal_entries_WIRE_7, 12, 12) connect _normal_entries_WIRE_6.g, _normal_entries_T_59 node _normal_entries_T_60 = bits(_normal_entries_WIRE_7, 13, 13) connect _normal_entries_WIRE_6.u, _normal_entries_T_60 node _normal_entries_T_61 = bits(_normal_entries_WIRE_7, 33, 14) connect _normal_entries_WIRE_6.ppn, _normal_entries_T_61 inst normal_entries_barrier_3 of OptimizationBarrier_EntryData_18 connect normal_entries_barrier_3.clock, clock connect normal_entries_barrier_3.reset, reset connect normal_entries_barrier_3.io.x.fragmented_superpage, _normal_entries_WIRE_6.fragmented_superpage connect normal_entries_barrier_3.io.x.c, _normal_entries_WIRE_6.c connect normal_entries_barrier_3.io.x.eff, _normal_entries_WIRE_6.eff connect normal_entries_barrier_3.io.x.paa, _normal_entries_WIRE_6.paa connect normal_entries_barrier_3.io.x.pal, _normal_entries_WIRE_6.pal connect normal_entries_barrier_3.io.x.pr, _normal_entries_WIRE_6.pr connect normal_entries_barrier_3.io.x.px, _normal_entries_WIRE_6.px connect normal_entries_barrier_3.io.x.pw, _normal_entries_WIRE_6.pw connect normal_entries_barrier_3.io.x.sr, _normal_entries_WIRE_6.sr connect normal_entries_barrier_3.io.x.sx, _normal_entries_WIRE_6.sx connect normal_entries_barrier_3.io.x.sw, _normal_entries_WIRE_6.sw connect normal_entries_barrier_3.io.x.ae, _normal_entries_WIRE_6.ae connect normal_entries_barrier_3.io.x.g, _normal_entries_WIRE_6.g connect normal_entries_barrier_3.io.x.u, _normal_entries_WIRE_6.u connect normal_entries_barrier_3.io.x.ppn, _normal_entries_WIRE_6.ppn wire _normal_entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_9 : UInt<34> connect _normal_entries_WIRE_9, superpage_entries[2].data[0] node _normal_entries_T_62 = bits(_normal_entries_WIRE_9, 0, 0) connect _normal_entries_WIRE_8.fragmented_superpage, _normal_entries_T_62 node _normal_entries_T_63 = bits(_normal_entries_WIRE_9, 1, 1) connect _normal_entries_WIRE_8.c, _normal_entries_T_63 node _normal_entries_T_64 = bits(_normal_entries_WIRE_9, 2, 2) connect _normal_entries_WIRE_8.eff, _normal_entries_T_64 node _normal_entries_T_65 = bits(_normal_entries_WIRE_9, 3, 3) connect _normal_entries_WIRE_8.paa, _normal_entries_T_65 node _normal_entries_T_66 = bits(_normal_entries_WIRE_9, 4, 4) connect _normal_entries_WIRE_8.pal, _normal_entries_T_66 node _normal_entries_T_67 = bits(_normal_entries_WIRE_9, 5, 5) connect _normal_entries_WIRE_8.pr, _normal_entries_T_67 node _normal_entries_T_68 = bits(_normal_entries_WIRE_9, 6, 6) connect _normal_entries_WIRE_8.px, _normal_entries_T_68 node _normal_entries_T_69 = bits(_normal_entries_WIRE_9, 7, 7) connect _normal_entries_WIRE_8.pw, _normal_entries_T_69 node _normal_entries_T_70 = bits(_normal_entries_WIRE_9, 8, 8) connect _normal_entries_WIRE_8.sr, _normal_entries_T_70 node _normal_entries_T_71 = bits(_normal_entries_WIRE_9, 9, 9) connect _normal_entries_WIRE_8.sx, _normal_entries_T_71 node _normal_entries_T_72 = bits(_normal_entries_WIRE_9, 10, 10) connect _normal_entries_WIRE_8.sw, _normal_entries_T_72 node _normal_entries_T_73 = bits(_normal_entries_WIRE_9, 11, 11) connect _normal_entries_WIRE_8.ae, _normal_entries_T_73 node _normal_entries_T_74 = bits(_normal_entries_WIRE_9, 12, 12) connect _normal_entries_WIRE_8.g, _normal_entries_T_74 node _normal_entries_T_75 = bits(_normal_entries_WIRE_9, 13, 13) connect _normal_entries_WIRE_8.u, _normal_entries_T_75 node _normal_entries_T_76 = bits(_normal_entries_WIRE_9, 33, 14) connect _normal_entries_WIRE_8.ppn, _normal_entries_T_76 inst normal_entries_barrier_4 of OptimizationBarrier_EntryData_19 connect normal_entries_barrier_4.clock, clock connect normal_entries_barrier_4.reset, reset connect normal_entries_barrier_4.io.x.fragmented_superpage, _normal_entries_WIRE_8.fragmented_superpage connect normal_entries_barrier_4.io.x.c, _normal_entries_WIRE_8.c connect normal_entries_barrier_4.io.x.eff, _normal_entries_WIRE_8.eff connect normal_entries_barrier_4.io.x.paa, _normal_entries_WIRE_8.paa connect normal_entries_barrier_4.io.x.pal, _normal_entries_WIRE_8.pal connect normal_entries_barrier_4.io.x.pr, _normal_entries_WIRE_8.pr connect normal_entries_barrier_4.io.x.px, _normal_entries_WIRE_8.px connect normal_entries_barrier_4.io.x.pw, _normal_entries_WIRE_8.pw connect normal_entries_barrier_4.io.x.sr, _normal_entries_WIRE_8.sr connect normal_entries_barrier_4.io.x.sx, _normal_entries_WIRE_8.sx connect normal_entries_barrier_4.io.x.sw, _normal_entries_WIRE_8.sw connect normal_entries_barrier_4.io.x.ae, _normal_entries_WIRE_8.ae connect normal_entries_barrier_4.io.x.g, _normal_entries_WIRE_8.g connect normal_entries_barrier_4.io.x.u, _normal_entries_WIRE_8.u connect normal_entries_barrier_4.io.x.ppn, _normal_entries_WIRE_8.ppn wire _normal_entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _normal_entries_WIRE_11 : UInt<34> connect _normal_entries_WIRE_11, superpage_entries[3].data[0] node _normal_entries_T_77 = bits(_normal_entries_WIRE_11, 0, 0) connect _normal_entries_WIRE_10.fragmented_superpage, _normal_entries_T_77 node _normal_entries_T_78 = bits(_normal_entries_WIRE_11, 1, 1) connect _normal_entries_WIRE_10.c, _normal_entries_T_78 node _normal_entries_T_79 = bits(_normal_entries_WIRE_11, 2, 2) connect _normal_entries_WIRE_10.eff, _normal_entries_T_79 node _normal_entries_T_80 = bits(_normal_entries_WIRE_11, 3, 3) connect _normal_entries_WIRE_10.paa, _normal_entries_T_80 node _normal_entries_T_81 = bits(_normal_entries_WIRE_11, 4, 4) connect _normal_entries_WIRE_10.pal, _normal_entries_T_81 node _normal_entries_T_82 = bits(_normal_entries_WIRE_11, 5, 5) connect _normal_entries_WIRE_10.pr, _normal_entries_T_82 node _normal_entries_T_83 = bits(_normal_entries_WIRE_11, 6, 6) connect _normal_entries_WIRE_10.px, _normal_entries_T_83 node _normal_entries_T_84 = bits(_normal_entries_WIRE_11, 7, 7) connect _normal_entries_WIRE_10.pw, _normal_entries_T_84 node _normal_entries_T_85 = bits(_normal_entries_WIRE_11, 8, 8) connect _normal_entries_WIRE_10.sr, _normal_entries_T_85 node _normal_entries_T_86 = bits(_normal_entries_WIRE_11, 9, 9) connect _normal_entries_WIRE_10.sx, _normal_entries_T_86 node _normal_entries_T_87 = bits(_normal_entries_WIRE_11, 10, 10) connect _normal_entries_WIRE_10.sw, _normal_entries_T_87 node _normal_entries_T_88 = bits(_normal_entries_WIRE_11, 11, 11) connect _normal_entries_WIRE_10.ae, _normal_entries_T_88 node _normal_entries_T_89 = bits(_normal_entries_WIRE_11, 12, 12) connect _normal_entries_WIRE_10.g, _normal_entries_T_89 node _normal_entries_T_90 = bits(_normal_entries_WIRE_11, 13, 13) connect _normal_entries_WIRE_10.u, _normal_entries_T_90 node _normal_entries_T_91 = bits(_normal_entries_WIRE_11, 33, 14) connect _normal_entries_WIRE_10.ppn, _normal_entries_T_91 inst normal_entries_barrier_5 of OptimizationBarrier_EntryData_20 connect normal_entries_barrier_5.clock, clock connect normal_entries_barrier_5.reset, reset connect normal_entries_barrier_5.io.x.fragmented_superpage, _normal_entries_WIRE_10.fragmented_superpage connect normal_entries_barrier_5.io.x.c, _normal_entries_WIRE_10.c connect normal_entries_barrier_5.io.x.eff, _normal_entries_WIRE_10.eff connect normal_entries_barrier_5.io.x.paa, _normal_entries_WIRE_10.paa connect normal_entries_barrier_5.io.x.pal, _normal_entries_WIRE_10.pal connect normal_entries_barrier_5.io.x.pr, _normal_entries_WIRE_10.pr connect normal_entries_barrier_5.io.x.px, _normal_entries_WIRE_10.px connect normal_entries_barrier_5.io.x.pw, _normal_entries_WIRE_10.pw connect normal_entries_barrier_5.io.x.sr, _normal_entries_WIRE_10.sr connect normal_entries_barrier_5.io.x.sx, _normal_entries_WIRE_10.sx connect normal_entries_barrier_5.io.x.sw, _normal_entries_WIRE_10.sw connect normal_entries_barrier_5.io.x.ae, _normal_entries_WIRE_10.ae connect normal_entries_barrier_5.io.x.g, _normal_entries_WIRE_10.g connect normal_entries_barrier_5.io.x.u, _normal_entries_WIRE_10.u connect normal_entries_barrier_5.io.x.ppn, _normal_entries_WIRE_10.ppn wire _normal_entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[6] connect _normal_entries_WIRE_12[0], normal_entries_barrier.io.y connect _normal_entries_WIRE_12[1], normal_entries_barrier_1.io.y connect _normal_entries_WIRE_12[2], normal_entries_barrier_2.io.y connect _normal_entries_WIRE_12[3], normal_entries_barrier_3.io.y connect _normal_entries_WIRE_12[4], normal_entries_barrier_4.io.y connect _normal_entries_WIRE_12[5], normal_entries_barrier_5.io.y wire normal_entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[6][1] connect normal_entries[0], _normal_entries_WIRE_12 node ptw_ae_array_lo_hi = cat(entries[0][2].ae, entries[0][1].ae) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries[0][0].ae) node ptw_ae_array_hi_lo = cat(entries[0][4].ae, entries[0][3].ae) node ptw_ae_array_hi_hi = cat(entries[0][6].ae, entries[0][5].ae) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node _ptw_ae_array_T_1 = cat(UInt<1>(0h0), _ptw_ae_array_T) wire ptw_ae_array : UInt<8>[1] connect ptw_ae_array[0], _ptw_ae_array_T_1 node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, io.ptw.status.sum) node priv_rw_ok_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries[0][0].u) node priv_rw_ok_hi_lo = cat(entries[0][4].u, entries[0][3].u) node priv_rw_ok_hi_hi = cat(entries[0][6].u, entries[0][5].u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries[0][0].u) node priv_rw_ok_hi_lo_1 = cat(entries[0][4].u, entries[0][3].u) node priv_rw_ok_hi_hi_1 = cat(entries[0][6].u, entries[0][5].u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node _priv_rw_ok_T_7 = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) wire priv_rw_ok : UInt<7>[1] connect priv_rw_ok[0], _priv_rw_ok_T_7 node priv_x_ok_lo_hi = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries[0][0].u) node priv_x_ok_hi_lo = cat(entries[0][4].u, entries[0][3].u) node priv_x_ok_hi_hi = cat(entries[0][6].u, entries[0][5].u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries[0][0].u) node priv_x_ok_hi_lo_1 = cat(entries[0][4].u, entries[0][3].u) node priv_x_ok_hi_hi_1 = cat(entries[0][6].u, entries[0][5].u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node _priv_x_ok_T_3 = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) wire priv_x_ok : UInt<7>[1] connect priv_x_ok[0], _priv_x_ok_T_3 node r_array_lo_hi = cat(entries[0][2].sr, entries[0][1].sr) node r_array_lo = cat(r_array_lo_hi, entries[0][0].sr) node r_array_hi_lo = cat(entries[0][4].sr, entries[0][3].sr) node r_array_hi_hi = cat(entries[0][6].sr, entries[0][5].sr) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries[0][2].sx, entries[0][1].sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries[0][0].sx) node r_array_hi_lo_1 = cat(entries[0][4].sx, entries[0][3].sx) node r_array_hi_hi_1 = cat(entries[0][6].sx, entries[0][5].sx) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(io.ptw.status.mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok[0], _r_array_T_3) node _r_array_T_5 = cat(UInt<1>(0h1), _r_array_T_4) wire r_array : UInt<8>[1] connect r_array[0], _r_array_T_5 node w_array_lo_hi = cat(entries[0][2].sw, entries[0][1].sw) node w_array_lo = cat(w_array_lo_hi, entries[0][0].sw) node w_array_hi_lo = cat(entries[0][4].sw, entries[0][3].sw) node w_array_hi_hi = cat(entries[0][6].sw, entries[0][5].sw) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok[0], _w_array_T) node _w_array_T_2 = cat(UInt<1>(0h1), _w_array_T_1) wire w_array : UInt<8>[1] connect w_array[0], _w_array_T_2 node x_array_lo_hi = cat(entries[0][2].sx, entries[0][1].sx) node x_array_lo = cat(x_array_lo_hi, entries[0][0].sx) node x_array_hi_lo = cat(entries[0][4].sx, entries[0][3].sx) node x_array_hi_hi = cat(entries[0][6].sx, entries[0][5].sx) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok[0], _x_array_T) node _x_array_T_2 = cat(UInt<1>(0h1), _x_array_T_1) wire x_array : UInt<8>[1] connect x_array[0], _x_array_T_2 node _pr_array_T = mux(prot_r[0], UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_hi = cat(normal_entries[0][2].pr, normal_entries[0][1].pr) node pr_array_lo = cat(pr_array_lo_hi, normal_entries[0][0].pr) node pr_array_hi_hi = cat(normal_entries[0][5].pr, normal_entries[0][4].pr) node pr_array_hi = cat(pr_array_hi_hi, normal_entries[0][3].pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = not(ptw_ae_array[0]) node _pr_array_T_4 = and(_pr_array_T_2, _pr_array_T_3) wire pr_array : UInt<8>[1] connect pr_array[0], _pr_array_T_4 node _pw_array_T = mux(prot_w[0], UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_hi = cat(normal_entries[0][2].pw, normal_entries[0][1].pw) node pw_array_lo = cat(pw_array_lo_hi, normal_entries[0][0].pw) node pw_array_hi_hi = cat(normal_entries[0][5].pw, normal_entries[0][4].pw) node pw_array_hi = cat(pw_array_hi_hi, normal_entries[0][3].pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = not(ptw_ae_array[0]) node _pw_array_T_4 = and(_pw_array_T_2, _pw_array_T_3) wire pw_array : UInt<8>[1] connect pw_array[0], _pw_array_T_4 node _px_array_T = mux(prot_x[0], UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_hi = cat(normal_entries[0][2].px, normal_entries[0][1].px) node px_array_lo = cat(px_array_lo_hi, normal_entries[0][0].px) node px_array_hi_hi = cat(normal_entries[0][5].px, normal_entries[0][4].px) node px_array_hi = cat(px_array_hi_hi, normal_entries[0][3].px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = not(ptw_ae_array[0]) node _px_array_T_4 = and(_px_array_T_2, _px_array_T_3) wire px_array : UInt<8>[1] connect px_array[0], _px_array_T_4 node _eff_array_T = mux(prot_eff[0], UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_hi = cat(normal_entries[0][2].eff, normal_entries[0][1].eff) node eff_array_lo = cat(eff_array_lo_hi, normal_entries[0][0].eff) node eff_array_hi_hi = cat(normal_entries[0][5].eff, normal_entries[0][4].eff) node eff_array_hi = cat(eff_array_hi_hi, normal_entries[0][3].eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node _eff_array_T_2 = cat(_eff_array_T, _eff_array_T_1) wire eff_array : UInt<8>[1] connect eff_array[0], _eff_array_T_2 node _c_array_T = mux(cacheable[0], UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node c_array_lo = cat(c_array_lo_hi, normal_entries[0][0].c) node c_array_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node c_array_hi = cat(c_array_hi_hi, normal_entries[0][3].c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node _c_array_T_2 = cat(_c_array_T, _c_array_T_1) wire c_array : UInt<8>[1] connect c_array[0], _c_array_T_2 node _paa_array_T = mux(prot_aa[0], UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_hi = cat(normal_entries[0][2].paa, normal_entries[0][1].paa) node paa_array_lo = cat(paa_array_lo_hi, normal_entries[0][0].paa) node paa_array_hi_hi = cat(normal_entries[0][5].paa, normal_entries[0][4].paa) node paa_array_hi = cat(paa_array_hi_hi, normal_entries[0][3].paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node _paa_array_T_2 = cat(_paa_array_T, _paa_array_T_1) wire paa_array : UInt<8>[1] connect paa_array[0], _paa_array_T_2 node _pal_array_T = mux(prot_al[0], UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_hi = cat(normal_entries[0][2].pal, normal_entries[0][1].pal) node pal_array_lo = cat(pal_array_lo_hi, normal_entries[0][0].pal) node pal_array_hi_hi = cat(normal_entries[0][5].pal, normal_entries[0][4].pal) node pal_array_hi = cat(pal_array_hi_hi, normal_entries[0][3].pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node _pal_array_T_2 = cat(_pal_array_T, _pal_array_T_1) wire pal_array : UInt<8>[1] connect pal_array[0], _pal_array_T_2 node _paa_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _paa_array_if_cached_T_1 = or(paa_array[0], _paa_array_if_cached_T) wire paa_array_if_cached : UInt<8>[1] connect paa_array_if_cached[0], _paa_array_if_cached_T_1 node _pal_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0)) node _pal_array_if_cached_T_1 = or(pal_array[0], _pal_array_if_cached_T) wire pal_array_if_cached : UInt<8>[1] connect pal_array_if_cached[0], _pal_array_if_cached_T_1 node _prefetchable_array_T = and(cacheable[0], homogeneous[0]) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, normal_entries[0][0].c) node prefetchable_array_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, normal_entries[0][3].c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node _prefetchable_array_T_3 = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) wire prefetchable_array : UInt<8>[1] connect prefetchable_array[0], _prefetchable_array_T_3 node _misaligned_T = dshl(UInt<1>(0h1), io.req[0].bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req[0].bits.vaddr, _misaligned_T_2) node _misaligned_T_4 = orr(_misaligned_T_3) wire misaligned : UInt<1>[1] connect misaligned[0], _misaligned_T_4 node bad_va_maskedVAddr = and(io.req[0].bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_1 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_3 = or(_bad_va_T_1, _bad_va_T_2) node _bad_va_T_4 = eq(_bad_va_T_3, UInt<1>(0h0)) node _bad_va_T_5 = and(_bad_va_T, _bad_va_T_4) node _bad_va_T_6 = and(vm_enabled[0], _bad_va_T_5) wire bad_va : UInt<1>[1] connect bad_va[0], _bad_va_T_6 node _cmd_lrsc_T = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node _cmd_lrsc_T_3 = and(UInt<1>(0h1), _cmd_lrsc_T_2) wire cmd_lrsc : UInt<1>[1] connect cmd_lrsc[0], _cmd_lrsc_T_3 node _cmd_amo_logical_T = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node _cmd_amo_logical_T_7 = and(UInt<1>(0h1), _cmd_amo_logical_T_6) wire cmd_amo_logical : UInt<1>[1] connect cmd_amo_logical[0], _cmd_amo_logical_T_7 node _cmd_amo_arithmetic_T = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node _cmd_amo_arithmetic_T_9 = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) wire cmd_amo_arithmetic : UInt<1>[1] connect cmd_amo_arithmetic[0], _cmd_amo_arithmetic_T_9 node _cmd_read_T = eq(io.req[0].bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req[0].bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node _cmd_read_T_24 = or(_cmd_read_T_6, _cmd_read_T_23) wire cmd_read : UInt<1>[1] connect cmd_read[0], _cmd_read_T_24 node _cmd_write_T = eq(io.req[0].bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req[0].bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req[0].bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req[0].bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req[0].bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req[0].bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node _cmd_write_T_22 = or(_cmd_write_T_4, _cmd_write_T_21) wire cmd_write : UInt<1>[1] connect cmd_write[0], _cmd_write_T_22 node _cmd_write_perms_T = eq(io.req[0].bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = and(UInt<1>(0h0), _cmd_write_perms_T) node _cmd_write_perms_T_2 = or(cmd_write[0], _cmd_write_perms_T_1) wire cmd_write_perms : UInt<1>[1] connect cmd_write_perms[0], _cmd_write_perms_T_2 node _lrscAllowed_T = mux(UInt<1>(0h0), UInt<1>(0h0), c_array[0]) wire lrscAllowed : UInt<8>[1] connect lrscAllowed[0], _lrscAllowed_T node _ae_array_T = mux(misaligned[0], eff_array[0], UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed[0]) node _ae_array_T_2 = mux(cmd_lrsc[0], _ae_array_T_1, UInt<1>(0h0)) node _ae_array_T_3 = or(_ae_array_T, _ae_array_T_2) wire ae_array : UInt<8>[1] connect ae_array[0], _ae_array_T_3 node _ae_valid_array_T = eq(do_refill, UInt<1>(0h0)) node _ae_valid_array_T_1 = cat(UInt<1>(0h1), _ae_valid_array_T) node _ae_valid_array_T_2 = mux(UInt<1>(0h1), UInt<6>(0h3f), UInt<6>(0h0)) node _ae_valid_array_T_3 = cat(_ae_valid_array_T_1, _ae_valid_array_T_2) wire ae_valid_array : UInt<8>[1] connect ae_valid_array[0], _ae_valid_array_T_3 node _ae_ld_array_T = not(pr_array[0]) node _ae_ld_array_T_1 = or(ae_array[0], _ae_ld_array_T) node _ae_ld_array_T_2 = mux(cmd_read[0], _ae_ld_array_T_1, UInt<1>(0h0)) wire ae_ld_array : UInt<8>[1] connect ae_ld_array[0], _ae_ld_array_T_2 node _ae_st_array_T = not(pw_array[0]) node _ae_st_array_T_1 = or(ae_array[0], _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms[0], _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(pal_array_if_cached[0]) node _ae_st_array_T_4 = mux(cmd_amo_logical[0], _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(paa_array_if_cached[0]) node _ae_st_array_T_7 = mux(cmd_amo_arithmetic[0], _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) wire ae_st_array : UInt<8>[1] connect ae_st_array[0], _ae_st_array_T_8 node _must_alloc_array_T = not(paa_array[0]) node _must_alloc_array_T_1 = mux(cmd_amo_logical[0], _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array[0]) node _must_alloc_array_T_3 = mux(cmd_amo_arithmetic[0], _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(UInt<8>(0h0)) node _must_alloc_array_T_6 = mux(cmd_lrsc[0], _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) wire must_alloc_array : UInt<8>[1] connect must_alloc_array[0], _must_alloc_array_T_7 node _ma_ld_array_T = and(misaligned[0], cmd_read[0]) node _ma_ld_array_T_1 = not(eff_array[0]) node _ma_ld_array_T_2 = mux(_ma_ld_array_T, _ma_ld_array_T_1, UInt<1>(0h0)) wire ma_ld_array : UInt<8>[1] connect ma_ld_array[0], _ma_ld_array_T_2 node _ma_st_array_T = and(misaligned[0], cmd_write[0]) node _ma_st_array_T_1 = not(eff_array[0]) node _ma_st_array_T_2 = mux(_ma_st_array_T, _ma_st_array_T_1, UInt<1>(0h0)) wire ma_st_array : UInt<8>[1] connect ma_st_array[0], _ma_st_array_T_2 node _pf_ld_array_T = or(r_array[0], ptw_ae_array[0]) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = mux(cmd_read[0], _pf_ld_array_T_1, UInt<1>(0h0)) wire pf_ld_array : UInt<8>[1] connect pf_ld_array[0], _pf_ld_array_T_2 node _pf_st_array_T = or(w_array[0], ptw_ae_array[0]) node _pf_st_array_T_1 = not(_pf_st_array_T) node _pf_st_array_T_2 = mux(cmd_write_perms[0], _pf_st_array_T_1, UInt<1>(0h0)) wire pf_st_array : UInt<8>[1] connect pf_st_array[0], _pf_st_array_T_2 node _pf_inst_array_T = or(x_array[0], ptw_ae_array[0]) node _pf_inst_array_T_1 = not(_pf_inst_array_T) wire pf_inst_array : UInt<8>[1] connect pf_inst_array[0], _pf_inst_array_T_1 node _tlb_hit_T = orr(real_hits[0]) wire tlb_hit : UInt<1>[1] connect tlb_hit[0], _tlb_hit_T node _tlb_miss_T = eq(bad_va[0], UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled[0], _tlb_miss_T) node _tlb_miss_T_2 = eq(tlb_hit[0], UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) wire tlb_miss : UInt<1>[1] connect tlb_miss[0], _tlb_miss_T_3 regreset state_reg : UInt<1>, clock, reset, UInt<1>(0h0) regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_11 = and(io.req[0].valid, vm_enabled[0]) when _T_11 : node _T_12 = or(sector_hits[0][0], sector_hits[0][1]) when _T_12 : node _T_13 = cat(sector_hits[0][1], sector_hits[0][0]) node _T_14 = bits(_T_13, 1, 1) node state_reg_touch_way_sized = bits(_T_14, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = eq(_state_reg_T, UInt<1>(0h0)) connect state_reg, _state_reg_T_1 node _T_15 = or(superpage_hits[0][0], superpage_hits[0][1]) node _T_16 = or(_T_15, superpage_hits[0][2]) node _T_17 = or(_T_16, superpage_hits[0][3]) when _T_17 : node lo = cat(superpage_hits[0][1], superpage_hits[0][0]) node hi = cat(superpage_hits[0][3], superpage_hits[0][2]) node _T_18 = cat(hi, lo) node hi_1 = bits(_T_18, 3, 2) node lo_1 = bits(_T_18, 1, 0) node _T_19 = orr(hi_1) node _T_20 = or(hi_1, lo_1) node _T_21 = bits(_T_20, 1, 1) node _T_22 = cat(_T_19, _T_21) node state_reg_touch_way_sized_1 = bits(_T_22, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized_1, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T_2 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_3 = bits(_state_reg_T_2, 0, 0) node _state_reg_T_4 = eq(_state_reg_T_3, UInt<1>(0h0)) node _state_reg_T_5 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_4) node _state_reg_T_6 = bits(state_reg_touch_way_sized_1, 0, 0) node _state_reg_T_7 = bits(_state_reg_T_6, 0, 0) node _state_reg_T_8 = eq(_state_reg_T_7, UInt<1>(0h0)) node _state_reg_T_9 = mux(state_reg_set_left_older, _state_reg_T_8, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_5) node _state_reg_T_10 = cat(state_reg_hi, _state_reg_T_9) connect state_reg_1, _state_reg_T_10 node _multipleHits_T = bits(real_hits[0], 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits[0], 6, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 1, 0) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_2) node _multipleHits_T_13 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_14 = and(multipleHits_leftOne_3, multipleHits_rightOne_2) node multipleHits_leftTwo_1 = or(_multipleHits_T_13, _multipleHits_T_14) node _multipleHits_T_15 = bits(_multipleHits_T_9, 3, 2) node _multipleHits_T_16 = bits(_multipleHits_T_15, 0, 0) node multipleHits_leftOne_5 = bits(_multipleHits_T_16, 0, 0) node _multipleHits_T_17 = bits(_multipleHits_T_15, 1, 1) node multipleHits_rightOne_3 = bits(_multipleHits_T_17, 0, 0) node multipleHits_rightOne_4 = or(multipleHits_leftOne_5, multipleHits_rightOne_3) node _multipleHits_T_18 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_19 = and(multipleHits_leftOne_5, multipleHits_rightOne_3) node multipleHits_rightTwo_1 = or(_multipleHits_T_18, _multipleHits_T_19) node multipleHits_rightOne_5 = or(multipleHits_leftOne_4, multipleHits_rightOne_4) node _multipleHits_T_20 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_1) node _multipleHits_T_21 = and(multipleHits_leftOne_4, multipleHits_rightOne_4) node multipleHits_rightTwo_2 = or(_multipleHits_T_20, _multipleHits_T_21) node _multipleHits_T_22 = or(multipleHits_leftOne_2, multipleHits_rightOne_5) node _multipleHits_T_23 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_24 = and(multipleHits_leftOne_2, multipleHits_rightOne_5) node _multipleHits_T_25 = or(_multipleHits_T_23, _multipleHits_T_24) wire multipleHits : UInt<1>[1] connect multipleHits[0], _multipleHits_T_25 node _io_miss_rdy_T = eq(state, UInt<2>(0h0)) connect io.miss_rdy, _io_miss_rdy_T connect io.req[0].ready, UInt<1>(0h1) invalidate io.resp[0].gpa invalidate io.resp[0].gpa_is_pte connect io.resp[0].gf.ld, UInt<1>(0h0) connect io.resp[0].gf.st, UInt<1>(0h0) connect io.resp[0].gf.inst, UInt<1>(0h0) node _io_resp_0_pf_ld_T = and(bad_va[0], cmd_read[0]) node _io_resp_0_pf_ld_T_1 = and(pf_ld_array[0], hits[0]) node _io_resp_0_pf_ld_T_2 = orr(_io_resp_0_pf_ld_T_1) node _io_resp_0_pf_ld_T_3 = or(_io_resp_0_pf_ld_T, _io_resp_0_pf_ld_T_2) connect io.resp[0].pf.ld, _io_resp_0_pf_ld_T_3 node _io_resp_0_pf_st_T = and(bad_va[0], cmd_write_perms[0]) node _io_resp_0_pf_st_T_1 = and(pf_st_array[0], hits[0]) node _io_resp_0_pf_st_T_2 = orr(_io_resp_0_pf_st_T_1) node _io_resp_0_pf_st_T_3 = or(_io_resp_0_pf_st_T, _io_resp_0_pf_st_T_2) connect io.resp[0].pf.st, _io_resp_0_pf_st_T_3 node _io_resp_0_pf_inst_T = and(pf_inst_array[0], hits[0]) node _io_resp_0_pf_inst_T_1 = orr(_io_resp_0_pf_inst_T) node _io_resp_0_pf_inst_T_2 = or(bad_va[0], _io_resp_0_pf_inst_T_1) connect io.resp[0].pf.inst, _io_resp_0_pf_inst_T_2 node _io_resp_0_ae_ld_T = and(ae_valid_array[0], ae_ld_array[0]) node _io_resp_0_ae_ld_T_1 = and(_io_resp_0_ae_ld_T, hits[0]) node _io_resp_0_ae_ld_T_2 = orr(_io_resp_0_ae_ld_T_1) connect io.resp[0].ae.ld, _io_resp_0_ae_ld_T_2 node _io_resp_0_ae_st_T = and(ae_valid_array[0], ae_st_array[0]) node _io_resp_0_ae_st_T_1 = and(_io_resp_0_ae_st_T, hits[0]) node _io_resp_0_ae_st_T_2 = orr(_io_resp_0_ae_st_T_1) connect io.resp[0].ae.st, _io_resp_0_ae_st_T_2 node _io_resp_0_ae_inst_T = not(px_array[0]) node _io_resp_0_ae_inst_T_1 = and(ae_valid_array[0], _io_resp_0_ae_inst_T) node _io_resp_0_ae_inst_T_2 = and(_io_resp_0_ae_inst_T_1, hits[0]) node _io_resp_0_ae_inst_T_3 = orr(_io_resp_0_ae_inst_T_2) connect io.resp[0].ae.inst, _io_resp_0_ae_inst_T_3 node _io_resp_0_ma_ld_T = and(ma_ld_array[0], hits[0]) node _io_resp_0_ma_ld_T_1 = orr(_io_resp_0_ma_ld_T) connect io.resp[0].ma.ld, _io_resp_0_ma_ld_T_1 node _io_resp_0_ma_st_T = and(ma_st_array[0], hits[0]) node _io_resp_0_ma_st_T_1 = orr(_io_resp_0_ma_st_T) connect io.resp[0].ma.st, _io_resp_0_ma_st_T_1 connect io.resp[0].ma.inst, UInt<1>(0h0) node _io_resp_0_cacheable_T = and(c_array[0], hits[0]) node _io_resp_0_cacheable_T_1 = orr(_io_resp_0_cacheable_T) connect io.resp[0].cacheable, _io_resp_0_cacheable_T_1 node _io_resp_0_must_alloc_T = and(must_alloc_array[0], hits[0]) node _io_resp_0_must_alloc_T_1 = orr(_io_resp_0_must_alloc_T) connect io.resp[0].must_alloc, _io_resp_0_must_alloc_T_1 node _io_resp_0_prefetchable_T = and(prefetchable_array[0], hits[0]) node _io_resp_0_prefetchable_T_1 = orr(_io_resp_0_prefetchable_T) node _io_resp_0_prefetchable_T_2 = and(_io_resp_0_prefetchable_T_1, UInt<1>(0h1)) connect io.resp[0].prefetchable, _io_resp_0_prefetchable_T_2 node _io_resp_0_miss_T = or(do_refill, tlb_miss[0]) node _io_resp_0_miss_T_1 = or(_io_resp_0_miss_T, multipleHits[0]) connect io.resp[0].miss, _io_resp_0_miss_T_1 node _io_resp_0_paddr_T = bits(io.req[0].bits.vaddr, 11, 0) node _io_resp_0_paddr_T_1 = cat(ppn[0], _io_resp_0_paddr_T) connect io.resp[0].paddr, _io_resp_0_paddr_T_1 connect io.resp[0].size, io.req[0].bits.size connect io.resp[0].cmd, io.req[0].bits.cmd invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T invalidate io.ptw.req.bits.bits.stage2 invalidate io.ptw.req.bits.bits.vstage1 invalidate io.ptw.req.bits.bits.need_gpa invalidate io.ptw.req.bits.bits.addr invalidate io.ptw.req.bits.valid node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag node _T_23 = and(io.req[0].ready, io.req[0].valid) node _T_24 = and(_T_23, tlb_miss[0]) node _T_25 = eq(state, UInt<2>(0h0)) node _T_26 = and(_T_24, _T_25) when _T_26 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn[0] node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node _r_sectored_repl_addr_T = bits(state_reg, 0, 0) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0].valid[0], sectored_entries[0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[1].valid[0], sectored_entries[1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[1].valid[3]) node r_sectored_repl_addr_valids = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node _r_sectored_repl_addr_T_1 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_2 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_3 = bits(_r_sectored_repl_addr_T_2, 0, 0) node _r_sectored_repl_addr_T_4 = bits(_r_sectored_repl_addr_T_2, 1, 1) node _r_sectored_repl_addr_T_5 = mux(_r_sectored_repl_addr_T_3, UInt<1>(0h0), UInt<1>(0h1)) node _r_sectored_repl_addr_T_6 = mux(_r_sectored_repl_addr_T_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_5) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_6 node _r_sectored_hit_addr_T = cat(sector_hits[0][1], sector_hits[0][0]) node _r_sectored_hit_addr_T_1 = bits(_r_sectored_hit_addr_T, 1, 1) connect r_sectored_hit_addr, _r_sectored_hit_addr_T_1 node _r_sectored_hit_T = or(sector_hits[0][0], sector_hits[0][1]) connect r_sectored_hit, _r_sectored_hit_T node _T_27 = eq(state, UInt<2>(0h1)) when _T_27 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_28 = eq(state, UInt<2>(0h2)) node _T_29 = and(_T_28, io.sfence.valid) when _T_29 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_30 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_31 = shr(io.sfence.bits.addr, 12) node _T_32 = eq(_T_31, vpn[0]) node _T_33 = or(_T_30, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at tlb.scala:349 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn(w))\n") : printf assert(clock, _T_33, UInt<1>(0h1), "") : assert when io.sfence.bits.rs1 : node _T_37 = xor(sectored_entries[0].tag, vpn[0]) node _T_38 = shr(_T_37, 2) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = bits(vpn[0], 1, 0) connect sectored_entries[0].valid[_T_40], UInt<1>(0h0) node _T_41 = xor(sectored_entries[0].tag, vpn[0]) node _T_42 = shr(_T_41, 18) node _T_43 = eq(_T_42, UInt<1>(0h0)) when _T_43 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<34> connect _WIRE_1, sectored_entries[0].data[0] node _T_44 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_44 node _T_45 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_45 node _T_46 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_46 node _T_47 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_47 node _T_48 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_48 node _T_49 = bits(_WIRE_1, 5, 5) connect _WIRE.pr, _T_49 node _T_50 = bits(_WIRE_1, 6, 6) connect _WIRE.px, _T_50 node _T_51 = bits(_WIRE_1, 7, 7) connect _WIRE.pw, _T_51 node _T_52 = bits(_WIRE_1, 8, 8) connect _WIRE.sr, _T_52 node _T_53 = bits(_WIRE_1, 9, 9) connect _WIRE.sx, _T_53 node _T_54 = bits(_WIRE_1, 10, 10) connect _WIRE.sw, _T_54 node _T_55 = bits(_WIRE_1, 11, 11) connect _WIRE.ae, _T_55 node _T_56 = bits(_WIRE_1, 12, 12) connect _WIRE.g, _T_56 node _T_57 = bits(_WIRE_1, 13, 13) connect _WIRE.u, _T_57 node _T_58 = bits(_WIRE_1, 33, 14) connect _WIRE.ppn, _T_58 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<34> connect _WIRE_3, sectored_entries[0].data[1] node _T_59 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_59 node _T_60 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_60 node _T_61 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_61 node _T_62 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_62 node _T_63 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_63 node _T_64 = bits(_WIRE_3, 5, 5) connect _WIRE_2.pr, _T_64 node _T_65 = bits(_WIRE_3, 6, 6) connect _WIRE_2.px, _T_65 node _T_66 = bits(_WIRE_3, 7, 7) connect _WIRE_2.pw, _T_66 node _T_67 = bits(_WIRE_3, 8, 8) connect _WIRE_2.sr, _T_67 node _T_68 = bits(_WIRE_3, 9, 9) connect _WIRE_2.sx, _T_68 node _T_69 = bits(_WIRE_3, 10, 10) connect _WIRE_2.sw, _T_69 node _T_70 = bits(_WIRE_3, 11, 11) connect _WIRE_2.ae, _T_70 node _T_71 = bits(_WIRE_3, 12, 12) connect _WIRE_2.g, _T_71 node _T_72 = bits(_WIRE_3, 13, 13) connect _WIRE_2.u, _T_72 node _T_73 = bits(_WIRE_3, 33, 14) connect _WIRE_2.ppn, _T_73 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<34> connect _WIRE_5, sectored_entries[0].data[2] node _T_74 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_74 node _T_75 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_75 node _T_76 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_76 node _T_77 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_77 node _T_78 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_78 node _T_79 = bits(_WIRE_5, 5, 5) connect _WIRE_4.pr, _T_79 node _T_80 = bits(_WIRE_5, 6, 6) connect _WIRE_4.px, _T_80 node _T_81 = bits(_WIRE_5, 7, 7) connect _WIRE_4.pw, _T_81 node _T_82 = bits(_WIRE_5, 8, 8) connect _WIRE_4.sr, _T_82 node _T_83 = bits(_WIRE_5, 9, 9) connect _WIRE_4.sx, _T_83 node _T_84 = bits(_WIRE_5, 10, 10) connect _WIRE_4.sw, _T_84 node _T_85 = bits(_WIRE_5, 11, 11) connect _WIRE_4.ae, _T_85 node _T_86 = bits(_WIRE_5, 12, 12) connect _WIRE_4.g, _T_86 node _T_87 = bits(_WIRE_5, 13, 13) connect _WIRE_4.u, _T_87 node _T_88 = bits(_WIRE_5, 33, 14) connect _WIRE_4.ppn, _T_88 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<34> connect _WIRE_7, sectored_entries[0].data[3] node _T_89 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_89 node _T_90 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_90 node _T_91 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_91 node _T_92 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_92 node _T_93 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_93 node _T_94 = bits(_WIRE_7, 5, 5) connect _WIRE_6.pr, _T_94 node _T_95 = bits(_WIRE_7, 6, 6) connect _WIRE_6.px, _T_95 node _T_96 = bits(_WIRE_7, 7, 7) connect _WIRE_6.pw, _T_96 node _T_97 = bits(_WIRE_7, 8, 8) connect _WIRE_6.sr, _T_97 node _T_98 = bits(_WIRE_7, 9, 9) connect _WIRE_6.sx, _T_98 node _T_99 = bits(_WIRE_7, 10, 10) connect _WIRE_6.sw, _T_99 node _T_100 = bits(_WIRE_7, 11, 11) connect _WIRE_6.ae, _T_100 node _T_101 = bits(_WIRE_7, 12, 12) connect _WIRE_6.g, _T_101 node _T_102 = bits(_WIRE_7, 13, 13) connect _WIRE_6.u, _T_102 node _T_103 = bits(_WIRE_7, 33, 14) connect _WIRE_6.ppn, _T_103 when _WIRE.fragmented_superpage : connect sectored_entries[0].valid[0], UInt<1>(0h0) when _WIRE_2.fragmented_superpage : connect sectored_entries[0].valid[1], UInt<1>(0h0) when _WIRE_4.fragmented_superpage : connect sectored_entries[0].valid[2], UInt<1>(0h0) when _WIRE_6.fragmented_superpage : connect sectored_entries[0].valid[3], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<34> connect _WIRE_9, sectored_entries[0].data[0] node _T_104 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_104 node _T_105 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_105 node _T_106 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_106 node _T_107 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_107 node _T_108 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_108 node _T_109 = bits(_WIRE_9, 5, 5) connect _WIRE_8.pr, _T_109 node _T_110 = bits(_WIRE_9, 6, 6) connect _WIRE_8.px, _T_110 node _T_111 = bits(_WIRE_9, 7, 7) connect _WIRE_8.pw, _T_111 node _T_112 = bits(_WIRE_9, 8, 8) connect _WIRE_8.sr, _T_112 node _T_113 = bits(_WIRE_9, 9, 9) connect _WIRE_8.sx, _T_113 node _T_114 = bits(_WIRE_9, 10, 10) connect _WIRE_8.sw, _T_114 node _T_115 = bits(_WIRE_9, 11, 11) connect _WIRE_8.ae, _T_115 node _T_116 = bits(_WIRE_9, 12, 12) connect _WIRE_8.g, _T_116 node _T_117 = bits(_WIRE_9, 13, 13) connect _WIRE_8.u, _T_117 node _T_118 = bits(_WIRE_9, 33, 14) connect _WIRE_8.ppn, _T_118 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<34> connect _WIRE_11, sectored_entries[0].data[1] node _T_119 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_119 node _T_120 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_120 node _T_121 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_121 node _T_122 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_122 node _T_123 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_123 node _T_124 = bits(_WIRE_11, 5, 5) connect _WIRE_10.pr, _T_124 node _T_125 = bits(_WIRE_11, 6, 6) connect _WIRE_10.px, _T_125 node _T_126 = bits(_WIRE_11, 7, 7) connect _WIRE_10.pw, _T_126 node _T_127 = bits(_WIRE_11, 8, 8) connect _WIRE_10.sr, _T_127 node _T_128 = bits(_WIRE_11, 9, 9) connect _WIRE_10.sx, _T_128 node _T_129 = bits(_WIRE_11, 10, 10) connect _WIRE_10.sw, _T_129 node _T_130 = bits(_WIRE_11, 11, 11) connect _WIRE_10.ae, _T_130 node _T_131 = bits(_WIRE_11, 12, 12) connect _WIRE_10.g, _T_131 node _T_132 = bits(_WIRE_11, 13, 13) connect _WIRE_10.u, _T_132 node _T_133 = bits(_WIRE_11, 33, 14) connect _WIRE_10.ppn, _T_133 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<34> connect _WIRE_13, sectored_entries[0].data[2] node _T_134 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_134 node _T_135 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_135 node _T_136 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_136 node _T_137 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_137 node _T_138 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_138 node _T_139 = bits(_WIRE_13, 5, 5) connect _WIRE_12.pr, _T_139 node _T_140 = bits(_WIRE_13, 6, 6) connect _WIRE_12.px, _T_140 node _T_141 = bits(_WIRE_13, 7, 7) connect _WIRE_12.pw, _T_141 node _T_142 = bits(_WIRE_13, 8, 8) connect _WIRE_12.sr, _T_142 node _T_143 = bits(_WIRE_13, 9, 9) connect _WIRE_12.sx, _T_143 node _T_144 = bits(_WIRE_13, 10, 10) connect _WIRE_12.sw, _T_144 node _T_145 = bits(_WIRE_13, 11, 11) connect _WIRE_12.ae, _T_145 node _T_146 = bits(_WIRE_13, 12, 12) connect _WIRE_12.g, _T_146 node _T_147 = bits(_WIRE_13, 13, 13) connect _WIRE_12.u, _T_147 node _T_148 = bits(_WIRE_13, 33, 14) connect _WIRE_12.ppn, _T_148 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<34> connect _WIRE_15, sectored_entries[0].data[3] node _T_149 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_149 node _T_150 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_150 node _T_151 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_151 node _T_152 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_152 node _T_153 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_153 node _T_154 = bits(_WIRE_15, 5, 5) connect _WIRE_14.pr, _T_154 node _T_155 = bits(_WIRE_15, 6, 6) connect _WIRE_14.px, _T_155 node _T_156 = bits(_WIRE_15, 7, 7) connect _WIRE_14.pw, _T_156 node _T_157 = bits(_WIRE_15, 8, 8) connect _WIRE_14.sr, _T_157 node _T_158 = bits(_WIRE_15, 9, 9) connect _WIRE_14.sx, _T_158 node _T_159 = bits(_WIRE_15, 10, 10) connect _WIRE_14.sw, _T_159 node _T_160 = bits(_WIRE_15, 11, 11) connect _WIRE_14.ae, _T_160 node _T_161 = bits(_WIRE_15, 12, 12) connect _WIRE_14.g, _T_161 node _T_162 = bits(_WIRE_15, 13, 13) connect _WIRE_14.u, _T_162 node _T_163 = bits(_WIRE_15, 33, 14) connect _WIRE_14.ppn, _T_163 node _T_164 = eq(_WIRE_8.g, UInt<1>(0h0)) when _T_164 : connect sectored_entries[0].valid[0], UInt<1>(0h0) node _T_165 = eq(_WIRE_10.g, UInt<1>(0h0)) when _T_165 : connect sectored_entries[0].valid[1], UInt<1>(0h0) node _T_166 = eq(_WIRE_12.g, UInt<1>(0h0)) when _T_166 : connect sectored_entries[0].valid[2], UInt<1>(0h0) node _T_167 = eq(_WIRE_14.g, UInt<1>(0h0)) when _T_167 : connect sectored_entries[0].valid[3], UInt<1>(0h0) else : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) when io.sfence.bits.rs1 : node _T_168 = xor(sectored_entries[1].tag, vpn[0]) node _T_169 = shr(_T_168, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = bits(vpn[0], 1, 0) connect sectored_entries[1].valid[_T_171], UInt<1>(0h0) node _T_172 = xor(sectored_entries[1].tag, vpn[0]) node _T_173 = shr(_T_172, 18) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<34> connect _WIRE_17, sectored_entries[1].data[0] node _T_175 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_175 node _T_176 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_176 node _T_177 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_177 node _T_178 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_178 node _T_179 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_179 node _T_180 = bits(_WIRE_17, 5, 5) connect _WIRE_16.pr, _T_180 node _T_181 = bits(_WIRE_17, 6, 6) connect _WIRE_16.px, _T_181 node _T_182 = bits(_WIRE_17, 7, 7) connect _WIRE_16.pw, _T_182 node _T_183 = bits(_WIRE_17, 8, 8) connect _WIRE_16.sr, _T_183 node _T_184 = bits(_WIRE_17, 9, 9) connect _WIRE_16.sx, _T_184 node _T_185 = bits(_WIRE_17, 10, 10) connect _WIRE_16.sw, _T_185 node _T_186 = bits(_WIRE_17, 11, 11) connect _WIRE_16.ae, _T_186 node _T_187 = bits(_WIRE_17, 12, 12) connect _WIRE_16.g, _T_187 node _T_188 = bits(_WIRE_17, 13, 13) connect _WIRE_16.u, _T_188 node _T_189 = bits(_WIRE_17, 33, 14) connect _WIRE_16.ppn, _T_189 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<34> connect _WIRE_19, sectored_entries[1].data[1] node _T_190 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_190 node _T_191 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_191 node _T_192 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_192 node _T_193 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_193 node _T_194 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_194 node _T_195 = bits(_WIRE_19, 5, 5) connect _WIRE_18.pr, _T_195 node _T_196 = bits(_WIRE_19, 6, 6) connect _WIRE_18.px, _T_196 node _T_197 = bits(_WIRE_19, 7, 7) connect _WIRE_18.pw, _T_197 node _T_198 = bits(_WIRE_19, 8, 8) connect _WIRE_18.sr, _T_198 node _T_199 = bits(_WIRE_19, 9, 9) connect _WIRE_18.sx, _T_199 node _T_200 = bits(_WIRE_19, 10, 10) connect _WIRE_18.sw, _T_200 node _T_201 = bits(_WIRE_19, 11, 11) connect _WIRE_18.ae, _T_201 node _T_202 = bits(_WIRE_19, 12, 12) connect _WIRE_18.g, _T_202 node _T_203 = bits(_WIRE_19, 13, 13) connect _WIRE_18.u, _T_203 node _T_204 = bits(_WIRE_19, 33, 14) connect _WIRE_18.ppn, _T_204 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<34> connect _WIRE_21, sectored_entries[1].data[2] node _T_205 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_205 node _T_206 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_206 node _T_207 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_207 node _T_208 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_208 node _T_209 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_209 node _T_210 = bits(_WIRE_21, 5, 5) connect _WIRE_20.pr, _T_210 node _T_211 = bits(_WIRE_21, 6, 6) connect _WIRE_20.px, _T_211 node _T_212 = bits(_WIRE_21, 7, 7) connect _WIRE_20.pw, _T_212 node _T_213 = bits(_WIRE_21, 8, 8) connect _WIRE_20.sr, _T_213 node _T_214 = bits(_WIRE_21, 9, 9) connect _WIRE_20.sx, _T_214 node _T_215 = bits(_WIRE_21, 10, 10) connect _WIRE_20.sw, _T_215 node _T_216 = bits(_WIRE_21, 11, 11) connect _WIRE_20.ae, _T_216 node _T_217 = bits(_WIRE_21, 12, 12) connect _WIRE_20.g, _T_217 node _T_218 = bits(_WIRE_21, 13, 13) connect _WIRE_20.u, _T_218 node _T_219 = bits(_WIRE_21, 33, 14) connect _WIRE_20.ppn, _T_219 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<34> connect _WIRE_23, sectored_entries[1].data[3] node _T_220 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_220 node _T_221 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_221 node _T_222 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_222 node _T_223 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_223 node _T_224 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_224 node _T_225 = bits(_WIRE_23, 5, 5) connect _WIRE_22.pr, _T_225 node _T_226 = bits(_WIRE_23, 6, 6) connect _WIRE_22.px, _T_226 node _T_227 = bits(_WIRE_23, 7, 7) connect _WIRE_22.pw, _T_227 node _T_228 = bits(_WIRE_23, 8, 8) connect _WIRE_22.sr, _T_228 node _T_229 = bits(_WIRE_23, 9, 9) connect _WIRE_22.sx, _T_229 node _T_230 = bits(_WIRE_23, 10, 10) connect _WIRE_22.sw, _T_230 node _T_231 = bits(_WIRE_23, 11, 11) connect _WIRE_22.ae, _T_231 node _T_232 = bits(_WIRE_23, 12, 12) connect _WIRE_22.g, _T_232 node _T_233 = bits(_WIRE_23, 13, 13) connect _WIRE_22.u, _T_233 node _T_234 = bits(_WIRE_23, 33, 14) connect _WIRE_22.ppn, _T_234 when _WIRE_16.fragmented_superpage : connect sectored_entries[1].valid[0], UInt<1>(0h0) when _WIRE_18.fragmented_superpage : connect sectored_entries[1].valid[1], UInt<1>(0h0) when _WIRE_20.fragmented_superpage : connect sectored_entries[1].valid[2], UInt<1>(0h0) when _WIRE_22.fragmented_superpage : connect sectored_entries[1].valid[3], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<34> connect _WIRE_25, sectored_entries[1].data[0] node _T_235 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_235 node _T_236 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_236 node _T_237 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_237 node _T_238 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_238 node _T_239 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_239 node _T_240 = bits(_WIRE_25, 5, 5) connect _WIRE_24.pr, _T_240 node _T_241 = bits(_WIRE_25, 6, 6) connect _WIRE_24.px, _T_241 node _T_242 = bits(_WIRE_25, 7, 7) connect _WIRE_24.pw, _T_242 node _T_243 = bits(_WIRE_25, 8, 8) connect _WIRE_24.sr, _T_243 node _T_244 = bits(_WIRE_25, 9, 9) connect _WIRE_24.sx, _T_244 node _T_245 = bits(_WIRE_25, 10, 10) connect _WIRE_24.sw, _T_245 node _T_246 = bits(_WIRE_25, 11, 11) connect _WIRE_24.ae, _T_246 node _T_247 = bits(_WIRE_25, 12, 12) connect _WIRE_24.g, _T_247 node _T_248 = bits(_WIRE_25, 13, 13) connect _WIRE_24.u, _T_248 node _T_249 = bits(_WIRE_25, 33, 14) connect _WIRE_24.ppn, _T_249 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<34> connect _WIRE_27, sectored_entries[1].data[1] node _T_250 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_250 node _T_251 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_251 node _T_252 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_252 node _T_253 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_253 node _T_254 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_254 node _T_255 = bits(_WIRE_27, 5, 5) connect _WIRE_26.pr, _T_255 node _T_256 = bits(_WIRE_27, 6, 6) connect _WIRE_26.px, _T_256 node _T_257 = bits(_WIRE_27, 7, 7) connect _WIRE_26.pw, _T_257 node _T_258 = bits(_WIRE_27, 8, 8) connect _WIRE_26.sr, _T_258 node _T_259 = bits(_WIRE_27, 9, 9) connect _WIRE_26.sx, _T_259 node _T_260 = bits(_WIRE_27, 10, 10) connect _WIRE_26.sw, _T_260 node _T_261 = bits(_WIRE_27, 11, 11) connect _WIRE_26.ae, _T_261 node _T_262 = bits(_WIRE_27, 12, 12) connect _WIRE_26.g, _T_262 node _T_263 = bits(_WIRE_27, 13, 13) connect _WIRE_26.u, _T_263 node _T_264 = bits(_WIRE_27, 33, 14) connect _WIRE_26.ppn, _T_264 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<34> connect _WIRE_29, sectored_entries[1].data[2] node _T_265 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_265 node _T_266 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_266 node _T_267 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_267 node _T_268 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_268 node _T_269 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_269 node _T_270 = bits(_WIRE_29, 5, 5) connect _WIRE_28.pr, _T_270 node _T_271 = bits(_WIRE_29, 6, 6) connect _WIRE_28.px, _T_271 node _T_272 = bits(_WIRE_29, 7, 7) connect _WIRE_28.pw, _T_272 node _T_273 = bits(_WIRE_29, 8, 8) connect _WIRE_28.sr, _T_273 node _T_274 = bits(_WIRE_29, 9, 9) connect _WIRE_28.sx, _T_274 node _T_275 = bits(_WIRE_29, 10, 10) connect _WIRE_28.sw, _T_275 node _T_276 = bits(_WIRE_29, 11, 11) connect _WIRE_28.ae, _T_276 node _T_277 = bits(_WIRE_29, 12, 12) connect _WIRE_28.g, _T_277 node _T_278 = bits(_WIRE_29, 13, 13) connect _WIRE_28.u, _T_278 node _T_279 = bits(_WIRE_29, 33, 14) connect _WIRE_28.ppn, _T_279 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<34> connect _WIRE_31, sectored_entries[1].data[3] node _T_280 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_280 node _T_281 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_281 node _T_282 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_282 node _T_283 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_283 node _T_284 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_284 node _T_285 = bits(_WIRE_31, 5, 5) connect _WIRE_30.pr, _T_285 node _T_286 = bits(_WIRE_31, 6, 6) connect _WIRE_30.px, _T_286 node _T_287 = bits(_WIRE_31, 7, 7) connect _WIRE_30.pw, _T_287 node _T_288 = bits(_WIRE_31, 8, 8) connect _WIRE_30.sr, _T_288 node _T_289 = bits(_WIRE_31, 9, 9) connect _WIRE_30.sx, _T_289 node _T_290 = bits(_WIRE_31, 10, 10) connect _WIRE_30.sw, _T_290 node _T_291 = bits(_WIRE_31, 11, 11) connect _WIRE_30.ae, _T_291 node _T_292 = bits(_WIRE_31, 12, 12) connect _WIRE_30.g, _T_292 node _T_293 = bits(_WIRE_31, 13, 13) connect _WIRE_30.u, _T_293 node _T_294 = bits(_WIRE_31, 33, 14) connect _WIRE_30.ppn, _T_294 node _T_295 = eq(_WIRE_24.g, UInt<1>(0h0)) when _T_295 : connect sectored_entries[1].valid[0], UInt<1>(0h0) node _T_296 = eq(_WIRE_26.g, UInt<1>(0h0)) when _T_296 : connect sectored_entries[1].valid[1], UInt<1>(0h0) node _T_297 = eq(_WIRE_28.g, UInt<1>(0h0)) when _T_297 : connect sectored_entries[1].valid[2], UInt<1>(0h0) node _T_298 = eq(_WIRE_30.g, UInt<1>(0h0)) when _T_298 : connect sectored_entries[1].valid[3], UInt<1>(0h0) else : connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_299 = bits(superpage_entries[0].tag, 26, 18) node _T_300 = bits(vpn[0], 26, 18) node _T_301 = eq(_T_299, _T_300) node _T_302 = or(ignore, _T_301) node _T_303 = and(superpage_entries[0].valid[0], _T_302) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_304 = bits(superpage_entries[0].tag, 17, 9) node _T_305 = bits(vpn[0], 17, 9) node _T_306 = eq(_T_304, _T_305) node _T_307 = or(ignore_1, _T_306) node _T_308 = and(_T_303, _T_307) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_309 = bits(superpage_entries[0].tag, 8, 0) node _T_310 = bits(vpn[0], 8, 0) node _T_311 = eq(_T_309, _T_310) node _T_312 = or(ignore_2, _T_311) node _T_313 = and(_T_308, _T_312) when _T_313 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<34> connect _WIRE_33, superpage_entries[0].data[0] node _T_314 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_314 node _T_315 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_315 node _T_316 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_316 node _T_317 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_317 node _T_318 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_318 node _T_319 = bits(_WIRE_33, 5, 5) connect _WIRE_32.pr, _T_319 node _T_320 = bits(_WIRE_33, 6, 6) connect _WIRE_32.px, _T_320 node _T_321 = bits(_WIRE_33, 7, 7) connect _WIRE_32.pw, _T_321 node _T_322 = bits(_WIRE_33, 8, 8) connect _WIRE_32.sr, _T_322 node _T_323 = bits(_WIRE_33, 9, 9) connect _WIRE_32.sx, _T_323 node _T_324 = bits(_WIRE_33, 10, 10) connect _WIRE_32.sw, _T_324 node _T_325 = bits(_WIRE_33, 11, 11) connect _WIRE_32.ae, _T_325 node _T_326 = bits(_WIRE_33, 12, 12) connect _WIRE_32.g, _T_326 node _T_327 = bits(_WIRE_33, 13, 13) connect _WIRE_32.u, _T_327 node _T_328 = bits(_WIRE_33, 33, 14) connect _WIRE_32.ppn, _T_328 node _T_329 = eq(_WIRE_32.g, UInt<1>(0h0)) when _T_329 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : connect superpage_entries[0].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_330 = bits(superpage_entries[1].tag, 26, 18) node _T_331 = bits(vpn[0], 26, 18) node _T_332 = eq(_T_330, _T_331) node _T_333 = or(ignore_3, _T_332) node _T_334 = and(superpage_entries[1].valid[0], _T_333) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_335 = bits(superpage_entries[1].tag, 17, 9) node _T_336 = bits(vpn[0], 17, 9) node _T_337 = eq(_T_335, _T_336) node _T_338 = or(ignore_4, _T_337) node _T_339 = and(_T_334, _T_338) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_340 = bits(superpage_entries[1].tag, 8, 0) node _T_341 = bits(vpn[0], 8, 0) node _T_342 = eq(_T_340, _T_341) node _T_343 = or(ignore_5, _T_342) node _T_344 = and(_T_339, _T_343) when _T_344 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<34> connect _WIRE_35, superpage_entries[1].data[0] node _T_345 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_345 node _T_346 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_346 node _T_347 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_347 node _T_348 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_348 node _T_349 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_349 node _T_350 = bits(_WIRE_35, 5, 5) connect _WIRE_34.pr, _T_350 node _T_351 = bits(_WIRE_35, 6, 6) connect _WIRE_34.px, _T_351 node _T_352 = bits(_WIRE_35, 7, 7) connect _WIRE_34.pw, _T_352 node _T_353 = bits(_WIRE_35, 8, 8) connect _WIRE_34.sr, _T_353 node _T_354 = bits(_WIRE_35, 9, 9) connect _WIRE_34.sx, _T_354 node _T_355 = bits(_WIRE_35, 10, 10) connect _WIRE_34.sw, _T_355 node _T_356 = bits(_WIRE_35, 11, 11) connect _WIRE_34.ae, _T_356 node _T_357 = bits(_WIRE_35, 12, 12) connect _WIRE_34.g, _T_357 node _T_358 = bits(_WIRE_35, 13, 13) connect _WIRE_34.u, _T_358 node _T_359 = bits(_WIRE_35, 33, 14) connect _WIRE_34.ppn, _T_359 node _T_360 = eq(_WIRE_34.g, UInt<1>(0h0)) when _T_360 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : connect superpage_entries[1].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_361 = bits(superpage_entries[2].tag, 26, 18) node _T_362 = bits(vpn[0], 26, 18) node _T_363 = eq(_T_361, _T_362) node _T_364 = or(ignore_6, _T_363) node _T_365 = and(superpage_entries[2].valid[0], _T_364) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_366 = bits(superpage_entries[2].tag, 17, 9) node _T_367 = bits(vpn[0], 17, 9) node _T_368 = eq(_T_366, _T_367) node _T_369 = or(ignore_7, _T_368) node _T_370 = and(_T_365, _T_369) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_371 = bits(superpage_entries[2].tag, 8, 0) node _T_372 = bits(vpn[0], 8, 0) node _T_373 = eq(_T_371, _T_372) node _T_374 = or(ignore_8, _T_373) node _T_375 = and(_T_370, _T_374) when _T_375 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<34> connect _WIRE_37, superpage_entries[2].data[0] node _T_376 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_376 node _T_377 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_377 node _T_378 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_378 node _T_379 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_379 node _T_380 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_380 node _T_381 = bits(_WIRE_37, 5, 5) connect _WIRE_36.pr, _T_381 node _T_382 = bits(_WIRE_37, 6, 6) connect _WIRE_36.px, _T_382 node _T_383 = bits(_WIRE_37, 7, 7) connect _WIRE_36.pw, _T_383 node _T_384 = bits(_WIRE_37, 8, 8) connect _WIRE_36.sr, _T_384 node _T_385 = bits(_WIRE_37, 9, 9) connect _WIRE_36.sx, _T_385 node _T_386 = bits(_WIRE_37, 10, 10) connect _WIRE_36.sw, _T_386 node _T_387 = bits(_WIRE_37, 11, 11) connect _WIRE_36.ae, _T_387 node _T_388 = bits(_WIRE_37, 12, 12) connect _WIRE_36.g, _T_388 node _T_389 = bits(_WIRE_37, 13, 13) connect _WIRE_36.u, _T_389 node _T_390 = bits(_WIRE_37, 33, 14) connect _WIRE_36.ppn, _T_390 node _T_391 = eq(_WIRE_36.g, UInt<1>(0h0)) when _T_391 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : connect superpage_entries[2].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_392 = bits(superpage_entries[3].tag, 26, 18) node _T_393 = bits(vpn[0], 26, 18) node _T_394 = eq(_T_392, _T_393) node _T_395 = or(ignore_9, _T_394) node _T_396 = and(superpage_entries[3].valid[0], _T_395) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_397 = bits(superpage_entries[3].tag, 17, 9) node _T_398 = bits(vpn[0], 17, 9) node _T_399 = eq(_T_397, _T_398) node _T_400 = or(ignore_10, _T_399) node _T_401 = and(_T_396, _T_400) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_402 = bits(superpage_entries[3].tag, 8, 0) node _T_403 = bits(vpn[0], 8, 0) node _T_404 = eq(_T_402, _T_403) node _T_405 = or(ignore_11, _T_404) node _T_406 = and(_T_401, _T_405) when _T_406 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<34> connect _WIRE_39, superpage_entries[3].data[0] node _T_407 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_407 node _T_408 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_408 node _T_409 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_409 node _T_410 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_410 node _T_411 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_411 node _T_412 = bits(_WIRE_39, 5, 5) connect _WIRE_38.pr, _T_412 node _T_413 = bits(_WIRE_39, 6, 6) connect _WIRE_38.px, _T_413 node _T_414 = bits(_WIRE_39, 7, 7) connect _WIRE_38.pw, _T_414 node _T_415 = bits(_WIRE_39, 8, 8) connect _WIRE_38.sr, _T_415 node _T_416 = bits(_WIRE_39, 9, 9) connect _WIRE_38.sx, _T_416 node _T_417 = bits(_WIRE_39, 10, 10) connect _WIRE_38.sw, _T_417 node _T_418 = bits(_WIRE_39, 11, 11) connect _WIRE_38.ae, _T_418 node _T_419 = bits(_WIRE_39, 12, 12) connect _WIRE_38.g, _T_419 node _T_420 = bits(_WIRE_39, 13, 13) connect _WIRE_38.u, _T_420 node _T_421 = bits(_WIRE_39, 33, 14) connect _WIRE_38.ppn, _T_421 node _T_422 = eq(_WIRE_38.g, UInt<1>(0h0)) when _T_422 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : connect superpage_entries[3].valid[0], UInt<1>(0h0) when io.sfence.bits.rs1 : node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_423 = bits(special_entry.tag, 26, 18) node _T_424 = bits(vpn[0], 26, 18) node _T_425 = eq(_T_423, _T_424) node _T_426 = or(ignore_12, _T_425) node _T_427 = and(special_entry.valid[0], _T_426) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_428 = bits(special_entry.tag, 17, 9) node _T_429 = bits(vpn[0], 17, 9) node _T_430 = eq(_T_428, _T_429) node _T_431 = or(ignore_13, _T_430) node _T_432 = and(_T_427, _T_431) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_433 = bits(special_entry.tag, 8, 0) node _T_434 = bits(vpn[0], 8, 0) node _T_435 = eq(_T_433, _T_434) node _T_436 = or(ignore_14, _T_435) node _T_437 = and(_T_432, _T_436) when _T_437 : connect special_entry.valid[0], UInt<1>(0h0) else : when io.sfence.bits.rs2 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<34> connect _WIRE_41, special_entry.data[0] node _T_438 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_438 node _T_439 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_439 node _T_440 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_440 node _T_441 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_441 node _T_442 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_442 node _T_443 = bits(_WIRE_41, 5, 5) connect _WIRE_40.pr, _T_443 node _T_444 = bits(_WIRE_41, 6, 6) connect _WIRE_40.px, _T_444 node _T_445 = bits(_WIRE_41, 7, 7) connect _WIRE_40.pw, _T_445 node _T_446 = bits(_WIRE_41, 8, 8) connect _WIRE_40.sr, _T_446 node _T_447 = bits(_WIRE_41, 9, 9) connect _WIRE_40.sx, _T_447 node _T_448 = bits(_WIRE_41, 10, 10) connect _WIRE_40.sw, _T_448 node _T_449 = bits(_WIRE_41, 11, 11) connect _WIRE_40.ae, _T_449 node _T_450 = bits(_WIRE_41, 12, 12) connect _WIRE_40.g, _T_450 node _T_451 = bits(_WIRE_41, 13, 13) connect _WIRE_40.u, _T_451 node _T_452 = bits(_WIRE_41, 33, 14) connect _WIRE_40.ppn, _T_452 node _T_453 = eq(_WIRE_40.g, UInt<1>(0h0)) when _T_453 : connect special_entry.valid[0], UInt<1>(0h0) else : connect special_entry.valid[0], UInt<1>(0h0) node _T_454 = asUInt(reset) node _T_455 = or(multipleHits[0], _T_454) when _T_455 : connect sectored_entries[0].valid[0], UInt<1>(0h0) connect sectored_entries[0].valid[1], UInt<1>(0h0) connect sectored_entries[0].valid[2], UInt<1>(0h0) connect sectored_entries[0].valid[3], UInt<1>(0h0) connect sectored_entries[1].valid[0], UInt<1>(0h0) connect sectored_entries[1].valid[1], UInt<1>(0h0) connect sectored_entries[1].valid[2], UInt<1>(0h0) connect sectored_entries[1].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0)

module NBDTLB( // @[tlb.scala:17:7] input clock, // @[tlb.scala:17:7] input reset, // @[tlb.scala:17:7] input io_req_0_valid, // @[tlb.scala:19:14] input [39:0] io_req_0_bits_vaddr, // @[tlb.scala:19:14] input io_req_0_bits_passthrough, // @[tlb.scala:19:14] input [1:0] io_req_0_bits_size, // @[tlb.scala:19:14] input [4:0] io_req_0_bits_cmd, // @[tlb.scala:19:14] input [1:0] io_req_0_bits_prv, // @[tlb.scala:19:14] input io_req_0_bits_v, // @[tlb.scala:19:14] output io_resp_0_miss, // @[tlb.scala:19:14] output [31:0] io_resp_0_paddr, // @[tlb.scala:19:14] output io_resp_0_pf_ld, // @[tlb.scala:19:14] output io_resp_0_pf_st, // @[tlb.scala:19:14] output io_resp_0_ae_ld, // @[tlb.scala:19:14] output io_resp_0_ae_st, // @[tlb.scala:19:14] output io_resp_0_ma_ld, // @[tlb.scala:19:14] output io_resp_0_ma_st, // @[tlb.scala:19:14] output io_resp_0_cacheable, // @[tlb.scala:19:14] input io_sfence_valid, // @[tlb.scala:19:14] input io_sfence_bits_rs1, // @[tlb.scala:19:14] input io_sfence_bits_rs2, // @[tlb.scala:19:14] input [38:0] io_sfence_bits_addr, // @[tlb.scala:19:14] input io_sfence_bits_asid, // @[tlb.scala:19:14] input io_sfence_bits_hv, // @[tlb.scala:19:14] input io_sfence_bits_hg, // @[tlb.scala:19:14] input io_ptw_req_ready, // @[tlb.scala:19:14] output io_ptw_req_valid, // @[tlb.scala:19:14] output io_ptw_req_bits_valid, // @[tlb.scala:19:14] output [26:0] io_ptw_req_bits_bits_addr, // @[tlb.scala:19:14] input io_ptw_resp_valid, // @[tlb.scala:19:14] input io_ptw_resp_bits_ae_ptw, // @[tlb.scala:19:14] input io_ptw_resp_bits_ae_final, // @[tlb.scala:19:14] input io_ptw_resp_bits_pf, // @[tlb.scala:19:14] input io_ptw_resp_bits_gf, // @[tlb.scala:19:14] input io_ptw_resp_bits_hr, // @[tlb.scala:19:14] input io_ptw_resp_bits_hw, // @[tlb.scala:19:14] input io_ptw_resp_bits_hx, // @[tlb.scala:19:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[tlb.scala:19:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[tlb.scala:19:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_d, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_a, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_g, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_u, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_x, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_w, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_r, // @[tlb.scala:19:14] input io_ptw_resp_bits_pte_v, // @[tlb.scala:19:14] input [1:0] io_ptw_resp_bits_level, // @[tlb.scala:19:14] input io_ptw_resp_bits_homogeneous, // @[tlb.scala:19:14] input io_ptw_resp_bits_gpa_valid, // @[tlb.scala:19:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[tlb.scala:19:14] input io_ptw_resp_bits_gpa_is_pte, // @[tlb.scala:19:14] input [3:0] io_ptw_ptbr_mode, // @[tlb.scala:19:14] input [43:0] io_ptw_ptbr_ppn, // @[tlb.scala:19:14] input io_ptw_status_debug, // @[tlb.scala:19:14] input io_ptw_status_cease, // @[tlb.scala:19:14] input io_ptw_status_wfi, // @[tlb.scala:19:14] input [1:0] io_ptw_status_dprv, // @[tlb.scala:19:14] input io_ptw_status_dv, // @[tlb.scala:19:14] input [1:0] io_ptw_status_prv, // @[tlb.scala:19:14] input io_ptw_status_v, // @[tlb.scala:19:14] input io_ptw_status_sd, // @[tlb.scala:19:14] input io_ptw_status_mpv, // @[tlb.scala:19:14] input io_ptw_status_gva, // @[tlb.scala:19:14] input io_ptw_status_tsr, // @[tlb.scala:19:14] input io_ptw_status_tw, // @[tlb.scala:19:14] input io_ptw_status_tvm, // @[tlb.scala:19:14] input io_ptw_status_mxr, // @[tlb.scala:19:14] input io_ptw_status_sum, // @[tlb.scala:19:14] input io_ptw_status_mprv, // @[tlb.scala:19:14] input [1:0] io_ptw_status_fs, // @[tlb.scala:19:14] input [1:0] io_ptw_status_mpp, // @[tlb.scala:19:14] input io_ptw_status_spp, // @[tlb.scala:19:14] input io_ptw_status_mpie, // @[tlb.scala:19:14] input io_ptw_status_spie, // @[tlb.scala:19:14] input io_ptw_status_mie, // @[tlb.scala:19:14] input io_ptw_status_sie, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_0_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_0_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_0_mask, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_1_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_1_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_1_mask, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_2_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_2_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_2_mask, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_3_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_3_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_3_mask, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_4_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_4_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_4_mask, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_5_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_5_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_5_mask, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_6_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_6_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_6_mask, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_l, // @[tlb.scala:19:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_x, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_w, // @[tlb.scala:19:14] input io_ptw_pmp_7_cfg_r, // @[tlb.scala:19:14] input [29:0] io_ptw_pmp_7_addr, // @[tlb.scala:19:14] input [31:0] io_ptw_pmp_7_mask, // @[tlb.scala:19:14] input io_kill // @[tlb.scala:19:14] ); wire _normal_entries_WIRE_12_5_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_5_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_5_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_4_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_4_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_3_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_3_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_2_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_2_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_1_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_1_ppn; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_fragmented_superpage; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_c; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_eff; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_paa; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_pal; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_pr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_px; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_pw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_sr; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_sx; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_sw; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_ae; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_g; // @[tlb.scala:212:45] wire _normal_entries_WIRE_12_0_u; // @[tlb.scala:212:45] wire [19:0] _normal_entries_WIRE_12_0_ppn; // @[tlb.scala:212:45] wire _entries_WIRE_14_6_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_6_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_6_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_5_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_5_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_4_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_4_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_3_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_3_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_2_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_2_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_1_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_1_ppn; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_fragmented_superpage; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_c; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_eff; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_paa; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_pal; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_pr; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_px; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_pw; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_sr; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_sx; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_sw; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_ae; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_g; // @[tlb.scala:211:38] wire _entries_WIRE_14_0_u; // @[tlb.scala:211:38] wire [19:0] _entries_WIRE_14_0_ppn; // @[tlb.scala:211:38] wire [19:0] _ppn_data_barrier_6_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_5_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_4_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_3_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_2_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_1_io_y_ppn; // @[package.scala:267:25] wire [19:0] _ppn_data_barrier_io_y_ppn; // @[package.scala:267:25] wire _pmp_0_io_r; // @[tlb.scala:150:40] wire _pmp_0_io_w; // @[tlb.scala:150:40] wire _pmp_0_io_x; // @[tlb.scala:150:40] wire [19:0] _mpu_ppn_data_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_0_valid_0 = io_req_0_valid; // @[tlb.scala:17:7] wire [39:0] io_req_0_bits_vaddr_0 = io_req_0_bits_vaddr; // @[tlb.scala:17:7] wire io_req_0_bits_passthrough_0 = io_req_0_bits_passthrough; // @[tlb.scala:17:7] wire [1:0] io_req_0_bits_size_0 = io_req_0_bits_size; // @[tlb.scala:17:7] wire [4:0] io_req_0_bits_cmd_0 = io_req_0_bits_cmd; // @[tlb.scala:17:7] wire [1:0] io_req_0_bits_prv_0 = io_req_0_bits_prv; // @[tlb.scala:17:7] wire io_req_0_bits_v_0 = io_req_0_bits_v; // @[tlb.scala:17:7] wire io_sfence_valid_0 = io_sfence_valid; // @[tlb.scala:17:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[tlb.scala:17:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[tlb.scala:17:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[tlb.scala:17:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[tlb.scala:17:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[tlb.scala:17:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[tlb.scala:17:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[tlb.scala:17:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[tlb.scala:17:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[tlb.scala:17:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[tlb.scala:17:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[tlb.scala:17:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[tlb.scala:17:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[tlb.scala:17:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[tlb.scala:17:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[tlb.scala:17:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[tlb.scala:17:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[tlb.scala:17:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[tlb.scala:17:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[tlb.scala:17:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[tlb.scala:17:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[tlb.scala:17:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[tlb.scala:17:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[tlb.scala:17:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[tlb.scala:17:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[tlb.scala:17:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[tlb.scala:17:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[tlb.scala:17:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[tlb.scala:17:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[tlb.scala:17:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[tlb.scala:17:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[tlb.scala:17:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[tlb.scala:17:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[tlb.scala:17:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[tlb.scala:17:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[tlb.scala:17:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[tlb.scala:17:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[tlb.scala:17:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[tlb.scala:17:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[tlb.scala:17:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[tlb.scala:17:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[tlb.scala:17:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[tlb.scala:17:7] wire io_kill_0 = io_kill; // @[tlb.scala:17:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[tlb.scala:17:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[tlb.scala:17:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[tlb.scala:17:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[tlb.scala:17:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[tlb.scala:17:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[tlb.scala:17:7] wire io_resp_0_gpa_is_pte = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_ld = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_st = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_gf_inst = 1'h0; // @[tlb.scala:17:7] wire io_resp_0_ma_inst = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_status_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_hu = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spvp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_spv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_debug = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_cease = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_wfi = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_dv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_v = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_gva = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sbe = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tsr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tw = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_tvm = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mxr = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sum = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mprv = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spp = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mpie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_ube = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_spie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_upie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_mie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_hie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_sie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_gstatus_uie = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[tlb.scala:17:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[tlb.scala:17:7] wire _cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _prot_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _prot_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _prot_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _prot_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _prot_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire _superpage_hits_ignore_T = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore = 1'h0; // @[tlb.scala:66:36] wire _superpage_hits_ignore_T_3 = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore_3 = 1'h0; // @[tlb.scala:66:36] wire _superpage_hits_ignore_T_6 = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore_6 = 1'h0; // @[tlb.scala:66:36] wire _superpage_hits_ignore_T_9 = 1'h0; // @[tlb.scala:66:30] wire superpage_hits_ignore_9 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_3 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_3 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_6 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_6 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_9 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_9 = 1'h0; // @[tlb.scala:66:36] wire _hitsVec_ignore_T_12 = 1'h0; // @[tlb.scala:66:30] wire hitsVec_ignore_12 = 1'h0; // @[tlb.scala:66:36] wire newEntry_fragmented_superpage = 1'h0; // @[tlb.scala:179:24] wire _cmd_write_perms_T_1 = 1'h0; // @[tlb.scala:248:29] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:37] wire _ignore_T = 1'h0; // @[tlb.scala:66:30] wire ignore = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_3 = 1'h0; // @[tlb.scala:66:30] wire ignore_3 = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_6 = 1'h0; // @[tlb.scala:66:30] wire ignore_6 = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_9 = 1'h0; // @[tlb.scala:66:30] wire ignore_9 = 1'h0; // @[tlb.scala:66:36] wire _ignore_T_12 = 1'h0; // @[tlb.scala:66:30] wire ignore_12 = 1'h0; // @[tlb.scala:66:36] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[tlb.scala:17:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[tlb.scala:17:7] wire io_req_0_ready = 1'h1; // @[tlb.scala:17:7] wire _homogeneous_T_60 = 1'h1; // @[TLBPermissions.scala:87:22] wire _prot_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire superpage_hits_ignore_2 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_13 = 1'h1; // @[tlb.scala:67:42] wire superpage_hits_ignore_5 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_28 = 1'h1; // @[tlb.scala:67:42] wire superpage_hits_ignore_8 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_43 = 1'h1; // @[tlb.scala:67:42] wire superpage_hits_ignore_11 = 1'h1; // @[tlb.scala:66:36] wire _superpage_hits_T_58 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_2 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_23 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_5 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_39 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_8 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_55 = 1'h1; // @[tlb.scala:67:42] wire hitsVec_ignore_11 = 1'h1; // @[tlb.scala:66:36] wire _hitsVec_T_71 = 1'h1; // @[tlb.scala:67:42] wire ppn_ignore_1 = 1'h1; // @[tlb.scala:80:38] wire ppn_ignore_3 = 1'h1; // @[tlb.scala:80:38] wire ppn_ignore_5 = 1'h1; // @[tlb.scala:80:38] wire ppn_ignore_7 = 1'h1; // @[tlb.scala:80:38] wire _bad_va_T = 1'h1; // @[tlb.scala:238:38] wire ignore_2 = 1'h1; // @[tlb.scala:66:36] wire ignore_5 = 1'h1; // @[tlb.scala:66:36] wire ignore_8 = 1'h1; // @[tlb.scala:66:36] wire ignore_11 = 1'h1; // @[tlb.scala:66:36] wire [39:0] io_resp_0_gpa = 40'h0; // @[tlb.scala:17:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[tlb.scala:17:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[tlb.scala:17:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[tlb.scala:17:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[tlb.scala:17:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[tlb.scala:17:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[tlb.scala:17:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[tlb.scala:17:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[tlb.scala:17:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[tlb.scala:17:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[tlb.scala:17:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[tlb.scala:17:7] wire [7:0] _must_alloc_array_T_5 = 8'hFF; // @[tlb.scala:264:32] wire [5:0] _ae_valid_array_T_2 = 6'h3F; // @[tlb.scala:255:9] wire [40:0] _prot_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _prot_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire [1:0] io_resp_0_size = io_req_0_bits_size_0; // @[tlb.scala:17:7] wire [4:0] io_resp_0_cmd = io_req_0_bits_cmd_0; // @[tlb.scala:17:7] wire _io_miss_rdy_T; // @[tlb.scala:290:24] wire _io_resp_0_miss_T_1; // @[tlb.scala:310:50] wire [31:0] _io_resp_0_paddr_T_1; // @[tlb.scala:311:28] wire _io_resp_0_pf_ld_T_3; // @[tlb.scala:298:54] wire _io_resp_0_pf_st_T_3; // @[tlb.scala:299:61] wire _io_resp_0_pf_inst_T_2; // @[tlb.scala:300:37] wire _io_resp_0_ae_ld_T_2; // @[tlb.scala:301:74] wire _io_resp_0_ae_st_T_2; // @[tlb.scala:302:74] wire _io_resp_0_ae_inst_T_3; // @[tlb.scala:303:74] wire _io_resp_0_ma_ld_T_1; // @[tlb.scala:304:54] wire _io_resp_0_ma_st_T_1; // @[tlb.scala:305:54] wire _io_resp_0_cacheable_T_1; // @[tlb.scala:307:55] wire _io_resp_0_must_alloc_T_1; // @[tlb.scala:308:64] wire _io_resp_0_prefetchable_T_2; // @[tlb.scala:309:70] wire _io_ptw_req_valid_T; // @[tlb.scala:317:29] wire _io_ptw_req_bits_valid_T; // @[tlb.scala:319:28] wire do_refill = io_ptw_resp_valid_0; // @[tlb.scala:17:7, :144:29] wire newEntry_ae = io_ptw_resp_bits_ae_final_0; // @[tlb.scala:17:7, :179:24] wire newEntry_g = io_ptw_resp_bits_pte_g_0; // @[tlb.scala:17:7, :179:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[tlb.scala:17:7, :179:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire io_resp_0_pf_ld_0; // @[tlb.scala:17:7] wire io_resp_0_pf_st_0; // @[tlb.scala:17:7] wire io_resp_0_pf_inst; // @[tlb.scala:17:7] wire io_resp_0_ae_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ae_st_0; // @[tlb.scala:17:7] wire io_resp_0_ae_inst; // @[tlb.scala:17:7] wire io_resp_0_ma_ld_0; // @[tlb.scala:17:7] wire io_resp_0_ma_st_0; // @[tlb.scala:17:7] wire io_resp_0_miss_0; // @[tlb.scala:17:7] wire [31:0] io_resp_0_paddr_0; // @[tlb.scala:17:7] wire io_resp_0_cacheable_0; // @[tlb.scala:17:7] wire io_resp_0_must_alloc; // @[tlb.scala:17:7] wire io_resp_0_prefetchable; // @[tlb.scala:17:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[tlb.scala:17:7] wire io_ptw_req_bits_valid_0; // @[tlb.scala:17:7] wire io_ptw_req_valid_0; // @[tlb.scala:17:7] wire io_miss_rdy; // @[tlb.scala:17:7] reg [1:0] sectored_entries_0_level; // @[tlb.scala:122:29] reg [26:0] sectored_entries_0_tag; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_0; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_1; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_2; // @[tlb.scala:122:29] reg [33:0] sectored_entries_0_data_3; // @[tlb.scala:122:29] reg sectored_entries_0_valid_0; // @[tlb.scala:122:29] reg sectored_entries_0_valid_1; // @[tlb.scala:122:29] reg sectored_entries_0_valid_2; // @[tlb.scala:122:29] reg sectored_entries_0_valid_3; // @[tlb.scala:122:29] reg [1:0] sectored_entries_1_level; // @[tlb.scala:122:29] reg [26:0] sectored_entries_1_tag; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_0; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_1; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_2; // @[tlb.scala:122:29] reg [33:0] sectored_entries_1_data_3; // @[tlb.scala:122:29] reg sectored_entries_1_valid_0; // @[tlb.scala:122:29] reg sectored_entries_1_valid_1; // @[tlb.scala:122:29] reg sectored_entries_1_valid_2; // @[tlb.scala:122:29] reg sectored_entries_1_valid_3; // @[tlb.scala:122:29] reg [1:0] superpage_entries_0_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_0_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_0_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_5 = superpage_entries_0_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_5 = superpage_entries_0_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_5 = superpage_entries_0_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_0_valid_0; // @[tlb.scala:123:30] reg [1:0] superpage_entries_1_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_1_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_1_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_7 = superpage_entries_1_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_7 = superpage_entries_1_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_7 = superpage_entries_1_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_1_valid_0; // @[tlb.scala:123:30] reg [1:0] superpage_entries_2_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_2_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_2_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_9 = superpage_entries_2_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_9 = superpage_entries_2_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_9 = superpage_entries_2_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_2_valid_0; // @[tlb.scala:123:30] reg [1:0] superpage_entries_3_level; // @[tlb.scala:123:30] reg [26:0] superpage_entries_3_tag; // @[tlb.scala:123:30] reg [33:0] superpage_entries_3_data_0; // @[tlb.scala:123:30] wire [33:0] _ppn_data_WIRE_11 = superpage_entries_3_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _entries_WIRE_11 = superpage_entries_3_data_0; // @[tlb.scala:58:79, :123:30] wire [33:0] _normal_entries_WIRE_11 = superpage_entries_3_data_0; // @[tlb.scala:58:79, :123:30] reg superpage_entries_3_valid_0; // @[tlb.scala:123:30] reg [1:0] special_entry_level; // @[tlb.scala:124:56] reg [26:0] special_entry_tag; // @[tlb.scala:124:56] reg [33:0] special_entry_data_0; // @[tlb.scala:124:56] wire [33:0] _mpu_ppn_data_WIRE_1 = special_entry_data_0; // @[tlb.scala:58:79, :124:56] wire [33:0] _ppn_data_WIRE_13 = special_entry_data_0; // @[tlb.scala:58:79, :124:56] wire [33:0] _entries_WIRE_13 = special_entry_data_0; // @[tlb.scala:58:79, :124:56] reg special_entry_valid_0; // @[tlb.scala:124:56] reg [1:0] state; // @[tlb.scala:129:22] reg [26:0] r_refill_tag; // @[tlb.scala:130:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[tlb.scala:17:7, :130:25] reg [1:0] r_superpage_repl_addr; // @[tlb.scala:131:34] reg r_sectored_repl_addr; // @[tlb.scala:132:33] reg r_sectored_hit_addr; // @[tlb.scala:133:32] reg r_sectored_hit; // @[tlb.scala:134:27] wire priv_s = io_ptw_status_dprv_0[0]; // @[tlb.scala:17:7, :137:20] wire priv_uses_vm = ~(io_ptw_status_dprv_0[1]); // @[tlb.scala:17:7, :138:27] wire _vm_enabled_T = io_ptw_ptbr_mode_0[3]; // @[tlb.scala:17:7, :139:63] wire _vm_enabled_T_1 = _vm_enabled_T; // @[tlb.scala:139:{44,63}] wire _vm_enabled_T_2 = _vm_enabled_T_1 & priv_uses_vm; // @[tlb.scala:138:27, :139:{44,93}] wire _vm_enabled_T_3 = ~io_req_0_bits_passthrough_0; // @[tlb.scala:17:7, :139:112] wire _vm_enabled_T_4 = _vm_enabled_T_2 & _vm_enabled_T_3; // @[tlb.scala:139:{93,109,112}] wire vm_enabled_0 = _vm_enabled_T_4; // @[tlb.scala:119:49, :139:109] wire _mpu_ppn_T = vm_enabled_0; // @[tlb.scala:119:49, :148:35] wire [26:0] _vpn_T = io_req_0_bits_vaddr_0[38:12]; // @[tlb.scala:17:7, :142:47] wire [26:0] vpn_0 = _vpn_T; // @[tlb.scala:119:49, :142:47] wire [26:0] _ppn_T_5 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [26:0] _ppn_T_13 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [26:0] _ppn_T_21 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [26:0] _ppn_T_29 = vpn_0; // @[tlb.scala:81:30, :119:49] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44, :179:24] wire _T_27 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_27; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_27; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_data_T_14; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_13; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_12; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_11; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_10; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_9; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_8; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_7; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_6; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_5; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_4; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_3; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_2; // @[tlb.scala:58:79] wire _mpu_ppn_data_T_1; // @[tlb.scala:58:79] wire _mpu_ppn_data_T; // @[tlb.scala:58:79] assign _mpu_ppn_data_T = _mpu_ppn_data_WIRE_1[0]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_fragmented_superpage = _mpu_ppn_data_T; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_1 = _mpu_ppn_data_WIRE_1[1]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_c = _mpu_ppn_data_T_1; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_2 = _mpu_ppn_data_WIRE_1[2]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_eff = _mpu_ppn_data_T_2; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_3 = _mpu_ppn_data_WIRE_1[3]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_paa = _mpu_ppn_data_T_3; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_4 = _mpu_ppn_data_WIRE_1[4]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pal = _mpu_ppn_data_T_4; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_5 = _mpu_ppn_data_WIRE_1[5]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pr = _mpu_ppn_data_T_5; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_6 = _mpu_ppn_data_WIRE_1[6]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_px = _mpu_ppn_data_T_6; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_7 = _mpu_ppn_data_WIRE_1[7]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_pw = _mpu_ppn_data_T_7; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_8 = _mpu_ppn_data_WIRE_1[8]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sr = _mpu_ppn_data_T_8; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_9 = _mpu_ppn_data_WIRE_1[9]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sx = _mpu_ppn_data_T_9; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_10 = _mpu_ppn_data_WIRE_1[10]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_sw = _mpu_ppn_data_T_10; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_11 = _mpu_ppn_data_WIRE_1[11]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_ae = _mpu_ppn_data_T_11; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_12 = _mpu_ppn_data_WIRE_1[12]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_g = _mpu_ppn_data_T_12; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_13 = _mpu_ppn_data_WIRE_1[13]; // @[tlb.scala:58:79] wire _mpu_ppn_data_WIRE_u = _mpu_ppn_data_T_13; // @[tlb.scala:58:79] assign _mpu_ppn_data_T_14 = _mpu_ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _mpu_ppn_data_WIRE_ppn = _mpu_ppn_data_T_14; // @[tlb.scala:58:79] wire [1:0] mpu_ppn_res = _mpu_ppn_data_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[tlb.scala:80:31, :124:56] wire _mpu_ppn_ignore_T; // @[tlb.scala:80:31] assign _mpu_ppn_ignore_T = _GEN; // @[tlb.scala:80:31] wire _hitsVec_ignore_T_13; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_13 = _GEN; // @[tlb.scala:66:30, :80:31] wire _ppn_ignore_T_8; // @[tlb.scala:80:31] assign _ppn_ignore_T_8 = _GEN; // @[tlb.scala:80:31] wire _ignore_T_13; // @[tlb.scala:66:30] assign _ignore_T_13 = _GEN; // @[tlb.scala:66:30, :80:31] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[tlb.scala:80:{31,38}] wire [26:0] _mpu_ppn_T_1 = mpu_ppn_ignore ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _mpu_ppn_T_2 = {_mpu_ppn_T_1[26:20], _mpu_ppn_T_1[19:0] | _mpu_ppn_data_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_3 = _mpu_ppn_T_2[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _mpu_ppn_T_4 = {mpu_ppn_res, _mpu_ppn_T_3}; // @[tlb.scala:78:28, :81:{20,60}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[tlb.scala:80:31, :124:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[tlb.scala:80:{31,38}] wire [26:0] _mpu_ppn_T_5 = mpu_ppn_ignore_1 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _mpu_ppn_T_6 = {_mpu_ppn_T_5[26:20], _mpu_ppn_T_5[19:0] | _mpu_ppn_data_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_7 = _mpu_ppn_T_6[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _mpu_ppn_T_8 = {_mpu_ppn_T_4, _mpu_ppn_T_7}; // @[tlb.scala:81:{20,60}] wire [27:0] _mpu_ppn_T_9 = io_req_0_bits_vaddr_0[39:12]; // @[tlb.scala:17:7, :148:134] wire [27:0] _mpu_ppn_T_10 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_8} : _mpu_ppn_T_9; // @[tlb.scala:81:20, :148:{20,35,134}] wire [27:0] _mpu_ppn_T_11 = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_10; // @[tlb.scala:143:44, :144:29, :147:20, :148:20] wire [27:0] mpu_ppn_0 = _mpu_ppn_T_11; // @[tlb.scala:119:49, :147:20] wire [11:0] _mpu_physaddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72] wire [11:0] _io_resp_0_paddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72, :311:57] wire [39:0] _mpu_physaddr_T_1 = {mpu_ppn_0, _mpu_physaddr_T}; // @[tlb.scala:119:49, :149:{39,72}] wire [39:0] mpu_physaddr_0 = _mpu_physaddr_T_1; // @[tlb.scala:119:49, :149:39] wire [39:0] _legal_address_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_68 = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_r_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T = mpu_physaddr_0; // @[Parameters.scala:137:31] wire _pmp_0_io_prv_T = do_refill | io_req_0_bits_passthrough_0; // @[tlb.scala:17:7, :144:29, :155:50] wire _pmp_0_io_prv_T_1 = _pmp_0_io_prv_T; // @[tlb.scala:155:{36,50}] wire [1:0] _pmp_0_io_prv_T_2 = _pmp_0_io_prv_T_1 ? 2'h1 : io_ptw_status_dprv_0; // @[tlb.scala:17:7, :155:{25,36}] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {mpu_physaddr_0[39:13], mpu_physaddr_0[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_29; // @[Parameters.scala:137:31] assign _prot_x_T_29 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {mpu_physaddr_0[39:14], mpu_physaddr_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_73; // @[Parameters.scala:137:31] assign _homogeneous_T_73 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_5; // @[Parameters.scala:137:31] assign _prot_x_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_35; // @[Parameters.scala:137:31] assign _prot_eff_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {mpu_physaddr_0[39:17], mpu_physaddr_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_5; // @[Parameters.scala:137:31] assign _cacheable_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_61; // @[Parameters.scala:137:31] assign _homogeneous_T_61 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_78; // @[Parameters.scala:137:31] assign _homogeneous_T_78 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_110; // @[Parameters.scala:137:31] assign _homogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_117; // @[Parameters.scala:137:31] assign _homogeneous_T_117 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_41; // @[Parameters.scala:137:31] assign _prot_w_T_41 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_41; // @[Parameters.scala:137:31] assign _prot_al_T_41 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_41; // @[Parameters.scala:137:31] assign _prot_aa_T_41 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_10; // @[Parameters.scala:137:31] assign _prot_x_T_10 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_40; // @[Parameters.scala:137:31] assign _prot_eff_T_40 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {mpu_physaddr_0[39:21], mpu_physaddr_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_15; // @[Parameters.scala:137:31] assign _homogeneous_T_15 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_5; // @[Parameters.scala:137:31] assign _prot_w_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_5; // @[Parameters.scala:137:31] assign _prot_al_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_5; // @[Parameters.scala:137:31] assign _prot_aa_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_34; // @[Parameters.scala:137:31] assign _prot_x_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_5; // @[Parameters.scala:137:31] assign _prot_eff_T_5 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {mpu_physaddr_0[39:21], mpu_physaddr_0[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {mpu_physaddr_0[39:26], mpu_physaddr_0[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_20; // @[Parameters.scala:137:31] assign _homogeneous_T_20 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_39; // @[Parameters.scala:137:31] assign _prot_x_T_39 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_10; // @[Parameters.scala:137:31] assign _prot_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {mpu_physaddr_0[39:26], mpu_physaddr_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_25; // @[Parameters.scala:137:31] assign _homogeneous_T_25 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_10; // @[Parameters.scala:137:31] assign _prot_w_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_10; // @[Parameters.scala:137:31] assign _prot_al_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_10; // @[Parameters.scala:137:31] assign _prot_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_44; // @[Parameters.scala:137:31] assign _prot_x_T_44 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_15; // @[Parameters.scala:137:31] assign _prot_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {mpu_physaddr_0[39:28], mpu_physaddr_0[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_17; // @[Parameters.scala:137:31] assign _cacheable_T_17 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_83; // @[Parameters.scala:137:31] assign _homogeneous_T_83 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_98; // @[Parameters.scala:137:31] assign _homogeneous_T_98 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_15; // @[Parameters.scala:137:31] assign _prot_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_20; // @[Parameters.scala:137:31] assign _prot_w_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_15; // @[Parameters.scala:137:31] assign _prot_al_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_20; // @[Parameters.scala:137:31] assign _prot_al_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_15; // @[Parameters.scala:137:31] assign _prot_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_20; // @[Parameters.scala:137:31] assign _prot_aa_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_15; // @[Parameters.scala:137:31] assign _prot_x_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_45; // @[Parameters.scala:137:31] assign _prot_eff_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {mpu_physaddr_0[39:28], mpu_physaddr_0[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_10; // @[Parameters.scala:137:31] assign _cacheable_T_10 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_35; // @[Parameters.scala:137:31] assign _homogeneous_T_35 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_49; // @[Parameters.scala:137:31] assign _prot_x_T_49 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_20; // @[Parameters.scala:137:31] assign _prot_eff_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _GEN_8 = {mpu_physaddr_0[39:29], mpu_physaddr_0[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_50; // @[Parameters.scala:137:31] assign _legal_address_T_50 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_40; // @[Parameters.scala:137:31] assign _homogeneous_T_40 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_9 = {mpu_physaddr_0[39:32], mpu_physaddr_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _cacheable_T_22; // @[Parameters.scala:137:31] assign _cacheable_T_22 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_88; // @[Parameters.scala:137:31] assign _homogeneous_T_88 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_103; // @[Parameters.scala:137:31] assign _homogeneous_T_103 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_30; // @[Parameters.scala:137:31] assign _prot_w_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_30; // @[Parameters.scala:137:31] assign _prot_al_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_30; // @[Parameters.scala:137:31] assign _prot_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_20; // @[Parameters.scala:137:31] assign _prot_x_T_20 = _GEN_9; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_50; // @[Parameters.scala:137:31] assign _prot_eff_T_50 = _GEN_9; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire _legal_address_T_70 = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire legal_address_0 = _legal_address_T_70; // @[tlb.scala:119:49, :157:84] wire _prot_r_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22] wire [40:0] _cacheable_T_1 = {1'h0, _cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_2 = _cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_3 = _cacheable_T_2; // @[Parameters.scala:137:46] wire _cacheable_T_4 = _cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _cacheable_T_6 = {1'h0, _cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_7 = _cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_8 = _cacheable_T_7; // @[Parameters.scala:137:46] wire _cacheable_T_9 = _cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _cacheable_T_11 = {1'h0, _cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_12 = _cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_13 = _cacheable_T_12; // @[Parameters.scala:137:46] wire _cacheable_T_14 = _cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_15 = _cacheable_T_4 | _cacheable_T_9; // @[Parameters.scala:629:89] wire _cacheable_T_16 = _cacheable_T_15 | _cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _cacheable_T_18 = {1'h0, _cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_19 = _cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_20 = _cacheable_T_19; // @[Parameters.scala:137:46] wire _cacheable_T_21 = _cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _cacheable_T_23 = {1'h0, _cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_24 = _cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_25 = _cacheable_T_24; // @[Parameters.scala:137:46] wire _cacheable_T_26 = _cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_27 = _cacheable_T_21 | _cacheable_T_26; // @[Parameters.scala:629:89] wire _cacheable_T_29 = _cacheable_T_27; // @[Mux.scala:30:73] wire _cacheable_T_30 = _cacheable_T_29; // @[Mux.scala:30:73] wire _cacheable_WIRE = _cacheable_T_30; // @[Mux.scala:30:73] wire _cacheable_T_31 = legal_address_0 & _cacheable_WIRE; // @[Mux.scala:30:73] wire _cacheable_T_32 = _cacheable_T_31; // @[tlb.scala:159:22, :160:66] wire cacheable_0 = _cacheable_T_32; // @[tlb.scala:119:49, :160:66] wire newEntry_c = cacheable_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_59 = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire homogeneous_0 = _homogeneous_T_59; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_62 = {1'h0, _homogeneous_T_61}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_64 = _homogeneous_T_63; // @[Parameters.scala:137:46] wire _homogeneous_T_65 = _homogeneous_T_64 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_66 = _homogeneous_T_65; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_67 = ~_homogeneous_T_66; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_69 = {1'h0, _homogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_71 = _homogeneous_T_70; // @[Parameters.scala:137:46] wire _homogeneous_T_72 = _homogeneous_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_72; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_74 = {1'h0, _homogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_76 = _homogeneous_T_75; // @[Parameters.scala:137:46] wire _homogeneous_T_77 = _homogeneous_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_79 = {1'h0, _homogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_81 = _homogeneous_T_80; // @[Parameters.scala:137:46] wire _homogeneous_T_82 = _homogeneous_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_84 = {1'h0, _homogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_86 = _homogeneous_T_85; // @[Parameters.scala:137:46] wire _homogeneous_T_87 = _homogeneous_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_89 = {1'h0, _homogeneous_T_88}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_91 = _homogeneous_T_90; // @[Parameters.scala:137:46] wire _homogeneous_T_92 = _homogeneous_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_77; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_82; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_87; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_97 = _homogeneous_T_96 | _homogeneous_T_92; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_99 = {1'h0, _homogeneous_T_98}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_101 = _homogeneous_T_100; // @[Parameters.scala:137:46] wire _homogeneous_T_102 = _homogeneous_T_101 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_102; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_104 = {1'h0, _homogeneous_T_103}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_106 = _homogeneous_T_105; // @[Parameters.scala:137:46] wire _homogeneous_T_107 = _homogeneous_T_106 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_109 = _homogeneous_T_108 | _homogeneous_T_107; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_111 = {1'h0, _homogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_113 = _homogeneous_T_112; // @[Parameters.scala:137:46] wire _homogeneous_T_114 = _homogeneous_T_113 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_115 = _homogeneous_T_114; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_116 = ~_homogeneous_T_115; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_118 = {1'h0, _homogeneous_T_117}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_120 = _homogeneous_T_119; // @[Parameters.scala:137:46] wire _homogeneous_T_121 = _homogeneous_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_122 = _homogeneous_T_121; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_123 = ~_homogeneous_T_122; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _prot_r_T_1 = {1'h0, _prot_r_T}; // @[Parameters.scala:137:{31,41}] wire _prot_r_T_6 = _prot_r_T_5 & _pmp_0_io_r; // @[tlb.scala:150:40, :159:22, :162:60] wire prot_r_0 = _prot_r_T_6; // @[tlb.scala:119:49, :162:60] wire newEntry_pr = prot_r_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_w_T_1 = {1'h0, _prot_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_2 = _prot_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_3 = _prot_w_T_2; // @[Parameters.scala:137:46] wire _prot_w_T_4 = _prot_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_6 = {1'h0, _prot_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_7 = _prot_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_8 = _prot_w_T_7; // @[Parameters.scala:137:46] wire _prot_w_T_9 = _prot_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_11 = {1'h0, _prot_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_12 = _prot_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_13 = _prot_w_T_12; // @[Parameters.scala:137:46] wire _prot_w_T_14 = _prot_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_16 = {1'h0, _prot_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_17 = _prot_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_18 = _prot_w_T_17; // @[Parameters.scala:137:46] wire _prot_w_T_19 = _prot_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_21 = {1'h0, _prot_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_22 = _prot_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_23 = _prot_w_T_22; // @[Parameters.scala:137:46] wire _prot_w_T_24 = _prot_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_10 = {mpu_physaddr_0[39:29], mpu_physaddr_0[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [39:0] _prot_w_T_25; // @[Parameters.scala:137:31] assign _prot_w_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_al_T_25; // @[Parameters.scala:137:31] assign _prot_al_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_aa_T_25; // @[Parameters.scala:137:31] assign _prot_aa_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_x_T_54; // @[Parameters.scala:137:31] assign _prot_x_T_54 = _GEN_10; // @[Parameters.scala:137:31] wire [39:0] _prot_eff_T_25; // @[Parameters.scala:137:31] assign _prot_eff_T_25 = _GEN_10; // @[Parameters.scala:137:31] wire [40:0] _prot_w_T_26 = {1'h0, _prot_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_27 = _prot_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_28 = _prot_w_T_27; // @[Parameters.scala:137:46] wire _prot_w_T_29 = _prot_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_w_T_31 = {1'h0, _prot_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_32 = _prot_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_33 = _prot_w_T_32; // @[Parameters.scala:137:46] wire _prot_w_T_34 = _prot_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_w_T_35 = _prot_w_T_4 | _prot_w_T_9; // @[Parameters.scala:629:89] wire _prot_w_T_36 = _prot_w_T_35 | _prot_w_T_14; // @[Parameters.scala:629:89] wire _prot_w_T_37 = _prot_w_T_36 | _prot_w_T_19; // @[Parameters.scala:629:89] wire _prot_w_T_38 = _prot_w_T_37 | _prot_w_T_24; // @[Parameters.scala:629:89] wire _prot_w_T_39 = _prot_w_T_38 | _prot_w_T_29; // @[Parameters.scala:629:89] wire _prot_w_T_40 = _prot_w_T_39 | _prot_w_T_34; // @[Parameters.scala:629:89] wire _prot_w_T_46 = _prot_w_T_40; // @[Mux.scala:30:73] wire [40:0] _prot_w_T_42 = {1'h0, _prot_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_w_T_43 = _prot_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_w_T_44 = _prot_w_T_43; // @[Parameters.scala:137:46] wire _prot_w_T_45 = _prot_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_w_T_48 = _prot_w_T_46; // @[Mux.scala:30:73] wire _prot_w_WIRE = _prot_w_T_48; // @[Mux.scala:30:73] wire _prot_w_T_49 = legal_address_0 & _prot_w_WIRE; // @[Mux.scala:30:73] wire _prot_w_T_50 = _prot_w_T_49 & _pmp_0_io_w; // @[tlb.scala:150:40, :159:22, :163:64] wire prot_w_0 = _prot_w_T_50; // @[tlb.scala:119:49, :163:64] wire newEntry_pw = prot_w_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_al_T_1 = {1'h0, _prot_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_2 = _prot_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_3 = _prot_al_T_2; // @[Parameters.scala:137:46] wire _prot_al_T_4 = _prot_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_6 = {1'h0, _prot_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_7 = _prot_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_8 = _prot_al_T_7; // @[Parameters.scala:137:46] wire _prot_al_T_9 = _prot_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_11 = {1'h0, _prot_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_12 = _prot_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_13 = _prot_al_T_12; // @[Parameters.scala:137:46] wire _prot_al_T_14 = _prot_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_16 = {1'h0, _prot_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_17 = _prot_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_18 = _prot_al_T_17; // @[Parameters.scala:137:46] wire _prot_al_T_19 = _prot_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_21 = {1'h0, _prot_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_22 = _prot_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_23 = _prot_al_T_22; // @[Parameters.scala:137:46] wire _prot_al_T_24 = _prot_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_26 = {1'h0, _prot_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_27 = _prot_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_28 = _prot_al_T_27; // @[Parameters.scala:137:46] wire _prot_al_T_29 = _prot_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_al_T_31 = {1'h0, _prot_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_32 = _prot_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_33 = _prot_al_T_32; // @[Parameters.scala:137:46] wire _prot_al_T_34 = _prot_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_al_T_35 = _prot_al_T_4 | _prot_al_T_9; // @[Parameters.scala:629:89] wire _prot_al_T_36 = _prot_al_T_35 | _prot_al_T_14; // @[Parameters.scala:629:89] wire _prot_al_T_37 = _prot_al_T_36 | _prot_al_T_19; // @[Parameters.scala:629:89] wire _prot_al_T_38 = _prot_al_T_37 | _prot_al_T_24; // @[Parameters.scala:629:89] wire _prot_al_T_39 = _prot_al_T_38 | _prot_al_T_29; // @[Parameters.scala:629:89] wire _prot_al_T_40 = _prot_al_T_39 | _prot_al_T_34; // @[Parameters.scala:629:89] wire _prot_al_T_46 = _prot_al_T_40; // @[Mux.scala:30:73] wire [40:0] _prot_al_T_42 = {1'h0, _prot_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_al_T_43 = _prot_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_al_T_44 = _prot_al_T_43; // @[Parameters.scala:137:46] wire _prot_al_T_45 = _prot_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_al_T_48 = _prot_al_T_46; // @[Mux.scala:30:73] wire _prot_al_WIRE = _prot_al_T_48; // @[Mux.scala:30:73] wire _prot_al_T_49 = legal_address_0 & _prot_al_WIRE; // @[Mux.scala:30:73] wire prot_al_0 = _prot_al_T_49; // @[tlb.scala:119:49, :159:22] wire newEntry_pal = prot_al_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_aa_T_1 = {1'h0, _prot_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_2 = _prot_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_3 = _prot_aa_T_2; // @[Parameters.scala:137:46] wire _prot_aa_T_4 = _prot_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_6 = {1'h0, _prot_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_7 = _prot_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_8 = _prot_aa_T_7; // @[Parameters.scala:137:46] wire _prot_aa_T_9 = _prot_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_11 = {1'h0, _prot_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_12 = _prot_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_13 = _prot_aa_T_12; // @[Parameters.scala:137:46] wire _prot_aa_T_14 = _prot_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_16 = {1'h0, _prot_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_17 = _prot_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_18 = _prot_aa_T_17; // @[Parameters.scala:137:46] wire _prot_aa_T_19 = _prot_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_21 = {1'h0, _prot_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_22 = _prot_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_23 = _prot_aa_T_22; // @[Parameters.scala:137:46] wire _prot_aa_T_24 = _prot_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_26 = {1'h0, _prot_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_27 = _prot_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_28 = _prot_aa_T_27; // @[Parameters.scala:137:46] wire _prot_aa_T_29 = _prot_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_aa_T_31 = {1'h0, _prot_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_32 = _prot_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_33 = _prot_aa_T_32; // @[Parameters.scala:137:46] wire _prot_aa_T_34 = _prot_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_aa_T_35 = _prot_aa_T_4 | _prot_aa_T_9; // @[Parameters.scala:629:89] wire _prot_aa_T_36 = _prot_aa_T_35 | _prot_aa_T_14; // @[Parameters.scala:629:89] wire _prot_aa_T_37 = _prot_aa_T_36 | _prot_aa_T_19; // @[Parameters.scala:629:89] wire _prot_aa_T_38 = _prot_aa_T_37 | _prot_aa_T_24; // @[Parameters.scala:629:89] wire _prot_aa_T_39 = _prot_aa_T_38 | _prot_aa_T_29; // @[Parameters.scala:629:89] wire _prot_aa_T_40 = _prot_aa_T_39 | _prot_aa_T_34; // @[Parameters.scala:629:89] wire _prot_aa_T_46 = _prot_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _prot_aa_T_42 = {1'h0, _prot_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_aa_T_43 = _prot_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_aa_T_44 = _prot_aa_T_43; // @[Parameters.scala:137:46] wire _prot_aa_T_45 = _prot_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_aa_T_48 = _prot_aa_T_46; // @[Mux.scala:30:73] wire _prot_aa_WIRE = _prot_aa_T_48; // @[Mux.scala:30:73] wire _prot_aa_T_49 = legal_address_0 & _prot_aa_WIRE; // @[Mux.scala:30:73] wire prot_aa_0 = _prot_aa_T_49; // @[tlb.scala:119:49, :159:22] wire newEntry_paa = prot_aa_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_x_T_1 = {1'h0, _prot_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_2 = _prot_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_3 = _prot_x_T_2; // @[Parameters.scala:137:46] wire _prot_x_T_4 = _prot_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_6 = {1'h0, _prot_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_7 = _prot_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_8 = _prot_x_T_7; // @[Parameters.scala:137:46] wire _prot_x_T_9 = _prot_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_11 = {1'h0, _prot_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_12 = _prot_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_13 = _prot_x_T_12; // @[Parameters.scala:137:46] wire _prot_x_T_14 = _prot_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_16 = {1'h0, _prot_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_17 = _prot_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_18 = _prot_x_T_17; // @[Parameters.scala:137:46] wire _prot_x_T_19 = _prot_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_21 = {1'h0, _prot_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_22 = _prot_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_23 = _prot_x_T_22; // @[Parameters.scala:137:46] wire _prot_x_T_24 = _prot_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_25 = _prot_x_T_4 | _prot_x_T_9; // @[Parameters.scala:629:89] wire _prot_x_T_26 = _prot_x_T_25 | _prot_x_T_14; // @[Parameters.scala:629:89] wire _prot_x_T_27 = _prot_x_T_26 | _prot_x_T_19; // @[Parameters.scala:629:89] wire _prot_x_T_28 = _prot_x_T_27 | _prot_x_T_24; // @[Parameters.scala:629:89] wire _prot_x_T_64 = _prot_x_T_28; // @[Mux.scala:30:73] wire [40:0] _prot_x_T_30 = {1'h0, _prot_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_31 = _prot_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_32 = _prot_x_T_31; // @[Parameters.scala:137:46] wire _prot_x_T_33 = _prot_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_35 = {1'h0, _prot_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_36 = _prot_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_37 = _prot_x_T_36; // @[Parameters.scala:137:46] wire _prot_x_T_38 = _prot_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_40 = {1'h0, _prot_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_41 = _prot_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_42 = _prot_x_T_41; // @[Parameters.scala:137:46] wire _prot_x_T_43 = _prot_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_45 = {1'h0, _prot_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_46 = _prot_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_47 = _prot_x_T_46; // @[Parameters.scala:137:46] wire _prot_x_T_48 = _prot_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_50 = {1'h0, _prot_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_51 = _prot_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_52 = _prot_x_T_51; // @[Parameters.scala:137:46] wire _prot_x_T_53 = _prot_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_x_T_55 = {1'h0, _prot_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_x_T_56 = _prot_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_x_T_57 = _prot_x_T_56; // @[Parameters.scala:137:46] wire _prot_x_T_58 = _prot_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_x_T_59 = _prot_x_T_33 | _prot_x_T_38; // @[Parameters.scala:629:89] wire _prot_x_T_60 = _prot_x_T_59 | _prot_x_T_43; // @[Parameters.scala:629:89] wire _prot_x_T_61 = _prot_x_T_60 | _prot_x_T_48; // @[Parameters.scala:629:89] wire _prot_x_T_62 = _prot_x_T_61 | _prot_x_T_53; // @[Parameters.scala:629:89] wire _prot_x_T_63 = _prot_x_T_62 | _prot_x_T_58; // @[Parameters.scala:629:89] wire _prot_x_T_66 = _prot_x_T_64; // @[Mux.scala:30:73] wire _prot_x_WIRE = _prot_x_T_66; // @[Mux.scala:30:73] wire _prot_x_T_67 = legal_address_0 & _prot_x_WIRE; // @[Mux.scala:30:73] wire _prot_x_T_68 = _prot_x_T_67 & _pmp_0_io_x; // @[tlb.scala:150:40, :159:22, :166:59] wire prot_x_0 = _prot_x_T_68; // @[tlb.scala:119:49, :166:59] wire newEntry_px = prot_x_0; // @[tlb.scala:119:49, :179:24] wire [40:0] _prot_eff_T_1 = {1'h0, _prot_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_2 = _prot_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_3 = _prot_eff_T_2; // @[Parameters.scala:137:46] wire _prot_eff_T_4 = _prot_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_6 = {1'h0, _prot_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_7 = _prot_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_8 = _prot_eff_T_7; // @[Parameters.scala:137:46] wire _prot_eff_T_9 = _prot_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_11 = {1'h0, _prot_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_12 = _prot_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_13 = _prot_eff_T_12; // @[Parameters.scala:137:46] wire _prot_eff_T_14 = _prot_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_16 = {1'h0, _prot_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_17 = _prot_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_18 = _prot_eff_T_17; // @[Parameters.scala:137:46] wire _prot_eff_T_19 = _prot_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_21 = {1'h0, _prot_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_22 = _prot_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_23 = _prot_eff_T_22; // @[Parameters.scala:137:46] wire _prot_eff_T_24 = _prot_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_26 = {1'h0, _prot_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_27 = _prot_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_28 = _prot_eff_T_27; // @[Parameters.scala:137:46] wire _prot_eff_T_29 = _prot_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_30 = _prot_eff_T_4 | _prot_eff_T_9; // @[Parameters.scala:629:89] wire _prot_eff_T_31 = _prot_eff_T_30 | _prot_eff_T_14; // @[Parameters.scala:629:89] wire _prot_eff_T_32 = _prot_eff_T_31 | _prot_eff_T_19; // @[Parameters.scala:629:89] wire _prot_eff_T_33 = _prot_eff_T_32 | _prot_eff_T_24; // @[Parameters.scala:629:89] wire _prot_eff_T_34 = _prot_eff_T_33 | _prot_eff_T_29; // @[Parameters.scala:629:89] wire _prot_eff_T_58 = _prot_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _prot_eff_T_36 = {1'h0, _prot_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_37 = _prot_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_38 = _prot_eff_T_37; // @[Parameters.scala:137:46] wire _prot_eff_T_39 = _prot_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_41 = {1'h0, _prot_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_42 = _prot_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_43 = _prot_eff_T_42; // @[Parameters.scala:137:46] wire _prot_eff_T_44 = _prot_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_46 = {1'h0, _prot_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_47 = _prot_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_48 = _prot_eff_T_47; // @[Parameters.scala:137:46] wire _prot_eff_T_49 = _prot_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _prot_eff_T_51 = {1'h0, _prot_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _prot_eff_T_52 = _prot_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _prot_eff_T_53 = _prot_eff_T_52; // @[Parameters.scala:137:46] wire _prot_eff_T_54 = _prot_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _prot_eff_T_55 = _prot_eff_T_39 | _prot_eff_T_44; // @[Parameters.scala:629:89] wire _prot_eff_T_56 = _prot_eff_T_55 | _prot_eff_T_49; // @[Parameters.scala:629:89] wire _prot_eff_T_57 = _prot_eff_T_56 | _prot_eff_T_54; // @[Parameters.scala:629:89] wire _prot_eff_T_60 = _prot_eff_T_58; // @[Mux.scala:30:73] wire _prot_eff_WIRE = _prot_eff_T_60; // @[Mux.scala:30:73] wire _prot_eff_T_61 = legal_address_0 & _prot_eff_WIRE; // @[Mux.scala:30:73] wire prot_eff_0 = _prot_eff_T_61; // @[tlb.scala:119:49, :159:22] wire newEntry_eff = prot_eff_0; // @[tlb.scala:119:49, :179:24] wire _GEN_11 = sectored_entries_0_valid_0 | sectored_entries_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_41 = sectored_entries_0_tag ^ vpn_0; // @[tlb.scala:60:43, :119:49, :122:29] wire [26:0] _sector_hits_T_3; // @[tlb.scala:60:43] assign _sector_hits_T_3 = _T_41; // @[tlb.scala:60:43] wire [26:0] _hitsVec_T; // @[tlb.scala:60:43] assign _hitsVec_T = _T_41; // @[tlb.scala:60:43] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_6 = _sector_hits_T_2 & _sector_hits_T_5; // @[package.scala:81:59] wire _sector_hits_WIRE_0 = _sector_hits_T_6; // @[tlb.scala:59:42, :169:42] wire _GEN_12 = sectored_entries_1_valid_0 | sectored_entries_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_7; // @[package.scala:81:59] assign _sector_hits_T_7 = _GEN_12; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_12; // @[package.scala:81:59] wire _sector_hits_T_8 = _sector_hits_T_7 | sectored_entries_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_172 = sectored_entries_1_tag ^ vpn_0; // @[tlb.scala:60:43, :119:49, :122:29] wire [26:0] _sector_hits_T_10; // @[tlb.scala:60:43] assign _sector_hits_T_10 = _T_172; // @[tlb.scala:60:43] wire [26:0] _hitsVec_T_5; // @[tlb.scala:60:43] assign _hitsVec_T_5 = _T_172; // @[tlb.scala:60:43] wire [24:0] _sector_hits_T_11 = _sector_hits_T_10[26:2]; // @[tlb.scala:60:{43,50}] wire _sector_hits_T_12 = _sector_hits_T_11 == 25'h0; // @[tlb.scala:60:{50,73}] wire _sector_hits_T_13 = _sector_hits_T_9 & _sector_hits_T_12; // @[package.scala:81:59] wire _sector_hits_WIRE_1 = _sector_hits_T_13; // @[tlb.scala:59:42, :169:42] wire sector_hits_0_0 = _sector_hits_WIRE_0; // @[tlb.scala:119:49, :169:42] wire sector_hits_0_1 = _sector_hits_WIRE_1; // @[tlb.scala:119:49, :169:42] wire state_reg_touch_way_sized = sector_hits_0_1; // @[package.scala:163:13] wire [8:0] _superpage_hits_T = superpage_entries_0_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_10 = superpage_entries_0_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _superpage_hits_T_1 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_16 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_31 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_46 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_11 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_27 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_43 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_59 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_75 = vpn_0[26:18]; // @[tlb.scala:67:86, :119:49] wire _superpage_hits_T_2 = _superpage_hits_T == _superpage_hits_T_1; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_4 = superpage_entries_0_valid_0 & _superpage_hits_T_3; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_13 = superpage_entries_0_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_1; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_1 = _GEN_13; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_1; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_1 = _GEN_13; // @[tlb.scala:66:30] wire _ppn_ignore_T; // @[tlb.scala:80:31] assign _ppn_ignore_T = _GEN_13; // @[tlb.scala:66:30, :80:31] wire _ignore_T_1; // @[tlb.scala:66:30] assign _ignore_T_1 = _GEN_13; // @[tlb.scala:66:30] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_5 = superpage_entries_0_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_15 = superpage_entries_0_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _superpage_hits_T_6 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_21 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_36 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_51 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_16 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_32 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_48 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_64 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_80 = vpn_0[17:9]; // @[tlb.scala:67:86, :119:49] wire _superpage_hits_T_7 = _superpage_hits_T_5 == _superpage_hits_T_6; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_14 = _superpage_hits_T_9; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_10 = superpage_entries_0_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_20 = superpage_entries_0_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _superpage_hits_T_11 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_26 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_41 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _superpage_hits_T_56 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_21 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_37 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_53 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_69 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire [8:0] _hitsVec_T_85 = vpn_0[8:0]; // @[tlb.scala:67:86, :119:49] wire _superpage_hits_T_12 = _superpage_hits_T_10 == _superpage_hits_T_11; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_0 = _superpage_hits_T_14; // @[tlb.scala:67:31, :170:45] wire [8:0] _superpage_hits_T_15 = superpage_entries_1_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_26 = superpage_entries_1_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_17 = _superpage_hits_T_15 == _superpage_hits_T_16; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_18 = _superpage_hits_T_17; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_19 = superpage_entries_1_valid_0 & _superpage_hits_T_18; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_14 = superpage_entries_1_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_4; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_4 = _GEN_14; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_4; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_4 = _GEN_14; // @[tlb.scala:66:30] wire _ppn_ignore_T_2; // @[tlb.scala:80:31] assign _ppn_ignore_T_2 = _GEN_14; // @[tlb.scala:66:30, :80:31] wire _ignore_T_4; // @[tlb.scala:66:30] assign _ignore_T_4 = _GEN_14; // @[tlb.scala:66:30] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_20 = superpage_entries_1_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_31 = superpage_entries_1_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_22 = _superpage_hits_T_20 == _superpage_hits_T_21; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_23 = superpage_hits_ignore_4 | _superpage_hits_T_22; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_24 = _superpage_hits_T_19 & _superpage_hits_T_23; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_29 = _superpage_hits_T_24; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_25 = superpage_entries_1_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_36 = superpage_entries_1_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_27 = _superpage_hits_T_25 == _superpage_hits_T_26; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_1 = _superpage_hits_T_29; // @[tlb.scala:67:31, :170:45] wire [8:0] _superpage_hits_T_30 = superpage_entries_2_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_42 = superpage_entries_2_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_32 = _superpage_hits_T_30 == _superpage_hits_T_31; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_33 = _superpage_hits_T_32; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_34 = superpage_entries_2_valid_0 & _superpage_hits_T_33; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_15 = superpage_entries_2_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_7; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_7 = _GEN_15; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_7; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_7 = _GEN_15; // @[tlb.scala:66:30] wire _ppn_ignore_T_4; // @[tlb.scala:80:31] assign _ppn_ignore_T_4 = _GEN_15; // @[tlb.scala:66:30, :80:31] wire _ignore_T_7; // @[tlb.scala:66:30] assign _ignore_T_7 = _GEN_15; // @[tlb.scala:66:30] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_35 = superpage_entries_2_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_47 = superpage_entries_2_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_37 = _superpage_hits_T_35 == _superpage_hits_T_36; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_38 = superpage_hits_ignore_7 | _superpage_hits_T_37; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_39 = _superpage_hits_T_34 & _superpage_hits_T_38; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_44 = _superpage_hits_T_39; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_40 = superpage_entries_2_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_52 = superpage_entries_2_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_42 = _superpage_hits_T_40 == _superpage_hits_T_41; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_2 = _superpage_hits_T_44; // @[tlb.scala:67:31, :170:45] wire [8:0] _superpage_hits_T_45 = superpage_entries_3_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_58 = superpage_entries_3_tag[26:18]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_47 = _superpage_hits_T_45 == _superpage_hits_T_46; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_48 = _superpage_hits_T_47; // @[tlb.scala:67:{42,79}] wire _superpage_hits_T_49 = superpage_entries_3_valid_0 & _superpage_hits_T_48; // @[tlb.scala:67:{31,42}, :123:30] wire _GEN_16 = superpage_entries_3_level == 2'h0; // @[tlb.scala:66:30, :123:30] wire _superpage_hits_ignore_T_10; // @[tlb.scala:66:30] assign _superpage_hits_ignore_T_10 = _GEN_16; // @[tlb.scala:66:30] wire _hitsVec_ignore_T_10; // @[tlb.scala:66:30] assign _hitsVec_ignore_T_10 = _GEN_16; // @[tlb.scala:66:30] wire _ppn_ignore_T_6; // @[tlb.scala:80:31] assign _ppn_ignore_T_6 = _GEN_16; // @[tlb.scala:66:30, :80:31] wire _ignore_T_10; // @[tlb.scala:66:30] assign _ignore_T_10 = _GEN_16; // @[tlb.scala:66:30] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[tlb.scala:66:{30,36}] wire [8:0] _superpage_hits_T_50 = superpage_entries_3_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_63 = superpage_entries_3_tag[17:9]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_52 = _superpage_hits_T_50 == _superpage_hits_T_51; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_T_53 = superpage_hits_ignore_10 | _superpage_hits_T_52; // @[tlb.scala:66:36, :67:{42,79}] wire _superpage_hits_T_54 = _superpage_hits_T_49 & _superpage_hits_T_53; // @[tlb.scala:67:{31,42}] wire _superpage_hits_T_59 = _superpage_hits_T_54; // @[tlb.scala:67:31] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[tlb.scala:66:30, :123:30] wire [8:0] _superpage_hits_T_55 = superpage_entries_3_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire [8:0] _hitsVec_T_68 = superpage_entries_3_tag[8:0]; // @[tlb.scala:67:48, :123:30] wire _superpage_hits_T_57 = _superpage_hits_T_55 == _superpage_hits_T_56; // @[tlb.scala:67:{48,79,86}] wire _superpage_hits_WIRE_3 = _superpage_hits_T_59; // @[tlb.scala:67:31, :170:45] wire superpage_hits_0_0 = _superpage_hits_WIRE_0; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_1 = _superpage_hits_WIRE_1; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_2 = _superpage_hits_WIRE_2; // @[tlb.scala:119:49, :170:45] wire superpage_hits_0_3 = _superpage_hits_WIRE_3; // @[tlb.scala:119:49, :170:45] wire [1:0] hitsVec_idx = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _ppn_data_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T = vpn_0[1:0]; // @[package.scala:163:13] wire [1:0] _normal_entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[tlb.scala:60:{50,73}] wire [3:0] _GEN_17 = {{sectored_entries_0_valid_3}, {sectored_entries_0_valid_2}, {sectored_entries_0_valid_1}, {sectored_entries_0_valid_0}}; // @[tlb.scala:72:20, :122:29] wire _hitsVec_T_3 = _GEN_17[hitsVec_idx] & _hitsVec_T_2; // @[package.scala:163:13] wire _hitsVec_T_4 = vm_enabled_0 & _hitsVec_T_3; // @[tlb.scala:72:20, :119:49, :171:69] wire _hitsVec_WIRE_0 = _hitsVec_T_4; // @[tlb.scala:171:{38,69}] wire [24:0] _hitsVec_T_6 = _hitsVec_T_5[26:2]; // @[tlb.scala:60:{43,50}] wire _hitsVec_T_7 = _hitsVec_T_6 == 25'h0; // @[tlb.scala:60:{50,73}] wire [3:0] _GEN_18 = {{sectored_entries_1_valid_3}, {sectored_entries_1_valid_2}, {sectored_entries_1_valid_1}, {sectored_entries_1_valid_0}}; // @[tlb.scala:72:20, :122:29] wire _hitsVec_T_8 = _GEN_18[hitsVec_idx_1] & _hitsVec_T_7; // @[package.scala:163:13] wire _hitsVec_T_9 = vm_enabled_0 & _hitsVec_T_8; // @[tlb.scala:72:20, :119:49, :171:69] wire _hitsVec_WIRE_1 = _hitsVec_T_9; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_12 = _hitsVec_T_10 == _hitsVec_T_11; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_13 = _hitsVec_T_12; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_14 = superpage_entries_0_valid_0 & _hitsVec_T_13; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_17 = _hitsVec_T_15 == _hitsVec_T_16; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_18 = hitsVec_ignore_1 | _hitsVec_T_17; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_19 = _hitsVec_T_14 & _hitsVec_T_18; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_24 = _hitsVec_T_19; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_22 = _hitsVec_T_20 == _hitsVec_T_21; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_25 = vm_enabled_0 & _hitsVec_T_24; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_2 = _hitsVec_T_25; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_28 = _hitsVec_T_26 == _hitsVec_T_27; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_29 = _hitsVec_T_28; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_30 = superpage_entries_1_valid_0 & _hitsVec_T_29; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_33 = _hitsVec_T_31 == _hitsVec_T_32; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_34 = hitsVec_ignore_4 | _hitsVec_T_33; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_35 = _hitsVec_T_30 & _hitsVec_T_34; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_40 = _hitsVec_T_35; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_38 = _hitsVec_T_36 == _hitsVec_T_37; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_41 = vm_enabled_0 & _hitsVec_T_40; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_3 = _hitsVec_T_41; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_44 = _hitsVec_T_42 == _hitsVec_T_43; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_45 = _hitsVec_T_44; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_46 = superpage_entries_2_valid_0 & _hitsVec_T_45; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_49 = _hitsVec_T_47 == _hitsVec_T_48; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_50 = hitsVec_ignore_7 | _hitsVec_T_49; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_51 = _hitsVec_T_46 & _hitsVec_T_50; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_56 = _hitsVec_T_51; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_54 = _hitsVec_T_52 == _hitsVec_T_53; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_57 = vm_enabled_0 & _hitsVec_T_56; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_4 = _hitsVec_T_57; // @[tlb.scala:171:{38,69}] wire _hitsVec_T_60 = _hitsVec_T_58 == _hitsVec_T_59; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_61 = _hitsVec_T_60; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_62 = superpage_entries_3_valid_0 & _hitsVec_T_61; // @[tlb.scala:67:{31,42}, :123:30] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[tlb.scala:66:{30,36}] wire _hitsVec_T_65 = _hitsVec_T_63 == _hitsVec_T_64; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_66 = hitsVec_ignore_10 | _hitsVec_T_65; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_67 = _hitsVec_T_62 & _hitsVec_T_66; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_72 = _hitsVec_T_67; // @[tlb.scala:67:31] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[tlb.scala:66:30, :123:30] wire _hitsVec_T_70 = _hitsVec_T_68 == _hitsVec_T_69; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_73 = vm_enabled_0 & _hitsVec_T_72; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_5 = _hitsVec_T_73; // @[tlb.scala:171:{38,69}] wire [8:0] _hitsVec_T_74 = special_entry_tag[26:18]; // @[tlb.scala:67:48, :124:56] wire _hitsVec_T_76 = _hitsVec_T_74 == _hitsVec_T_75; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_77 = _hitsVec_T_76; // @[tlb.scala:67:{42,79}] wire _hitsVec_T_78 = special_entry_valid_0 & _hitsVec_T_77; // @[tlb.scala:67:{31,42}, :124:56] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[tlb.scala:66:{30,36}] wire [8:0] _hitsVec_T_79 = special_entry_tag[17:9]; // @[tlb.scala:67:48, :124:56] wire _hitsVec_T_81 = _hitsVec_T_79 == _hitsVec_T_80; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_82 = hitsVec_ignore_13 | _hitsVec_T_81; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_83 = _hitsVec_T_78 & _hitsVec_T_82; // @[tlb.scala:67:{31,42}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[tlb.scala:66:30, :80:31, :124:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[tlb.scala:66:{30,36}] wire [8:0] _hitsVec_T_84 = special_entry_tag[8:0]; // @[tlb.scala:67:48, :124:56] wire _hitsVec_T_86 = _hitsVec_T_84 == _hitsVec_T_85; // @[tlb.scala:67:{48,79,86}] wire _hitsVec_T_87 = hitsVec_ignore_14 | _hitsVec_T_86; // @[tlb.scala:66:36, :67:{42,79}] wire _hitsVec_T_88 = _hitsVec_T_83 & _hitsVec_T_87; // @[tlb.scala:67:{31,42}] wire _hitsVec_T_89 = vm_enabled_0 & _hitsVec_T_88; // @[tlb.scala:67:31, :119:49, :171:69] wire _hitsVec_WIRE_6 = _hitsVec_T_89; // @[tlb.scala:171:{38,69}] wire hitsVec_0_0 = _hitsVec_WIRE_0; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_1 = _hitsVec_WIRE_1; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_2 = _hitsVec_WIRE_2; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_3 = _hitsVec_WIRE_3; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_4 = _hitsVec_WIRE_4; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_5 = _hitsVec_WIRE_5; // @[tlb.scala:119:49, :171:38] wire hitsVec_0_6 = _hitsVec_WIRE_6; // @[tlb.scala:119:49, :171:38] wire [1:0] real_hits_lo_hi = {hitsVec_0_2, hitsVec_0_1}; // @[tlb.scala:119:49, :172:44] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0_0}; // @[tlb.scala:119:49, :172:44] wire [1:0] real_hits_hi_lo = {hitsVec_0_4, hitsVec_0_3}; // @[tlb.scala:119:49, :172:44] wire [1:0] real_hits_hi_hi = {hitsVec_0_6, hitsVec_0_5}; // @[tlb.scala:119:49, :172:44] wire [3:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[tlb.scala:172:44] wire [6:0] _real_hits_T = {real_hits_hi, real_hits_lo}; // @[tlb.scala:172:44] wire [6:0] real_hits_0 = _real_hits_T; // @[tlb.scala:119:49, :172:44] wire _hits_T = ~vm_enabled_0; // @[tlb.scala:119:49, :173:32] wire [7:0] _hits_T_1 = {_hits_T, real_hits_0}; // @[tlb.scala:119:49, :173:{31,32}] wire [7:0] hits_0 = _hits_T_1; // @[tlb.scala:119:49, :173:31] wire _ppn_T = ~vm_enabled_0; // @[tlb.scala:119:49, :173:32, :174:47] wire [19:0] _ppn_data_T_15; // @[tlb.scala:58:79] wire _ppn_data_T_14; // @[tlb.scala:58:79] wire _ppn_data_T_13; // @[tlb.scala:58:79] wire _ppn_data_T_12; // @[tlb.scala:58:79] wire _ppn_data_T_11; // @[tlb.scala:58:79] wire _ppn_data_T_10; // @[tlb.scala:58:79] wire _ppn_data_T_9; // @[tlb.scala:58:79] wire _ppn_data_T_8; // @[tlb.scala:58:79] wire _ppn_data_T_7; // @[tlb.scala:58:79] wire _ppn_data_T_6; // @[tlb.scala:58:79] wire _ppn_data_T_5; // @[tlb.scala:58:79] wire _ppn_data_T_4; // @[tlb.scala:58:79] wire _ppn_data_T_3; // @[tlb.scala:58:79] wire _ppn_data_T_2; // @[tlb.scala:58:79] wire _ppn_data_T_1; // @[tlb.scala:58:79] wire [3:0][33:0] _GEN_19 = {{sectored_entries_0_data_3}, {sectored_entries_0_data_2}, {sectored_entries_0_data_1}, {sectored_entries_0_data_0}}; // @[tlb.scala:58:79, :122:29] wire [33:0] _ppn_data_WIRE_1 = _GEN_19[_ppn_data_T]; // @[package.scala:163:13] assign _ppn_data_T_1 = _ppn_data_WIRE_1[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_fragmented_superpage = _ppn_data_T_1; // @[tlb.scala:58:79] assign _ppn_data_T_2 = _ppn_data_WIRE_1[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_c = _ppn_data_T_2; // @[tlb.scala:58:79] assign _ppn_data_T_3 = _ppn_data_WIRE_1[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_eff = _ppn_data_T_3; // @[tlb.scala:58:79] assign _ppn_data_T_4 = _ppn_data_WIRE_1[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_paa = _ppn_data_T_4; // @[tlb.scala:58:79] assign _ppn_data_T_5 = _ppn_data_WIRE_1[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pal = _ppn_data_T_5; // @[tlb.scala:58:79] assign _ppn_data_T_6 = _ppn_data_WIRE_1[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pr = _ppn_data_T_6; // @[tlb.scala:58:79] assign _ppn_data_T_7 = _ppn_data_WIRE_1[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_px = _ppn_data_T_7; // @[tlb.scala:58:79] assign _ppn_data_T_8 = _ppn_data_WIRE_1[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_pw = _ppn_data_T_8; // @[tlb.scala:58:79] assign _ppn_data_T_9 = _ppn_data_WIRE_1[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sr = _ppn_data_T_9; // @[tlb.scala:58:79] assign _ppn_data_T_10 = _ppn_data_WIRE_1[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sx = _ppn_data_T_10; // @[tlb.scala:58:79] assign _ppn_data_T_11 = _ppn_data_WIRE_1[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_sw = _ppn_data_T_11; // @[tlb.scala:58:79] assign _ppn_data_T_12 = _ppn_data_WIRE_1[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_ae = _ppn_data_T_12; // @[tlb.scala:58:79] assign _ppn_data_T_13 = _ppn_data_WIRE_1[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_g = _ppn_data_T_13; // @[tlb.scala:58:79] assign _ppn_data_T_14 = _ppn_data_WIRE_1[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_u = _ppn_data_T_14; // @[tlb.scala:58:79] assign _ppn_data_T_15 = _ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_ppn = _ppn_data_T_15; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_31; // @[tlb.scala:58:79] wire _ppn_data_T_30; // @[tlb.scala:58:79] wire _ppn_data_T_29; // @[tlb.scala:58:79] wire _ppn_data_T_28; // @[tlb.scala:58:79] wire _ppn_data_T_27; // @[tlb.scala:58:79] wire _ppn_data_T_26; // @[tlb.scala:58:79] wire _ppn_data_T_25; // @[tlb.scala:58:79] wire _ppn_data_T_24; // @[tlb.scala:58:79] wire _ppn_data_T_23; // @[tlb.scala:58:79] wire _ppn_data_T_22; // @[tlb.scala:58:79] wire _ppn_data_T_21; // @[tlb.scala:58:79] wire _ppn_data_T_20; // @[tlb.scala:58:79] wire _ppn_data_T_19; // @[tlb.scala:58:79] wire _ppn_data_T_18; // @[tlb.scala:58:79] wire _ppn_data_T_17; // @[tlb.scala:58:79] wire [3:0][33:0] _GEN_20 = {{sectored_entries_1_data_3}, {sectored_entries_1_data_2}, {sectored_entries_1_data_1}, {sectored_entries_1_data_0}}; // @[tlb.scala:58:79, :122:29] wire [33:0] _ppn_data_WIRE_3 = _GEN_20[_ppn_data_T_16]; // @[package.scala:163:13] assign _ppn_data_T_17 = _ppn_data_WIRE_3[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_fragmented_superpage = _ppn_data_T_17; // @[tlb.scala:58:79] assign _ppn_data_T_18 = _ppn_data_WIRE_3[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_c = _ppn_data_T_18; // @[tlb.scala:58:79] assign _ppn_data_T_19 = _ppn_data_WIRE_3[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_eff = _ppn_data_T_19; // @[tlb.scala:58:79] assign _ppn_data_T_20 = _ppn_data_WIRE_3[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_paa = _ppn_data_T_20; // @[tlb.scala:58:79] assign _ppn_data_T_21 = _ppn_data_WIRE_3[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pal = _ppn_data_T_21; // @[tlb.scala:58:79] assign _ppn_data_T_22 = _ppn_data_WIRE_3[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pr = _ppn_data_T_22; // @[tlb.scala:58:79] assign _ppn_data_T_23 = _ppn_data_WIRE_3[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_px = _ppn_data_T_23; // @[tlb.scala:58:79] assign _ppn_data_T_24 = _ppn_data_WIRE_3[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_pw = _ppn_data_T_24; // @[tlb.scala:58:79] assign _ppn_data_T_25 = _ppn_data_WIRE_3[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sr = _ppn_data_T_25; // @[tlb.scala:58:79] assign _ppn_data_T_26 = _ppn_data_WIRE_3[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sx = _ppn_data_T_26; // @[tlb.scala:58:79] assign _ppn_data_T_27 = _ppn_data_WIRE_3[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_sw = _ppn_data_T_27; // @[tlb.scala:58:79] assign _ppn_data_T_28 = _ppn_data_WIRE_3[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_ae = _ppn_data_T_28; // @[tlb.scala:58:79] assign _ppn_data_T_29 = _ppn_data_WIRE_3[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_g = _ppn_data_T_29; // @[tlb.scala:58:79] assign _ppn_data_T_30 = _ppn_data_WIRE_3[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_2_u = _ppn_data_T_30; // @[tlb.scala:58:79] assign _ppn_data_T_31 = _ppn_data_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_2_ppn = _ppn_data_T_31; // @[tlb.scala:58:79] wire [19:0] _ppn_data_T_46; // @[tlb.scala:58:79] wire _ppn_data_T_45; // @[tlb.scala:58:79] wire _ppn_data_T_44; // @[tlb.scala:58:79] wire _ppn_data_T_43; // @[tlb.scala:58:79] wire _ppn_data_T_42; // @[tlb.scala:58:79] wire _ppn_data_T_41; // @[tlb.scala:58:79] wire _ppn_data_T_40; // @[tlb.scala:58:79] wire _ppn_data_T_39; // @[tlb.scala:58:79] wire _ppn_data_T_38; // @[tlb.scala:58:79] wire _ppn_data_T_37; // @[tlb.scala:58:79] wire _ppn_data_T_36; // @[tlb.scala:58:79] wire _ppn_data_T_35; // @[tlb.scala:58:79] wire _ppn_data_T_34; // @[tlb.scala:58:79] wire _ppn_data_T_33; // @[tlb.scala:58:79] wire _ppn_data_T_32; // @[tlb.scala:58:79] assign _ppn_data_T_32 = _ppn_data_WIRE_5[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_fragmented_superpage = _ppn_data_T_32; // @[tlb.scala:58:79] assign _ppn_data_T_33 = _ppn_data_WIRE_5[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_c = _ppn_data_T_33; // @[tlb.scala:58:79] assign _ppn_data_T_34 = _ppn_data_WIRE_5[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_eff = _ppn_data_T_34; // @[tlb.scala:58:79] assign _ppn_data_T_35 = _ppn_data_WIRE_5[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_paa = _ppn_data_T_35; // @[tlb.scala:58:79] assign _ppn_data_T_36 = _ppn_data_WIRE_5[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pal = _ppn_data_T_36; // @[tlb.scala:58:79] assign _ppn_data_T_37 = _ppn_data_WIRE_5[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pr = _ppn_data_T_37; // @[tlb.scala:58:79] assign _ppn_data_T_38 = _ppn_data_WIRE_5[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_px = _ppn_data_T_38; // @[tlb.scala:58:79] assign _ppn_data_T_39 = _ppn_data_WIRE_5[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_pw = _ppn_data_T_39; // @[tlb.scala:58:79] assign _ppn_data_T_40 = _ppn_data_WIRE_5[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sr = _ppn_data_T_40; // @[tlb.scala:58:79] assign _ppn_data_T_41 = _ppn_data_WIRE_5[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sx = _ppn_data_T_41; // @[tlb.scala:58:79] assign _ppn_data_T_42 = _ppn_data_WIRE_5[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_sw = _ppn_data_T_42; // @[tlb.scala:58:79] assign _ppn_data_T_43 = _ppn_data_WIRE_5[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_ae = _ppn_data_T_43; // @[tlb.scala:58:79] assign _ppn_data_T_44 = _ppn_data_WIRE_5[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_g = _ppn_data_T_44; // @[tlb.scala:58:79] assign _ppn_data_T_45 = _ppn_data_WIRE_5[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_4_u = _ppn_data_T_45; // @[tlb.scala:58:79] assign _ppn_data_T_46 = _ppn_data_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_4_ppn = _ppn_data_T_46; // @[tlb.scala:58:79] wire [1:0] ppn_res = _ppn_data_barrier_2_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _ppn_data_barrier_2_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _ppn_data_barrier_2_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_61; // @[tlb.scala:58:79] wire _ppn_data_T_60; // @[tlb.scala:58:79] wire _ppn_data_T_59; // @[tlb.scala:58:79] wire _ppn_data_T_58; // @[tlb.scala:58:79] wire _ppn_data_T_57; // @[tlb.scala:58:79] wire _ppn_data_T_56; // @[tlb.scala:58:79] wire _ppn_data_T_55; // @[tlb.scala:58:79] wire _ppn_data_T_54; // @[tlb.scala:58:79] wire _ppn_data_T_53; // @[tlb.scala:58:79] wire _ppn_data_T_52; // @[tlb.scala:58:79] wire _ppn_data_T_51; // @[tlb.scala:58:79] wire _ppn_data_T_50; // @[tlb.scala:58:79] wire _ppn_data_T_49; // @[tlb.scala:58:79] wire _ppn_data_T_48; // @[tlb.scala:58:79] wire _ppn_data_T_47; // @[tlb.scala:58:79] assign _ppn_data_T_47 = _ppn_data_WIRE_7[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_fragmented_superpage = _ppn_data_T_47; // @[tlb.scala:58:79] assign _ppn_data_T_48 = _ppn_data_WIRE_7[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_c = _ppn_data_T_48; // @[tlb.scala:58:79] assign _ppn_data_T_49 = _ppn_data_WIRE_7[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_eff = _ppn_data_T_49; // @[tlb.scala:58:79] assign _ppn_data_T_50 = _ppn_data_WIRE_7[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_paa = _ppn_data_T_50; // @[tlb.scala:58:79] assign _ppn_data_T_51 = _ppn_data_WIRE_7[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pal = _ppn_data_T_51; // @[tlb.scala:58:79] assign _ppn_data_T_52 = _ppn_data_WIRE_7[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pr = _ppn_data_T_52; // @[tlb.scala:58:79] assign _ppn_data_T_53 = _ppn_data_WIRE_7[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_px = _ppn_data_T_53; // @[tlb.scala:58:79] assign _ppn_data_T_54 = _ppn_data_WIRE_7[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_pw = _ppn_data_T_54; // @[tlb.scala:58:79] assign _ppn_data_T_55 = _ppn_data_WIRE_7[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sr = _ppn_data_T_55; // @[tlb.scala:58:79] assign _ppn_data_T_56 = _ppn_data_WIRE_7[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sx = _ppn_data_T_56; // @[tlb.scala:58:79] assign _ppn_data_T_57 = _ppn_data_WIRE_7[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_sw = _ppn_data_T_57; // @[tlb.scala:58:79] assign _ppn_data_T_58 = _ppn_data_WIRE_7[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_ae = _ppn_data_T_58; // @[tlb.scala:58:79] assign _ppn_data_T_59 = _ppn_data_WIRE_7[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_g = _ppn_data_T_59; // @[tlb.scala:58:79] assign _ppn_data_T_60 = _ppn_data_WIRE_7[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_6_u = _ppn_data_T_60; // @[tlb.scala:58:79] assign _ppn_data_T_61 = _ppn_data_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_6_ppn = _ppn_data_T_61; // @[tlb.scala:58:79] wire [1:0] ppn_res_1 = _ppn_data_barrier_3_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _ppn_data_barrier_3_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _ppn_data_barrier_3_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_76; // @[tlb.scala:58:79] wire _ppn_data_T_75; // @[tlb.scala:58:79] wire _ppn_data_T_74; // @[tlb.scala:58:79] wire _ppn_data_T_73; // @[tlb.scala:58:79] wire _ppn_data_T_72; // @[tlb.scala:58:79] wire _ppn_data_T_71; // @[tlb.scala:58:79] wire _ppn_data_T_70; // @[tlb.scala:58:79] wire _ppn_data_T_69; // @[tlb.scala:58:79] wire _ppn_data_T_68; // @[tlb.scala:58:79] wire _ppn_data_T_67; // @[tlb.scala:58:79] wire _ppn_data_T_66; // @[tlb.scala:58:79] wire _ppn_data_T_65; // @[tlb.scala:58:79] wire _ppn_data_T_64; // @[tlb.scala:58:79] wire _ppn_data_T_63; // @[tlb.scala:58:79] wire _ppn_data_T_62; // @[tlb.scala:58:79] assign _ppn_data_T_62 = _ppn_data_WIRE_9[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_fragmented_superpage = _ppn_data_T_62; // @[tlb.scala:58:79] assign _ppn_data_T_63 = _ppn_data_WIRE_9[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_c = _ppn_data_T_63; // @[tlb.scala:58:79] assign _ppn_data_T_64 = _ppn_data_WIRE_9[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_eff = _ppn_data_T_64; // @[tlb.scala:58:79] assign _ppn_data_T_65 = _ppn_data_WIRE_9[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_paa = _ppn_data_T_65; // @[tlb.scala:58:79] assign _ppn_data_T_66 = _ppn_data_WIRE_9[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pal = _ppn_data_T_66; // @[tlb.scala:58:79] assign _ppn_data_T_67 = _ppn_data_WIRE_9[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pr = _ppn_data_T_67; // @[tlb.scala:58:79] assign _ppn_data_T_68 = _ppn_data_WIRE_9[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_px = _ppn_data_T_68; // @[tlb.scala:58:79] assign _ppn_data_T_69 = _ppn_data_WIRE_9[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_pw = _ppn_data_T_69; // @[tlb.scala:58:79] assign _ppn_data_T_70 = _ppn_data_WIRE_9[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sr = _ppn_data_T_70; // @[tlb.scala:58:79] assign _ppn_data_T_71 = _ppn_data_WIRE_9[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sx = _ppn_data_T_71; // @[tlb.scala:58:79] assign _ppn_data_T_72 = _ppn_data_WIRE_9[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_sw = _ppn_data_T_72; // @[tlb.scala:58:79] assign _ppn_data_T_73 = _ppn_data_WIRE_9[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_ae = _ppn_data_T_73; // @[tlb.scala:58:79] assign _ppn_data_T_74 = _ppn_data_WIRE_9[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_g = _ppn_data_T_74; // @[tlb.scala:58:79] assign _ppn_data_T_75 = _ppn_data_WIRE_9[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_8_u = _ppn_data_T_75; // @[tlb.scala:58:79] assign _ppn_data_T_76 = _ppn_data_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_8_ppn = _ppn_data_T_76; // @[tlb.scala:58:79] wire [1:0] ppn_res_2 = _ppn_data_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _ppn_data_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _ppn_data_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_91; // @[tlb.scala:58:79] wire _ppn_data_T_90; // @[tlb.scala:58:79] wire _ppn_data_T_89; // @[tlb.scala:58:79] wire _ppn_data_T_88; // @[tlb.scala:58:79] wire _ppn_data_T_87; // @[tlb.scala:58:79] wire _ppn_data_T_86; // @[tlb.scala:58:79] wire _ppn_data_T_85; // @[tlb.scala:58:79] wire _ppn_data_T_84; // @[tlb.scala:58:79] wire _ppn_data_T_83; // @[tlb.scala:58:79] wire _ppn_data_T_82; // @[tlb.scala:58:79] wire _ppn_data_T_81; // @[tlb.scala:58:79] wire _ppn_data_T_80; // @[tlb.scala:58:79] wire _ppn_data_T_79; // @[tlb.scala:58:79] wire _ppn_data_T_78; // @[tlb.scala:58:79] wire _ppn_data_T_77; // @[tlb.scala:58:79] assign _ppn_data_T_77 = _ppn_data_WIRE_11[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_fragmented_superpage = _ppn_data_T_77; // @[tlb.scala:58:79] assign _ppn_data_T_78 = _ppn_data_WIRE_11[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_c = _ppn_data_T_78; // @[tlb.scala:58:79] assign _ppn_data_T_79 = _ppn_data_WIRE_11[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_eff = _ppn_data_T_79; // @[tlb.scala:58:79] assign _ppn_data_T_80 = _ppn_data_WIRE_11[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_paa = _ppn_data_T_80; // @[tlb.scala:58:79] assign _ppn_data_T_81 = _ppn_data_WIRE_11[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pal = _ppn_data_T_81; // @[tlb.scala:58:79] assign _ppn_data_T_82 = _ppn_data_WIRE_11[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pr = _ppn_data_T_82; // @[tlb.scala:58:79] assign _ppn_data_T_83 = _ppn_data_WIRE_11[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_px = _ppn_data_T_83; // @[tlb.scala:58:79] assign _ppn_data_T_84 = _ppn_data_WIRE_11[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_pw = _ppn_data_T_84; // @[tlb.scala:58:79] assign _ppn_data_T_85 = _ppn_data_WIRE_11[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sr = _ppn_data_T_85; // @[tlb.scala:58:79] assign _ppn_data_T_86 = _ppn_data_WIRE_11[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sx = _ppn_data_T_86; // @[tlb.scala:58:79] assign _ppn_data_T_87 = _ppn_data_WIRE_11[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_sw = _ppn_data_T_87; // @[tlb.scala:58:79] assign _ppn_data_T_88 = _ppn_data_WIRE_11[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_ae = _ppn_data_T_88; // @[tlb.scala:58:79] assign _ppn_data_T_89 = _ppn_data_WIRE_11[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_g = _ppn_data_T_89; // @[tlb.scala:58:79] assign _ppn_data_T_90 = _ppn_data_WIRE_11[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_10_u = _ppn_data_T_90; // @[tlb.scala:58:79] assign _ppn_data_T_91 = _ppn_data_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_10_ppn = _ppn_data_T_91; // @[tlb.scala:58:79] wire [1:0] ppn_res_3 = _ppn_data_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _ppn_data_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[tlb.scala:66:30, :80:31, :123:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _ppn_data_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_data_T_106; // @[tlb.scala:58:79] wire _ppn_data_T_105; // @[tlb.scala:58:79] wire _ppn_data_T_104; // @[tlb.scala:58:79] wire _ppn_data_T_103; // @[tlb.scala:58:79] wire _ppn_data_T_102; // @[tlb.scala:58:79] wire _ppn_data_T_101; // @[tlb.scala:58:79] wire _ppn_data_T_100; // @[tlb.scala:58:79] wire _ppn_data_T_99; // @[tlb.scala:58:79] wire _ppn_data_T_98; // @[tlb.scala:58:79] wire _ppn_data_T_97; // @[tlb.scala:58:79] wire _ppn_data_T_96; // @[tlb.scala:58:79] wire _ppn_data_T_95; // @[tlb.scala:58:79] wire _ppn_data_T_94; // @[tlb.scala:58:79] wire _ppn_data_T_93; // @[tlb.scala:58:79] wire _ppn_data_T_92; // @[tlb.scala:58:79] assign _ppn_data_T_92 = _ppn_data_WIRE_13[0]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_fragmented_superpage = _ppn_data_T_92; // @[tlb.scala:58:79] assign _ppn_data_T_93 = _ppn_data_WIRE_13[1]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_c = _ppn_data_T_93; // @[tlb.scala:58:79] assign _ppn_data_T_94 = _ppn_data_WIRE_13[2]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_eff = _ppn_data_T_94; // @[tlb.scala:58:79] assign _ppn_data_T_95 = _ppn_data_WIRE_13[3]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_paa = _ppn_data_T_95; // @[tlb.scala:58:79] assign _ppn_data_T_96 = _ppn_data_WIRE_13[4]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pal = _ppn_data_T_96; // @[tlb.scala:58:79] assign _ppn_data_T_97 = _ppn_data_WIRE_13[5]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pr = _ppn_data_T_97; // @[tlb.scala:58:79] assign _ppn_data_T_98 = _ppn_data_WIRE_13[6]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_px = _ppn_data_T_98; // @[tlb.scala:58:79] assign _ppn_data_T_99 = _ppn_data_WIRE_13[7]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_pw = _ppn_data_T_99; // @[tlb.scala:58:79] assign _ppn_data_T_100 = _ppn_data_WIRE_13[8]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sr = _ppn_data_T_100; // @[tlb.scala:58:79] assign _ppn_data_T_101 = _ppn_data_WIRE_13[9]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sx = _ppn_data_T_101; // @[tlb.scala:58:79] assign _ppn_data_T_102 = _ppn_data_WIRE_13[10]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_sw = _ppn_data_T_102; // @[tlb.scala:58:79] assign _ppn_data_T_103 = _ppn_data_WIRE_13[11]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_ae = _ppn_data_T_103; // @[tlb.scala:58:79] assign _ppn_data_T_104 = _ppn_data_WIRE_13[12]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_g = _ppn_data_T_104; // @[tlb.scala:58:79] assign _ppn_data_T_105 = _ppn_data_WIRE_13[13]; // @[tlb.scala:58:79] wire _ppn_data_WIRE_12_u = _ppn_data_T_105; // @[tlb.scala:58:79] assign _ppn_data_T_106 = _ppn_data_WIRE_13[33:14]; // @[tlb.scala:58:79] wire [19:0] _ppn_data_WIRE_12_ppn = _ppn_data_T_106; // @[tlb.scala:58:79] wire [1:0] ppn_res_4 = _ppn_data_barrier_6_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _ppn_data_barrier_6_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[tlb.scala:81:{49,60}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[tlb.scala:78:28, :81:{20,60}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[tlb.scala:80:31, :124:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[tlb.scala:80:{31,38}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn_0 : 27'h0; // @[tlb.scala:80:38, :81:30, :119:49] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _ppn_data_barrier_6_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[tlb.scala:81:{49,60}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[tlb.scala:81:{20,60}] wire [19:0] _ppn_T_41 = vpn_0[19:0]; // @[tlb.scala:119:49, :174:103] wire [19:0] _ppn_T_42 = hitsVec_0_0 ? _ppn_data_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_0_1 ? _ppn_data_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_0_2 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_0_3 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_0_4 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_0_5 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_0_6 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = _ppn_T_50 | _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = _ppn_T_51 | _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = _ppn_T_52 | _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = _ppn_T_53 | _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T_54 | _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_55 | _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_WIRE = _ppn_T_56; // @[Mux.scala:30:73] wire [19:0] ppn_0 = _ppn_WIRE; // @[Mux.scala:30:73] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_sw; // @[tlb.scala:179:24] wire newEntry_sx; // @[tlb.scala:179:24] wire newEntry_sr; // @[tlb.scala:179:24] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:47] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[PTW.scala:141:{44,47}] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[PTW.scala:141:{38,44}] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[PTW.scala:141:{32,38}] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[PTW.scala:141:{32,52}] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[PTW.scala:141:52, :149:35] assign newEntry_sr = _newEntry_sr_T_5; // @[PTW.scala:149:35] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:47] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[PTW.scala:141:{44,47}] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[PTW.scala:141:{38,44}] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[PTW.scala:141:{32,38}] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[PTW.scala:141:{32,52}] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:52, :151:35] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[PTW.scala:151:{35,40}] assign newEntry_sw = _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[PTW.scala:141:47] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[PTW.scala:141:{44,47}] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[PTW.scala:141:{38,44}] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[PTW.scala:141:{32,38}] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[PTW.scala:141:{32,52}] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[PTW.scala:141:52, :153:35] assign newEntry_sx = _newEntry_sx_T_5; // @[PTW.scala:153:35] wire [1:0] _GEN_21 = {newEntry_eff, newEntry_c}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign special_entry_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_lo_hi = _GEN_21; // @[tlb.scala:95:26] wire [2:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [1:0] _GEN_22 = {newEntry_pal, newEntry_paa}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign special_entry_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_hi_lo = _GEN_22; // @[tlb.scala:95:26] wire [1:0] _GEN_23 = {newEntry_px, newEntry_pr}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign special_entry_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_lo_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_lo_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_lo_hi_hi = _GEN_23; // @[tlb.scala:95:26] wire [3:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[tlb.scala:95:26] wire [1:0] _GEN_24 = {newEntry_sr, newEntry_pw}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign special_entry_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_lo_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_lo_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_lo_lo = _GEN_24; // @[tlb.scala:95:26] wire [1:0] _GEN_25 = {newEntry_sw, newEntry_sx}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign special_entry_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_lo_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_lo_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_lo_hi = _GEN_25; // @[tlb.scala:95:26] wire [3:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [1:0] _GEN_26 = {newEntry_g, newEntry_ae}; // @[tlb.scala:95:26, :179:24] wire [1:0] special_entry_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign special_entry_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_0_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_1_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_2_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] superpage_entries_3_data_0_hi_hi_lo; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] sectored_entries_0_data_hi_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [1:0] sectored_entries_1_data_hi_hi_lo; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_hi_lo = _GEN_26; // @[tlb.scala:95:26] wire [20:0] _GEN_27 = {newEntry_ppn, newEntry_u}; // @[tlb.scala:95:26, :179:24] wire [20:0] special_entry_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign special_entry_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_0_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_0_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_1_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_1_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_2_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_2_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] superpage_entries_3_data_0_hi_hi_hi; // @[tlb.scala:95:26] assign superpage_entries_3_data_0_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] sectored_entries_0_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_0_data_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [20:0] sectored_entries_1_data_hi_hi_hi; // @[tlb.scala:95:26] assign sectored_entries_1_data_hi_hi_hi = _GEN_27; // @[tlb.scala:95:26] wire [22:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[tlb.scala:95:26] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[tlb.scala:95:26] wire [2:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[tlb.scala:95:26] wire [3:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[tlb.scala:95:26] wire waddr = r_sectored_hit ? r_sectored_hit_addr : r_sectored_repl_addr; // @[tlb.scala:132:33, :133:32, :134:27, :203:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_data_lo_lo = {sectored_entries_0_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_0_data_lo_hi = {sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_0_data_lo = {sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_0_data_hi_lo = {sectored_entries_0_data_hi_lo_hi, sectored_entries_0_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_0_data_hi_hi = {sectored_entries_0_data_hi_hi_hi, sectored_entries_0_data_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_0_data_hi = {sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_0_data_T = {sectored_entries_0_data_hi, sectored_entries_0_data_lo}; // @[tlb.scala:95:26] wire [2:0] sectored_entries_1_data_lo_lo = {sectored_entries_1_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_1_data_lo_hi = {sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo}; // @[tlb.scala:95:26] wire [6:0] sectored_entries_1_data_lo = {sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo}; // @[tlb.scala:95:26] wire [3:0] sectored_entries_1_data_hi_lo = {sectored_entries_1_data_hi_lo_hi, sectored_entries_1_data_hi_lo_lo}; // @[tlb.scala:95:26] wire [22:0] sectored_entries_1_data_hi_hi = {sectored_entries_1_data_hi_hi_hi, sectored_entries_1_data_hi_hi_lo}; // @[tlb.scala:95:26] wire [26:0] sectored_entries_1_data_hi = {sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo}; // @[tlb.scala:95:26] wire [33:0] _sectored_entries_1_data_T = {sectored_entries_1_data_hi, sectored_entries_1_data_lo}; // @[tlb.scala:95:26] wire [19:0] _entries_T_15; // @[tlb.scala:58:79] wire _entries_T_14; // @[tlb.scala:58:79] wire _entries_T_13; // @[tlb.scala:58:79] wire _entries_T_12; // @[tlb.scala:58:79] wire _entries_T_11; // @[tlb.scala:58:79] wire _entries_T_10; // @[tlb.scala:58:79] wire _entries_T_9; // @[tlb.scala:58:79] wire _entries_T_8; // @[tlb.scala:58:79] wire _entries_T_7; // @[tlb.scala:58:79] wire _entries_T_6; // @[tlb.scala:58:79] wire _entries_T_5; // @[tlb.scala:58:79] wire _entries_T_4; // @[tlb.scala:58:79] wire _entries_T_3; // @[tlb.scala:58:79] wire _entries_T_2; // @[tlb.scala:58:79] wire _entries_T_1; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_1 = _GEN_19[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[tlb.scala:58:79] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[tlb.scala:58:79] assign _entries_T_2 = _entries_WIRE_1[1]; // @[tlb.scala:58:79] wire _entries_WIRE_c = _entries_T_2; // @[tlb.scala:58:79] assign _entries_T_3 = _entries_WIRE_1[2]; // @[tlb.scala:58:79] wire _entries_WIRE_eff = _entries_T_3; // @[tlb.scala:58:79] assign _entries_T_4 = _entries_WIRE_1[3]; // @[tlb.scala:58:79] wire _entries_WIRE_paa = _entries_T_4; // @[tlb.scala:58:79] assign _entries_T_5 = _entries_WIRE_1[4]; // @[tlb.scala:58:79] wire _entries_WIRE_pal = _entries_T_5; // @[tlb.scala:58:79] assign _entries_T_6 = _entries_WIRE_1[5]; // @[tlb.scala:58:79] wire _entries_WIRE_pr = _entries_T_6; // @[tlb.scala:58:79] assign _entries_T_7 = _entries_WIRE_1[6]; // @[tlb.scala:58:79] wire _entries_WIRE_px = _entries_T_7; // @[tlb.scala:58:79] assign _entries_T_8 = _entries_WIRE_1[7]; // @[tlb.scala:58:79] wire _entries_WIRE_pw = _entries_T_8; // @[tlb.scala:58:79] assign _entries_T_9 = _entries_WIRE_1[8]; // @[tlb.scala:58:79] wire _entries_WIRE_sr = _entries_T_9; // @[tlb.scala:58:79] assign _entries_T_10 = _entries_WIRE_1[9]; // @[tlb.scala:58:79] wire _entries_WIRE_sx = _entries_T_10; // @[tlb.scala:58:79] assign _entries_T_11 = _entries_WIRE_1[10]; // @[tlb.scala:58:79] wire _entries_WIRE_sw = _entries_T_11; // @[tlb.scala:58:79] assign _entries_T_12 = _entries_WIRE_1[11]; // @[tlb.scala:58:79] wire _entries_WIRE_ae = _entries_T_12; // @[tlb.scala:58:79] assign _entries_T_13 = _entries_WIRE_1[12]; // @[tlb.scala:58:79] wire _entries_WIRE_g = _entries_T_13; // @[tlb.scala:58:79] assign _entries_T_14 = _entries_WIRE_1[13]; // @[tlb.scala:58:79] wire _entries_WIRE_u = _entries_T_14; // @[tlb.scala:58:79] assign _entries_T_15 = _entries_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_ppn = _entries_T_15; // @[tlb.scala:58:79] wire [19:0] _entries_T_31; // @[tlb.scala:58:79] wire _entries_T_30; // @[tlb.scala:58:79] wire _entries_T_29; // @[tlb.scala:58:79] wire _entries_T_28; // @[tlb.scala:58:79] wire _entries_T_27; // @[tlb.scala:58:79] wire _entries_T_26; // @[tlb.scala:58:79] wire _entries_T_25; // @[tlb.scala:58:79] wire _entries_T_24; // @[tlb.scala:58:79] wire _entries_T_23; // @[tlb.scala:58:79] wire _entries_T_22; // @[tlb.scala:58:79] wire _entries_T_21; // @[tlb.scala:58:79] wire _entries_T_20; // @[tlb.scala:58:79] wire _entries_T_19; // @[tlb.scala:58:79] wire _entries_T_18; // @[tlb.scala:58:79] wire _entries_T_17; // @[tlb.scala:58:79] wire [33:0] _entries_WIRE_3 = _GEN_20[_entries_T_16]; // @[package.scala:163:13] assign _entries_T_17 = _entries_WIRE_3[0]; // @[tlb.scala:58:79] wire _entries_WIRE_2_fragmented_superpage = _entries_T_17; // @[tlb.scala:58:79] assign _entries_T_18 = _entries_WIRE_3[1]; // @[tlb.scala:58:79] wire _entries_WIRE_2_c = _entries_T_18; // @[tlb.scala:58:79] assign _entries_T_19 = _entries_WIRE_3[2]; // @[tlb.scala:58:79] wire _entries_WIRE_2_eff = _entries_T_19; // @[tlb.scala:58:79] assign _entries_T_20 = _entries_WIRE_3[3]; // @[tlb.scala:58:79] wire _entries_WIRE_2_paa = _entries_T_20; // @[tlb.scala:58:79] assign _entries_T_21 = _entries_WIRE_3[4]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pal = _entries_T_21; // @[tlb.scala:58:79] assign _entries_T_22 = _entries_WIRE_3[5]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pr = _entries_T_22; // @[tlb.scala:58:79] assign _entries_T_23 = _entries_WIRE_3[6]; // @[tlb.scala:58:79] wire _entries_WIRE_2_px = _entries_T_23; // @[tlb.scala:58:79] assign _entries_T_24 = _entries_WIRE_3[7]; // @[tlb.scala:58:79] wire _entries_WIRE_2_pw = _entries_T_24; // @[tlb.scala:58:79] assign _entries_T_25 = _entries_WIRE_3[8]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sr = _entries_T_25; // @[tlb.scala:58:79] assign _entries_T_26 = _entries_WIRE_3[9]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sx = _entries_T_26; // @[tlb.scala:58:79] assign _entries_T_27 = _entries_WIRE_3[10]; // @[tlb.scala:58:79] wire _entries_WIRE_2_sw = _entries_T_27; // @[tlb.scala:58:79] assign _entries_T_28 = _entries_WIRE_3[11]; // @[tlb.scala:58:79] wire _entries_WIRE_2_ae = _entries_T_28; // @[tlb.scala:58:79] assign _entries_T_29 = _entries_WIRE_3[12]; // @[tlb.scala:58:79] wire _entries_WIRE_2_g = _entries_T_29; // @[tlb.scala:58:79] assign _entries_T_30 = _entries_WIRE_3[13]; // @[tlb.scala:58:79] wire _entries_WIRE_2_u = _entries_T_30; // @[tlb.scala:58:79] assign _entries_T_31 = _entries_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_2_ppn = _entries_T_31; // @[tlb.scala:58:79] wire [19:0] _entries_T_46; // @[tlb.scala:58:79] wire _entries_T_45; // @[tlb.scala:58:79] wire _entries_T_44; // @[tlb.scala:58:79] wire _entries_T_43; // @[tlb.scala:58:79] wire _entries_T_42; // @[tlb.scala:58:79] wire _entries_T_41; // @[tlb.scala:58:79] wire _entries_T_40; // @[tlb.scala:58:79] wire _entries_T_39; // @[tlb.scala:58:79] wire _entries_T_38; // @[tlb.scala:58:79] wire _entries_T_37; // @[tlb.scala:58:79] wire _entries_T_36; // @[tlb.scala:58:79] wire _entries_T_35; // @[tlb.scala:58:79] wire _entries_T_34; // @[tlb.scala:58:79] wire _entries_T_33; // @[tlb.scala:58:79] wire _entries_T_32; // @[tlb.scala:58:79] assign _entries_T_32 = _entries_WIRE_5[0]; // @[tlb.scala:58:79] wire _entries_WIRE_4_fragmented_superpage = _entries_T_32; // @[tlb.scala:58:79] assign _entries_T_33 = _entries_WIRE_5[1]; // @[tlb.scala:58:79] wire _entries_WIRE_4_c = _entries_T_33; // @[tlb.scala:58:79] assign _entries_T_34 = _entries_WIRE_5[2]; // @[tlb.scala:58:79] wire _entries_WIRE_4_eff = _entries_T_34; // @[tlb.scala:58:79] assign _entries_T_35 = _entries_WIRE_5[3]; // @[tlb.scala:58:79] wire _entries_WIRE_4_paa = _entries_T_35; // @[tlb.scala:58:79] assign _entries_T_36 = _entries_WIRE_5[4]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pal = _entries_T_36; // @[tlb.scala:58:79] assign _entries_T_37 = _entries_WIRE_5[5]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pr = _entries_T_37; // @[tlb.scala:58:79] assign _entries_T_38 = _entries_WIRE_5[6]; // @[tlb.scala:58:79] wire _entries_WIRE_4_px = _entries_T_38; // @[tlb.scala:58:79] assign _entries_T_39 = _entries_WIRE_5[7]; // @[tlb.scala:58:79] wire _entries_WIRE_4_pw = _entries_T_39; // @[tlb.scala:58:79] assign _entries_T_40 = _entries_WIRE_5[8]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sr = _entries_T_40; // @[tlb.scala:58:79] assign _entries_T_41 = _entries_WIRE_5[9]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sx = _entries_T_41; // @[tlb.scala:58:79] assign _entries_T_42 = _entries_WIRE_5[10]; // @[tlb.scala:58:79] wire _entries_WIRE_4_sw = _entries_T_42; // @[tlb.scala:58:79] assign _entries_T_43 = _entries_WIRE_5[11]; // @[tlb.scala:58:79] wire _entries_WIRE_4_ae = _entries_T_43; // @[tlb.scala:58:79] assign _entries_T_44 = _entries_WIRE_5[12]; // @[tlb.scala:58:79] wire _entries_WIRE_4_g = _entries_T_44; // @[tlb.scala:58:79] assign _entries_T_45 = _entries_WIRE_5[13]; // @[tlb.scala:58:79] wire _entries_WIRE_4_u = _entries_T_45; // @[tlb.scala:58:79] assign _entries_T_46 = _entries_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_4_ppn = _entries_T_46; // @[tlb.scala:58:79] wire [19:0] _entries_T_61; // @[tlb.scala:58:79] wire _entries_T_60; // @[tlb.scala:58:79] wire _entries_T_59; // @[tlb.scala:58:79] wire _entries_T_58; // @[tlb.scala:58:79] wire _entries_T_57; // @[tlb.scala:58:79] wire _entries_T_56; // @[tlb.scala:58:79] wire _entries_T_55; // @[tlb.scala:58:79] wire _entries_T_54; // @[tlb.scala:58:79] wire _entries_T_53; // @[tlb.scala:58:79] wire _entries_T_52; // @[tlb.scala:58:79] wire _entries_T_51; // @[tlb.scala:58:79] wire _entries_T_50; // @[tlb.scala:58:79] wire _entries_T_49; // @[tlb.scala:58:79] wire _entries_T_48; // @[tlb.scala:58:79] wire _entries_T_47; // @[tlb.scala:58:79] assign _entries_T_47 = _entries_WIRE_7[0]; // @[tlb.scala:58:79] wire _entries_WIRE_6_fragmented_superpage = _entries_T_47; // @[tlb.scala:58:79] assign _entries_T_48 = _entries_WIRE_7[1]; // @[tlb.scala:58:79] wire _entries_WIRE_6_c = _entries_T_48; // @[tlb.scala:58:79] assign _entries_T_49 = _entries_WIRE_7[2]; // @[tlb.scala:58:79] wire _entries_WIRE_6_eff = _entries_T_49; // @[tlb.scala:58:79] assign _entries_T_50 = _entries_WIRE_7[3]; // @[tlb.scala:58:79] wire _entries_WIRE_6_paa = _entries_T_50; // @[tlb.scala:58:79] assign _entries_T_51 = _entries_WIRE_7[4]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pal = _entries_T_51; // @[tlb.scala:58:79] assign _entries_T_52 = _entries_WIRE_7[5]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pr = _entries_T_52; // @[tlb.scala:58:79] assign _entries_T_53 = _entries_WIRE_7[6]; // @[tlb.scala:58:79] wire _entries_WIRE_6_px = _entries_T_53; // @[tlb.scala:58:79] assign _entries_T_54 = _entries_WIRE_7[7]; // @[tlb.scala:58:79] wire _entries_WIRE_6_pw = _entries_T_54; // @[tlb.scala:58:79] assign _entries_T_55 = _entries_WIRE_7[8]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sr = _entries_T_55; // @[tlb.scala:58:79] assign _entries_T_56 = _entries_WIRE_7[9]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sx = _entries_T_56; // @[tlb.scala:58:79] assign _entries_T_57 = _entries_WIRE_7[10]; // @[tlb.scala:58:79] wire _entries_WIRE_6_sw = _entries_T_57; // @[tlb.scala:58:79] assign _entries_T_58 = _entries_WIRE_7[11]; // @[tlb.scala:58:79] wire _entries_WIRE_6_ae = _entries_T_58; // @[tlb.scala:58:79] assign _entries_T_59 = _entries_WIRE_7[12]; // @[tlb.scala:58:79] wire _entries_WIRE_6_g = _entries_T_59; // @[tlb.scala:58:79] assign _entries_T_60 = _entries_WIRE_7[13]; // @[tlb.scala:58:79] wire _entries_WIRE_6_u = _entries_T_60; // @[tlb.scala:58:79] assign _entries_T_61 = _entries_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_6_ppn = _entries_T_61; // @[tlb.scala:58:79] wire [19:0] _entries_T_76; // @[tlb.scala:58:79] wire _entries_T_75; // @[tlb.scala:58:79] wire _entries_T_74; // @[tlb.scala:58:79] wire _entries_T_73; // @[tlb.scala:58:79] wire _entries_T_72; // @[tlb.scala:58:79] wire _entries_T_71; // @[tlb.scala:58:79] wire _entries_T_70; // @[tlb.scala:58:79] wire _entries_T_69; // @[tlb.scala:58:79] wire _entries_T_68; // @[tlb.scala:58:79] wire _entries_T_67; // @[tlb.scala:58:79] wire _entries_T_66; // @[tlb.scala:58:79] wire _entries_T_65; // @[tlb.scala:58:79] wire _entries_T_64; // @[tlb.scala:58:79] wire _entries_T_63; // @[tlb.scala:58:79] wire _entries_T_62; // @[tlb.scala:58:79] assign _entries_T_62 = _entries_WIRE_9[0]; // @[tlb.scala:58:79] wire _entries_WIRE_8_fragmented_superpage = _entries_T_62; // @[tlb.scala:58:79] assign _entries_T_63 = _entries_WIRE_9[1]; // @[tlb.scala:58:79] wire _entries_WIRE_8_c = _entries_T_63; // @[tlb.scala:58:79] assign _entries_T_64 = _entries_WIRE_9[2]; // @[tlb.scala:58:79] wire _entries_WIRE_8_eff = _entries_T_64; // @[tlb.scala:58:79] assign _entries_T_65 = _entries_WIRE_9[3]; // @[tlb.scala:58:79] wire _entries_WIRE_8_paa = _entries_T_65; // @[tlb.scala:58:79] assign _entries_T_66 = _entries_WIRE_9[4]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pal = _entries_T_66; // @[tlb.scala:58:79] assign _entries_T_67 = _entries_WIRE_9[5]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pr = _entries_T_67; // @[tlb.scala:58:79] assign _entries_T_68 = _entries_WIRE_9[6]; // @[tlb.scala:58:79] wire _entries_WIRE_8_px = _entries_T_68; // @[tlb.scala:58:79] assign _entries_T_69 = _entries_WIRE_9[7]; // @[tlb.scala:58:79] wire _entries_WIRE_8_pw = _entries_T_69; // @[tlb.scala:58:79] assign _entries_T_70 = _entries_WIRE_9[8]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sr = _entries_T_70; // @[tlb.scala:58:79] assign _entries_T_71 = _entries_WIRE_9[9]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sx = _entries_T_71; // @[tlb.scala:58:79] assign _entries_T_72 = _entries_WIRE_9[10]; // @[tlb.scala:58:79] wire _entries_WIRE_8_sw = _entries_T_72; // @[tlb.scala:58:79] assign _entries_T_73 = _entries_WIRE_9[11]; // @[tlb.scala:58:79] wire _entries_WIRE_8_ae = _entries_T_73; // @[tlb.scala:58:79] assign _entries_T_74 = _entries_WIRE_9[12]; // @[tlb.scala:58:79] wire _entries_WIRE_8_g = _entries_T_74; // @[tlb.scala:58:79] assign _entries_T_75 = _entries_WIRE_9[13]; // @[tlb.scala:58:79] wire _entries_WIRE_8_u = _entries_T_75; // @[tlb.scala:58:79] assign _entries_T_76 = _entries_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_8_ppn = _entries_T_76; // @[tlb.scala:58:79] wire [19:0] _entries_T_91; // @[tlb.scala:58:79] wire _entries_T_90; // @[tlb.scala:58:79] wire _entries_T_89; // @[tlb.scala:58:79] wire _entries_T_88; // @[tlb.scala:58:79] wire _entries_T_87; // @[tlb.scala:58:79] wire _entries_T_86; // @[tlb.scala:58:79] wire _entries_T_85; // @[tlb.scala:58:79] wire _entries_T_84; // @[tlb.scala:58:79] wire _entries_T_83; // @[tlb.scala:58:79] wire _entries_T_82; // @[tlb.scala:58:79] wire _entries_T_81; // @[tlb.scala:58:79] wire _entries_T_80; // @[tlb.scala:58:79] wire _entries_T_79; // @[tlb.scala:58:79] wire _entries_T_78; // @[tlb.scala:58:79] wire _entries_T_77; // @[tlb.scala:58:79] assign _entries_T_77 = _entries_WIRE_11[0]; // @[tlb.scala:58:79] wire _entries_WIRE_10_fragmented_superpage = _entries_T_77; // @[tlb.scala:58:79] assign _entries_T_78 = _entries_WIRE_11[1]; // @[tlb.scala:58:79] wire _entries_WIRE_10_c = _entries_T_78; // @[tlb.scala:58:79] assign _entries_T_79 = _entries_WIRE_11[2]; // @[tlb.scala:58:79] wire _entries_WIRE_10_eff = _entries_T_79; // @[tlb.scala:58:79] assign _entries_T_80 = _entries_WIRE_11[3]; // @[tlb.scala:58:79] wire _entries_WIRE_10_paa = _entries_T_80; // @[tlb.scala:58:79] assign _entries_T_81 = _entries_WIRE_11[4]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pal = _entries_T_81; // @[tlb.scala:58:79] assign _entries_T_82 = _entries_WIRE_11[5]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pr = _entries_T_82; // @[tlb.scala:58:79] assign _entries_T_83 = _entries_WIRE_11[6]; // @[tlb.scala:58:79] wire _entries_WIRE_10_px = _entries_T_83; // @[tlb.scala:58:79] assign _entries_T_84 = _entries_WIRE_11[7]; // @[tlb.scala:58:79] wire _entries_WIRE_10_pw = _entries_T_84; // @[tlb.scala:58:79] assign _entries_T_85 = _entries_WIRE_11[8]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sr = _entries_T_85; // @[tlb.scala:58:79] assign _entries_T_86 = _entries_WIRE_11[9]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sx = _entries_T_86; // @[tlb.scala:58:79] assign _entries_T_87 = _entries_WIRE_11[10]; // @[tlb.scala:58:79] wire _entries_WIRE_10_sw = _entries_T_87; // @[tlb.scala:58:79] assign _entries_T_88 = _entries_WIRE_11[11]; // @[tlb.scala:58:79] wire _entries_WIRE_10_ae = _entries_T_88; // @[tlb.scala:58:79] assign _entries_T_89 = _entries_WIRE_11[12]; // @[tlb.scala:58:79] wire _entries_WIRE_10_g = _entries_T_89; // @[tlb.scala:58:79] assign _entries_T_90 = _entries_WIRE_11[13]; // @[tlb.scala:58:79] wire _entries_WIRE_10_u = _entries_T_90; // @[tlb.scala:58:79] assign _entries_T_91 = _entries_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_10_ppn = _entries_T_91; // @[tlb.scala:58:79] wire [19:0] _entries_T_106; // @[tlb.scala:58:79] wire _entries_T_105; // @[tlb.scala:58:79] wire _entries_T_104; // @[tlb.scala:58:79] wire _entries_T_103; // @[tlb.scala:58:79] wire _entries_T_102; // @[tlb.scala:58:79] wire _entries_T_101; // @[tlb.scala:58:79] wire _entries_T_100; // @[tlb.scala:58:79] wire _entries_T_99; // @[tlb.scala:58:79] wire _entries_T_98; // @[tlb.scala:58:79] wire _entries_T_97; // @[tlb.scala:58:79] wire _entries_T_96; // @[tlb.scala:58:79] wire _entries_T_95; // @[tlb.scala:58:79] wire _entries_T_94; // @[tlb.scala:58:79] wire _entries_T_93; // @[tlb.scala:58:79] wire _entries_T_92; // @[tlb.scala:58:79] assign _entries_T_92 = _entries_WIRE_13[0]; // @[tlb.scala:58:79] wire _entries_WIRE_12_fragmented_superpage = _entries_T_92; // @[tlb.scala:58:79] assign _entries_T_93 = _entries_WIRE_13[1]; // @[tlb.scala:58:79] wire _entries_WIRE_12_c = _entries_T_93; // @[tlb.scala:58:79] assign _entries_T_94 = _entries_WIRE_13[2]; // @[tlb.scala:58:79] wire _entries_WIRE_12_eff = _entries_T_94; // @[tlb.scala:58:79] assign _entries_T_95 = _entries_WIRE_13[3]; // @[tlb.scala:58:79] wire _entries_WIRE_12_paa = _entries_T_95; // @[tlb.scala:58:79] assign _entries_T_96 = _entries_WIRE_13[4]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pal = _entries_T_96; // @[tlb.scala:58:79] assign _entries_T_97 = _entries_WIRE_13[5]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pr = _entries_T_97; // @[tlb.scala:58:79] assign _entries_T_98 = _entries_WIRE_13[6]; // @[tlb.scala:58:79] wire _entries_WIRE_12_px = _entries_T_98; // @[tlb.scala:58:79] assign _entries_T_99 = _entries_WIRE_13[7]; // @[tlb.scala:58:79] wire _entries_WIRE_12_pw = _entries_T_99; // @[tlb.scala:58:79] assign _entries_T_100 = _entries_WIRE_13[8]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sr = _entries_T_100; // @[tlb.scala:58:79] assign _entries_T_101 = _entries_WIRE_13[9]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sx = _entries_T_101; // @[tlb.scala:58:79] assign _entries_T_102 = _entries_WIRE_13[10]; // @[tlb.scala:58:79] wire _entries_WIRE_12_sw = _entries_T_102; // @[tlb.scala:58:79] assign _entries_T_103 = _entries_WIRE_13[11]; // @[tlb.scala:58:79] wire _entries_WIRE_12_ae = _entries_T_103; // @[tlb.scala:58:79] assign _entries_T_104 = _entries_WIRE_13[12]; // @[tlb.scala:58:79] wire _entries_WIRE_12_g = _entries_T_104; // @[tlb.scala:58:79] assign _entries_T_105 = _entries_WIRE_13[13]; // @[tlb.scala:58:79] wire _entries_WIRE_12_u = _entries_T_105; // @[tlb.scala:58:79] assign _entries_T_106 = _entries_WIRE_13[33:14]; // @[tlb.scala:58:79] wire [19:0] _entries_WIRE_12_ppn = _entries_T_106; // @[tlb.scala:58:79] wire [19:0] entries_0_0_ppn = _entries_WIRE_14_0_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_0_u = _entries_WIRE_14_0_u; // @[tlb.scala:119:49, :211:38] wire entries_0_0_g = _entries_WIRE_14_0_g; // @[tlb.scala:119:49, :211:38] wire entries_0_0_ae = _entries_WIRE_14_0_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sw = _entries_WIRE_14_0_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sx = _entries_WIRE_14_0_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_0_sr = _entries_WIRE_14_0_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pw = _entries_WIRE_14_0_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_0_px = _entries_WIRE_14_0_px; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pr = _entries_WIRE_14_0_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_0_pal = _entries_WIRE_14_0_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_0_paa = _entries_WIRE_14_0_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_0_eff = _entries_WIRE_14_0_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_0_c = _entries_WIRE_14_0_c; // @[tlb.scala:119:49, :211:38] wire entries_0_0_fragmented_superpage = _entries_WIRE_14_0_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_1_ppn = _entries_WIRE_14_1_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_1_u = _entries_WIRE_14_1_u; // @[tlb.scala:119:49, :211:38] wire entries_0_1_g = _entries_WIRE_14_1_g; // @[tlb.scala:119:49, :211:38] wire entries_0_1_ae = _entries_WIRE_14_1_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sw = _entries_WIRE_14_1_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sx = _entries_WIRE_14_1_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_1_sr = _entries_WIRE_14_1_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pw = _entries_WIRE_14_1_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_1_px = _entries_WIRE_14_1_px; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pr = _entries_WIRE_14_1_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_1_pal = _entries_WIRE_14_1_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_1_paa = _entries_WIRE_14_1_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_1_eff = _entries_WIRE_14_1_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_1_c = _entries_WIRE_14_1_c; // @[tlb.scala:119:49, :211:38] wire entries_0_1_fragmented_superpage = _entries_WIRE_14_1_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_2_ppn = _entries_WIRE_14_2_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_2_u = _entries_WIRE_14_2_u; // @[tlb.scala:119:49, :211:38] wire entries_0_2_g = _entries_WIRE_14_2_g; // @[tlb.scala:119:49, :211:38] wire entries_0_2_ae = _entries_WIRE_14_2_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sw = _entries_WIRE_14_2_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sx = _entries_WIRE_14_2_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_2_sr = _entries_WIRE_14_2_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pw = _entries_WIRE_14_2_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_2_px = _entries_WIRE_14_2_px; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pr = _entries_WIRE_14_2_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_2_pal = _entries_WIRE_14_2_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_2_paa = _entries_WIRE_14_2_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_2_eff = _entries_WIRE_14_2_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_2_c = _entries_WIRE_14_2_c; // @[tlb.scala:119:49, :211:38] wire entries_0_2_fragmented_superpage = _entries_WIRE_14_2_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_3_ppn = _entries_WIRE_14_3_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_3_u = _entries_WIRE_14_3_u; // @[tlb.scala:119:49, :211:38] wire entries_0_3_g = _entries_WIRE_14_3_g; // @[tlb.scala:119:49, :211:38] wire entries_0_3_ae = _entries_WIRE_14_3_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sw = _entries_WIRE_14_3_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sx = _entries_WIRE_14_3_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_3_sr = _entries_WIRE_14_3_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pw = _entries_WIRE_14_3_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_3_px = _entries_WIRE_14_3_px; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pr = _entries_WIRE_14_3_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_3_pal = _entries_WIRE_14_3_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_3_paa = _entries_WIRE_14_3_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_3_eff = _entries_WIRE_14_3_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_3_c = _entries_WIRE_14_3_c; // @[tlb.scala:119:49, :211:38] wire entries_0_3_fragmented_superpage = _entries_WIRE_14_3_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_4_ppn = _entries_WIRE_14_4_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_4_u = _entries_WIRE_14_4_u; // @[tlb.scala:119:49, :211:38] wire entries_0_4_g = _entries_WIRE_14_4_g; // @[tlb.scala:119:49, :211:38] wire entries_0_4_ae = _entries_WIRE_14_4_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sw = _entries_WIRE_14_4_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sx = _entries_WIRE_14_4_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_4_sr = _entries_WIRE_14_4_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pw = _entries_WIRE_14_4_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_4_px = _entries_WIRE_14_4_px; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pr = _entries_WIRE_14_4_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_4_pal = _entries_WIRE_14_4_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_4_paa = _entries_WIRE_14_4_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_4_eff = _entries_WIRE_14_4_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_4_c = _entries_WIRE_14_4_c; // @[tlb.scala:119:49, :211:38] wire entries_0_4_fragmented_superpage = _entries_WIRE_14_4_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_5_ppn = _entries_WIRE_14_5_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_5_u = _entries_WIRE_14_5_u; // @[tlb.scala:119:49, :211:38] wire entries_0_5_g = _entries_WIRE_14_5_g; // @[tlb.scala:119:49, :211:38] wire entries_0_5_ae = _entries_WIRE_14_5_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sw = _entries_WIRE_14_5_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sx = _entries_WIRE_14_5_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_5_sr = _entries_WIRE_14_5_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pw = _entries_WIRE_14_5_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_5_px = _entries_WIRE_14_5_px; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pr = _entries_WIRE_14_5_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_5_pal = _entries_WIRE_14_5_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_5_paa = _entries_WIRE_14_5_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_5_eff = _entries_WIRE_14_5_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_5_c = _entries_WIRE_14_5_c; // @[tlb.scala:119:49, :211:38] wire entries_0_5_fragmented_superpage = _entries_WIRE_14_5_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] entries_0_6_ppn = _entries_WIRE_14_6_ppn; // @[tlb.scala:119:49, :211:38] wire entries_0_6_u = _entries_WIRE_14_6_u; // @[tlb.scala:119:49, :211:38] wire entries_0_6_g = _entries_WIRE_14_6_g; // @[tlb.scala:119:49, :211:38] wire entries_0_6_ae = _entries_WIRE_14_6_ae; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sw = _entries_WIRE_14_6_sw; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sx = _entries_WIRE_14_6_sx; // @[tlb.scala:119:49, :211:38] wire entries_0_6_sr = _entries_WIRE_14_6_sr; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pw = _entries_WIRE_14_6_pw; // @[tlb.scala:119:49, :211:38] wire entries_0_6_px = _entries_WIRE_14_6_px; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pr = _entries_WIRE_14_6_pr; // @[tlb.scala:119:49, :211:38] wire entries_0_6_pal = _entries_WIRE_14_6_pal; // @[tlb.scala:119:49, :211:38] wire entries_0_6_paa = _entries_WIRE_14_6_paa; // @[tlb.scala:119:49, :211:38] wire entries_0_6_eff = _entries_WIRE_14_6_eff; // @[tlb.scala:119:49, :211:38] wire entries_0_6_c = _entries_WIRE_14_6_c; // @[tlb.scala:119:49, :211:38] wire entries_0_6_fragmented_superpage = _entries_WIRE_14_6_fragmented_superpage; // @[tlb.scala:119:49, :211:38] wire [19:0] _normal_entries_T_15; // @[tlb.scala:58:79] wire _normal_entries_T_14; // @[tlb.scala:58:79] wire _normal_entries_T_13; // @[tlb.scala:58:79] wire _normal_entries_T_12; // @[tlb.scala:58:79] wire _normal_entries_T_11; // @[tlb.scala:58:79] wire _normal_entries_T_10; // @[tlb.scala:58:79] wire _normal_entries_T_9; // @[tlb.scala:58:79] wire _normal_entries_T_8; // @[tlb.scala:58:79] wire _normal_entries_T_7; // @[tlb.scala:58:79] wire _normal_entries_T_6; // @[tlb.scala:58:79] wire _normal_entries_T_5; // @[tlb.scala:58:79] wire _normal_entries_T_4; // @[tlb.scala:58:79] wire _normal_entries_T_3; // @[tlb.scala:58:79] wire _normal_entries_T_2; // @[tlb.scala:58:79] wire _normal_entries_T_1; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_1 = _GEN_19[_normal_entries_T]; // @[package.scala:163:13] assign _normal_entries_T_1 = _normal_entries_WIRE_1[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_fragmented_superpage = _normal_entries_T_1; // @[tlb.scala:58:79] assign _normal_entries_T_2 = _normal_entries_WIRE_1[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_c = _normal_entries_T_2; // @[tlb.scala:58:79] assign _normal_entries_T_3 = _normal_entries_WIRE_1[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_eff = _normal_entries_T_3; // @[tlb.scala:58:79] assign _normal_entries_T_4 = _normal_entries_WIRE_1[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_paa = _normal_entries_T_4; // @[tlb.scala:58:79] assign _normal_entries_T_5 = _normal_entries_WIRE_1[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pal = _normal_entries_T_5; // @[tlb.scala:58:79] assign _normal_entries_T_6 = _normal_entries_WIRE_1[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pr = _normal_entries_T_6; // @[tlb.scala:58:79] assign _normal_entries_T_7 = _normal_entries_WIRE_1[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_px = _normal_entries_T_7; // @[tlb.scala:58:79] assign _normal_entries_T_8 = _normal_entries_WIRE_1[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_pw = _normal_entries_T_8; // @[tlb.scala:58:79] assign _normal_entries_T_9 = _normal_entries_WIRE_1[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sr = _normal_entries_T_9; // @[tlb.scala:58:79] assign _normal_entries_T_10 = _normal_entries_WIRE_1[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sx = _normal_entries_T_10; // @[tlb.scala:58:79] assign _normal_entries_T_11 = _normal_entries_WIRE_1[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_sw = _normal_entries_T_11; // @[tlb.scala:58:79] assign _normal_entries_T_12 = _normal_entries_WIRE_1[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_ae = _normal_entries_T_12; // @[tlb.scala:58:79] assign _normal_entries_T_13 = _normal_entries_WIRE_1[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_g = _normal_entries_T_13; // @[tlb.scala:58:79] assign _normal_entries_T_14 = _normal_entries_WIRE_1[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_u = _normal_entries_T_14; // @[tlb.scala:58:79] assign _normal_entries_T_15 = _normal_entries_WIRE_1[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_ppn = _normal_entries_T_15; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_31; // @[tlb.scala:58:79] wire _normal_entries_T_30; // @[tlb.scala:58:79] wire _normal_entries_T_29; // @[tlb.scala:58:79] wire _normal_entries_T_28; // @[tlb.scala:58:79] wire _normal_entries_T_27; // @[tlb.scala:58:79] wire _normal_entries_T_26; // @[tlb.scala:58:79] wire _normal_entries_T_25; // @[tlb.scala:58:79] wire _normal_entries_T_24; // @[tlb.scala:58:79] wire _normal_entries_T_23; // @[tlb.scala:58:79] wire _normal_entries_T_22; // @[tlb.scala:58:79] wire _normal_entries_T_21; // @[tlb.scala:58:79] wire _normal_entries_T_20; // @[tlb.scala:58:79] wire _normal_entries_T_19; // @[tlb.scala:58:79] wire _normal_entries_T_18; // @[tlb.scala:58:79] wire _normal_entries_T_17; // @[tlb.scala:58:79] wire [33:0] _normal_entries_WIRE_3 = _GEN_20[_normal_entries_T_16]; // @[package.scala:163:13] assign _normal_entries_T_17 = _normal_entries_WIRE_3[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_fragmented_superpage = _normal_entries_T_17; // @[tlb.scala:58:79] assign _normal_entries_T_18 = _normal_entries_WIRE_3[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_c = _normal_entries_T_18; // @[tlb.scala:58:79] assign _normal_entries_T_19 = _normal_entries_WIRE_3[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_eff = _normal_entries_T_19; // @[tlb.scala:58:79] assign _normal_entries_T_20 = _normal_entries_WIRE_3[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_paa = _normal_entries_T_20; // @[tlb.scala:58:79] assign _normal_entries_T_21 = _normal_entries_WIRE_3[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pal = _normal_entries_T_21; // @[tlb.scala:58:79] assign _normal_entries_T_22 = _normal_entries_WIRE_3[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pr = _normal_entries_T_22; // @[tlb.scala:58:79] assign _normal_entries_T_23 = _normal_entries_WIRE_3[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_px = _normal_entries_T_23; // @[tlb.scala:58:79] assign _normal_entries_T_24 = _normal_entries_WIRE_3[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_pw = _normal_entries_T_24; // @[tlb.scala:58:79] assign _normal_entries_T_25 = _normal_entries_WIRE_3[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sr = _normal_entries_T_25; // @[tlb.scala:58:79] assign _normal_entries_T_26 = _normal_entries_WIRE_3[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sx = _normal_entries_T_26; // @[tlb.scala:58:79] assign _normal_entries_T_27 = _normal_entries_WIRE_3[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_sw = _normal_entries_T_27; // @[tlb.scala:58:79] assign _normal_entries_T_28 = _normal_entries_WIRE_3[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_ae = _normal_entries_T_28; // @[tlb.scala:58:79] assign _normal_entries_T_29 = _normal_entries_WIRE_3[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_g = _normal_entries_T_29; // @[tlb.scala:58:79] assign _normal_entries_T_30 = _normal_entries_WIRE_3[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_2_u = _normal_entries_T_30; // @[tlb.scala:58:79] assign _normal_entries_T_31 = _normal_entries_WIRE_3[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_2_ppn = _normal_entries_T_31; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_46; // @[tlb.scala:58:79] wire _normal_entries_T_45; // @[tlb.scala:58:79] wire _normal_entries_T_44; // @[tlb.scala:58:79] wire _normal_entries_T_43; // @[tlb.scala:58:79] wire _normal_entries_T_42; // @[tlb.scala:58:79] wire _normal_entries_T_41; // @[tlb.scala:58:79] wire _normal_entries_T_40; // @[tlb.scala:58:79] wire _normal_entries_T_39; // @[tlb.scala:58:79] wire _normal_entries_T_38; // @[tlb.scala:58:79] wire _normal_entries_T_37; // @[tlb.scala:58:79] wire _normal_entries_T_36; // @[tlb.scala:58:79] wire _normal_entries_T_35; // @[tlb.scala:58:79] wire _normal_entries_T_34; // @[tlb.scala:58:79] wire _normal_entries_T_33; // @[tlb.scala:58:79] wire _normal_entries_T_32; // @[tlb.scala:58:79] assign _normal_entries_T_32 = _normal_entries_WIRE_5[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_fragmented_superpage = _normal_entries_T_32; // @[tlb.scala:58:79] assign _normal_entries_T_33 = _normal_entries_WIRE_5[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_c = _normal_entries_T_33; // @[tlb.scala:58:79] assign _normal_entries_T_34 = _normal_entries_WIRE_5[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_eff = _normal_entries_T_34; // @[tlb.scala:58:79] assign _normal_entries_T_35 = _normal_entries_WIRE_5[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_paa = _normal_entries_T_35; // @[tlb.scala:58:79] assign _normal_entries_T_36 = _normal_entries_WIRE_5[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pal = _normal_entries_T_36; // @[tlb.scala:58:79] assign _normal_entries_T_37 = _normal_entries_WIRE_5[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pr = _normal_entries_T_37; // @[tlb.scala:58:79] assign _normal_entries_T_38 = _normal_entries_WIRE_5[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_px = _normal_entries_T_38; // @[tlb.scala:58:79] assign _normal_entries_T_39 = _normal_entries_WIRE_5[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_pw = _normal_entries_T_39; // @[tlb.scala:58:79] assign _normal_entries_T_40 = _normal_entries_WIRE_5[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sr = _normal_entries_T_40; // @[tlb.scala:58:79] assign _normal_entries_T_41 = _normal_entries_WIRE_5[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sx = _normal_entries_T_41; // @[tlb.scala:58:79] assign _normal_entries_T_42 = _normal_entries_WIRE_5[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_sw = _normal_entries_T_42; // @[tlb.scala:58:79] assign _normal_entries_T_43 = _normal_entries_WIRE_5[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_ae = _normal_entries_T_43; // @[tlb.scala:58:79] assign _normal_entries_T_44 = _normal_entries_WIRE_5[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_g = _normal_entries_T_44; // @[tlb.scala:58:79] assign _normal_entries_T_45 = _normal_entries_WIRE_5[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_4_u = _normal_entries_T_45; // @[tlb.scala:58:79] assign _normal_entries_T_46 = _normal_entries_WIRE_5[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_4_ppn = _normal_entries_T_46; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_61; // @[tlb.scala:58:79] wire _normal_entries_T_60; // @[tlb.scala:58:79] wire _normal_entries_T_59; // @[tlb.scala:58:79] wire _normal_entries_T_58; // @[tlb.scala:58:79] wire _normal_entries_T_57; // @[tlb.scala:58:79] wire _normal_entries_T_56; // @[tlb.scala:58:79] wire _normal_entries_T_55; // @[tlb.scala:58:79] wire _normal_entries_T_54; // @[tlb.scala:58:79] wire _normal_entries_T_53; // @[tlb.scala:58:79] wire _normal_entries_T_52; // @[tlb.scala:58:79] wire _normal_entries_T_51; // @[tlb.scala:58:79] wire _normal_entries_T_50; // @[tlb.scala:58:79] wire _normal_entries_T_49; // @[tlb.scala:58:79] wire _normal_entries_T_48; // @[tlb.scala:58:79] wire _normal_entries_T_47; // @[tlb.scala:58:79] assign _normal_entries_T_47 = _normal_entries_WIRE_7[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_fragmented_superpage = _normal_entries_T_47; // @[tlb.scala:58:79] assign _normal_entries_T_48 = _normal_entries_WIRE_7[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_c = _normal_entries_T_48; // @[tlb.scala:58:79] assign _normal_entries_T_49 = _normal_entries_WIRE_7[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_eff = _normal_entries_T_49; // @[tlb.scala:58:79] assign _normal_entries_T_50 = _normal_entries_WIRE_7[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_paa = _normal_entries_T_50; // @[tlb.scala:58:79] assign _normal_entries_T_51 = _normal_entries_WIRE_7[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pal = _normal_entries_T_51; // @[tlb.scala:58:79] assign _normal_entries_T_52 = _normal_entries_WIRE_7[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pr = _normal_entries_T_52; // @[tlb.scala:58:79] assign _normal_entries_T_53 = _normal_entries_WIRE_7[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_px = _normal_entries_T_53; // @[tlb.scala:58:79] assign _normal_entries_T_54 = _normal_entries_WIRE_7[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_pw = _normal_entries_T_54; // @[tlb.scala:58:79] assign _normal_entries_T_55 = _normal_entries_WIRE_7[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sr = _normal_entries_T_55; // @[tlb.scala:58:79] assign _normal_entries_T_56 = _normal_entries_WIRE_7[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sx = _normal_entries_T_56; // @[tlb.scala:58:79] assign _normal_entries_T_57 = _normal_entries_WIRE_7[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_sw = _normal_entries_T_57; // @[tlb.scala:58:79] assign _normal_entries_T_58 = _normal_entries_WIRE_7[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_ae = _normal_entries_T_58; // @[tlb.scala:58:79] assign _normal_entries_T_59 = _normal_entries_WIRE_7[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_g = _normal_entries_T_59; // @[tlb.scala:58:79] assign _normal_entries_T_60 = _normal_entries_WIRE_7[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_6_u = _normal_entries_T_60; // @[tlb.scala:58:79] assign _normal_entries_T_61 = _normal_entries_WIRE_7[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_6_ppn = _normal_entries_T_61; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_76; // @[tlb.scala:58:79] wire _normal_entries_T_75; // @[tlb.scala:58:79] wire _normal_entries_T_74; // @[tlb.scala:58:79] wire _normal_entries_T_73; // @[tlb.scala:58:79] wire _normal_entries_T_72; // @[tlb.scala:58:79] wire _normal_entries_T_71; // @[tlb.scala:58:79] wire _normal_entries_T_70; // @[tlb.scala:58:79] wire _normal_entries_T_69; // @[tlb.scala:58:79] wire _normal_entries_T_68; // @[tlb.scala:58:79] wire _normal_entries_T_67; // @[tlb.scala:58:79] wire _normal_entries_T_66; // @[tlb.scala:58:79] wire _normal_entries_T_65; // @[tlb.scala:58:79] wire _normal_entries_T_64; // @[tlb.scala:58:79] wire _normal_entries_T_63; // @[tlb.scala:58:79] wire _normal_entries_T_62; // @[tlb.scala:58:79] assign _normal_entries_T_62 = _normal_entries_WIRE_9[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_fragmented_superpage = _normal_entries_T_62; // @[tlb.scala:58:79] assign _normal_entries_T_63 = _normal_entries_WIRE_9[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_c = _normal_entries_T_63; // @[tlb.scala:58:79] assign _normal_entries_T_64 = _normal_entries_WIRE_9[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_eff = _normal_entries_T_64; // @[tlb.scala:58:79] assign _normal_entries_T_65 = _normal_entries_WIRE_9[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_paa = _normal_entries_T_65; // @[tlb.scala:58:79] assign _normal_entries_T_66 = _normal_entries_WIRE_9[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pal = _normal_entries_T_66; // @[tlb.scala:58:79] assign _normal_entries_T_67 = _normal_entries_WIRE_9[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pr = _normal_entries_T_67; // @[tlb.scala:58:79] assign _normal_entries_T_68 = _normal_entries_WIRE_9[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_px = _normal_entries_T_68; // @[tlb.scala:58:79] assign _normal_entries_T_69 = _normal_entries_WIRE_9[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_pw = _normal_entries_T_69; // @[tlb.scala:58:79] assign _normal_entries_T_70 = _normal_entries_WIRE_9[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sr = _normal_entries_T_70; // @[tlb.scala:58:79] assign _normal_entries_T_71 = _normal_entries_WIRE_9[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sx = _normal_entries_T_71; // @[tlb.scala:58:79] assign _normal_entries_T_72 = _normal_entries_WIRE_9[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_sw = _normal_entries_T_72; // @[tlb.scala:58:79] assign _normal_entries_T_73 = _normal_entries_WIRE_9[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_ae = _normal_entries_T_73; // @[tlb.scala:58:79] assign _normal_entries_T_74 = _normal_entries_WIRE_9[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_g = _normal_entries_T_74; // @[tlb.scala:58:79] assign _normal_entries_T_75 = _normal_entries_WIRE_9[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_8_u = _normal_entries_T_75; // @[tlb.scala:58:79] assign _normal_entries_T_76 = _normal_entries_WIRE_9[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_8_ppn = _normal_entries_T_76; // @[tlb.scala:58:79] wire [19:0] _normal_entries_T_91; // @[tlb.scala:58:79] wire _normal_entries_T_90; // @[tlb.scala:58:79] wire _normal_entries_T_89; // @[tlb.scala:58:79] wire _normal_entries_T_88; // @[tlb.scala:58:79] wire _normal_entries_T_87; // @[tlb.scala:58:79] wire _normal_entries_T_86; // @[tlb.scala:58:79] wire _normal_entries_T_85; // @[tlb.scala:58:79] wire _normal_entries_T_84; // @[tlb.scala:58:79] wire _normal_entries_T_83; // @[tlb.scala:58:79] wire _normal_entries_T_82; // @[tlb.scala:58:79] wire _normal_entries_T_81; // @[tlb.scala:58:79] wire _normal_entries_T_80; // @[tlb.scala:58:79] wire _normal_entries_T_79; // @[tlb.scala:58:79] wire _normal_entries_T_78; // @[tlb.scala:58:79] wire _normal_entries_T_77; // @[tlb.scala:58:79] assign _normal_entries_T_77 = _normal_entries_WIRE_11[0]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_fragmented_superpage = _normal_entries_T_77; // @[tlb.scala:58:79] assign _normal_entries_T_78 = _normal_entries_WIRE_11[1]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_c = _normal_entries_T_78; // @[tlb.scala:58:79] assign _normal_entries_T_79 = _normal_entries_WIRE_11[2]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_eff = _normal_entries_T_79; // @[tlb.scala:58:79] assign _normal_entries_T_80 = _normal_entries_WIRE_11[3]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_paa = _normal_entries_T_80; // @[tlb.scala:58:79] assign _normal_entries_T_81 = _normal_entries_WIRE_11[4]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pal = _normal_entries_T_81; // @[tlb.scala:58:79] assign _normal_entries_T_82 = _normal_entries_WIRE_11[5]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pr = _normal_entries_T_82; // @[tlb.scala:58:79] assign _normal_entries_T_83 = _normal_entries_WIRE_11[6]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_px = _normal_entries_T_83; // @[tlb.scala:58:79] assign _normal_entries_T_84 = _normal_entries_WIRE_11[7]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_pw = _normal_entries_T_84; // @[tlb.scala:58:79] assign _normal_entries_T_85 = _normal_entries_WIRE_11[8]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sr = _normal_entries_T_85; // @[tlb.scala:58:79] assign _normal_entries_T_86 = _normal_entries_WIRE_11[9]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sx = _normal_entries_T_86; // @[tlb.scala:58:79] assign _normal_entries_T_87 = _normal_entries_WIRE_11[10]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_sw = _normal_entries_T_87; // @[tlb.scala:58:79] assign _normal_entries_T_88 = _normal_entries_WIRE_11[11]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_ae = _normal_entries_T_88; // @[tlb.scala:58:79] assign _normal_entries_T_89 = _normal_entries_WIRE_11[12]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_g = _normal_entries_T_89; // @[tlb.scala:58:79] assign _normal_entries_T_90 = _normal_entries_WIRE_11[13]; // @[tlb.scala:58:79] wire _normal_entries_WIRE_10_u = _normal_entries_T_90; // @[tlb.scala:58:79] assign _normal_entries_T_91 = _normal_entries_WIRE_11[33:14]; // @[tlb.scala:58:79] wire [19:0] _normal_entries_WIRE_10_ppn = _normal_entries_T_91; // @[tlb.scala:58:79] wire [19:0] normal_entries_0_0_ppn = _normal_entries_WIRE_12_0_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_u = _normal_entries_WIRE_12_0_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_g = _normal_entries_WIRE_12_0_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_ae = _normal_entries_WIRE_12_0_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sw = _normal_entries_WIRE_12_0_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sx = _normal_entries_WIRE_12_0_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_sr = _normal_entries_WIRE_12_0_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pw = _normal_entries_WIRE_12_0_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_px = _normal_entries_WIRE_12_0_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pr = _normal_entries_WIRE_12_0_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_pal = _normal_entries_WIRE_12_0_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_paa = _normal_entries_WIRE_12_0_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_eff = _normal_entries_WIRE_12_0_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_c = _normal_entries_WIRE_12_0_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_0_fragmented_superpage = _normal_entries_WIRE_12_0_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_1_ppn = _normal_entries_WIRE_12_1_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_u = _normal_entries_WIRE_12_1_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_g = _normal_entries_WIRE_12_1_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_ae = _normal_entries_WIRE_12_1_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sw = _normal_entries_WIRE_12_1_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sx = _normal_entries_WIRE_12_1_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_sr = _normal_entries_WIRE_12_1_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pw = _normal_entries_WIRE_12_1_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_px = _normal_entries_WIRE_12_1_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pr = _normal_entries_WIRE_12_1_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_pal = _normal_entries_WIRE_12_1_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_paa = _normal_entries_WIRE_12_1_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_eff = _normal_entries_WIRE_12_1_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_c = _normal_entries_WIRE_12_1_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_1_fragmented_superpage = _normal_entries_WIRE_12_1_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_2_ppn = _normal_entries_WIRE_12_2_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_u = _normal_entries_WIRE_12_2_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_g = _normal_entries_WIRE_12_2_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_ae = _normal_entries_WIRE_12_2_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sw = _normal_entries_WIRE_12_2_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sx = _normal_entries_WIRE_12_2_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_sr = _normal_entries_WIRE_12_2_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pw = _normal_entries_WIRE_12_2_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_px = _normal_entries_WIRE_12_2_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pr = _normal_entries_WIRE_12_2_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_pal = _normal_entries_WIRE_12_2_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_paa = _normal_entries_WIRE_12_2_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_eff = _normal_entries_WIRE_12_2_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_c = _normal_entries_WIRE_12_2_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_2_fragmented_superpage = _normal_entries_WIRE_12_2_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_3_ppn = _normal_entries_WIRE_12_3_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_u = _normal_entries_WIRE_12_3_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_g = _normal_entries_WIRE_12_3_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_ae = _normal_entries_WIRE_12_3_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sw = _normal_entries_WIRE_12_3_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sx = _normal_entries_WIRE_12_3_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_sr = _normal_entries_WIRE_12_3_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pw = _normal_entries_WIRE_12_3_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_px = _normal_entries_WIRE_12_3_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pr = _normal_entries_WIRE_12_3_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_pal = _normal_entries_WIRE_12_3_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_paa = _normal_entries_WIRE_12_3_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_eff = _normal_entries_WIRE_12_3_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_c = _normal_entries_WIRE_12_3_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_3_fragmented_superpage = _normal_entries_WIRE_12_3_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_4_ppn = _normal_entries_WIRE_12_4_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_u = _normal_entries_WIRE_12_4_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_g = _normal_entries_WIRE_12_4_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_ae = _normal_entries_WIRE_12_4_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sw = _normal_entries_WIRE_12_4_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sx = _normal_entries_WIRE_12_4_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_sr = _normal_entries_WIRE_12_4_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pw = _normal_entries_WIRE_12_4_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_px = _normal_entries_WIRE_12_4_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pr = _normal_entries_WIRE_12_4_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_pal = _normal_entries_WIRE_12_4_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_paa = _normal_entries_WIRE_12_4_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_eff = _normal_entries_WIRE_12_4_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_c = _normal_entries_WIRE_12_4_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_4_fragmented_superpage = _normal_entries_WIRE_12_4_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [19:0] normal_entries_0_5_ppn = _normal_entries_WIRE_12_5_ppn; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_u = _normal_entries_WIRE_12_5_u; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_g = _normal_entries_WIRE_12_5_g; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_ae = _normal_entries_WIRE_12_5_ae; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sw = _normal_entries_WIRE_12_5_sw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sx = _normal_entries_WIRE_12_5_sx; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_sr = _normal_entries_WIRE_12_5_sr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pw = _normal_entries_WIRE_12_5_pw; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_px = _normal_entries_WIRE_12_5_px; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pr = _normal_entries_WIRE_12_5_pr; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_pal = _normal_entries_WIRE_12_5_pal; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_paa = _normal_entries_WIRE_12_5_paa; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_eff = _normal_entries_WIRE_12_5_eff; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_c = _normal_entries_WIRE_12_5_c; // @[tlb.scala:119:49, :212:45] wire normal_entries_0_5_fragmented_superpage = _normal_entries_WIRE_12_5_fragmented_superpage; // @[tlb.scala:119:49, :212:45] wire [1:0] ptw_ae_array_lo_hi = {entries_0_2_ae, entries_0_1_ae}; // @[package.scala:45:27] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, entries_0_0_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo = {entries_0_4_ae, entries_0_3_ae}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_hi = {entries_0_6_ae, entries_0_5_ae}; // @[package.scala:45:27] wire [3:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [7:0] _ptw_ae_array_T_1 = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [7:0] ptw_ae_array_0 = _ptw_ae_array_T_1; // @[tlb.scala:119:49, :214:39] wire _priv_rw_ok_T = ~priv_s; // @[tlb.scala:137:20, :215:40] wire _priv_rw_ok_T_1 = _priv_rw_ok_T | io_ptw_status_sum_0; // @[tlb.scala:17:7, :215:{40,48}] wire [1:0] _GEN_28 = {entries_0_2_u, entries_0_1_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_28; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_28; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_28; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_28; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [1:0] _GEN_29 = {entries_0_4_u, entries_0_3_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_lo = _GEN_29; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_1 = _GEN_29; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_lo = _GEN_29; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_1 = _GEN_29; // @[package.scala:45:27] wire [1:0] _GEN_30 = {entries_0_6_u, entries_0_5_u}; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_30; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_30; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_30; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_30; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 7'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [6:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 7'h0; // @[tlb.scala:137:20, :215:{108,117}] wire [6:0] _priv_rw_ok_T_7 = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[tlb.scala:215:{39,103,108}] wire [6:0] priv_rw_ok_0 = _priv_rw_ok_T_7; // @[tlb.scala:119:49, :215:103] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, entries_0_0_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27] wire [3:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [6:0] _priv_x_ok_T_3 = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire [6:0] priv_x_ok_0 = _priv_x_ok_T_3; // @[tlb.scala:119:49, :216:39] wire [1:0] r_array_lo_hi = {entries_0_2_sr, entries_0_1_sr}; // @[package.scala:45:27] wire [2:0] r_array_lo = {r_array_lo_hi, entries_0_0_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo = {entries_0_4_sr, entries_0_3_sr}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi = {entries_0_6_sr, entries_0_5_sr}; // @[package.scala:45:27] wire [3:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_31 = {entries_0_2_sx, entries_0_1_sx}; // @[package.scala:45:27] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_31; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_31; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, entries_0_0_sx}; // @[package.scala:45:27] wire [1:0] _GEN_32 = {entries_0_4_sx, entries_0_3_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_lo_1 = _GEN_32; // @[package.scala:45:27] wire [1:0] x_array_hi_lo; // @[package.scala:45:27] assign x_array_hi_lo = _GEN_32; // @[package.scala:45:27] wire [1:0] _GEN_33 = {entries_0_6_sx, entries_0_5_sx}; // @[package.scala:45:27] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_33; // @[package.scala:45:27] wire [3:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [6:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [6:0] _r_array_T_2 = io_ptw_status_mxr_0 ? _r_array_T_1 : 7'h0; // @[package.scala:45:27] wire [6:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [6:0] _r_array_T_4 = priv_rw_ok_0 & _r_array_T_3; // @[tlb.scala:119:49, :217:{62,93}] wire [7:0] _r_array_T_5 = {1'h1, _r_array_T_4}; // @[tlb.scala:217:{39,62}] wire [7:0] r_array_0 = _r_array_T_5; // @[tlb.scala:119:49, :217:39] wire [1:0] w_array_lo_hi = {entries_0_2_sw, entries_0_1_sw}; // @[package.scala:45:27] wire [2:0] w_array_lo = {w_array_lo_hi, entries_0_0_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo = {entries_0_4_sw, entries_0_3_sw}; // @[package.scala:45:27] wire [1:0] w_array_hi_hi = {entries_0_6_sw, entries_0_5_sw}; // @[package.scala:45:27] wire [3:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [6:0] _w_array_T_1 = priv_rw_ok_0 & _w_array_T; // @[package.scala:45:27] wire [7:0] _w_array_T_2 = {1'h1, _w_array_T_1}; // @[tlb.scala:218:{39,62}] wire [7:0] w_array_0 = _w_array_T_2; // @[tlb.scala:119:49, :218:39] wire [2:0] x_array_lo = {x_array_lo_hi, entries_0_0_sx}; // @[package.scala:45:27] wire [3:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [6:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [6:0] _x_array_T_1 = priv_x_ok_0 & _x_array_T; // @[package.scala:45:27] wire [7:0] _x_array_T_2 = {1'h1, _x_array_T_1}; // @[tlb.scala:219:{39,62}] wire [7:0] x_array_0 = _x_array_T_2; // @[tlb.scala:119:49, :219:39] wire [1:0] _pr_array_T = {2{prot_r_0}}; // @[tlb.scala:119:49, :220:44] wire [1:0] pr_array_lo_hi = {normal_entries_0_2_pr, normal_entries_0_1_pr}; // @[package.scala:45:27] wire [2:0] pr_array_lo = {pr_array_lo_hi, normal_entries_0_0_pr}; // @[package.scala:45:27] wire [1:0] pr_array_hi_hi = {normal_entries_0_5_pr, normal_entries_0_4_pr}; // @[package.scala:45:27] wire [2:0] pr_array_hi = {pr_array_hi_hi, normal_entries_0_3_pr}; // @[package.scala:45:27] wire [5:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [7:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [7:0] _pr_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116] wire [7:0] _pr_array_T_4 = _pr_array_T_2 & _pr_array_T_3; // @[tlb.scala:220:{39,114,116}] wire [7:0] pr_array_0 = _pr_array_T_4; // @[tlb.scala:119:49, :220:114] wire [1:0] _pw_array_T = {2{prot_w_0}}; // @[tlb.scala:119:49, :221:44] wire [1:0] pw_array_lo_hi = {normal_entries_0_2_pw, normal_entries_0_1_pw}; // @[package.scala:45:27] wire [2:0] pw_array_lo = {pw_array_lo_hi, normal_entries_0_0_pw}; // @[package.scala:45:27] wire [1:0] pw_array_hi_hi = {normal_entries_0_5_pw, normal_entries_0_4_pw}; // @[package.scala:45:27] wire [2:0] pw_array_hi = {pw_array_hi_hi, normal_entries_0_3_pw}; // @[package.scala:45:27] wire [5:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [7:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [7:0] _pw_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :221:116] wire [7:0] _pw_array_T_4 = _pw_array_T_2 & _pw_array_T_3; // @[tlb.scala:221:{39,114,116}] wire [7:0] pw_array_0 = _pw_array_T_4; // @[tlb.scala:119:49, :221:114] wire [1:0] _px_array_T = {2{prot_x_0}}; // @[tlb.scala:119:49, :222:44] wire [1:0] px_array_lo_hi = {normal_entries_0_2_px, normal_entries_0_1_px}; // @[package.scala:45:27] wire [2:0] px_array_lo = {px_array_lo_hi, normal_entries_0_0_px}; // @[package.scala:45:27] wire [1:0] px_array_hi_hi = {normal_entries_0_5_px, normal_entries_0_4_px}; // @[package.scala:45:27] wire [2:0] px_array_hi = {px_array_hi_hi, normal_entries_0_3_px}; // @[package.scala:45:27] wire [5:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [7:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [7:0] _px_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :222:116] wire [7:0] _px_array_T_4 = _px_array_T_2 & _px_array_T_3; // @[tlb.scala:222:{39,114,116}] wire [7:0] px_array_0 = _px_array_T_4; // @[tlb.scala:119:49, :222:114] wire [1:0] _eff_array_T = {2{prot_eff_0}}; // @[tlb.scala:119:49, :223:44] wire [1:0] eff_array_lo_hi = {normal_entries_0_2_eff, normal_entries_0_1_eff}; // @[package.scala:45:27] wire [2:0] eff_array_lo = {eff_array_lo_hi, normal_entries_0_0_eff}; // @[package.scala:45:27] wire [1:0] eff_array_hi_hi = {normal_entries_0_5_eff, normal_entries_0_4_eff}; // @[package.scala:45:27] wire [2:0] eff_array_hi = {eff_array_hi_hi, normal_entries_0_3_eff}; // @[package.scala:45:27] wire [5:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [7:0] _eff_array_T_2 = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [7:0] eff_array_0 = _eff_array_T_2; // @[tlb.scala:119:49, :223:39] wire [1:0] _c_array_T = {2{cacheable_0}}; // @[tlb.scala:119:49, :224:44] wire [1:0] _GEN_34 = {normal_entries_0_2_c, normal_entries_0_1_c}; // @[package.scala:45:27] wire [1:0] c_array_lo_hi; // @[package.scala:45:27] assign c_array_lo_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi = _GEN_34; // @[package.scala:45:27] wire [2:0] c_array_lo = {c_array_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {normal_entries_0_5_c, normal_entries_0_4_c}; // @[package.scala:45:27] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_35; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [7:0] _c_array_T_2 = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [7:0] c_array_0 = _c_array_T_2; // @[tlb.scala:119:49, :224:39] wire [7:0] _paa_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :227:61] wire [7:0] _pal_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :228:61] wire [7:0] _lrscAllowed_T = c_array_0; // @[tlb.scala:119:49, :250:38] wire [1:0] _paa_array_T = {2{prot_aa_0}}; // @[tlb.scala:119:49, :225:44] wire [1:0] paa_array_lo_hi = {normal_entries_0_2_paa, normal_entries_0_1_paa}; // @[package.scala:45:27] wire [2:0] paa_array_lo = {paa_array_lo_hi, normal_entries_0_0_paa}; // @[package.scala:45:27] wire [1:0] paa_array_hi_hi = {normal_entries_0_5_paa, normal_entries_0_4_paa}; // @[package.scala:45:27] wire [2:0] paa_array_hi = {paa_array_hi_hi, normal_entries_0_3_paa}; // @[package.scala:45:27] wire [5:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [7:0] _paa_array_T_2 = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [7:0] paa_array_0 = _paa_array_T_2; // @[tlb.scala:119:49, :225:39] wire [1:0] _pal_array_T = {2{prot_al_0}}; // @[tlb.scala:119:49, :226:44] wire [1:0] pal_array_lo_hi = {normal_entries_0_2_pal, normal_entries_0_1_pal}; // @[package.scala:45:27] wire [2:0] pal_array_lo = {pal_array_lo_hi, normal_entries_0_0_pal}; // @[package.scala:45:27] wire [1:0] pal_array_hi_hi = {normal_entries_0_5_pal, normal_entries_0_4_pal}; // @[package.scala:45:27] wire [2:0] pal_array_hi = {pal_array_hi_hi, normal_entries_0_3_pal}; // @[package.scala:45:27] wire [5:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [7:0] _pal_array_T_2 = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [7:0] pal_array_0 = _pal_array_T_2; // @[tlb.scala:119:49, :226:39] wire [7:0] _paa_array_if_cached_T_1 = paa_array_0 | _paa_array_if_cached_T; // @[tlb.scala:119:49, :227:{56,61}] wire [7:0] paa_array_if_cached_0 = _paa_array_if_cached_T_1; // @[tlb.scala:119:49, :227:56] wire [7:0] _pal_array_if_cached_T_1 = pal_array_0 | _pal_array_if_cached_T; // @[tlb.scala:119:49, :228:{56,61}] wire [7:0] pal_array_if_cached_0 = _pal_array_if_cached_T_1; // @[tlb.scala:119:49, :228:56] wire _prefetchable_array_T = cacheable_0 & homogeneous_0; // @[tlb.scala:119:49, :229:61] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[tlb.scala:229:{61,80}] wire [2:0] prefetchable_array_lo = {prefetchable_array_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27] wire [5:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [7:0] _prefetchable_array_T_3 = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [7:0] prefetchable_array_0 = _prefetchable_array_T_3; // @[tlb.scala:119:49, :229:46] wire [3:0] _misaligned_T = 4'h1 << io_req_0_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[tlb.scala:231:89] wire [39:0] _misaligned_T_3 = {36'h0, io_req_0_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[tlb.scala:17:7, :231:{56,89}] wire _misaligned_T_4 = |_misaligned_T_3; // @[tlb.scala:231:{56,97}] wire misaligned_0 = _misaligned_T_4; // @[tlb.scala:119:49, :231:97] wire [39:0] bad_va_maskedVAddr = io_req_0_bits_vaddr_0 & 40'hC000000000; // @[tlb.scala:17:7, :237:46] wire _bad_va_T_1 = bad_va_maskedVAddr == 40'h0; // @[tlb.scala:237:46, :238:63] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'hC000000000; // @[tlb.scala:237:46, :238:86] wire _bad_va_T_3 = _bad_va_T_1 | _bad_va_T_2; // @[tlb.scala:238:{63,71,86}] wire _bad_va_T_4 = ~_bad_va_T_3; // @[tlb.scala:238:{49,71}] wire _bad_va_T_5 = _bad_va_T_4; // @[tlb.scala:238:{46,49}] wire _bad_va_T_6 = vm_enabled_0 & _bad_va_T_5; // @[tlb.scala:119:49, :232:134, :238:46] wire bad_va_0 = _bad_va_T_6; // @[tlb.scala:119:49, :232:134] wire _GEN_36 = io_req_0_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_36; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = io_req_0_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_37; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_37; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_37; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire _cmd_lrsc_T_3 = _cmd_lrsc_T_2; // @[package.scala:81:59] wire cmd_lrsc_0 = _cmd_lrsc_T_3; // @[tlb.scala:119:49, :242:57] wire _GEN_38 = io_req_0_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_38; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_38; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = io_req_0_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_39; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_39; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = io_req_0_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_40; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_40; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = io_req_0_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_41; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_41; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_41; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_7 = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire cmd_amo_logical_0 = _cmd_amo_logical_T_7; // @[tlb.scala:119:49, :243:57] wire _GEN_42 = io_req_0_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_42; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_0_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_43; // @[package.scala:16:47] wire _GEN_44 = io_req_0_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_0_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_0_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_46; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_9 = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire cmd_amo_arithmetic_0 = _cmd_amo_arithmetic_T_9; // @[tlb.scala:119:49, :244:57] wire _cmd_read_T = io_req_0_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _cmd_read_T_1 = io_req_0_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire _cmd_read_T_24 = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire cmd_read_0 = _cmd_read_T_24; // @[Consts.scala:89:68] wire _cmd_write_T = io_req_0_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _cmd_write_T_1 = io_req_0_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire _cmd_write_T_22 = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire cmd_write_0 = _cmd_write_T_22; // @[Consts.scala:90:76] wire _cmd_write_perms_T_2 = cmd_write_0; // @[tlb.scala:119:49, :247:55] wire _cmd_write_perms_T = io_req_0_bits_cmd_0 == 5'h5; // @[tlb.scala:17:7, :248:51] wire cmd_write_perms_0 = _cmd_write_perms_T_2; // @[tlb.scala:119:49, :247:55] wire [7:0] lrscAllowed_0 = _lrscAllowed_T; // @[tlb.scala:119:49, :250:38] wire [7:0] _ae_array_T = misaligned_0 ? eff_array_0 : 8'h0; // @[tlb.scala:119:49, :252:8] wire [7:0] _ae_array_T_1 = ~lrscAllowed_0; // @[tlb.scala:119:49, :253:24] wire [7:0] _ae_array_T_2 = cmd_lrsc_0 ? _ae_array_T_1 : 8'h0; // @[tlb.scala:119:49, :253:{8,24}] wire [7:0] _ae_array_T_3 = _ae_array_T | _ae_array_T_2; // @[tlb.scala:252:{8,43}, :253:8] wire [7:0] ae_array_0 = _ae_array_T_3; // @[tlb.scala:119:49, :252:43] wire _ae_valid_array_T = ~do_refill; // @[tlb.scala:144:29, :254:118] wire [1:0] _ae_valid_array_T_1 = {1'h1, _ae_valid_array_T}; // @[tlb.scala:254:{84,118}] wire [7:0] _ae_valid_array_T_3 = {_ae_valid_array_T_1, 6'h3F}; // @[tlb.scala:254:{41,84}] wire [7:0] ae_valid_array_0 = _ae_valid_array_T_3; // @[tlb.scala:119:49, :254:41] wire [7:0] _ae_ld_array_T = ~pr_array_0; // @[tlb.scala:119:49, :256:66] wire [7:0] _ae_ld_array_T_1 = ae_array_0 | _ae_ld_array_T; // @[tlb.scala:119:49, :256:{64,66}] wire [7:0] _ae_ld_array_T_2 = cmd_read_0 ? _ae_ld_array_T_1 : 8'h0; // @[tlb.scala:119:49, :256:{38,64}] wire [7:0] ae_ld_array_0 = _ae_ld_array_T_2; // @[tlb.scala:119:49, :256:38] wire [7:0] _ae_st_array_T = ~pw_array_0; // @[tlb.scala:119:49, :258:46] wire [7:0] _ae_st_array_T_1 = ae_array_0 | _ae_st_array_T; // @[tlb.scala:119:49, :258:{44,46}] wire [7:0] _ae_st_array_T_2 = cmd_write_perms_0 ? _ae_st_array_T_1 : 8'h0; // @[tlb.scala:119:49, :258:{8,44}] wire [7:0] _ae_st_array_T_3 = ~pal_array_if_cached_0; // @[tlb.scala:119:49, :259:32] wire [7:0] _ae_st_array_T_4 = cmd_amo_logical_0 ? _ae_st_array_T_3 : 8'h0; // @[tlb.scala:119:49, :259:{8,32}] wire [7:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[tlb.scala:258:{8,65}, :259:8] wire [7:0] _ae_st_array_T_6 = ~paa_array_if_cached_0; // @[tlb.scala:119:49, :260:32] wire [7:0] _ae_st_array_T_7 = cmd_amo_arithmetic_0 ? _ae_st_array_T_6 : 8'h0; // @[tlb.scala:119:49, :260:{8,32}] wire [7:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[tlb.scala:258:65, :259:62, :260:8] wire [7:0] ae_st_array_0 = _ae_st_array_T_8; // @[tlb.scala:119:49, :259:62] wire [7:0] _must_alloc_array_T = ~paa_array_0; // @[tlb.scala:119:49, :262:32] wire [7:0] _must_alloc_array_T_1 = cmd_amo_logical_0 ? _must_alloc_array_T : 8'h0; // @[tlb.scala:119:49, :262:{8,32}] wire [7:0] _must_alloc_array_T_2 = ~pal_array_0; // @[tlb.scala:119:49, :263:32] wire [7:0] _must_alloc_array_T_3 = cmd_amo_arithmetic_0 ? _must_alloc_array_T_2 : 8'h0; // @[tlb.scala:119:49, :263:{8,32}] wire [7:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[tlb.scala:262:{8,52}, :263:8] wire [7:0] _must_alloc_array_T_6 = {8{cmd_lrsc_0}}; // @[tlb.scala:119:49, :264:8] wire [7:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[tlb.scala:262:52, :263:52, :264:8] wire [7:0] must_alloc_array_0 = _must_alloc_array_T_7; // @[tlb.scala:119:49, :263:52] wire _ma_ld_array_T = misaligned_0 & cmd_read_0; // @[tlb.scala:119:49, :265:53] wire [7:0] _ma_ld_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70] wire [7:0] _ma_ld_array_T_2 = _ma_ld_array_T ? _ma_ld_array_T_1 : 8'h0; // @[tlb.scala:265:{38,53,70}] wire [7:0] ma_ld_array_0 = _ma_ld_array_T_2; // @[tlb.scala:119:49, :265:38] wire _ma_st_array_T = misaligned_0 & cmd_write_0; // @[tlb.scala:119:49, :266:53] wire [7:0] _ma_st_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70, :266:70] wire [7:0] _ma_st_array_T_2 = _ma_st_array_T ? _ma_st_array_T_1 : 8'h0; // @[tlb.scala:266:{38,53,70}] wire [7:0] ma_st_array_0 = _ma_st_array_T_2; // @[tlb.scala:119:49, :266:38] wire [7:0] _pf_ld_array_T = r_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :267:72] wire [7:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[tlb.scala:267:{59,72}] wire [7:0] _pf_ld_array_T_2 = cmd_read_0 ? _pf_ld_array_T_1 : 8'h0; // @[tlb.scala:119:49, :267:{38,59}] wire [7:0] pf_ld_array_0 = _pf_ld_array_T_2; // @[tlb.scala:119:49, :267:38] wire [7:0] _pf_st_array_T = w_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :268:72] wire [7:0] _pf_st_array_T_1 = ~_pf_st_array_T; // @[tlb.scala:268:{59,72}] wire [7:0] _pf_st_array_T_2 = cmd_write_perms_0 ? _pf_st_array_T_1 : 8'h0; // @[tlb.scala:119:49, :268:{38,59}] wire [7:0] pf_st_array_0 = _pf_st_array_T_2; // @[tlb.scala:119:49, :268:38] wire [7:0] _pf_inst_array_T = x_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :269:50] wire [7:0] _pf_inst_array_T_1 = ~_pf_inst_array_T; // @[tlb.scala:269:{37,50}] wire [7:0] pf_inst_array_0 = _pf_inst_array_T_1; // @[tlb.scala:119:49, :269:37] wire _tlb_hit_T = |real_hits_0; // @[tlb.scala:119:49, :271:44] wire tlb_hit_0 = _tlb_hit_T; // @[tlb.scala:119:49, :271:44] wire _tlb_miss_T = ~bad_va_0; // @[tlb.scala:119:49, :272:49] wire _tlb_miss_T_1 = vm_enabled_0 & _tlb_miss_T; // @[tlb.scala:119:49, :272:{46,49}] wire _tlb_miss_T_2 = ~tlb_hit_0; // @[tlb.scala:119:49, :272:63] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[tlb.scala:272:{46,60,63}] wire tlb_miss_0 = _tlb_miss_T_3; // @[tlb.scala:119:49, :272:60] reg state_reg; // @[Replacement.scala:168:70] wire _r_sectored_repl_addr_T = state_reg; // @[Replacement.scala:168:70, :262:12] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire _state_reg_T = state_reg_touch_way_sized; // @[package.scala:163:13] wire _state_reg_T_1 = ~_state_reg_T; // @[Replacement.scala:218:{7,17}] wire [1:0] lo = {superpage_hits_0_1, superpage_hits_0_0}; // @[OneHot.scala:22:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:22:45, :31:18] wire [1:0] hi = {superpage_hits_0_3, superpage_hits_0_2}; // @[OneHot.scala:22:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:22:45, :30:18] wire [1:0] state_reg_touch_way_sized_1 = {|hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T_2 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_6 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13] wire _state_reg_T_3 = _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_4 = ~_state_reg_T_3; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_5 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_4; // @[package.scala:163:13] wire _state_reg_T_7 = _state_reg_T_6; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_8 = ~_state_reg_T_7; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_9 = state_reg_set_left_older ? _state_reg_T_8 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_5}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_10 = {state_reg_hi, _state_reg_T_9}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits_0[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 | _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_9 = real_hits_0[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_10 = _multipleHits_T_9[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_12 = _multipleHits_T_10[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_2 = _multipleHits_T_12; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_14 = multipleHits_leftOne_3 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_1 = _multipleHits_T_14; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_15 = _multipleHits_T_9[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_16 = _multipleHits_T_15[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_5 = _multipleHits_T_16; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_17 = _multipleHits_T_15[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_3 = _multipleHits_T_17; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_4 = multipleHits_leftOne_5 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_19 = multipleHits_leftOne_5 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_19; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_5 = multipleHits_leftOne_4 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_20 = multipleHits_leftTwo_1 | multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_21 = multipleHits_leftOne_4 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_20 | _multipleHits_T_21; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_22 = multipleHits_leftOne_2 | multipleHits_rightOne_5; // @[Misc.scala:183:16] wire _multipleHits_T_23 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_24 = multipleHits_leftOne_2 & multipleHits_rightOne_5; // @[Misc.scala:183:{16,61}] wire _multipleHits_T_25 = _multipleHits_T_23 | _multipleHits_T_24; // @[Misc.scala:183:{37,49,61}] wire multipleHits_0 = _multipleHits_T_25; // @[Misc.scala:183:49] assign _io_miss_rdy_T = state == 2'h0; // @[tlb.scala:129:22, :290:24] assign io_miss_rdy = _io_miss_rdy_T; // @[tlb.scala:17:7, :290:24] wire _io_resp_0_pf_ld_T = bad_va_0 & cmd_read_0; // @[tlb.scala:119:49, :298:38] wire [7:0] _io_resp_0_pf_ld_T_1 = pf_ld_array_0 & hits_0; // @[tlb.scala:119:49, :298:73] wire _io_resp_0_pf_ld_T_2 = |_io_resp_0_pf_ld_T_1; // @[tlb.scala:298:{73,84}] assign _io_resp_0_pf_ld_T_3 = _io_resp_0_pf_ld_T | _io_resp_0_pf_ld_T_2; // @[tlb.scala:298:{38,54,84}] assign io_resp_0_pf_ld_0 = _io_resp_0_pf_ld_T_3; // @[tlb.scala:17:7, :298:54] wire _io_resp_0_pf_st_T = bad_va_0 & cmd_write_perms_0; // @[tlb.scala:119:49, :299:38] wire [7:0] _io_resp_0_pf_st_T_1 = pf_st_array_0 & hits_0; // @[tlb.scala:119:49, :299:80] wire _io_resp_0_pf_st_T_2 = |_io_resp_0_pf_st_T_1; // @[tlb.scala:299:{80,91}] assign _io_resp_0_pf_st_T_3 = _io_resp_0_pf_st_T | _io_resp_0_pf_st_T_2; // @[tlb.scala:299:{38,61,91}] assign io_resp_0_pf_st_0 = _io_resp_0_pf_st_T_3; // @[tlb.scala:17:7, :299:61] wire [7:0] _io_resp_0_pf_inst_T = pf_inst_array_0 & hits_0; // @[tlb.scala:119:49, :300:58] wire _io_resp_0_pf_inst_T_1 = |_io_resp_0_pf_inst_T; // @[tlb.scala:300:{58,69}] assign _io_resp_0_pf_inst_T_2 = bad_va_0 | _io_resp_0_pf_inst_T_1; // @[tlb.scala:119:49, :300:{37,69}] assign io_resp_0_pf_inst = _io_resp_0_pf_inst_T_2; // @[tlb.scala:17:7, :300:37] wire [7:0] _io_resp_0_ae_ld_T = ae_valid_array_0 & ae_ld_array_0; // @[tlb.scala:119:49, :301:46] wire [7:0] _io_resp_0_ae_ld_T_1 = _io_resp_0_ae_ld_T & hits_0; // @[tlb.scala:119:49, :301:{46,63}] assign _io_resp_0_ae_ld_T_2 = |_io_resp_0_ae_ld_T_1; // @[tlb.scala:301:{63,74}] assign io_resp_0_ae_ld_0 = _io_resp_0_ae_ld_T_2; // @[tlb.scala:17:7, :301:74] wire [7:0] _io_resp_0_ae_st_T = ae_valid_array_0 & ae_st_array_0; // @[tlb.scala:119:49, :302:46] wire [7:0] _io_resp_0_ae_st_T_1 = _io_resp_0_ae_st_T & hits_0; // @[tlb.scala:119:49, :302:{46,63}] assign _io_resp_0_ae_st_T_2 = |_io_resp_0_ae_st_T_1; // @[tlb.scala:302:{63,74}] assign io_resp_0_ae_st_0 = _io_resp_0_ae_st_T_2; // @[tlb.scala:17:7, :302:74] wire [7:0] _io_resp_0_ae_inst_T = ~px_array_0; // @[tlb.scala:119:49, :303:48] wire [7:0] _io_resp_0_ae_inst_T_1 = ae_valid_array_0 & _io_resp_0_ae_inst_T; // @[tlb.scala:119:49, :303:{46,48}] wire [7:0] _io_resp_0_ae_inst_T_2 = _io_resp_0_ae_inst_T_1 & hits_0; // @[tlb.scala:119:49, :303:{46,63}] assign _io_resp_0_ae_inst_T_3 = |_io_resp_0_ae_inst_T_2; // @[tlb.scala:303:{63,74}] assign io_resp_0_ae_inst = _io_resp_0_ae_inst_T_3; // @[tlb.scala:17:7, :303:74] wire [7:0] _io_resp_0_ma_ld_T = ma_ld_array_0 & hits_0; // @[tlb.scala:119:49, :304:43] assign _io_resp_0_ma_ld_T_1 = |_io_resp_0_ma_ld_T; // @[tlb.scala:304:{43,54}] assign io_resp_0_ma_ld_0 = _io_resp_0_ma_ld_T_1; // @[tlb.scala:17:7, :304:54] wire [7:0] _io_resp_0_ma_st_T = ma_st_array_0 & hits_0; // @[tlb.scala:119:49, :305:43] assign _io_resp_0_ma_st_T_1 = |_io_resp_0_ma_st_T; // @[tlb.scala:305:{43,54}] assign io_resp_0_ma_st_0 = _io_resp_0_ma_st_T_1; // @[tlb.scala:17:7, :305:54] wire [7:0] _io_resp_0_cacheable_T = c_array_0 & hits_0; // @[tlb.scala:119:49, :307:44] assign _io_resp_0_cacheable_T_1 = |_io_resp_0_cacheable_T; // @[tlb.scala:307:{44,55}] assign io_resp_0_cacheable_0 = _io_resp_0_cacheable_T_1; // @[tlb.scala:17:7, :307:55] wire [7:0] _io_resp_0_must_alloc_T = must_alloc_array_0 & hits_0; // @[tlb.scala:119:49, :308:53] assign _io_resp_0_must_alloc_T_1 = |_io_resp_0_must_alloc_T; // @[tlb.scala:308:{53,64}] assign io_resp_0_must_alloc = _io_resp_0_must_alloc_T_1; // @[tlb.scala:17:7, :308:64] wire [7:0] _io_resp_0_prefetchable_T = prefetchable_array_0 & hits_0; // @[tlb.scala:119:49, :309:55] wire _io_resp_0_prefetchable_T_1 = |_io_resp_0_prefetchable_T; // @[tlb.scala:309:{55,66}] assign _io_resp_0_prefetchable_T_2 = _io_resp_0_prefetchable_T_1; // @[tlb.scala:309:{66,70}] assign io_resp_0_prefetchable = _io_resp_0_prefetchable_T_2; // @[tlb.scala:17:7, :309:70] wire _io_resp_0_miss_T = do_refill | tlb_miss_0; // @[tlb.scala:119:49, :144:29, :310:35] assign _io_resp_0_miss_T_1 = _io_resp_0_miss_T | multipleHits_0; // @[tlb.scala:119:49, :310:{35,50}] assign io_resp_0_miss_0 = _io_resp_0_miss_T_1; // @[tlb.scala:17:7, :310:50] assign _io_resp_0_paddr_T_1 = {ppn_0, _io_resp_0_paddr_T}; // @[tlb.scala:119:49, :311:{28,57}] assign io_resp_0_paddr_0 = _io_resp_0_paddr_T_1; // @[tlb.scala:17:7, :311:28] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[tlb.scala:17:7, :317:29] assign _io_ptw_req_bits_valid_T = ~io_kill_0; // @[tlb.scala:17:7, :319:28] assign io_ptw_req_bits_valid_0 = _io_ptw_req_bits_valid_T; // @[tlb.scala:17:7, :319:28] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_1_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire _r_sectored_repl_addr_T_1 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [1:0] _r_sectored_repl_addr_T_2 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_3 = _r_sectored_repl_addr_T_2[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_4 = _r_sectored_repl_addr_T_2[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_5 = ~_r_sectored_repl_addr_T_3; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_5; // @[Mux.scala:50:70] wire [1:0] _r_sectored_hit_addr_T = {sector_hits_0_1, sector_hits_0_0}; // @[OneHot.scala:22:45] wire _r_sectored_hit_addr_T_1 = _r_sectored_hit_addr_T[1]; // @[OneHot.scala:22:45] wire _r_sectored_hit_T = sector_hits_0_0 | sector_hits_0_1; // @[package.scala:81:59] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[tlb.scala:17:7, :337:45]

Generate the Verilog code corresponding to this FIRRTL code module SourceX_6 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}, x : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}} wire x : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}} inst io_x_q of Queue1_SourceXRequest_6 connect io_x_q.clock, clock connect io_x_q.reset, reset connect io_x_q.io.enq.valid, x.valid connect io_x_q.io.enq.bits.fail, x.bits.fail connect x.ready, io_x_q.io.enq.ready connect io.x.bits, io_x_q.io.deq.bits connect io.x.valid, io_x_q.io.deq.valid connect io_x_q.io.deq.ready, io.x.ready connect io.req.ready, x.ready connect x.valid, io.req.valid node _T = eq(x.ready, UInt<1>(0h0)) node _T_1 = and(x.valid, _T) connect x.bits, io.req.bits

module SourceX_6( // @[SourceX.scala:29:7] input clock, // @[SourceX.scala:29:7] input reset, // @[SourceX.scala:29:7] output io_req_ready, // @[SourceX.scala:31:14] input io_req_valid, // @[SourceX.scala:31:14] output io_x_valid // @[SourceX.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceX.scala:29:7] wire io_x_ready = 1'h1; // @[Decoupled.scala:362:21] wire io_req_bits_fail = 1'h0; // @[SourceX.scala:29:7] wire io_x_bits_fail = 1'h0; // @[SourceX.scala:29:7] wire x_ready; // @[SourceX.scala:36:15] wire x_bits_fail = 1'h0; // @[SourceX.scala:36:15] wire x_valid = io_req_valid_0; // @[SourceX.scala:29:7, :36:15] wire io_req_ready_0; // @[SourceX.scala:29:7] wire io_x_valid_0; // @[SourceX.scala:29:7] assign io_req_ready_0 = x_ready; // @[SourceX.scala:29:7, :36:15] Queue1_SourceXRequest_6 io_x_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x_ready), .io_enq_valid (x_valid), // @[SourceX.scala:36:15] .io_deq_valid (io_x_valid_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceX.scala:29:7] assign io_x_valid = io_x_valid_0; // @[SourceX.scala:29:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = and(_T_207, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_206, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_215, UInt<1>(0h1), "") : assert_26 node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(is_aligned, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(io.in.a.bits.mask, mask) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_229, UInt<1>(0h1), "") : assert_30 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_237 = shr(io.in.a.bits.source, 11) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(_T_244, _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_253, UInt<1>(0h1), "") : assert_31 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_263, UInt<1>(0h1), "") : assert_34 node _T_267 = not(mask) node _T_268 = and(io.in.a.bits.mask, _T_267) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_269, UInt<1>(0h1), "") : assert_35 node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_277 = shr(io.in.a.bits.source, 11) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) node _T_280 = and(_T_278, _T_279) node _T_281 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_282 = and(_T_280, _T_281) node _T_283 = and(_T_276, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_T_284, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_293, UInt<1>(0h1), "") : assert_36 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(is_aligned, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_303, UInt<1>(0h1), "") : assert_39 node _T_307 = eq(io.in.a.bits.mask, mask) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_307, UInt<1>(0h1), "") : assert_40 node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_311 : node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_315 = shr(io.in.a.bits.source, 11) node _T_316 = eq(_T_315, UInt<1>(0h0)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_320 = and(_T_318, _T_319) node _T_321 = and(_T_314, _T_320) node _T_322 = or(UInt<1>(0h0), _T_321) node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = and(_T_323, _T_328) node _T_330 = or(UInt<1>(0h0), _T_329) node _T_331 = and(_T_322, _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_331, UInt<1>(0h1), "") : assert_41 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(is_aligned, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_341, UInt<1>(0h1), "") : assert_44 node _T_345 = eq(io.in.a.bits.mask, mask) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_345, UInt<1>(0h1), "") : assert_45 node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_349 : node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_353 = shr(io.in.a.bits.source, 11) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_358 = and(_T_356, _T_357) node _T_359 = and(_T_352, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = and(_T_361, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(_T_360, _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_369, UInt<1>(0h1), "") : assert_46 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(is_aligned, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_379, UInt<1>(0h1), "") : assert_49 node _T_383 = eq(io.in.a.bits.mask, mask) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_383, UInt<1>(0h1), "") : assert_50 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_387, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_391, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_399, UInt<1>(0h1), "") : assert_54 node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_403, UInt<1>(0h1), "") : assert_55 node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_407, UInt<1>(0h1), "") : assert_56 node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_411, UInt<1>(0h1), "") : assert_57 node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(sink_ok, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_422, UInt<1>(0h1), "") : assert_60 node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_426, UInt<1>(0h1), "") : assert_61 node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_430, UInt<1>(0h1), "") : assert_62 node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_434, UInt<1>(0h1), "") : assert_63 node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_439, UInt<1>(0h1), "") : assert_64 node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_443 : node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(sink_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_450, UInt<1>(0h1), "") : assert_67 node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_454, UInt<1>(0h1), "") : assert_68 node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_458, UInt<1>(0h1), "") : assert_69 node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_463 = or(_T_462, io.in.d.bits.corrupt) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_463, UInt<1>(0h1), "") : assert_70 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_468, UInt<1>(0h1), "") : assert_71 node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_472 : node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_476, UInt<1>(0h1), "") : assert_73 node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_480, UInt<1>(0h1), "") : assert_74 node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_485, UInt<1>(0h1), "") : assert_75 node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_493, UInt<1>(0h1), "") : assert_77 node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_498 = or(_T_497, io.in.d.bits.corrupt) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_498, UInt<1>(0h1), "") : assert_78 node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_503, UInt<1>(0h1), "") : assert_79 node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_507 : node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_511, UInt<1>(0h1), "") : assert_81 node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_515, UInt<1>(0h1), "") : assert_82 node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_520, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_524, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_528, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_532, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_536 = eq(a_first, UInt<1>(0h0)) node _T_537 = and(io.in.a.valid, _T_536) when _T_537 : node _T_538 = eq(io.in.a.bits.opcode, opcode) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_538, UInt<1>(0h1), "") : assert_87 node _T_542 = eq(io.in.a.bits.param, param) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_542, UInt<1>(0h1), "") : assert_88 node _T_546 = eq(io.in.a.bits.size, size) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_546, UInt<1>(0h1), "") : assert_89 node _T_550 = eq(io.in.a.bits.source, source) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_550, UInt<1>(0h1), "") : assert_90 node _T_554 = eq(io.in.a.bits.address, address) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_554, UInt<1>(0h1), "") : assert_91 node _T_558 = and(io.in.a.ready, io.in.a.valid) node _T_559 = and(_T_558, a_first) when _T_559 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_560 = eq(d_first, UInt<1>(0h0)) node _T_561 = and(io.in.d.valid, _T_560) when _T_561 : node _T_562 = eq(io.in.d.bits.opcode, opcode_1) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_562, UInt<1>(0h1), "") : assert_92 node _T_566 = eq(io.in.d.bits.param, param_1) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_566, UInt<1>(0h1), "") : assert_93 node _T_570 = eq(io.in.d.bits.size, size_1) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_570, UInt<1>(0h1), "") : assert_94 node _T_574 = eq(io.in.d.bits.source, source_1) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_574, UInt<1>(0h1), "") : assert_95 node _T_578 = eq(io.in.d.bits.sink, sink) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_578, UInt<1>(0h1), "") : assert_96 node _T_582 = eq(io.in.d.bits.denied, denied) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_582, UInt<1>(0h1), "") : assert_97 node _T_586 = and(io.in.d.ready, io.in.d.valid) node _T_587 = and(_T_586, d_first) when _T_587 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_588 = and(io.in.a.valid, a_first_1) node _T_589 = and(_T_588, UInt<1>(0h1)) when _T_589 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_590 = and(io.in.a.ready, io.in.a.valid) node _T_591 = and(_T_590, a_first_1) node _T_592 = and(_T_591, UInt<1>(0h1)) when _T_592 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_593 = dshr(inflight, io.in.a.bits.source) node _T_594 = bits(_T_593, 0, 0) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_595, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_599 = and(io.in.d.valid, d_first_1) node _T_600 = and(_T_599, UInt<1>(0h1)) node _T_601 = eq(d_release_ack, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) when _T_602 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_603 = and(io.in.d.ready, io.in.d.valid) node _T_604 = and(_T_603, d_first_1) node _T_605 = and(_T_604, UInt<1>(0h1)) node _T_606 = eq(d_release_ack, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_608 = and(io.in.d.valid, d_first_1) node _T_609 = and(_T_608, UInt<1>(0h1)) node _T_610 = eq(d_release_ack, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) when _T_611 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_612 = dshr(inflight, io.in.d.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = or(_T_613, same_cycle_resp) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_614, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_620 = or(_T_618, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_620, UInt<1>(0h1), "") : assert_100 node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_624, UInt<1>(0h1), "") : assert_101 else : node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_630 = or(_T_628, _T_629) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_630, UInt<1>(0h1), "") : assert_102 node _T_634 = eq(io.in.d.bits.size, a_size_lookup) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_634, UInt<1>(0h1), "") : assert_103 node _T_638 = and(io.in.d.valid, d_first_1) node _T_639 = and(_T_638, a_first_1) node _T_640 = and(_T_639, io.in.a.valid) node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_642 = and(_T_640, _T_641) node _T_643 = eq(d_release_ack, UInt<1>(0h0)) node _T_644 = and(_T_642, _T_643) when _T_644 : node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_646 = or(_T_645, io.in.a.ready) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_646, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_131 node _T_650 = orr(inflight) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_653 = or(_T_651, _T_652) node _T_654 = lt(watchdog, plusarg_reader.out) node _T_655 = or(_T_653, _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_655, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_659 = and(io.in.a.ready, io.in.a.valid) node _T_660 = and(io.in.d.ready, io.in.d.valid) node _T_661 = or(_T_659, _T_660) when _T_661 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_662 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_665 = and(_T_663, _T_664) node _T_666 = and(_T_662, _T_665) when _T_666 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_668 = and(_T_667, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) node _T_674 = bits(_T_673, 0, 0) node _T_675 = eq(_T_674, UInt<1>(0h0)) node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(_T_675, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_675, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_679 = and(io.in.d.valid, d_first_2) node _T_680 = and(_T_679, UInt<1>(0h1)) node _T_681 = and(_T_680, d_release_ack_1) when _T_681 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_682 = and(io.in.d.ready, io.in.d.valid) node _T_683 = and(_T_682, d_first_2) node _T_684 = and(_T_683, UInt<1>(0h1)) node _T_685 = and(_T_684, d_release_ack_1) when _T_685 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_686 = and(io.in.d.valid, d_first_2) node _T_687 = and(_T_686, UInt<1>(0h1)) node _T_688 = and(_T_687, d_release_ack_1) when _T_688 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_689 = dshr(inflight_1, io.in.d.bits.source) node _T_690 = bits(_T_689, 0, 0) node _T_691 = or(_T_690, same_cycle_resp_1) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_691, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_695, UInt<1>(0h1), "") : assert_108 else : node _T_699 = eq(io.in.d.bits.size, c_size_lookup) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_699, UInt<1>(0h1), "") : assert_109 node _T_703 = and(io.in.d.valid, d_first_2) node _T_704 = and(_T_703, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_705 = and(_T_704, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_707 = and(_T_705, _T_706) node _T_708 = and(_T_707, d_release_ack_1) node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_712 = or(_T_711, _WIRE_23.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_132 node _T_716 = orr(inflight_1) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_719 = or(_T_717, _T_718) node _T_720 = lt(watchdog_1, plusarg_reader_1.out) node _T_721 = or(_T_719, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_721, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_726 = and(io.in.d.ready, io.in.d.valid) node _T_727 = or(_T_725, _T_726) when _T_727 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<13>(0h1000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = and(_T_381, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = and(_T_380, _T_388) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_389, UInt<1>(0h1), "") : assert_2 node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<1>(0h0)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_8) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h1)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_9) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<2>(0h2)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_10) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h3)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_11) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_393 connect _WIRE[1], _T_399 connect _WIRE[2], _T_405 connect _WIRE[3], _T_411 connect _WIRE[4], _T_417 connect _WIRE[5], _T_418 connect _WIRE[6], _T_419 connect _WIRE[7], _T_420 connect _WIRE[8], _T_421 connect _WIRE[9], _T_422 connect _WIRE[10], _T_423 connect _WIRE[11], _T_424 connect _WIRE[12], _T_425 connect _WIRE[13], _T_426 connect _WIRE[14], _T_427 connect _WIRE[15], _T_428 connect _WIRE[16], _T_429 connect _WIRE[17], _T_430 connect _WIRE[18], _T_431 connect _WIRE[19], _T_432 connect _WIRE[20], _T_433 connect _WIRE[21], _T_434 connect _WIRE[22], _T_435 connect _WIRE[23], _T_436 connect _WIRE[24], _T_437 connect _WIRE[25], _T_438 connect _WIRE[26], _T_439 connect _WIRE[27], _T_440 connect _WIRE[28], _T_441 connect _WIRE[29], _T_442 node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0)) node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0)) node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0)) node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0)) node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0)) node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0)) node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0)) node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0)) node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_481 = or(_T_451, _T_452) node _T_482 = or(_T_481, _T_453) node _T_483 = or(_T_482, _T_454) node _T_484 = or(_T_483, _T_455) node _T_485 = or(_T_484, _T_456) node _T_486 = or(_T_485, _T_457) node _T_487 = or(_T_486, _T_458) node _T_488 = or(_T_487, _T_459) node _T_489 = or(_T_488, _T_460) node _T_490 = or(_T_489, _T_461) node _T_491 = or(_T_490, _T_462) node _T_492 = or(_T_491, _T_463) node _T_493 = or(_T_492, _T_464) node _T_494 = or(_T_493, _T_465) node _T_495 = or(_T_494, _T_466) node _T_496 = or(_T_495, _T_467) node _T_497 = or(_T_496, _T_468) node _T_498 = or(_T_497, _T_469) node _T_499 = or(_T_498, _T_470) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_472) node _T_502 = or(_T_501, _T_473) node _T_503 = or(_T_502, _T_474) node _T_504 = or(_T_503, _T_475) node _T_505 = or(_T_504, _T_476) node _T_506 = or(_T_505, _T_477) node _T_507 = or(_T_506, _T_478) node _T_508 = or(_T_507, _T_479) node _T_509 = or(_T_508, _T_480) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_509 node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(UInt<1>(0h0), _T_512) node _T_514 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_WIRE_1, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_521, UInt<1>(0h1), "") : assert_3 node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(source_ok, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_528, UInt<1>(0h1), "") : assert_5 node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(is_aligned, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_535, UInt<1>(0h1), "") : assert_7 node _T_539 = not(io.in.a.bits.mask) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_540, UInt<1>(0h1), "") : assert_8 node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_544, UInt<1>(0h1), "") : assert_9 node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<1>(0h0)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_12) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<1>(0h1)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_13) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<2>(0h2)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_14) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<2>(0h3)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_15) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_602 = or(_T_552, _T_558) node _T_603 = or(_T_602, _T_564) node _T_604 = or(_T_603, _T_570) node _T_605 = or(_T_604, _T_576) node _T_606 = or(_T_605, _T_577) node _T_607 = or(_T_606, _T_578) node _T_608 = or(_T_607, _T_579) node _T_609 = or(_T_608, _T_580) node _T_610 = or(_T_609, _T_581) node _T_611 = or(_T_610, _T_582) node _T_612 = or(_T_611, _T_583) node _T_613 = or(_T_612, _T_584) node _T_614 = or(_T_613, _T_585) node _T_615 = or(_T_614, _T_586) node _T_616 = or(_T_615, _T_587) node _T_617 = or(_T_616, _T_588) node _T_618 = or(_T_617, _T_589) node _T_619 = or(_T_618, _T_590) node _T_620 = or(_T_619, _T_591) node _T_621 = or(_T_620, _T_592) node _T_622 = or(_T_621, _T_593) node _T_623 = or(_T_622, _T_594) node _T_624 = or(_T_623, _T_595) node _T_625 = or(_T_624, _T_596) node _T_626 = or(_T_625, _T_597) node _T_627 = or(_T_626, _T_598) node _T_628 = or(_T_627, _T_599) node _T_629 = or(_T_628, _T_600) node _T_630 = or(_T_629, _T_601) node _T_631 = and(_T_551, _T_630) node _T_632 = or(UInt<1>(0h0), _T_631) node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = and(_T_633, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = and(_T_632, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_641, UInt<1>(0h1), "") : assert_10 node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_646 = shr(io.in.a.bits.source, 2) node _T_647 = eq(_T_646, UInt<1>(0h0)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_16) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_652 = shr(io.in.a.bits.source, 2) node _T_653 = eq(_T_652, UInt<1>(0h1)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_17) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_658 = shr(io.in.a.bits.source, 2) node _T_659 = eq(_T_658, UInt<2>(0h2)) node _T_660 = leq(UInt<1>(0h0), uncommonBits_18) node _T_661 = and(_T_659, _T_660) node _T_662 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<2>(0h3)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_19) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_645 connect _WIRE_2[1], _T_651 connect _WIRE_2[2], _T_657 connect _WIRE_2[3], _T_663 connect _WIRE_2[4], _T_669 connect _WIRE_2[5], _T_670 connect _WIRE_2[6], _T_671 connect _WIRE_2[7], _T_672 connect _WIRE_2[8], _T_673 connect _WIRE_2[9], _T_674 connect _WIRE_2[10], _T_675 connect _WIRE_2[11], _T_676 connect _WIRE_2[12], _T_677 connect _WIRE_2[13], _T_678 connect _WIRE_2[14], _T_679 connect _WIRE_2[15], _T_680 connect _WIRE_2[16], _T_681 connect _WIRE_2[17], _T_682 connect _WIRE_2[18], _T_683 connect _WIRE_2[19], _T_684 connect _WIRE_2[20], _T_685 connect _WIRE_2[21], _T_686 connect _WIRE_2[22], _T_687 connect _WIRE_2[23], _T_688 connect _WIRE_2[24], _T_689 connect _WIRE_2[25], _T_690 connect _WIRE_2[26], _T_691 connect _WIRE_2[27], _T_692 connect _WIRE_2[28], _T_693 connect _WIRE_2[29], _T_694 node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0)) node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0)) node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0)) node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0)) node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0)) node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0)) node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0)) node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0)) node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_733 = or(_T_703, _T_704) node _T_734 = or(_T_733, _T_705) node _T_735 = or(_T_734, _T_706) node _T_736 = or(_T_735, _T_707) node _T_737 = or(_T_736, _T_708) node _T_738 = or(_T_737, _T_709) node _T_739 = or(_T_738, _T_710) node _T_740 = or(_T_739, _T_711) node _T_741 = or(_T_740, _T_712) node _T_742 = or(_T_741, _T_713) node _T_743 = or(_T_742, _T_714) node _T_744 = or(_T_743, _T_715) node _T_745 = or(_T_744, _T_716) node _T_746 = or(_T_745, _T_717) node _T_747 = or(_T_746, _T_718) node _T_748 = or(_T_747, _T_719) node _T_749 = or(_T_748, _T_720) node _T_750 = or(_T_749, _T_721) node _T_751 = or(_T_750, _T_722) node _T_752 = or(_T_751, _T_723) node _T_753 = or(_T_752, _T_724) node _T_754 = or(_T_753, _T_725) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_727) node _T_757 = or(_T_756, _T_728) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_730) node _T_760 = or(_T_759, _T_731) node _T_761 = or(_T_760, _T_732) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_761 node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_764 = and(_T_762, _T_763) node _T_765 = or(UInt<1>(0h0), _T_764) node _T_766 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_771) node _T_773 = and(_WIRE_3, _T_772) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_773, UInt<1>(0h1), "") : assert_11 node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(source_ok, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_780, UInt<1>(0h1), "") : assert_13 node _T_784 = asUInt(reset) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(is_aligned, UInt<1>(0h0)) when _T_786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_787, UInt<1>(0h1), "") : assert_15 node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_791, UInt<1>(0h1), "") : assert_16 node _T_795 = not(io.in.a.bits.mask) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_796, UInt<1>(0h1), "") : assert_17 node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_800, UInt<1>(0h1), "") : assert_18 node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_20) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_21) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_22) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_23) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_858 = or(_T_808, _T_814) node _T_859 = or(_T_858, _T_820) node _T_860 = or(_T_859, _T_826) node _T_861 = or(_T_860, _T_832) node _T_862 = or(_T_861, _T_833) node _T_863 = or(_T_862, _T_834) node _T_864 = or(_T_863, _T_835) node _T_865 = or(_T_864, _T_836) node _T_866 = or(_T_865, _T_837) node _T_867 = or(_T_866, _T_838) node _T_868 = or(_T_867, _T_839) node _T_869 = or(_T_868, _T_840) node _T_870 = or(_T_869, _T_841) node _T_871 = or(_T_870, _T_842) node _T_872 = or(_T_871, _T_843) node _T_873 = or(_T_872, _T_844) node _T_874 = or(_T_873, _T_845) node _T_875 = or(_T_874, _T_846) node _T_876 = or(_T_875, _T_847) node _T_877 = or(_T_876, _T_848) node _T_878 = or(_T_877, _T_849) node _T_879 = or(_T_878, _T_850) node _T_880 = or(_T_879, _T_851) node _T_881 = or(_T_880, _T_852) node _T_882 = or(_T_881, _T_853) node _T_883 = or(_T_882, _T_854) node _T_884 = or(_T_883, _T_855) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = and(_T_807, _T_886) node _T_888 = or(UInt<1>(0h0), _T_887) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_888, UInt<1>(0h1), "") : assert_19 node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_893 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_894 = and(_T_892, _T_893) node _T_895 = or(UInt<1>(0h0), _T_894) node _T_896 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = and(_T_895, _T_900) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_902, UInt<1>(0h1), "") : assert_20 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(is_aligned, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_912, UInt<1>(0h1), "") : assert_23 node _T_916 = eq(io.in.a.bits.mask, mask) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_916, UInt<1>(0h1), "") : assert_24 node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_920, UInt<1>(0h1), "") : assert_25 node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_924 : node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_927 = and(_T_925, _T_926) node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_929 = shr(io.in.a.bits.source, 2) node _T_930 = eq(_T_929, UInt<1>(0h0)) node _T_931 = leq(UInt<1>(0h0), uncommonBits_24) node _T_932 = and(_T_930, _T_931) node _T_933 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_934 = and(_T_932, _T_933) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_935 = shr(io.in.a.bits.source, 2) node _T_936 = eq(_T_935, UInt<1>(0h1)) node _T_937 = leq(UInt<1>(0h0), uncommonBits_25) node _T_938 = and(_T_936, _T_937) node _T_939 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_940 = and(_T_938, _T_939) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_941 = shr(io.in.a.bits.source, 2) node _T_942 = eq(_T_941, UInt<2>(0h2)) node _T_943 = leq(UInt<1>(0h0), uncommonBits_26) node _T_944 = and(_T_942, _T_943) node _T_945 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_946 = and(_T_944, _T_945) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_947 = shr(io.in.a.bits.source, 2) node _T_948 = eq(_T_947, UInt<2>(0h3)) node _T_949 = leq(UInt<1>(0h0), uncommonBits_27) node _T_950 = and(_T_948, _T_949) node _T_951 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_952 = and(_T_950, _T_951) node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_978 = or(_T_928, _T_934) node _T_979 = or(_T_978, _T_940) node _T_980 = or(_T_979, _T_946) node _T_981 = or(_T_980, _T_952) node _T_982 = or(_T_981, _T_953) node _T_983 = or(_T_982, _T_954) node _T_984 = or(_T_983, _T_955) node _T_985 = or(_T_984, _T_956) node _T_986 = or(_T_985, _T_957) node _T_987 = or(_T_986, _T_958) node _T_988 = or(_T_987, _T_959) node _T_989 = or(_T_988, _T_960) node _T_990 = or(_T_989, _T_961) node _T_991 = or(_T_990, _T_962) node _T_992 = or(_T_991, _T_963) node _T_993 = or(_T_992, _T_964) node _T_994 = or(_T_993, _T_965) node _T_995 = or(_T_994, _T_966) node _T_996 = or(_T_995, _T_967) node _T_997 = or(_T_996, _T_968) node _T_998 = or(_T_997, _T_969) node _T_999 = or(_T_998, _T_970) node _T_1000 = or(_T_999, _T_971) node _T_1001 = or(_T_1000, _T_972) node _T_1002 = or(_T_1001, _T_973) node _T_1003 = or(_T_1002, _T_974) node _T_1004 = or(_T_1003, _T_975) node _T_1005 = or(_T_1004, _T_976) node _T_1006 = or(_T_1005, _T_977) node _T_1007 = and(_T_927, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1010 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = and(_T_1012, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = and(_T_1008, _T_1019) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_26 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(source_ok, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(is_aligned, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1030 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_29 node _T_1034 = eq(io.in.a.bits.mask, mask) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_30 node _T_1038 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1038 : node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1040 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1043 = shr(io.in.a.bits.source, 2) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1048 = and(_T_1046, _T_1047) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1049 = shr(io.in.a.bits.source, 2) node _T_1050 = eq(_T_1049, UInt<1>(0h1)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1055 = shr(io.in.a.bits.source, 2) node _T_1056 = eq(_T_1055, UInt<2>(0h2)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1061 = shr(io.in.a.bits.source, 2) node _T_1062 = eq(_T_1061, UInt<2>(0h3)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1092 = or(_T_1042, _T_1048) node _T_1093 = or(_T_1092, _T_1054) node _T_1094 = or(_T_1093, _T_1060) node _T_1095 = or(_T_1094, _T_1066) node _T_1096 = or(_T_1095, _T_1067) node _T_1097 = or(_T_1096, _T_1068) node _T_1098 = or(_T_1097, _T_1069) node _T_1099 = or(_T_1098, _T_1070) node _T_1100 = or(_T_1099, _T_1071) node _T_1101 = or(_T_1100, _T_1072) node _T_1102 = or(_T_1101, _T_1073) node _T_1103 = or(_T_1102, _T_1074) node _T_1104 = or(_T_1103, _T_1075) node _T_1105 = or(_T_1104, _T_1076) node _T_1106 = or(_T_1105, _T_1077) node _T_1107 = or(_T_1106, _T_1078) node _T_1108 = or(_T_1107, _T_1079) node _T_1109 = or(_T_1108, _T_1080) node _T_1110 = or(_T_1109, _T_1081) node _T_1111 = or(_T_1110, _T_1082) node _T_1112 = or(_T_1111, _T_1083) node _T_1113 = or(_T_1112, _T_1084) node _T_1114 = or(_T_1113, _T_1085) node _T_1115 = or(_T_1114, _T_1086) node _T_1116 = or(_T_1115, _T_1087) node _T_1117 = or(_T_1116, _T_1088) node _T_1118 = or(_T_1117, _T_1089) node _T_1119 = or(_T_1118, _T_1090) node _T_1120 = or(_T_1119, _T_1091) node _T_1121 = and(_T_1041, _T_1120) node _T_1122 = or(UInt<1>(0h0), _T_1121) node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = or(UInt<1>(0h0), _T_1125) node _T_1127 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = and(_T_1126, _T_1131) node _T_1133 = or(UInt<1>(0h0), _T_1132) node _T_1134 = and(_T_1122, _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_31 node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(source_ok, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(is_aligned, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1144 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_34 node _T_1148 = not(mask) node _T_1149 = and(io.in.a.bits.mask, _T_1148) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_35 node _T_1154 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1154 : node _T_1155 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1156 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1159 = shr(io.in.a.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1165 = shr(io.in.a.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1171 = shr(io.in.a.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1177 = shr(io.in.a.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1201 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1202 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1203 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1204 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1205 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1207 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1208 = or(_T_1158, _T_1164) node _T_1209 = or(_T_1208, _T_1170) node _T_1210 = or(_T_1209, _T_1176) node _T_1211 = or(_T_1210, _T_1182) node _T_1212 = or(_T_1211, _T_1183) node _T_1213 = or(_T_1212, _T_1184) node _T_1214 = or(_T_1213, _T_1185) node _T_1215 = or(_T_1214, _T_1186) node _T_1216 = or(_T_1215, _T_1187) node _T_1217 = or(_T_1216, _T_1188) node _T_1218 = or(_T_1217, _T_1189) node _T_1219 = or(_T_1218, _T_1190) node _T_1220 = or(_T_1219, _T_1191) node _T_1221 = or(_T_1220, _T_1192) node _T_1222 = or(_T_1221, _T_1193) node _T_1223 = or(_T_1222, _T_1194) node _T_1224 = or(_T_1223, _T_1195) node _T_1225 = or(_T_1224, _T_1196) node _T_1226 = or(_T_1225, _T_1197) node _T_1227 = or(_T_1226, _T_1198) node _T_1228 = or(_T_1227, _T_1199) node _T_1229 = or(_T_1228, _T_1200) node _T_1230 = or(_T_1229, _T_1201) node _T_1231 = or(_T_1230, _T_1202) node _T_1232 = or(_T_1231, _T_1203) node _T_1233 = or(_T_1232, _T_1204) node _T_1234 = or(_T_1233, _T_1205) node _T_1235 = or(_T_1234, _T_1206) node _T_1236 = or(_T_1235, _T_1207) node _T_1237 = and(_T_1157, _T_1236) node _T_1238 = or(UInt<1>(0h0), _T_1237) node _T_1239 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1240 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1241 = and(_T_1239, _T_1240) node _T_1242 = or(UInt<1>(0h0), _T_1241) node _T_1243 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<13>(0h1000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = and(_T_1242, _T_1247) node _T_1249 = or(UInt<1>(0h0), _T_1248) node _T_1250 = and(_T_1238, _T_1249) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_36 node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(source_ok, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(is_aligned, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1260 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_39 node _T_1264 = eq(io.in.a.bits.mask, mask) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_40 node _T_1268 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1268 : node _T_1269 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1270 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1271 = and(_T_1269, _T_1270) node _T_1272 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1273 = shr(io.in.a.bits.source, 2) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) node _T_1275 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1276 = and(_T_1274, _T_1275) node _T_1277 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1278 = and(_T_1276, _T_1277) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1279 = shr(io.in.a.bits.source, 2) node _T_1280 = eq(_T_1279, UInt<1>(0h1)) node _T_1281 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1282 = and(_T_1280, _T_1281) node _T_1283 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1284 = and(_T_1282, _T_1283) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1285 = shr(io.in.a.bits.source, 2) node _T_1286 = eq(_T_1285, UInt<2>(0h2)) node _T_1287 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1288 = and(_T_1286, _T_1287) node _T_1289 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1290 = and(_T_1288, _T_1289) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1291 = shr(io.in.a.bits.source, 2) node _T_1292 = eq(_T_1291, UInt<2>(0h3)) node _T_1293 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1294 = and(_T_1292, _T_1293) node _T_1295 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1312 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1313 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1315 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1316 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1317 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1318 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1319 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1320 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1321 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1322 = or(_T_1272, _T_1278) node _T_1323 = or(_T_1322, _T_1284) node _T_1324 = or(_T_1323, _T_1290) node _T_1325 = or(_T_1324, _T_1296) node _T_1326 = or(_T_1325, _T_1297) node _T_1327 = or(_T_1326, _T_1298) node _T_1328 = or(_T_1327, _T_1299) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1301) node _T_1331 = or(_T_1330, _T_1302) node _T_1332 = or(_T_1331, _T_1303) node _T_1333 = or(_T_1332, _T_1304) node _T_1334 = or(_T_1333, _T_1305) node _T_1335 = or(_T_1334, _T_1306) node _T_1336 = or(_T_1335, _T_1307) node _T_1337 = or(_T_1336, _T_1308) node _T_1338 = or(_T_1337, _T_1309) node _T_1339 = or(_T_1338, _T_1310) node _T_1340 = or(_T_1339, _T_1311) node _T_1341 = or(_T_1340, _T_1312) node _T_1342 = or(_T_1341, _T_1313) node _T_1343 = or(_T_1342, _T_1314) node _T_1344 = or(_T_1343, _T_1315) node _T_1345 = or(_T_1344, _T_1316) node _T_1346 = or(_T_1345, _T_1317) node _T_1347 = or(_T_1346, _T_1318) node _T_1348 = or(_T_1347, _T_1319) node _T_1349 = or(_T_1348, _T_1320) node _T_1350 = or(_T_1349, _T_1321) node _T_1351 = and(_T_1271, _T_1350) node _T_1352 = or(UInt<1>(0h0), _T_1351) node _T_1353 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1354 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1355 = and(_T_1353, _T_1354) node _T_1356 = or(UInt<1>(0h0), _T_1355) node _T_1357 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1358 = cvt(_T_1357) node _T_1359 = and(_T_1358, asSInt(UInt<13>(0h1000))) node _T_1360 = asSInt(_T_1359) node _T_1361 = eq(_T_1360, asSInt(UInt<1>(0h0))) node _T_1362 = and(_T_1356, _T_1361) node _T_1363 = or(UInt<1>(0h0), _T_1362) node _T_1364 = and(_T_1352, _T_1363) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_41 node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(source_ok, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1371 = asUInt(reset) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = eq(is_aligned, UInt<1>(0h0)) when _T_1373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1374 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_44 node _T_1378 = eq(io.in.a.bits.mask, mask) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_45 node _T_1382 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1382 : node _T_1383 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1384 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1385 = and(_T_1383, _T_1384) node _T_1386 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1387 = shr(io.in.a.bits.source, 2) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) node _T_1389 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1390 = and(_T_1388, _T_1389) node _T_1391 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1392 = and(_T_1390, _T_1391) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1393 = shr(io.in.a.bits.source, 2) node _T_1394 = eq(_T_1393, UInt<1>(0h1)) node _T_1395 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1398 = and(_T_1396, _T_1397) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1399 = shr(io.in.a.bits.source, 2) node _T_1400 = eq(_T_1399, UInt<2>(0h2)) node _T_1401 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1404 = and(_T_1402, _T_1403) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1405 = shr(io.in.a.bits.source, 2) node _T_1406 = eq(_T_1405, UInt<2>(0h3)) node _T_1407 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1410 = and(_T_1408, _T_1409) node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1429 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1430 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1431 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1432 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1433 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1434 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1435 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1436 = or(_T_1386, _T_1392) node _T_1437 = or(_T_1436, _T_1398) node _T_1438 = or(_T_1437, _T_1404) node _T_1439 = or(_T_1438, _T_1410) node _T_1440 = or(_T_1439, _T_1411) node _T_1441 = or(_T_1440, _T_1412) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1414) node _T_1444 = or(_T_1443, _T_1415) node _T_1445 = or(_T_1444, _T_1416) node _T_1446 = or(_T_1445, _T_1417) node _T_1447 = or(_T_1446, _T_1418) node _T_1448 = or(_T_1447, _T_1419) node _T_1449 = or(_T_1448, _T_1420) node _T_1450 = or(_T_1449, _T_1421) node _T_1451 = or(_T_1450, _T_1422) node _T_1452 = or(_T_1451, _T_1423) node _T_1453 = or(_T_1452, _T_1424) node _T_1454 = or(_T_1453, _T_1425) node _T_1455 = or(_T_1454, _T_1426) node _T_1456 = or(_T_1455, _T_1427) node _T_1457 = or(_T_1456, _T_1428) node _T_1458 = or(_T_1457, _T_1429) node _T_1459 = or(_T_1458, _T_1430) node _T_1460 = or(_T_1459, _T_1431) node _T_1461 = or(_T_1460, _T_1432) node _T_1462 = or(_T_1461, _T_1433) node _T_1463 = or(_T_1462, _T_1434) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = and(_T_1385, _T_1464) node _T_1466 = or(UInt<1>(0h0), _T_1465) node _T_1467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = or(UInt<1>(0h0), _T_1469) node _T_1471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1472 = cvt(_T_1471) node _T_1473 = and(_T_1472, asSInt(UInt<13>(0h1000))) node _T_1474 = asSInt(_T_1473) node _T_1475 = eq(_T_1474, asSInt(UInt<1>(0h0))) node _T_1476 = and(_T_1470, _T_1475) node _T_1477 = or(UInt<1>(0h0), _T_1476) node _T_1478 = and(_T_1466, _T_1477) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_46 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(source_ok, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(is_aligned, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1488 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_49 node _T_1492 = eq(io.in.a.bits.mask, mask) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_50 node _T_1496 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(_T_1496, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1496, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1500 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1504 : node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok_1, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1508 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_54 node _T_1512 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(_T_1512, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1512, UInt<1>(0h1), "") : assert_55 node _T_1516 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_56 node _T_1520 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_57 node _T_1524 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1524 : node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(source_ok_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(sink_ok, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1531 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(_T_1531, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1531, UInt<1>(0h1), "") : assert_60 node _T_1535 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_61 node _T_1539 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_62 node _T_1543 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_63 node _T_1547 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1548 = or(UInt<1>(0h1), _T_1547) node _T_1549 = asUInt(reset) node _T_1550 = eq(_T_1549, UInt<1>(0h0)) when _T_1550 : node _T_1551 = eq(_T_1548, UInt<1>(0h0)) when _T_1551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1548, UInt<1>(0h1), "") : assert_64 node _T_1552 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1552 : node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(source_ok_1, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(sink_ok, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1559 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_67 node _T_1563 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1564 = asUInt(reset) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(_T_1563, UInt<1>(0h0)) when _T_1566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1563, UInt<1>(0h1), "") : assert_68 node _T_1567 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(_T_1567, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1567, UInt<1>(0h1), "") : assert_69 node _T_1571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1572 = or(_T_1571, io.in.d.bits.corrupt) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_70 node _T_1576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1577 = or(UInt<1>(0h1), _T_1576) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_71 node _T_1581 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1581 : node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(source_ok_1, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_73 node _T_1589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_74 node _T_1593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1594 = or(UInt<1>(0h1), _T_1593) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_75 node _T_1598 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1598 : node _T_1599 = asUInt(reset) node _T_1600 = eq(_T_1599, UInt<1>(0h0)) when _T_1600 : node _T_1601 = eq(source_ok_1, UInt<1>(0h0)) when _T_1601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1602 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(_T_1602, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1602, UInt<1>(0h1), "") : assert_77 node _T_1606 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1607 = or(_T_1606, io.in.d.bits.corrupt) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_78 node _T_1611 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1612 = or(UInt<1>(0h1), _T_1611) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_79 node _T_1616 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1616 : node _T_1617 = asUInt(reset) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) when _T_1618 : node _T_1619 = eq(source_ok_1, UInt<1>(0h0)) when _T_1619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1620 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(_T_1620, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1620, UInt<1>(0h1), "") : assert_81 node _T_1624 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(_T_1624, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1624, UInt<1>(0h1), "") : assert_82 node _T_1628 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1629 = or(UInt<1>(0h1), _T_1628) node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(_T_1629, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1629, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1633 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(_T_1633, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1633, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1637 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1641 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1642 = asUInt(reset) node _T_1643 = eq(_T_1642, UInt<1>(0h0)) when _T_1643 : node _T_1644 = eq(_T_1641, UInt<1>(0h0)) when _T_1644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1641, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1645 = eq(a_first, UInt<1>(0h0)) node _T_1646 = and(io.in.a.valid, _T_1645) when _T_1646 : node _T_1647 = eq(io.in.a.bits.opcode, opcode) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_87 node _T_1651 = eq(io.in.a.bits.param, param) node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(_T_1651, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1651, UInt<1>(0h1), "") : assert_88 node _T_1655 = eq(io.in.a.bits.size, size) node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(_T_1655, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1655, UInt<1>(0h1), "") : assert_89 node _T_1659 = eq(io.in.a.bits.source, source) node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(_T_1659, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1659, UInt<1>(0h1), "") : assert_90 node _T_1663 = eq(io.in.a.bits.address, address) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_91 node _T_1667 = and(io.in.a.ready, io.in.a.valid) node _T_1668 = and(_T_1667, a_first) when _T_1668 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1669 = eq(d_first, UInt<1>(0h0)) node _T_1670 = and(io.in.d.valid, _T_1669) when _T_1670 : node _T_1671 = eq(io.in.d.bits.opcode, opcode_1) node _T_1672 = asUInt(reset) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(_T_1671, UInt<1>(0h0)) when _T_1674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1671, UInt<1>(0h1), "") : assert_92 node _T_1675 = eq(io.in.d.bits.param, param_1) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_93 node _T_1679 = eq(io.in.d.bits.size, size_1) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_94 node _T_1683 = eq(io.in.d.bits.source, source_1) node _T_1684 = asUInt(reset) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(_T_1683, UInt<1>(0h0)) when _T_1686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1683, UInt<1>(0h1), "") : assert_95 node _T_1687 = eq(io.in.d.bits.sink, sink) node _T_1688 = asUInt(reset) node _T_1689 = eq(_T_1688, UInt<1>(0h0)) when _T_1689 : node _T_1690 = eq(_T_1687, UInt<1>(0h0)) when _T_1690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1687, UInt<1>(0h1), "") : assert_96 node _T_1691 = eq(io.in.d.bits.denied, denied) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_97 node _T_1695 = and(io.in.d.ready, io.in.d.valid) node _T_1696 = and(_T_1695, d_first) when _T_1696 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1697 = and(io.in.a.valid, a_first_1) node _T_1698 = and(_T_1697, UInt<1>(0h1)) when _T_1698 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1699 = and(io.in.a.ready, io.in.a.valid) node _T_1700 = and(_T_1699, a_first_1) node _T_1701 = and(_T_1700, UInt<1>(0h1)) when _T_1701 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1702 = dshr(inflight, io.in.a.bits.source) node _T_1703 = bits(_T_1702, 0, 0) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1708 = and(io.in.d.valid, d_first_1) node _T_1709 = and(_T_1708, UInt<1>(0h1)) node _T_1710 = eq(d_release_ack, UInt<1>(0h0)) node _T_1711 = and(_T_1709, _T_1710) when _T_1711 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1712 = and(io.in.d.ready, io.in.d.valid) node _T_1713 = and(_T_1712, d_first_1) node _T_1714 = and(_T_1713, UInt<1>(0h1)) node _T_1715 = eq(d_release_ack, UInt<1>(0h0)) node _T_1716 = and(_T_1714, _T_1715) when _T_1716 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1717 = and(io.in.d.valid, d_first_1) node _T_1718 = and(_T_1717, UInt<1>(0h1)) node _T_1719 = eq(d_release_ack, UInt<1>(0h0)) node _T_1720 = and(_T_1718, _T_1719) when _T_1720 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1721 = dshr(inflight, io.in.d.bits.source) node _T_1722 = bits(_T_1721, 0, 0) node _T_1723 = or(_T_1722, same_cycle_resp) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1727 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1728 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1729 = or(_T_1727, _T_1728) node _T_1730 = asUInt(reset) node _T_1731 = eq(_T_1730, UInt<1>(0h0)) when _T_1731 : node _T_1732 = eq(_T_1729, UInt<1>(0h0)) when _T_1732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1729, UInt<1>(0h1), "") : assert_100 node _T_1733 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1734 = asUInt(reset) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) when _T_1735 : node _T_1736 = eq(_T_1733, UInt<1>(0h0)) when _T_1736 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1733, UInt<1>(0h1), "") : assert_101 else : node _T_1737 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1738 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1739 = or(_T_1737, _T_1738) node _T_1740 = asUInt(reset) node _T_1741 = eq(_T_1740, UInt<1>(0h0)) when _T_1741 : node _T_1742 = eq(_T_1739, UInt<1>(0h0)) when _T_1742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1739, UInt<1>(0h1), "") : assert_102 node _T_1743 = eq(io.in.d.bits.size, a_size_lookup) node _T_1744 = asUInt(reset) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) when _T_1745 : node _T_1746 = eq(_T_1743, UInt<1>(0h0)) when _T_1746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1743, UInt<1>(0h1), "") : assert_103 node _T_1747 = and(io.in.d.valid, d_first_1) node _T_1748 = and(_T_1747, a_first_1) node _T_1749 = and(_T_1748, io.in.a.valid) node _T_1750 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1751 = and(_T_1749, _T_1750) node _T_1752 = eq(d_release_ack, UInt<1>(0h0)) node _T_1753 = and(_T_1751, _T_1752) when _T_1753 : node _T_1754 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1755 = or(_T_1754, io.in.a.ready) node _T_1756 = asUInt(reset) node _T_1757 = eq(_T_1756, UInt<1>(0h0)) when _T_1757 : node _T_1758 = eq(_T_1755, UInt<1>(0h0)) when _T_1758 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1755, UInt<1>(0h1), "") : assert_104 node _T_1759 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1760 = orr(a_set_wo_ready) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = or(_T_1759, _T_1761) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_78 node _T_1766 = orr(inflight) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) node _T_1768 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1769 = or(_T_1767, _T_1768) node _T_1770 = lt(watchdog, plusarg_reader.out) node _T_1771 = or(_T_1769, _T_1770) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1775 = and(io.in.a.ready, io.in.a.valid) node _T_1776 = and(io.in.d.ready, io.in.d.valid) node _T_1777 = or(_T_1775, _T_1776) when _T_1777 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1778 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1779 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1780 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1781 = and(_T_1779, _T_1780) node _T_1782 = and(_T_1778, _T_1781) when _T_1782 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1783 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1784 = and(_T_1783, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1785 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1786 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = and(_T_1784, _T_1787) when _T_1788 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1789 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1790 = bits(_T_1789, 0, 0) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1795 = and(io.in.d.valid, d_first_2) node _T_1796 = and(_T_1795, UInt<1>(0h1)) node _T_1797 = and(_T_1796, d_release_ack_1) when _T_1797 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1798 = and(io.in.d.ready, io.in.d.valid) node _T_1799 = and(_T_1798, d_first_2) node _T_1800 = and(_T_1799, UInt<1>(0h1)) node _T_1801 = and(_T_1800, d_release_ack_1) when _T_1801 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1802 = and(io.in.d.valid, d_first_2) node _T_1803 = and(_T_1802, UInt<1>(0h1)) node _T_1804 = and(_T_1803, d_release_ack_1) when _T_1804 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1805 = dshr(inflight_1, io.in.d.bits.source) node _T_1806 = bits(_T_1805, 0, 0) node _T_1807 = or(_T_1806, same_cycle_resp_1) node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(_T_1807, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1807, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1811 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1812 = asUInt(reset) node _T_1813 = eq(_T_1812, UInt<1>(0h0)) when _T_1813 : node _T_1814 = eq(_T_1811, UInt<1>(0h0)) when _T_1814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1811, UInt<1>(0h1), "") : assert_109 else : node _T_1815 = eq(io.in.d.bits.size, c_size_lookup) node _T_1816 = asUInt(reset) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) when _T_1817 : node _T_1818 = eq(_T_1815, UInt<1>(0h0)) when _T_1818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1815, UInt<1>(0h1), "") : assert_110 node _T_1819 = and(io.in.d.valid, d_first_2) node _T_1820 = and(_T_1819, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1821 = and(_T_1820, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1822 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = and(_T_1823, d_release_ack_1) node _T_1825 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1826 = and(_T_1824, _T_1825) when _T_1826 : node _T_1827 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1828 = or(_T_1827, _WIRE_27.ready) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_111 node _T_1832 = orr(c_set_wo_ready) when _T_1832 : node _T_1833 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1834 = asUInt(reset) node _T_1835 = eq(_T_1834, UInt<1>(0h0)) when _T_1835 : node _T_1836 = eq(_T_1833, UInt<1>(0h0)) when _T_1836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1833, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_79 node _T_1837 = orr(inflight_1) node _T_1838 = eq(_T_1837, UInt<1>(0h0)) node _T_1839 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1840 = or(_T_1838, _T_1839) node _T_1841 = lt(watchdog_1, plusarg_reader_1.out) node _T_1842 = or(_T_1840, _T_1841) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1846 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1847 = and(io.in.d.ready, io.in.d.valid) node _T_1848 = or(_T_1846, _T_1847) when _T_1848 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module BranchPredictor : input clock : Clock input reset : Reset output io : { flip f0_req : { valid : UInt<1>, bits : { pc : UInt<40>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}}}, resp : { f1 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]}, f2 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]}, f3 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[8], meta : UInt<120>[2], lhist : UInt<1>[2]}}, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<8>, pc : UInt<40>, br_mask : UInt<8>, cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[2], target : UInt<40>, meta : UInt<120>[2]}}} inst banked_predictors_0 of ComposedBranchPredictorBank connect banked_predictors_0.clock, clock connect banked_predictors_0.reset, reset inst banked_predictors_1 of ComposedBranchPredictorBank_1 connect banked_predictors_1.clock, clock connect banked_predictors_1.reset, reset inst banked_lhist_providers_0 of NullLocalBranchPredictorBank connect banked_lhist_providers_0.clock, clock connect banked_lhist_providers_0.reset, reset inst banked_lhist_providers_1 of NullLocalBranchPredictorBank_1 connect banked_lhist_providers_1.clock, clock connect banked_lhist_providers_1.reset, reset wire _banked_predictors_0_io_resp_in_0_WIRE : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]} connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br, UInt<1>(0h0) connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken, UInt<1>(0h0) connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal connect banked_predictors_0.io.resp_in[0].f3[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br connect banked_predictors_0.io.resp_in[0].f3[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal connect banked_predictors_0.io.resp_in[0].f3[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br connect banked_predictors_0.io.resp_in[0].f3[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal connect banked_predictors_0.io.resp_in[0].f3[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br connect banked_predictors_0.io.resp_in[0].f3[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f3[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal connect banked_predictors_0.io.resp_in[0].f3[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br connect banked_predictors_0.io.resp_in[0].f3[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal connect banked_predictors_0.io.resp_in[0].f2[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br connect banked_predictors_0.io.resp_in[0].f2[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal connect banked_predictors_0.io.resp_in[0].f2[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br connect banked_predictors_0.io.resp_in[0].f2[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal connect banked_predictors_0.io.resp_in[0].f2[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br connect banked_predictors_0.io.resp_in[0].f2[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f2[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal connect banked_predictors_0.io.resp_in[0].f2[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br connect banked_predictors_0.io.resp_in[0].f2[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal connect banked_predictors_0.io.resp_in[0].f1[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br connect banked_predictors_0.io.resp_in[0].f1[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal connect banked_predictors_0.io.resp_in[0].f1[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br connect banked_predictors_0.io.resp_in[0].f1[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal connect banked_predictors_0.io.resp_in[0].f1[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br connect banked_predictors_0.io.resp_in[0].f1[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid connect banked_predictors_0.io.resp_in[0].f1[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal connect banked_predictors_0.io.resp_in[0].f1[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br connect banked_predictors_0.io.resp_in[0].f1[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken wire _banked_predictors_1_io_resp_in_0_WIRE : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]} connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[0].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[1].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[2].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f3[3].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[0].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[1].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[2].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f2[3].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[0].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[1].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[2].taken, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.bits, UInt<40>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.valid, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_jal, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_br, UInt<1>(0h0) connect _banked_predictors_1_io_resp_in_0_WIRE.f1[3].taken, UInt<1>(0h0) connect banked_predictors_1.io.resp_in[0].f3[0].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[0].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[0].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_jal connect banked_predictors_1.io.resp_in[0].f3[0].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].is_br connect banked_predictors_1.io.resp_in[0].f3[0].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[0].taken connect banked_predictors_1.io.resp_in[0].f3[1].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[1].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[1].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_jal connect banked_predictors_1.io.resp_in[0].f3[1].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].is_br connect banked_predictors_1.io.resp_in[0].f3[1].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[1].taken connect banked_predictors_1.io.resp_in[0].f3[2].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[2].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[2].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_jal connect banked_predictors_1.io.resp_in[0].f3[2].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].is_br connect banked_predictors_1.io.resp_in[0].f3[2].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[2].taken connect banked_predictors_1.io.resp_in[0].f3[3].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f3[3].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f3[3].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_jal connect banked_predictors_1.io.resp_in[0].f3[3].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].is_br connect banked_predictors_1.io.resp_in[0].f3[3].taken, _banked_predictors_1_io_resp_in_0_WIRE.f3[3].taken connect banked_predictors_1.io.resp_in[0].f2[0].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[0].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[0].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_jal connect banked_predictors_1.io.resp_in[0].f2[0].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].is_br connect banked_predictors_1.io.resp_in[0].f2[0].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[0].taken connect banked_predictors_1.io.resp_in[0].f2[1].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[1].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[1].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_jal connect banked_predictors_1.io.resp_in[0].f2[1].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].is_br connect banked_predictors_1.io.resp_in[0].f2[1].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[1].taken connect banked_predictors_1.io.resp_in[0].f2[2].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[2].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[2].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_jal connect banked_predictors_1.io.resp_in[0].f2[2].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].is_br connect banked_predictors_1.io.resp_in[0].f2[2].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[2].taken connect banked_predictors_1.io.resp_in[0].f2[3].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f2[3].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f2[3].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_jal connect banked_predictors_1.io.resp_in[0].f2[3].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].is_br connect banked_predictors_1.io.resp_in[0].f2[3].taken, _banked_predictors_1_io_resp_in_0_WIRE.f2[3].taken connect banked_predictors_1.io.resp_in[0].f1[0].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[0].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[0].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_jal connect banked_predictors_1.io.resp_in[0].f1[0].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].is_br connect banked_predictors_1.io.resp_in[0].f1[0].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[0].taken connect banked_predictors_1.io.resp_in[0].f1[1].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[1].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[1].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_jal connect banked_predictors_1.io.resp_in[0].f1[1].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].is_br connect banked_predictors_1.io.resp_in[0].f1[1].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[1].taken connect banked_predictors_1.io.resp_in[0].f1[2].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[2].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[2].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_jal connect banked_predictors_1.io.resp_in[0].f1[2].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].is_br connect banked_predictors_1.io.resp_in[0].f1[2].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[2].taken connect banked_predictors_1.io.resp_in[0].f1[3].predicted_pc.bits, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.bits connect banked_predictors_1.io.resp_in[0].f1[3].predicted_pc.valid, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].predicted_pc.valid connect banked_predictors_1.io.resp_in[0].f1[3].is_jal, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_jal connect banked_predictors_1.io.resp_in[0].f1[3].is_br, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].is_br connect banked_predictors_1.io.resp_in[0].f1[3].taken, _banked_predictors_1_io_resp_in_0_WIRE.f1[3].taken connect banked_predictors_0.io.f1_lhist, banked_lhist_providers_0.io.f1_lhist connect banked_predictors_1.io.f1_lhist, banked_lhist_providers_1.io.f1_lhist node _T = bits(io.f0_req.bits.pc, 3, 3) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : connect banked_lhist_providers_0.io.f0_valid, io.f0_req.valid node _banked_lhist_providers_0_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_lhist_providers_0_io_f0_pc_T_1 = or(_banked_lhist_providers_0_io_f0_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_0_io_f0_pc_T_2 = not(_banked_lhist_providers_0_io_f0_pc_T_1) connect banked_lhist_providers_0.io.f0_pc, _banked_lhist_providers_0_io_f0_pc_T_2 connect banked_lhist_providers_1.io.f0_valid, io.f0_req.valid node _banked_lhist_providers_1_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_lhist_providers_1_io_f0_pc_T_1 = or(_banked_lhist_providers_1_io_f0_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_1_io_f0_pc_T_2 = not(_banked_lhist_providers_1_io_f0_pc_T_1) node _banked_lhist_providers_1_io_f0_pc_T_3 = add(_banked_lhist_providers_1_io_f0_pc_T_2, UInt<4>(0h8)) node _banked_lhist_providers_1_io_f0_pc_T_4 = tail(_banked_lhist_providers_1_io_f0_pc_T_3, 1) connect banked_lhist_providers_1.io.f0_pc, _banked_lhist_providers_1_io_f0_pc_T_4 connect banked_predictors_0.io.f0_valid, io.f0_req.valid connect banked_predictors_0.io.f0_pc, io.f0_req.bits.pc node banked_predictors_0_io_f0_mask_idx = bits(io.f0_req.bits.pc, 3, 1) node banked_predictors_0_io_f0_mask_shamt = bits(banked_predictors_0_io_f0_mask_idx, 1, 0) node _banked_predictors_0_io_f0_mask_end_mask_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_predictors_0_io_f0_mask_end_mask_T_1 = eq(_banked_predictors_0_io_f0_mask_end_mask_T, UInt<3>(0h7)) node _banked_predictors_0_io_f0_mask_end_mask_T_2 = and(UInt<1>(0h1), _banked_predictors_0_io_f0_mask_end_mask_T_1) node _banked_predictors_0_io_f0_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _banked_predictors_0_io_f0_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node banked_predictors_0_io_f0_mask_end_mask = mux(_banked_predictors_0_io_f0_mask_end_mask_T_2, _banked_predictors_0_io_f0_mask_end_mask_T_3, _banked_predictors_0_io_f0_mask_end_mask_T_4) node _banked_predictors_0_io_f0_mask_T = dshl(UInt<8>(0hff), banked_predictors_0_io_f0_mask_shamt) node _banked_predictors_0_io_f0_mask_T_1 = and(_banked_predictors_0_io_f0_mask_T, banked_predictors_0_io_f0_mask_end_mask) connect banked_predictors_0.io.f0_mask, _banked_predictors_0_io_f0_mask_T_1 connect banked_predictors_1.io.f0_valid, io.f0_req.valid node _banked_predictors_1_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_predictors_1_io_f0_pc_T_1 = or(_banked_predictors_1_io_f0_pc_T, UInt<3>(0h7)) node _banked_predictors_1_io_f0_pc_T_2 = not(_banked_predictors_1_io_f0_pc_T_1) node _banked_predictors_1_io_f0_pc_T_3 = add(_banked_predictors_1_io_f0_pc_T_2, UInt<4>(0h8)) node _banked_predictors_1_io_f0_pc_T_4 = tail(_banked_predictors_1_io_f0_pc_T_3, 1) connect banked_predictors_1.io.f0_pc, _banked_predictors_1_io_f0_pc_T_4 node _banked_predictors_1_io_f0_mask_T = not(UInt<4>(0h0)) connect banked_predictors_1.io.f0_mask, _banked_predictors_1_io_f0_mask_T else : node _banked_lhist_providers_0_io_f0_valid_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_lhist_providers_0_io_f0_valid_T_1 = eq(_banked_lhist_providers_0_io_f0_valid_T, UInt<3>(0h7)) node _banked_lhist_providers_0_io_f0_valid_T_2 = and(UInt<1>(0h1), _banked_lhist_providers_0_io_f0_valid_T_1) node _banked_lhist_providers_0_io_f0_valid_T_3 = eq(_banked_lhist_providers_0_io_f0_valid_T_2, UInt<1>(0h0)) node _banked_lhist_providers_0_io_f0_valid_T_4 = and(io.f0_req.valid, _banked_lhist_providers_0_io_f0_valid_T_3) connect banked_lhist_providers_0.io.f0_valid, _banked_lhist_providers_0_io_f0_valid_T_4 node _banked_lhist_providers_0_io_f0_pc_T_3 = not(io.f0_req.bits.pc) node _banked_lhist_providers_0_io_f0_pc_T_4 = or(_banked_lhist_providers_0_io_f0_pc_T_3, UInt<3>(0h7)) node _banked_lhist_providers_0_io_f0_pc_T_5 = not(_banked_lhist_providers_0_io_f0_pc_T_4) node _banked_lhist_providers_0_io_f0_pc_T_6 = add(_banked_lhist_providers_0_io_f0_pc_T_5, UInt<4>(0h8)) node _banked_lhist_providers_0_io_f0_pc_T_7 = tail(_banked_lhist_providers_0_io_f0_pc_T_6, 1) connect banked_lhist_providers_0.io.f0_pc, _banked_lhist_providers_0_io_f0_pc_T_7 connect banked_lhist_providers_1.io.f0_valid, io.f0_req.valid node _banked_lhist_providers_1_io_f0_pc_T_5 = not(io.f0_req.bits.pc) node _banked_lhist_providers_1_io_f0_pc_T_6 = or(_banked_lhist_providers_1_io_f0_pc_T_5, UInt<3>(0h7)) node _banked_lhist_providers_1_io_f0_pc_T_7 = not(_banked_lhist_providers_1_io_f0_pc_T_6) connect banked_lhist_providers_1.io.f0_pc, _banked_lhist_providers_1_io_f0_pc_T_7 node _banked_predictors_0_io_f0_valid_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_predictors_0_io_f0_valid_T_1 = eq(_banked_predictors_0_io_f0_valid_T, UInt<3>(0h7)) node _banked_predictors_0_io_f0_valid_T_2 = and(UInt<1>(0h1), _banked_predictors_0_io_f0_valid_T_1) node _banked_predictors_0_io_f0_valid_T_3 = eq(_banked_predictors_0_io_f0_valid_T_2, UInt<1>(0h0)) node _banked_predictors_0_io_f0_valid_T_4 = and(io.f0_req.valid, _banked_predictors_0_io_f0_valid_T_3) connect banked_predictors_0.io.f0_valid, _banked_predictors_0_io_f0_valid_T_4 node _banked_predictors_0_io_f0_pc_T = not(io.f0_req.bits.pc) node _banked_predictors_0_io_f0_pc_T_1 = or(_banked_predictors_0_io_f0_pc_T, UInt<3>(0h7)) node _banked_predictors_0_io_f0_pc_T_2 = not(_banked_predictors_0_io_f0_pc_T_1) node _banked_predictors_0_io_f0_pc_T_3 = add(_banked_predictors_0_io_f0_pc_T_2, UInt<4>(0h8)) node _banked_predictors_0_io_f0_pc_T_4 = tail(_banked_predictors_0_io_f0_pc_T_3, 1) connect banked_predictors_0.io.f0_pc, _banked_predictors_0_io_f0_pc_T_4 node _banked_predictors_0_io_f0_mask_T_2 = not(UInt<4>(0h0)) connect banked_predictors_0.io.f0_mask, _banked_predictors_0_io_f0_mask_T_2 connect banked_predictors_1.io.f0_valid, io.f0_req.valid connect banked_predictors_1.io.f0_pc, io.f0_req.bits.pc node banked_predictors_1_io_f0_mask_idx = bits(io.f0_req.bits.pc, 3, 1) node banked_predictors_1_io_f0_mask_shamt = bits(banked_predictors_1_io_f0_mask_idx, 1, 0) node _banked_predictors_1_io_f0_mask_end_mask_T = bits(io.f0_req.bits.pc, 5, 3) node _banked_predictors_1_io_f0_mask_end_mask_T_1 = eq(_banked_predictors_1_io_f0_mask_end_mask_T, UInt<3>(0h7)) node _banked_predictors_1_io_f0_mask_end_mask_T_2 = and(UInt<1>(0h1), _banked_predictors_1_io_f0_mask_end_mask_T_1) node _banked_predictors_1_io_f0_mask_end_mask_T_3 = mux(UInt<1>(0h1), UInt<4>(0hf), UInt<4>(0h0)) node _banked_predictors_1_io_f0_mask_end_mask_T_4 = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) node banked_predictors_1_io_f0_mask_end_mask = mux(_banked_predictors_1_io_f0_mask_end_mask_T_2, _banked_predictors_1_io_f0_mask_end_mask_T_3, _banked_predictors_1_io_f0_mask_end_mask_T_4) node _banked_predictors_1_io_f0_mask_T_1 = dshl(UInt<8>(0hff), banked_predictors_1_io_f0_mask_shamt) node _banked_predictors_1_io_f0_mask_T_2 = and(_banked_predictors_1_io_f0_mask_T_1, banked_predictors_1_io_f0_mask_end_mask) connect banked_predictors_1.io.f0_mask, _banked_predictors_1_io_f0_mask_T_2 node _T_2 = bits(io.f0_req.bits.pc, 3, 3) node _T_3 = eq(_T_2, UInt<1>(0h0)) reg REG : UInt<1>, clock connect REG, _T_3 when REG : reg banked_predictors_0_io_f1_ghist_REG : UInt, clock connect banked_predictors_0_io_f1_ghist_REG, io.f0_req.bits.ghist.old_history connect banked_predictors_0.io.f1_ghist, banked_predictors_0_io_f1_ghist_REG node _banked_predictors_1_io_f1_ghist_T = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_1_io_f1_ghist_T_1 = or(_banked_predictors_1_io_f1_ghist_T, UInt<1>(0h1)) node _banked_predictors_1_io_f1_ghist_T_2 = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_1_io_f1_ghist_T_3 = mux(io.f0_req.bits.ghist.new_saw_branch_not_taken, _banked_predictors_1_io_f1_ghist_T_2, io.f0_req.bits.ghist.old_history) node _banked_predictors_1_io_f1_ghist_T_4 = mux(io.f0_req.bits.ghist.new_saw_branch_taken, _banked_predictors_1_io_f1_ghist_T_1, _banked_predictors_1_io_f1_ghist_T_3) reg banked_predictors_1_io_f1_ghist_REG : UInt, clock connect banked_predictors_1_io_f1_ghist_REG, _banked_predictors_1_io_f1_ghist_T_4 connect banked_predictors_1.io.f1_ghist, banked_predictors_1_io_f1_ghist_REG else : node _banked_predictors_0_io_f1_ghist_T = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_0_io_f1_ghist_T_1 = or(_banked_predictors_0_io_f1_ghist_T, UInt<1>(0h1)) node _banked_predictors_0_io_f1_ghist_T_2 = shl(io.f0_req.bits.ghist.old_history, 1) node _banked_predictors_0_io_f1_ghist_T_3 = mux(io.f0_req.bits.ghist.new_saw_branch_not_taken, _banked_predictors_0_io_f1_ghist_T_2, io.f0_req.bits.ghist.old_history) node _banked_predictors_0_io_f1_ghist_T_4 = mux(io.f0_req.bits.ghist.new_saw_branch_taken, _banked_predictors_0_io_f1_ghist_T_1, _banked_predictors_0_io_f1_ghist_T_3) reg banked_predictors_0_io_f1_ghist_REG_1 : UInt, clock connect banked_predictors_0_io_f1_ghist_REG_1, _banked_predictors_0_io_f1_ghist_T_4 connect banked_predictors_0.io.f1_ghist, banked_predictors_0_io_f1_ghist_REG_1 reg banked_predictors_1_io_f1_ghist_REG_1 : UInt, clock connect banked_predictors_1_io_f1_ghist_REG_1, io.f0_req.bits.ghist.old_history connect banked_predictors_1.io.f1_ghist, banked_predictors_1_io_f1_ghist_REG_1 node _banked_lhist_providers_0_io_f3_taken_br_T = and(banked_predictors_0.io.resp.f3[0].is_br, banked_predictors_0.io.resp.f3[0].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_1 = and(_banked_lhist_providers_0_io_f3_taken_br_T, banked_predictors_0.io.resp.f3[0].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_2 = and(banked_predictors_0.io.resp.f3[1].is_br, banked_predictors_0.io.resp.f3[1].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_3 = and(_banked_lhist_providers_0_io_f3_taken_br_T_2, banked_predictors_0.io.resp.f3[1].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_4 = and(banked_predictors_0.io.resp.f3[2].is_br, banked_predictors_0.io.resp.f3[2].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_5 = and(_banked_lhist_providers_0_io_f3_taken_br_T_4, banked_predictors_0.io.resp.f3[2].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_6 = and(banked_predictors_0.io.resp.f3[3].is_br, banked_predictors_0.io.resp.f3[3].predicted_pc.valid) node _banked_lhist_providers_0_io_f3_taken_br_T_7 = and(_banked_lhist_providers_0_io_f3_taken_br_T_6, banked_predictors_0.io.resp.f3[3].taken) node _banked_lhist_providers_0_io_f3_taken_br_T_8 = or(_banked_lhist_providers_0_io_f3_taken_br_T_1, _banked_lhist_providers_0_io_f3_taken_br_T_3) node _banked_lhist_providers_0_io_f3_taken_br_T_9 = or(_banked_lhist_providers_0_io_f3_taken_br_T_8, _banked_lhist_providers_0_io_f3_taken_br_T_5) node _banked_lhist_providers_0_io_f3_taken_br_T_10 = or(_banked_lhist_providers_0_io_f3_taken_br_T_9, _banked_lhist_providers_0_io_f3_taken_br_T_7) connect banked_lhist_providers_0.io.f3_taken_br, _banked_lhist_providers_0_io_f3_taken_br_T_10 node _banked_lhist_providers_1_io_f3_taken_br_T = and(banked_predictors_1.io.resp.f3[0].is_br, banked_predictors_1.io.resp.f3[0].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_1 = and(_banked_lhist_providers_1_io_f3_taken_br_T, banked_predictors_1.io.resp.f3[0].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_2 = and(banked_predictors_1.io.resp.f3[1].is_br, banked_predictors_1.io.resp.f3[1].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_3 = and(_banked_lhist_providers_1_io_f3_taken_br_T_2, banked_predictors_1.io.resp.f3[1].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_4 = and(banked_predictors_1.io.resp.f3[2].is_br, banked_predictors_1.io.resp.f3[2].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_5 = and(_banked_lhist_providers_1_io_f3_taken_br_T_4, banked_predictors_1.io.resp.f3[2].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_6 = and(banked_predictors_1.io.resp.f3[3].is_br, banked_predictors_1.io.resp.f3[3].predicted_pc.valid) node _banked_lhist_providers_1_io_f3_taken_br_T_7 = and(_banked_lhist_providers_1_io_f3_taken_br_T_6, banked_predictors_1.io.resp.f3[3].taken) node _banked_lhist_providers_1_io_f3_taken_br_T_8 = or(_banked_lhist_providers_1_io_f3_taken_br_T_1, _banked_lhist_providers_1_io_f3_taken_br_T_3) node _banked_lhist_providers_1_io_f3_taken_br_T_9 = or(_banked_lhist_providers_1_io_f3_taken_br_T_8, _banked_lhist_providers_1_io_f3_taken_br_T_5) node _banked_lhist_providers_1_io_f3_taken_br_T_10 = or(_banked_lhist_providers_1_io_f3_taken_br_T_9, _banked_lhist_providers_1_io_f3_taken_br_T_7) connect banked_lhist_providers_1.io.f3_taken_br, _banked_lhist_providers_1_io_f3_taken_br_T_10 reg b0_fire_REG : UInt<1>, clock connect b0_fire_REG, banked_predictors_0.io.f0_valid reg b0_fire_REG_1 : UInt<1>, clock connect b0_fire_REG_1, b0_fire_REG reg b0_fire_REG_2 : UInt<1>, clock connect b0_fire_REG_2, b0_fire_REG_1 node b0_fire = and(io.f3_fire, b0_fire_REG_2) reg b1_fire_REG : UInt<1>, clock connect b1_fire_REG, banked_predictors_1.io.f0_valid reg b1_fire_REG_1 : UInt<1>, clock connect b1_fire_REG_1, b1_fire_REG reg b1_fire_REG_2 : UInt<1>, clock connect b1_fire_REG_2, b1_fire_REG_1 node b1_fire = and(io.f3_fire, b1_fire_REG_2) connect banked_predictors_0.io.f3_fire, b0_fire connect banked_predictors_1.io.f3_fire, b1_fire connect banked_lhist_providers_0.io.f3_fire, b0_fire connect banked_lhist_providers_1.io.f3_fire, b1_fire connect io.resp.f3.meta[0], banked_predictors_0.io.f3_meta connect io.resp.f3.meta[1], banked_predictors_1.io.f3_meta connect io.resp.f3.lhist[0], banked_lhist_providers_0.io.f3_lhist connect io.resp.f3.lhist[1], banked_lhist_providers_1.io.f3_lhist node _T_4 = bits(io.resp.f1.pc, 3, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : connect io.resp.f1.preds[0], banked_predictors_0.io.resp.f1[0] connect io.resp.f1.preds[4], banked_predictors_1.io.resp.f1[0] connect io.resp.f1.preds[1], banked_predictors_0.io.resp.f1[1] connect io.resp.f1.preds[5], banked_predictors_1.io.resp.f1[1] connect io.resp.f1.preds[2], banked_predictors_0.io.resp.f1[2] connect io.resp.f1.preds[6], banked_predictors_1.io.resp.f1[2] connect io.resp.f1.preds[3], banked_predictors_0.io.resp.f1[3] connect io.resp.f1.preds[7], banked_predictors_1.io.resp.f1[3] else : connect io.resp.f1.preds[0], banked_predictors_1.io.resp.f1[0] connect io.resp.f1.preds[4], banked_predictors_0.io.resp.f1[0] connect io.resp.f1.preds[1], banked_predictors_1.io.resp.f1[1] connect io.resp.f1.preds[5], banked_predictors_0.io.resp.f1[1] connect io.resp.f1.preds[2], banked_predictors_1.io.resp.f1[2] connect io.resp.f1.preds[6], banked_predictors_0.io.resp.f1[2] connect io.resp.f1.preds[3], banked_predictors_1.io.resp.f1[3] connect io.resp.f1.preds[7], banked_predictors_0.io.resp.f1[3] node _T_6 = bits(io.resp.f2.pc, 3, 3) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : connect io.resp.f2.preds[0], banked_predictors_0.io.resp.f2[0] connect io.resp.f2.preds[4], banked_predictors_1.io.resp.f2[0] connect io.resp.f2.preds[1], banked_predictors_0.io.resp.f2[1] connect io.resp.f2.preds[5], banked_predictors_1.io.resp.f2[1] connect io.resp.f2.preds[2], banked_predictors_0.io.resp.f2[2] connect io.resp.f2.preds[6], banked_predictors_1.io.resp.f2[2] connect io.resp.f2.preds[3], banked_predictors_0.io.resp.f2[3] connect io.resp.f2.preds[7], banked_predictors_1.io.resp.f2[3] else : connect io.resp.f2.preds[0], banked_predictors_1.io.resp.f2[0] connect io.resp.f2.preds[4], banked_predictors_0.io.resp.f2[0] connect io.resp.f2.preds[1], banked_predictors_1.io.resp.f2[1] connect io.resp.f2.preds[5], banked_predictors_0.io.resp.f2[1] connect io.resp.f2.preds[2], banked_predictors_1.io.resp.f2[2] connect io.resp.f2.preds[6], banked_predictors_0.io.resp.f2[2] connect io.resp.f2.preds[3], banked_predictors_1.io.resp.f2[3] connect io.resp.f2.preds[7], banked_predictors_0.io.resp.f2[3] node _T_8 = bits(io.resp.f3.pc, 3, 3) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : connect io.resp.f3.preds[0], banked_predictors_0.io.resp.f3[0] connect io.resp.f3.preds[4], banked_predictors_1.io.resp.f3[0] connect io.resp.f3.preds[1], banked_predictors_0.io.resp.f3[1] connect io.resp.f3.preds[5], banked_predictors_1.io.resp.f3[1] connect io.resp.f3.preds[2], banked_predictors_0.io.resp.f3[2] connect io.resp.f3.preds[6], banked_predictors_1.io.resp.f3[2] connect io.resp.f3.preds[3], banked_predictors_0.io.resp.f3[3] connect io.resp.f3.preds[7], banked_predictors_1.io.resp.f3[3] else : connect io.resp.f3.preds[0], banked_predictors_1.io.resp.f3[0] connect io.resp.f3.preds[4], banked_predictors_0.io.resp.f3[0] connect io.resp.f3.preds[1], banked_predictors_1.io.resp.f3[1] connect io.resp.f3.preds[5], banked_predictors_0.io.resp.f3[1] connect io.resp.f3.preds[2], banked_predictors_1.io.resp.f3[2] connect io.resp.f3.preds[6], banked_predictors_0.io.resp.f3[2] connect io.resp.f3.preds[3], banked_predictors_1.io.resp.f3[3] connect io.resp.f3.preds[7], banked_predictors_0.io.resp.f3[3] reg io_resp_f1_pc_REG : UInt, clock connect io_resp_f1_pc_REG, io.f0_req.bits.pc connect io.resp.f1.pc, io_resp_f1_pc_REG reg io_resp_f2_pc_REG : UInt, clock connect io_resp_f2_pc_REG, io.resp.f1.pc connect io.resp.f2.pc, io_resp_f2_pc_REG reg io_resp_f3_pc_REG : UInt, clock connect io_resp_f3_pc_REG, io.resp.f2.pc connect io.resp.f3.pc, io_resp_f3_pc_REG invalidate io.resp.f1.meta[0] invalidate io.resp.f1.meta[1] invalidate io.resp.f2.meta[0] invalidate io.resp.f2.meta[1] invalidate io.resp.f1.lhist[0] invalidate io.resp.f1.lhist[1] invalidate io.resp.f2.lhist[0] invalidate io.resp.f2.lhist[1] connect banked_predictors_0.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect banked_predictors_0.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect banked_predictors_0.io.update.bits.meta, io.update.bits.meta[0] connect banked_predictors_0.io.update.bits.lhist, io.update.bits.lhist[0] connect banked_predictors_0.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect banked_predictors_0.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect banked_predictors_0.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect banked_predictors_0.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect banked_predictors_0.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect banked_predictors_0.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect banked_predictors_0.io.update.bits.target, io.update.bits.target connect banked_lhist_providers_0.io.update.mispredict, io.update.bits.is_mispredict_update connect banked_lhist_providers_0.io.update.repair, io.update.bits.is_repair_update connect banked_lhist_providers_0.io.update.lhist, io.update.bits.lhist[0] connect banked_predictors_1.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect banked_predictors_1.io.update.bits.is_repair_update, io.update.bits.is_repair_update connect banked_predictors_1.io.update.bits.meta, io.update.bits.meta[1] connect banked_predictors_1.io.update.bits.lhist, io.update.bits.lhist[1] connect banked_predictors_1.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect banked_predictors_1.io.update.bits.cfi_taken, io.update.bits.cfi_taken connect banked_predictors_1.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect banked_predictors_1.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br connect banked_predictors_1.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect banked_predictors_1.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect banked_predictors_1.io.update.bits.target, io.update.bits.target connect banked_lhist_providers_1.io.update.mispredict, io.update.bits.is_mispredict_update connect banked_lhist_providers_1.io.update.repair, io.update.bits.is_repair_update connect banked_lhist_providers_1.io.update.lhist, io.update.bits.lhist[1] node _T_10 = bits(io.update.bits.pc, 3, 3) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _b1_update_valid_T = eq(io.update.bits.cfi_idx.valid, UInt<1>(0h0)) node _b1_update_valid_T_1 = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _b1_update_valid_T_2 = or(_b1_update_valid_T, _b1_update_valid_T_1) node b1_update_valid = and(io.update.valid, _b1_update_valid_T_2) node _banked_lhist_providers_0_io_update_valid_T = bits(io.update.bits.br_mask, 3, 0) node _banked_lhist_providers_0_io_update_valid_T_1 = neq(_banked_lhist_providers_0_io_update_valid_T, UInt<1>(0h0)) node _banked_lhist_providers_0_io_update_valid_T_2 = and(io.update.valid, _banked_lhist_providers_0_io_update_valid_T_1) connect banked_lhist_providers_0.io.update.valid, _banked_lhist_providers_0_io_update_valid_T_2 node _banked_lhist_providers_1_io_update_valid_T = bits(io.update.bits.br_mask, 7, 4) node _banked_lhist_providers_1_io_update_valid_T_1 = neq(_banked_lhist_providers_1_io_update_valid_T, UInt<1>(0h0)) node _banked_lhist_providers_1_io_update_valid_T_2 = and(b1_update_valid, _banked_lhist_providers_1_io_update_valid_T_1) connect banked_lhist_providers_1.io.update.valid, _banked_lhist_providers_1_io_update_valid_T_2 node _banked_lhist_providers_0_io_update_pc_T = not(io.update.bits.pc) node _banked_lhist_providers_0_io_update_pc_T_1 = or(_banked_lhist_providers_0_io_update_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_0_io_update_pc_T_2 = not(_banked_lhist_providers_0_io_update_pc_T_1) connect banked_lhist_providers_0.io.update.pc, _banked_lhist_providers_0_io_update_pc_T_2 node _banked_lhist_providers_1_io_update_pc_T = not(io.update.bits.pc) node _banked_lhist_providers_1_io_update_pc_T_1 = or(_banked_lhist_providers_1_io_update_pc_T, UInt<3>(0h7)) node _banked_lhist_providers_1_io_update_pc_T_2 = not(_banked_lhist_providers_1_io_update_pc_T_1) node _banked_lhist_providers_1_io_update_pc_T_3 = add(_banked_lhist_providers_1_io_update_pc_T_2, UInt<4>(0h8)) node _banked_lhist_providers_1_io_update_pc_T_4 = tail(_banked_lhist_providers_1_io_update_pc_T_3, 1) connect banked_lhist_providers_1.io.update.pc, _banked_lhist_providers_1_io_update_pc_T_4 connect banked_predictors_0.io.update.valid, io.update.valid connect banked_predictors_1.io.update.valid, b1_update_valid connect banked_predictors_0.io.update.bits.pc, io.update.bits.pc node _banked_predictors_1_io_update_bits_pc_T = not(io.update.bits.pc) node _banked_predictors_1_io_update_bits_pc_T_1 = or(_banked_predictors_1_io_update_bits_pc_T, UInt<3>(0h7)) node _banked_predictors_1_io_update_bits_pc_T_2 = not(_banked_predictors_1_io_update_bits_pc_T_1) node _banked_predictors_1_io_update_bits_pc_T_3 = add(_banked_predictors_1_io_update_bits_pc_T_2, UInt<4>(0h8)) node _banked_predictors_1_io_update_bits_pc_T_4 = tail(_banked_predictors_1_io_update_bits_pc_T_3, 1) connect banked_predictors_1.io.update.bits.pc, _banked_predictors_1_io_update_bits_pc_T_4 connect banked_predictors_0.io.update.bits.br_mask, io.update.bits.br_mask node _banked_predictors_1_io_update_bits_br_mask_T = shr(io.update.bits.br_mask, 4) connect banked_predictors_1.io.update.bits.br_mask, _banked_predictors_1_io_update_bits_br_mask_T connect banked_predictors_0.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts node _banked_predictors_1_io_update_bits_btb_mispredicts_T = shr(io.update.bits.btb_mispredicts, 4) connect banked_predictors_1.io.update.bits.btb_mispredicts, _banked_predictors_1_io_update_bits_btb_mispredicts_T node _banked_predictors_0_io_update_bits_cfi_idx_valid_T = lt(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_0_io_update_bits_cfi_idx_valid_T_1 = and(io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T) connect banked_predictors_0.io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T_1 node _banked_predictors_1_io_update_bits_cfi_idx_valid_T = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_1_io_update_bits_cfi_idx_valid_T_1 = and(io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T) connect banked_predictors_1.io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T_1 connect banked_predictors_0.io.update.bits.ghist, io.update.bits.ghist.old_history node _banked_predictors_1_io_update_bits_ghist_T = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_1_io_update_bits_ghist_T_1 = or(_banked_predictors_1_io_update_bits_ghist_T, UInt<1>(0h1)) node _banked_predictors_1_io_update_bits_ghist_T_2 = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_1_io_update_bits_ghist_T_3 = mux(io.update.bits.ghist.new_saw_branch_not_taken, _banked_predictors_1_io_update_bits_ghist_T_2, io.update.bits.ghist.old_history) node _banked_predictors_1_io_update_bits_ghist_T_4 = mux(io.update.bits.ghist.new_saw_branch_taken, _banked_predictors_1_io_update_bits_ghist_T_1, _banked_predictors_1_io_update_bits_ghist_T_3) connect banked_predictors_1.io.update.bits.ghist, _banked_predictors_1_io_update_bits_ghist_T_4 else : node _b0_update_valid_T = bits(io.update.bits.pc, 5, 3) node _b0_update_valid_T_1 = eq(_b0_update_valid_T, UInt<3>(0h7)) node _b0_update_valid_T_2 = and(UInt<1>(0h1), _b0_update_valid_T_1) node _b0_update_valid_T_3 = eq(_b0_update_valid_T_2, UInt<1>(0h0)) node _b0_update_valid_T_4 = and(io.update.valid, _b0_update_valid_T_3) node _b0_update_valid_T_5 = eq(io.update.bits.cfi_idx.valid, UInt<1>(0h0)) node _b0_update_valid_T_6 = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _b0_update_valid_T_7 = or(_b0_update_valid_T_5, _b0_update_valid_T_6) node b0_update_valid = and(_b0_update_valid_T_4, _b0_update_valid_T_7) node _banked_lhist_providers_1_io_update_valid_T_3 = bits(io.update.bits.br_mask, 3, 0) node _banked_lhist_providers_1_io_update_valid_T_4 = neq(_banked_lhist_providers_1_io_update_valid_T_3, UInt<1>(0h0)) node _banked_lhist_providers_1_io_update_valid_T_5 = and(io.update.valid, _banked_lhist_providers_1_io_update_valid_T_4) connect banked_lhist_providers_1.io.update.valid, _banked_lhist_providers_1_io_update_valid_T_5 node _banked_lhist_providers_0_io_update_valid_T_3 = bits(io.update.bits.br_mask, 7, 4) node _banked_lhist_providers_0_io_update_valid_T_4 = neq(_banked_lhist_providers_0_io_update_valid_T_3, UInt<1>(0h0)) node _banked_lhist_providers_0_io_update_valid_T_5 = and(b0_update_valid, _banked_lhist_providers_0_io_update_valid_T_4) connect banked_lhist_providers_0.io.update.valid, _banked_lhist_providers_0_io_update_valid_T_5 node _banked_lhist_providers_1_io_update_pc_T_5 = not(io.update.bits.pc) node _banked_lhist_providers_1_io_update_pc_T_6 = or(_banked_lhist_providers_1_io_update_pc_T_5, UInt<3>(0h7)) node _banked_lhist_providers_1_io_update_pc_T_7 = not(_banked_lhist_providers_1_io_update_pc_T_6) connect banked_lhist_providers_1.io.update.pc, _banked_lhist_providers_1_io_update_pc_T_7 node _banked_lhist_providers_0_io_update_pc_T_3 = not(io.update.bits.pc) node _banked_lhist_providers_0_io_update_pc_T_4 = or(_banked_lhist_providers_0_io_update_pc_T_3, UInt<3>(0h7)) node _banked_lhist_providers_0_io_update_pc_T_5 = not(_banked_lhist_providers_0_io_update_pc_T_4) node _banked_lhist_providers_0_io_update_pc_T_6 = add(_banked_lhist_providers_0_io_update_pc_T_5, UInt<4>(0h8)) node _banked_lhist_providers_0_io_update_pc_T_7 = tail(_banked_lhist_providers_0_io_update_pc_T_6, 1) connect banked_lhist_providers_0.io.update.pc, _banked_lhist_providers_0_io_update_pc_T_7 connect banked_predictors_1.io.update.valid, io.update.valid connect banked_predictors_0.io.update.valid, b0_update_valid connect banked_predictors_1.io.update.bits.pc, io.update.bits.pc node _banked_predictors_0_io_update_bits_pc_T = not(io.update.bits.pc) node _banked_predictors_0_io_update_bits_pc_T_1 = or(_banked_predictors_0_io_update_bits_pc_T, UInt<3>(0h7)) node _banked_predictors_0_io_update_bits_pc_T_2 = not(_banked_predictors_0_io_update_bits_pc_T_1) node _banked_predictors_0_io_update_bits_pc_T_3 = add(_banked_predictors_0_io_update_bits_pc_T_2, UInt<4>(0h8)) node _banked_predictors_0_io_update_bits_pc_T_4 = tail(_banked_predictors_0_io_update_bits_pc_T_3, 1) connect banked_predictors_0.io.update.bits.pc, _banked_predictors_0_io_update_bits_pc_T_4 connect banked_predictors_1.io.update.bits.br_mask, io.update.bits.br_mask node _banked_predictors_0_io_update_bits_br_mask_T = shr(io.update.bits.br_mask, 4) connect banked_predictors_0.io.update.bits.br_mask, _banked_predictors_0_io_update_bits_br_mask_T connect banked_predictors_1.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts node _banked_predictors_0_io_update_bits_btb_mispredicts_T = shr(io.update.bits.btb_mispredicts, 4) connect banked_predictors_0.io.update.bits.btb_mispredicts, _banked_predictors_0_io_update_bits_btb_mispredicts_T node _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2 = lt(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_1_io_update_bits_cfi_idx_valid_T_3 = and(io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2) connect banked_predictors_1.io.update.bits.cfi_idx.valid, _banked_predictors_1_io_update_bits_cfi_idx_valid_T_3 node _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2 = geq(io.update.bits.cfi_idx.bits, UInt<3>(0h4)) node _banked_predictors_0_io_update_bits_cfi_idx_valid_T_3 = and(io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2) connect banked_predictors_0.io.update.bits.cfi_idx.valid, _banked_predictors_0_io_update_bits_cfi_idx_valid_T_3 connect banked_predictors_1.io.update.bits.ghist, io.update.bits.ghist.old_history node _banked_predictors_0_io_update_bits_ghist_T = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_0_io_update_bits_ghist_T_1 = or(_banked_predictors_0_io_update_bits_ghist_T, UInt<1>(0h1)) node _banked_predictors_0_io_update_bits_ghist_T_2 = shl(io.update.bits.ghist.old_history, 1) node _banked_predictors_0_io_update_bits_ghist_T_3 = mux(io.update.bits.ghist.new_saw_branch_not_taken, _banked_predictors_0_io_update_bits_ghist_T_2, io.update.bits.ghist.old_history) node _banked_predictors_0_io_update_bits_ghist_T_4 = mux(io.update.bits.ghist.new_saw_branch_taken, _banked_predictors_0_io_update_bits_ghist_T_1, _banked_predictors_0_io_update_bits_ghist_T_3) connect banked_predictors_0.io.update.bits.ghist, _banked_predictors_0_io_update_bits_ghist_T_4 when io.update.valid : node _T_12 = and(io.update.bits.cfi_is_br, io.update.bits.cfi_idx.valid) when _T_12 : node _T_13 = dshr(io.update.bits.br_mask, io.update.bits.cfi_idx.bits) node _T_14 = bits(_T_13, 0, 0) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at predictor.scala:470 assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits))\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert

module BranchPredictor( // @[predictor.scala:196:7] input clock, // @[predictor.scala:196:7] input reset, // @[predictor.scala:196:7] input io_f0_req_valid, // @[predictor.scala:199:14] input [39:0] io_f0_req_bits_pc, // @[predictor.scala:199:14] input [63:0] io_f0_req_bits_ghist_old_history, // @[predictor.scala:199:14] input io_f0_req_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:199:14] input io_f0_req_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:199:14] input io_f0_req_bits_ghist_new_saw_branch_taken, // @[predictor.scala:199:14] input [4:0] io_f0_req_bits_ghist_ras_idx, // @[predictor.scala:199:14] output io_resp_f1_preds_0_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_0_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_0_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_0_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_0_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_1_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_1_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_1_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_1_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_1_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_2_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_2_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_2_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_2_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_2_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_3_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_3_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_3_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_3_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_3_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_4_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_4_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_4_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_4_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_4_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_5_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_5_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_5_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_5_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_5_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_6_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_6_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_6_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_6_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_6_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f1_preds_7_taken, // @[predictor.scala:199:14] output io_resp_f1_preds_7_is_br, // @[predictor.scala:199:14] output io_resp_f1_preds_7_is_jal, // @[predictor.scala:199:14] output io_resp_f1_preds_7_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f1_preds_7_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_0_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_0_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_0_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_0_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_0_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_1_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_1_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_1_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_1_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_1_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_2_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_2_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_2_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_2_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_2_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_3_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_3_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_3_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_3_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_3_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_4_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_4_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_4_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_4_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_4_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_5_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_5_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_5_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_5_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_5_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_6_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_6_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_6_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_6_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_6_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f2_preds_7_taken, // @[predictor.scala:199:14] output io_resp_f2_preds_7_is_br, // @[predictor.scala:199:14] output io_resp_f2_preds_7_is_jal, // @[predictor.scala:199:14] output io_resp_f2_preds_7_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f2_preds_7_predicted_pc_bits, // @[predictor.scala:199:14] output [39:0] io_resp_f3_pc, // @[predictor.scala:199:14] output io_resp_f3_preds_0_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_0_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_0_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_0_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_0_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_1_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_1_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_1_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_1_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_1_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_2_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_2_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_2_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_2_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_2_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_3_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_3_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_3_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_3_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_3_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_4_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_4_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_4_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_4_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_4_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_5_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_5_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_5_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_5_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_5_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_6_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_6_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_6_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_6_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_6_predicted_pc_bits, // @[predictor.scala:199:14] output io_resp_f3_preds_7_taken, // @[predictor.scala:199:14] output io_resp_f3_preds_7_is_br, // @[predictor.scala:199:14] output io_resp_f3_preds_7_is_jal, // @[predictor.scala:199:14] output io_resp_f3_preds_7_predicted_pc_valid, // @[predictor.scala:199:14] output [39:0] io_resp_f3_preds_7_predicted_pc_bits, // @[predictor.scala:199:14] output [119:0] io_resp_f3_meta_0, // @[predictor.scala:199:14] output [119:0] io_resp_f3_meta_1, // @[predictor.scala:199:14] input io_f3_fire, // @[predictor.scala:199:14] input io_update_valid, // @[predictor.scala:199:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:199:14] input io_update_bits_is_repair_update, // @[predictor.scala:199:14] input [7:0] io_update_bits_btb_mispredicts, // @[predictor.scala:199:14] input [39:0] io_update_bits_pc, // @[predictor.scala:199:14] input [7:0] io_update_bits_br_mask, // @[predictor.scala:199:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:199:14] input [2:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:199:14] input io_update_bits_cfi_taken, // @[predictor.scala:199:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:199:14] input io_update_bits_cfi_is_br, // @[predictor.scala:199:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:199:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:199:14] input [63:0] io_update_bits_ghist_old_history, // @[predictor.scala:199:14] input io_update_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:199:14] input io_update_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:199:14] input io_update_bits_ghist_new_saw_branch_taken, // @[predictor.scala:199:14] input [4:0] io_update_bits_ghist_ras_idx, // @[predictor.scala:199:14] input io_update_bits_lhist_0, // @[predictor.scala:199:14] input io_update_bits_lhist_1, // @[predictor.scala:199:14] input [39:0] io_update_bits_target, // @[predictor.scala:199:14] input [119:0] io_update_bits_meta_0, // @[predictor.scala:199:14] input [119:0] io_update_bits_meta_1 // @[predictor.scala:199:14] ); wire _banked_predictors_1_io_resp_f1_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f1_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f1_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f2_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f2_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_1_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_1_io_resp_f3_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f1_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f1_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f2_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f2_3_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_0_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_1_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_2_predicted_pc_bits; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_is_br; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_is_jal; // @[predictor.scala:221:19] wire _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19] wire [39:0] _banked_predictors_0_io_resp_f3_3_predicted_pc_bits; // @[predictor.scala:221:19] wire io_f0_req_valid_0 = io_f0_req_valid; // @[predictor.scala:196:7] wire [39:0] io_f0_req_bits_pc_0 = io_f0_req_bits_pc; // @[predictor.scala:196:7] wire [63:0] io_f0_req_bits_ghist_old_history_0 = io_f0_req_bits_ghist_old_history; // @[predictor.scala:196:7] wire io_f0_req_bits_ghist_current_saw_branch_not_taken_0 = io_f0_req_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_f0_req_bits_ghist_new_saw_branch_not_taken_0 = io_f0_req_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_f0_req_bits_ghist_new_saw_branch_taken_0 = io_f0_req_bits_ghist_new_saw_branch_taken; // @[predictor.scala:196:7] wire [4:0] io_f0_req_bits_ghist_ras_idx_0 = io_f0_req_bits_ghist_ras_idx; // @[predictor.scala:196:7] wire io_f3_fire_0 = io_f3_fire; // @[predictor.scala:196:7] wire io_update_valid_0 = io_update_valid; // @[predictor.scala:196:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[predictor.scala:196:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[predictor.scala:196:7] wire [7:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[predictor.scala:196:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[predictor.scala:196:7] wire [7:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[predictor.scala:196:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[predictor.scala:196:7] wire [2:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[predictor.scala:196:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[predictor.scala:196:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[predictor.scala:196:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[predictor.scala:196:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[predictor.scala:196:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[predictor.scala:196:7] wire [63:0] io_update_bits_ghist_old_history_0 = io_update_bits_ghist_old_history; // @[predictor.scala:196:7] wire io_update_bits_ghist_current_saw_branch_not_taken_0 = io_update_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_update_bits_ghist_new_saw_branch_not_taken_0 = io_update_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:196:7] wire io_update_bits_ghist_new_saw_branch_taken_0 = io_update_bits_ghist_new_saw_branch_taken; // @[predictor.scala:196:7] wire [4:0] io_update_bits_ghist_ras_idx_0 = io_update_bits_ghist_ras_idx; // @[predictor.scala:196:7] wire io_update_bits_lhist_0_0 = io_update_bits_lhist_0; // @[predictor.scala:196:7] wire io_update_bits_lhist_1_0 = io_update_bits_lhist_1; // @[predictor.scala:196:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[predictor.scala:196:7] wire [119:0] io_update_bits_meta_0_0 = io_update_bits_meta_0; // @[predictor.scala:196:7] wire [119:0] io_update_bits_meta_1_0 = io_update_bits_meta_1; // @[predictor.scala:196:7] wire [119:0] io_resp_f1_meta_0 = 120'h0; // @[predictor.scala:196:7] wire [119:0] io_resp_f1_meta_1 = 120'h0; // @[predictor.scala:196:7] wire [119:0] io_resp_f2_meta_0 = 120'h0; // @[predictor.scala:196:7] wire [119:0] io_resp_f2_meta_1 = 120'h0; // @[predictor.scala:196:7] wire io_resp_f1_lhist_0 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f1_lhist_1 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f2_lhist_0 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f2_lhist_1 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f3_lhist_0 = 1'h0; // @[predictor.scala:196:7] wire io_resp_f3_lhist_1 = 1'h0; // @[predictor.scala:196:7] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_taken = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_br = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_jal = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:249:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_taken = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_is_br = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_is_jal = 1'h0; // @[predictor.scala:250:67] wire _banked_predictors_1_io_resp_in_0_WIRE_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:250:67] wire [7:0] _banked_predictors_0_io_f0_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:167:81] wire [7:0] _banked_predictors_1_io_f0_mask_end_mask_T_4 = 8'hFF; // @[frontend.scala:167:81] wire [3:0] _banked_predictors_0_io_f0_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:167:56] wire [3:0] _banked_predictors_1_io_f0_mask_T = 4'hF; // @[predictor.scala:268:43] wire [3:0] _banked_predictors_0_io_f0_mask_T_2 = 4'hF; // @[predictor.scala:278:43] wire [3:0] _banked_predictors_1_io_f0_mask_end_mask_T_3 = 4'hF; // @[frontend.scala:167:56] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:249:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire [39:0] _banked_predictors_1_io_resp_in_0_WIRE_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:250:67] wire io_resp_f1_preds_0_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_0_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_0_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_0_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_0_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_1_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_1_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_2_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_2_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_3_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_3_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_4_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_4_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_5_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_5_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_6_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_6_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_preds_7_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_taken_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_is_br_0; // @[predictor.scala:196:7] wire io_resp_f1_preds_7_is_jal_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f1_pc; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_0_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_0_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_1_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_1_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_2_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_2_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_3_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_3_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_4_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_4_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_5_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_5_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_6_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_6_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_preds_7_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_taken_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_is_br_0; // @[predictor.scala:196:7] wire io_resp_f2_preds_7_is_jal_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f2_pc; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_0_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_0_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_1_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_1_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_2_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_2_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_3_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_3_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_4_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_4_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_5_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_5_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_6_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_6_is_jal_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_predicted_pc_valid_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_preds_7_predicted_pc_bits_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_taken_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_is_br_0; // @[predictor.scala:196:7] wire io_resp_f3_preds_7_is_jal_0; // @[predictor.scala:196:7] wire [119:0] io_resp_f3_meta_0_0; // @[predictor.scala:196:7] wire [119:0] io_resp_f3_meta_1_0; // @[predictor.scala:196:7] wire [39:0] io_resp_f3_pc_0; // @[predictor.scala:196:7] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_1 = {_banked_lhist_providers_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_2 = ~_banked_lhist_providers_0_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_1 = {_banked_lhist_providers_1_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_2 = ~_banked_lhist_providers_1_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_1_io_f0_pc_T_3 = {1'h0, _banked_lhist_providers_1_io_f0_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_4 = _banked_lhist_providers_1_io_f0_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [2:0] banked_predictors_0_io_f0_mask_idx = io_f0_req_bits_pc_0[3:1]; // @[package.scala:163:13] wire [2:0] banked_predictors_1_io_f0_mask_idx = io_f0_req_bits_pc_0[3:1]; // @[package.scala:163:13] wire [1:0] banked_predictors_0_io_f0_mask_shamt = banked_predictors_0_io_f0_mask_idx[1:0]; // @[package.scala:163:13] wire [2:0] _banked_predictors_0_io_f0_mask_end_mask_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire [2:0] _banked_lhist_providers_0_io_f0_valid_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire [2:0] _banked_predictors_0_io_f0_valid_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire [2:0] _banked_predictors_1_io_f0_mask_end_mask_T = io_f0_req_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire _banked_predictors_0_io_f0_mask_end_mask_T_1 = &_banked_predictors_0_io_f0_mask_end_mask_T; // @[frontend.scala:139:{28,66}] wire _banked_predictors_0_io_f0_mask_end_mask_T_2 = _banked_predictors_0_io_f0_mask_end_mask_T_1; // @[frontend.scala:139:{21,66}] wire [7:0] banked_predictors_0_io_f0_mask_end_mask = _banked_predictors_0_io_f0_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:139:21, :167:25] wire [10:0] _banked_predictors_0_io_f0_mask_T = 11'hFF << banked_predictors_0_io_f0_mask_shamt; // @[package.scala:163:13] wire [10:0] _banked_predictors_0_io_f0_mask_T_1 = {3'h0, _banked_predictors_0_io_f0_mask_T[7:0] & banked_predictors_0_io_f0_mask_end_mask}; // @[frontend.scala:167:25, :168:{31,40}] wire [39:0] _banked_predictors_1_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_1_io_f0_pc_T_1 = {_banked_predictors_1_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_1_io_f0_pc_T_2 = ~_banked_predictors_1_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_1_io_f0_pc_T_3 = {1'h0, _banked_predictors_1_io_f0_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_1_io_f0_pc_T_4 = _banked_predictors_1_io_f0_pc_T_3[39:0]; // @[frontend.scala:151:46] wire _banked_lhist_providers_0_io_f0_valid_T_1 = &_banked_lhist_providers_0_io_f0_valid_T; // @[frontend.scala:139:{28,66}] wire _banked_lhist_providers_0_io_f0_valid_T_2 = _banked_lhist_providers_0_io_f0_valid_T_1; // @[frontend.scala:139:{21,66}] wire _banked_lhist_providers_0_io_f0_valid_T_3 = ~_banked_lhist_providers_0_io_f0_valid_T_2; // @[frontend.scala:139:21] wire _banked_lhist_providers_0_io_f0_valid_T_4 = io_f0_req_valid_0 & _banked_lhist_providers_0_io_f0_valid_T_3; // @[predictor.scala:196:7, :270:{64,67}] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_3 = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_4 = {_banked_lhist_providers_0_io_f0_pc_T_3[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_5 = ~_banked_lhist_providers_0_io_f0_pc_T_4; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_0_io_f0_pc_T_6 = {1'h0, _banked_lhist_providers_0_io_f0_pc_T_5} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_7 = _banked_lhist_providers_0_io_f0_pc_T_6[39:0]; // @[frontend.scala:151:46] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_5 = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_6 = {_banked_lhist_providers_1_io_f0_pc_T_5[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_f0_pc_T_7 = ~_banked_lhist_providers_1_io_f0_pc_T_6; // @[frontend.scala:147:{31,39}] wire _banked_predictors_0_io_f0_valid_T_1 = &_banked_predictors_0_io_f0_valid_T; // @[frontend.scala:139:{28,66}] wire _banked_predictors_0_io_f0_valid_T_2 = _banked_predictors_0_io_f0_valid_T_1; // @[frontend.scala:139:{21,66}] wire _banked_predictors_0_io_f0_valid_T_3 = ~_banked_predictors_0_io_f0_valid_T_2; // @[frontend.scala:139:21] wire _banked_predictors_0_io_f0_valid_T_4 = io_f0_req_valid_0 & _banked_predictors_0_io_f0_valid_T_3; // @[predictor.scala:196:7, :276:{59,62}] wire banked_predictors_0_io_f0_valid = io_f0_req_bits_pc_0[3] ? _banked_predictors_0_io_f0_valid_T_4 : io_f0_req_valid_0; // @[frontend.scala:137:47] wire [39:0] _banked_predictors_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_0_io_f0_pc_T_1 = {_banked_predictors_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_0_io_f0_pc_T_2 = ~_banked_predictors_0_io_f0_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_0_io_f0_pc_T_3 = {1'h0, _banked_predictors_0_io_f0_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_0_io_f0_pc_T_4 = _banked_predictors_0_io_f0_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [1:0] banked_predictors_1_io_f0_mask_shamt = banked_predictors_1_io_f0_mask_idx[1:0]; // @[package.scala:163:13] wire _banked_predictors_1_io_f0_mask_end_mask_T_1 = &_banked_predictors_1_io_f0_mask_end_mask_T; // @[frontend.scala:139:{28,66}] wire _banked_predictors_1_io_f0_mask_end_mask_T_2 = _banked_predictors_1_io_f0_mask_end_mask_T_1; // @[frontend.scala:139:{21,66}] wire [7:0] banked_predictors_1_io_f0_mask_end_mask = _banked_predictors_1_io_f0_mask_end_mask_T_2 ? 8'hF : 8'hFF; // @[frontend.scala:139:21, :167:25] wire [10:0] _banked_predictors_1_io_f0_mask_T_1 = 11'hFF << banked_predictors_1_io_f0_mask_shamt; // @[package.scala:163:13] wire [10:0] _banked_predictors_1_io_f0_mask_T_2 = {3'h0, _banked_predictors_1_io_f0_mask_T_1[7:0] & banked_predictors_1_io_f0_mask_end_mask}; // @[frontend.scala:167:25, :168:{31,40}] reg REG; // @[predictor.scala:284:18] reg [63:0] banked_predictors_0_io_f1_ghist_REG; // @[predictor.scala:285:51] wire [64:0] _GEN = {io_f0_req_bits_ghist_old_history_0, 1'h0}; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_f1_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_1_io_f1_ghist_T = _GEN; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_f1_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_1_io_f1_ghist_T_2 = _GEN; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_0_io_f1_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_0_io_f1_ghist_T = _GEN; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_0_io_f1_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_0_io_f1_ghist_T_2 = _GEN; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_1_io_f1_ghist_T_1 = {_banked_predictors_1_io_f1_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _GEN_0 = {1'h0, io_f0_req_bits_ghist_old_history_0}; // @[frontend.scala:54:12] wire [64:0] _banked_predictors_1_io_f1_ghist_T_3 = io_f0_req_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_1_io_f1_ghist_T_2 : _GEN_0; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_1_io_f1_ghist_T_4 = io_f0_req_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_1_io_f1_ghist_T_1 : _banked_predictors_1_io_f1_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12] reg [64:0] banked_predictors_1_io_f1_ghist_REG; // @[predictor.scala:286:51] wire [64:0] _banked_predictors_0_io_f1_ghist_T_1 = {_banked_predictors_0_io_f1_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _banked_predictors_0_io_f1_ghist_T_3 = io_f0_req_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_0_io_f1_ghist_T_2 : _GEN_0; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_0_io_f1_ghist_T_4 = io_f0_req_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_0_io_f1_ghist_T_1 : _banked_predictors_0_io_f1_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12] reg [64:0] banked_predictors_0_io_f1_ghist_REG_1; // @[predictor.scala:288:51] reg [63:0] banked_predictors_1_io_f1_ghist_REG_1; // @[predictor.scala:289:51] wire _banked_lhist_providers_0_io_f3_taken_br_T = _banked_predictors_0_io_resp_f3_0_is_br & _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_1 = _banked_lhist_providers_0_io_f3_taken_br_T & _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_2 = _banked_predictors_0_io_resp_f3_1_is_br & _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_3 = _banked_lhist_providers_0_io_f3_taken_br_T_2 & _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_4 = _banked_predictors_0_io_resp_f3_2_is_br & _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_5 = _banked_lhist_providers_0_io_f3_taken_br_T_4 & _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_6 = _banked_predictors_0_io_resp_f3_3_is_br & _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_7 = _banked_lhist_providers_0_io_f3_taken_br_T_6 & _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_0_io_f3_taken_br_T_8 = _banked_lhist_providers_0_io_f3_taken_br_T_1 | _banked_lhist_providers_0_io_f3_taken_br_T_3; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_9 = _banked_lhist_providers_0_io_f3_taken_br_T_8 | _banked_lhist_providers_0_io_f3_taken_br_T_5; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_0_io_f3_taken_br_T_10 = _banked_lhist_providers_0_io_f3_taken_br_T_9 | _banked_lhist_providers_0_io_f3_taken_br_T_7; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_1_io_f3_taken_br_T = _banked_predictors_1_io_resp_f3_0_is_br & _banked_predictors_1_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_1 = _banked_lhist_providers_1_io_f3_taken_br_T & _banked_predictors_1_io_resp_f3_0_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_2 = _banked_predictors_1_io_resp_f3_1_is_br & _banked_predictors_1_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_3 = _banked_lhist_providers_1_io_f3_taken_br_T_2 & _banked_predictors_1_io_resp_f3_1_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_4 = _banked_predictors_1_io_resp_f3_2_is_br & _banked_predictors_1_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_5 = _banked_lhist_providers_1_io_f3_taken_br_T_4 & _banked_predictors_1_io_resp_f3_2_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_6 = _banked_predictors_1_io_resp_f3_3_is_br & _banked_predictors_1_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:221:19, :296:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_7 = _banked_lhist_providers_1_io_f3_taken_br_T_6 & _banked_predictors_1_io_resp_f3_3_taken; // @[predictor.scala:221:19, :296:{15,39}] wire _banked_lhist_providers_1_io_f3_taken_br_T_8 = _banked_lhist_providers_1_io_f3_taken_br_T_1 | _banked_lhist_providers_1_io_f3_taken_br_T_3; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_9 = _banked_lhist_providers_1_io_f3_taken_br_T_8 | _banked_lhist_providers_1_io_f3_taken_br_T_5; // @[predictor.scala:296:39, :297:15] wire _banked_lhist_providers_1_io_f3_taken_br_T_10 = _banked_lhist_providers_1_io_f3_taken_br_T_9 | _banked_lhist_providers_1_io_f3_taken_br_T_7; // @[predictor.scala:296:39, :297:15] reg b0_fire_REG; // @[predictor.scala:311:56] reg b0_fire_REG_1; // @[predictor.scala:311:48] reg b0_fire_REG_2; // @[predictor.scala:311:40] wire b0_fire = io_f3_fire_0 & b0_fire_REG_2; // @[predictor.scala:196:7, :311:{30,40}] reg b1_fire_REG; // @[predictor.scala:312:56] reg b1_fire_REG_1; // @[predictor.scala:312:48] reg b1_fire_REG_2; // @[predictor.scala:312:40] wire b1_fire = io_f3_fire_0 & b1_fire_REG_2; // @[predictor.scala:196:7, :312:{30,40}] assign io_resp_f1_preds_0_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_taken : _banked_predictors_0_io_resp_f1_0_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_is_br : _banked_predictors_0_io_resp_f1_0_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_is_jal : _banked_predictors_0_io_resp_f1_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_predicted_pc_valid : _banked_predictors_0_io_resp_f1_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_0_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_0_predicted_pc_bits : _banked_predictors_0_io_resp_f1_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_taken : _banked_predictors_1_io_resp_f1_0_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_is_br : _banked_predictors_1_io_resp_f1_0_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_is_jal : _banked_predictors_1_io_resp_f1_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_predicted_pc_valid : _banked_predictors_1_io_resp_f1_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_4_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_0_predicted_pc_bits : _banked_predictors_1_io_resp_f1_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_taken : _banked_predictors_0_io_resp_f1_1_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_is_br : _banked_predictors_0_io_resp_f1_1_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_is_jal : _banked_predictors_0_io_resp_f1_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_predicted_pc_valid : _banked_predictors_0_io_resp_f1_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_1_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_1_predicted_pc_bits : _banked_predictors_0_io_resp_f1_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_taken : _banked_predictors_1_io_resp_f1_1_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_is_br : _banked_predictors_1_io_resp_f1_1_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_is_jal : _banked_predictors_1_io_resp_f1_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_predicted_pc_valid : _banked_predictors_1_io_resp_f1_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_5_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_1_predicted_pc_bits : _banked_predictors_1_io_resp_f1_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_taken : _banked_predictors_0_io_resp_f1_2_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_is_br : _banked_predictors_0_io_resp_f1_2_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_is_jal : _banked_predictors_0_io_resp_f1_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_predicted_pc_valid : _banked_predictors_0_io_resp_f1_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_2_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_2_predicted_pc_bits : _banked_predictors_0_io_resp_f1_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_taken : _banked_predictors_1_io_resp_f1_2_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_is_br : _banked_predictors_1_io_resp_f1_2_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_is_jal : _banked_predictors_1_io_resp_f1_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_predicted_pc_valid : _banked_predictors_1_io_resp_f1_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_6_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_2_predicted_pc_bits : _banked_predictors_1_io_resp_f1_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_taken : _banked_predictors_0_io_resp_f1_3_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_is_br : _banked_predictors_0_io_resp_f1_3_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_is_jal : _banked_predictors_0_io_resp_f1_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_predicted_pc_valid : _banked_predictors_0_io_resp_f1_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_3_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_1_io_resp_f1_3_predicted_pc_bits : _banked_predictors_0_io_resp_f1_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_taken_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_taken : _banked_predictors_1_io_resp_f1_3_taken; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_is_br_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_is_br : _banked_predictors_1_io_resp_f1_3_is_br; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_is_jal_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_is_jal : _banked_predictors_1_io_resp_f1_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_predicted_pc_valid_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_predicted_pc_valid : _banked_predictors_1_io_resp_f1_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f1_preds_7_predicted_pc_bits_0 = io_resp_f1_pc[3] ? _banked_predictors_0_io_resp_f1_3_predicted_pc_bits : _banked_predictors_1_io_resp_f1_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_taken : _banked_predictors_0_io_resp_f2_0_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_is_br : _banked_predictors_0_io_resp_f2_0_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_is_jal : _banked_predictors_0_io_resp_f2_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_predicted_pc_valid : _banked_predictors_0_io_resp_f2_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_0_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_0_predicted_pc_bits : _banked_predictors_0_io_resp_f2_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_taken : _banked_predictors_1_io_resp_f2_0_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_is_br : _banked_predictors_1_io_resp_f2_0_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_is_jal : _banked_predictors_1_io_resp_f2_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_predicted_pc_valid : _banked_predictors_1_io_resp_f2_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_4_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_0_predicted_pc_bits : _banked_predictors_1_io_resp_f2_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_taken : _banked_predictors_0_io_resp_f2_1_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_is_br : _banked_predictors_0_io_resp_f2_1_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_is_jal : _banked_predictors_0_io_resp_f2_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_predicted_pc_valid : _banked_predictors_0_io_resp_f2_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_1_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_1_predicted_pc_bits : _banked_predictors_0_io_resp_f2_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_taken : _banked_predictors_1_io_resp_f2_1_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_is_br : _banked_predictors_1_io_resp_f2_1_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_is_jal : _banked_predictors_1_io_resp_f2_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_predicted_pc_valid : _banked_predictors_1_io_resp_f2_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_5_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_1_predicted_pc_bits : _banked_predictors_1_io_resp_f2_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_taken : _banked_predictors_0_io_resp_f2_2_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_is_br : _banked_predictors_0_io_resp_f2_2_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_is_jal : _banked_predictors_0_io_resp_f2_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_predicted_pc_valid : _banked_predictors_0_io_resp_f2_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_2_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_2_predicted_pc_bits : _banked_predictors_0_io_resp_f2_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_taken : _banked_predictors_1_io_resp_f2_2_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_is_br : _banked_predictors_1_io_resp_f2_2_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_is_jal : _banked_predictors_1_io_resp_f2_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_predicted_pc_valid : _banked_predictors_1_io_resp_f2_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_6_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_2_predicted_pc_bits : _banked_predictors_1_io_resp_f2_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_taken : _banked_predictors_0_io_resp_f2_3_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_is_br : _banked_predictors_0_io_resp_f2_3_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_is_jal : _banked_predictors_0_io_resp_f2_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_predicted_pc_valid : _banked_predictors_0_io_resp_f2_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_3_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_1_io_resp_f2_3_predicted_pc_bits : _banked_predictors_0_io_resp_f2_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_taken_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_taken : _banked_predictors_1_io_resp_f2_3_taken; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_is_br_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_is_br : _banked_predictors_1_io_resp_f2_3_is_br; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_is_jal_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_is_jal : _banked_predictors_1_io_resp_f2_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_predicted_pc_valid_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_predicted_pc_valid : _banked_predictors_1_io_resp_f2_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f2_preds_7_predicted_pc_bits_0 = io_resp_f2_pc[3] ? _banked_predictors_0_io_resp_f2_3_predicted_pc_bits : _banked_predictors_1_io_resp_f2_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_taken : _banked_predictors_0_io_resp_f3_0_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_is_br : _banked_predictors_0_io_resp_f3_0_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_is_jal : _banked_predictors_0_io_resp_f3_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_predicted_pc_valid : _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_0_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_0_predicted_pc_bits : _banked_predictors_0_io_resp_f3_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_taken : _banked_predictors_1_io_resp_f3_0_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_is_br : _banked_predictors_1_io_resp_f3_0_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_is_jal : _banked_predictors_1_io_resp_f3_0_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_predicted_pc_valid : _banked_predictors_1_io_resp_f3_0_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_4_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_0_predicted_pc_bits : _banked_predictors_1_io_resp_f3_0_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_taken : _banked_predictors_0_io_resp_f3_1_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_is_br : _banked_predictors_0_io_resp_f3_1_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_is_jal : _banked_predictors_0_io_resp_f3_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_predicted_pc_valid : _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_1_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_1_predicted_pc_bits : _banked_predictors_0_io_resp_f3_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_taken : _banked_predictors_1_io_resp_f3_1_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_is_br : _banked_predictors_1_io_resp_f3_1_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_is_jal : _banked_predictors_1_io_resp_f3_1_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_predicted_pc_valid : _banked_predictors_1_io_resp_f3_1_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_5_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_1_predicted_pc_bits : _banked_predictors_1_io_resp_f3_1_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_taken : _banked_predictors_0_io_resp_f3_2_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_is_br : _banked_predictors_0_io_resp_f3_2_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_is_jal : _banked_predictors_0_io_resp_f3_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_predicted_pc_valid : _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_2_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_2_predicted_pc_bits : _banked_predictors_0_io_resp_f3_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_taken : _banked_predictors_1_io_resp_f3_2_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_is_br : _banked_predictors_1_io_resp_f3_2_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_is_jal : _banked_predictors_1_io_resp_f3_2_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_predicted_pc_valid : _banked_predictors_1_io_resp_f3_2_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_6_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_2_predicted_pc_bits : _banked_predictors_1_io_resp_f3_2_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_taken : _banked_predictors_0_io_resp_f3_3_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_is_br : _banked_predictors_0_io_resp_f3_3_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_is_jal : _banked_predictors_0_io_resp_f3_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_predicted_pc_valid : _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_3_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_1_io_resp_f3_3_predicted_pc_bits : _banked_predictors_0_io_resp_f3_3_predicted_pc_bits; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_taken_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_taken : _banked_predictors_1_io_resp_f3_3_taken; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_is_br_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_is_br : _banked_predictors_1_io_resp_f3_3_is_br; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_is_jal_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_is_jal : _banked_predictors_1_io_resp_f3_3_is_jal; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_predicted_pc_valid_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_predicted_pc_valid : _banked_predictors_1_io_resp_f3_3_predicted_pc_valid; // @[frontend.scala:137:47] assign io_resp_f3_preds_7_predicted_pc_bits_0 = io_resp_f3_pc_0[3] ? _banked_predictors_0_io_resp_f3_3_predicted_pc_bits : _banked_predictors_1_io_resp_f3_3_predicted_pc_bits; // @[frontend.scala:137:47] reg [39:0] io_resp_f1_pc_REG; // @[predictor.scala:365:27] assign io_resp_f1_pc = io_resp_f1_pc_REG; // @[predictor.scala:196:7, :365:27] reg [39:0] io_resp_f2_pc_REG; // @[predictor.scala:366:27] assign io_resp_f2_pc = io_resp_f2_pc_REG; // @[predictor.scala:196:7, :366:27] reg [39:0] io_resp_f3_pc_REG; // @[predictor.scala:367:27] assign io_resp_f3_pc_0 = io_resp_f3_pc_REG; // @[predictor.scala:196:7, :367:27] wire _b1_update_valid_T = ~io_update_bits_cfi_idx_valid_0; // @[predictor.scala:196:7, :413:10] wire _b1_update_valid_T_1 = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71, :434:120] wire _b0_update_valid_T_6 = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71, :440:71] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2 = io_update_bits_cfi_idx_bits_0[2]; // @[predictor.scala:196:7, :413:71, :461:120] wire _b1_update_valid_T_2 = _b1_update_valid_T | _b1_update_valid_T_1; // @[predictor.scala:413:{10,40,71}] wire b1_update_valid = io_update_valid_0 & _b1_update_valid_T_2; // @[predictor.scala:196:7, :412:45, :413:40] wire [3:0] _banked_lhist_providers_0_io_update_valid_T = io_update_bits_br_mask_0[3:0]; // @[predictor.scala:196:7, :415:93] wire [3:0] _banked_lhist_providers_1_io_update_valid_T_3 = io_update_bits_br_mask_0[3:0]; // @[predictor.scala:196:7, :415:93, :442:93] wire _banked_lhist_providers_0_io_update_valid_T_1 = |_banked_lhist_providers_0_io_update_valid_T; // @[predictor.scala:415:{93,109}] wire _banked_lhist_providers_0_io_update_valid_T_2 = io_update_valid_0 & _banked_lhist_providers_0_io_update_valid_T_1; // @[predictor.scala:196:7, :415:{68,109}] wire [3:0] _banked_lhist_providers_1_io_update_valid_T = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93] wire [3:0] _banked_predictors_1_io_update_bits_br_mask_T = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93, :428:77] wire [3:0] _banked_lhist_providers_0_io_update_valid_T_3 = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93, :443:93] wire [3:0] _banked_predictors_0_io_update_bits_br_mask_T = io_update_bits_br_mask_0[7:4]; // @[predictor.scala:196:7, :416:93, :455:77] wire _banked_lhist_providers_1_io_update_valid_T_1 = |_banked_lhist_providers_1_io_update_valid_T; // @[predictor.scala:416:{93,118}] wire _banked_lhist_providers_1_io_update_valid_T_2 = b1_update_valid & _banked_lhist_providers_1_io_update_valid_T_1; // @[predictor.scala:412:45, :416:{68,118}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_1 = {_banked_lhist_providers_0_io_update_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_2 = ~_banked_lhist_providers_0_io_update_pc_T_1; // @[frontend.scala:147:{31,39}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_1 = {_banked_lhist_providers_1_io_update_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_2 = ~_banked_lhist_providers_1_io_update_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_1_io_update_pc_T_3 = {1'h0, _banked_lhist_providers_1_io_update_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_4 = _banked_lhist_providers_1_io_update_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [39:0] _banked_predictors_1_io_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_1_io_update_bits_pc_T_1 = {_banked_predictors_1_io_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_1_io_update_bits_pc_T_2 = ~_banked_predictors_1_io_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_1_io_update_bits_pc_T_3 = {1'h0, _banked_predictors_1_io_update_bits_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_1_io_update_bits_pc_T_4 = _banked_predictors_1_io_update_bits_pc_T_3[39:0]; // @[frontend.scala:151:46] wire [3:0] _banked_predictors_1_io_update_bits_btb_mispredicts_T = io_update_bits_btb_mispredicts_0[7:4]; // @[predictor.scala:196:7, :431:94] wire [3:0] _banked_predictors_0_io_update_bits_btb_mispredicts_T = io_update_bits_btb_mispredicts_0[7:4]; // @[predictor.scala:196:7, :431:94, :458:94] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T = ~(io_update_bits_cfi_idx_bits_0[2]); // @[predictor.scala:196:7, :413:71, :433:120] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T_1 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_0_io_update_bits_cfi_idx_valid_T; // @[predictor.scala:196:7, :433:{89,120}] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T_1 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_1_io_update_bits_cfi_idx_valid_T; // @[predictor.scala:196:7, :434:{89,120}] wire [64:0] _GEN_1 = {io_update_bits_ghist_old_history_0, 1'h0}; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_1_io_update_bits_ghist_T = _GEN_1; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_1_io_update_bits_ghist_T_2 = _GEN_1; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T; // @[frontend.scala:53:75] assign _banked_predictors_0_io_update_bits_ghist_T = _GEN_1; // @[frontend.scala:53:75] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_2; // @[frontend.scala:54:75] assign _banked_predictors_0_io_update_bits_ghist_T_2 = _GEN_1; // @[frontend.scala:53:75, :54:75] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_1 = {_banked_predictors_1_io_update_bits_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _GEN_2 = {1'h0, io_update_bits_ghist_old_history_0}; // @[frontend.scala:54:12] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_3 = io_update_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_1_io_update_bits_ghist_T_2 : _GEN_2; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_1_io_update_bits_ghist_T_4 = io_update_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_1_io_update_bits_ghist_T_1 : _banked_predictors_1_io_update_bits_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12] wire [2:0] _b0_update_valid_T = io_update_bits_pc_0[5:3]; // @[frontend.scala:139:28] wire _b0_update_valid_T_1 = &_b0_update_valid_T; // @[frontend.scala:139:{28,66}] wire _b0_update_valid_T_2 = _b0_update_valid_T_1; // @[frontend.scala:139:{21,66}] wire _b0_update_valid_T_3 = ~_b0_update_valid_T_2; // @[frontend.scala:139:21] wire _b0_update_valid_T_4 = io_update_valid_0 & _b0_update_valid_T_3; // @[predictor.scala:196:7, :439:{45,48}] wire _b0_update_valid_T_5 = ~io_update_bits_cfi_idx_valid_0; // @[predictor.scala:196:7, :413:10, :440:10] wire _b0_update_valid_T_7 = _b0_update_valid_T_5 | _b0_update_valid_T_6; // @[predictor.scala:440:{10,40,71}] wire b0_update_valid = _b0_update_valid_T_4 & _b0_update_valid_T_7; // @[predictor.scala:439:{45,87}, :440:40] wire _banked_lhist_providers_1_io_update_valid_T_4 = |_banked_lhist_providers_1_io_update_valid_T_3; // @[predictor.scala:442:{93,109}] wire _banked_lhist_providers_1_io_update_valid_T_5 = io_update_valid_0 & _banked_lhist_providers_1_io_update_valid_T_4; // @[predictor.scala:196:7, :442:{68,109}] wire _banked_lhist_providers_0_io_update_valid_T_4 = |_banked_lhist_providers_0_io_update_valid_T_3; // @[predictor.scala:443:{93,118}] wire _banked_lhist_providers_0_io_update_valid_T_5 = b0_update_valid & _banked_lhist_providers_0_io_update_valid_T_4; // @[predictor.scala:439:87, :443:{68,118}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_5 = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_6 = {_banked_lhist_providers_1_io_update_pc_T_5[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_1_io_update_pc_T_7 = ~_banked_lhist_providers_1_io_update_pc_T_6; // @[frontend.scala:147:{31,39}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_3 = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_4 = {_banked_lhist_providers_0_io_update_pc_T_3[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_5 = ~_banked_lhist_providers_0_io_update_pc_T_4; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_lhist_providers_0_io_update_pc_T_6 = {1'h0, _banked_lhist_providers_0_io_update_pc_T_5} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_lhist_providers_0_io_update_pc_T_7 = _banked_lhist_providers_0_io_update_pc_T_6[39:0]; // @[frontend.scala:151:46] wire [39:0] _banked_predictors_0_io_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33] wire [39:0] _banked_predictors_0_io_update_bits_pc_T_1 = {_banked_predictors_0_io_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _banked_predictors_0_io_update_bits_pc_T_2 = ~_banked_predictors_0_io_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}] wire [40:0] _banked_predictors_0_io_update_bits_pc_T_3 = {1'h0, _banked_predictors_0_io_update_bits_pc_T_2} + 41'h8; // @[frontend.scala:147:31, :151:46] wire [39:0] _banked_predictors_0_io_update_bits_pc_T_4 = _banked_predictors_0_io_update_bits_pc_T_3[39:0]; // @[frontend.scala:151:46] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2 = ~(io_update_bits_cfi_idx_bits_0[2]); // @[predictor.scala:196:7, :413:71, :433:120, :460:120] wire _banked_predictors_1_io_update_bits_cfi_idx_valid_T_3 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_1_io_update_bits_cfi_idx_valid_T_2; // @[predictor.scala:196:7, :460:{89,120}] wire _banked_predictors_0_io_update_bits_cfi_idx_valid_T_3 = io_update_bits_cfi_idx_valid_0 & _banked_predictors_0_io_update_bits_cfi_idx_valid_T_2; // @[predictor.scala:196:7, :461:{89,120}] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_1 = {_banked_predictors_0_io_update_bits_ghist_T[64:1], 1'h1}; // @[frontend.scala:53:{75,80}] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_3 = io_update_bits_ghist_new_saw_branch_not_taken_0 ? _banked_predictors_0_io_update_bits_ghist_T_2 : _GEN_2; // @[frontend.scala:54:{12,75}] wire [64:0] _banked_predictors_0_io_update_bits_ghist_T_4 = io_update_bits_ghist_new_saw_branch_taken_0 ? _banked_predictors_0_io_update_bits_ghist_T_1 : _banked_predictors_0_io_update_bits_ghist_T_3; // @[frontend.scala:53:{12,80}, :54:12]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_4.bits.sink, UInt<5>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_58 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_59 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_60 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_61 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_100 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_101 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:60)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [4095:0] _GEN = {4084'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [4095:0] _GEN_2 = {4084'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_99 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_57 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_114 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_115 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_66 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(_T_12, _T_19) node _T_35 = or(_T_34, _T_26) node _T_36 = or(_T_35, _T_33) node _T_37 = or(_T_5, _T_36) node _T_38 = asUInt(reset) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = eq(_T_37, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_37, UInt<1>(0h1), "") : assert_1 node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_43 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_50 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_57 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_64 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = or(_T_48, _T_55) node _T_71 = or(_T_70, _T_62) node _T_72 = or(_T_71, _T_69) node _T_73 = or(_T_41, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2 node _T_77 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_84 = and(_T_82, _T_83) node _T_85 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_89 = and(_T_87, _T_88) node _T_90 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_91 = and(_T_89, _T_90) node _T_92 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_105 = and(_T_103, _T_104) node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = or(_T_84, _T_91) node _T_135 = or(_T_134, _T_98) node _T_136 = or(_T_135, _T_105) node _T_137 = or(_T_136, _T_112) node _T_138 = or(_T_137, _T_119) node _T_139 = or(_T_138, _T_126) node _T_140 = or(_T_139, _T_133) node _T_141 = or(_T_77, _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_141, UInt<1>(0h1), "") : assert_3 node _T_145 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_194 = and(_T_192, _T_193) node _T_195 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_196 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_201 = and(_T_199, _T_200) node _T_202 = or(_T_152, _T_159) node _T_203 = or(_T_202, _T_166) node _T_204 = or(_T_203, _T_173) node _T_205 = or(_T_204, _T_180) node _T_206 = or(_T_205, _T_187) node _T_207 = or(_T_206, _T_194) node _T_208 = or(_T_207, _T_201) node _T_209 = or(_T_145, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_209, UInt<1>(0h1), "") : assert_4 node _T_213 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_215 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_222 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_229 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_236 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_243 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_250 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_257 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_258 = and(_T_256, _T_257) node _T_259 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_264 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_271 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_272 = and(_T_270, _T_271) node _T_273 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_278 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_285 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_292 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_299 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_304 = and(_T_302, _T_303) node _T_305 = or(_T_220, _T_227) node _T_306 = or(_T_305, _T_234) node _T_307 = or(_T_306, _T_241) node _T_308 = or(_T_307, _T_248) node _T_309 = or(_T_308, _T_255) node _T_310 = or(_T_309, _T_262) node _T_311 = or(_T_310, _T_269) node _T_312 = or(_T_311, _T_276) node _T_313 = or(_T_312, _T_283) node _T_314 = or(_T_313, _T_290) node _T_315 = or(_T_314, _T_297) node _T_316 = or(_T_315, _T_304) node _T_317 = or(_T_213, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_317, UInt<1>(0h1), "") : assert_5 node _T_321 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_322 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_323 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_328 = and(_T_326, _T_327) node _T_329 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_330 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_335 = and(_T_333, _T_334) node _T_336 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_337 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_344 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_345 = and(_T_343, _T_344) node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_351 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_358 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_365 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_370 = and(_T_368, _T_369) node _T_371 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_372 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_373 = and(_T_371, _T_372) node _T_374 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_377 = and(_T_375, _T_376) node _T_378 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_379 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_386 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_387 = and(_T_385, _T_386) node _T_388 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_389 = and(_T_387, _T_388) node _T_390 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_391 = and(_T_389, _T_390) node _T_392 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_393 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_400 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_401 = and(_T_399, _T_400) node _T_402 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_407 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_408 = and(_T_406, _T_407) node _T_409 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_412 = and(_T_410, _T_411) node _T_413 = or(_T_328, _T_335) node _T_414 = or(_T_413, _T_342) node _T_415 = or(_T_414, _T_349) node _T_416 = or(_T_415, _T_356) node _T_417 = or(_T_416, _T_363) node _T_418 = or(_T_417, _T_370) node _T_419 = or(_T_418, _T_377) node _T_420 = or(_T_419, _T_384) node _T_421 = or(_T_420, _T_391) node _T_422 = or(_T_421, _T_398) node _T_423 = or(_T_422, _T_405) node _T_424 = or(_T_423, _T_412) node _T_425 = or(_T_321, _T_424) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_425, UInt<1>(0h1), "") : assert_6 node _T_429 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_431 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_436 = and(_T_434, _T_435) node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_438 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_443 = and(_T_441, _T_442) node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_445 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_446 = and(_T_444, _T_445) node _T_447 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_448 = and(_T_446, _T_447) node _T_449 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_452 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_459 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_462 = and(_T_460, _T_461) node _T_463 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_464 = and(_T_462, _T_463) node _T_465 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_466 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_473 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_476 = and(_T_474, _T_475) node _T_477 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_480 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_481 = and(_T_479, _T_480) node _T_482 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_483 = and(_T_481, _T_482) node _T_484 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_485 = and(_T_483, _T_484) node _T_486 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_487 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_488 = and(_T_486, _T_487) node _T_489 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_490 = and(_T_488, _T_489) node _T_491 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_492 = and(_T_490, _T_491) node _T_493 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_494 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_495 = and(_T_493, _T_494) node _T_496 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_499 = and(_T_497, _T_498) node _T_500 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_501 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_504 = and(_T_502, _T_503) node _T_505 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_508 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_509 = and(_T_507, _T_508) node _T_510 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_511 = and(_T_509, _T_510) node _T_512 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_515 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_516 = and(_T_514, _T_515) node _T_517 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_520 = and(_T_518, _T_519) node _T_521 = or(_T_436, _T_443) node _T_522 = or(_T_521, _T_450) node _T_523 = or(_T_522, _T_457) node _T_524 = or(_T_523, _T_464) node _T_525 = or(_T_524, _T_471) node _T_526 = or(_T_525, _T_478) node _T_527 = or(_T_526, _T_485) node _T_528 = or(_T_527, _T_492) node _T_529 = or(_T_528, _T_499) node _T_530 = or(_T_529, _T_506) node _T_531 = or(_T_530, _T_513) node _T_532 = or(_T_531, _T_520) node _T_533 = or(_T_429, _T_532) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_533, UInt<1>(0h1), "") : assert_7 node _T_537 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_539 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_540 = and(_T_538, _T_539) node _T_541 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_542 = and(_T_540, _T_541) node _T_543 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_546 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_547 = and(_T_545, _T_546) node _T_548 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_553 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_560 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_561 = and(_T_559, _T_560) node _T_562 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_567 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_568 = and(_T_566, _T_567) node _T_569 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_570 = and(_T_568, _T_569) node _T_571 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_574 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_575 = and(_T_573, _T_574) node _T_576 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_577 = and(_T_575, _T_576) node _T_578 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_581 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_582 = and(_T_580, _T_581) node _T_583 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_584 = and(_T_582, _T_583) node _T_585 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_586 = and(_T_584, _T_585) node _T_587 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_588 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_589 = and(_T_587, _T_588) node _T_590 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_591 = and(_T_589, _T_590) node _T_592 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_593 = and(_T_591, _T_592) node _T_594 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_595 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_596 = and(_T_594, _T_595) node _T_597 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_600 = and(_T_598, _T_599) node _T_601 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_602 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_605 = and(_T_603, _T_604) node _T_606 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_609 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_612 = and(_T_610, _T_611) node _T_613 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_614 = and(_T_612, _T_613) node _T_615 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_616 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_617 = and(_T_615, _T_616) node _T_618 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_619 = and(_T_617, _T_618) node _T_620 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_621 = and(_T_619, _T_620) node _T_622 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he)) node _T_623 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_624 = and(_T_622, _T_623) node _T_625 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(_T_544, _T_551) node _T_630 = or(_T_629, _T_558) node _T_631 = or(_T_630, _T_565) node _T_632 = or(_T_631, _T_572) node _T_633 = or(_T_632, _T_579) node _T_634 = or(_T_633, _T_586) node _T_635 = or(_T_634, _T_593) node _T_636 = or(_T_635, _T_600) node _T_637 = or(_T_636, _T_607) node _T_638 = or(_T_637, _T_614) node _T_639 = or(_T_638, _T_621) node _T_640 = or(_T_639, _T_628) node _T_641 = or(_T_537, _T_640) node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(_T_641, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_641, UInt<1>(0h1), "") : assert_8

module NoCMonitor_66( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_46 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_92 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_46 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = and(io.in.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail invalidate route_buffer.io.enq.bits.flow.egress_node_id invalidate route_buffer.io.enq.bits.flow.egress_node invalidate route_buffer.io.enq.bits.flow.ingress_node_id invalidate route_buffer.io.enq.bits.flow.ingress_node invalidate route_buffer.io.enq.bits.flow.vnet_id connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h4)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_6 = and(io.in.ready, io.in.valid) node _T_7 = and(_T_6, io.in.bits.head) node _T_8 = and(_T_7, at_dest) when _T_8 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<4>(0he), io.in.bits.egress_id) when _T_9 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<4>(0hf), io.in.bits.egress_id) when _T_10 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<5>(0h10), io.in.bits.egress_id) when _T_11 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_12 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_13 = and(route_q.io.enq.valid, _T_12) node _T_14 = eq(_T_13, UInt<1>(0h0)) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_14, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_93 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_46 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_18 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(vcalloc_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2]) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1 connect io.in.ready, UInt<1>(0h0) connect io.router_req.valid, UInt<1>(0h0) invalidate io.router_req.bits.flow.egress_node_id invalidate io.router_req.bits.flow.egress_node invalidate io.router_req.bits.flow.ingress_node_id invalidate io.router_req.bits.flow.ingress_node invalidate io.router_req.bits.flow.vnet_id invalidate io.router_req.bits.src_virt_id connect io.vcalloc_req.valid, UInt<1>(0h0) invalidate io.vcalloc_req.bits.vc_sel.`0`[0] invalidate io.vcalloc_req.bits.vc_sel.`0`[1] invalidate io.vcalloc_req.bits.vc_sel.`0`[2] invalidate io.vcalloc_req.bits.vc_sel.`0`[3] invalidate io.vcalloc_req.bits.vc_sel.`0`[4] invalidate io.vcalloc_req.bits.vc_sel.`1`[0] invalidate io.vcalloc_req.bits.vc_sel.`2`[0] invalidate io.vcalloc_req.bits.vc_sel.`3`[0] invalidate io.vcalloc_req.bits.in_vc invalidate io.vcalloc_req.bits.flow.egress_node_id invalidate io.vcalloc_req.bits.flow.egress_node invalidate io.vcalloc_req.bits.flow.ingress_node_id invalidate io.vcalloc_req.bits.flow.ingress_node invalidate io.vcalloc_req.bits.flow.vnet_id connect io.salloc_req[0].valid, UInt<1>(0h0) invalidate io.salloc_req[0].bits.tail invalidate io.salloc_req[0].bits.vc_sel.`0`[0] invalidate io.salloc_req[0].bits.vc_sel.`0`[1] invalidate io.salloc_req[0].bits.vc_sel.`0`[2] invalidate io.salloc_req[0].bits.vc_sel.`0`[3] invalidate io.salloc_req[0].bits.vc_sel.`0`[4] invalidate io.salloc_req[0].bits.vc_sel.`1`[0] invalidate io.salloc_req[0].bits.vc_sel.`2`[0] invalidate io.salloc_req[0].bits.vc_sel.`3`[0] connect io.out[0].valid, UInt<1>(0h0) invalidate io.out[0].bits.out_virt_channel invalidate io.out[0].bits.flit.virt_channel_id invalidate io.out[0].bits.flit.flow.egress_node_id invalidate io.out[0].bits.flit.flow.egress_node invalidate io.out[0].bits.flit.flow.ingress_node_id invalidate io.out[0].bits.flit.flow.ingress_node invalidate io.out[0].bits.flit.flow.vnet_id invalidate io.out[0].bits.flit.payload invalidate io.out[0].bits.flit.tail invalidate io.out[0].bits.flit.head

module IngressUnit_46( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_28 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_28( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_473 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_473( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_13 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0)) node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0)) node ordered = and(_ordered_T, _ordered_T_1) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) node _common_ltMags_T = lt(rawA.sExp, rawB.sExp) node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig) node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1) node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2) node _common_eqMags_T = eq(rawA.sig, rawB.sig) node common_eqMags = and(eqExps, _common_eqMags_T) node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0)) node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1) node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0)) node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0)) node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4) node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0)) node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6) node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags) node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9) node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10) node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11) node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12) node _ordered_eq_T = eq(rawA.sign, rawB.sign) node _ordered_eq_T_1 = or(bothInfs, common_eqMags) node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1) node ordered_eq = or(bothZeros, _ordered_eq_T_2) node _invalid_T = bits(rawA.sig, 22, 22) node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0)) node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1) node _invalid_T_3 = bits(rawB.sig, 22, 22) node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0)) node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4) node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5) node _invalid_T_7 = eq(ordered, UInt<1>(0h0)) node _invalid_T_8 = and(io.signaling, _invalid_T_7) node invalid = or(_invalid_T_6, _invalid_T_8) node _io_lt_T = and(ordered, ordered_lt) connect io.lt, _io_lt_T node _io_eq_T = and(ordered, ordered_eq) connect io.eq, _io_eq_T node _io_gt_T = eq(ordered_lt, UInt<1>(0h0)) node _io_gt_T_1 = and(ordered, _io_gt_T) node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0)) node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2) connect io.gt, _io_gt_T_3 node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T

module CompareRecFN_13( // @[CompareRecFN.scala:42:7] input [32:0] io_b, // @[CompareRecFN.scala:44:16] output io_gt // @[CompareRecFN.scala:44:16] ); wire [32:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7] wire [8:0] rawA_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [9:0] rawA_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawA_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawA_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawA_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawA_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawA_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rawA_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawA_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _ordered_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _ordered_lt_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _invalid_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_signaling = 1'h0; // @[CompareRecFN.scala:42:7] wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawA_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire bothInfs = 1'h0; // @[CompareRecFN.scala:58:33] wire _ordered_lt_T_2 = 1'h0; // @[CompareRecFN.scala:67:25] wire _ordered_lt_T_5 = 1'h0; // @[CompareRecFN.scala:69:35] wire _ordered_lt_T_7 = 1'h0; // @[CompareRecFN.scala:69:54] wire _invalid_T = 1'h0; // @[common.scala:82:56] wire _invalid_T_2 = 1'h0; // @[common.scala:82:46] wire _invalid_T_8 = 1'h0; // @[CompareRecFN.scala:76:27] wire [32:0] io_a = 33'h15800000; // @[CompareRecFN.scala:42:7, :44:16] wire _io_lt_T; // @[CompareRecFN.scala:78:22] wire _io_eq_T; // @[CompareRecFN.scala:79:22] wire _io_gt_T_3; // @[CompareRecFN.scala:80:38] wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34] wire io_lt; // @[CompareRecFN.scala:42:7] wire io_eq; // @[CompareRecFN.scala:42:7] wire io_gt_0; // @[CompareRecFN.scala:42:7] wire [4:0] io_exceptionFlags; // @[CompareRecFN.scala:42:7] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire bothZeros = rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire ordered = _ordered_T_1; // @[CompareRecFN.scala:57:{32,35}] wire eqExps = rawB_sExp == 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _common_ltMags_T = $signed(rawB_sExp) > 10'sh2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _common_ltMags_T_1 = |rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}] wire common_ltMags = _common_ltMags_T | _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}] wire _common_eqMags_T = rawB_sig == 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}] wire _ordered_eq_T_1 = common_eqMags; // @[CompareRecFN.scala:63:32, :72:62] wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9] wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38] wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57] wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}] wire _ordered_lt_T_10 = _ordered_lt_T_9; // @[CompareRecFN.scala:69:74, :70:41] wire _ordered_lt_T_11 = _ordered_lt_T_10; // @[CompareRecFN.scala:68:30, :69:74] wire _ordered_lt_T_12 = _ordered_lt_T_11; // @[CompareRecFN.scala:67:41, :68:30] wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41] wire _ordered_eq_T = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}] wire ordered_eq = bothZeros | _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}] wire _invalid_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}] wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_6 = _invalid_T_5; // @[common.scala:82:46] wire invalid = _invalid_T_6; // @[CompareRecFN.scala:75:{32,58}] wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30] assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22] assign io_lt = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22] assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22] assign io_eq = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22] wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25] wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}] wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41] assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}] assign io_gt_0 = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38] assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34] assign io_exceptionFlags = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34] assign io_gt = io_gt_0; // @[CompareRecFN.scala:42:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_1 : input clock : Clock input reset : Reset output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[1], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, flip get_ftq_pc : { flip ftq_idx : UInt<5>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} connect io.req.ready, UInt<1>(0h0) connect io.iresp.valid, UInt<1>(0h0) invalidate io.iresp.bits.fflags.bits.flags invalidate io.iresp.bits.fflags.bits.uop.debug_tsrc invalidate io.iresp.bits.fflags.bits.uop.debug_fsrc invalidate io.iresp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.iresp.bits.fflags.bits.uop.bp_debug_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.iresp.bits.fflags.bits.uop.fp_single invalidate io.iresp.bits.fflags.bits.uop.fp_val invalidate io.iresp.bits.fflags.bits.uop.frs3_en invalidate io.iresp.bits.fflags.bits.uop.lrs2_rtype invalidate io.iresp.bits.fflags.bits.uop.lrs1_rtype invalidate io.iresp.bits.fflags.bits.uop.dst_rtype invalidate io.iresp.bits.fflags.bits.uop.ldst_val invalidate io.iresp.bits.fflags.bits.uop.lrs3 invalidate io.iresp.bits.fflags.bits.uop.lrs2 invalidate io.iresp.bits.fflags.bits.uop.lrs1 invalidate io.iresp.bits.fflags.bits.uop.ldst invalidate io.iresp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.iresp.bits.fflags.bits.uop.flush_on_commit invalidate io.iresp.bits.fflags.bits.uop.is_unique invalidate io.iresp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.iresp.bits.fflags.bits.uop.uses_stq invalidate io.iresp.bits.fflags.bits.uop.uses_ldq invalidate io.iresp.bits.fflags.bits.uop.is_amo invalidate io.iresp.bits.fflags.bits.uop.is_fencei invalidate io.iresp.bits.fflags.bits.uop.is_fence invalidate io.iresp.bits.fflags.bits.uop.mem_signed invalidate io.iresp.bits.fflags.bits.uop.mem_size invalidate io.iresp.bits.fflags.bits.uop.mem_cmd invalidate io.iresp.bits.fflags.bits.uop.bypassable invalidate io.iresp.bits.fflags.bits.uop.exc_cause invalidate io.iresp.bits.fflags.bits.uop.exception invalidate io.iresp.bits.fflags.bits.uop.stale_pdst invalidate io.iresp.bits.fflags.bits.uop.ppred_busy invalidate io.iresp.bits.fflags.bits.uop.prs3_busy invalidate io.iresp.bits.fflags.bits.uop.prs2_busy invalidate io.iresp.bits.fflags.bits.uop.prs1_busy invalidate io.iresp.bits.fflags.bits.uop.ppred invalidate io.iresp.bits.fflags.bits.uop.prs3 invalidate io.iresp.bits.fflags.bits.uop.prs2 invalidate io.iresp.bits.fflags.bits.uop.prs1 invalidate io.iresp.bits.fflags.bits.uop.pdst invalidate io.iresp.bits.fflags.bits.uop.rxq_idx invalidate io.iresp.bits.fflags.bits.uop.stq_idx invalidate io.iresp.bits.fflags.bits.uop.ldq_idx invalidate io.iresp.bits.fflags.bits.uop.rob_idx invalidate io.iresp.bits.fflags.bits.uop.csr_addr invalidate io.iresp.bits.fflags.bits.uop.imm_packed invalidate io.iresp.bits.fflags.bits.uop.taken invalidate io.iresp.bits.fflags.bits.uop.pc_lob invalidate io.iresp.bits.fflags.bits.uop.edge_inst invalidate io.iresp.bits.fflags.bits.uop.ftq_idx invalidate io.iresp.bits.fflags.bits.uop.br_tag invalidate io.iresp.bits.fflags.bits.uop.br_mask invalidate io.iresp.bits.fflags.bits.uop.is_sfb invalidate io.iresp.bits.fflags.bits.uop.is_jal invalidate io.iresp.bits.fflags.bits.uop.is_jalr invalidate io.iresp.bits.fflags.bits.uop.is_br invalidate io.iresp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.iresp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.iresp.bits.fflags.bits.uop.iw_state invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_std invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_load invalidate io.iresp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.iresp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.iresp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.iresp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.br_type invalidate io.iresp.bits.fflags.bits.uop.fu_code invalidate io.iresp.bits.fflags.bits.uop.iq_type invalidate io.iresp.bits.fflags.bits.uop.debug_pc invalidate io.iresp.bits.fflags.bits.uop.is_rvc invalidate io.iresp.bits.fflags.bits.uop.debug_inst invalidate io.iresp.bits.fflags.bits.uop.inst invalidate io.iresp.bits.fflags.bits.uop.uopc invalidate io.iresp.bits.fflags.valid invalidate io.iresp.bits.predicated invalidate io.iresp.bits.data invalidate io.iresp.bits.uop.debug_tsrc invalidate io.iresp.bits.uop.debug_fsrc invalidate io.iresp.bits.uop.bp_xcpt_if invalidate io.iresp.bits.uop.bp_debug_if invalidate io.iresp.bits.uop.xcpt_ma_if invalidate io.iresp.bits.uop.xcpt_ae_if invalidate io.iresp.bits.uop.xcpt_pf_if invalidate io.iresp.bits.uop.fp_single invalidate io.iresp.bits.uop.fp_val invalidate io.iresp.bits.uop.frs3_en invalidate io.iresp.bits.uop.lrs2_rtype invalidate io.iresp.bits.uop.lrs1_rtype invalidate io.iresp.bits.uop.dst_rtype invalidate io.iresp.bits.uop.ldst_val invalidate io.iresp.bits.uop.lrs3 invalidate io.iresp.bits.uop.lrs2 invalidate io.iresp.bits.uop.lrs1 invalidate io.iresp.bits.uop.ldst invalidate io.iresp.bits.uop.ldst_is_rs1 invalidate io.iresp.bits.uop.flush_on_commit invalidate io.iresp.bits.uop.is_unique invalidate io.iresp.bits.uop.is_sys_pc2epc invalidate io.iresp.bits.uop.uses_stq invalidate io.iresp.bits.uop.uses_ldq invalidate io.iresp.bits.uop.is_amo invalidate io.iresp.bits.uop.is_fencei invalidate io.iresp.bits.uop.is_fence invalidate io.iresp.bits.uop.mem_signed invalidate io.iresp.bits.uop.mem_size invalidate io.iresp.bits.uop.mem_cmd invalidate io.iresp.bits.uop.bypassable invalidate io.iresp.bits.uop.exc_cause invalidate io.iresp.bits.uop.exception invalidate io.iresp.bits.uop.stale_pdst invalidate io.iresp.bits.uop.ppred_busy invalidate io.iresp.bits.uop.prs3_busy invalidate io.iresp.bits.uop.prs2_busy invalidate io.iresp.bits.uop.prs1_busy invalidate io.iresp.bits.uop.ppred invalidate io.iresp.bits.uop.prs3 invalidate io.iresp.bits.uop.prs2 invalidate io.iresp.bits.uop.prs1 invalidate io.iresp.bits.uop.pdst invalidate io.iresp.bits.uop.rxq_idx invalidate io.iresp.bits.uop.stq_idx invalidate io.iresp.bits.uop.ldq_idx invalidate io.iresp.bits.uop.rob_idx invalidate io.iresp.bits.uop.csr_addr invalidate io.iresp.bits.uop.imm_packed invalidate io.iresp.bits.uop.taken invalidate io.iresp.bits.uop.pc_lob invalidate io.iresp.bits.uop.edge_inst invalidate io.iresp.bits.uop.ftq_idx invalidate io.iresp.bits.uop.br_tag invalidate io.iresp.bits.uop.br_mask invalidate io.iresp.bits.uop.is_sfb invalidate io.iresp.bits.uop.is_jal invalidate io.iresp.bits.uop.is_jalr invalidate io.iresp.bits.uop.is_br invalidate io.iresp.bits.uop.iw_p2_poisoned invalidate io.iresp.bits.uop.iw_p1_poisoned invalidate io.iresp.bits.uop.iw_state invalidate io.iresp.bits.uop.ctrl.is_std invalidate io.iresp.bits.uop.ctrl.is_sta invalidate io.iresp.bits.uop.ctrl.is_load invalidate io.iresp.bits.uop.ctrl.csr_cmd invalidate io.iresp.bits.uop.ctrl.fcn_dw invalidate io.iresp.bits.uop.ctrl.op_fcn invalidate io.iresp.bits.uop.ctrl.imm_sel invalidate io.iresp.bits.uop.ctrl.op2_sel invalidate io.iresp.bits.uop.ctrl.op1_sel invalidate io.iresp.bits.uop.ctrl.br_type invalidate io.iresp.bits.uop.fu_code invalidate io.iresp.bits.uop.iq_type invalidate io.iresp.bits.uop.debug_pc invalidate io.iresp.bits.uop.is_rvc invalidate io.iresp.bits.uop.debug_inst invalidate io.iresp.bits.uop.inst invalidate io.iresp.bits.uop.uopc connect io.iresp.bits.fflags.valid, UInt<1>(0h0) connect io.iresp.bits.predicated, UInt<1>(0h0) node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : node _T_2 = eq(io.iresp.ready, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:147 assert(io.iresp.ready)\n") : printf assert(clock, io.iresp.ready, UInt<1>(0h1), "") : assert wire div_busy : UInt<1> connect div_busy, UInt<1>(0h0) wire ifpu_busy : UInt<1> connect ifpu_busy, UInt<1>(0h0) node _io_fu_types_T = mux(UInt<1>(0h1), UInt<10>(0h1), UInt<1>(0h0)) node _io_fu_types_T_1 = mux(UInt<1>(0h0), UInt<10>(0h8), UInt<1>(0h0)) node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1) node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0)) node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h1)) node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0)) node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5) node _io_fu_types_T_7 = mux(UInt<1>(0h0), UInt<10>(0h20), UInt<1>(0h0)) node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7) node _io_fu_types_T_9 = mux(UInt<1>(0h1), UInt<10>(0h2), UInt<1>(0h0)) node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9) node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0)) node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h0)) node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0)) node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13) node _io_fu_types_T_15 = mux(UInt<1>(0h0), UInt<10>(0h4), UInt<1>(0h0)) node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15) connect io.fu_types, _io_fu_types_T_16 inst ALUUnit of ALUUnit connect ALUUnit.clock, clock connect ALUUnit.reset, reset node _T_3 = eq(io.req.bits.uop.fu_code, UInt<10>(0h1)) node _T_4 = eq(io.req.bits.uop.fu_code, UInt<10>(0h2)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(io.req.bits.uop.fu_code, UInt<10>(0h20)) node _T_7 = neq(io.req.bits.uop.uopc, UInt<7>(0h6c)) node _T_8 = and(_T_6, _T_7) node _T_9 = or(_T_5, _T_8) node _T_10 = and(io.req.valid, _T_9) connect ALUUnit.io.req.valid, _T_10 connect ALUUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect ALUUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect ALUUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect ALUUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect ALUUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect ALUUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect ALUUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect ALUUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect ALUUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect ALUUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect ALUUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect ALUUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect ALUUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect ALUUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect ALUUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect ALUUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect ALUUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect ALUUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect ALUUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect ALUUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect ALUUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect ALUUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect ALUUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect ALUUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect ALUUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect ALUUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect ALUUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect ALUUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect ALUUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect ALUUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect ALUUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect ALUUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect ALUUnit.io.req.bits.uop.exception, io.req.bits.uop.exception connect ALUUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect ALUUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect ALUUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect ALUUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect ALUUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect ALUUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect ALUUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect ALUUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect ALUUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect ALUUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect ALUUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect ALUUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect ALUUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect ALUUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect ALUUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect ALUUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect ALUUnit.io.req.bits.uop.taken, io.req.bits.uop.taken connect ALUUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect ALUUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect ALUUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect ALUUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect ALUUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect ALUUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect ALUUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect ALUUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect ALUUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect ALUUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect ALUUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect ALUUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect ALUUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect ALUUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect ALUUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect ALUUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect ALUUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect ALUUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect ALUUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect ALUUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect ALUUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect ALUUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect ALUUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect ALUUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect ALUUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect ALUUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect ALUUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect ALUUnit.io.req.bits.uop.inst, io.req.bits.uop.inst connect ALUUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect ALUUnit.io.req.bits.kill, io.req.bits.kill connect ALUUnit.io.req.bits.rs1_data, io.req.bits.rs1_data connect ALUUnit.io.req.bits.rs2_data, io.req.bits.rs2_data invalidate ALUUnit.io.req.bits.rs3_data connect ALUUnit.io.req.bits.pred_data, io.req.bits.pred_data invalidate ALUUnit.io.resp.ready connect ALUUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect ALUUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect ALUUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect ALUUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect ALUUnit.io.brupdate.b2.taken, io.brupdate.b2.taken connect ALUUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect ALUUnit.io.brupdate.b2.valid, io.brupdate.b2.valid connect ALUUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect ALUUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect ALUUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect ALUUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect ALUUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect ALUUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect ALUUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect ALUUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect ALUUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect ALUUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect ALUUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect ALUUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect ALUUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect ALUUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect ALUUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect ALUUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect ALUUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect ALUUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect ALUUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect ALUUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect ALUUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect ALUUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect ALUUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect ALUUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect ALUUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect ALUUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect ALUUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect ALUUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect ALUUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect ALUUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect ALUUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect ALUUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect ALUUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect ALUUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect ALUUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect ALUUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect ALUUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect ALUUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect ALUUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect ALUUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect ALUUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect ALUUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect ALUUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect ALUUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect ALUUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect ALUUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect ALUUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect ALUUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect ALUUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect ALUUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect ALUUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect ALUUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect ALUUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect ALUUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect ALUUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect ALUUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect ALUUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect ALUUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect ALUUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect ALUUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect ALUUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect ALUUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect ALUUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect ALUUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect ALUUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect ALUUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect ALUUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect ALUUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect ALUUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect ALUUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect ALUUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect ALUUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect ALUUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect ALUUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect ALUUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect ALUUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect ALUUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect ALUUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect io.bypass, ALUUnit.io.bypass connect io.brinfo, ALUUnit.io.brinfo connect ALUUnit.io.get_ftq_pc, io.get_ftq_pc wire div_resp_val : UInt<1> connect div_resp_val, UInt<1>(0h0) inst DivUnit of DivUnit connect DivUnit.clock, clock connect DivUnit.reset, reset invalidate DivUnit.io.brupdate.b2.target_offset invalidate DivUnit.io.brupdate.b2.jalr_target invalidate DivUnit.io.brupdate.b2.pc_sel invalidate DivUnit.io.brupdate.b2.cfi_type invalidate DivUnit.io.brupdate.b2.taken invalidate DivUnit.io.brupdate.b2.mispredict invalidate DivUnit.io.brupdate.b2.valid invalidate DivUnit.io.brupdate.b2.uop.debug_tsrc invalidate DivUnit.io.brupdate.b2.uop.debug_fsrc invalidate DivUnit.io.brupdate.b2.uop.bp_xcpt_if invalidate DivUnit.io.brupdate.b2.uop.bp_debug_if invalidate DivUnit.io.brupdate.b2.uop.xcpt_ma_if invalidate DivUnit.io.brupdate.b2.uop.xcpt_ae_if invalidate DivUnit.io.brupdate.b2.uop.xcpt_pf_if invalidate DivUnit.io.brupdate.b2.uop.fp_single invalidate DivUnit.io.brupdate.b2.uop.fp_val invalidate DivUnit.io.brupdate.b2.uop.frs3_en invalidate DivUnit.io.brupdate.b2.uop.lrs2_rtype invalidate DivUnit.io.brupdate.b2.uop.lrs1_rtype invalidate DivUnit.io.brupdate.b2.uop.dst_rtype invalidate DivUnit.io.brupdate.b2.uop.ldst_val invalidate DivUnit.io.brupdate.b2.uop.lrs3 invalidate DivUnit.io.brupdate.b2.uop.lrs2 invalidate DivUnit.io.brupdate.b2.uop.lrs1 invalidate DivUnit.io.brupdate.b2.uop.ldst invalidate DivUnit.io.brupdate.b2.uop.ldst_is_rs1 invalidate DivUnit.io.brupdate.b2.uop.flush_on_commit invalidate DivUnit.io.brupdate.b2.uop.is_unique invalidate DivUnit.io.brupdate.b2.uop.is_sys_pc2epc invalidate DivUnit.io.brupdate.b2.uop.uses_stq invalidate DivUnit.io.brupdate.b2.uop.uses_ldq invalidate DivUnit.io.brupdate.b2.uop.is_amo invalidate DivUnit.io.brupdate.b2.uop.is_fencei invalidate DivUnit.io.brupdate.b2.uop.is_fence invalidate DivUnit.io.brupdate.b2.uop.mem_signed invalidate DivUnit.io.brupdate.b2.uop.mem_size invalidate DivUnit.io.brupdate.b2.uop.mem_cmd invalidate DivUnit.io.brupdate.b2.uop.bypassable invalidate DivUnit.io.brupdate.b2.uop.exc_cause invalidate DivUnit.io.brupdate.b2.uop.exception invalidate DivUnit.io.brupdate.b2.uop.stale_pdst invalidate DivUnit.io.brupdate.b2.uop.ppred_busy invalidate DivUnit.io.brupdate.b2.uop.prs3_busy invalidate DivUnit.io.brupdate.b2.uop.prs2_busy invalidate DivUnit.io.brupdate.b2.uop.prs1_busy invalidate DivUnit.io.brupdate.b2.uop.ppred invalidate DivUnit.io.brupdate.b2.uop.prs3 invalidate DivUnit.io.brupdate.b2.uop.prs2 invalidate DivUnit.io.brupdate.b2.uop.prs1 invalidate DivUnit.io.brupdate.b2.uop.pdst invalidate DivUnit.io.brupdate.b2.uop.rxq_idx invalidate DivUnit.io.brupdate.b2.uop.stq_idx invalidate DivUnit.io.brupdate.b2.uop.ldq_idx invalidate DivUnit.io.brupdate.b2.uop.rob_idx invalidate DivUnit.io.brupdate.b2.uop.csr_addr invalidate DivUnit.io.brupdate.b2.uop.imm_packed invalidate DivUnit.io.brupdate.b2.uop.taken invalidate DivUnit.io.brupdate.b2.uop.pc_lob invalidate DivUnit.io.brupdate.b2.uop.edge_inst invalidate DivUnit.io.brupdate.b2.uop.ftq_idx invalidate DivUnit.io.brupdate.b2.uop.br_tag invalidate DivUnit.io.brupdate.b2.uop.br_mask invalidate DivUnit.io.brupdate.b2.uop.is_sfb invalidate DivUnit.io.brupdate.b2.uop.is_jal invalidate DivUnit.io.brupdate.b2.uop.is_jalr invalidate DivUnit.io.brupdate.b2.uop.is_br invalidate DivUnit.io.brupdate.b2.uop.iw_p2_poisoned invalidate DivUnit.io.brupdate.b2.uop.iw_p1_poisoned invalidate DivUnit.io.brupdate.b2.uop.iw_state invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_std invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_sta invalidate DivUnit.io.brupdate.b2.uop.ctrl.is_load invalidate DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd invalidate DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw invalidate DivUnit.io.brupdate.b2.uop.ctrl.op_fcn invalidate DivUnit.io.brupdate.b2.uop.ctrl.imm_sel invalidate DivUnit.io.brupdate.b2.uop.ctrl.op2_sel invalidate DivUnit.io.brupdate.b2.uop.ctrl.op1_sel invalidate DivUnit.io.brupdate.b2.uop.ctrl.br_type invalidate DivUnit.io.brupdate.b2.uop.fu_code invalidate DivUnit.io.brupdate.b2.uop.iq_type invalidate DivUnit.io.brupdate.b2.uop.debug_pc invalidate DivUnit.io.brupdate.b2.uop.is_rvc invalidate DivUnit.io.brupdate.b2.uop.debug_inst invalidate DivUnit.io.brupdate.b2.uop.inst invalidate DivUnit.io.brupdate.b2.uop.uopc invalidate DivUnit.io.brupdate.b1.mispredict_mask invalidate DivUnit.io.brupdate.b1.resolve_mask invalidate DivUnit.io.resp.bits.sfence.bits.hg invalidate DivUnit.io.resp.bits.sfence.bits.hv invalidate DivUnit.io.resp.bits.sfence.bits.asid invalidate DivUnit.io.resp.bits.sfence.bits.addr invalidate DivUnit.io.resp.bits.sfence.bits.rs2 invalidate DivUnit.io.resp.bits.sfence.bits.rs1 invalidate DivUnit.io.resp.bits.sfence.valid invalidate DivUnit.io.resp.bits.mxcpt.bits invalidate DivUnit.io.resp.bits.mxcpt.valid invalidate DivUnit.io.resp.bits.addr invalidate DivUnit.io.resp.bits.fflags.bits.flags invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_tsrc invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_fsrc invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.bp_debug_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_single invalidate DivUnit.io.resp.bits.fflags.bits.uop.fp_val invalidate DivUnit.io.resp.bits.fflags.bits.uop.frs3_en invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate DivUnit.io.resp.bits.fflags.bits.uop.dst_rtype invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_val invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs3 invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs2 invalidate DivUnit.io.resp.bits.fflags.bits.uop.lrs1 invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate DivUnit.io.resp.bits.fflags.bits.uop.flush_on_commit invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_unique invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_stq invalidate DivUnit.io.resp.bits.fflags.bits.uop.uses_ldq invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_amo invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fencei invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_fence invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_signed invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_size invalidate DivUnit.io.resp.bits.fflags.bits.uop.mem_cmd invalidate DivUnit.io.resp.bits.fflags.bits.uop.bypassable invalidate DivUnit.io.resp.bits.fflags.bits.uop.exc_cause invalidate DivUnit.io.resp.bits.fflags.bits.uop.exception invalidate DivUnit.io.resp.bits.fflags.bits.uop.stale_pdst invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1_busy invalidate DivUnit.io.resp.bits.fflags.bits.uop.ppred invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs3 invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs2 invalidate DivUnit.io.resp.bits.fflags.bits.uop.prs1 invalidate DivUnit.io.resp.bits.fflags.bits.uop.pdst invalidate DivUnit.io.resp.bits.fflags.bits.uop.rxq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.stq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.ldq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.rob_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.csr_addr invalidate DivUnit.io.resp.bits.fflags.bits.uop.imm_packed invalidate DivUnit.io.resp.bits.fflags.bits.uop.taken invalidate DivUnit.io.resp.bits.fflags.bits.uop.pc_lob invalidate DivUnit.io.resp.bits.fflags.bits.uop.edge_inst invalidate DivUnit.io.resp.bits.fflags.bits.uop.ftq_idx invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_tag invalidate DivUnit.io.resp.bits.fflags.bits.uop.br_mask invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_sfb invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jal invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_jalr invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_br invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate DivUnit.io.resp.bits.fflags.bits.uop.iw_state invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate DivUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate DivUnit.io.resp.bits.fflags.bits.uop.fu_code invalidate DivUnit.io.resp.bits.fflags.bits.uop.iq_type invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_pc invalidate DivUnit.io.resp.bits.fflags.bits.uop.is_rvc invalidate DivUnit.io.resp.bits.fflags.bits.uop.debug_inst invalidate DivUnit.io.resp.bits.fflags.bits.uop.inst invalidate DivUnit.io.resp.bits.fflags.bits.uop.uopc invalidate DivUnit.io.resp.bits.fflags.valid invalidate DivUnit.io.resp.bits.data invalidate DivUnit.io.resp.bits.predicated invalidate DivUnit.io.resp.bits.uop.debug_tsrc invalidate DivUnit.io.resp.bits.uop.debug_fsrc invalidate DivUnit.io.resp.bits.uop.bp_xcpt_if invalidate DivUnit.io.resp.bits.uop.bp_debug_if invalidate DivUnit.io.resp.bits.uop.xcpt_ma_if invalidate DivUnit.io.resp.bits.uop.xcpt_ae_if invalidate DivUnit.io.resp.bits.uop.xcpt_pf_if invalidate DivUnit.io.resp.bits.uop.fp_single invalidate DivUnit.io.resp.bits.uop.fp_val invalidate DivUnit.io.resp.bits.uop.frs3_en invalidate DivUnit.io.resp.bits.uop.lrs2_rtype invalidate DivUnit.io.resp.bits.uop.lrs1_rtype invalidate DivUnit.io.resp.bits.uop.dst_rtype invalidate DivUnit.io.resp.bits.uop.ldst_val invalidate DivUnit.io.resp.bits.uop.lrs3 invalidate DivUnit.io.resp.bits.uop.lrs2 invalidate DivUnit.io.resp.bits.uop.lrs1 invalidate DivUnit.io.resp.bits.uop.ldst invalidate DivUnit.io.resp.bits.uop.ldst_is_rs1 invalidate DivUnit.io.resp.bits.uop.flush_on_commit invalidate DivUnit.io.resp.bits.uop.is_unique invalidate DivUnit.io.resp.bits.uop.is_sys_pc2epc invalidate DivUnit.io.resp.bits.uop.uses_stq invalidate DivUnit.io.resp.bits.uop.uses_ldq invalidate DivUnit.io.resp.bits.uop.is_amo invalidate DivUnit.io.resp.bits.uop.is_fencei invalidate DivUnit.io.resp.bits.uop.is_fence invalidate DivUnit.io.resp.bits.uop.mem_signed invalidate DivUnit.io.resp.bits.uop.mem_size invalidate DivUnit.io.resp.bits.uop.mem_cmd invalidate DivUnit.io.resp.bits.uop.bypassable invalidate DivUnit.io.resp.bits.uop.exc_cause invalidate DivUnit.io.resp.bits.uop.exception invalidate DivUnit.io.resp.bits.uop.stale_pdst invalidate DivUnit.io.resp.bits.uop.ppred_busy invalidate DivUnit.io.resp.bits.uop.prs3_busy invalidate DivUnit.io.resp.bits.uop.prs2_busy invalidate DivUnit.io.resp.bits.uop.prs1_busy invalidate DivUnit.io.resp.bits.uop.ppred invalidate DivUnit.io.resp.bits.uop.prs3 invalidate DivUnit.io.resp.bits.uop.prs2 invalidate DivUnit.io.resp.bits.uop.prs1 invalidate DivUnit.io.resp.bits.uop.pdst invalidate DivUnit.io.resp.bits.uop.rxq_idx invalidate DivUnit.io.resp.bits.uop.stq_idx invalidate DivUnit.io.resp.bits.uop.ldq_idx invalidate DivUnit.io.resp.bits.uop.rob_idx invalidate DivUnit.io.resp.bits.uop.csr_addr invalidate DivUnit.io.resp.bits.uop.imm_packed invalidate DivUnit.io.resp.bits.uop.taken invalidate DivUnit.io.resp.bits.uop.pc_lob invalidate DivUnit.io.resp.bits.uop.edge_inst invalidate DivUnit.io.resp.bits.uop.ftq_idx invalidate DivUnit.io.resp.bits.uop.br_tag invalidate DivUnit.io.resp.bits.uop.br_mask invalidate DivUnit.io.resp.bits.uop.is_sfb invalidate DivUnit.io.resp.bits.uop.is_jal invalidate DivUnit.io.resp.bits.uop.is_jalr invalidate DivUnit.io.resp.bits.uop.is_br invalidate DivUnit.io.resp.bits.uop.iw_p2_poisoned invalidate DivUnit.io.resp.bits.uop.iw_p1_poisoned invalidate DivUnit.io.resp.bits.uop.iw_state invalidate DivUnit.io.resp.bits.uop.ctrl.is_std invalidate DivUnit.io.resp.bits.uop.ctrl.is_sta invalidate DivUnit.io.resp.bits.uop.ctrl.is_load invalidate DivUnit.io.resp.bits.uop.ctrl.csr_cmd invalidate DivUnit.io.resp.bits.uop.ctrl.fcn_dw invalidate DivUnit.io.resp.bits.uop.ctrl.op_fcn invalidate DivUnit.io.resp.bits.uop.ctrl.imm_sel invalidate DivUnit.io.resp.bits.uop.ctrl.op2_sel invalidate DivUnit.io.resp.bits.uop.ctrl.op1_sel invalidate DivUnit.io.resp.bits.uop.ctrl.br_type invalidate DivUnit.io.resp.bits.uop.fu_code invalidate DivUnit.io.resp.bits.uop.iq_type invalidate DivUnit.io.resp.bits.uop.debug_pc invalidate DivUnit.io.resp.bits.uop.is_rvc invalidate DivUnit.io.resp.bits.uop.debug_inst invalidate DivUnit.io.resp.bits.uop.inst invalidate DivUnit.io.resp.bits.uop.uopc invalidate DivUnit.io.resp.valid invalidate DivUnit.io.resp.ready invalidate DivUnit.io.req.bits.kill invalidate DivUnit.io.req.bits.pred_data invalidate DivUnit.io.req.bits.rs3_data invalidate DivUnit.io.req.bits.rs2_data invalidate DivUnit.io.req.bits.rs1_data invalidate DivUnit.io.req.bits.uop.debug_tsrc invalidate DivUnit.io.req.bits.uop.debug_fsrc invalidate DivUnit.io.req.bits.uop.bp_xcpt_if invalidate DivUnit.io.req.bits.uop.bp_debug_if invalidate DivUnit.io.req.bits.uop.xcpt_ma_if invalidate DivUnit.io.req.bits.uop.xcpt_ae_if invalidate DivUnit.io.req.bits.uop.xcpt_pf_if invalidate DivUnit.io.req.bits.uop.fp_single invalidate DivUnit.io.req.bits.uop.fp_val invalidate DivUnit.io.req.bits.uop.frs3_en invalidate DivUnit.io.req.bits.uop.lrs2_rtype invalidate DivUnit.io.req.bits.uop.lrs1_rtype invalidate DivUnit.io.req.bits.uop.dst_rtype invalidate DivUnit.io.req.bits.uop.ldst_val invalidate DivUnit.io.req.bits.uop.lrs3 invalidate DivUnit.io.req.bits.uop.lrs2 invalidate DivUnit.io.req.bits.uop.lrs1 invalidate DivUnit.io.req.bits.uop.ldst invalidate DivUnit.io.req.bits.uop.ldst_is_rs1 invalidate DivUnit.io.req.bits.uop.flush_on_commit invalidate DivUnit.io.req.bits.uop.is_unique invalidate DivUnit.io.req.bits.uop.is_sys_pc2epc invalidate DivUnit.io.req.bits.uop.uses_stq invalidate DivUnit.io.req.bits.uop.uses_ldq invalidate DivUnit.io.req.bits.uop.is_amo invalidate DivUnit.io.req.bits.uop.is_fencei invalidate DivUnit.io.req.bits.uop.is_fence invalidate DivUnit.io.req.bits.uop.mem_signed invalidate DivUnit.io.req.bits.uop.mem_size invalidate DivUnit.io.req.bits.uop.mem_cmd invalidate DivUnit.io.req.bits.uop.bypassable invalidate DivUnit.io.req.bits.uop.exc_cause invalidate DivUnit.io.req.bits.uop.exception invalidate DivUnit.io.req.bits.uop.stale_pdst invalidate DivUnit.io.req.bits.uop.ppred_busy invalidate DivUnit.io.req.bits.uop.prs3_busy invalidate DivUnit.io.req.bits.uop.prs2_busy invalidate DivUnit.io.req.bits.uop.prs1_busy invalidate DivUnit.io.req.bits.uop.ppred invalidate DivUnit.io.req.bits.uop.prs3 invalidate DivUnit.io.req.bits.uop.prs2 invalidate DivUnit.io.req.bits.uop.prs1 invalidate DivUnit.io.req.bits.uop.pdst invalidate DivUnit.io.req.bits.uop.rxq_idx invalidate DivUnit.io.req.bits.uop.stq_idx invalidate DivUnit.io.req.bits.uop.ldq_idx invalidate DivUnit.io.req.bits.uop.rob_idx invalidate DivUnit.io.req.bits.uop.csr_addr invalidate DivUnit.io.req.bits.uop.imm_packed invalidate DivUnit.io.req.bits.uop.taken invalidate DivUnit.io.req.bits.uop.pc_lob invalidate DivUnit.io.req.bits.uop.edge_inst invalidate DivUnit.io.req.bits.uop.ftq_idx invalidate DivUnit.io.req.bits.uop.br_tag invalidate DivUnit.io.req.bits.uop.br_mask invalidate DivUnit.io.req.bits.uop.is_sfb invalidate DivUnit.io.req.bits.uop.is_jal invalidate DivUnit.io.req.bits.uop.is_jalr invalidate DivUnit.io.req.bits.uop.is_br invalidate DivUnit.io.req.bits.uop.iw_p2_poisoned invalidate DivUnit.io.req.bits.uop.iw_p1_poisoned invalidate DivUnit.io.req.bits.uop.iw_state invalidate DivUnit.io.req.bits.uop.ctrl.is_std invalidate DivUnit.io.req.bits.uop.ctrl.is_sta invalidate DivUnit.io.req.bits.uop.ctrl.is_load invalidate DivUnit.io.req.bits.uop.ctrl.csr_cmd invalidate DivUnit.io.req.bits.uop.ctrl.fcn_dw invalidate DivUnit.io.req.bits.uop.ctrl.op_fcn invalidate DivUnit.io.req.bits.uop.ctrl.imm_sel invalidate DivUnit.io.req.bits.uop.ctrl.op2_sel invalidate DivUnit.io.req.bits.uop.ctrl.op1_sel invalidate DivUnit.io.req.bits.uop.ctrl.br_type invalidate DivUnit.io.req.bits.uop.fu_code invalidate DivUnit.io.req.bits.uop.iq_type invalidate DivUnit.io.req.bits.uop.debug_pc invalidate DivUnit.io.req.bits.uop.is_rvc invalidate DivUnit.io.req.bits.uop.debug_inst invalidate DivUnit.io.req.bits.uop.inst invalidate DivUnit.io.req.bits.uop.uopc invalidate DivUnit.io.req.valid invalidate DivUnit.io.req.ready node _T_11 = and(io.req.bits.uop.fu_code, UInt<10>(0h10)) node _T_12 = neq(_T_11, UInt<1>(0h0)) node _T_13 = and(io.req.valid, _T_12) node _T_14 = and(_T_13, UInt<1>(0h1)) connect DivUnit.io.req.valid, _T_14 connect DivUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect DivUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect DivUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect DivUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect DivUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect DivUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect DivUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect DivUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect DivUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect DivUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect DivUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect DivUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect DivUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect DivUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect DivUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect DivUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect DivUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect DivUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect DivUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect DivUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect DivUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect DivUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect DivUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect DivUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect DivUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect DivUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect DivUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect DivUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect DivUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect DivUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect DivUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect DivUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect DivUnit.io.req.bits.uop.exception, io.req.bits.uop.exception connect DivUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect DivUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect DivUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect DivUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect DivUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect DivUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect DivUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect DivUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect DivUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect DivUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect DivUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect DivUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect DivUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect DivUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect DivUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect DivUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect DivUnit.io.req.bits.uop.taken, io.req.bits.uop.taken connect DivUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect DivUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect DivUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect DivUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect DivUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect DivUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect DivUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect DivUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect DivUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect DivUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect DivUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect DivUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect DivUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect DivUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect DivUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect DivUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect DivUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect DivUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect DivUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect DivUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect DivUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect DivUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect DivUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect DivUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect DivUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect DivUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect DivUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect DivUnit.io.req.bits.uop.inst, io.req.bits.uop.inst connect DivUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect DivUnit.io.req.bits.rs1_data, io.req.bits.rs1_data connect DivUnit.io.req.bits.rs2_data, io.req.bits.rs2_data connect DivUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect DivUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect DivUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect DivUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect DivUnit.io.brupdate.b2.taken, io.brupdate.b2.taken connect DivUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect DivUnit.io.brupdate.b2.valid, io.brupdate.b2.valid connect DivUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect DivUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect DivUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect DivUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect DivUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect DivUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect DivUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect DivUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect DivUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect DivUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect DivUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect DivUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect DivUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect DivUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect DivUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect DivUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect DivUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect DivUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect DivUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect DivUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect DivUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect DivUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect DivUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect DivUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect DivUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect DivUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect DivUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect DivUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect DivUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect DivUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect DivUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect DivUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect DivUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect DivUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect DivUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect DivUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect DivUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect DivUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect DivUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect DivUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect DivUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect DivUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect DivUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect DivUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect DivUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect DivUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect DivUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect DivUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect DivUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect DivUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect DivUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect DivUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect DivUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect DivUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect DivUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect DivUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect DivUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect DivUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect DivUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect DivUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect DivUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect DivUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect DivUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect DivUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect DivUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect DivUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect DivUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect DivUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect DivUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect DivUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect DivUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect DivUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect DivUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect DivUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect DivUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect DivUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect DivUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect DivUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect DivUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect DivUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect DivUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect DivUnit.io.req.bits.kill, io.req.bits.kill node _T_15 = eq(ALUUnit.io.resp.valid, UInt<1>(0h0)) connect DivUnit.io.resp.ready, _T_15 connect div_resp_val, DivUnit.io.resp.valid node _div_busy_T = eq(DivUnit.io.req.ready, UInt<1>(0h0)) node _div_busy_T_1 = and(io.req.bits.uop.fu_code, UInt<10>(0h10)) node _div_busy_T_2 = neq(_div_busy_T_1, UInt<1>(0h0)) node _div_busy_T_3 = and(io.req.valid, _div_busy_T_2) node _div_busy_T_4 = or(_div_busy_T, _div_busy_T_3) connect div_busy, _div_busy_T_4 node _io_iresp_valid_T = or(ALUUnit.io.resp.valid, DivUnit.io.resp.valid) connect io.iresp.valid, _io_iresp_valid_T node _io_iresp_bits_uop_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.uop, DivUnit.io.resp.bits.uop) connect io.iresp.bits.uop, _io_iresp_bits_uop_T node _io_iresp_bits_data_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.data, DivUnit.io.resp.bits.data) connect io.iresp.bits.data, _io_iresp_bits_data_T node _io_iresp_bits_predicated_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.predicated, DivUnit.io.resp.bits.predicated) connect io.iresp.bits.predicated, _io_iresp_bits_predicated_T node _io_iresp_bits_uop_csr_addr_sign_T = bits(ALUUnit.io.resp.bits.uop.imm_packed, 19, 19) node io_iresp_bits_uop_csr_addr_sign = asSInt(_io_iresp_bits_uop_csr_addr_sign_T) node _io_iresp_bits_uop_csr_addr_i30_20_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i30_20_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 8) node _io_iresp_bits_uop_csr_addr_i30_20_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i30_20_T_1) node io_iresp_bits_uop_csr_addr_i30_20 = mux(_io_iresp_bits_uop_csr_addr_i30_20_T, _io_iresp_bits_uop_csr_addr_i30_20_T_2, io_iresp_bits_uop_csr_addr_sign) node _io_iresp_bits_uop_csr_addr_i19_12_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i19_12_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4)) node _io_iresp_bits_uop_csr_addr_i19_12_T_2 = or(_io_iresp_bits_uop_csr_addr_i19_12_T, _io_iresp_bits_uop_csr_addr_i19_12_T_1) node _io_iresp_bits_uop_csr_addr_i19_12_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 7, 0) node _io_iresp_bits_uop_csr_addr_i19_12_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i19_12_T_3) node io_iresp_bits_uop_csr_addr_i19_12 = mux(_io_iresp_bits_uop_csr_addr_i19_12_T_2, _io_iresp_bits_uop_csr_addr_i19_12_T_4, io_iresp_bits_uop_csr_addr_sign) node _io_iresp_bits_uop_csr_addr_i11_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i11_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4)) node _io_iresp_bits_uop_csr_addr_i11_T_2 = eq(UInt<3>(0h0), UInt<3>(0h2)) node _io_iresp_bits_uop_csr_addr_i11_T_3 = or(_io_iresp_bits_uop_csr_addr_i11_T_1, _io_iresp_bits_uop_csr_addr_i11_T_2) node _io_iresp_bits_uop_csr_addr_i11_T_4 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8) node _io_iresp_bits_uop_csr_addr_i11_T_5 = asSInt(_io_iresp_bits_uop_csr_addr_i11_T_4) node _io_iresp_bits_uop_csr_addr_i11_T_6 = mux(_io_iresp_bits_uop_csr_addr_i11_T_3, _io_iresp_bits_uop_csr_addr_i11_T_5, io_iresp_bits_uop_csr_addr_sign) node io_iresp_bits_uop_csr_addr_i11 = mux(_io_iresp_bits_uop_csr_addr_i11_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i11_T_6) node _io_iresp_bits_uop_csr_addr_i10_5_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i10_5_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 14) node _io_iresp_bits_uop_csr_addr_i10_5_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i10_5_T_1) node io_iresp_bits_uop_csr_addr_i10_5 = mux(_io_iresp_bits_uop_csr_addr_i10_5_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i10_5_T_2) node _io_iresp_bits_uop_csr_addr_i4_1_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i4_1_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 13, 9) node _io_iresp_bits_uop_csr_addr_i4_1_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i4_1_T_1) node io_iresp_bits_uop_csr_addr_i4_1 = mux(_io_iresp_bits_uop_csr_addr_i4_1_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i4_1_T_2) node _io_iresp_bits_uop_csr_addr_i0_T = eq(UInt<3>(0h0), UInt<3>(0h1)) node _io_iresp_bits_uop_csr_addr_i0_T_1 = eq(UInt<3>(0h0), UInt<3>(0h0)) node _io_iresp_bits_uop_csr_addr_i0_T_2 = or(_io_iresp_bits_uop_csr_addr_i0_T, _io_iresp_bits_uop_csr_addr_i0_T_1) node _io_iresp_bits_uop_csr_addr_i0_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8) node _io_iresp_bits_uop_csr_addr_i0_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i0_T_3) node io_iresp_bits_uop_csr_addr_i0 = mux(_io_iresp_bits_uop_csr_addr_i0_T_2, _io_iresp_bits_uop_csr_addr_i0_T_4, asSInt(UInt<1>(0h0))) node io_iresp_bits_uop_csr_addr_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i0) node io_iresp_bits_uop_csr_addr_lo_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i4_1) node io_iresp_bits_uop_csr_addr_lo_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_i10_5) node io_iresp_bits_uop_csr_addr_lo_hi = cat(io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo) node io_iresp_bits_uop_csr_addr_lo = cat(io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo) node io_iresp_bits_uop_csr_addr_hi_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i11) node io_iresp_bits_uop_csr_addr_hi_lo_hi = asUInt(io_iresp_bits_uop_csr_addr_i19_12) node io_iresp_bits_uop_csr_addr_hi_lo = cat(io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo) node io_iresp_bits_uop_csr_addr_hi_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i30_20) node io_iresp_bits_uop_csr_addr_hi_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_sign) node io_iresp_bits_uop_csr_addr_hi_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo) node io_iresp_bits_uop_csr_addr_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo) node _io_iresp_bits_uop_csr_addr_T = cat(io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo) node _io_iresp_bits_uop_csr_addr_T_1 = asSInt(_io_iresp_bits_uop_csr_addr_T) node _io_iresp_bits_uop_csr_addr_T_2 = asUInt(_io_iresp_bits_uop_csr_addr_T_1) connect io.iresp.bits.uop.csr_addr, _io_iresp_bits_uop_csr_addr_T_2 connect io.iresp.bits.uop.ctrl.csr_cmd, ALUUnit.io.resp.bits.uop.ctrl.csr_cmd node _T_16 = add(ALUUnit.io.resp.valid, DivUnit.io.resp.valid) node _T_17 = bits(_T_16, 1, 0) node _T_18 = leq(_T_17, UInt<1>(0h1)) node _T_19 = eq(div_resp_val, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = add(ALUUnit.io.resp.valid, DivUnit.io.resp.valid) node _T_22 = bits(_T_21, 1, 0) node _T_23 = leq(_T_22, UInt<2>(0h2)) node _T_24 = and(_T_23, div_resp_val) node _T_25 = or(_T_20, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: Multiple functional units are fighting over the write port.\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1

module ALUExeUnit_1( // @[execution-unit.scala:204:7] input clock, // @[execution-unit.scala:204:7] input reset, // @[execution-unit.scala:204:7] output [9:0] io_fu_types, // @[execution-unit.scala:104:14] input io_req_valid, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14] input [15:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14] input io_req_bits_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_req_bits_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14] input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14] input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14] input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14] input io_req_bits_kill, // @[execution-unit.scala:104:14] output io_iresp_valid, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_iresp_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_iresp_bits_data, // @[execution-unit.scala:104:14] output io_bypass_0_valid, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_bypass_0_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_bypass_0_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_bypass_0_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_bypass_0_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_bypass_0_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_bypass_0_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_bypass_0_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_bypass_0_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_bypass_0_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_bypass_0_bits_data, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14] input io_brupdate_b2_valid, // @[execution-unit.scala:104:14] input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14] input io_brupdate_b2_taken, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14] input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_brinfo_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_brinfo_uop_debug_inst, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_brinfo_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_brinfo_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_brinfo_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_iw_state, // @[execution-unit.scala:104:14] output io_brinfo_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_brinfo_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_br, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_jalr, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_jal, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_brinfo_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_brinfo_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_brinfo_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_pc_lob, // @[execution-unit.scala:104:14] output io_brinfo_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_brinfo_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_brinfo_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ppred, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_brinfo_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_brinfo_uop_exc_cause, // @[execution-unit.scala:104:14] output io_brinfo_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_mem_size, // @[execution-unit.scala:104:14] output io_brinfo_uop_mem_signed, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_fence, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_fencei, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_amo, // @[execution-unit.scala:104:14] output io_brinfo_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_brinfo_uop_uses_stq, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_unique, // @[execution-unit.scala:104:14] output io_brinfo_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_brinfo_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs3, // @[execution-unit.scala:104:14] output io_brinfo_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_brinfo_uop_frs3_en, // @[execution-unit.scala:104:14] output io_brinfo_uop_fp_val, // @[execution-unit.scala:104:14] output io_brinfo_uop_fp_single, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_debug_tsrc, // @[execution-unit.scala:104:14] output io_brinfo_valid, // @[execution-unit.scala:104:14] output io_brinfo_mispredict, // @[execution-unit.scala:104:14] output io_brinfo_taken, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_cfi_type, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_pc_sel, // @[execution-unit.scala:104:14] output [39:0] io_brinfo_jalr_target, // @[execution-unit.scala:104:14] output [20:0] io_brinfo_target_offset, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_idx_valid, // @[execution-unit.scala:104:14] input [2:0] io_get_ftq_pc_entry_cfi_idx_bits, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_taken, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_mispredicted, // @[execution-unit.scala:104:14] input [2:0] io_get_ftq_pc_entry_cfi_type, // @[execution-unit.scala:104:14] input [7:0] io_get_ftq_pc_entry_br_mask, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_is_call, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_is_ret, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_cfi_npc_plus4, // @[execution-unit.scala:104:14] input [39:0] io_get_ftq_pc_entry_ras_top, // @[execution-unit.scala:104:14] input [4:0] io_get_ftq_pc_entry_ras_idx, // @[execution-unit.scala:104:14] input io_get_ftq_pc_entry_start_bank, // @[execution-unit.scala:104:14] input [39:0] io_get_ftq_pc_pc, // @[execution-unit.scala:104:14] input io_get_ftq_pc_next_val, // @[execution-unit.scala:104:14] input [39:0] io_get_ftq_pc_next_pc, // @[execution-unit.scala:104:14] input io_status_debug, // @[execution-unit.scala:104:14] input io_status_cease, // @[execution-unit.scala:104:14] input io_status_wfi, // @[execution-unit.scala:104:14] input [1:0] io_status_dprv, // @[execution-unit.scala:104:14] input io_status_dv, // @[execution-unit.scala:104:14] input [1:0] io_status_prv, // @[execution-unit.scala:104:14] input io_status_v, // @[execution-unit.scala:104:14] input io_status_sd, // @[execution-unit.scala:104:14] input io_status_mpv, // @[execution-unit.scala:104:14] input io_status_gva, // @[execution-unit.scala:104:14] input io_status_tsr, // @[execution-unit.scala:104:14] input io_status_tw, // @[execution-unit.scala:104:14] input io_status_tvm, // @[execution-unit.scala:104:14] input io_status_mxr, // @[execution-unit.scala:104:14] input io_status_sum, // @[execution-unit.scala:104:14] input io_status_mprv, // @[execution-unit.scala:104:14] input [1:0] io_status_fs, // @[execution-unit.scala:104:14] input [1:0] io_status_mpp, // @[execution-unit.scala:104:14] input io_status_spp, // @[execution-unit.scala:104:14] input io_status_mpie, // @[execution-unit.scala:104:14] input io_status_spie, // @[execution-unit.scala:104:14] input io_status_mie, // @[execution-unit.scala:104:14] input io_status_sie // @[execution-unit.scala:104:14] ); wire _DivUnit_io_req_ready; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_valid; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:366:17] wire [31:0] _DivUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:366:17] wire [31:0] _DivUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:366:17] wire [39:0] _DivUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:366:17] wire [9:0] _DivUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:366:17] wire [3:0] _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:366:17] wire [2:0] _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:366:17] wire [15:0] _DivUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:366:17] wire [3:0] _DivUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:366:17] wire [19:0] _DivUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:366:17] wire [11:0] _DivUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:366:17] wire [6:0] _DivUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:366:17] wire [63:0] _DivUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:366:17] wire [4:0] _DivUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:366:17] wire [5:0] _DivUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:366:17] wire _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:366:17] wire [1:0] _DivUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:366:17] wire [63:0] _DivUnit_io_resp_bits_data; // @[execution-unit.scala:366:17] wire _ALUUnit_io_resp_valid; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:271:17] wire [31:0] _ALUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:271:17] wire [31:0] _ALUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:271:17] wire [39:0] _ALUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:271:17] wire [9:0] _ALUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:271:17] wire [3:0] _ALUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:271:17] wire [15:0] _ALUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:271:17] wire [3:0] _ALUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:271:17] wire [19:0] _ALUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:271:17] wire [11:0] _ALUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_resp_bits_data; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_bypass_0_bits_data; // @[execution-unit.scala:271:17] wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:204:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:204:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:204:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:204:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:204:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:204:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:204:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:204:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:204:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:204:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:204:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:204:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:204:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:204:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:204:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:204:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:204:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:204:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:204:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:204:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:204:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:204:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:204:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:204:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:204:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:204:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:204:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:204:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:204:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:204:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:204:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:204:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:204:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:204:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:204:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_idx_valid_0 = io_get_ftq_pc_entry_cfi_idx_valid; // @[execution-unit.scala:204:7] wire [2:0] io_get_ftq_pc_entry_cfi_idx_bits_0 = io_get_ftq_pc_entry_cfi_idx_bits; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_taken_0 = io_get_ftq_pc_entry_cfi_taken; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_mispredicted_0 = io_get_ftq_pc_entry_cfi_mispredicted; // @[execution-unit.scala:204:7] wire [2:0] io_get_ftq_pc_entry_cfi_type_0 = io_get_ftq_pc_entry_cfi_type; // @[execution-unit.scala:204:7] wire [7:0] io_get_ftq_pc_entry_br_mask_0 = io_get_ftq_pc_entry_br_mask; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_is_call_0 = io_get_ftq_pc_entry_cfi_is_call; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_is_ret_0 = io_get_ftq_pc_entry_cfi_is_ret; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_cfi_npc_plus4_0 = io_get_ftq_pc_entry_cfi_npc_plus4; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_entry_ras_top_0 = io_get_ftq_pc_entry_ras_top; // @[execution-unit.scala:204:7] wire [4:0] io_get_ftq_pc_entry_ras_idx_0 = io_get_ftq_pc_entry_ras_idx; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_entry_start_bank_0 = io_get_ftq_pc_entry_start_bank; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_pc_0 = io_get_ftq_pc_pc; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_next_val_0 = io_get_ftq_pc_next_val; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_next_pc_0 = io_get_ftq_pc_next_pc; // @[execution-unit.scala:204:7] wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:204:7] wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:204:7] wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:204:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:204:7] wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:204:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:204:7] wire io_status_v_0 = io_status_v; // @[execution-unit.scala:204:7] wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:204:7] wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:204:7] wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:204:7] wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:204:7] wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:204:7] wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:204:7] wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:204:7] wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:204:7] wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:204:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:204:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:204:7] wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:204:7] wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:204:7] wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:204:7] wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:204:7] wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:204:7] wire io_req_ready = 1'h0; // @[execution-unit.scala:204:7] wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_get_ftq_pc_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_status_mbe = 1'h0; // @[execution-unit.scala:204:7] wire io_status_sbe = 1'h0; // @[execution-unit.scala:204:7] wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:204:7] wire io_status_ube = 1'h0; // @[execution-unit.scala:204:7] wire io_status_upie = 1'h0; // @[execution-unit.scala:204:7] wire io_status_hie = 1'h0; // @[execution-unit.scala:204:7] wire io_status_uie = 1'h0; // @[execution-unit.scala:204:7] wire ifpu_busy = 1'h0; // @[execution-unit.scala:254:27] wire _io_fu_types_T_12 = 1'h0; // @[execution-unit.scala:265:33] wire _io_iresp_bits_predicated_T = 1'h0; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_csr_addr_i30_20_T = 1'h0; // @[util.scala:274:27] wire _io_iresp_bits_uop_csr_addr_i19_12_T = 1'h0; // @[util.scala:275:27] wire _io_iresp_bits_uop_csr_addr_i19_12_T_1 = 1'h0; // @[util.scala:275:44] wire _io_iresp_bits_uop_csr_addr_i19_12_T_2 = 1'h0; // @[util.scala:275:36] wire _io_iresp_bits_uop_csr_addr_i11_T = 1'h0; // @[util.scala:276:27] wire _io_iresp_bits_uop_csr_addr_i11_T_1 = 1'h0; // @[util.scala:277:27] wire _io_iresp_bits_uop_csr_addr_i11_T_2 = 1'h0; // @[util.scala:277:44] wire _io_iresp_bits_uop_csr_addr_i11_T_3 = 1'h0; // @[util.scala:277:36] wire _io_iresp_bits_uop_csr_addr_i10_5_T = 1'h0; // @[util.scala:278:27] wire _io_iresp_bits_uop_csr_addr_i4_1_T = 1'h0; // @[util.scala:279:27] wire _io_iresp_bits_uop_csr_addr_i0_T = 1'h0; // @[util.scala:280:27] wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:204:7] wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:204:7] wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[execution-unit.scala:204:7] wire io_iresp_ready = 1'h1; // @[execution-unit.scala:204:7] wire _io_fu_types_T_11 = 1'h1; // @[execution-unit.scala:265:22] wire _io_iresp_bits_uop_csr_addr_i0_T_1 = 1'h1; // @[util.scala:280:44] wire _io_iresp_bits_uop_csr_addr_i0_T_2 = 1'h1; // @[util.scala:280:36] wire [6:0] io_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [39:0] io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_get_ftq_pc_com_pc = 40'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [9:0] io_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] _io_fu_types_T_1 = 10'h0; // @[execution-unit.scala:261:21] wire [9:0] _io_fu_types_T_7 = 10'h0; // @[execution-unit.scala:263:21] wire [9:0] _io_fu_types_T_13 = 10'h0; // @[execution-unit.scala:265:21] wire [9:0] _io_fu_types_T_15 = 10'h0; // @[execution-unit.scala:266:21] wire [3:0] io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_get_ftq_pc_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_get_ftq_pc_ghist_ras_idx = 5'h0; // @[execution-unit.scala:204:7] wire [15:0] io_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [19:0] io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [11:0] io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [63:0] io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [63:0] io_get_ftq_pc_ghist_old_history = 64'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:204:7] wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:204:7] wire [9:0] _io_fu_types_T_9 = 10'h2; // @[execution-unit.scala:264:21] wire [9:0] _io_fu_types_T = 10'h1; // @[execution-unit.scala:260:21] wire [9:0] _io_fu_types_T_2 = 10'h1; // @[execution-unit.scala:260:45] wire [9:0] _io_fu_types_T_16; // @[execution-unit.scala:265:60] wire _io_iresp_valid_T; // @[execution-unit.scala:409:71] wire [6:0] _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70] wire [31:0] _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70] wire [31:0] _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] wire [39:0] _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] wire [9:0] _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] wire [3:0] _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] wire [15:0] _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] wire [3:0] _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70] wire [19:0] _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70] wire [63:0] _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [3:0] io_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_iresp_bits_data_0; // @[execution-unit.scala:204:7] wire io_iresp_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_0_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_0_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_0_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_0_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_0_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_0_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_bypass_0_bits_data_0; // @[execution-unit.scala:204:7] wire io_bypass_0_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_brinfo_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_brinfo_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_brinfo_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_brinfo_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_brinfo_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_brinfo_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_brinfo_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_brinfo_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_brinfo_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire io_brinfo_valid_0; // @[execution-unit.scala:204:7] wire io_brinfo_mispredict_0; // @[execution-unit.scala:204:7] wire io_brinfo_taken_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_cfi_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_pc_sel_0; // @[execution-unit.scala:204:7] wire [39:0] io_brinfo_jalr_target_0; // @[execution-unit.scala:204:7] wire [20:0] io_brinfo_target_offset_0; // @[execution-unit.scala:204:7] wire [9:0] io_fu_types_0; // @[execution-unit.scala:204:7] wire _div_busy_T_4; // @[execution-unit.scala:379:39] wire div_busy; // @[execution-unit.scala:253:27] wire _io_fu_types_T_3 = ~div_busy; // @[execution-unit.scala:253:27, :262:22] wire _io_fu_types_T_4 = _io_fu_types_T_3; // @[execution-unit.scala:262:{22,32}] wire [9:0] _io_fu_types_T_5 = {5'h0, _io_fu_types_T_4, 4'h0}; // @[execution-unit.scala:262:{21,32}] wire [9:0] _io_fu_types_T_6 = _io_fu_types_T_5 | 10'h1; // @[execution-unit.scala:261:45, :262:21] wire [9:0] _io_fu_types_T_8 = _io_fu_types_T_6; // @[execution-unit.scala:261:45, :262:58] wire [9:0] _io_fu_types_T_10 = _io_fu_types_T_8 | 10'h2; // @[execution-unit.scala:262:58, :263:45] wire [9:0] _io_fu_types_T_14 = _io_fu_types_T_10; // @[execution-unit.scala:263:45, :264:49] assign _io_fu_types_T_16 = _io_fu_types_T_14; // @[execution-unit.scala:264:49, :265:60] assign io_fu_types_0 = _io_fu_types_T_16; // @[execution-unit.scala:204:7, :265:60] assign io_bypass_0_bits_data_0 = {1'h0, _ALUUnit_io_bypass_0_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15] wire div_resp_val; // @[execution-unit.scala:364:30] wire [9:0] _div_busy_T_1 = io_req_bits_uop_fu_code_0 & 10'h10; // @[execution-unit.scala:204:7] wire _div_busy_T = ~_DivUnit_io_req_ready; // @[execution-unit.scala:366:17, :379:21] wire _div_busy_T_2 = |_div_busy_T_1; // @[micro-op.scala:154:{40,47}] wire _div_busy_T_3 = io_req_valid_0 & _div_busy_T_2; // @[execution-unit.scala:204:7, :380:35] assign _div_busy_T_4 = _div_busy_T | _div_busy_T_3; // @[execution-unit.scala:379:{21,39}, :380:35] assign div_busy = _div_busy_T_4; // @[execution-unit.scala:253:27, :379:39] assign _io_iresp_valid_T = _ALUUnit_io_resp_valid | _DivUnit_io_resp_valid; // @[execution-unit.scala:271:17, :366:17, :409:71] assign io_iresp_valid_0 = _io_iresp_valid_T; // @[execution-unit.scala:204:7, :409:71] assign _io_iresp_bits_uop_T_uopc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uopc : _DivUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_inst : _DivUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_inst : _DivUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_rvc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_rvc : _DivUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_pc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_pc : _DivUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iq_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iq_type : _DivUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fu_code = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fu_code : _DivUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_br_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_br_type : _DivUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op1_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op1_sel : _DivUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op2_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op2_sel : _DivUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_imm_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_imm_sel : _DivUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op_fcn = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op_fcn : _DivUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_fcn_dw = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw : _DivUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_csr_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd : _DivUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_load = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_load : _DivUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_sta = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_sta : _DivUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_std = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_std : _DivUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_state = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_state : _DivUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_p1_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p1_poisoned : _DivUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_p2_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p2_poisoned : _DivUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_br = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_br : _DivUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_jalr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jalr : _DivUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_jal = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jal : _DivUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_sfb = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sfb : _DivUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_br_mask = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_mask : _DivUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_br_tag = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_tag : _DivUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ftq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ftq_idx : _DivUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_edge_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_edge_inst : _DivUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_pc_lob = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pc_lob : _DivUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_taken = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_taken : _DivUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_imm_packed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_imm_packed : _DivUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70] wire [11:0] _io_iresp_bits_uop_T_csr_addr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_csr_addr : _DivUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_rob_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rob_idx : _DivUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldq_idx : _DivUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_stq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stq_idx : _DivUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_rxq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rxq_idx : _DivUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pdst : _DivUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1 : _DivUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2 : _DivUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3 : _DivUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ppred = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred : _DivUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs1_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1_busy : _DivUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs2_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2_busy : _DivUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs3_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3_busy : _DivUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ppred_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred_busy : _DivUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_stale_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stale_pdst : _DivUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_exception = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exception : _DivUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_exc_cause = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exc_cause : _DivUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bypassable = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bypassable : _DivUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_cmd : _DivUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_size = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_size : _DivUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_signed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_signed : _DivUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_fence = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fence : _DivUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_fencei = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fencei : _DivUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_amo = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_amo : _DivUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_uses_ldq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_ldq : _DivUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_uses_stq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_stq : _DivUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_sys_pc2epc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sys_pc2epc : _DivUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_unique = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_unique : _DivUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_flush_on_commit = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_flush_on_commit : _DivUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst_is_rs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_is_rs1 : _DivUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst : _DivUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1 : _DivUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2 : _DivUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs3 : _DivUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_val : _DivUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_dst_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_dst_rtype : _DivUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs1_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1_rtype : _DivUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs2_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2_rtype : _DivUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_frs3_en = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_frs3_en : _DivUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fp_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_val : _DivUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fp_single = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_single : _DivUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_pf_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_pf_if : _DivUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_ae_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ae_if : _DivUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_ma_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ma_if : _DivUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bp_debug_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_debug_if : _DivUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bp_xcpt_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_xcpt_if : _DivUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_fsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_fsrc : _DivUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_tsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_tsrc : _DivUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uopc_0 = _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_inst_0 = _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_inst_0 = _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_rvc_0 = _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_pc_0 = _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iq_type_0 = _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fu_code_0 = _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_br_type_0 = _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op1_sel_0 = _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op2_sel_0 = _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_imm_sel_0 = _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op_fcn_0 = _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_fcn_dw_0 = _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_load_0 = _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_sta_0 = _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_std_0 = _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_state_0 = _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_p1_poisoned_0 = _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_p2_poisoned_0 = _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_br_0 = _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_jalr_0 = _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_jal_0 = _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_sfb_0 = _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] assign io_iresp_bits_uop_br_mask_0 = _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] assign io_iresp_bits_uop_br_tag_0 = _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ftq_idx_0 = _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_edge_inst_0 = _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_pc_lob_0 = _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] assign io_iresp_bits_uop_taken_0 = _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70] assign io_iresp_bits_uop_imm_packed_0 = _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] assign io_iresp_bits_uop_rob_idx_0 = _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldq_idx_0 = _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_stq_idx_0 = _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_rxq_idx_0 = _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_pdst_0 = _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs1_0 = _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs2_0 = _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs3_0 = _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ppred_0 = _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs1_busy_0 = _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs2_busy_0 = _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs3_busy_0 = _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ppred_busy_0 = _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_stale_pdst_0 = _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_exception_0 = _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70] assign io_iresp_bits_uop_exc_cause_0 = _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bypassable_0 = _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_cmd_0 = _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_size_0 = _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_signed_0 = _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_fence_0 = _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_fencei_0 = _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_amo_0 = _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uses_ldq_0 = _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uses_stq_0 = _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_sys_pc2epc_0 = _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_unique_0 = _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] assign io_iresp_bits_uop_flush_on_commit_0 = _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_is_rs1_0 = _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_0 = _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs1_0 = _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs2_0 = _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs3_0 = _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_val_0 = _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] assign io_iresp_bits_uop_dst_rtype_0 = _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs1_rtype_0 = _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs2_rtype_0 = _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_frs3_en_0 = _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fp_val_0 = _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fp_single_0 = _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_pf_if_0 = _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_ae_if_0 = _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_ma_if_0 = _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bp_debug_if_0 = _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bp_xcpt_if_0 = _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_fsrc_0 = _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_tsrc_0 = _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [63:0] _io_iresp_bits_data_T = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_data : _DivUnit_io_resp_bits_data; // @[Mux.scala:50:70] assign io_iresp_bits_data_0 = {1'h0, _io_iresp_bits_data_T}; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_csr_addr_sign_T = _ALUUnit_io_resp_bits_uop_imm_packed[19]; // @[util.scala:273:18] wire io_iresp_bits_uop_csr_addr_sign = _io_iresp_bits_uop_csr_addr_sign_T; // @[util.scala:273:{18,37}] wire _io_iresp_bits_uop_csr_addr_i11_T_6 = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :277:21] wire io_iresp_bits_uop_csr_addr_hi_hi_hi = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :282:15] wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:8]; // @[util.scala:274:39] wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_2 = _io_iresp_bits_uop_csr_addr_i30_20_T_1; // @[util.scala:274:{39,46}] wire [10:0] io_iresp_bits_uop_csr_addr_i30_20 = {11{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :274:21] wire [10:0] io_iresp_bits_uop_csr_addr_hi_hi_lo = io_iresp_bits_uop_csr_addr_i30_20; // @[util.scala:274:21, :282:15] wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[7:0]; // @[util.scala:275:56] wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_4 = _io_iresp_bits_uop_csr_addr_i19_12_T_3; // @[util.scala:275:{56,62}] wire [7:0] io_iresp_bits_uop_csr_addr_i19_12 = {8{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :275:21] wire [7:0] io_iresp_bits_uop_csr_addr_hi_lo_hi = io_iresp_bits_uop_csr_addr_i19_12; // @[util.scala:275:21, :282:15] wire _io_iresp_bits_uop_csr_addr_i11_T_4 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56] wire _io_iresp_bits_uop_csr_addr_i0_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56, :280:56] wire _io_iresp_bits_uop_csr_addr_i11_T_5 = _io_iresp_bits_uop_csr_addr_i11_T_4; // @[util.scala:277:{56,60}] wire io_iresp_bits_uop_csr_addr_i11 = _io_iresp_bits_uop_csr_addr_i11_T_6; // @[util.scala:276:21, :277:21] wire io_iresp_bits_uop_csr_addr_hi_lo_lo = io_iresp_bits_uop_csr_addr_i11; // @[util.scala:276:21, :282:15] wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:14]; // @[util.scala:278:44] wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_2 = _io_iresp_bits_uop_csr_addr_i10_5_T_1; // @[util.scala:278:{44,52}] wire [4:0] io_iresp_bits_uop_csr_addr_i10_5 = _io_iresp_bits_uop_csr_addr_i10_5_T_2; // @[util.scala:278:{21,52}] wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_hi = io_iresp_bits_uop_csr_addr_i10_5; // @[util.scala:278:21, :282:15] wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[13:9]; // @[util.scala:279:44] wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_2 = _io_iresp_bits_uop_csr_addr_i4_1_T_1; // @[util.scala:279:{44,51}] wire [4:0] io_iresp_bits_uop_csr_addr_i4_1 = _io_iresp_bits_uop_csr_addr_i4_1_T_2; // @[util.scala:279:{21,51}] wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_lo = io_iresp_bits_uop_csr_addr_i4_1; // @[util.scala:279:21, :282:15] wire _io_iresp_bits_uop_csr_addr_i0_T_4 = _io_iresp_bits_uop_csr_addr_i0_T_3; // @[util.scala:280:{56,60}] wire io_iresp_bits_uop_csr_addr_i0 = _io_iresp_bits_uop_csr_addr_i0_T_4; // @[util.scala:280:{21,60}] wire io_iresp_bits_uop_csr_addr_lo_lo = io_iresp_bits_uop_csr_addr_i0; // @[util.scala:280:21, :282:15] wire [9:0] io_iresp_bits_uop_csr_addr_lo_hi = {io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo}; // @[util.scala:282:15] wire [10:0] io_iresp_bits_uop_csr_addr_lo = {io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo}; // @[util.scala:282:15] wire [8:0] io_iresp_bits_uop_csr_addr_hi_lo = {io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo}; // @[util.scala:282:15] wire [11:0] io_iresp_bits_uop_csr_addr_hi_hi = {io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo}; // @[util.scala:282:15] wire [20:0] io_iresp_bits_uop_csr_addr_hi = {io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo}; // @[util.scala:282:15] wire [31:0] _io_iresp_bits_uop_csr_addr_T = {io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo}; // @[util.scala:282:15] wire [31:0] _io_iresp_bits_uop_csr_addr_T_1 = _io_iresp_bits_uop_csr_addr_T; // @[util.scala:282:{15,60}] wire [31:0] _io_iresp_bits_uop_csr_addr_T_2 = _io_iresp_bits_uop_csr_addr_T_1; // @[util.scala:282:60] assign io_iresp_bits_uop_csr_addr_0 = _io_iresp_bits_uop_csr_addr_T_2[11:0]; // @[execution-unit.scala:204:7, :420:{34,83}]

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_51 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_51( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_55 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_55( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<13>(0h1000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_27, _T_32) node _T_69 = or(_T_68, _T_37) node _T_70 = or(_T_69, _T_42) node _T_71 = or(_T_70, _T_47) node _T_72 = or(_T_71, _T_52) node _T_73 = or(_T_72, _T_57) node _T_74 = or(_T_73, _T_62) node _T_75 = or(_T_74, _T_67) node _T_76 = and(_T_22, _T_75) node _T_77 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_78 = or(UInt<1>(0h0), _T_77) node _T_79 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<17>(0h10000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<29>(0h10000000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = and(_T_78, _T_89) node _T_91 = or(UInt<1>(0h0), _T_76) node _T_92 = or(_T_91, _T_90) node _T_93 = and(_T_21, _T_92) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_93, UInt<1>(0h1), "") : assert_2 node _T_97 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_98 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(UInt<1>(0h0), _T_99) node _T_101 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<14>(0h2000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<13>(0h1000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<18>(0h2f000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<17>(0h10000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<17>(0h10000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_105, _T_110) node _T_157 = or(_T_156, _T_115) node _T_158 = or(_T_157, _T_120) node _T_159 = or(_T_158, _T_125) node _T_160 = or(_T_159, _T_130) node _T_161 = or(_T_160, _T_135) node _T_162 = or(_T_161, _T_140) node _T_163 = or(_T_162, _T_145) node _T_164 = or(_T_163, _T_150) node _T_165 = or(_T_164, _T_155) node _T_166 = and(_T_100, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(UInt<1>(0h0), _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_168, UInt<1>(0h1), "") : assert_3 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_175 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_175, UInt<1>(0h1), "") : assert_5 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(is_aligned, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_182 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_183 = asUInt(reset) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : node _T_185 = eq(_T_182, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_182, UInt<1>(0h1), "") : assert_7 node _T_186 = not(io.in.a.bits.mask) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_187, UInt<1>(0h1), "") : assert_8 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_191, UInt<1>(0h1), "") : assert_9 node _T_195 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<14>(0h2000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<18>(0h2f000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<17>(0h10000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_234 = cvt(_T_233) node _T_235 = and(_T_234, asSInt(UInt<27>(0h4000000))) node _T_236 = asSInt(_T_235) node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0))) node _T_238 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_239 = cvt(_T_238) node _T_240 = and(_T_239, asSInt(UInt<13>(0h1000))) node _T_241 = asSInt(_T_240) node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = or(_T_207, _T_212) node _T_249 = or(_T_248, _T_217) node _T_250 = or(_T_249, _T_222) node _T_251 = or(_T_250, _T_227) node _T_252 = or(_T_251, _T_232) node _T_253 = or(_T_252, _T_237) node _T_254 = or(_T_253, _T_242) node _T_255 = or(_T_254, _T_247) node _T_256 = and(_T_202, _T_255) node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<29>(0h10000000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = or(_T_263, _T_268) node _T_270 = and(_T_258, _T_269) node _T_271 = or(UInt<1>(0h0), _T_256) node _T_272 = or(_T_271, _T_270) node _T_273 = and(_T_201, _T_272) node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_T_273, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_273, UInt<1>(0h1), "") : assert_10 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<18>(0h2f000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<29>(0h10000000))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = or(_T_285, _T_290) node _T_337 = or(_T_336, _T_295) node _T_338 = or(_T_337, _T_300) node _T_339 = or(_T_338, _T_305) node _T_340 = or(_T_339, _T_310) node _T_341 = or(_T_340, _T_315) node _T_342 = or(_T_341, _T_320) node _T_343 = or(_T_342, _T_325) node _T_344 = or(_T_343, _T_330) node _T_345 = or(_T_344, _T_335) node _T_346 = and(_T_280, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_348, UInt<1>(0h1), "") : assert_11 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_355 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_355, UInt<1>(0h1), "") : assert_13 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_362, UInt<1>(0h1), "") : assert_15 node _T_366 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_366, UInt<1>(0h1), "") : assert_16 node _T_370 = not(io.in.a.bits.mask) node _T_371 = eq(_T_370, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_371, UInt<1>(0h1), "") : assert_17 node _T_375 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_375, UInt<1>(0h1), "") : assert_18 node _T_379 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_379 : node _T_380 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_381 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = or(UInt<1>(0h0), _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_385, UInt<1>(0h1), "") : assert_19 node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_391 = and(_T_389, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_394 = cvt(_T_393) node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000))) node _T_396 = asSInt(_T_395) node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0))) node _T_398 = and(_T_392, _T_397) node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_400 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_401 = and(_T_399, _T_400) node _T_402 = or(UInt<1>(0h0), _T_401) node _T_403 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_404 = cvt(_T_403) node _T_405 = and(_T_404, asSInt(UInt<14>(0h2000))) node _T_406 = asSInt(_T_405) node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0))) node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_409 = cvt(_T_408) node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000))) node _T_411 = asSInt(_T_410) node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0))) node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_414 = cvt(_T_413) node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000))) node _T_416 = asSInt(_T_415) node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0))) node _T_418 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_419 = cvt(_T_418) node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000))) node _T_421 = asSInt(_T_420) node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0))) node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_424 = cvt(_T_423) node _T_425 = and(_T_424, asSInt(UInt<13>(0h1000))) node _T_426 = asSInt(_T_425) node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0))) node _T_428 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_429 = cvt(_T_428) node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000))) node _T_431 = asSInt(_T_430) node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0))) node _T_433 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_434 = cvt(_T_433) node _T_435 = and(_T_434, asSInt(UInt<27>(0h4000000))) node _T_436 = asSInt(_T_435) node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0))) node _T_438 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_439 = cvt(_T_438) node _T_440 = and(_T_439, asSInt(UInt<13>(0h1000))) node _T_441 = asSInt(_T_440) node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0))) node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_444 = cvt(_T_443) node _T_445 = and(_T_444, asSInt(UInt<13>(0h1000))) node _T_446 = asSInt(_T_445) node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0))) node _T_448 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<29>(0h10000000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = or(_T_407, _T_412) node _T_454 = or(_T_453, _T_417) node _T_455 = or(_T_454, _T_422) node _T_456 = or(_T_455, _T_427) node _T_457 = or(_T_456, _T_432) node _T_458 = or(_T_457, _T_437) node _T_459 = or(_T_458, _T_442) node _T_460 = or(_T_459, _T_447) node _T_461 = or(_T_460, _T_452) node _T_462 = and(_T_402, _T_461) node _T_463 = or(UInt<1>(0h0), _T_398) node _T_464 = or(_T_463, _T_462) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_464, UInt<1>(0h1), "") : assert_20 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(is_aligned, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_474 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_474, UInt<1>(0h1), "") : assert_23 node _T_478 = eq(io.in.a.bits.mask, mask) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_478, UInt<1>(0h1), "") : assert_24 node _T_482 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_482, UInt<1>(0h1), "") : assert_25 node _T_486 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_486 : node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_488 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_489 = and(_T_487, _T_488) node _T_490 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(UInt<1>(0h0), _T_495) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = and(_T_496, _T_501) node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_505 = and(_T_503, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<14>(0h2000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<18>(0h2f000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<17>(0h10000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<13>(0h1000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<27>(0h4000000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<13>(0h1000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<13>(0h1000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<29>(0h10000000))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = or(_T_511, _T_516) node _T_553 = or(_T_552, _T_521) node _T_554 = or(_T_553, _T_526) node _T_555 = or(_T_554, _T_531) node _T_556 = or(_T_555, _T_536) node _T_557 = or(_T_556, _T_541) node _T_558 = or(_T_557, _T_546) node _T_559 = or(_T_558, _T_551) node _T_560 = and(_T_506, _T_559) node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_562 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<17>(0h10000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = and(_T_561, _T_566) node _T_568 = or(UInt<1>(0h0), _T_502) node _T_569 = or(_T_568, _T_560) node _T_570 = or(_T_569, _T_567) node _T_571 = and(_T_492, _T_570) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_571, UInt<1>(0h1), "") : assert_26 node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(is_aligned, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_581 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_581, UInt<1>(0h1), "") : assert_29 node _T_585 = eq(io.in.a.bits.mask, mask) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_585, UInt<1>(0h1), "") : assert_30 node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_589 : node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) node _T_595 = or(UInt<1>(0h0), _T_594) node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_598 = and(_T_596, _T_597) node _T_599 = or(UInt<1>(0h0), _T_598) node _T_600 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_601 = cvt(_T_600) node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000))) node _T_603 = asSInt(_T_602) node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0))) node _T_605 = and(_T_599, _T_604) node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<14>(0h2000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<18>(0h2f000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<13>(0h1000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<17>(0h10000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<27>(0h4000000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<13>(0h1000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<29>(0h10000000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = or(_T_614, _T_619) node _T_656 = or(_T_655, _T_624) node _T_657 = or(_T_656, _T_629) node _T_658 = or(_T_657, _T_634) node _T_659 = or(_T_658, _T_639) node _T_660 = or(_T_659, _T_644) node _T_661 = or(_T_660, _T_649) node _T_662 = or(_T_661, _T_654) node _T_663 = and(_T_609, _T_662) node _T_664 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_665 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_605) node _T_672 = or(_T_671, _T_663) node _T_673 = or(_T_672, _T_670) node _T_674 = and(_T_595, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_674, UInt<1>(0h1), "") : assert_31 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_684, UInt<1>(0h1), "") : assert_34 node _T_688 = not(mask) node _T_689 = and(io.in.a.bits.mask, _T_688) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_690, UInt<1>(0h1), "") : assert_35 node _T_694 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_699 = and(_T_697, _T_698) node _T_700 = or(UInt<1>(0h0), _T_699) node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<14>(0h2000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<18>(0h2f000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<17>(0h10000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<13>(0h1000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<27>(0h4000000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<13>(0h1000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<13>(0h1000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = or(_T_709, _T_714) node _T_746 = or(_T_745, _T_719) node _T_747 = or(_T_746, _T_724) node _T_748 = or(_T_747, _T_729) node _T_749 = or(_T_748, _T_734) node _T_750 = or(_T_749, _T_739) node _T_751 = or(_T_750, _T_744) node _T_752 = and(_T_704, _T_751) node _T_753 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_754 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<17>(0h10000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = and(_T_753, _T_758) node _T_760 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_761 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_762 = and(_T_760, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<17>(0h10000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<29>(0h10000000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = or(_T_768, _T_773) node _T_775 = and(_T_763, _T_774) node _T_776 = or(UInt<1>(0h0), _T_752) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_775) node _T_779 = and(_T_700, _T_778) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_779, UInt<1>(0h1), "") : assert_36 node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(is_aligned, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_789 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_789, UInt<1>(0h1), "") : assert_39 node _T_793 = eq(io.in.a.bits.mask, mask) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_793, UInt<1>(0h1), "") : assert_40 node _T_797 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_797 : node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_800 = and(_T_798, _T_799) node _T_801 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_805 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_806 = and(_T_804, _T_805) node _T_807 = or(UInt<1>(0h0), _T_806) node _T_808 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<14>(0h2000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<13>(0h1000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<18>(0h2f000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<13>(0h1000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_834 = cvt(_T_833) node _T_835 = and(_T_834, asSInt(UInt<27>(0h4000000))) node _T_836 = asSInt(_T_835) node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) node _T_838 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<13>(0h1000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = or(_T_812, _T_817) node _T_849 = or(_T_848, _T_822) node _T_850 = or(_T_849, _T_827) node _T_851 = or(_T_850, _T_832) node _T_852 = or(_T_851, _T_837) node _T_853 = or(_T_852, _T_842) node _T_854 = or(_T_853, _T_847) node _T_855 = and(_T_807, _T_854) node _T_856 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_857 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<17>(0h10000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_864 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_865 = and(_T_863, _T_864) node _T_866 = or(UInt<1>(0h0), _T_865) node _T_867 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_873 = cvt(_T_872) node _T_874 = and(_T_873, asSInt(UInt<29>(0h10000000))) node _T_875 = asSInt(_T_874) node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0))) node _T_877 = or(_T_871, _T_876) node _T_878 = and(_T_866, _T_877) node _T_879 = or(UInt<1>(0h0), _T_855) node _T_880 = or(_T_879, _T_862) node _T_881 = or(_T_880, _T_878) node _T_882 = and(_T_803, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = and(_T_903, _T_904) node _T_906 = or(UInt<1>(0h0), _T_905) node _T_907 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_908 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_909 = and(_T_907, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = and(_T_910, _T_915) node _T_917 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<14>(0h2000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<17>(0h10000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<18>(0h2f000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<17>(0h10000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_939 = cvt(_T_938) node _T_940 = and(_T_939, asSInt(UInt<13>(0h1000))) node _T_941 = asSInt(_T_940) node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0))) node _T_943 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_944 = cvt(_T_943) node _T_945 = and(_T_944, asSInt(UInt<27>(0h4000000))) node _T_946 = asSInt(_T_945) node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0))) node _T_948 = xor(io.in.a.bits.address, UInt<29>(0h10016000)) node _T_949 = cvt(_T_948) node _T_950 = and(_T_949, asSInt(UInt<13>(0h1000))) node _T_951 = asSInt(_T_950) node _T_952 = eq(_T_951, asSInt(UInt<1>(0h0))) node _T_953 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_954 = cvt(_T_953) node _T_955 = and(_T_954, asSInt(UInt<13>(0h1000))) node _T_956 = asSInt(_T_955) node _T_957 = eq(_T_956, asSInt(UInt<1>(0h0))) node _T_958 = or(_T_922, _T_927) node _T_959 = or(_T_958, _T_932) node _T_960 = or(_T_959, _T_937) node _T_961 = or(_T_960, _T_942) node _T_962 = or(_T_961, _T_947) node _T_963 = or(_T_962, _T_952) node _T_964 = or(_T_963, _T_957) node _T_965 = and(_T_917, _T_964) node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_967 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_968 = and(_T_966, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_971 = cvt(_T_970) node _T_972 = and(_T_971, asSInt(UInt<17>(0h10000))) node _T_973 = asSInt(_T_972) node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0))) node _T_975 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_976 = cvt(_T_975) node _T_977 = and(_T_976, asSInt(UInt<29>(0h10000000))) node _T_978 = asSInt(_T_977) node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0))) node _T_980 = or(_T_974, _T_979) node _T_981 = and(_T_969, _T_980) node _T_982 = or(UInt<1>(0h0), _T_916) node _T_983 = or(_T_982, _T_965) node _T_984 = or(_T_983, _T_981) node _T_985 = and(_T_906, _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_985, UInt<1>(0h1), "") : assert_46 node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(is_aligned, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_995 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_995, UInt<1>(0h1), "") : assert_49 node _T_999 = eq(io.in.a.bits.mask, mask) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_999, UInt<1>(0h1), "") : assert_50 node _T_1003 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1007 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1011 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1011 : node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1015 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_54 node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_55 node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_56 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_57 node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1031 : node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(sink_ok, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1038 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_60 node _T_1042 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(_T_1042, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1042, UInt<1>(0h1), "") : assert_61 node _T_1046 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_62 node _T_1050 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_63 node _T_1054 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1055 = or(UInt<1>(0h1), _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_64 node _T_1059 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1059 : node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(sink_ok, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1066 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_67 node _T_1070 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_68 node _T_1074 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_69 node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1079 = or(_T_1078, io.in.d.bits.corrupt) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_70 node _T_1083 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1084 = or(UInt<1>(0h1), _T_1083) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_71 node _T_1088 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1088 : node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1092 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_73 node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_74 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(UInt<1>(0h1), _T_1100) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_75 node _T_1105 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1105 : node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1109 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_77 node _T_1113 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1114 = or(_T_1113, io.in.d.bits.corrupt) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_78 node _T_1118 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1119 = or(UInt<1>(0h1), _T_1118) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_79 node _T_1123 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1123 : node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1127 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_81 node _T_1131 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_82 node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1136 = or(UInt<1>(0h1), _T_1135) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1140 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1144 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1148 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1152 = eq(a_first, UInt<1>(0h0)) node _T_1153 = and(io.in.a.valid, _T_1152) when _T_1153 : node _T_1154 = eq(io.in.a.bits.opcode, opcode) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_87 node _T_1158 = eq(io.in.a.bits.param, param) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_88 node _T_1162 = eq(io.in.a.bits.size, size) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_89 node _T_1166 = eq(io.in.a.bits.source, source) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_90 node _T_1170 = eq(io.in.a.bits.address, address) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_91 node _T_1174 = and(io.in.a.ready, io.in.a.valid) node _T_1175 = and(_T_1174, a_first) when _T_1175 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1176 = eq(d_first, UInt<1>(0h0)) node _T_1177 = and(io.in.d.valid, _T_1176) when _T_1177 : node _T_1178 = eq(io.in.d.bits.opcode, opcode_1) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_92 node _T_1182 = eq(io.in.d.bits.param, param_1) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_93 node _T_1186 = eq(io.in.d.bits.size, size_1) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_94 node _T_1190 = eq(io.in.d.bits.source, source_1) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_95 node _T_1194 = eq(io.in.d.bits.sink, sink) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_96 node _T_1198 = eq(io.in.d.bits.denied, denied) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_97 node _T_1202 = and(io.in.d.ready, io.in.d.valid) node _T_1203 = and(_T_1202, d_first) when _T_1203 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1204 = and(io.in.a.valid, a_first_1) node _T_1205 = and(_T_1204, UInt<1>(0h1)) when _T_1205 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1206 = and(io.in.a.ready, io.in.a.valid) node _T_1207 = and(_T_1206, a_first_1) node _T_1208 = and(_T_1207, UInt<1>(0h1)) when _T_1208 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1209 = dshr(inflight, io.in.a.bits.source) node _T_1210 = bits(_T_1209, 0, 0) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1215 = and(io.in.d.valid, d_first_1) node _T_1216 = and(_T_1215, UInt<1>(0h1)) node _T_1217 = eq(d_release_ack, UInt<1>(0h0)) node _T_1218 = and(_T_1216, _T_1217) when _T_1218 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1219 = and(io.in.d.ready, io.in.d.valid) node _T_1220 = and(_T_1219, d_first_1) node _T_1221 = and(_T_1220, UInt<1>(0h1)) node _T_1222 = eq(d_release_ack, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1224 = and(io.in.d.valid, d_first_1) node _T_1225 = and(_T_1224, UInt<1>(0h1)) node _T_1226 = eq(d_release_ack, UInt<1>(0h0)) node _T_1227 = and(_T_1225, _T_1226) when _T_1227 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1228 = dshr(inflight, io.in.d.bits.source) node _T_1229 = bits(_T_1228, 0, 0) node _T_1230 = or(_T_1229, same_cycle_resp) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1234 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1236 = or(_T_1234, _T_1235) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_100 node _T_1240 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_101 else : node _T_1244 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1245 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1246 = or(_T_1244, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_102 node _T_1250 = eq(io.in.d.bits.size, a_size_lookup) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_103 node _T_1254 = and(io.in.d.valid, d_first_1) node _T_1255 = and(_T_1254, a_first_1) node _T_1256 = and(_T_1255, io.in.a.valid) node _T_1257 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1258 = and(_T_1256, _T_1257) node _T_1259 = eq(d_release_ack, UInt<1>(0h0)) node _T_1260 = and(_T_1258, _T_1259) when _T_1260 : node _T_1261 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1262 = or(_T_1261, io.in.a.ready) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_104 node _T_1266 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1267 = orr(a_set_wo_ready) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) node _T_1269 = or(_T_1266, _T_1268) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_88 node _T_1273 = orr(inflight) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) node _T_1275 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1276 = or(_T_1274, _T_1275) node _T_1277 = lt(watchdog, plusarg_reader.out) node _T_1278 = or(_T_1276, _T_1277) node _T_1279 = asUInt(reset) node _T_1280 = eq(_T_1279, UInt<1>(0h0)) when _T_1280 : node _T_1281 = eq(_T_1278, UInt<1>(0h0)) when _T_1281 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1278, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1282 = and(io.in.a.ready, io.in.a.valid) node _T_1283 = and(io.in.d.ready, io.in.d.valid) node _T_1284 = or(_T_1282, _T_1283) when _T_1284 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1285 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1286 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1287 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1288 = and(_T_1286, _T_1287) node _T_1289 = and(_T_1285, _T_1288) when _T_1289 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1290 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1291 = and(_T_1290, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1292 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1293 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1294 = and(_T_1292, _T_1293) node _T_1295 = and(_T_1291, _T_1294) when _T_1295 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1296 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1297 = bits(_T_1296, 0, 0) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1302 = and(io.in.d.valid, d_first_2) node _T_1303 = and(_T_1302, UInt<1>(0h1)) node _T_1304 = and(_T_1303, d_release_ack_1) when _T_1304 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1305 = and(io.in.d.ready, io.in.d.valid) node _T_1306 = and(_T_1305, d_first_2) node _T_1307 = and(_T_1306, UInt<1>(0h1)) node _T_1308 = and(_T_1307, d_release_ack_1) when _T_1308 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1309 = and(io.in.d.valid, d_first_2) node _T_1310 = and(_T_1309, UInt<1>(0h1)) node _T_1311 = and(_T_1310, d_release_ack_1) when _T_1311 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1312 = dshr(inflight_1, io.in.d.bits.source) node _T_1313 = bits(_T_1312, 0, 0) node _T_1314 = or(_T_1313, same_cycle_resp_1) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1318 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_109 else : node _T_1322 = eq(io.in.d.bits.size, c_size_lookup) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_110 node _T_1326 = and(io.in.d.valid, d_first_2) node _T_1327 = and(_T_1326, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1328 = and(_T_1327, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1329 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = and(_T_1330, d_release_ack_1) node _T_1332 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1333 = and(_T_1331, _T_1332) when _T_1333 : node _T_1334 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1335 = or(_T_1334, _WIRE_23.ready) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_111 node _T_1339 = orr(c_set_wo_ready) when _T_1339 : node _T_1340 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_89 node _T_1344 = orr(inflight_1) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) node _T_1346 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1347 = or(_T_1345, _T_1346) node _T_1348 = lt(watchdog_1, plusarg_reader_1.out) node _T_1349 = or(_T_1347, _T_1348) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1353 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1354 = and(io.in.d.ready, io.in.d.valid) node _T_1355 = or(_T_1353, _T_1354) when _T_1355 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [7:0] a_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] a_first_beats1_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count_1 = 8'h0; // @[Edges.scala:234:25] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [15:0] io_in_a_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_a_bits_data = 128'h0; // @[Monitor.scala:36:7] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [7:0] a_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [7:0] a_first_beats1_decode_1 = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _T_1282 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1282; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1282; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T = a_first ? 8'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T_1 = a_first_1 ? 8'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1205 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1205; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1205; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1282 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1254 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1254 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1326 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1326 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_114 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_115 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_116 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_117 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_100 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_160 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_100( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_160 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d32s1k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d32s1k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d32s1k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_86 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBuffer_a32d32s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [31:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeIn_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d32s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d32s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_5 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<2>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}} [3] wire _valids_WIRE : UInt<1>[3] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) regreset valids : UInt<1>[3], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], clock regreset enq_ptr_value : UInt<2>, clock, reset, UInt<2>(0h0) regreset deq_ptr_value : UInt<2>, clock, reset, UInt<2>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, UInt<1>(0h1)) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, UInt<1>(0h1)) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, UInt<1>(0h1)) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT.fflags, io.enq.bits.fflags connect MPORT.predicated, io.enq.bits.predicated connect MPORT.data, io.enq.bits.data connect MPORT.uop, io.enq.bits.uop connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<2>(0h2)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when wrap : connect enq_ptr_value, UInt<1>(0h0) when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<2>(0h2)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 when wrap_1 : connect deq_ptr_value, UInt<1>(0h0) node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}} infer mport out_MPORT = ram[deq_ptr_value], clock connect out.fflags, out_MPORT.fflags connect out.predicated, out_MPORT.predicated connect out.data, out_MPORT.data connect out.uop, out_MPORT.uop connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, UInt<1>(0h1)) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 when io.empty : connect io.deq.valid, io.enq.valid connect io.deq.bits, io.enq.bits node _io_deq_bits_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_3 = and(io.enq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_2) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_3 connect do_deq, UInt<1>(0h0) when io.deq.ready : connect do_enq, UInt<1>(0h0) node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = mux(maybe_full, UInt<2>(0h3), UInt<1>(0h0)) node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value) node _io_count_T_2 = add(UInt<2>(0h3), ptr_diff) node _io_count_T_3 = tail(_io_count_T_2, 1) node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff) node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4) connect io.count, _io_count_T_5

module BranchKillableQueue_5( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [7:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [64:0] io_enq_bits_data, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [7:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [64:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_predicated, // @[util.scala:453:14] output io_deq_bits_fflags_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_fflags_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_fflags_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_fflags_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_fflags_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_fflags_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_fflags_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_sfb, // @[util.scala:453:14] output [7:0] io_deq_bits_fflags_bits_uop_br_mask, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_br_tag, // @[util.scala:453:14] output [3:0] io_deq_bits_fflags_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_fflags_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_fflags_bits_uop_csr_addr, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_uop_rob_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_ldq_idx, // @[util.scala:453:14] output [2:0] io_deq_bits_fflags_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_rxq_idx, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_pdst, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_prs1, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_prs2, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_prs3, // @[util.scala:453:14] output [3:0] io_deq_bits_fflags_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ppred_busy, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_fflags_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_fflags_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_fflags_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_fflags_bits_uop_debug_tsrc, // @[util.scala:453:14] output [4:0] io_deq_bits_fflags_bits_flags, // @[util.scala:453:14] input [7:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_is_br, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14] input io_brupdate_b2_uop_taken, // @[util.scala:453:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14] input io_brupdate_b2_uop_exception, // @[util.scala:453:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14] input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14] input io_brupdate_b2_valid, // @[util.scala:453:14] input io_brupdate_b2_mispredict, // @[util.scala:453:14] input io_brupdate_b2_taken, // @[util.scala:453:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14] input io_flush, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [460:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [7:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [64:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7] wire io_flush_0 = io_flush; // @[util.scala:448:7] wire [63:0] io_enq_bits_fflags_bits_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14] wire [11:0] io_enq_bits_fflags_bits_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14] wire [19:0] io_enq_bits_fflags_bits_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_pdst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_prs1 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_prs2 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_prs3 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_enq_bits_fflags_bits_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14] wire [7:0] io_enq_bits_fflags_bits_uop_br_mask = 8'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_uop_rob_idx = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_enq_bits_fflags_bits_flags = 5'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_enq_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_iw_state = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_mem_size = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[util.scala:448:7] wire [1:0] io_enq_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[util.scala:448:7] wire [3:0] io_enq_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7, :453:14] wire [3:0] io_enq_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[util.scala:448:7, :453:14] wire [3:0] io_enq_bits_fflags_bits_uop_ppred = 4'h0; // @[util.scala:448:7, :453:14] wire [9:0] io_enq_bits_fflags_bits_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_br_tag = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_enq_bits_fflags_bits_uop_stq_idx = 3'h0; // @[util.scala:448:7, :453:14] wire [39:0] io_enq_bits_fflags_bits_uop_debug_pc = 40'h0; // @[util.scala:448:7, :453:14] wire [31:0] io_enq_bits_fflags_bits_uop_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [31:0] io_enq_bits_fflags_bits_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_enq_bits_fflags_bits_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14] wire io_enq_bits_predicated = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_valid = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_rvc = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_br = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_jalr = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_jal = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_sfb = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_edge_inst = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_taken = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_exception = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_bypassable = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_mem_signed = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_fence = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_fencei = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_amo = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_uses_stq = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_is_unique = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_ldst_val = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_frs3_en = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_fp_val = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_fp_single = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[util.scala:448:7] wire io_enq_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _io_enq_ready_T; // @[util.scala:504:19] wire _io_empty_T_1; // @[util.scala:473:25] wire _valids_0_T_4 = io_flush_0; // @[util.scala:448:7, :481:83] wire _valids_1_T_4 = io_flush_0; // @[util.scala:448:7, :481:83] wire _valids_2_T_4 = io_flush_0; // @[util.scala:448:7, :481:83] wire _io_deq_valid_T_6 = io_flush_0; // @[util.scala:448:7, :509:122] wire [1:0] _io_count_T_5; // @[util.scala:529:20] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_fflags_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_fflags_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_fflags_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_fflags_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_fflags_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_fflags_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_fflags_bits_uop_br_mask_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_br_tag_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_fflags_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_fflags_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_fflags_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_fflags_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_pdst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_prs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_prs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_prs3_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_fflags_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_fflags_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_fflags_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_fflags_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_fflags_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_fflags_bits_flags_0; // @[util.scala:448:7] wire io_deq_bits_fflags_valid_0; // @[util.scala:448:7] wire [64:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_predicated_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [1:0] io_count; // @[util.scala:448:7] wire [64:0] out_data = _ram_ext_R0_data[64:0]; // @[util.scala:464:20, :506:17] wire out_predicated = _ram_ext_R0_data[65]; // @[util.scala:464:20, :506:17] wire out_fflags_valid = _ram_ext_R0_data[66]; // @[util.scala:464:20, :506:17] wire [6:0] out_fflags_bits_uop_uopc = _ram_ext_R0_data[73:67]; // @[util.scala:464:20, :506:17] wire [31:0] out_fflags_bits_uop_inst = _ram_ext_R0_data[105:74]; // @[util.scala:464:20, :506:17] wire [31:0] out_fflags_bits_uop_debug_inst = _ram_ext_R0_data[137:106]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_rvc = _ram_ext_R0_data[138]; // @[util.scala:464:20, :506:17] wire [39:0] out_fflags_bits_uop_debug_pc = _ram_ext_R0_data[178:139]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_iq_type = _ram_ext_R0_data[181:179]; // @[util.scala:464:20, :506:17] wire [9:0] out_fflags_bits_uop_fu_code = _ram_ext_R0_data[191:182]; // @[util.scala:464:20, :506:17] wire [3:0] out_fflags_bits_uop_ctrl_br_type = _ram_ext_R0_data[195:192]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_ctrl_op1_sel = _ram_ext_R0_data[197:196]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ctrl_op2_sel = _ram_ext_R0_data[200:198]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ctrl_imm_sel = _ram_ext_R0_data[203:201]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_uop_ctrl_op_fcn = _ram_ext_R0_data[208:204]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_fcn_dw = _ram_ext_R0_data[209]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ctrl_csr_cmd = _ram_ext_R0_data[212:210]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_is_load = _ram_ext_R0_data[213]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_is_sta = _ram_ext_R0_data[214]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ctrl_is_std = _ram_ext_R0_data[215]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_iw_state = _ram_ext_R0_data[217:216]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_iw_p1_poisoned = _ram_ext_R0_data[218]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_iw_p2_poisoned = _ram_ext_R0_data[219]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_br = _ram_ext_R0_data[220]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_jalr = _ram_ext_R0_data[221]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_jal = _ram_ext_R0_data[222]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_sfb = _ram_ext_R0_data[223]; // @[util.scala:464:20, :506:17] wire [7:0] out_fflags_bits_uop_br_mask = _ram_ext_R0_data[231:224]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_br_tag = _ram_ext_R0_data[234:232]; // @[util.scala:464:20, :506:17] wire [3:0] out_fflags_bits_uop_ftq_idx = _ram_ext_R0_data[238:235]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_edge_inst = _ram_ext_R0_data[239]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_pc_lob = _ram_ext_R0_data[245:240]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_taken = _ram_ext_R0_data[246]; // @[util.scala:464:20, :506:17] wire [19:0] out_fflags_bits_uop_imm_packed = _ram_ext_R0_data[266:247]; // @[util.scala:464:20, :506:17] wire [11:0] out_fflags_bits_uop_csr_addr = _ram_ext_R0_data[278:267]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_uop_rob_idx = _ram_ext_R0_data[283:279]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_ldq_idx = _ram_ext_R0_data[286:284]; // @[util.scala:464:20, :506:17] wire [2:0] out_fflags_bits_uop_stq_idx = _ram_ext_R0_data[289:287]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_rxq_idx = _ram_ext_R0_data[291:290]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_pdst = _ram_ext_R0_data[297:292]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_prs1 = _ram_ext_R0_data[303:298]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_prs2 = _ram_ext_R0_data[309:304]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_prs3 = _ram_ext_R0_data[315:310]; // @[util.scala:464:20, :506:17] wire [3:0] out_fflags_bits_uop_ppred = _ram_ext_R0_data[319:316]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_prs1_busy = _ram_ext_R0_data[320]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_prs2_busy = _ram_ext_R0_data[321]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_prs3_busy = _ram_ext_R0_data[322]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ppred_busy = _ram_ext_R0_data[323]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_stale_pdst = _ram_ext_R0_data[329:324]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_exception = _ram_ext_R0_data[330]; // @[util.scala:464:20, :506:17] wire [63:0] out_fflags_bits_uop_exc_cause = _ram_ext_R0_data[394:331]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_bypassable = _ram_ext_R0_data[395]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_uop_mem_cmd = _ram_ext_R0_data[400:396]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_mem_size = _ram_ext_R0_data[402:401]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_mem_signed = _ram_ext_R0_data[403]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_fence = _ram_ext_R0_data[404]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_fencei = _ram_ext_R0_data[405]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_amo = _ram_ext_R0_data[406]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_uses_ldq = _ram_ext_R0_data[407]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_uses_stq = _ram_ext_R0_data[408]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_sys_pc2epc = _ram_ext_R0_data[409]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_is_unique = _ram_ext_R0_data[410]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_flush_on_commit = _ram_ext_R0_data[411]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ldst_is_rs1 = _ram_ext_R0_data[412]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_ldst = _ram_ext_R0_data[418:413]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_lrs1 = _ram_ext_R0_data[424:419]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_lrs2 = _ram_ext_R0_data[430:425]; // @[util.scala:464:20, :506:17] wire [5:0] out_fflags_bits_uop_lrs3 = _ram_ext_R0_data[436:431]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_ldst_val = _ram_ext_R0_data[437]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_dst_rtype = _ram_ext_R0_data[439:438]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_lrs1_rtype = _ram_ext_R0_data[441:440]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_lrs2_rtype = _ram_ext_R0_data[443:442]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_frs3_en = _ram_ext_R0_data[444]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_fp_val = _ram_ext_R0_data[445]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_fp_single = _ram_ext_R0_data[446]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_xcpt_pf_if = _ram_ext_R0_data[447]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_xcpt_ae_if = _ram_ext_R0_data[448]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_xcpt_ma_if = _ram_ext_R0_data[449]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_bp_debug_if = _ram_ext_R0_data[450]; // @[util.scala:464:20, :506:17] wire out_fflags_bits_uop_bp_xcpt_if = _ram_ext_R0_data[451]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_debug_fsrc = _ram_ext_R0_data[453:452]; // @[util.scala:464:20, :506:17] wire [1:0] out_fflags_bits_uop_debug_tsrc = _ram_ext_R0_data[455:454]; // @[util.scala:464:20, :506:17] wire [4:0] out_fflags_bits_flags = _ram_ext_R0_data[460:456]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] reg valids_1; // @[util.scala:465:24] reg valids_2; // @[util.scala:465:24] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [39:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [7:0] uops_0_br_mask; // @[util.scala:466:20] reg [2:0] uops_0_br_tag; // @[util.scala:466:20] reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [4:0] uops_0_rob_idx; // @[util.scala:466:20] reg [2:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [2:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [5:0] uops_0_pdst; // @[util.scala:466:20] reg [5:0] uops_0_prs1; // @[util.scala:466:20] reg [5:0] uops_0_prs2; // @[util.scala:466:20] reg [5:0] uops_0_prs3; // @[util.scala:466:20] reg [3:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [5:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [39:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [7:0] uops_1_br_mask; // @[util.scala:466:20] reg [2:0] uops_1_br_tag; // @[util.scala:466:20] reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [4:0] uops_1_rob_idx; // @[util.scala:466:20] reg [2:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [2:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [5:0] uops_1_pdst; // @[util.scala:466:20] reg [5:0] uops_1_prs1; // @[util.scala:466:20] reg [5:0] uops_1_prs2; // @[util.scala:466:20] reg [5:0] uops_1_prs3; // @[util.scala:466:20] reg [3:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [5:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [39:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [7:0] uops_2_br_mask; // @[util.scala:466:20] reg [2:0] uops_2_br_tag; // @[util.scala:466:20] reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [4:0] uops_2_rob_idx; // @[util.scala:466:20] reg [2:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [2:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [5:0] uops_2_pdst; // @[util.scala:466:20] reg [5:0] uops_2_prs1; // @[util.scala:466:20] reg [5:0] uops_2_prs2; // @[util.scala:466:20] reg [5:0] uops_2_prs3; // @[util.scala:466:20] reg [3:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [5:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [1:0] enq_ptr_value; // @[Counter.scala:61:40] reg [1:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire full = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq; // @[util.scala:475:24] wire [3:0] _GEN = {{valids_0}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq; // @[util.scala:476:24] wire [7:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}] wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32] wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}] wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}] wire [7:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [7:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [7:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}] wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32] wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}] wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}] wire [7:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [7:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [7:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}] wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32] wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}] wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}] wire [7:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [7:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire wrap = enq_ptr_value == 2'h2; // @[Counter.scala:61:40, :73:24] wire [7:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7] wire [2:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [2:0] _value_T = _GEN_1 + 3'h1; // @[Counter.scala:77:24] wire [1:0] _value_T_1 = _value_T[1:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 2'h2; // @[Counter.scala:61:40, :73:24] wire [2:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [2:0] _value_T_2 = _GEN_2 + 3'h1; // @[Counter.scala:77:24] wire [1:0] _value_T_3 = _value_T_2[1:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [39:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [7:0] out_uop_br_mask; // @[util.scala:506:17] wire [2:0] out_uop_br_tag; // @[util.scala:506:17] wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [4:0] out_uop_rob_idx; // @[util.scala:506:17] wire [2:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [2:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [5:0] out_uop_pdst; // @[util.scala:506:17] wire [5:0] out_uop_prs1; // @[util.scala:506:17] wire [5:0] out_uop_prs2; // @[util.scala:506:17] wire [5:0] out_uop_prs3; // @[util.scala:506:17] wire [3:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [5:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [3:0][6:0] _GEN_3 = {{uops_0_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][31:0] _GEN_4 = {{uops_0_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][31:0] _GEN_5 = {{uops_0_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_6 = {{uops_0_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][39:0] _GEN_7 = {{uops_0_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_8 = {{uops_0_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][9:0] _GEN_9 = {{uops_0_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][3:0] _GEN_10 = {{uops_0_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_11 = {{uops_0_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_12 = {{uops_0_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_13 = {{uops_0_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][4:0] _GEN_14 = {{uops_0_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_15 = {{uops_0_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_16 = {{uops_0_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_17 = {{uops_0_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_18 = {{uops_0_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_19 = {{uops_0_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_20 = {{uops_0_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_21 = {{uops_0_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_22 = {{uops_0_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_23 = {{uops_0_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_24 = {{uops_0_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_25 = {{uops_0_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_26 = {{uops_0_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][7:0] _GEN_27 = {{uops_0_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_28 = {{uops_0_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][3:0] _GEN_29 = {{uops_0_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_30 = {{uops_0_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_31 = {{uops_0_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_32 = {{uops_0_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][19:0] _GEN_33 = {{uops_0_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][11:0] _GEN_34 = {{uops_0_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][4:0] _GEN_35 = {{uops_0_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_36 = {{uops_0_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][2:0] _GEN_37 = {{uops_0_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_38 = {{uops_0_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_39 = {{uops_0_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_40 = {{uops_0_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_41 = {{uops_0_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_42 = {{uops_0_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][3:0] _GEN_43 = {{uops_0_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_44 = {{uops_0_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_45 = {{uops_0_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_46 = {{uops_0_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_47 = {{uops_0_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_48 = {{uops_0_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_49 = {{uops_0_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][63:0] _GEN_50 = {{uops_0_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_51 = {{uops_0_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][4:0] _GEN_52 = {{uops_0_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_53 = {{uops_0_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_54 = {{uops_0_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_55 = {{uops_0_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_56 = {{uops_0_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_57 = {{uops_0_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_58 = {{uops_0_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_59 = {{uops_0_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_60 = {{uops_0_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_61 = {{uops_0_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_62 = {{uops_0_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_63 = {{uops_0_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_64 = {{uops_0_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_65 = {{uops_0_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_66 = {{uops_0_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][5:0] _GEN_67 = {{uops_0_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_68 = {{uops_0_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_69 = {{uops_0_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_70 = {{uops_0_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_71 = {{uops_0_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_72 = {{uops_0_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_73 = {{uops_0_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_74 = {{uops_0_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_75 = {{uops_0_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_76 = {{uops_0_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_77 = {{uops_0_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_78 = {{uops_0_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0] _GEN_79 = {{uops_0_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_80 = {{uops_0_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [3:0][1:0] _GEN_81 = {{uops_0_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:476:42, :509:{30,40}] wire [7:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17] wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}] wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68] wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}] wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}] wire _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}] wire [7:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [7:0] _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17] assign io_deq_valid_0 = io_empty_0 ? io_enq_valid_0 : _io_deq_valid_T_8; // @[util.scala:448:7, :509:{27,108}, :515:21, :516:20] assign io_deq_bits_uop_uopc_0 = io_empty_0 ? io_enq_bits_uop_uopc_0 : out_uop_uopc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_inst_0 = io_empty_0 ? io_enq_bits_uop_inst_0 : out_uop_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_inst_0 = io_empty_0 ? io_enq_bits_uop_debug_inst_0 : out_uop_debug_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_rvc_0 = io_empty_0 ? io_enq_bits_uop_is_rvc_0 : out_uop_is_rvc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_pc_0 = io_empty_0 ? io_enq_bits_uop_debug_pc_0 : out_uop_debug_pc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iq_type_0 = io_empty_0 ? io_enq_bits_uop_iq_type_0 : out_uop_iq_type; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_fu_code_0 = io_empty_0 ? io_enq_bits_uop_fu_code_0 : out_uop_fu_code; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_br_type_0 = io_empty_0 ? io_enq_bits_uop_ctrl_br_type_0 : out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_op1_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op1_sel_0 : out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_op2_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op2_sel_0 : out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_imm_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_imm_sel_0 : out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_op_fcn_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op_fcn_0 : out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_fcn_dw_0 = io_empty_0 ? io_enq_bits_uop_ctrl_fcn_dw_0 : out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_csr_cmd_0 = io_empty_0 ? io_enq_bits_uop_ctrl_csr_cmd_0 : out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_is_load_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_load_0 : out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_is_sta_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_sta_0 : out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ctrl_is_std_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_std_0 : out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iw_state_0 = io_empty_0 ? io_enq_bits_uop_iw_state_0 : out_uop_iw_state; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iw_p1_poisoned_0 = io_empty_0 ? io_enq_bits_uop_iw_p1_poisoned_0 : out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_iw_p2_poisoned_0 = io_empty_0 ? io_enq_bits_uop_iw_p2_poisoned_0 : out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_br_0 = io_empty_0 ? io_enq_bits_uop_is_br_0 : out_uop_is_br; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_jalr_0 = io_empty_0 ? io_enq_bits_uop_is_jalr_0 : out_uop_is_jalr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_jal_0 = io_empty_0 ? io_enq_bits_uop_is_jal_0 : out_uop_is_jal; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_sfb_0 = io_empty_0 ? io_enq_bits_uop_is_sfb_0 : out_uop_is_sfb; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_br_tag_0 = io_empty_0 ? io_enq_bits_uop_br_tag_0 : out_uop_br_tag; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ftq_idx_0 = io_empty_0 ? io_enq_bits_uop_ftq_idx_0 : out_uop_ftq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_edge_inst_0 = io_empty_0 ? io_enq_bits_uop_edge_inst_0 : out_uop_edge_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_pc_lob_0 = io_empty_0 ? io_enq_bits_uop_pc_lob_0 : out_uop_pc_lob; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_taken_0 = io_empty_0 ? io_enq_bits_uop_taken_0 : out_uop_taken; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_imm_packed_0 = io_empty_0 ? io_enq_bits_uop_imm_packed_0 : out_uop_imm_packed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_csr_addr_0 = io_empty_0 ? io_enq_bits_uop_csr_addr_0 : out_uop_csr_addr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_rob_idx_0 = io_empty_0 ? io_enq_bits_uop_rob_idx_0 : out_uop_rob_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldq_idx_0 = io_empty_0 ? io_enq_bits_uop_ldq_idx_0 : out_uop_ldq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_stq_idx_0 = io_empty_0 ? io_enq_bits_uop_stq_idx_0 : out_uop_stq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_rxq_idx_0 = io_empty_0 ? io_enq_bits_uop_rxq_idx_0 : out_uop_rxq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_pdst_0 = io_empty_0 ? io_enq_bits_uop_pdst_0 : out_uop_pdst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs1_0 = io_empty_0 ? io_enq_bits_uop_prs1_0 : out_uop_prs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs2_0 = io_empty_0 ? io_enq_bits_uop_prs2_0 : out_uop_prs2; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs3_0 = io_empty_0 ? io_enq_bits_uop_prs3_0 : out_uop_prs3; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ppred_0 = io_empty_0 ? io_enq_bits_uop_ppred_0 : out_uop_ppred; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs1_busy_0 = io_empty_0 ? io_enq_bits_uop_prs1_busy_0 : out_uop_prs1_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs2_busy_0 = io_empty_0 ? io_enq_bits_uop_prs2_busy_0 : out_uop_prs2_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_prs3_busy_0 = io_empty_0 ? io_enq_bits_uop_prs3_busy_0 : out_uop_prs3_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ppred_busy_0 = io_empty_0 ? io_enq_bits_uop_ppred_busy_0 : out_uop_ppred_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_stale_pdst_0 = io_empty_0 ? io_enq_bits_uop_stale_pdst_0 : out_uop_stale_pdst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_exception_0 = io_empty_0 ? io_enq_bits_uop_exception_0 : out_uop_exception; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_exc_cause_0 = io_empty_0 ? io_enq_bits_uop_exc_cause_0 : out_uop_exc_cause; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_bypassable_0 = io_empty_0 ? io_enq_bits_uop_bypassable_0 : out_uop_bypassable; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_mem_cmd_0 = io_empty_0 ? io_enq_bits_uop_mem_cmd_0 : out_uop_mem_cmd; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_mem_size_0 = io_empty_0 ? io_enq_bits_uop_mem_size_0 : out_uop_mem_size; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_mem_signed_0 = io_empty_0 ? io_enq_bits_uop_mem_signed_0 : out_uop_mem_signed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_fence_0 = io_empty_0 ? io_enq_bits_uop_is_fence_0 : out_uop_is_fence; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_fencei_0 = io_empty_0 ? io_enq_bits_uop_is_fencei_0 : out_uop_is_fencei; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_amo_0 = io_empty_0 ? io_enq_bits_uop_is_amo_0 : out_uop_is_amo; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_uses_ldq_0 = io_empty_0 ? io_enq_bits_uop_uses_ldq_0 : out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_uses_stq_0 = io_empty_0 ? io_enq_bits_uop_uses_stq_0 : out_uop_uses_stq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = io_empty_0 ? io_enq_bits_uop_is_sys_pc2epc_0 : out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_is_unique_0 = io_empty_0 ? io_enq_bits_uop_is_unique_0 : out_uop_is_unique; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_flush_on_commit_0 = io_empty_0 ? io_enq_bits_uop_flush_on_commit_0 : out_uop_flush_on_commit; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldst_is_rs1_0 = io_empty_0 ? io_enq_bits_uop_ldst_is_rs1_0 : out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldst_0 = io_empty_0 ? io_enq_bits_uop_ldst_0 : out_uop_ldst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs1_0 = io_empty_0 ? io_enq_bits_uop_lrs1_0 : out_uop_lrs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs2_0 = io_empty_0 ? io_enq_bits_uop_lrs2_0 : out_uop_lrs2; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs3_0 = io_empty_0 ? io_enq_bits_uop_lrs3_0 : out_uop_lrs3; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_ldst_val_0 = io_empty_0 ? io_enq_bits_uop_ldst_val_0 : out_uop_ldst_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_dst_rtype_0 = io_empty_0 ? io_enq_bits_uop_dst_rtype_0 : out_uop_dst_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs1_rtype_0 = io_empty_0 ? io_enq_bits_uop_lrs1_rtype_0 : out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_lrs2_rtype_0 = io_empty_0 ? io_enq_bits_uop_lrs2_rtype_0 : out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_frs3_en_0 = io_empty_0 ? io_enq_bits_uop_frs3_en_0 : out_uop_frs3_en; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_fp_val_0 = io_empty_0 ? io_enq_bits_uop_fp_val_0 : out_uop_fp_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_fp_single_0 = io_empty_0 ? io_enq_bits_uop_fp_single_0 : out_uop_fp_single; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_xcpt_pf_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_pf_if_0 : out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_xcpt_ae_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_ae_if_0 : out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_xcpt_ma_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_ma_if_0 : out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_bp_debug_if_0 = io_empty_0 ? io_enq_bits_uop_bp_debug_if_0 : out_uop_bp_debug_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_bp_xcpt_if_0 = io_empty_0 ? io_enq_bits_uop_bp_xcpt_if_0 : out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_fsrc_0 = io_empty_0 ? io_enq_bits_uop_debug_fsrc_0 : out_uop_debug_fsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_uop_debug_tsrc_0 = io_empty_0 ? io_enq_bits_uop_debug_tsrc_0 : out_uop_debug_tsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_data_0 = io_empty_0 ? io_enq_bits_data_0 : out_data; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_predicated_0 = ~io_empty_0 & out_predicated; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_valid_0 = ~io_empty_0 & out_fflags_valid; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_uopc_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_uopc; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_inst_0 = io_empty_0 ? 32'h0 : out_fflags_bits_uop_inst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_inst_0 = io_empty_0 ? 32'h0 : out_fflags_bits_uop_debug_inst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_rvc_0 = ~io_empty_0 & out_fflags_bits_uop_is_rvc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_pc_0 = io_empty_0 ? 40'h0 : out_fflags_bits_uop_debug_pc; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iq_type_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_iq_type; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_fu_code_0 = io_empty_0 ? 10'h0 : out_fflags_bits_uop_fu_code; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_br_type_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_ctrl_br_type; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_op2_sel; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_imm_sel; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_ctrl_op_fcn; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_is_load_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_load; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_is_sta_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ctrl_is_std_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_std; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iw_state_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_iw_state; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0 = ~io_empty_0 & out_fflags_bits_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0 = ~io_empty_0 & out_fflags_bits_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_br_0 = ~io_empty_0 & out_fflags_bits_uop_is_br; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_jalr_0 = ~io_empty_0 & out_fflags_bits_uop_is_jalr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_jal_0 = ~io_empty_0 & out_fflags_bits_uop_is_jal; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_sfb_0 = ~io_empty_0 & out_fflags_bits_uop_is_sfb; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_br_mask_0 = io_empty_0 ? 8'h0 : out_fflags_bits_uop_br_mask; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_br_tag_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_br_tag; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ftq_idx_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_ftq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_edge_inst_0 = ~io_empty_0 & out_fflags_bits_uop_edge_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_pc_lob_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_pc_lob; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_taken_0 = ~io_empty_0 & out_fflags_bits_uop_taken; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_imm_packed_0 = io_empty_0 ? 20'h0 : out_fflags_bits_uop_imm_packed; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_csr_addr_0 = io_empty_0 ? 12'h0 : out_fflags_bits_uop_csr_addr; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_rob_idx_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_rob_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldq_idx_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ldq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_stq_idx_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_stq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_rxq_idx_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_rxq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_pdst_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_pdst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs1_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_prs1; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs2_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_prs2; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs3_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_prs3; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ppred_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_ppred; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs1_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs1_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs2_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs2_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_prs3_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs3_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ppred_busy_0 = ~io_empty_0 & out_fflags_bits_uop_ppred_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_stale_pdst_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_stale_pdst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_exception_0 = ~io_empty_0 & out_fflags_bits_uop_exception; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_exc_cause_0 = io_empty_0 ? 64'h0 : out_fflags_bits_uop_exc_cause; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_bypassable_0 = ~io_empty_0 & out_fflags_bits_uop_bypassable; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_mem_cmd_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_mem_cmd; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_mem_size_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_mem_size; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_mem_signed_0 = ~io_empty_0 & out_fflags_bits_uop_mem_signed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_fence_0 = ~io_empty_0 & out_fflags_bits_uop_is_fence; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_fencei_0 = ~io_empty_0 & out_fflags_bits_uop_is_fencei; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_amo_0 = ~io_empty_0 & out_fflags_bits_uop_is_amo; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_uses_ldq_0 = ~io_empty_0 & out_fflags_bits_uop_uses_ldq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_uses_stq_0 = ~io_empty_0 & out_fflags_bits_uop_uses_stq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0 = ~io_empty_0 & out_fflags_bits_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_is_unique_0 = ~io_empty_0 & out_fflags_bits_uop_is_unique; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_flush_on_commit_0 = ~io_empty_0 & out_fflags_bits_uop_flush_on_commit; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldst_is_rs1_0 = ~io_empty_0 & out_fflags_bits_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldst_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_ldst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs1_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs1; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs2_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs2; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs3_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs3; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_ldst_val_0 = ~io_empty_0 & out_fflags_bits_uop_ldst_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_dst_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_dst_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs1_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_lrs1_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_lrs2_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_lrs2_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_frs3_en_0 = ~io_empty_0 & out_fflags_bits_uop_frs3_en; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_fp_val_0 = ~io_empty_0 & out_fflags_bits_uop_fp_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_fp_single_0 = ~io_empty_0 & out_fflags_bits_uop_fp_single; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_xcpt_pf_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_xcpt_ae_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_xcpt_ma_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_bp_debug_if_0 = ~io_empty_0 & out_fflags_bits_uop_bp_debug_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_bp_xcpt_if_0 = ~io_empty_0 & out_fflags_bits_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_fsrc_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_debug_fsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_uop_debug_tsrc_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_debug_tsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19] assign io_deq_bits_fflags_bits_flags_0 = io_empty_0 ? 5'h0 : out_fflags_bits_flags; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19] wire [7:0] _io_deq_bits_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [7:0] _io_deq_bits_uop_br_mask_T_3 = io_enq_bits_uop_br_mask_0 & _io_deq_bits_uop_br_mask_T_2; // @[util.scala:85:{25,27}, :448:7] assign io_deq_bits_uop_br_mask_0 = io_empty_0 ? _io_deq_bits_uop_br_mask_T_3 : _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7, :511:27, :515:21, :518:31] assign do_deq = ~io_empty_0 & _do_deq_T_3; // @[util.scala:448:7, :476:{24,66}, :510:27, :515:21, :517:19, :520:14] assign do_enq = ~(io_empty_0 & io_deq_ready_0) & _do_enq_T; // @[Decoupled.scala:51:35] wire [2:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [1:0] ptr_diff = _ptr_diff_T[1:0]; // @[util.scala:524:40] wire [1:0] _io_count_T = {2{maybe_full}}; // @[util.scala:470:27, :530:24] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [2:0] _io_count_T_2 = {1'h0, ptr_diff} + 3'h3; // @[util.scala:524:40, :533:40] wire [1:0] _io_count_T_3 = _io_count_T_2[1:0]; // @[util.scala:533:40] wire [1:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:524:40, :532:{24,39}, :533:40] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:472:33, :529:20, :530:24, :532:24] assign io_count = _io_count_T_5; // @[util.scala:448:7, :529:20] wire _GEN_82 = enq_ptr_value == 2'h0; // @[Counter.scala:61:40] wire _GEN_83 = do_enq & _GEN_82; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_84 = enq_ptr_value == 2'h1; // @[Counter.scala:61:40] wire _GEN_85 = do_enq & _GEN_84; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_86 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 2'h0; // @[Counter.scala:61:40] deq_ptr_value <= 2'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_83 | _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_85 | _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & wrap_1) & (_GEN_86 | _valids_2_T_6); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= wrap ? 2'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= wrap_1 ? 2'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_83) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_82) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_85) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_84) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_3x461 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({396'h0, io_enq_bits_data_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_predicated = io_deq_bits_predicated_0; // @[util.scala:448:7] assign io_deq_bits_fflags_valid = io_deq_bits_fflags_valid_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_uopc = io_deq_bits_fflags_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_inst = io_deq_bits_fflags_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_inst = io_deq_bits_fflags_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_rvc = io_deq_bits_fflags_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_pc = io_deq_bits_fflags_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iq_type = io_deq_bits_fflags_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_fu_code = io_deq_bits_fflags_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_br_type = io_deq_bits_fflags_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_op1_sel = io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_op2_sel = io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_imm_sel = io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_op_fcn = io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_fcn_dw = io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_csr_cmd = io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_is_load = io_deq_bits_fflags_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_is_sta = io_deq_bits_fflags_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ctrl_is_std = io_deq_bits_fflags_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iw_state = io_deq_bits_fflags_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iw_p1_poisoned = io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_iw_p2_poisoned = io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_br = io_deq_bits_fflags_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_jalr = io_deq_bits_fflags_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_jal = io_deq_bits_fflags_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_sfb = io_deq_bits_fflags_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_br_mask = io_deq_bits_fflags_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_br_tag = io_deq_bits_fflags_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ftq_idx = io_deq_bits_fflags_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_edge_inst = io_deq_bits_fflags_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_pc_lob = io_deq_bits_fflags_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_taken = io_deq_bits_fflags_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_imm_packed = io_deq_bits_fflags_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_csr_addr = io_deq_bits_fflags_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_rob_idx = io_deq_bits_fflags_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldq_idx = io_deq_bits_fflags_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_stq_idx = io_deq_bits_fflags_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_rxq_idx = io_deq_bits_fflags_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_pdst = io_deq_bits_fflags_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs1 = io_deq_bits_fflags_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs2 = io_deq_bits_fflags_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs3 = io_deq_bits_fflags_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ppred = io_deq_bits_fflags_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs1_busy = io_deq_bits_fflags_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs2_busy = io_deq_bits_fflags_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_prs3_busy = io_deq_bits_fflags_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ppred_busy = io_deq_bits_fflags_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_stale_pdst = io_deq_bits_fflags_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_exception = io_deq_bits_fflags_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_exc_cause = io_deq_bits_fflags_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_bypassable = io_deq_bits_fflags_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_mem_cmd = io_deq_bits_fflags_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_mem_size = io_deq_bits_fflags_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_mem_signed = io_deq_bits_fflags_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_fence = io_deq_bits_fflags_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_fencei = io_deq_bits_fflags_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_amo = io_deq_bits_fflags_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_uses_ldq = io_deq_bits_fflags_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_uses_stq = io_deq_bits_fflags_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_sys_pc2epc = io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_is_unique = io_deq_bits_fflags_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_flush_on_commit = io_deq_bits_fflags_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldst_is_rs1 = io_deq_bits_fflags_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldst = io_deq_bits_fflags_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs1 = io_deq_bits_fflags_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs2 = io_deq_bits_fflags_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs3 = io_deq_bits_fflags_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_ldst_val = io_deq_bits_fflags_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_dst_rtype = io_deq_bits_fflags_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs1_rtype = io_deq_bits_fflags_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_lrs2_rtype = io_deq_bits_fflags_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_frs3_en = io_deq_bits_fflags_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_fp_val = io_deq_bits_fflags_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_fp_single = io_deq_bits_fflags_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_xcpt_pf_if = io_deq_bits_fflags_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_xcpt_ae_if = io_deq_bits_fflags_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_xcpt_ma_if = io_deq_bits_fflags_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_bp_debug_if = io_deq_bits_fflags_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_bp_xcpt_if = io_deq_bits_fflags_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_fsrc = io_deq_bits_fflags_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_uop_debug_tsrc = io_deq_bits_fflags_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_fflags_bits_flags = io_deq_bits_fflags_bits_flags_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_61 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in wire initval : { state : UInt<2>} connect initval.state, UInt<1>(0h0) wire _cam_s_WIRE : { state : UInt<2>}[1] connect _cam_s_WIRE[0], initval regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) node _a_canLogical_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canLogical_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canLogical_T_2 = cvt(_a_canLogical_T_1) node _a_canLogical_T_3 = and(_a_canLogical_T_2, asSInt(UInt<1>(0h0))) node _a_canLogical_T_4 = asSInt(_a_canLogical_T_3) node _a_canLogical_T_5 = eq(_a_canLogical_T_4, asSInt(UInt<1>(0h0))) node _a_canLogical_T_6 = and(_a_canLogical_T, _a_canLogical_T_5) node _a_canLogical_T_7 = or(UInt<1>(0h0), _a_canLogical_T_6) node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_7) node _a_canArithmetic_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canArithmetic_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canArithmetic_T_2 = cvt(_a_canArithmetic_T_1) node _a_canArithmetic_T_3 = and(_a_canArithmetic_T_2, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_4 = asSInt(_a_canArithmetic_T_3) node _a_canArithmetic_T_5 = eq(_a_canArithmetic_T_4, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_6 = and(_a_canArithmetic_T, _a_canArithmetic_T_5) node _a_canArithmetic_T_7 = or(UInt<1>(0h0), _a_canArithmetic_T_6) node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_7) node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_fifoId_T_1 = cvt(_a_fifoId_T) node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) node _indexes_T = bits(cam_a[0].bits.data, 0, 0) node _indexes_T_1 = bits(cam_d[0].data, 0, 0) node indexes_0 = cat(_indexes_T, _indexes_T_1) node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) node _indexes_T_3 = bits(cam_d[0].data, 1, 1) node indexes_1 = cat(_indexes_T_2, _indexes_T_3) node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) node _indexes_T_5 = bits(cam_d[0].data, 2, 2) node indexes_2 = cat(_indexes_T_4, _indexes_T_5) node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) node _indexes_T_7 = bits(cam_d[0].data, 3, 3) node indexes_3 = cat(_indexes_T_6, _indexes_T_7) node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) node _indexes_T_9 = bits(cam_d[0].data, 4, 4) node indexes_4 = cat(_indexes_T_8, _indexes_T_9) node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) node _indexes_T_11 = bits(cam_d[0].data, 5, 5) node indexes_5 = cat(_indexes_T_10, _indexes_T_11) node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) node _indexes_T_13 = bits(cam_d[0].data, 6, 6) node indexes_6 = cat(_indexes_T_12, _indexes_T_13) node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) node _indexes_T_15 = bits(cam_d[0].data, 7, 7) node indexes_7 = cat(_indexes_T_14, _indexes_T_15) node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) node _indexes_T_17 = bits(cam_d[0].data, 8, 8) node indexes_8 = cat(_indexes_T_16, _indexes_T_17) node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) node _indexes_T_19 = bits(cam_d[0].data, 9, 9) node indexes_9 = cat(_indexes_T_18, _indexes_T_19) node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) node _indexes_T_21 = bits(cam_d[0].data, 10, 10) node indexes_10 = cat(_indexes_T_20, _indexes_T_21) node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) node _indexes_T_23 = bits(cam_d[0].data, 11, 11) node indexes_11 = cat(_indexes_T_22, _indexes_T_23) node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) node _indexes_T_25 = bits(cam_d[0].data, 12, 12) node indexes_12 = cat(_indexes_T_24, _indexes_T_25) node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) node _indexes_T_27 = bits(cam_d[0].data, 13, 13) node indexes_13 = cat(_indexes_T_26, _indexes_T_27) node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) node _indexes_T_29 = bits(cam_d[0].data, 14, 14) node indexes_14 = cat(_indexes_T_28, _indexes_T_29) node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) node _indexes_T_31 = bits(cam_d[0].data, 15, 15) node indexes_15 = cat(_indexes_T_30, _indexes_T_31) node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) node _indexes_T_33 = bits(cam_d[0].data, 16, 16) node indexes_16 = cat(_indexes_T_32, _indexes_T_33) node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) node _indexes_T_35 = bits(cam_d[0].data, 17, 17) node indexes_17 = cat(_indexes_T_34, _indexes_T_35) node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) node _indexes_T_37 = bits(cam_d[0].data, 18, 18) node indexes_18 = cat(_indexes_T_36, _indexes_T_37) node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) node _indexes_T_39 = bits(cam_d[0].data, 19, 19) node indexes_19 = cat(_indexes_T_38, _indexes_T_39) node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) node _indexes_T_41 = bits(cam_d[0].data, 20, 20) node indexes_20 = cat(_indexes_T_40, _indexes_T_41) node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) node _indexes_T_43 = bits(cam_d[0].data, 21, 21) node indexes_21 = cat(_indexes_T_42, _indexes_T_43) node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) node _indexes_T_45 = bits(cam_d[0].data, 22, 22) node indexes_22 = cat(_indexes_T_44, _indexes_T_45) node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) node _indexes_T_47 = bits(cam_d[0].data, 23, 23) node indexes_23 = cat(_indexes_T_46, _indexes_T_47) node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) node _indexes_T_49 = bits(cam_d[0].data, 24, 24) node indexes_24 = cat(_indexes_T_48, _indexes_T_49) node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) node _indexes_T_51 = bits(cam_d[0].data, 25, 25) node indexes_25 = cat(_indexes_T_50, _indexes_T_51) node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) node _indexes_T_53 = bits(cam_d[0].data, 26, 26) node indexes_26 = cat(_indexes_T_52, _indexes_T_53) node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) node _indexes_T_55 = bits(cam_d[0].data, 27, 27) node indexes_27 = cat(_indexes_T_54, _indexes_T_55) node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) node _indexes_T_57 = bits(cam_d[0].data, 28, 28) node indexes_28 = cat(_indexes_T_56, _indexes_T_57) node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) node _indexes_T_59 = bits(cam_d[0].data, 29, 29) node indexes_29 = cat(_indexes_T_58, _indexes_T_59) node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) node _indexes_T_61 = bits(cam_d[0].data, 30, 30) node indexes_30 = cat(_indexes_T_60, _indexes_T_61) node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) node _indexes_T_63 = bits(cam_d[0].data, 31, 31) node indexes_31 = cat(_indexes_T_62, _indexes_T_63) node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) node _indexes_T_65 = bits(cam_d[0].data, 32, 32) node indexes_32 = cat(_indexes_T_64, _indexes_T_65) node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) node _indexes_T_67 = bits(cam_d[0].data, 33, 33) node indexes_33 = cat(_indexes_T_66, _indexes_T_67) node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) node _indexes_T_69 = bits(cam_d[0].data, 34, 34) node indexes_34 = cat(_indexes_T_68, _indexes_T_69) node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) node _indexes_T_71 = bits(cam_d[0].data, 35, 35) node indexes_35 = cat(_indexes_T_70, _indexes_T_71) node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) node _indexes_T_73 = bits(cam_d[0].data, 36, 36) node indexes_36 = cat(_indexes_T_72, _indexes_T_73) node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) node _indexes_T_75 = bits(cam_d[0].data, 37, 37) node indexes_37 = cat(_indexes_T_74, _indexes_T_75) node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) node _indexes_T_77 = bits(cam_d[0].data, 38, 38) node indexes_38 = cat(_indexes_T_76, _indexes_T_77) node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) node _indexes_T_79 = bits(cam_d[0].data, 39, 39) node indexes_39 = cat(_indexes_T_78, _indexes_T_79) node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) node _indexes_T_81 = bits(cam_d[0].data, 40, 40) node indexes_40 = cat(_indexes_T_80, _indexes_T_81) node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) node _indexes_T_83 = bits(cam_d[0].data, 41, 41) node indexes_41 = cat(_indexes_T_82, _indexes_T_83) node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) node _indexes_T_85 = bits(cam_d[0].data, 42, 42) node indexes_42 = cat(_indexes_T_84, _indexes_T_85) node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) node _indexes_T_87 = bits(cam_d[0].data, 43, 43) node indexes_43 = cat(_indexes_T_86, _indexes_T_87) node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) node _indexes_T_89 = bits(cam_d[0].data, 44, 44) node indexes_44 = cat(_indexes_T_88, _indexes_T_89) node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) node _indexes_T_91 = bits(cam_d[0].data, 45, 45) node indexes_45 = cat(_indexes_T_90, _indexes_T_91) node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) node _indexes_T_93 = bits(cam_d[0].data, 46, 46) node indexes_46 = cat(_indexes_T_92, _indexes_T_93) node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) node _indexes_T_95 = bits(cam_d[0].data, 47, 47) node indexes_47 = cat(_indexes_T_94, _indexes_T_95) node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) node _indexes_T_97 = bits(cam_d[0].data, 48, 48) node indexes_48 = cat(_indexes_T_96, _indexes_T_97) node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) node _indexes_T_99 = bits(cam_d[0].data, 49, 49) node indexes_49 = cat(_indexes_T_98, _indexes_T_99) node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) node _indexes_T_101 = bits(cam_d[0].data, 50, 50) node indexes_50 = cat(_indexes_T_100, _indexes_T_101) node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) node _indexes_T_103 = bits(cam_d[0].data, 51, 51) node indexes_51 = cat(_indexes_T_102, _indexes_T_103) node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) node _indexes_T_105 = bits(cam_d[0].data, 52, 52) node indexes_52 = cat(_indexes_T_104, _indexes_T_105) node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) node _indexes_T_107 = bits(cam_d[0].data, 53, 53) node indexes_53 = cat(_indexes_T_106, _indexes_T_107) node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) node _indexes_T_109 = bits(cam_d[0].data, 54, 54) node indexes_54 = cat(_indexes_T_108, _indexes_T_109) node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) node _indexes_T_111 = bits(cam_d[0].data, 55, 55) node indexes_55 = cat(_indexes_T_110, _indexes_T_111) node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) node _indexes_T_113 = bits(cam_d[0].data, 56, 56) node indexes_56 = cat(_indexes_T_112, _indexes_T_113) node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) node _indexes_T_115 = bits(cam_d[0].data, 57, 57) node indexes_57 = cat(_indexes_T_114, _indexes_T_115) node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) node _indexes_T_117 = bits(cam_d[0].data, 58, 58) node indexes_58 = cat(_indexes_T_116, _indexes_T_117) node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) node _indexes_T_119 = bits(cam_d[0].data, 59, 59) node indexes_59 = cat(_indexes_T_118, _indexes_T_119) node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) node _indexes_T_121 = bits(cam_d[0].data, 60, 60) node indexes_60 = cat(_indexes_T_120, _indexes_T_121) node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) node _indexes_T_123 = bits(cam_d[0].data, 61, 61) node indexes_61 = cat(_indexes_T_122, _indexes_T_123) node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) node _indexes_T_125 = bits(cam_d[0].data, 62, 62) node indexes_62 = cat(_indexes_T_124, _indexes_T_125) node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) node _indexes_T_127 = bits(cam_d[0].data, 63, 63) node indexes_63 = cat(_indexes_T_126, _indexes_T_127) node _logic_out_T = dshr(cam_a[0].lut, indexes_0) node _logic_out_T_1 = bits(_logic_out_T, 0, 0) node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) node logic_out = cat(logic_out_hi, logic_out_lo) node unsigned = bits(cam_a[0].bits.param, 1, 1) node take_max = bits(cam_a[0].bits.param, 0, 0) node adder = bits(cam_a[0].bits.param, 2, 2) node _signSel_T = not(cam_a[0].bits.mask) node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) node _signSel_T_2 = or(_signSel_T, _signSel_T_1) node signSel = not(_signSel_T_2) node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) node signbits_a = cat(signbits_a_hi, signbits_a_lo) node _signbits_d_T = bits(cam_d[0].data, 7, 7) node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) node signbits_d = cat(signbits_d_hi, signbits_d_lo) node _signbit_a_T = and(signbits_a, signSel) node _signbit_a_T_1 = shl(_signbit_a_T, 1) node signbit_a = bits(_signbit_a_T_1, 7, 0) node _signbit_d_T = and(signbits_d, signSel) node _signbit_d_T_1 = shl(_signbit_d_T, 1) node signbit_d = bits(_signbit_d_T_1, 7, 0) node _signext_a_T = shl(signbit_a, 1) node _signext_a_T_1 = bits(_signext_a_T, 7, 0) node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) node _signext_a_T_3 = shl(_signext_a_T_2, 2) node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) node _signext_a_T_6 = shl(_signext_a_T_5, 4) node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) node signext_a = cat(signext_a_hi, signext_a_lo) node _signext_d_T = shl(signbit_d, 1) node _signext_d_T_1 = bits(_signext_d_T, 7, 0) node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) node _signext_d_T_3 = shl(_signext_d_T_2, 2) node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) node _signext_d_T_6 = shl(_signext_d_T_5, 4) node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) node signext_d = cat(signext_d_hi, signext_d_lo) node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) node wide_mask = cat(wide_mask_hi, wide_mask_lo) node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) node a_a_ext = or(_a_a_ext_T, signext_a) node _a_d_ext_T = and(cam_d[0].data, wide_mask) node a_d_ext = or(_a_d_ext_T, signext_d) node _a_d_inv_T = not(a_d_ext) node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) node _adder_out_T = add(a_a_ext, a_d_inv) node adder_out = tail(_adder_out_T, 1) node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) node _a_bigger_T = bits(a_a_ext, 63, 63) node _a_bigger_T_1 = bits(a_d_ext, 63, 63) node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) node _a_bigger_T_3 = bits(adder_out, 63, 63) node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) node pick_a = eq(take_max, a_bigger) node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) node arith_out = mux(adder, adder_out, _arith_out_T) node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) node amo_data = mux(_amo_data_T, logic_out, arith_out) wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) node _a_allow_T_1 = or(a_isSupported, cam_free_0) node a_allow = and(_a_allow_T, _a_allow_T_1) node _nodeIn_a_ready_T = and(source_i.ready, a_allow) connect nodeIn.a.ready, _nodeIn_a_ready_T node _source_i_valid_T = and(nodeIn.a.valid, a_allow) connect source_i.valid, _source_i_valid_T connect source_i.bits, nodeIn.a.bits node _T = eq(a_isSupported, UInt<1>(0h0)) when _T : connect source_i.bits.opcode, UInt<3>(0h4) connect source_i.bits.param, UInt<1>(0h0) wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect source_c.valid, cam_amo_0 node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<2>(0h3)) node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<1>(0h0)) node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) node source_c_bits_legal = or(UInt<1>(0h0), _source_c_bits_legal_T_9) wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect source_c_bits_a.opcode, UInt<1>(0h0) connect source_c_bits_a.param, UInt<1>(0h0) connect source_c_bits_a.size, cam_a[0].bits.size connect source_c_bits_a.source, cam_a[0].bits.source connect source_c_bits_a.address, cam_a[0].bits.address node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) connect source_c_bits_a.mask, _source_c_bits_a_mask_T connect source_c_bits_a.data, amo_data connect source_c_bits_a.corrupt, _source_c_bits_T connect source_c.bits, source_c_bits_a node _decode_T = dshl(UInt<3>(0h7), nodeIn.a.bits.size) node _decode_T_1 = bits(_decode_T, 2, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_1 = mux(opdata, decode, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, nodeOut.a.ready) node _readys_T = cat(source_i.valid, source_c.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 1, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = bits(_readys_T_3, 1, 0) node _readys_T_5 = shl(_readys_T_4, 1) node _readys_T_6 = bits(_readys_T_5, 1, 0) node _readys_T_7 = not(_readys_T_6) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], source_c.valid) node _winner_T_1 = and(readys[1], source_i.valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_3 = eq(winner[0], UInt<1>(0h0)) node _T_4 = or(_T_2, _T_3) node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) node _T_6 = eq(winner[1], UInt<1>(0h0)) node _T_7 = or(_T_5, _T_6) node _T_8 = and(_T_4, _T_7) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_8, UInt<1>(0h1), "") : assert node _T_12 = or(source_c.valid, source_i.valid) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = or(winner[0], winner[1]) node _T_15 = or(_T_13, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) connect source_c.ready, _source_c_ready_T node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) connect source_i.ready, _source_i_ready_T node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) wire _nodeOut_a_valid_WIRE : UInt<1> connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) connect nodeOut.a.valid, _nodeOut_a_valid_T_4 wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) wire _nodeOut_a_bits_WIRE_1 : UInt<1> connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) wire _nodeOut_a_bits_WIRE_2 : UInt<64> connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) wire _nodeOut_a_bits_WIRE_3 : UInt<8> connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 wire _nodeOut_a_bits_WIRE_4 : { } connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 wire _nodeOut_a_bits_WIRE_5 : { } connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) wire _nodeOut_a_bits_WIRE_6 : UInt<29> connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11 connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6 node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) wire _nodeOut_a_bits_WIRE_7 : UInt<12> connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14 connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7 node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) wire _nodeOut_a_bits_WIRE_8 : UInt<2> connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17 connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8 node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) wire _nodeOut_a_bits_WIRE_9 : UInt<3> connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20 connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9 node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) wire _nodeOut_a_bits_WIRE_10 : UInt<3> connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23 connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10 connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode node _T_19 = and(source_i.ready, source_i.valid) node _T_20 = eq(a_isSupported, UInt<1>(0h0)) node _T_21 = and(_T_19, _T_20) when _T_21 : when a_cam_sel_free_0 : connect cam_a[0].fifoId, UInt<1>(0h0) connect cam_a[0].bits, nodeIn.a.bits node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) connect cam_a[0].lut, _cam_a_0_lut_T_6 when a_cam_sel_free_0 : connect cam_s[0].state, UInt<2>(0h3) node _T_22 = and(source_c.ready, source_c.valid) when _T_22 : when a_cam_sel_put_0 : connect cam_s[0].state, UInt<1>(0h1) node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), nodeOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) node _d_cam_sel_bypass_T = eq(nodeOut.d.bits.source, nodeIn.a.bits.source) node _d_cam_sel_bypass_T_1 = and(_d_cam_sel_bypass_T, nodeIn.a.valid) node _d_cam_sel_bypass_T_2 = eq(a_isSupported, UInt<1>(0h0)) node d_cam_sel_bypass = and(_d_cam_sel_bypass_T_1, _d_cam_sel_bypass_T_2) node d_cam_sel_0 = mux(d_cam_sel_bypass, a_cam_sel_free_0, d_cam_sel_match_0) node d_cam_sel_any = or(d_cam_sel_bypass, d_cam_sel_match_0) node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) node _T_24 = and(_T_23, d_first) when _T_24 : node _T_25 = and(d_cam_sel_0, d_ackd) when _T_25 : connect cam_d[0].data, nodeOut.d.bits.data connect cam_d[0].denied, nodeOut.d.bits.denied connect cam_d[0].corrupt, nodeOut.d.bits.corrupt when d_cam_sel_0 : node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) connect cam_s[0].state, _cam_s_0_state_T node _d_drop_T = and(d_first, d_ackd) node d_drop = and(_d_drop_T, d_cam_sel_any) node _d_replace_T = and(d_first, d_ack) node d_replace = and(_d_replace_T, d_cam_sel_match_0) node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) connect nodeIn.d.valid, _nodeIn_d_valid_T_1 node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) connect nodeOut.d.ready, _nodeOut_d_ready_T connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn.d.bits.data, nodeOut.d.bits.data connect nodeIn.d.bits.denied, nodeOut.d.bits.denied connect nodeIn.d.bits.sink, nodeOut.d.bits.sink connect nodeIn.d.bits.source, nodeOut.d.bits.source connect nodeIn.d.bits.size, nodeOut.d.bits.size connect nodeIn.d.bits.param, nodeOut.d.bits.param connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode when d_replace : connect nodeIn.d.bits.opcode, UInt<1>(0h1) connect nodeIn.d.bits.data, cam_d[0].data node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLAtomicAutomata( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_sink = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_denied = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_corrupt = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_sink = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_denied = 1'h0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_corrupt = 1'h0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _a_canLogical_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canLogical_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canLogical_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canLogical = 1'h0; // @[AtomicAutomata.scala:94:45] wire _a_canArithmetic_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canArithmetic_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canArithmetic_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canArithmetic = 1'h0; // @[AtomicAutomata.scala:95:45] wire decode = 1'h0; // @[Edges.scala:220:59] wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1 = 1'h0; // @[Arbiter.scala:82:69] wire initBeats = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire _nodeIn_d_bits_corrupt_T = 1'h0; // @[AtomicAutomata.scala:248:46] wire _nodeIn_d_bits_denied_T = 1'h0; // @[AtomicAutomata.scala:249:46] wire _a_canLogical_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_canArithmetic_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83] wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60] wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85] wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _source_c_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _source_c_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _source_c_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _source_c_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _source_c_bits_legal_T_9 = 1'h1; // @[Parameters.scala:684:54] wire source_c_bits_legal = 1'h1; // @[Parameters.scala:686:26] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire [1:0] auto_in_d_bits_param = 2'h0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_param = 2'h0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27] wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50] wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [29:0] _a_canLogical_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canLogical_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_6 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_7 = 30'h0; // @[Parameters.scala:137:46] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [11:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9] wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9] wire [1:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28] wire [11:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28] wire [28:0] _a_canLogical_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28] wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28] wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28] wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [1:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [11:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [1:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] wire [1:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17] reg [11:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] wire [11:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] _source_c_bits_legal_T_4 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_T = cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24, :172:45] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44] wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58] wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82] wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire cam_amo_0; // @[AtomicAutomata.scala:87:44] assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44] wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68] assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68] wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56] wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80] wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28] wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49] wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}] wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96] wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49] wire [29:0] _a_canLogical_T_2 = {1'h0, _a_canLogical_T_1}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_2 = {1'h0, _a_canArithmetic_T_1}; // @[Parameters.scala:137:{31,41}] wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47] wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47] wire _a_isSupported_T = ~a_isArithmetic; // @[AtomicAutomata.scala:97:47, :98:63] wire a_isSupported = ~a_isLogical & _a_isSupported_T; // @[AtomicAutomata.scala:96:47, :98:{32,63}] wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}] wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}] wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57] wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28] wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42] wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42] wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39] wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25] wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39] wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}] wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}] wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29] wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29] wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38] wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}] wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}] wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38] wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}] wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}] wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17] wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17] wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17] wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17] wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17] wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17] wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17] wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17] wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40] wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40] wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17] wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17] wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17] wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17] wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17] wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17] wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17] wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17] wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40] wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40] wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40] wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28] wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}] wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28] wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}] wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43] wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}] wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33] wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33] wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49] wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35] wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}] wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50] wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}] wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65] wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}] wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}] wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31] wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50] wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}] wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34] wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}] wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17] wire _source_i_ready_T; // @[Arbiter.scala:94:31] wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38] wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28] wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28] wire source_i_ready; // @[AtomicAutomata.scala:154:28] wire source_i_valid; // @[AtomicAutomata.scala:154:28] wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23] wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53] wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}] assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38] assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32] assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32] wire _source_c_ready_T; // @[Arbiter.scala:94:31] wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17] wire source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28] wire [11:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28] wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28] wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28] wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28] wire source_c_ready; // @[AtomicAutomata.scala:165:28] assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17] wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17] assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17] assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10] assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17] assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17] assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [2:0] _source_c_bits_a_mask_sizeOH_T = {1'h0, cam_a_0_bits_size}; // @[Misc.scala:202:34] wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire source_c_bits_a_mask_sub_sub_sub_0_1 = &cam_a_0_bits_size; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10] assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10] wire [5:0] _decode_T = 6'h7 << nodeIn_a_bits_size; // @[package.scala:243:71] wire [2:0] _decode_T_1 = _decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}] reg beatsLeft; // @[Arbiter.scala:60:30] wire idle = ~beatsLeft; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28]